1 /* Target-dependent code for SPARC.
3 Copyright (C) 2003-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "arch-utils.h"
23 #include "dwarf2-frame.h"
24 #include "floatformat.h"
26 #include "frame-base.h"
27 #include "frame-unwind.h"
38 #include "gdb_assert.h"
39 #include "gdb_string.h"
41 #include "sparc-tdep.h"
45 /* This file implements the SPARC 32-bit ABI as defined by the section
46 "Low-Level System Information" of the SPARC Compliance Definition
47 (SCD) 2.4.1, which is the 32-bit System V psABI for SPARC. The SCD
48 lists changes with respect to the original 32-bit psABI as defined
49 in the "System V ABI, SPARC Processor Supplement".
51 Note that if we talk about SunOS, we mean SunOS 4.x, which was
52 BSD-based, which is sometimes (retroactively?) referred to as
53 Solaris 1.x. If we talk about Solaris we mean Solaris 2.x and
54 above (Solaris 7, 8 and 9 are nothing but Solaris 2.7, 2.8 and 2.9
55 suffering from severe version number inflation). Solaris 2.x is
56 also known as SunOS 5.x, since that's what uname(1) says. Solaris
59 /* Please use the sparc32_-prefix for 32-bit specific code, the
60 sparc64_-prefix for 64-bit specific code and the sparc_-prefix for
61 code that can handle both. The 64-bit specific code lives in
62 sparc64-tdep.c; don't add any here. */
64 /* The SPARC Floating-Point Quad-Precision format is similar to
65 big-endian IA-64 Quad-Precision format. */
66 #define floatformats_sparc_quad floatformats_ia64_quad
68 /* The stack pointer is offset from the stack frame by a BIAS of 2047
69 (0x7ff) for 64-bit code. BIAS is likely to be defined on SPARC
70 hosts, so undefine it first. */
74 /* Macros to extract fields from SPARC instructions. */
75 #define X_OP(i) (((i) >> 30) & 0x3)
76 #define X_RD(i) (((i) >> 25) & 0x1f)
77 #define X_A(i) (((i) >> 29) & 1)
78 #define X_COND(i) (((i) >> 25) & 0xf)
79 #define X_OP2(i) (((i) >> 22) & 0x7)
80 #define X_IMM22(i) ((i) & 0x3fffff)
81 #define X_OP3(i) (((i) >> 19) & 0x3f)
82 #define X_RS1(i) (((i) >> 14) & 0x1f)
83 #define X_RS2(i) ((i) & 0x1f)
84 #define X_I(i) (((i) >> 13) & 1)
85 /* Sign extension macros. */
86 #define X_DISP22(i) ((X_IMM22 (i) ^ 0x200000) - 0x200000)
87 #define X_DISP19(i) ((((i) & 0x7ffff) ^ 0x40000) - 0x40000)
88 #define X_DISP10(i) ((((((i) >> 11) && 0x300) | (((i) >> 5) & 0xff)) ^ 0x200) - 0x200)
89 #define X_SIMM13(i) ((((i) & 0x1fff) ^ 0x1000) - 0x1000)
91 /* Fetch the instruction at PC. Instructions are always big-endian
92 even if the processor operates in little-endian mode. */
95 sparc_fetch_instruction (CORE_ADDR pc)
101 /* If we can't read the instruction at PC, return zero. */
102 if (target_read_memory (pc, buf, sizeof (buf)))
106 for (i = 0; i < sizeof (buf); i++)
107 insn = (insn << 8) | buf[i];
112 /* Return non-zero if the instruction corresponding to PC is an "unimp"
116 sparc_is_unimp_insn (CORE_ADDR pc)
118 const unsigned long insn = sparc_fetch_instruction (pc);
120 return ((insn & 0xc1c00000) == 0);
123 /* OpenBSD/sparc includes StackGhost, which according to the author's
124 website http://stackghost.cerias.purdue.edu "... transparently and
125 automatically protects applications' stack frames; more
126 specifically, it guards the return pointers. The protection
127 mechanisms require no application source or binary modification and
128 imposes only a negligible performance penalty."
130 The same website provides the following description of how
133 "StackGhost interfaces with the kernel trap handler that would
134 normally write out registers to the stack and the handler that
135 would read them back in. By XORing a cookie into the
136 return-address saved in the user stack when it is actually written
137 to the stack, and then XOR it out when the return-address is pulled
138 from the stack, StackGhost can cause attacker corrupted return
139 pointers to behave in a manner the attacker cannot predict.
140 StackGhost can also use several unused bits in the return pointer
141 to detect a smashed return pointer and abort the process."
143 For GDB this means that whenever we're reading %i7 from a stack
144 frame's window save area, we'll have to XOR the cookie.
146 More information on StackGuard can be found on in:
148 Mike Frantzen and Mike Shuey. "StackGhost: Hardware Facilitated
149 Stack Protection." 2001. Published in USENIX Security Symposium
152 /* Fetch StackGhost Per-Process XOR cookie. */
155 sparc_fetch_wcookie (struct gdbarch *gdbarch)
157 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
158 struct target_ops *ops = ¤t_target;
162 len = target_read (ops, TARGET_OBJECT_WCOOKIE, NULL, buf, 0, 8);
166 /* We should have either an 32-bit or an 64-bit cookie. */
167 gdb_assert (len == 4 || len == 8);
169 return extract_unsigned_integer (buf, len, byte_order);
173 /* The functions on this page are intended to be used to classify
174 function arguments. */
176 /* Check whether TYPE is "Integral or Pointer". */
179 sparc_integral_or_pointer_p (const struct type *type)
181 int len = TYPE_LENGTH (type);
183 switch (TYPE_CODE (type))
189 case TYPE_CODE_RANGE:
190 /* We have byte, half-word, word and extended-word/doubleword
191 integral types. The doubleword is an extension to the
192 original 32-bit ABI by the SCD 2.4.x. */
193 return (len == 1 || len == 2 || len == 4 || len == 8);
196 /* Allow either 32-bit or 64-bit pointers. */
197 return (len == 4 || len == 8);
205 /* Check whether TYPE is "Floating". */
208 sparc_floating_p (const struct type *type)
210 switch (TYPE_CODE (type))
214 int len = TYPE_LENGTH (type);
215 return (len == 4 || len == 8 || len == 16);
224 /* Check whether TYPE is "Complex Floating". */
227 sparc_complex_floating_p (const struct type *type)
229 switch (TYPE_CODE (type))
231 case TYPE_CODE_COMPLEX:
233 int len = TYPE_LENGTH (type);
234 return (len == 8 || len == 16 || len == 32);
243 /* Check whether TYPE is "Structure or Union".
245 In terms of Ada subprogram calls, arrays are treated the same as
246 struct and union types. So this function also returns non-zero
250 sparc_structure_or_union_p (const struct type *type)
252 switch (TYPE_CODE (type))
254 case TYPE_CODE_STRUCT:
255 case TYPE_CODE_UNION:
256 case TYPE_CODE_ARRAY:
265 /* Register information. */
267 static const char *sparc32_register_names[] =
269 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
270 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
271 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
272 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
274 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
275 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
276 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
277 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
279 "y", "psr", "wim", "tbr", "pc", "npc", "fsr", "csr"
282 /* Total number of registers. */
283 #define SPARC32_NUM_REGS ARRAY_SIZE (sparc32_register_names)
285 /* We provide the aliases %d0..%d30 for the floating registers as
286 "psuedo" registers. */
288 static const char *sparc32_pseudo_register_names[] =
290 "d0", "d2", "d4", "d6", "d8", "d10", "d12", "d14",
291 "d16", "d18", "d20", "d22", "d24", "d26", "d28", "d30"
294 /* Total number of pseudo registers. */
295 #define SPARC32_NUM_PSEUDO_REGS ARRAY_SIZE (sparc32_pseudo_register_names)
297 /* Return the name of register REGNUM. */
300 sparc32_register_name (struct gdbarch *gdbarch, int regnum)
302 if (regnum >= 0 && regnum < SPARC32_NUM_REGS)
303 return sparc32_register_names[regnum];
305 if (regnum < SPARC32_NUM_REGS + SPARC32_NUM_PSEUDO_REGS)
306 return sparc32_pseudo_register_names[regnum - SPARC32_NUM_REGS];
311 /* Construct types for ISA-specific registers. */
314 sparc_psr_type (struct gdbarch *gdbarch)
316 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
318 if (!tdep->sparc_psr_type)
322 type = arch_flags_type (gdbarch, "builtin_type_sparc_psr", 4);
323 append_flags_type_flag (type, 5, "ET");
324 append_flags_type_flag (type, 6, "PS");
325 append_flags_type_flag (type, 7, "S");
326 append_flags_type_flag (type, 12, "EF");
327 append_flags_type_flag (type, 13, "EC");
329 tdep->sparc_psr_type = type;
332 return tdep->sparc_psr_type;
336 sparc_fsr_type (struct gdbarch *gdbarch)
338 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
340 if (!tdep->sparc_fsr_type)
344 type = arch_flags_type (gdbarch, "builtin_type_sparc_fsr", 4);
345 append_flags_type_flag (type, 0, "NXA");
346 append_flags_type_flag (type, 1, "DZA");
347 append_flags_type_flag (type, 2, "UFA");
348 append_flags_type_flag (type, 3, "OFA");
349 append_flags_type_flag (type, 4, "NVA");
350 append_flags_type_flag (type, 5, "NXC");
351 append_flags_type_flag (type, 6, "DZC");
352 append_flags_type_flag (type, 7, "UFC");
353 append_flags_type_flag (type, 8, "OFC");
354 append_flags_type_flag (type, 9, "NVC");
355 append_flags_type_flag (type, 22, "NS");
356 append_flags_type_flag (type, 23, "NXM");
357 append_flags_type_flag (type, 24, "DZM");
358 append_flags_type_flag (type, 25, "UFM");
359 append_flags_type_flag (type, 26, "OFM");
360 append_flags_type_flag (type, 27, "NVM");
362 tdep->sparc_fsr_type = type;
365 return tdep->sparc_fsr_type;
368 /* Return the GDB type object for the "standard" data type of data in
372 sparc32_register_type (struct gdbarch *gdbarch, int regnum)
374 if (regnum >= SPARC_F0_REGNUM && regnum <= SPARC_F31_REGNUM)
375 return builtin_type (gdbarch)->builtin_float;
377 if (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM)
378 return builtin_type (gdbarch)->builtin_double;
380 if (regnum == SPARC_SP_REGNUM || regnum == SPARC_FP_REGNUM)
381 return builtin_type (gdbarch)->builtin_data_ptr;
383 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
384 return builtin_type (gdbarch)->builtin_func_ptr;
386 if (regnum == SPARC32_PSR_REGNUM)
387 return sparc_psr_type (gdbarch);
389 if (regnum == SPARC32_FSR_REGNUM)
390 return sparc_fsr_type (gdbarch);
392 return builtin_type (gdbarch)->builtin_int32;
395 static enum register_status
396 sparc32_pseudo_register_read (struct gdbarch *gdbarch,
397 struct regcache *regcache,
398 int regnum, gdb_byte *buf)
400 enum register_status status;
402 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
404 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
405 status = regcache_raw_read (regcache, regnum, buf);
406 if (status == REG_VALID)
407 status = regcache_raw_read (regcache, regnum + 1, buf + 4);
412 sparc32_pseudo_register_write (struct gdbarch *gdbarch,
413 struct regcache *regcache,
414 int regnum, const gdb_byte *buf)
416 gdb_assert (regnum >= SPARC32_D0_REGNUM && regnum <= SPARC32_D30_REGNUM);
418 regnum = SPARC_F0_REGNUM + 2 * (regnum - SPARC32_D0_REGNUM);
419 regcache_raw_write (regcache, regnum, buf);
420 regcache_raw_write (regcache, regnum + 1, buf + 4);
425 sparc32_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
427 /* The ABI requires double-word alignment. */
428 return address & ~0x7;
432 sparc32_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
434 struct value **args, int nargs,
435 struct type *value_type,
436 CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
437 struct regcache *regcache)
439 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
444 if (using_struct_return (gdbarch, NULL, value_type))
448 /* This is an UNIMP instruction. */
449 store_unsigned_integer (buf, 4, byte_order,
450 TYPE_LENGTH (value_type) & 0x1fff);
451 write_memory (sp - 8, buf, 4);
459 sparc32_store_arguments (struct regcache *regcache, int nargs,
460 struct value **args, CORE_ADDR sp,
461 int struct_return, CORE_ADDR struct_addr)
463 struct gdbarch *gdbarch = get_regcache_arch (regcache);
464 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
465 /* Number of words in the "parameter array". */
466 int num_elements = 0;
470 for (i = 0; i < nargs; i++)
472 struct type *type = value_type (args[i]);
473 int len = TYPE_LENGTH (type);
475 if (sparc_structure_or_union_p (type)
476 || (sparc_floating_p (type) && len == 16)
477 || sparc_complex_floating_p (type))
479 /* Structure, Union and Quad-Precision Arguments. */
482 /* Use doubleword alignment for these values. That's always
483 correct, and wasting a few bytes shouldn't be a problem. */
486 write_memory (sp, value_contents (args[i]), len);
487 args[i] = value_from_pointer (lookup_pointer_type (type), sp);
490 else if (sparc_floating_p (type))
492 /* Floating arguments. */
493 gdb_assert (len == 4 || len == 8);
494 num_elements += (len / 4);
498 /* Integral and pointer arguments. */
499 gdb_assert (sparc_integral_or_pointer_p (type));
502 args[i] = value_cast (builtin_type (gdbarch)->builtin_int32,
504 num_elements += ((len + 3) / 4);
508 /* Always allocate at least six words. */
509 sp -= max (6, num_elements) * 4;
511 /* The psABI says that "Software convention requires space for the
512 struct/union return value pointer, even if the word is unused." */
515 /* The psABI says that "Although software convention and the
516 operating system require every stack frame to be doubleword
520 for (i = 0; i < nargs; i++)
522 const bfd_byte *valbuf = value_contents (args[i]);
523 struct type *type = value_type (args[i]);
524 int len = TYPE_LENGTH (type);
526 gdb_assert (len == 4 || len == 8);
530 int regnum = SPARC_O0_REGNUM + element;
532 regcache_cooked_write (regcache, regnum, valbuf);
533 if (len > 4 && element < 5)
534 regcache_cooked_write (regcache, regnum + 1, valbuf + 4);
537 /* Always store the argument in memory. */
538 write_memory (sp + 4 + element * 4, valbuf, len);
542 gdb_assert (element == num_elements);
548 store_unsigned_integer (buf, 4, byte_order, struct_addr);
549 write_memory (sp, buf, 4);
556 sparc32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
557 struct regcache *regcache, CORE_ADDR bp_addr,
558 int nargs, struct value **args, CORE_ADDR sp,
559 int struct_return, CORE_ADDR struct_addr)
561 CORE_ADDR call_pc = (struct_return ? (bp_addr - 12) : (bp_addr - 8));
563 /* Set return address. */
564 regcache_cooked_write_unsigned (regcache, SPARC_O7_REGNUM, call_pc);
566 /* Set up function arguments. */
567 sp = sparc32_store_arguments (regcache, nargs, args, sp,
568 struct_return, struct_addr);
570 /* Allocate the 16-word window save area. */
573 /* Stack should be doubleword aligned at this point. */
574 gdb_assert (sp % 8 == 0);
576 /* Finally, update the stack pointer. */
577 regcache_cooked_write_unsigned (regcache, SPARC_SP_REGNUM, sp);
583 /* Use the program counter to determine the contents and size of a
584 breakpoint instruction. Return a pointer to a string of bytes that
585 encode a breakpoint instruction, store the length of the string in
586 *LEN and optionally adjust *PC to point to the correct memory
587 location for inserting the breakpoint. */
589 static const gdb_byte *
590 sparc_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pc, int *len)
592 static const gdb_byte break_insn[] = { 0x91, 0xd0, 0x20, 0x01 };
594 *len = sizeof (break_insn);
599 /* Allocate and initialize a frame cache. */
601 static struct sparc_frame_cache *
602 sparc_alloc_frame_cache (void)
604 struct sparc_frame_cache *cache;
607 cache = FRAME_OBSTACK_ZALLOC (struct sparc_frame_cache);
613 /* Frameless until proven otherwise. */
614 cache->frameless_p = 1;
615 cache->frame_offset = 0;
616 cache->saved_regs_mask = 0;
617 cache->copied_regs_mask = 0;
618 cache->struct_return_p = 0;
623 /* GCC generates several well-known sequences of instructions at the begining
624 of each function prologue when compiling with -fstack-check. If one of
625 such sequences starts at START_PC, then return the address of the
626 instruction immediately past this sequence. Otherwise, return START_PC. */
629 sparc_skip_stack_check (const CORE_ADDR start_pc)
631 CORE_ADDR pc = start_pc;
633 int offset_stack_checking_sequence = 0;
634 int probing_loop = 0;
636 /* With GCC, all stack checking sequences begin with the same two
637 instructions, plus an optional one in the case of a probing loop:
639 sethi <some immediate>, %g1
644 sethi <some immediate>, %g1
645 sethi <some immediate>, %g4
650 sethi <some immediate>, %g1
652 sethi <some immediate>, %g4
654 If the optional instruction is found (setting g4), assume that a
655 probing loop will follow. */
657 /* sethi <some immediate>, %g1 */
658 insn = sparc_fetch_instruction (pc);
660 if (!(X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 1))
663 /* optional: sethi <some immediate>, %g4 */
664 insn = sparc_fetch_instruction (pc);
666 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
669 insn = sparc_fetch_instruction (pc);
673 /* sub %sp, %g1, %g1 */
674 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
675 && X_RD (insn) == 1 && X_RS1 (insn) == 14 && X_RS2 (insn) == 1))
678 insn = sparc_fetch_instruction (pc);
681 /* optional: sethi <some immediate>, %g4 */
682 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x4 && X_RD (insn) == 4)
685 insn = sparc_fetch_instruction (pc);
689 /* First possible sequence:
690 [first two instructions above]
691 clr [%g1 - some immediate] */
693 /* clr [%g1 - some immediate] */
694 if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
695 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
697 /* Valid stack-check sequence, return the new PC. */
701 /* Second possible sequence: A small number of probes.
702 [first two instructions above]
704 add %g1, -<some immediate>, %g1
706 [repeat the two instructions above any (small) number of times]
707 clr [%g1 - some immediate] */
710 else if (X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
711 && X_RS1 (insn) == 1 && X_RD (insn) == 0)
715 /* add %g1, -<some immediate>, %g1 */
716 insn = sparc_fetch_instruction (pc);
718 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
719 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
723 insn = sparc_fetch_instruction (pc);
725 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && !X_I(insn)
726 && X_RD (insn) == 0 && X_RS1 (insn) == 1))
730 /* clr [%g1 - some immediate] */
731 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
732 && X_RS1 (insn) == 1 && X_RD (insn) == 0))
735 /* We found a valid stack-check sequence, return the new PC. */
739 /* Third sequence: A probing loop.
740 [first three instructions above]
744 add %g1, -<some immediate>, %g1
748 And an optional last probe for the remainder:
750 clr [%g4 - some immediate] */
754 /* sub %g1, %g4, %g4 */
755 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x4 && !X_I(insn)
756 && X_RD (insn) == 4 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
760 insn = sparc_fetch_instruction (pc);
762 if (!(X_OP (insn) == 2 && X_OP3 (insn) == 0x14 && !X_I(insn)
763 && X_RD (insn) == 0 && X_RS1 (insn) == 1 && X_RS2 (insn) == 4))
767 insn = sparc_fetch_instruction (pc);
769 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x1))
772 /* add %g1, -<some immediate>, %g1 */
773 insn = sparc_fetch_instruction (pc);
775 if (!(X_OP (insn) == 2 && X_OP3(insn) == 0 && X_I(insn)
776 && X_RS1 (insn) == 1 && X_RD (insn) == 1))
780 insn = sparc_fetch_instruction (pc);
782 if (!(X_OP (insn) == 0 && X_COND (insn) == 0x8))
785 /* clr [%g1] (st %g0, [%g1] or st %g0, [%g1+0]) */
786 insn = sparc_fetch_instruction (pc);
788 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4
789 && X_RD (insn) == 0 && X_RS1 (insn) == 1
790 && (!X_I(insn) || X_SIMM13 (insn) == 0)))
793 /* We found a valid stack-check sequence, return the new PC. */
795 /* optional: clr [%g4 - some immediate] */
796 insn = sparc_fetch_instruction (pc);
798 if (!(X_OP (insn) == 3 && X_OP3(insn) == 0x4 && X_I(insn)
799 && X_RS1 (insn) == 4 && X_RD (insn) == 0))
805 /* No stack check code in our prologue, return the start_pc. */
809 /* Record the effect of a SAVE instruction on CACHE. */
812 sparc_record_save_insn (struct sparc_frame_cache *cache)
814 /* The frame is set up. */
815 cache->frameless_p = 0;
817 /* The frame pointer contains the CFA. */
818 cache->frame_offset = 0;
820 /* The `local' and `in' registers are all saved. */
821 cache->saved_regs_mask = 0xffff;
823 /* The `out' registers are all renamed. */
824 cache->copied_regs_mask = 0xff;
827 /* Do a full analysis of the prologue at PC and update CACHE accordingly.
828 Bail out early if CURRENT_PC is reached. Return the address where
829 the analysis stopped.
831 We handle both the traditional register window model and the single
832 register window (aka flat) model. */
835 sparc_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR pc,
836 CORE_ADDR current_pc, struct sparc_frame_cache *cache)
838 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
843 pc = sparc_skip_stack_check (pc);
845 if (current_pc <= pc)
848 /* We have to handle to "Procedure Linkage Table" (PLT) special. On
849 SPARC the linker usually defines a symbol (typically
850 _PROCEDURE_LINKAGE_TABLE_) at the start of the .plt section.
851 This symbol makes us end up here with PC pointing at the start of
852 the PLT and CURRENT_PC probably pointing at a PLT entry. If we
853 would do our normal prologue analysis, we would probably conclude
854 that we've got a frame when in reality we don't, since the
855 dynamic linker patches up the first PLT with some code that
856 starts with a SAVE instruction. Patch up PC such that it points
857 at the start of our PLT entry. */
858 if (tdep->plt_entry_size > 0 && in_plt_section (current_pc, NULL))
859 pc = current_pc - ((current_pc - pc) % tdep->plt_entry_size);
861 insn = sparc_fetch_instruction (pc);
863 /* Recognize store insns and record their sources. */
864 while (X_OP (insn) == 3
865 && (X_OP3 (insn) == 0x4 /* stw */
866 || X_OP3 (insn) == 0x7 /* std */
867 || X_OP3 (insn) == 0xe) /* stx */
868 && X_RS1 (insn) == SPARC_SP_REGNUM)
870 int regnum = X_RD (insn);
872 /* Recognize stores into the corresponding stack slots. */
873 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
875 && X_SIMM13 (insn) == (X_OP3 (insn) == 0xe
876 ? (regnum - SPARC_L0_REGNUM) * 8 + BIAS
877 : (regnum - SPARC_L0_REGNUM) * 4))
878 || (!X_I (insn) && regnum == SPARC_L0_REGNUM)))
880 cache->saved_regs_mask |= (1 << (regnum - SPARC_L0_REGNUM));
881 if (X_OP3 (insn) == 0x7)
882 cache->saved_regs_mask |= (1 << (regnum + 1 - SPARC_L0_REGNUM));
887 insn = sparc_fetch_instruction (pc + offset);
890 /* Recognize a SETHI insn and record its destination. */
891 if (X_OP (insn) == 0 && X_OP2 (insn) == 0x04)
896 insn = sparc_fetch_instruction (pc + offset);
899 /* Allow for an arithmetic operation on DEST or %g1. */
900 if (X_OP (insn) == 2 && X_I (insn)
901 && (X_RD (insn) == 1 || X_RD (insn) == dest))
905 insn = sparc_fetch_instruction (pc + offset);
908 /* Check for the SAVE instruction that sets up the frame. */
909 if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3c)
911 sparc_record_save_insn (cache);
916 /* Check for an arithmetic operation on %sp. */
918 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
919 && X_RS1 (insn) == SPARC_SP_REGNUM
920 && X_RD (insn) == SPARC_SP_REGNUM)
924 cache->frame_offset = X_SIMM13 (insn);
925 if (X_OP3 (insn) == 0)
926 cache->frame_offset = -cache->frame_offset;
930 insn = sparc_fetch_instruction (pc + offset);
932 /* Check for an arithmetic operation that sets up the frame. */
934 && (X_OP3 (insn) == 0 || X_OP3 (insn) == 0x4)
935 && X_RS1 (insn) == SPARC_SP_REGNUM
936 && X_RD (insn) == SPARC_FP_REGNUM)
938 cache->frameless_p = 0;
939 cache->frame_offset = 0;
940 /* We could check that the amount subtracted to %sp above is the
941 same as the one added here, but this seems superfluous. */
942 cache->copied_regs_mask |= 0x40;
945 insn = sparc_fetch_instruction (pc + offset);
948 /* Check for a move (or) operation that copies the return register. */
950 && X_OP3 (insn) == 0x2
952 && X_RS1 (insn) == SPARC_G0_REGNUM
953 && X_RS2 (insn) == SPARC_O7_REGNUM
954 && X_RD (insn) == SPARC_I7_REGNUM)
956 cache->copied_regs_mask |= 0x80;
967 sparc_unwind_pc (struct gdbarch *gdbarch, struct frame_info *this_frame)
969 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
970 return frame_unwind_register_unsigned (this_frame, tdep->pc_regnum);
973 /* Return PC of first real instruction of the function starting at
977 sparc32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
979 struct symtab_and_line sal;
980 CORE_ADDR func_start, func_end;
981 struct sparc_frame_cache cache;
983 /* This is the preferred method, find the end of the prologue by
984 using the debugging information. */
985 if (find_pc_partial_function (start_pc, NULL, &func_start, &func_end))
987 sal = find_pc_line (func_start, 0);
989 if (sal.end < func_end
990 && start_pc <= sal.end)
994 start_pc = sparc_analyze_prologue (gdbarch, start_pc, 0xffffffffUL, &cache);
996 /* The psABI says that "Although the first 6 words of arguments
997 reside in registers, the standard stack frame reserves space for
998 them.". It also suggests that a function may use that space to
999 "write incoming arguments 0 to 5" into that space, and that's
1000 indeed what GCC seems to be doing. In that case GCC will
1001 generate debug information that points to the stack slots instead
1002 of the registers, so we should consider the instructions that
1003 write out these incoming arguments onto the stack. */
1007 unsigned long insn = sparc_fetch_instruction (start_pc);
1009 /* Recognize instructions that store incoming arguments into the
1010 corresponding stack slots. */
1011 if (X_OP (insn) == 3 && (X_OP3 (insn) & 0x3c) == 0x04
1012 && X_I (insn) && X_RS1 (insn) == SPARC_FP_REGNUM)
1014 int regnum = X_RD (insn);
1016 /* Case of arguments still in %o[0..5]. */
1017 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O5_REGNUM
1018 && !(cache.copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM)))
1019 && X_SIMM13 (insn) == 68 + (regnum - SPARC_O0_REGNUM) * 4)
1025 /* Case of arguments copied into %i[0..5]. */
1026 if (regnum >= SPARC_I0_REGNUM && regnum <= SPARC_I5_REGNUM
1027 && (cache.copied_regs_mask & (1 << (regnum - SPARC_I0_REGNUM)))
1028 && X_SIMM13 (insn) == 68 + (regnum - SPARC_I0_REGNUM) * 4)
1041 /* Normal frames. */
1043 struct sparc_frame_cache *
1044 sparc_frame_cache (struct frame_info *this_frame, void **this_cache)
1046 struct sparc_frame_cache *cache;
1051 cache = sparc_alloc_frame_cache ();
1052 *this_cache = cache;
1054 cache->pc = get_frame_func (this_frame);
1056 sparc_analyze_prologue (get_frame_arch (this_frame), cache->pc,
1057 get_frame_pc (this_frame), cache);
1059 if (cache->frameless_p)
1061 /* This function is frameless, so %fp (%i6) holds the frame
1062 pointer for our calling frame. Use %sp (%o6) as this frame's
1065 get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1069 /* For normal frames, %fp (%i6) holds the frame pointer, the
1070 base address for the current stack frame. */
1072 get_frame_register_unsigned (this_frame, SPARC_FP_REGNUM);
1075 cache->base += cache->frame_offset;
1077 if (cache->base & 1)
1078 cache->base += BIAS;
1084 sparc32_struct_return_from_sym (struct symbol *sym)
1086 struct type *type = check_typedef (SYMBOL_TYPE (sym));
1087 enum type_code code = TYPE_CODE (type);
1089 if (code == TYPE_CODE_FUNC || code == TYPE_CODE_METHOD)
1091 type = check_typedef (TYPE_TARGET_TYPE (type));
1092 if (sparc_structure_or_union_p (type)
1093 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1100 struct sparc_frame_cache *
1101 sparc32_frame_cache (struct frame_info *this_frame, void **this_cache)
1103 struct sparc_frame_cache *cache;
1109 cache = sparc_frame_cache (this_frame, this_cache);
1111 sym = find_pc_function (cache->pc);
1114 cache->struct_return_p = sparc32_struct_return_from_sym (sym);
1118 /* There is no debugging information for this function to
1119 help us determine whether this function returns a struct
1120 or not. So we rely on another heuristic which is to check
1121 the instruction at the return address and see if this is
1122 an "unimp" instruction. If it is, then it is a struct-return
1126 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1128 pc = get_frame_register_unsigned (this_frame, regnum) + 8;
1129 if (sparc_is_unimp_insn (pc))
1130 cache->struct_return_p = 1;
1137 sparc32_frame_this_id (struct frame_info *this_frame, void **this_cache,
1138 struct frame_id *this_id)
1140 struct sparc_frame_cache *cache =
1141 sparc32_frame_cache (this_frame, this_cache);
1143 /* This marks the outermost frame. */
1144 if (cache->base == 0)
1147 (*this_id) = frame_id_build (cache->base, cache->pc);
1150 static struct value *
1151 sparc32_frame_prev_register (struct frame_info *this_frame,
1152 void **this_cache, int regnum)
1154 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1155 struct sparc_frame_cache *cache =
1156 sparc32_frame_cache (this_frame, this_cache);
1158 if (regnum == SPARC32_PC_REGNUM || regnum == SPARC32_NPC_REGNUM)
1160 CORE_ADDR pc = (regnum == SPARC32_NPC_REGNUM) ? 4 : 0;
1162 /* If this functions has a Structure, Union or Quad-Precision
1163 return value, we have to skip the UNIMP instruction that encodes
1164 the size of the structure. */
1165 if (cache->struct_return_p)
1169 (cache->copied_regs_mask & 0x80) ? SPARC_I7_REGNUM : SPARC_O7_REGNUM;
1170 pc += get_frame_register_unsigned (this_frame, regnum) + 8;
1171 return frame_unwind_got_constant (this_frame, regnum, pc);
1174 /* Handle StackGhost. */
1176 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1178 if (wcookie != 0 && !cache->frameless_p && regnum == SPARC_I7_REGNUM)
1180 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1183 /* Read the value in from memory. */
1184 i7 = get_frame_memory_unsigned (this_frame, addr, 4);
1185 return frame_unwind_got_constant (this_frame, regnum, i7 ^ wcookie);
1189 /* The previous frame's `local' and `in' registers may have been saved
1190 in the register save area. */
1191 if (regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM
1192 && (cache->saved_regs_mask & (1 << (regnum - SPARC_L0_REGNUM))))
1194 CORE_ADDR addr = cache->base + (regnum - SPARC_L0_REGNUM) * 4;
1196 return frame_unwind_got_memory (this_frame, regnum, addr);
1199 /* The previous frame's `out' registers may be accessible as the current
1200 frame's `in' registers. */
1201 if (regnum >= SPARC_O0_REGNUM && regnum <= SPARC_O7_REGNUM
1202 && (cache->copied_regs_mask & (1 << (regnum - SPARC_O0_REGNUM))))
1203 regnum += (SPARC_I0_REGNUM - SPARC_O0_REGNUM);
1205 return frame_unwind_got_register (this_frame, regnum, regnum);
1208 static const struct frame_unwind sparc32_frame_unwind =
1211 default_frame_unwind_stop_reason,
1212 sparc32_frame_this_id,
1213 sparc32_frame_prev_register,
1215 default_frame_sniffer
1220 sparc32_frame_base_address (struct frame_info *this_frame, void **this_cache)
1222 struct sparc_frame_cache *cache =
1223 sparc32_frame_cache (this_frame, this_cache);
1228 static const struct frame_base sparc32_frame_base =
1230 &sparc32_frame_unwind,
1231 sparc32_frame_base_address,
1232 sparc32_frame_base_address,
1233 sparc32_frame_base_address
1236 static struct frame_id
1237 sparc_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1241 sp = get_frame_register_unsigned (this_frame, SPARC_SP_REGNUM);
1244 return frame_id_build (sp, get_frame_pc (this_frame));
1248 /* Extract a function return value of TYPE from REGCACHE, and copy
1249 that into VALBUF. */
1252 sparc32_extract_return_value (struct type *type, struct regcache *regcache,
1255 int len = TYPE_LENGTH (type);
1258 gdb_assert (!sparc_structure_or_union_p (type));
1259 gdb_assert (!(sparc_floating_p (type) && len == 16));
1261 if (sparc_floating_p (type) || sparc_complex_floating_p (type))
1263 /* Floating return values. */
1264 regcache_cooked_read (regcache, SPARC_F0_REGNUM, buf);
1266 regcache_cooked_read (regcache, SPARC_F1_REGNUM, buf + 4);
1269 regcache_cooked_read (regcache, SPARC_F2_REGNUM, buf + 8);
1270 regcache_cooked_read (regcache, SPARC_F3_REGNUM, buf + 12);
1274 regcache_cooked_read (regcache, SPARC_F4_REGNUM, buf + 16);
1275 regcache_cooked_read (regcache, SPARC_F5_REGNUM, buf + 20);
1276 regcache_cooked_read (regcache, SPARC_F6_REGNUM, buf + 24);
1277 regcache_cooked_read (regcache, SPARC_F7_REGNUM, buf + 28);
1279 memcpy (valbuf, buf, len);
1283 /* Integral and pointer return values. */
1284 gdb_assert (sparc_integral_or_pointer_p (type));
1286 regcache_cooked_read (regcache, SPARC_O0_REGNUM, buf);
1289 regcache_cooked_read (regcache, SPARC_O1_REGNUM, buf + 4);
1290 gdb_assert (len == 8);
1291 memcpy (valbuf, buf, 8);
1295 /* Just stripping off any unused bytes should preserve the
1296 signed-ness just fine. */
1297 memcpy (valbuf, buf + 4 - len, len);
1302 /* Store the function return value of type TYPE from VALBUF into
1306 sparc32_store_return_value (struct type *type, struct regcache *regcache,
1307 const gdb_byte *valbuf)
1309 int len = TYPE_LENGTH (type);
1312 gdb_assert (!sparc_structure_or_union_p (type));
1313 gdb_assert (!(sparc_floating_p (type) && len == 16));
1314 gdb_assert (len <= 8);
1316 if (sparc_floating_p (type) || sparc_complex_floating_p (type))
1318 /* Floating return values. */
1319 memcpy (buf, valbuf, len);
1320 regcache_cooked_write (regcache, SPARC_F0_REGNUM, buf);
1322 regcache_cooked_write (regcache, SPARC_F1_REGNUM, buf + 4);
1325 regcache_cooked_write (regcache, SPARC_F2_REGNUM, buf + 8);
1326 regcache_cooked_write (regcache, SPARC_F3_REGNUM, buf + 12);
1330 regcache_cooked_write (regcache, SPARC_F4_REGNUM, buf + 16);
1331 regcache_cooked_write (regcache, SPARC_F5_REGNUM, buf + 20);
1332 regcache_cooked_write (regcache, SPARC_F6_REGNUM, buf + 24);
1333 regcache_cooked_write (regcache, SPARC_F7_REGNUM, buf + 28);
1338 /* Integral and pointer return values. */
1339 gdb_assert (sparc_integral_or_pointer_p (type));
1343 gdb_assert (len == 8);
1344 memcpy (buf, valbuf, 8);
1345 regcache_cooked_write (regcache, SPARC_O1_REGNUM, buf + 4);
1349 /* ??? Do we need to do any sign-extension here? */
1350 memcpy (buf + 4 - len, valbuf, len);
1352 regcache_cooked_write (regcache, SPARC_O0_REGNUM, buf);
1356 static enum return_value_convention
1357 sparc32_return_value (struct gdbarch *gdbarch, struct type *func_type,
1358 struct type *type, struct regcache *regcache,
1359 gdb_byte *readbuf, const gdb_byte *writebuf)
1361 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1363 /* The psABI says that "...every stack frame reserves the word at
1364 %fp+64. If a function returns a structure, union, or
1365 quad-precision value, this word should hold the address of the
1366 object into which the return value should be copied." This
1367 guarantees that we can always find the return value, not just
1368 before the function returns. */
1370 if (sparc_structure_or_union_p (type)
1371 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16))
1378 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1379 addr = read_memory_unsigned_integer (sp + 64, 4, byte_order);
1380 read_memory (addr, readbuf, TYPE_LENGTH (type));
1383 return RETURN_VALUE_ABI_PRESERVES_ADDRESS;
1387 sparc32_extract_return_value (type, regcache, readbuf);
1389 sparc32_store_return_value (type, regcache, writebuf);
1391 return RETURN_VALUE_REGISTER_CONVENTION;
1395 sparc32_stabs_argument_has_addr (struct gdbarch *gdbarch, struct type *type)
1397 return (sparc_structure_or_union_p (type)
1398 || (sparc_floating_p (type) && TYPE_LENGTH (type) == 16)
1399 || sparc_complex_floating_p (type));
1403 sparc32_dwarf2_struct_return_p (struct frame_info *this_frame)
1405 CORE_ADDR pc = get_frame_address_in_block (this_frame);
1406 struct symbol *sym = find_pc_function (pc);
1409 return sparc32_struct_return_from_sym (sym);
1414 sparc32_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
1415 struct dwarf2_frame_state_reg *reg,
1416 struct frame_info *this_frame)
1422 case SPARC_G0_REGNUM:
1423 /* Since %g0 is always zero, there is no point in saving it, and
1424 people will be inclined omit it from the CFI. Make sure we
1425 don't warn about that. */
1426 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
1428 case SPARC_SP_REGNUM:
1429 reg->how = DWARF2_FRAME_REG_CFA;
1431 case SPARC32_PC_REGNUM:
1432 case SPARC32_NPC_REGNUM:
1433 reg->how = DWARF2_FRAME_REG_RA_OFFSET;
1435 if (sparc32_dwarf2_struct_return_p (this_frame))
1437 if (regnum == SPARC32_NPC_REGNUM)
1439 reg->loc.offset = off;
1445 /* The SPARC Architecture doesn't have hardware single-step support,
1446 and most operating systems don't implement it either, so we provide
1447 software single-step mechanism. */
1450 sparc_analyze_control_transfer (struct frame_info *frame,
1451 CORE_ADDR pc, CORE_ADDR *npc)
1453 unsigned long insn = sparc_fetch_instruction (pc);
1454 int conditional_p = X_COND (insn) & 0x7;
1455 int branch_p = 0, fused_p = 0;
1456 long offset = 0; /* Must be signed for sign-extend. */
1458 if (X_OP (insn) == 0 && X_OP2 (insn) == 3)
1460 if ((insn & 0x10000000) == 0)
1462 /* Branch on Integer Register with Prediction (BPr). */
1468 /* Compare and Branch */
1471 offset = 4 * X_DISP10 (insn);
1474 else if (X_OP (insn) == 0 && X_OP2 (insn) == 6)
1476 /* Branch on Floating-Point Condition Codes (FBfcc). */
1478 offset = 4 * X_DISP22 (insn);
1480 else if (X_OP (insn) == 0 && X_OP2 (insn) == 5)
1482 /* Branch on Floating-Point Condition Codes with Prediction
1485 offset = 4 * X_DISP19 (insn);
1487 else if (X_OP (insn) == 0 && X_OP2 (insn) == 2)
1489 /* Branch on Integer Condition Codes (Bicc). */
1491 offset = 4 * X_DISP22 (insn);
1493 else if (X_OP (insn) == 0 && X_OP2 (insn) == 1)
1495 /* Branch on Integer Condition Codes with Prediction (BPcc). */
1497 offset = 4 * X_DISP19 (insn);
1499 else if (X_OP (insn) == 2 && X_OP3 (insn) == 0x3a)
1501 /* Trap instruction (TRAP). */
1502 return gdbarch_tdep (get_frame_arch (frame))->step_trap (frame, insn);
1505 /* FIXME: Handle DONE and RETRY instructions. */
1511 /* Fused compare-and-branch instructions are non-delayed,
1512 and do not have an annuling capability. So we need to
1513 always set a breakpoint on both the NPC and the branch
1515 gdb_assert (offset != 0);
1518 else if (conditional_p)
1520 /* For conditional branches, return nPC + 4 iff the annul
1522 return (X_A (insn) ? *npc + 4 : 0);
1526 /* For unconditional branches, return the target if its
1527 specified condition is "always" and return nPC + 4 if the
1528 condition is "never". If the annul bit is 1, set *NPC to
1530 if (X_COND (insn) == 0x0)
1531 pc = *npc, offset = 4;
1535 gdb_assert (offset != 0);
1544 sparc_step_trap (struct frame_info *frame, unsigned long insn)
1550 sparc_software_single_step (struct frame_info *frame)
1552 struct gdbarch *arch = get_frame_arch (frame);
1553 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1554 struct address_space *aspace = get_frame_address_space (frame);
1555 CORE_ADDR npc, nnpc;
1557 CORE_ADDR pc, orig_npc;
1559 pc = get_frame_register_unsigned (frame, tdep->pc_regnum);
1560 orig_npc = npc = get_frame_register_unsigned (frame, tdep->npc_regnum);
1562 /* Analyze the instruction at PC. */
1563 nnpc = sparc_analyze_control_transfer (frame, pc, &npc);
1565 insert_single_step_breakpoint (arch, aspace, npc);
1568 insert_single_step_breakpoint (arch, aspace, nnpc);
1570 /* Assert that we have set at least one breakpoint, and that
1571 they're not set at the same spot - unless we're going
1572 from here straight to NULL, i.e. a call or jump to 0. */
1573 gdb_assert (npc != 0 || nnpc != 0 || orig_npc == 0);
1574 gdb_assert (nnpc != npc || orig_npc == 0);
1580 sparc_write_pc (struct regcache *regcache, CORE_ADDR pc)
1582 struct gdbarch_tdep *tdep = gdbarch_tdep (get_regcache_arch (regcache));
1584 regcache_cooked_write_unsigned (regcache, tdep->pc_regnum, pc);
1585 regcache_cooked_write_unsigned (regcache, tdep->npc_regnum, pc + 4);
1589 /* Return the appropriate register set for the core section identified
1590 by SECT_NAME and SECT_SIZE. */
1592 static const struct regset *
1593 sparc_regset_from_core_section (struct gdbarch *gdbarch,
1594 const char *sect_name, size_t sect_size)
1596 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1598 if (strcmp (sect_name, ".reg") == 0 && sect_size >= tdep->sizeof_gregset)
1599 return tdep->gregset;
1601 if (strcmp (sect_name, ".reg2") == 0 && sect_size >= tdep->sizeof_fpregset)
1602 return tdep->fpregset;
1608 static struct gdbarch *
1609 sparc32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1611 struct gdbarch_tdep *tdep;
1612 struct gdbarch *gdbarch;
1614 /* If there is already a candidate, use it. */
1615 arches = gdbarch_list_lookup_by_info (arches, &info);
1617 return arches->gdbarch;
1619 /* Allocate space for the new architecture. */
1620 tdep = XZALLOC (struct gdbarch_tdep);
1621 gdbarch = gdbarch_alloc (&info, tdep);
1623 tdep->pc_regnum = SPARC32_PC_REGNUM;
1624 tdep->npc_regnum = SPARC32_NPC_REGNUM;
1625 tdep->step_trap = sparc_step_trap;
1627 set_gdbarch_long_double_bit (gdbarch, 128);
1628 set_gdbarch_long_double_format (gdbarch, floatformats_sparc_quad);
1630 set_gdbarch_num_regs (gdbarch, SPARC32_NUM_REGS);
1631 set_gdbarch_register_name (gdbarch, sparc32_register_name);
1632 set_gdbarch_register_type (gdbarch, sparc32_register_type);
1633 set_gdbarch_num_pseudo_regs (gdbarch, SPARC32_NUM_PSEUDO_REGS);
1634 set_gdbarch_pseudo_register_read (gdbarch, sparc32_pseudo_register_read);
1635 set_gdbarch_pseudo_register_write (gdbarch, sparc32_pseudo_register_write);
1637 /* Register numbers of various important registers. */
1638 set_gdbarch_sp_regnum (gdbarch, SPARC_SP_REGNUM); /* %sp */
1639 set_gdbarch_pc_regnum (gdbarch, SPARC32_PC_REGNUM); /* %pc */
1640 set_gdbarch_fp0_regnum (gdbarch, SPARC_F0_REGNUM); /* %f0 */
1642 /* Call dummy code. */
1643 set_gdbarch_frame_align (gdbarch, sparc32_frame_align);
1644 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
1645 set_gdbarch_push_dummy_code (gdbarch, sparc32_push_dummy_code);
1646 set_gdbarch_push_dummy_call (gdbarch, sparc32_push_dummy_call);
1648 set_gdbarch_return_value (gdbarch, sparc32_return_value);
1649 set_gdbarch_stabs_argument_has_addr
1650 (gdbarch, sparc32_stabs_argument_has_addr);
1652 set_gdbarch_skip_prologue (gdbarch, sparc32_skip_prologue);
1654 /* Stack grows downward. */
1655 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1657 set_gdbarch_breakpoint_from_pc (gdbarch, sparc_breakpoint_from_pc);
1659 set_gdbarch_frame_args_skip (gdbarch, 8);
1661 set_gdbarch_print_insn (gdbarch, print_insn_sparc);
1663 set_gdbarch_software_single_step (gdbarch, sparc_software_single_step);
1664 set_gdbarch_write_pc (gdbarch, sparc_write_pc);
1666 set_gdbarch_dummy_id (gdbarch, sparc_dummy_id);
1668 set_gdbarch_unwind_pc (gdbarch, sparc_unwind_pc);
1670 frame_base_set_default (gdbarch, &sparc32_frame_base);
1672 /* Hook in the DWARF CFI frame unwinder. */
1673 dwarf2_frame_set_init_reg (gdbarch, sparc32_dwarf2_frame_init_reg);
1674 /* FIXME: kettenis/20050423: Don't enable the unwinder until the
1675 StackGhost issues have been resolved. */
1677 /* Hook in ABI-specific overrides, if they have been registered. */
1678 gdbarch_init_osabi (info, gdbarch);
1680 frame_unwind_append_unwinder (gdbarch, &sparc32_frame_unwind);
1682 /* If we have register sets, enable the generic core file support. */
1684 set_gdbarch_regset_from_core_section (gdbarch,
1685 sparc_regset_from_core_section);
1690 /* Helper functions for dealing with register windows. */
1693 sparc_supply_rwindow (struct regcache *regcache, CORE_ADDR sp, int regnum)
1695 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1696 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1703 /* Registers are 64-bit. */
1706 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1708 if (regnum == i || regnum == -1)
1710 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1712 /* Handle StackGhost. */
1713 if (i == SPARC_I7_REGNUM)
1715 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1718 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1719 store_unsigned_integer (buf + offset, 8, byte_order,
1723 regcache_raw_supply (regcache, i, buf);
1729 /* Registers are 32-bit. Toss any sign-extension of the stack
1733 /* Clear out the top half of the temporary buffer, and put the
1734 register value in the bottom half if we're in 64-bit mode. */
1735 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1741 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1743 if (regnum == i || regnum == -1)
1745 target_read_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1748 /* Handle StackGhost. */
1749 if (i == SPARC_I7_REGNUM)
1751 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1754 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
1755 store_unsigned_integer (buf + offset, 4, byte_order,
1759 regcache_raw_supply (regcache, i, buf);
1766 sparc_collect_rwindow (const struct regcache *regcache,
1767 CORE_ADDR sp, int regnum)
1769 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1770 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1777 /* Registers are 64-bit. */
1780 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1782 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1784 regcache_raw_collect (regcache, i, buf);
1786 /* Handle StackGhost. */
1787 if (i == SPARC_I7_REGNUM)
1789 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1792 i7 = extract_unsigned_integer (buf + offset, 8, byte_order);
1793 store_unsigned_integer (buf, 8, byte_order, i7 ^ wcookie);
1796 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 8), buf, 8);
1802 /* Registers are 32-bit. Toss any sign-extension of the stack
1806 /* Only use the bottom half if we're in 64-bit mode. */
1807 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64)
1810 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1812 if (regnum == -1 || regnum == SPARC_SP_REGNUM || regnum == i)
1814 regcache_raw_collect (regcache, i, buf);
1816 /* Handle StackGhost. */
1817 if (i == SPARC_I7_REGNUM)
1819 ULONGEST wcookie = sparc_fetch_wcookie (gdbarch);
1822 i7 = extract_unsigned_integer (buf + offset, 4, byte_order);
1823 store_unsigned_integer (buf + offset, 4, byte_order,
1827 target_write_memory (sp + ((i - SPARC_L0_REGNUM) * 4),
1834 /* Helper functions for dealing with register sets. */
1837 sparc32_supply_gregset (const struct sparc_gregset *gregset,
1838 struct regcache *regcache,
1839 int regnum, const void *gregs)
1841 const gdb_byte *regs = gregs;
1842 gdb_byte zero[4] = { 0 };
1845 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1846 regcache_raw_supply (regcache, SPARC32_PSR_REGNUM,
1847 regs + gregset->r_psr_offset);
1849 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1850 regcache_raw_supply (regcache, SPARC32_PC_REGNUM,
1851 regs + gregset->r_pc_offset);
1853 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1854 regcache_raw_supply (regcache, SPARC32_NPC_REGNUM,
1855 regs + gregset->r_npc_offset);
1857 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1858 regcache_raw_supply (regcache, SPARC32_Y_REGNUM,
1859 regs + gregset->r_y_offset);
1861 if (regnum == SPARC_G0_REGNUM || regnum == -1)
1862 regcache_raw_supply (regcache, SPARC_G0_REGNUM, &zero);
1864 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1866 int offset = gregset->r_g1_offset;
1868 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1870 if (regnum == i || regnum == -1)
1871 regcache_raw_supply (regcache, i, regs + offset);
1876 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1878 /* Not all of the register set variants include Locals and
1879 Inputs. For those that don't, we read them off the stack. */
1880 if (gregset->r_l0_offset == -1)
1884 regcache_cooked_read_unsigned (regcache, SPARC_SP_REGNUM, &sp);
1885 sparc_supply_rwindow (regcache, sp, regnum);
1889 int offset = gregset->r_l0_offset;
1891 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1893 if (regnum == i || regnum == -1)
1894 regcache_raw_supply (regcache, i, regs + offset);
1902 sparc32_collect_gregset (const struct sparc_gregset *gregset,
1903 const struct regcache *regcache,
1904 int regnum, void *gregs)
1906 gdb_byte *regs = gregs;
1909 if (regnum == SPARC32_PSR_REGNUM || regnum == -1)
1910 regcache_raw_collect (regcache, SPARC32_PSR_REGNUM,
1911 regs + gregset->r_psr_offset);
1913 if (regnum == SPARC32_PC_REGNUM || regnum == -1)
1914 regcache_raw_collect (regcache, SPARC32_PC_REGNUM,
1915 regs + gregset->r_pc_offset);
1917 if (regnum == SPARC32_NPC_REGNUM || regnum == -1)
1918 regcache_raw_collect (regcache, SPARC32_NPC_REGNUM,
1919 regs + gregset->r_npc_offset);
1921 if (regnum == SPARC32_Y_REGNUM || regnum == -1)
1922 regcache_raw_collect (regcache, SPARC32_Y_REGNUM,
1923 regs + gregset->r_y_offset);
1925 if ((regnum >= SPARC_G1_REGNUM && regnum <= SPARC_O7_REGNUM) || regnum == -1)
1927 int offset = gregset->r_g1_offset;
1929 /* %g0 is always zero. */
1930 for (i = SPARC_G1_REGNUM; i <= SPARC_O7_REGNUM; i++)
1932 if (regnum == i || regnum == -1)
1933 regcache_raw_collect (regcache, i, regs + offset);
1938 if ((regnum >= SPARC_L0_REGNUM && regnum <= SPARC_I7_REGNUM) || regnum == -1)
1940 /* Not all of the register set variants include Locals and
1941 Inputs. For those that don't, we read them off the stack. */
1942 if (gregset->r_l0_offset != -1)
1944 int offset = gregset->r_l0_offset;
1946 for (i = SPARC_L0_REGNUM; i <= SPARC_I7_REGNUM; i++)
1948 if (regnum == i || regnum == -1)
1949 regcache_raw_collect (regcache, i, regs + offset);
1957 sparc32_supply_fpregset (struct regcache *regcache,
1958 int regnum, const void *fpregs)
1960 const gdb_byte *regs = fpregs;
1963 for (i = 0; i < 32; i++)
1965 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1966 regcache_raw_supply (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1969 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1970 regcache_raw_supply (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1974 sparc32_collect_fpregset (const struct regcache *regcache,
1975 int regnum, void *fpregs)
1977 gdb_byte *regs = fpregs;
1980 for (i = 0; i < 32; i++)
1982 if (regnum == (SPARC_F0_REGNUM + i) || regnum == -1)
1983 regcache_raw_collect (regcache, SPARC_F0_REGNUM + i, regs + (i * 4));
1986 if (regnum == SPARC32_FSR_REGNUM || regnum == -1)
1987 regcache_raw_collect (regcache, SPARC32_FSR_REGNUM, regs + (32 * 4) + 4);
1993 /* From <machine/reg.h>. */
1994 const struct sparc_gregset sparc32_sunos4_gregset =
2007 /* Provide a prototype to silence -Wmissing-prototypes. */
2008 void _initialize_sparc_tdep (void);
2011 _initialize_sparc_tdep (void)
2013 register_gdbarch_init (bfd_arch_sparc, sparc32_gdbarch_init);