1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
24 Contributed by Steve Chamberlain
30 #include "frame-base.h"
31 #include "frame-unwind.h"
32 #include "dwarf2-frame.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
50 /* registers numbers shared with the simulator */
51 #include "gdb/sim-sh.h"
53 /* Information that is dependent on the processor variant. */
66 struct sh64_frame_cache
73 /* Flag showing that a frame has been created in the prologue code. */
78 /* Saved registers. */
79 CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
83 /* Registers of SH5 */
87 DEFAULT_RETURN_REGNUM = 2,
88 STRUCT_RETURN_REGNUM = 2,
91 FLOAT_ARGLAST_REGNUM = 11,
97 /* FPP stands for Floating Point Pair, to avoid confusion with
98 GDB's FP0_REGNUM, which is the number of the first Floating
99 point register. Unfortunately on the sh5, the floating point
100 registers are called FR, and the floating point pairs are called FP. */
102 FPP_LAST_REGNUM = 204,
104 FV_LAST_REGNUM = 220,
106 R_LAST_C_REGNUM = 236,
113 FPSCR_C_REGNUM = 243,
116 FP_LAST_C_REGNUM = 260,
118 DR_LAST_C_REGNUM = 268,
120 FV_LAST_C_REGNUM = 272,
121 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
122 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
123 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
124 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
125 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
129 sh64_register_name (int reg_nr)
131 static char *register_names[] =
133 /* SH MEDIA MODE (ISA 32) */
134 /* general registers (64-bit) 0-63 */
135 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
136 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
137 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
138 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
139 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
140 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
141 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
142 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
147 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
150 /* target registers (64-bit) 68-75*/
151 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
153 /* floating point state control register (32-bit) 76 */
156 /* single precision floating point registers (32-bit) 77-140*/
157 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
158 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
159 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
160 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
161 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
162 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
163 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
164 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
166 /* double precision registers (pseudo) 141-172 */
167 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
168 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
169 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
170 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
172 /* floating point pairs (pseudo) 173-204*/
173 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
174 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
175 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
176 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
178 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
179 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
180 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
182 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
183 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
184 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
186 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
188 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
189 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
190 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
191 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
192 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return register_names[reg_nr];
202 #define NUM_PSEUDO_REGS_SH_MEDIA 80
203 #define NUM_PSEUDO_REGS_SH_COMPACT 51
205 /* Macros and functions for setting and testing a bit in a minimal
206 symbol that marks it as 32-bit function. The MSB of the minimal
207 symbol's "info" field is used for this purpose.
209 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
210 i.e. refers to a 32-bit function, and sets a "special" bit in a
211 minimal symbol to mark it as a 32-bit function
212 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
214 #define MSYMBOL_IS_SPECIAL(msym) \
215 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
218 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
223 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
225 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
226 SYMBOL_VALUE_ADDRESS (msym) |= 1;
230 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
231 are some macros to test, set, or clear bit 0 of addresses. */
232 #define IS_ISA32_ADDR(addr) ((addr) & 1)
233 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
234 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
237 pc_is_isa32 (bfd_vma memaddr)
239 struct minimal_symbol *sym;
241 /* If bit 0 of the address is set, assume this is a
242 ISA32 (shmedia) address. */
243 if (IS_ISA32_ADDR (memaddr))
246 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
247 the high bit of the info field. Use this to decide if the function is
249 sym = lookup_minimal_symbol_by_pc (memaddr);
251 return MSYMBOL_IS_SPECIAL (sym);
256 static const unsigned char *
257 sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
259 /* The BRK instruction for shmedia is
260 01101111 11110101 11111111 11110000
261 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
262 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
264 /* The BRK instruction for shcompact is
266 which translates in big endian mode to 0x0, 0x3b
267 and in little endian mode to 0x3b, 0x0*/
269 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
271 if (pc_is_isa32 (*pcptr))
273 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
274 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
275 *lenptr = sizeof (big_breakpoint_media);
276 return big_breakpoint_media;
280 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
281 *lenptr = sizeof (big_breakpoint_compact);
282 return big_breakpoint_compact;
287 if (pc_is_isa32 (*pcptr))
289 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
290 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
291 *lenptr = sizeof (little_breakpoint_media);
292 return little_breakpoint_media;
296 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
297 *lenptr = sizeof (little_breakpoint_compact);
298 return little_breakpoint_compact;
303 /* Prologue looks like
304 [mov.l <regs>,@-r15]...
309 Actually it can be more complicated than this. For instance, with
327 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
328 with l=1 and n = 18 0110101111110001010010100aaa0000 */
329 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
331 /* STS.L PR,@-r0 0100000000100010
332 r0-4-->r0, PR-->(r0) */
333 #define IS_STS_R0(x) ((x) == 0x4022)
335 /* STS PR, Rm 0000mmmm00101010
337 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
339 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
341 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
343 /* MOV.L R14,@(disp,r15) 000111111110dddd
344 R14-->(dispx4+r15) */
345 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
347 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
348 R18-->(dispx8+R14) */
349 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
351 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
352 R18-->(dispx8+R15) */
353 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
355 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
356 R18-->(dispx4+R15) */
357 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
359 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
360 R14-->(dispx8+R15) */
361 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
363 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
364 R14-->(dispx4+R15) */
365 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
367 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
369 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
371 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
373 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
375 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
377 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
379 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
381 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
383 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
385 /* MOV #imm, R0 1110 0000 ssss ssss
387 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
389 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
390 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
392 /* ADD r15,r0 0011 0000 1111 1100
394 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
396 /* MOV.L R14 @-R0 0010 0000 1110 0110
397 R14-->(R0-4), R0-4-->R0 */
398 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
400 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
401 where Rm is one of r2-r9 which are the argument registers. */
402 /* FIXME: Recognize the float and double register moves too! */
403 #define IS_MEDIA_IND_ARG_MOV(x) \
404 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
406 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
407 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
408 where Rm is one of r2-r9 which are the argument registers. */
409 #define IS_MEDIA_ARG_MOV(x) \
410 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
411 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
413 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
414 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
415 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
416 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
417 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
418 #define IS_MEDIA_MOV_TO_R14(x) \
419 ((((x) & 0xfffffc0f) == 0xa0e00000) \
420 || (((x) & 0xfffffc0f) == 0xa4e00000) \
421 || (((x) & 0xfffffc0f) == 0xa8e00000) \
422 || (((x) & 0xfffffc0f) == 0xb4e00000) \
423 || (((x) & 0xfffffc0f) == 0xbce00000))
425 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
427 #define IS_COMPACT_IND_ARG_MOV(x) \
428 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
430 /* compact direct arg move!
431 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
432 #define IS_COMPACT_ARG_MOV(x) \
433 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
435 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
436 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
437 #define IS_COMPACT_MOV_TO_R14(x) \
438 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
440 #define IS_JSR_R0(x) ((x) == 0x400b)
441 #define IS_NOP(x) ((x) == 0x0009)
444 /* MOV r15,r14 0110111011110011
446 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
448 /* ADD #imm,r15 01111111iiiiiiii
450 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
452 /* Skip any prologue before the guts of a function */
454 /* Skip the prologue using the debug information. If this fails we'll
455 fall back on the 'guess' method below. */
457 after_prologue (CORE_ADDR pc)
459 struct symtab_and_line sal;
460 CORE_ADDR func_addr, func_end;
462 /* If we can not find the symbol in the partial symbol table, then
463 there is no hope we can determine the function's start address
465 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
469 /* Get the line associated with FUNC_ADDR. */
470 sal = find_pc_line (func_addr, 0);
472 /* There are only two cases to consider. First, the end of the source line
473 is within the function bounds. In that case we return the end of the
474 source line. Second is the end of the source line extends beyond the
475 bounds of the current function. We need to use the slow code to
476 examine instructions in that case. */
477 if (sal.end < func_end)
484 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
488 int insn_size = (media_mode ? 4 : 2);
490 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
494 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
496 if (IS_MEDIA_IND_ARG_MOV (w))
498 /* This must be followed by a store to r14, so the argument
499 is where the debug info says it is. This can happen after
500 the SP has been saved, unfortunately. */
502 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
505 if (IS_MEDIA_MOV_TO_R14 (next_insn))
508 else if (IS_MEDIA_ARG_MOV (w))
510 /* These instructions store directly the argument in r14. */
518 w = read_memory_integer (here, insn_size);
521 if (IS_COMPACT_IND_ARG_MOV (w))
523 /* This must be followed by a store to r14, so the argument
524 is where the debug info says it is. This can happen after
525 the SP has been saved, unfortunately. */
527 int next_insn = 0xffff & read_memory_integer (here, insn_size);
529 if (IS_COMPACT_MOV_TO_R14 (next_insn))
532 else if (IS_COMPACT_ARG_MOV (w))
534 /* These instructions store directly the argument in r14. */
537 else if (IS_MOVL_R0 (w))
539 /* There is a function that gcc calls to get the arguments
540 passed correctly to the function. Only after this
541 function call the arguments will be found at the place
542 where they are supposed to be. This happens in case the
543 argument has to be stored into a 64-bit register (for
544 instance doubles, long longs). SHcompact doesn't have
545 access to the full 64-bits, so we store the register in
546 stack slot and store the address of the stack slot in
547 the register, then do a call through a wrapper that
548 loads the memory value into the register. A SHcompact
549 callee calls an argument decoder
550 (GCC_shcompact_incoming_args) that stores the 64-bit
551 value in a stack slot and stores the address of the
552 stack slot in the register. GCC thinks the argument is
553 just passed by transparent reference, but this is only
554 true after the argument decoder is called. Such a call
555 needs to be considered part of the prologue. */
557 /* This must be followed by a JSR @r0 instruction and by
558 a NOP instruction. After these, the prologue is over! */
560 int next_insn = 0xffff & read_memory_integer (here, insn_size);
562 if (IS_JSR_R0 (next_insn))
564 next_insn = 0xffff & read_memory_integer (here, insn_size);
567 if (IS_NOP (next_insn))
580 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
590 if (pc_is_isa32 (start_pc) == 0)
596 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
601 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
603 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
604 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
605 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
609 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
617 /* Don't bail out yet, we may have arguments stored in
618 registers here, according to the debug info, so that
619 gdb can print the frames correctly. */
620 start_pc = look_for_args_moves (here - insn_size, media_mode);
626 int w = 0xffff & read_memory_integer (here, insn_size);
629 if (IS_STS_R0 (w) || IS_STS_PR (w)
630 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
631 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
635 else if (IS_MOV_SP_FP (w))
643 /* Don't bail out yet, we may have arguments stored in
644 registers here, according to the debug info, so that
645 gdb can print the frames correctly. */
646 start_pc = look_for_args_moves (here - insn_size, media_mode);
656 sh64_skip_prologue (CORE_ADDR pc)
658 CORE_ADDR post_prologue_pc;
660 /* See if we can determine the end of the prologue via the symbol table.
661 If so, then return either PC, or the PC after the prologue, whichever
663 post_prologue_pc = after_prologue (pc);
665 /* If after_prologue returned a useful address, then use it. Else
666 fall back on the instruction skipping code. */
667 if (post_prologue_pc != 0)
668 return max (pc, post_prologue_pc);
670 return sh64_skip_prologue_hard_way (pc);
673 /* Should call_function allocate stack space for a struct return? */
675 sh64_use_struct_convention (struct type *type)
677 return (TYPE_LENGTH (type) > 8);
680 /* Disassemble an instruction. */
682 gdb_print_insn_sh64 (bfd_vma memaddr, disassemble_info *info)
684 info->endian = gdbarch_byte_order (current_gdbarch);
685 return print_insn_sh (memaddr, info);
688 /* For vectors of 4 floating point registers. */
690 sh64_fv_reg_base_num (int fv_regnum)
694 fp_regnum = FP0_REGNUM +
695 (fv_regnum - FV0_REGNUM) * 4;
699 /* For double precision floating point registers, i.e 2 fp regs.*/
701 sh64_dr_reg_base_num (int dr_regnum)
705 fp_regnum = FP0_REGNUM +
706 (dr_regnum - DR0_REGNUM) * 2;
710 /* For pairs of floating point registers */
712 sh64_fpp_reg_base_num (int fpp_regnum)
716 fp_regnum = FP0_REGNUM +
717 (fpp_regnum - FPP0_REGNUM) * 2;
723 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
724 GDB_REGNUM BASE_REGNUM
784 sh64_compact_reg_base_num (int reg_nr)
786 int base_regnum = reg_nr;
788 /* general register N maps to general register N */
789 if (reg_nr >= R0_C_REGNUM
790 && reg_nr <= R_LAST_C_REGNUM)
791 base_regnum = reg_nr - R0_C_REGNUM;
793 /* floating point register N maps to floating point register N */
794 else if (reg_nr >= FP0_C_REGNUM
795 && reg_nr <= FP_LAST_C_REGNUM)
796 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
798 /* double prec register N maps to base regnum for double prec register N */
799 else if (reg_nr >= DR0_C_REGNUM
800 && reg_nr <= DR_LAST_C_REGNUM)
801 base_regnum = sh64_dr_reg_base_num (DR0_REGNUM + reg_nr - DR0_C_REGNUM);
803 /* vector N maps to base regnum for vector register N */
804 else if (reg_nr >= FV0_C_REGNUM
805 && reg_nr <= FV_LAST_C_REGNUM)
806 base_regnum = sh64_fv_reg_base_num (FV0_REGNUM + reg_nr - FV0_C_REGNUM);
808 else if (reg_nr == PC_C_REGNUM)
809 base_regnum = PC_REGNUM;
811 else if (reg_nr == GBR_C_REGNUM)
814 else if (reg_nr == MACH_C_REGNUM
815 || reg_nr == MACL_C_REGNUM)
818 else if (reg_nr == PR_C_REGNUM)
819 base_regnum = PR_REGNUM;
821 else if (reg_nr == T_C_REGNUM)
824 else if (reg_nr == FPSCR_C_REGNUM)
825 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
827 else if (reg_nr == FPUL_C_REGNUM)
828 base_regnum = FP0_REGNUM + 32;
834 sign_extend (int value, int bits)
836 value = value & ((1 << bits) - 1);
837 return (value & (1 << (bits - 1))
838 ? value | (~((1 << bits) - 1))
843 sh64_analyze_prologue (struct gdbarch *gdbarch,
844 struct sh64_frame_cache *cache,
846 CORE_ADDR current_pc)
854 int gdb_register_number;
856 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
858 cache->sp_offset = 0;
860 /* Loop around examining the prologue insns until we find something
861 that does not appear to be part of the prologue. But give up
862 after 20 of them, since we're getting silly then. */
866 if (cache->media_mode)
871 opc = pc + (insn_size * 28);
872 if (opc > current_pc)
874 for ( ; pc <= opc; pc += insn_size)
876 insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
880 if (!cache->media_mode)
882 if (IS_STS_PR (insn))
884 int next_insn = read_memory_integer (pc + insn_size, insn_size);
885 if (IS_MOV_TO_R15 (next_insn))
887 cache->saved_regs[PR_REGNUM] =
888 cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
893 else if (IS_MOV_R14 (insn))
894 cache->saved_regs[MEDIA_FP_REGNUM] =
895 cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
897 else if (IS_MOV_R0 (insn))
899 /* Put in R0 the offset from SP at which to store some
900 registers. We are interested in this value, because it
901 will tell us where the given registers are stored within
903 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
906 else if (IS_ADD_SP_R0 (insn))
908 /* This instruction still prepares r0, but we don't care.
909 We already have the offset in r0_val. */
912 else if (IS_STS_R0 (insn))
914 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
915 cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
919 else if (IS_MOV_R14_R0 (insn))
921 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
922 cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
927 else if (IS_ADD_SP (insn))
928 cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
930 else if (IS_MOV_SP_FP (insn))
935 if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
937 sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
939 else if (IS_STQ_R18_R15 (insn))
940 cache->saved_regs[PR_REGNUM] =
941 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
943 else if (IS_STL_R18_R15 (insn))
944 cache->saved_regs[PR_REGNUM] =
945 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
947 else if (IS_STQ_R14_R15 (insn))
948 cache->saved_regs[MEDIA_FP_REGNUM] =
949 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
951 else if (IS_STL_R14_R15 (insn))
952 cache->saved_regs[MEDIA_FP_REGNUM] =
953 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
955 else if (IS_MOV_SP_FP_MEDIA (insn))
960 if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0)
965 sh64_extract_struct_value_address (struct regcache *regcache)
967 /* FIXME: cagney/2004-01-17: Does the ABI guarantee that the return
968 address regster is preserved across function calls? Probably
969 not, making this function wrong. */
971 regcache_raw_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &val);
976 sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
981 /* Function: push_dummy_call
982 Setup the function arguments for calling a function in the inferior.
984 On the Renesas SH architecture, there are four registers (R4 to R7)
985 which are dedicated for passing function arguments. Up to the first
986 four arguments (depending on size) may go into these registers.
987 The rest go on the stack.
989 Arguments that are smaller than 4 bytes will still take up a whole
990 register or a whole 32-bit word on the stack, and will be
991 right-justified in the register or the stack word. This includes
992 chars, shorts, and small aggregate types.
994 Arguments that are larger than 4 bytes may be split between two or
995 more registers. If there are not enough registers free, an argument
996 may be passed partly in a register (or registers), and partly on the
997 stack. This includes doubles, long longs, and larger aggregates.
998 As far as I know, there is no upper limit to the size of aggregates
999 that will be passed in this way; in other words, the convention of
1000 passing a pointer to a large aggregate instead of a copy is not used.
1002 An exceptional case exists for struct arguments (and possibly other
1003 aggregates such as arrays) if the size is larger than 4 bytes but
1004 not a multiple of 4 bytes. In this case the argument is never split
1005 between the registers and the stack, but instead is copied in its
1006 entirety onto the stack, AND also copied into as many registers as
1007 there is room for. In other words, space in registers permitting,
1008 two copies of the same argument are passed in. As far as I can tell,
1009 only the one on the stack is used, although that may be a function
1010 of the level of compiler optimization. I suspect this is a compiler
1011 bug. Arguments of these odd sizes are left-justified within the
1012 word (as opposed to arguments smaller than 4 bytes, which are
1015 If the function is to return an aggregate type such as a struct, it
1016 is either returned in the normal return value register R0 (if its
1017 size is no greater than one byte), or else the caller must allocate
1018 space into which the callee will copy the return value (if the size
1019 is greater than one byte). In this case, a pointer to the return
1020 value location is passed into the callee in register R2, which does
1021 not displace any of the other arguments passed in via registers R4
1024 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1025 non-scalar (struct, union) elements (even if the elements are
1027 FR0-FR11 for single precision floating point (float)
1028 DR0-DR10 for double precision floating point (double)
1030 If a float is argument number 3 (for instance) and arguments number
1031 1,2, and 4 are integer, the mapping will be:
1032 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1034 If a float is argument number 10 (for instance) and arguments number
1035 1 through 10 are integer, the mapping will be:
1036 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1037 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1038 I.e. there is hole in the stack.
1040 Different rules apply for variable arguments functions, and for functions
1041 for which the prototype is not known. */
1044 sh64_push_dummy_call (struct gdbarch *gdbarch,
1045 struct value *function,
1046 struct regcache *regcache,
1048 int nargs, struct value **args,
1049 CORE_ADDR sp, int struct_return,
1050 CORE_ADDR struct_addr)
1052 int stack_offset, stack_alloc;
1056 int float_arg_index = 0;
1057 int double_arg_index = 0;
1068 memset (fp_args, 0, sizeof (fp_args));
1070 /* first force sp to a 8-byte alignment */
1071 sp = sh64_frame_align (gdbarch, sp);
1073 /* The "struct return pointer" pseudo-argument has its own dedicated
1077 regcache_cooked_write_unsigned (regcache,
1078 STRUCT_RETURN_REGNUM, struct_addr);
1080 /* Now make sure there's space on the stack */
1081 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1082 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
1083 sp -= stack_alloc; /* make room on stack for args */
1085 /* Now load as many as possible of the first arguments into
1086 registers, and push the rest onto the stack. There are 64 bytes
1087 in eight registers available. Loop thru args from first to last. */
1089 int_argreg = ARG0_REGNUM;
1090 float_argreg = FP0_REGNUM;
1091 double_argreg = DR0_REGNUM;
1093 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1095 type = value_type (args[argnum]);
1096 len = TYPE_LENGTH (type);
1097 memset (valbuf, 0, sizeof (valbuf));
1099 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1101 argreg_size = register_size (current_gdbarch, int_argreg);
1103 if (len < argreg_size)
1105 /* value gets right-justified in the register or stack word */
1106 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1107 memcpy (valbuf + argreg_size - len,
1108 (char *) value_contents (args[argnum]), len);
1110 memcpy (valbuf, (char *) value_contents (args[argnum]), len);
1115 val = (char *) value_contents (args[argnum]);
1119 if (int_argreg > ARGLAST_REGNUM)
1121 /* must go on the stack */
1122 write_memory (sp + stack_offset, (const bfd_byte *) val,
1124 stack_offset += 8;/*argreg_size;*/
1126 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1127 That's because some *&^%$ things get passed on the stack
1128 AND in the registers! */
1129 if (int_argreg <= ARGLAST_REGNUM)
1131 /* there's room in a register */
1132 regval = extract_unsigned_integer (val, argreg_size);
1133 regcache_cooked_write_unsigned (regcache, int_argreg, regval);
1135 /* Store the value 8 bytes at a time. This means that
1136 things larger than 8 bytes may go partly in registers
1137 and partly on the stack. FIXME: argreg is incremented
1138 before we use its size. */
1146 val = (char *) value_contents (args[argnum]);
1149 /* Where is it going to be stored? */
1150 while (fp_args[float_arg_index])
1153 /* Now float_argreg points to the register where it
1154 should be stored. Are we still within the allowed
1156 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1158 /* Goes in FR0...FR11 */
1159 regcache_cooked_write (regcache,
1160 FP0_REGNUM + float_arg_index,
1162 fp_args[float_arg_index] = 1;
1163 /* Skip the corresponding general argument register. */
1168 /* Store it as the integers, 8 bytes at the time, if
1169 necessary spilling on the stack. */
1174 /* Where is it going to be stored? */
1175 while (fp_args[double_arg_index])
1176 double_arg_index += 2;
1177 /* Now double_argreg points to the register
1178 where it should be stored.
1179 Are we still within the allowed register set? */
1180 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1182 /* Goes in DR0...DR10 */
1183 /* The numbering of the DRi registers is consecutive,
1184 i.e. includes odd numbers. */
1185 int double_register_offset = double_arg_index / 2;
1186 int regnum = DR0_REGNUM + double_register_offset;
1187 regcache_cooked_write (regcache, regnum, val);
1188 fp_args[double_arg_index] = 1;
1189 fp_args[double_arg_index + 1] = 1;
1190 /* Skip the corresponding general argument register. */
1195 /* Store it as the integers, 8 bytes at the time, if
1196 necessary spilling on the stack. */
1200 /* Store return address. */
1201 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1203 /* Update stack pointer. */
1204 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1209 /* Find a function's return value in the appropriate registers (in
1210 regbuf), and copy it into valbuf. Extract from an array REGBUF
1211 containing the (raw) register state a function return value of type
1212 TYPE, and copy that, in virtual format, into VALBUF. */
1214 sh64_extract_return_value (struct type *type, struct regcache *regcache,
1217 int len = TYPE_LENGTH (type);
1219 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1223 /* Return value stored in FP0_REGNUM */
1224 regcache_raw_read (regcache, FP0_REGNUM, valbuf);
1228 /* return value stored in DR0_REGNUM */
1232 regcache_cooked_read (regcache, DR0_REGNUM, buf);
1234 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1235 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1238 floatformat_to_doublest (&floatformat_ieee_double_big,
1240 store_typed_floating (valbuf, type, val);
1249 /* Result is in register 2. If smaller than 8 bytes, it is padded
1250 at the most significant end. */
1251 regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf);
1253 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1254 offset = register_size (current_gdbarch, DEFAULT_RETURN_REGNUM)
1258 memcpy (valbuf, buf + offset, len);
1261 error ("bad size for return value");
1265 /* Write into appropriate registers a function return value
1266 of type TYPE, given in virtual format.
1267 If the architecture is sh4 or sh3e, store a function's return value
1268 in the R0 general register or in the FP0 floating point register,
1269 depending on the type of the return value. In all the other cases
1270 the result is stored in r0, left-justified. */
1273 sh64_store_return_value (struct type *type, struct regcache *regcache,
1276 char buf[64]; /* more than enough... */
1277 int len = TYPE_LENGTH (type);
1279 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1281 int i, regnum = FP0_REGNUM;
1282 for (i = 0; i < len; i += 4)
1283 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1284 regcache_raw_write (regcache, regnum++,
1285 (char *) valbuf + len - 4 - i);
1287 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1291 int return_register = DEFAULT_RETURN_REGNUM;
1294 if (len <= register_size (current_gdbarch, return_register))
1296 /* Pad with zeros. */
1297 memset (buf, 0, register_size (current_gdbarch, return_register));
1298 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
1299 offset = 0; /*register_size (current_gdbarch,
1300 return_register) - len;*/
1302 offset = register_size (current_gdbarch, return_register) - len;
1304 memcpy (buf + offset, valbuf, len);
1305 regcache_raw_write (regcache, return_register, buf);
1308 regcache_raw_write (regcache, return_register, valbuf);
1312 static enum return_value_convention
1313 sh64_return_value (struct gdbarch *gdbarch, struct type *type,
1314 struct regcache *regcache,
1315 gdb_byte *readbuf, const gdb_byte *writebuf)
1317 if (sh64_use_struct_convention (type))
1318 return RETURN_VALUE_STRUCT_CONVENTION;
1320 sh64_store_return_value (type, regcache, writebuf);
1322 sh64_extract_return_value (type, regcache, readbuf);
1323 return RETURN_VALUE_REGISTER_CONVENTION;
1327 sh64_show_media_regs (struct frame_info *frame)
1332 ("PC=%s SR=%016llx \n",
1333 paddr (get_frame_register_unsigned (frame, PC_REGNUM)),
1334 (long long) get_frame_register_unsigned (frame, SR_REGNUM));
1337 ("SSR=%016llx SPC=%016llx \n",
1338 (long long) get_frame_register_unsigned (frame, SSR_REGNUM),
1339 (long long) get_frame_register_unsigned (frame, SPC_REGNUM));
1342 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1344 for (i = 0; i < 64; i = i + 4)
1346 ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1348 (long long) get_frame_register_unsigned (frame, i + 0),
1349 (long long) get_frame_register_unsigned (frame, i + 1),
1350 (long long) get_frame_register_unsigned (frame, i + 2),
1351 (long long) get_frame_register_unsigned (frame, i + 3));
1353 printf_filtered ("\n");
1355 for (i = 0; i < 64; i = i + 8)
1357 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1359 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 0),
1360 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 1),
1361 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 2),
1362 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 3),
1363 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 4),
1364 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 5),
1365 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 6),
1366 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 7));
1370 sh64_show_compact_regs (struct frame_info *frame)
1376 paddr (get_frame_register_unsigned (frame, PC_C_REGNUM)));
1379 ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1380 (long) get_frame_register_unsigned (frame, GBR_C_REGNUM),
1381 (long) get_frame_register_unsigned (frame, MACH_C_REGNUM),
1382 (long) get_frame_register_unsigned (frame, MACL_C_REGNUM),
1383 (long) get_frame_register_unsigned (frame, PR_C_REGNUM),
1384 (long) get_frame_register_unsigned (frame, T_C_REGNUM));
1386 ("FPSCR=%08lx FPUL=%08lx\n",
1387 (long) get_frame_register_unsigned (frame, FPSCR_C_REGNUM),
1388 (long) get_frame_register_unsigned (frame, FPUL_C_REGNUM));
1390 for (i = 0; i < 16; i = i + 4)
1392 ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1394 (long) get_frame_register_unsigned (frame, i + 0),
1395 (long) get_frame_register_unsigned (frame, i + 1),
1396 (long) get_frame_register_unsigned (frame, i + 2),
1397 (long) get_frame_register_unsigned (frame, i + 3));
1399 printf_filtered ("\n");
1401 for (i = 0; i < 16; i = i + 8)
1403 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1405 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 0),
1406 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 1),
1407 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 2),
1408 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 3),
1409 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 4),
1410 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 5),
1411 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 6),
1412 (long) get_frame_register_unsigned (frame, FP0_REGNUM + i + 7));
1415 /* FIXME!!! This only shows the registers for shmedia, excluding the
1416 pseudo registers. */
1418 sh64_show_regs (struct frame_info *frame)
1420 if (pc_is_isa32 (get_frame_pc (frame)))
1421 sh64_show_media_regs (frame);
1423 sh64_show_compact_regs (frame);
1428 SH MEDIA MODE (ISA 32)
1429 general registers (64-bit) 0-63
1430 0 r0, r1, r2, r3, r4, r5, r6, r7,
1431 64 r8, r9, r10, r11, r12, r13, r14, r15,
1432 128 r16, r17, r18, r19, r20, r21, r22, r23,
1433 192 r24, r25, r26, r27, r28, r29, r30, r31,
1434 256 r32, r33, r34, r35, r36, r37, r38, r39,
1435 320 r40, r41, r42, r43, r44, r45, r46, r47,
1436 384 r48, r49, r50, r51, r52, r53, r54, r55,
1437 448 r56, r57, r58, r59, r60, r61, r62, r63,
1442 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1445 target registers (64-bit) 68-75
1446 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1448 floating point state control register (32-bit) 76
1451 single precision floating point registers (32-bit) 77-140
1452 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1453 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1454 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1455 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1456 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1457 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1458 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1459 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1461 TOTAL SPACE FOR REGISTERS: 868 bytes
1463 From here on they are all pseudo registers: no memory allocated.
1464 REGISTER_BYTE returns the register byte for the base register.
1466 double precision registers (pseudo) 141-172
1467 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1468 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1469 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1470 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1472 floating point pairs (pseudo) 173-204
1473 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1474 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1475 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1476 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1478 floating point vectors (4 floating point regs) (pseudo) 205-220
1479 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1480 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1482 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1483 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1484 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1486 gbr_c, mach_c, macl_c, pr_c, t_c,
1488 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1489 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1490 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1491 fv0_c, fv4_c, fv8_c, fv12_c
1494 static struct type *
1495 sh64_build_float_register_type (int high)
1499 temp = create_range_type (NULL, builtin_type_int, 0, high);
1500 return create_array_type (NULL, builtin_type_float, temp);
1503 /* Return the GDB type object for the "standard" data type
1504 of data in register REG_NR. */
1505 static struct type *
1506 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
1508 if ((reg_nr >= FP0_REGNUM
1509 && reg_nr <= FP_LAST_REGNUM)
1510 || (reg_nr >= FP0_C_REGNUM
1511 && reg_nr <= FP_LAST_C_REGNUM))
1512 return builtin_type_float;
1513 else if ((reg_nr >= DR0_REGNUM
1514 && reg_nr <= DR_LAST_REGNUM)
1515 || (reg_nr >= DR0_C_REGNUM
1516 && reg_nr <= DR_LAST_C_REGNUM))
1517 return builtin_type_double;
1518 else if (reg_nr >= FPP0_REGNUM
1519 && reg_nr <= FPP_LAST_REGNUM)
1520 return sh64_build_float_register_type (1);
1521 else if ((reg_nr >= FV0_REGNUM
1522 && reg_nr <= FV_LAST_REGNUM)
1523 ||(reg_nr >= FV0_C_REGNUM
1524 && reg_nr <= FV_LAST_C_REGNUM))
1525 return sh64_build_float_register_type (3);
1526 else if (reg_nr == FPSCR_REGNUM)
1527 return builtin_type_int;
1528 else if (reg_nr >= R0_C_REGNUM
1529 && reg_nr < FP0_C_REGNUM)
1530 return builtin_type_int;
1532 return builtin_type_long_long;
1536 sh64_register_convert_to_virtual (int regnum, struct type *type,
1537 char *from, char *to)
1539 if (gdbarch_byte_order (current_gdbarch) != BFD_ENDIAN_LITTLE)
1541 /* It is a no-op. */
1542 memcpy (to, from, register_size (current_gdbarch, regnum));
1546 if ((regnum >= DR0_REGNUM
1547 && regnum <= DR_LAST_REGNUM)
1548 || (regnum >= DR0_C_REGNUM
1549 && regnum <= DR_LAST_C_REGNUM))
1552 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1554 store_typed_floating (to, type, val);
1557 error ("sh64_register_convert_to_virtual called with non DR register number");
1561 sh64_register_convert_to_raw (struct type *type, int regnum,
1562 const void *from, void *to)
1564 if (gdbarch_byte_order (current_gdbarch) != BFD_ENDIAN_LITTLE)
1566 /* It is a no-op. */
1567 memcpy (to, from, register_size (current_gdbarch, regnum));
1571 if ((regnum >= DR0_REGNUM
1572 && regnum <= DR_LAST_REGNUM)
1573 || (regnum >= DR0_C_REGNUM
1574 && regnum <= DR_LAST_C_REGNUM))
1576 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
1577 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1581 error ("sh64_register_convert_to_raw called with non DR register number");
1585 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1586 int reg_nr, gdb_byte *buffer)
1591 char temp_buffer[MAX_REGISTER_SIZE];
1593 if (reg_nr >= DR0_REGNUM
1594 && reg_nr <= DR_LAST_REGNUM)
1596 base_regnum = sh64_dr_reg_base_num (reg_nr);
1598 /* Build the value in the provided buffer. */
1599 /* DR regs are double precision registers obtained by
1600 concatenating 2 single precision floating point registers. */
1601 for (portion = 0; portion < 2; portion++)
1602 regcache_raw_read (regcache, base_regnum + portion,
1604 + register_size (gdbarch, base_regnum) * portion));
1606 /* We must pay attention to the endianness. */
1607 sh64_register_convert_to_virtual (reg_nr,
1608 register_type (gdbarch, reg_nr),
1609 temp_buffer, buffer);
1613 else if (reg_nr >= FPP0_REGNUM
1614 && reg_nr <= FPP_LAST_REGNUM)
1616 base_regnum = sh64_fpp_reg_base_num (reg_nr);
1618 /* Build the value in the provided buffer. */
1619 /* FPP regs are pairs of single precision registers obtained by
1620 concatenating 2 single precision floating point registers. */
1621 for (portion = 0; portion < 2; portion++)
1622 regcache_raw_read (regcache, base_regnum + portion,
1624 + register_size (gdbarch, base_regnum) * portion));
1627 else if (reg_nr >= FV0_REGNUM
1628 && reg_nr <= FV_LAST_REGNUM)
1630 base_regnum = sh64_fv_reg_base_num (reg_nr);
1632 /* Build the value in the provided buffer. */
1633 /* FV regs are vectors of single precision registers obtained by
1634 concatenating 4 single precision floating point registers. */
1635 for (portion = 0; portion < 4; portion++)
1636 regcache_raw_read (regcache, base_regnum + portion,
1638 + register_size (gdbarch, base_regnum) * portion));
1641 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
1642 else if (reg_nr >= R0_C_REGNUM
1643 && reg_nr <= T_C_REGNUM)
1645 base_regnum = sh64_compact_reg_base_num (reg_nr);
1647 /* Build the value in the provided buffer. */
1648 regcache_raw_read (regcache, base_regnum, temp_buffer);
1649 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1651 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
1654 else if (reg_nr >= FP0_C_REGNUM
1655 && reg_nr <= FP_LAST_C_REGNUM)
1657 base_regnum = sh64_compact_reg_base_num (reg_nr);
1659 /* Build the value in the provided buffer. */
1660 /* Floating point registers map 1-1 to the media fp regs,
1661 they have the same size and endianness. */
1662 regcache_raw_read (regcache, base_regnum, buffer);
1665 else if (reg_nr >= DR0_C_REGNUM
1666 && reg_nr <= DR_LAST_C_REGNUM)
1668 base_regnum = sh64_compact_reg_base_num (reg_nr);
1670 /* DR_C regs are double precision registers obtained by
1671 concatenating 2 single precision floating point registers. */
1672 for (portion = 0; portion < 2; portion++)
1673 regcache_raw_read (regcache, base_regnum + portion,
1675 + register_size (gdbarch, base_regnum) * portion));
1677 /* We must pay attention to the endianness. */
1678 sh64_register_convert_to_virtual (reg_nr,
1679 register_type (gdbarch, reg_nr),
1680 temp_buffer, buffer);
1683 else if (reg_nr >= FV0_C_REGNUM
1684 && reg_nr <= FV_LAST_C_REGNUM)
1686 base_regnum = sh64_compact_reg_base_num (reg_nr);
1688 /* Build the value in the provided buffer. */
1689 /* FV_C regs are vectors of single precision registers obtained by
1690 concatenating 4 single precision floating point registers. */
1691 for (portion = 0; portion < 4; portion++)
1692 regcache_raw_read (regcache, base_regnum + portion,
1694 + register_size (gdbarch, base_regnum) * portion));
1697 else if (reg_nr == FPSCR_C_REGNUM)
1699 int fpscr_base_regnum;
1701 unsigned int fpscr_value;
1702 unsigned int sr_value;
1703 unsigned int fpscr_c_value;
1704 unsigned int fpscr_c_part1_value;
1705 unsigned int fpscr_c_part2_value;
1707 fpscr_base_regnum = FPSCR_REGNUM;
1708 sr_base_regnum = SR_REGNUM;
1710 /* Build the value in the provided buffer. */
1711 /* FPSCR_C is a very weird register that contains sparse bits
1712 from the FPSCR and the SR architectural registers.
1719 2-17 Bit 2-18 of FPSCR
1720 18-20 Bits 12,13,14 of SR
1724 /* Get FPSCR into a local buffer */
1725 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1726 /* Get value as an int. */
1727 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
1728 /* Get SR into a local buffer */
1729 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1730 /* Get value as an int. */
1731 sr_value = extract_unsigned_integer (temp_buffer, 4);
1732 /* Build the new value. */
1733 fpscr_c_part1_value = fpscr_value & 0x3fffd;
1734 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
1735 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
1736 /* Store that in out buffer!!! */
1737 store_unsigned_integer (buffer, 4, fpscr_c_value);
1738 /* FIXME There is surely an endianness gotcha here. */
1741 else if (reg_nr == FPUL_C_REGNUM)
1743 base_regnum = sh64_compact_reg_base_num (reg_nr);
1745 /* FPUL_C register is floating point register 32,
1746 same size, same endianness. */
1747 regcache_raw_read (regcache, base_regnum, buffer);
1752 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1753 int reg_nr, const gdb_byte *buffer)
1755 int base_regnum, portion;
1757 char temp_buffer[MAX_REGISTER_SIZE];
1759 if (reg_nr >= DR0_REGNUM
1760 && reg_nr <= DR_LAST_REGNUM)
1762 base_regnum = sh64_dr_reg_base_num (reg_nr);
1763 /* We must pay attention to the endianness. */
1764 sh64_register_convert_to_raw (register_type (gdbarch, reg_nr),
1766 buffer, temp_buffer);
1768 /* Write the real regs for which this one is an alias. */
1769 for (portion = 0; portion < 2; portion++)
1770 regcache_raw_write (regcache, base_regnum + portion,
1772 + register_size (gdbarch,
1773 base_regnum) * portion));
1776 else if (reg_nr >= FPP0_REGNUM
1777 && reg_nr <= FPP_LAST_REGNUM)
1779 base_regnum = sh64_fpp_reg_base_num (reg_nr);
1781 /* Write the real regs for which this one is an alias. */
1782 for (portion = 0; portion < 2; portion++)
1783 regcache_raw_write (regcache, base_regnum + portion,
1785 + register_size (gdbarch,
1786 base_regnum) * portion));
1789 else if (reg_nr >= FV0_REGNUM
1790 && reg_nr <= FV_LAST_REGNUM)
1792 base_regnum = sh64_fv_reg_base_num (reg_nr);
1794 /* Write the real regs for which this one is an alias. */
1795 for (portion = 0; portion < 4; portion++)
1796 regcache_raw_write (regcache, base_regnum + portion,
1798 + register_size (gdbarch,
1799 base_regnum) * portion));
1802 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1803 register but only 4 bytes of it. */
1804 else if (reg_nr >= R0_C_REGNUM
1805 && reg_nr <= T_C_REGNUM)
1807 base_regnum = sh64_compact_reg_base_num (reg_nr);
1808 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1809 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
1813 /* Let's read the value of the base register into a temporary
1814 buffer, so that overwriting the last four bytes with the new
1815 value of the pseudo will leave the upper 4 bytes unchanged. */
1816 regcache_raw_read (regcache, base_regnum, temp_buffer);
1817 /* Write as an 8 byte quantity */
1818 memcpy (temp_buffer + offset, buffer, 4);
1819 regcache_raw_write (regcache, base_regnum, temp_buffer);
1822 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1823 registers. Both are 4 bytes. */
1824 else if (reg_nr >= FP0_C_REGNUM
1825 && reg_nr <= FP_LAST_C_REGNUM)
1827 base_regnum = sh64_compact_reg_base_num (reg_nr);
1828 regcache_raw_write (regcache, base_regnum, buffer);
1831 else if (reg_nr >= DR0_C_REGNUM
1832 && reg_nr <= DR_LAST_C_REGNUM)
1834 base_regnum = sh64_compact_reg_base_num (reg_nr);
1835 for (portion = 0; portion < 2; portion++)
1837 /* We must pay attention to the endianness. */
1838 sh64_register_convert_to_raw (register_type (gdbarch, reg_nr),
1840 buffer, temp_buffer);
1842 regcache_raw_write (regcache, base_regnum + portion,
1844 + register_size (gdbarch,
1845 base_regnum) * portion));
1849 else if (reg_nr >= FV0_C_REGNUM
1850 && reg_nr <= FV_LAST_C_REGNUM)
1852 base_regnum = sh64_compact_reg_base_num (reg_nr);
1854 for (portion = 0; portion < 4; portion++)
1856 regcache_raw_write (regcache, base_regnum + portion,
1858 + register_size (gdbarch,
1859 base_regnum) * portion));
1863 else if (reg_nr == FPSCR_C_REGNUM)
1865 int fpscr_base_regnum;
1867 unsigned int fpscr_value;
1868 unsigned int sr_value;
1869 unsigned int old_fpscr_value;
1870 unsigned int old_sr_value;
1871 unsigned int fpscr_c_value;
1872 unsigned int fpscr_mask;
1873 unsigned int sr_mask;
1875 fpscr_base_regnum = FPSCR_REGNUM;
1876 sr_base_regnum = SR_REGNUM;
1878 /* FPSCR_C is a very weird register that contains sparse bits
1879 from the FPSCR and the SR architectural registers.
1886 2-17 Bit 2-18 of FPSCR
1887 18-20 Bits 12,13,14 of SR
1891 /* Get value as an int. */
1892 fpscr_c_value = extract_unsigned_integer (buffer, 4);
1894 /* Build the new values. */
1895 fpscr_mask = 0x0003fffd;
1896 sr_mask = 0x001c0000;
1898 fpscr_value = fpscr_c_value & fpscr_mask;
1899 sr_value = (fpscr_value & sr_mask) >> 6;
1901 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1902 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
1903 old_fpscr_value &= 0xfffc0002;
1904 fpscr_value |= old_fpscr_value;
1905 store_unsigned_integer (temp_buffer, 4, fpscr_value);
1906 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
1908 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1909 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
1910 old_sr_value &= 0xffff8fff;
1911 sr_value |= old_sr_value;
1912 store_unsigned_integer (temp_buffer, 4, sr_value);
1913 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
1916 else if (reg_nr == FPUL_C_REGNUM)
1918 base_regnum = sh64_compact_reg_base_num (reg_nr);
1919 regcache_raw_write (regcache, base_regnum, buffer);
1923 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1924 shmedia REGISTERS. */
1925 /* Control registers, compact mode. */
1927 sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame,
1930 switch (cr_c_regnum)
1933 fprintf_filtered (file, "pc_c\t0x%08x\n",
1934 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1937 fprintf_filtered (file, "gbr_c\t0x%08x\n",
1938 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1941 fprintf_filtered (file, "mach_c\t0x%08x\n",
1942 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1945 fprintf_filtered (file, "macl_c\t0x%08x\n",
1946 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1949 fprintf_filtered (file, "pr_c\t0x%08x\n",
1950 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1953 fprintf_filtered (file, "t_c\t0x%08x\n",
1954 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1956 case FPSCR_C_REGNUM:
1957 fprintf_filtered (file, "fpscr_c\t0x%08x\n",
1958 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1961 fprintf_filtered (file, "fpul_c\t0x%08x\n",
1962 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1968 sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file,
1969 struct frame_info *frame, int regnum)
1970 { /* do values for FP (float) regs */
1971 unsigned char *raw_buffer;
1972 double flt; /* double extracted from raw hex data */
1976 /* Allocate space for the float. */
1977 raw_buffer = (unsigned char *) alloca (register_size (gdbarch, FP0_REGNUM));
1979 /* Get the data in raw format. */
1980 if (!frame_register_read (frame, regnum, raw_buffer))
1981 error ("can't read register %d (%s)",
1982 regnum, gdbarch_register_name (current_gdbarch, regnum));
1984 /* Get the register as a number */
1985 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1987 /* Print the name and some spaces. */
1988 fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file);
1989 print_spaces_filtered (15 - strlen (gdbarch_register_name
1990 (current_gdbarch, regnum)), file);
1992 /* Print the value. */
1994 fprintf_filtered (file, "<invalid float>");
1996 fprintf_filtered (file, "%-10.9g", flt);
1998 /* Print the fp register as hex. */
1999 fprintf_filtered (file, "\t(raw 0x");
2000 for (j = 0; j < register_size (gdbarch, regnum); j++)
2002 int idx = gdbarch_byte_order (current_gdbarch)
2003 == BFD_ENDIAN_BIG ? j : register_size
2004 (gdbarch, regnum) - 1 - j;
2005 fprintf_filtered (file, "%02x", raw_buffer[idx]);
2007 fprintf_filtered (file, ")");
2008 fprintf_filtered (file, "\n");
2012 sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
2013 struct frame_info *frame, int regnum)
2015 /* All the sh64-compact mode registers are pseudo registers. */
2017 if (regnum < gdbarch_num_regs (current_gdbarch)
2018 || regnum >= gdbarch_num_regs (current_gdbarch)
2019 + NUM_PSEUDO_REGS_SH_MEDIA
2020 + NUM_PSEUDO_REGS_SH_COMPACT)
2021 internal_error (__FILE__, __LINE__,
2022 _("Invalid pseudo register number %d\n"), regnum);
2024 else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM))
2026 int fp_regnum = sh64_dr_reg_base_num (regnum);
2027 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM,
2028 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2029 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2032 else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM))
2034 int fp_regnum = sh64_compact_reg_base_num (regnum);
2035 fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM,
2036 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2037 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2040 else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM))
2042 int fp_regnum = sh64_fv_reg_base_num (regnum);
2043 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2044 regnum - FV0_REGNUM,
2045 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2046 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2047 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2048 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2051 else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM))
2053 int fp_regnum = sh64_compact_reg_base_num (regnum);
2054 fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2055 regnum - FV0_C_REGNUM,
2056 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2057 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2058 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2059 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2062 else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM)
2064 int fp_regnum = sh64_fpp_reg_base_num (regnum);
2065 fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM,
2066 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2067 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2070 else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM)
2072 int c_regnum = sh64_compact_reg_base_num (regnum);
2073 fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM,
2074 (unsigned) get_frame_register_unsigned (frame, c_regnum));
2076 else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM)
2077 /* This should work also for pseudoregs. */
2078 sh64_do_fp_register (gdbarch, file, frame, regnum);
2079 else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM)
2080 sh64_do_cr_c_register_info (file, frame, regnum);
2084 sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file,
2085 struct frame_info *frame, int regnum)
2087 unsigned char raw_buffer[MAX_REGISTER_SIZE];
2089 fputs_filtered (gdbarch_register_name (current_gdbarch, regnum), file);
2090 print_spaces_filtered (15 - strlen (gdbarch_register_name
2091 (current_gdbarch, regnum)), file);
2093 /* Get the data in raw format. */
2094 if (!frame_register_read (frame, regnum, raw_buffer))
2095 fprintf_filtered (file, "*value not available*\n");
2097 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2098 file, 'x', 1, 0, Val_pretty_default);
2099 fprintf_filtered (file, "\t");
2100 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2101 file, 0, 1, 0, Val_pretty_default);
2102 fprintf_filtered (file, "\n");
2106 sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file,
2107 struct frame_info *frame, int regnum)
2109 if (regnum < 0 || regnum >= gdbarch_num_regs (current_gdbarch)
2110 + gdbarch_num_pseudo_regs (current_gdbarch))
2111 internal_error (__FILE__, __LINE__,
2112 _("Invalid register number %d\n"), regnum);
2114 else if (regnum >= 0 && regnum < gdbarch_num_regs (current_gdbarch))
2116 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2117 sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */
2119 sh64_do_register (gdbarch, file, frame, regnum);
2122 else if (regnum < gdbarch_num_regs (current_gdbarch)
2123 + gdbarch_num_pseudo_regs (current_gdbarch))
2124 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2128 sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2129 struct frame_info *frame, int regnum,
2132 if (regnum != -1) /* do one specified register */
2134 if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0')
2135 error ("Not a valid register for the current processor type");
2137 sh64_print_register (gdbarch, file, frame, regnum);
2140 /* do all (or most) registers */
2143 while (regnum < gdbarch_num_regs (current_gdbarch))
2145 /* If the register name is empty, it is undefined for this
2146 processor, so don't display anything. */
2147 if (gdbarch_register_name (current_gdbarch, regnum) == NULL
2148 || *(gdbarch_register_name (current_gdbarch, regnum)) == '\0')
2154 if (TYPE_CODE (register_type (gdbarch, regnum))
2159 /* true for "INFO ALL-REGISTERS" command */
2160 sh64_do_fp_register (gdbarch, file, frame, regnum);
2164 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2168 sh64_do_register (gdbarch, file, frame, regnum);
2174 while (regnum < gdbarch_num_regs (current_gdbarch)
2175 + gdbarch_num_pseudo_regs (current_gdbarch))
2177 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2184 sh64_compact_print_registers_info (struct gdbarch *gdbarch,
2185 struct ui_file *file,
2186 struct frame_info *frame, int regnum,
2189 if (regnum != -1) /* do one specified register */
2191 if (*(gdbarch_register_name (current_gdbarch, regnum)) == '\0')
2192 error ("Not a valid register for the current processor type");
2194 if (regnum >= 0 && regnum < R0_C_REGNUM)
2195 error ("Not a valid register for the current processor mode.");
2197 sh64_print_register (gdbarch, file, frame, regnum);
2200 /* do all compact registers */
2202 regnum = R0_C_REGNUM;
2203 while (regnum < gdbarch_num_regs (current_gdbarch)
2204 + gdbarch_num_pseudo_regs (current_gdbarch))
2206 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2213 sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2214 struct frame_info *frame, int regnum, int fpregs)
2216 if (pc_is_isa32 (get_frame_pc (frame)))
2217 sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2219 sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2222 static struct sh64_frame_cache *
2223 sh64_alloc_frame_cache (void)
2225 struct sh64_frame_cache *cache;
2228 cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache);
2232 cache->saved_sp = 0;
2233 cache->sp_offset = 0;
2236 /* Frameless until proven otherwise. */
2239 /* Saved registers. We initialize these to -1 since zero is a valid
2240 offset (that's where fp is supposed to be stored). */
2241 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2243 cache->saved_regs[i] = -1;
2249 static struct sh64_frame_cache *
2250 sh64_frame_cache (struct frame_info *next_frame, void **this_cache)
2252 struct sh64_frame_cache *cache;
2253 CORE_ADDR current_pc;
2259 cache = sh64_alloc_frame_cache ();
2260 *this_cache = cache;
2262 current_pc = frame_pc_unwind (next_frame);
2263 cache->media_mode = pc_is_isa32 (current_pc);
2265 /* In principle, for normal frames, fp holds the frame pointer,
2266 which holds the base address for the current stack frame.
2267 However, for functions that don't need it, the frame pointer is
2268 optional. For these "frameless" functions the frame pointer is
2269 actually the frame pointer of the calling frame. */
2270 cache->base = frame_unwind_register_unsigned (next_frame, MEDIA_FP_REGNUM);
2271 if (cache->base == 0)
2274 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME);
2276 sh64_analyze_prologue (current_gdbarch, cache, cache->pc, current_pc);
2278 if (!cache->uses_fp)
2280 /* We didn't find a valid frame, which means that CACHE->base
2281 currently holds the frame pointer for our calling frame. If
2282 we're at the start of a function, or somewhere half-way its
2283 prologue, the function's frame probably hasn't been fully
2284 setup yet. Try to reconstruct the base address for the stack
2285 frame by looking at the stack pointer. For truly "frameless"
2286 functions this might work too. */
2287 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2290 /* Now that we have the base address for the stack frame we can
2291 calculate the value of sp in the calling frame. */
2292 cache->saved_sp = cache->base + cache->sp_offset;
2294 /* Adjust all the saved registers such that they contain addresses
2295 instead of offsets. */
2296 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2297 if (cache->saved_regs[i] != -1)
2298 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i];
2304 sh64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2305 int regnum, int *optimizedp,
2306 enum lval_type *lvalp, CORE_ADDR *addrp,
2307 int *realnump, gdb_byte *valuep)
2309 struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache);
2311 gdb_assert (regnum >= 0);
2313 if (regnum == SP_REGNUM && cache->saved_sp)
2321 /* Store the value. */
2322 store_unsigned_integer (valuep,
2323 register_size (current_gdbarch, SP_REGNUM),
2329 /* The PC of the previous frame is stored in the PR register of
2330 the current frame. Frob regnum so that we pull the value from
2331 the correct place. */
2332 if (regnum == PC_REGNUM)
2335 if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1)
2337 int reg_size = register_size (current_gdbarch, regnum);
2341 *lvalp = lval_memory;
2342 *addrp = cache->saved_regs[regnum];
2344 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32
2345 && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM))
2351 memset (valuep, 0, reg_size);
2352 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_LITTLE)
2353 read_memory (*addrp, valuep, size);
2355 read_memory (*addrp, (char *) valuep + reg_size - size, size);
2361 *lvalp = lval_register;
2365 frame_unwind_register (next_frame, (*realnump), valuep);
2369 sh64_frame_this_id (struct frame_info *next_frame, void **this_cache,
2370 struct frame_id *this_id)
2372 struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache);
2374 /* This marks the outermost frame. */
2375 if (cache->base == 0)
2378 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2381 static const struct frame_unwind sh64_frame_unwind = {
2384 sh64_frame_prev_register
2387 static const struct frame_unwind *
2388 sh64_frame_sniffer (struct frame_info *next_frame)
2390 return &sh64_frame_unwind;
2394 sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2396 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2400 sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2402 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2405 static struct frame_id
2406 sh64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2408 return frame_id_build (sh64_unwind_sp (gdbarch, next_frame),
2409 frame_pc_unwind (next_frame));
2413 sh64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2415 struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache);
2420 static const struct frame_base sh64_frame_base = {
2422 sh64_frame_base_address,
2423 sh64_frame_base_address,
2424 sh64_frame_base_address
2429 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2431 struct gdbarch *gdbarch;
2432 struct gdbarch_tdep *tdep;
2434 /* If there is already a candidate, use it. */
2435 arches = gdbarch_list_lookup_by_info (arches, &info);
2437 return arches->gdbarch;
2439 /* None found, create a new architecture from the information
2441 tdep = XMALLOC (struct gdbarch_tdep);
2442 gdbarch = gdbarch_alloc (&info, tdep);
2444 /* Determine the ABI */
2445 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2447 /* If the ABI is the 64-bit one, it can only be sh-media. */
2448 tdep->sh_abi = SH_ABI_64;
2449 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2450 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2454 /* If the ABI is the 32-bit one it could be either media or
2456 tdep->sh_abi = SH_ABI_32;
2457 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2458 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2461 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2462 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2463 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2464 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2465 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2466 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2467 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2469 /* The number of real registers is the same whether we are in
2470 ISA16(compact) or ISA32(media). */
2471 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2472 set_gdbarch_sp_regnum (gdbarch, 15);
2473 set_gdbarch_pc_regnum (gdbarch, 64);
2474 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2475 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA
2476 + NUM_PSEUDO_REGS_SH_COMPACT);
2478 set_gdbarch_register_name (gdbarch, sh64_register_name);
2479 set_gdbarch_register_type (gdbarch, sh64_register_type);
2481 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2482 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2484 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
2486 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh64);
2487 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2489 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2491 set_gdbarch_return_value (gdbarch, sh64_return_value);
2492 set_gdbarch_deprecated_extract_struct_value_address (gdbarch,
2493 sh64_extract_struct_value_address);
2495 set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue);
2496 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2498 set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call);
2500 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2502 set_gdbarch_frame_align (gdbarch, sh64_frame_align);
2503 set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp);
2504 set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc);
2505 set_gdbarch_unwind_dummy_id (gdbarch, sh64_unwind_dummy_id);
2506 frame_base_set_default (gdbarch, &sh64_frame_base);
2508 set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info);
2510 set_gdbarch_elf_make_msymbol_special (gdbarch,
2511 sh64_elf_make_msymbol_special);
2513 /* Hook in ABI-specific overrides, if they have been registered. */
2514 gdbarch_init_osabi (info, gdbarch);
2516 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2517 frame_unwind_append_sniffer (gdbarch, sh64_frame_sniffer);