1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
4 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 Contributed by Steve Chamberlain
30 #include "frame-base.h"
31 #include "frame-unwind.h"
32 #include "dwarf2-frame.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
50 /* registers numbers shared with the simulator */
51 #include "gdb/sim-sh.h"
53 /* Information that is dependent on the processor variant. */
66 struct sh64_frame_cache
73 /* Flag showing that a frame has been created in the prologue code. */
78 /* Saved registers. */
79 CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
83 /* Registers of SH5 */
87 DEFAULT_RETURN_REGNUM = 2,
88 STRUCT_RETURN_REGNUM = 2,
91 FLOAT_ARGLAST_REGNUM = 11,
97 /* FPP stands for Floating Point Pair, to avoid confusion with
98 GDB's FP0_REGNUM, which is the number of the first Floating
99 point register. Unfortunately on the sh5, the floating point
100 registers are called FR, and the floating point pairs are called FP. */
102 FPP_LAST_REGNUM = 204,
104 FV_LAST_REGNUM = 220,
106 R_LAST_C_REGNUM = 236,
113 FPSCR_C_REGNUM = 243,
116 FP_LAST_C_REGNUM = 260,
118 DR_LAST_C_REGNUM = 268,
120 FV_LAST_C_REGNUM = 272,
121 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
122 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
123 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
124 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
125 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
129 sh64_register_name (int reg_nr)
131 static char *register_names[] =
133 /* SH MEDIA MODE (ISA 32) */
134 /* general registers (64-bit) 0-63 */
135 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
136 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
137 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
138 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
139 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
140 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
141 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
142 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
147 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
150 /* target registers (64-bit) 68-75*/
151 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
153 /* floating point state control register (32-bit) 76 */
156 /* single precision floating point registers (32-bit) 77-140*/
157 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
158 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
159 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
160 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
161 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
162 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
163 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
164 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
166 /* double precision registers (pseudo) 141-172 */
167 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
168 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
169 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
170 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
172 /* floating point pairs (pseudo) 173-204*/
173 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
174 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
175 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
176 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
178 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
179 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
180 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
182 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
183 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
184 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
186 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
188 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
189 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
190 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
191 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
192 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return register_names[reg_nr];
202 #define NUM_PSEUDO_REGS_SH_MEDIA 80
203 #define NUM_PSEUDO_REGS_SH_COMPACT 51
205 /* Macros and functions for setting and testing a bit in a minimal
206 symbol that marks it as 32-bit function. The MSB of the minimal
207 symbol's "info" field is used for this purpose.
209 ELF_MAKE_MSYMBOL_SPECIAL
210 tests whether an ELF symbol is "special", i.e. refers
211 to a 32-bit function, and sets a "special" bit in a
212 minimal symbol to mark it as a 32-bit function
213 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
215 #define MSYMBOL_IS_SPECIAL(msym) \
216 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
219 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
224 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
226 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
227 SYMBOL_VALUE_ADDRESS (msym) |= 1;
231 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
232 are some macros to test, set, or clear bit 0 of addresses. */
233 #define IS_ISA32_ADDR(addr) ((addr) & 1)
234 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
235 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
238 pc_is_isa32 (bfd_vma memaddr)
240 struct minimal_symbol *sym;
242 /* If bit 0 of the address is set, assume this is a
243 ISA32 (shmedia) address. */
244 if (IS_ISA32_ADDR (memaddr))
247 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
248 the high bit of the info field. Use this to decide if the function is
250 sym = lookup_minimal_symbol_by_pc (memaddr);
252 return MSYMBOL_IS_SPECIAL (sym);
257 static const unsigned char *
258 sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
260 /* The BRK instruction for shmedia is
261 01101111 11110101 11111111 11110000
262 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
263 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
265 /* The BRK instruction for shcompact is
267 which translates in big endian mode to 0x0, 0x3b
268 and in little endian mode to 0x3b, 0x0*/
270 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
272 if (pc_is_isa32 (*pcptr))
274 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
275 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
276 *lenptr = sizeof (big_breakpoint_media);
277 return big_breakpoint_media;
281 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
282 *lenptr = sizeof (big_breakpoint_compact);
283 return big_breakpoint_compact;
288 if (pc_is_isa32 (*pcptr))
290 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
291 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
292 *lenptr = sizeof (little_breakpoint_media);
293 return little_breakpoint_media;
297 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
298 *lenptr = sizeof (little_breakpoint_compact);
299 return little_breakpoint_compact;
304 /* Prologue looks like
305 [mov.l <regs>,@-r15]...
310 Actually it can be more complicated than this. For instance, with
328 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
329 with l=1 and n = 18 0110101111110001010010100aaa0000 */
330 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
332 /* STS.L PR,@-r0 0100000000100010
333 r0-4-->r0, PR-->(r0) */
334 #define IS_STS_R0(x) ((x) == 0x4022)
336 /* STS PR, Rm 0000mmmm00101010
338 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
340 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
342 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
344 /* MOV.L R14,@(disp,r15) 000111111110dddd
345 R14-->(dispx4+r15) */
346 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
348 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
349 R18-->(dispx8+R14) */
350 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
352 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
353 R18-->(dispx8+R15) */
354 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
356 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
357 R18-->(dispx4+R15) */
358 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
360 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
361 R14-->(dispx8+R15) */
362 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
364 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
365 R14-->(dispx4+R15) */
366 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
368 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
370 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
372 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
374 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
376 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
378 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
380 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
382 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
384 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
386 /* MOV #imm, R0 1110 0000 ssss ssss
388 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
390 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
391 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
393 /* ADD r15,r0 0011 0000 1111 1100
395 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
397 /* MOV.L R14 @-R0 0010 0000 1110 0110
398 R14-->(R0-4), R0-4-->R0 */
399 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
401 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
402 where Rm is one of r2-r9 which are the argument registers. */
403 /* FIXME: Recognize the float and double register moves too! */
404 #define IS_MEDIA_IND_ARG_MOV(x) \
405 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
407 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
408 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
409 where Rm is one of r2-r9 which are the argument registers. */
410 #define IS_MEDIA_ARG_MOV(x) \
411 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
412 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
414 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
415 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
416 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
417 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
418 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
419 #define IS_MEDIA_MOV_TO_R14(x) \
420 ((((x) & 0xfffffc0f) == 0xa0e00000) \
421 || (((x) & 0xfffffc0f) == 0xa4e00000) \
422 || (((x) & 0xfffffc0f) == 0xa8e00000) \
423 || (((x) & 0xfffffc0f) == 0xb4e00000) \
424 || (((x) & 0xfffffc0f) == 0xbce00000))
426 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
428 #define IS_COMPACT_IND_ARG_MOV(x) \
429 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
431 /* compact direct arg move!
432 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
433 #define IS_COMPACT_ARG_MOV(x) \
434 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
436 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
437 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
438 #define IS_COMPACT_MOV_TO_R14(x) \
439 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
441 #define IS_JSR_R0(x) ((x) == 0x400b)
442 #define IS_NOP(x) ((x) == 0x0009)
445 /* MOV r15,r14 0110111011110011
447 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
449 /* ADD #imm,r15 01111111iiiiiiii
451 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
453 /* Skip any prologue before the guts of a function */
455 /* Skip the prologue using the debug information. If this fails we'll
456 fall back on the 'guess' method below. */
458 after_prologue (CORE_ADDR pc)
460 struct symtab_and_line sal;
461 CORE_ADDR func_addr, func_end;
463 /* If we can not find the symbol in the partial symbol table, then
464 there is no hope we can determine the function's start address
466 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
470 /* Get the line associated with FUNC_ADDR. */
471 sal = find_pc_line (func_addr, 0);
473 /* There are only two cases to consider. First, the end of the source line
474 is within the function bounds. In that case we return the end of the
475 source line. Second is the end of the source line extends beyond the
476 bounds of the current function. We need to use the slow code to
477 examine instructions in that case. */
478 if (sal.end < func_end)
485 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
489 int insn_size = (media_mode ? 4 : 2);
491 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
495 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
497 if (IS_MEDIA_IND_ARG_MOV (w))
499 /* This must be followed by a store to r14, so the argument
500 is where the debug info says it is. This can happen after
501 the SP has been saved, unfortunately. */
503 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
506 if (IS_MEDIA_MOV_TO_R14 (next_insn))
509 else if (IS_MEDIA_ARG_MOV (w))
511 /* These instructions store directly the argument in r14. */
519 w = read_memory_integer (here, insn_size);
522 if (IS_COMPACT_IND_ARG_MOV (w))
524 /* This must be followed by a store to r14, so the argument
525 is where the debug info says it is. This can happen after
526 the SP has been saved, unfortunately. */
528 int next_insn = 0xffff & read_memory_integer (here, insn_size);
530 if (IS_COMPACT_MOV_TO_R14 (next_insn))
533 else if (IS_COMPACT_ARG_MOV (w))
535 /* These instructions store directly the argument in r14. */
538 else if (IS_MOVL_R0 (w))
540 /* There is a function that gcc calls to get the arguments
541 passed correctly to the function. Only after this
542 function call the arguments will be found at the place
543 where they are supposed to be. This happens in case the
544 argument has to be stored into a 64-bit register (for
545 instance doubles, long longs). SHcompact doesn't have
546 access to the full 64-bits, so we store the register in
547 stack slot and store the address of the stack slot in
548 the register, then do a call through a wrapper that
549 loads the memory value into the register. A SHcompact
550 callee calls an argument decoder
551 (GCC_shcompact_incoming_args) that stores the 64-bit
552 value in a stack slot and stores the address of the
553 stack slot in the register. GCC thinks the argument is
554 just passed by transparent reference, but this is only
555 true after the argument decoder is called. Such a call
556 needs to be considered part of the prologue. */
558 /* This must be followed by a JSR @r0 instruction and by
559 a NOP instruction. After these, the prologue is over! */
561 int next_insn = 0xffff & read_memory_integer (here, insn_size);
563 if (IS_JSR_R0 (next_insn))
565 next_insn = 0xffff & read_memory_integer (here, insn_size);
568 if (IS_NOP (next_insn))
581 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
591 if (pc_is_isa32 (start_pc) == 0)
597 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
602 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
604 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
605 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
606 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
610 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
618 /* Don't bail out yet, we may have arguments stored in
619 registers here, according to the debug info, so that
620 gdb can print the frames correctly. */
621 start_pc = look_for_args_moves (here - insn_size, media_mode);
627 int w = 0xffff & read_memory_integer (here, insn_size);
630 if (IS_STS_R0 (w) || IS_STS_PR (w)
631 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
632 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
636 else if (IS_MOV_SP_FP (w))
644 /* Don't bail out yet, we may have arguments stored in
645 registers here, according to the debug info, so that
646 gdb can print the frames correctly. */
647 start_pc = look_for_args_moves (here - insn_size, media_mode);
657 sh64_skip_prologue (CORE_ADDR pc)
659 CORE_ADDR post_prologue_pc;
661 /* See if we can determine the end of the prologue via the symbol table.
662 If so, then return either PC, or the PC after the prologue, whichever
664 post_prologue_pc = after_prologue (pc);
666 /* If after_prologue returned a useful address, then use it. Else
667 fall back on the instruction skipping code. */
668 if (post_prologue_pc != 0)
669 return max (pc, post_prologue_pc);
671 return sh64_skip_prologue_hard_way (pc);
674 /* Should call_function allocate stack space for a struct return? */
676 sh64_use_struct_convention (struct type *type)
678 return (TYPE_LENGTH (type) > 8);
681 /* Disassemble an instruction. */
683 gdb_print_insn_sh64 (bfd_vma memaddr, disassemble_info *info)
685 info->endian = TARGET_BYTE_ORDER;
686 return print_insn_sh (memaddr, info);
689 /* For vectors of 4 floating point registers. */
691 sh64_fv_reg_base_num (int fv_regnum)
695 fp_regnum = FP0_REGNUM +
696 (fv_regnum - FV0_REGNUM) * 4;
700 /* For double precision floating point registers, i.e 2 fp regs.*/
702 sh64_dr_reg_base_num (int dr_regnum)
706 fp_regnum = FP0_REGNUM +
707 (dr_regnum - DR0_REGNUM) * 2;
711 /* For pairs of floating point registers */
713 sh64_fpp_reg_base_num (int fpp_regnum)
717 fp_regnum = FP0_REGNUM +
718 (fpp_regnum - FPP0_REGNUM) * 2;
724 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
725 GDB_REGNUM BASE_REGNUM
785 sh64_compact_reg_base_num (int reg_nr)
787 int base_regnum = reg_nr;
789 /* general register N maps to general register N */
790 if (reg_nr >= R0_C_REGNUM
791 && reg_nr <= R_LAST_C_REGNUM)
792 base_regnum = reg_nr - R0_C_REGNUM;
794 /* floating point register N maps to floating point register N */
795 else if (reg_nr >= FP0_C_REGNUM
796 && reg_nr <= FP_LAST_C_REGNUM)
797 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
799 /* double prec register N maps to base regnum for double prec register N */
800 else if (reg_nr >= DR0_C_REGNUM
801 && reg_nr <= DR_LAST_C_REGNUM)
802 base_regnum = sh64_dr_reg_base_num (DR0_REGNUM + reg_nr - DR0_C_REGNUM);
804 /* vector N maps to base regnum for vector register N */
805 else if (reg_nr >= FV0_C_REGNUM
806 && reg_nr <= FV_LAST_C_REGNUM)
807 base_regnum = sh64_fv_reg_base_num (FV0_REGNUM + reg_nr - FV0_C_REGNUM);
809 else if (reg_nr == PC_C_REGNUM)
810 base_regnum = PC_REGNUM;
812 else if (reg_nr == GBR_C_REGNUM)
815 else if (reg_nr == MACH_C_REGNUM
816 || reg_nr == MACL_C_REGNUM)
819 else if (reg_nr == PR_C_REGNUM)
820 base_regnum = PR_REGNUM;
822 else if (reg_nr == T_C_REGNUM)
825 else if (reg_nr == FPSCR_C_REGNUM)
826 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
828 else if (reg_nr == FPUL_C_REGNUM)
829 base_regnum = FP0_REGNUM + 32;
835 sign_extend (int value, int bits)
837 value = value & ((1 << bits) - 1);
838 return (value & (1 << (bits - 1))
839 ? value | (~((1 << bits) - 1))
844 sh64_analyze_prologue (struct gdbarch *gdbarch,
845 struct sh64_frame_cache *cache,
847 CORE_ADDR current_pc)
855 int gdb_register_number;
857 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
859 cache->sp_offset = 0;
861 /* Loop around examining the prologue insns until we find something
862 that does not appear to be part of the prologue. But give up
863 after 20 of them, since we're getting silly then. */
867 if (cache->media_mode)
872 opc = pc + (insn_size * 28);
873 if (opc > current_pc)
875 for ( ; pc <= opc; pc += insn_size)
877 insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
881 if (!cache->media_mode)
883 if (IS_STS_PR (insn))
885 int next_insn = read_memory_integer (pc + insn_size, insn_size);
886 if (IS_MOV_TO_R15 (next_insn))
888 cache->saved_regs[PR_REGNUM] =
889 cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
894 else if (IS_MOV_R14 (insn))
895 cache->saved_regs[MEDIA_FP_REGNUM] =
896 cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
898 else if (IS_MOV_R0 (insn))
900 /* Put in R0 the offset from SP at which to store some
901 registers. We are interested in this value, because it
902 will tell us where the given registers are stored within
904 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
907 else if (IS_ADD_SP_R0 (insn))
909 /* This instruction still prepares r0, but we don't care.
910 We already have the offset in r0_val. */
913 else if (IS_STS_R0 (insn))
915 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
916 cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
920 else if (IS_MOV_R14_R0 (insn))
922 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
923 cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
928 else if (IS_ADD_SP (insn))
929 cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
931 else if (IS_MOV_SP_FP (insn))
936 if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
938 sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
940 else if (IS_STQ_R18_R15 (insn))
941 cache->saved_regs[PR_REGNUM] =
942 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
944 else if (IS_STL_R18_R15 (insn))
945 cache->saved_regs[PR_REGNUM] =
946 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
948 else if (IS_STQ_R14_R15 (insn))
949 cache->saved_regs[MEDIA_FP_REGNUM] =
950 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
952 else if (IS_STL_R14_R15 (insn))
953 cache->saved_regs[MEDIA_FP_REGNUM] =
954 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
956 else if (IS_MOV_SP_FP_MEDIA (insn))
961 if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0)
966 sh64_extract_struct_value_address (struct regcache *regcache)
968 /* FIXME: cagney/2004-01-17: Does the ABI guarantee that the return
969 address regster is preserved across function calls? Probably
970 not, making this function wrong. */
972 regcache_raw_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &val);
977 sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
982 /* Function: push_dummy_call
983 Setup the function arguments for calling a function in the inferior.
985 On the Renesas SH architecture, there are four registers (R4 to R7)
986 which are dedicated for passing function arguments. Up to the first
987 four arguments (depending on size) may go into these registers.
988 The rest go on the stack.
990 Arguments that are smaller than 4 bytes will still take up a whole
991 register or a whole 32-bit word on the stack, and will be
992 right-justified in the register or the stack word. This includes
993 chars, shorts, and small aggregate types.
995 Arguments that are larger than 4 bytes may be split between two or
996 more registers. If there are not enough registers free, an argument
997 may be passed partly in a register (or registers), and partly on the
998 stack. This includes doubles, long longs, and larger aggregates.
999 As far as I know, there is no upper limit to the size of aggregates
1000 that will be passed in this way; in other words, the convention of
1001 passing a pointer to a large aggregate instead of a copy is not used.
1003 An exceptional case exists for struct arguments (and possibly other
1004 aggregates such as arrays) if the size is larger than 4 bytes but
1005 not a multiple of 4 bytes. In this case the argument is never split
1006 between the registers and the stack, but instead is copied in its
1007 entirety onto the stack, AND also copied into as many registers as
1008 there is room for. In other words, space in registers permitting,
1009 two copies of the same argument are passed in. As far as I can tell,
1010 only the one on the stack is used, although that may be a function
1011 of the level of compiler optimization. I suspect this is a compiler
1012 bug. Arguments of these odd sizes are left-justified within the
1013 word (as opposed to arguments smaller than 4 bytes, which are
1016 If the function is to return an aggregate type such as a struct, it
1017 is either returned in the normal return value register R0 (if its
1018 size is no greater than one byte), or else the caller must allocate
1019 space into which the callee will copy the return value (if the size
1020 is greater than one byte). In this case, a pointer to the return
1021 value location is passed into the callee in register R2, which does
1022 not displace any of the other arguments passed in via registers R4
1025 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1026 non-scalar (struct, union) elements (even if the elements are
1028 FR0-FR11 for single precision floating point (float)
1029 DR0-DR10 for double precision floating point (double)
1031 If a float is argument number 3 (for instance) and arguments number
1032 1,2, and 4 are integer, the mapping will be:
1033 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1035 If a float is argument number 10 (for instance) and arguments number
1036 1 through 10 are integer, the mapping will be:
1037 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1038 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1039 I.e. there is hole in the stack.
1041 Different rules apply for variable arguments functions, and for functions
1042 for which the prototype is not known. */
1045 sh64_push_dummy_call (struct gdbarch *gdbarch,
1046 struct value *function,
1047 struct regcache *regcache,
1049 int nargs, struct value **args,
1050 CORE_ADDR sp, int struct_return,
1051 CORE_ADDR struct_addr)
1053 int stack_offset, stack_alloc;
1057 int float_arg_index = 0;
1058 int double_arg_index = 0;
1069 memset (fp_args, 0, sizeof (fp_args));
1071 /* first force sp to a 8-byte alignment */
1072 sp = sh64_frame_align (gdbarch, sp);
1074 /* The "struct return pointer" pseudo-argument has its own dedicated
1078 regcache_cooked_write_unsigned (regcache,
1079 STRUCT_RETURN_REGNUM, struct_addr);
1081 /* Now make sure there's space on the stack */
1082 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1083 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
1084 sp -= stack_alloc; /* make room on stack for args */
1086 /* Now load as many as possible of the first arguments into
1087 registers, and push the rest onto the stack. There are 64 bytes
1088 in eight registers available. Loop thru args from first to last. */
1090 int_argreg = ARG0_REGNUM;
1091 float_argreg = FP0_REGNUM;
1092 double_argreg = DR0_REGNUM;
1094 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1096 type = value_type (args[argnum]);
1097 len = TYPE_LENGTH (type);
1098 memset (valbuf, 0, sizeof (valbuf));
1100 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1102 argreg_size = register_size (current_gdbarch, int_argreg);
1104 if (len < argreg_size)
1106 /* value gets right-justified in the register or stack word */
1107 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1108 memcpy (valbuf + argreg_size - len,
1109 (char *) value_contents (args[argnum]), len);
1111 memcpy (valbuf, (char *) value_contents (args[argnum]), len);
1116 val = (char *) value_contents (args[argnum]);
1120 if (int_argreg > ARGLAST_REGNUM)
1122 /* must go on the stack */
1123 write_memory (sp + stack_offset, val, argreg_size);
1124 stack_offset += 8;/*argreg_size;*/
1126 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1127 That's because some *&^%$ things get passed on the stack
1128 AND in the registers! */
1129 if (int_argreg <= ARGLAST_REGNUM)
1131 /* there's room in a register */
1132 regval = extract_unsigned_integer (val, argreg_size);
1133 regcache_cooked_write_unsigned (regcache, int_argreg, regval);
1135 /* Store the value 8 bytes at a time. This means that
1136 things larger than 8 bytes may go partly in registers
1137 and partly on the stack. FIXME: argreg is incremented
1138 before we use its size. */
1146 val = (char *) value_contents (args[argnum]);
1149 /* Where is it going to be stored? */
1150 while (fp_args[float_arg_index])
1153 /* Now float_argreg points to the register where it
1154 should be stored. Are we still within the allowed
1156 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1158 /* Goes in FR0...FR11 */
1159 regcache_cooked_write (regcache,
1160 FP0_REGNUM + float_arg_index,
1162 fp_args[float_arg_index] = 1;
1163 /* Skip the corresponding general argument register. */
1168 /* Store it as the integers, 8 bytes at the time, if
1169 necessary spilling on the stack. */
1174 /* Where is it going to be stored? */
1175 while (fp_args[double_arg_index])
1176 double_arg_index += 2;
1177 /* Now double_argreg points to the register
1178 where it should be stored.
1179 Are we still within the allowed register set? */
1180 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1182 /* Goes in DR0...DR10 */
1183 /* The numbering of the DRi registers is consecutive,
1184 i.e. includes odd numbers. */
1185 int double_register_offset = double_arg_index / 2;
1186 int regnum = DR0_REGNUM + double_register_offset;
1187 regcache_cooked_write (regcache, regnum, val);
1188 fp_args[double_arg_index] = 1;
1189 fp_args[double_arg_index + 1] = 1;
1190 /* Skip the corresponding general argument register. */
1195 /* Store it as the integers, 8 bytes at the time, if
1196 necessary spilling on the stack. */
1200 /* Store return address. */
1201 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1203 /* Update stack pointer. */
1204 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1209 /* Find a function's return value in the appropriate registers (in
1210 regbuf), and copy it into valbuf. Extract from an array REGBUF
1211 containing the (raw) register state a function return value of type
1212 TYPE, and copy that, in virtual format, into VALBUF. */
1214 sh64_extract_return_value (struct type *type, struct regcache *regcache,
1217 int len = TYPE_LENGTH (type);
1219 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1223 /* Return value stored in FP0_REGNUM */
1224 regcache_raw_read (regcache, FP0_REGNUM, valbuf);
1228 /* return value stored in DR0_REGNUM */
1232 regcache_cooked_read (regcache, DR0_REGNUM, &buf);
1234 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1235 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1238 floatformat_to_doublest (&floatformat_ieee_double_big,
1240 store_typed_floating (valbuf, type, val);
1249 /* Result is in register 2. If smaller than 8 bytes, it is padded
1250 at the most significant end. */
1251 regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf);
1253 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1254 offset = register_size (current_gdbarch, DEFAULT_RETURN_REGNUM)
1258 memcpy (valbuf, buf + offset, len);
1261 error ("bad size for return value");
1265 /* Write into appropriate registers a function return value
1266 of type TYPE, given in virtual format.
1267 If the architecture is sh4 or sh3e, store a function's return value
1268 in the R0 general register or in the FP0 floating point register,
1269 depending on the type of the return value. In all the other cases
1270 the result is stored in r0, left-justified. */
1273 sh64_store_return_value (struct type *type, struct regcache *regcache,
1276 char buf[64]; /* more than enough... */
1277 int len = TYPE_LENGTH (type);
1279 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1281 int i, regnum = FP0_REGNUM;
1282 for (i = 0; i < len; i += 4)
1283 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1284 regcache_raw_write (regcache, regnum++,
1285 (char *) valbuf + len - 4 - i);
1287 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1291 int return_register = DEFAULT_RETURN_REGNUM;
1294 if (len <= register_size (current_gdbarch, return_register))
1296 /* Pad with zeros. */
1297 memset (buf, 0, register_size (current_gdbarch, return_register));
1298 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1299 offset = 0; /*register_size (current_gdbarch,
1300 return_register) - len;*/
1302 offset = register_size (current_gdbarch, return_register) - len;
1304 memcpy (buf + offset, valbuf, len);
1305 regcache_raw_write (regcache, return_register, buf);
1308 regcache_raw_write (regcache, return_register, valbuf);
1312 static enum return_value_convention
1313 sh64_return_value (struct gdbarch *gdbarch, struct type *type,
1314 struct regcache *regcache,
1315 void *readbuf, const void *writebuf)
1317 if (sh64_use_struct_convention (type))
1318 return RETURN_VALUE_STRUCT_CONVENTION;
1320 sh64_store_return_value (type, regcache, writebuf);
1322 sh64_extract_return_value (type, regcache, readbuf);
1323 return RETURN_VALUE_REGISTER_CONVENTION;
1327 sh64_show_media_regs (void)
1331 printf_filtered ("PC=%s SR=%016llx \n",
1332 paddr (read_register (PC_REGNUM)),
1333 (long long) read_register (SR_REGNUM));
1335 printf_filtered ("SSR=%016llx SPC=%016llx \n",
1336 (long long) read_register (SSR_REGNUM),
1337 (long long) read_register (SPC_REGNUM));
1338 printf_filtered ("FPSCR=%016lx\n ",
1339 (long) read_register (FPSCR_REGNUM));
1341 for (i = 0; i < 64; i = i + 4)
1342 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1344 (long long) read_register (i + 0),
1345 (long long) read_register (i + 1),
1346 (long long) read_register (i + 2),
1347 (long long) read_register (i + 3));
1349 printf_filtered ("\n");
1351 for (i = 0; i < 64; i = i + 8)
1352 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1354 (long) read_register (FP0_REGNUM + i + 0),
1355 (long) read_register (FP0_REGNUM + i + 1),
1356 (long) read_register (FP0_REGNUM + i + 2),
1357 (long) read_register (FP0_REGNUM + i + 3),
1358 (long) read_register (FP0_REGNUM + i + 4),
1359 (long) read_register (FP0_REGNUM + i + 5),
1360 (long) read_register (FP0_REGNUM + i + 6),
1361 (long) read_register (FP0_REGNUM + i + 7));
1365 sh64_show_compact_regs (void)
1369 printf_filtered ("PC=%s \n",
1370 paddr (read_register (PC_C_REGNUM)));
1372 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1373 (long) read_register (GBR_C_REGNUM),
1374 (long) read_register (MACH_C_REGNUM),
1375 (long) read_register (MACL_C_REGNUM),
1376 (long) read_register (PR_C_REGNUM),
1377 (long) read_register (T_C_REGNUM));
1378 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
1379 (long) read_register (FPSCR_C_REGNUM),
1380 (long) read_register (FPUL_C_REGNUM));
1382 for (i = 0; i < 16; i = i + 4)
1383 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1385 (long) read_register (i + 0),
1386 (long) read_register (i + 1),
1387 (long) read_register (i + 2),
1388 (long) read_register (i + 3));
1390 printf_filtered ("\n");
1392 for (i = 0; i < 16; i = i + 8)
1393 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1395 (long) read_register (FP0_REGNUM + i + 0),
1396 (long) read_register (FP0_REGNUM + i + 1),
1397 (long) read_register (FP0_REGNUM + i + 2),
1398 (long) read_register (FP0_REGNUM + i + 3),
1399 (long) read_register (FP0_REGNUM + i + 4),
1400 (long) read_register (FP0_REGNUM + i + 5),
1401 (long) read_register (FP0_REGNUM + i + 6),
1402 (long) read_register (FP0_REGNUM + i + 7));
1405 /* FIXME!!! This only shows the registers for shmedia, excluding the
1406 pseudo registers. */
1408 sh64_show_regs (void)
1410 if (deprecated_selected_frame
1411 && pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
1412 sh64_show_media_regs ();
1414 sh64_show_compact_regs ();
1419 SH MEDIA MODE (ISA 32)
1420 general registers (64-bit) 0-63
1421 0 r0, r1, r2, r3, r4, r5, r6, r7,
1422 64 r8, r9, r10, r11, r12, r13, r14, r15,
1423 128 r16, r17, r18, r19, r20, r21, r22, r23,
1424 192 r24, r25, r26, r27, r28, r29, r30, r31,
1425 256 r32, r33, r34, r35, r36, r37, r38, r39,
1426 320 r40, r41, r42, r43, r44, r45, r46, r47,
1427 384 r48, r49, r50, r51, r52, r53, r54, r55,
1428 448 r56, r57, r58, r59, r60, r61, r62, r63,
1433 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1436 target registers (64-bit) 68-75
1437 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1439 floating point state control register (32-bit) 76
1442 single precision floating point registers (32-bit) 77-140
1443 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1444 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1445 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1446 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1447 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1448 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1449 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1450 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1452 TOTAL SPACE FOR REGISTERS: 868 bytes
1454 From here on they are all pseudo registers: no memory allocated.
1455 REGISTER_BYTE returns the register byte for the base register.
1457 double precision registers (pseudo) 141-172
1458 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1459 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1460 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1461 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1463 floating point pairs (pseudo) 173-204
1464 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1465 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1466 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1467 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1469 floating point vectors (4 floating point regs) (pseudo) 205-220
1470 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1471 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1473 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1474 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1475 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1477 gbr_c, mach_c, macl_c, pr_c, t_c,
1479 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1480 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1481 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1482 fv0_c, fv4_c, fv8_c, fv12_c
1485 static struct type *
1486 sh64_build_float_register_type (int high)
1490 temp = create_range_type (NULL, builtin_type_int, 0, high);
1491 return create_array_type (NULL, builtin_type_float, temp);
1494 /* Return the GDB type object for the "standard" data type
1495 of data in register REG_NR. */
1496 static struct type *
1497 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
1499 if ((reg_nr >= FP0_REGNUM
1500 && reg_nr <= FP_LAST_REGNUM)
1501 || (reg_nr >= FP0_C_REGNUM
1502 && reg_nr <= FP_LAST_C_REGNUM))
1503 return builtin_type_float;
1504 else if ((reg_nr >= DR0_REGNUM
1505 && reg_nr <= DR_LAST_REGNUM)
1506 || (reg_nr >= DR0_C_REGNUM
1507 && reg_nr <= DR_LAST_C_REGNUM))
1508 return builtin_type_double;
1509 else if (reg_nr >= FPP0_REGNUM
1510 && reg_nr <= FPP_LAST_REGNUM)
1511 return sh64_build_float_register_type (1);
1512 else if ((reg_nr >= FV0_REGNUM
1513 && reg_nr <= FV_LAST_REGNUM)
1514 ||(reg_nr >= FV0_C_REGNUM
1515 && reg_nr <= FV_LAST_C_REGNUM))
1516 return sh64_build_float_register_type (3);
1517 else if (reg_nr == FPSCR_REGNUM)
1518 return builtin_type_int;
1519 else if (reg_nr >= R0_C_REGNUM
1520 && reg_nr < FP0_C_REGNUM)
1521 return builtin_type_int;
1523 return builtin_type_long_long;
1527 sh64_register_convert_to_virtual (int regnum, struct type *type,
1528 char *from, char *to)
1530 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
1532 /* It is a no-op. */
1533 memcpy (to, from, register_size (current_gdbarch, regnum));
1537 if ((regnum >= DR0_REGNUM
1538 && regnum <= DR_LAST_REGNUM)
1539 || (regnum >= DR0_C_REGNUM
1540 && regnum <= DR_LAST_C_REGNUM))
1543 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1545 store_typed_floating (to, type, val);
1548 error ("sh64_register_convert_to_virtual called with non DR register number");
1552 sh64_register_convert_to_raw (struct type *type, int regnum,
1553 const void *from, void *to)
1555 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
1557 /* It is a no-op. */
1558 memcpy (to, from, register_size (current_gdbarch, regnum));
1562 if ((regnum >= DR0_REGNUM
1563 && regnum <= DR_LAST_REGNUM)
1564 || (regnum >= DR0_C_REGNUM
1565 && regnum <= DR_LAST_C_REGNUM))
1567 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
1568 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1572 error ("sh64_register_convert_to_raw called with non DR register number");
1576 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1577 int reg_nr, void *buffer)
1582 char temp_buffer[MAX_REGISTER_SIZE];
1584 if (reg_nr >= DR0_REGNUM
1585 && reg_nr <= DR_LAST_REGNUM)
1587 base_regnum = sh64_dr_reg_base_num (reg_nr);
1589 /* Build the value in the provided buffer. */
1590 /* DR regs are double precision registers obtained by
1591 concatenating 2 single precision floating point registers. */
1592 for (portion = 0; portion < 2; portion++)
1593 regcache_raw_read (regcache, base_regnum + portion,
1595 + register_size (gdbarch, base_regnum) * portion));
1597 /* We must pay attention to the endianness. */
1598 sh64_register_convert_to_virtual (reg_nr,
1599 gdbarch_register_type (gdbarch,
1601 temp_buffer, buffer);
1605 else if (reg_nr >= FPP0_REGNUM
1606 && reg_nr <= FPP_LAST_REGNUM)
1608 base_regnum = sh64_fpp_reg_base_num (reg_nr);
1610 /* Build the value in the provided buffer. */
1611 /* FPP regs are pairs of single precision registers obtained by
1612 concatenating 2 single precision floating point registers. */
1613 for (portion = 0; portion < 2; portion++)
1614 regcache_raw_read (regcache, base_regnum + portion,
1616 + register_size (gdbarch, base_regnum) * portion));
1619 else if (reg_nr >= FV0_REGNUM
1620 && reg_nr <= FV_LAST_REGNUM)
1622 base_regnum = sh64_fv_reg_base_num (reg_nr);
1624 /* Build the value in the provided buffer. */
1625 /* FV regs are vectors of single precision registers obtained by
1626 concatenating 4 single precision floating point registers. */
1627 for (portion = 0; portion < 4; portion++)
1628 regcache_raw_read (regcache, base_regnum + portion,
1630 + register_size (gdbarch, base_regnum) * portion));
1633 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
1634 else if (reg_nr >= R0_C_REGNUM
1635 && reg_nr <= T_C_REGNUM)
1637 base_regnum = sh64_compact_reg_base_num (reg_nr);
1639 /* Build the value in the provided buffer. */
1640 regcache_raw_read (regcache, base_regnum, temp_buffer);
1641 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1643 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
1646 else if (reg_nr >= FP0_C_REGNUM
1647 && reg_nr <= FP_LAST_C_REGNUM)
1649 base_regnum = sh64_compact_reg_base_num (reg_nr);
1651 /* Build the value in the provided buffer. */
1652 /* Floating point registers map 1-1 to the media fp regs,
1653 they have the same size and endianness. */
1654 regcache_raw_read (regcache, base_regnum, buffer);
1657 else if (reg_nr >= DR0_C_REGNUM
1658 && reg_nr <= DR_LAST_C_REGNUM)
1660 base_regnum = sh64_compact_reg_base_num (reg_nr);
1662 /* DR_C regs are double precision registers obtained by
1663 concatenating 2 single precision floating point registers. */
1664 for (portion = 0; portion < 2; portion++)
1665 regcache_raw_read (regcache, base_regnum + portion,
1667 + register_size (gdbarch, base_regnum) * portion));
1669 /* We must pay attention to the endianness. */
1670 sh64_register_convert_to_virtual (reg_nr,
1671 gdbarch_register_type (gdbarch,
1673 temp_buffer, buffer);
1676 else if (reg_nr >= FV0_C_REGNUM
1677 && reg_nr <= FV_LAST_C_REGNUM)
1679 base_regnum = sh64_compact_reg_base_num (reg_nr);
1681 /* Build the value in the provided buffer. */
1682 /* FV_C regs are vectors of single precision registers obtained by
1683 concatenating 4 single precision floating point registers. */
1684 for (portion = 0; portion < 4; portion++)
1685 regcache_raw_read (regcache, base_regnum + portion,
1687 + register_size (gdbarch, base_regnum) * portion));
1690 else if (reg_nr == FPSCR_C_REGNUM)
1692 int fpscr_base_regnum;
1694 unsigned int fpscr_value;
1695 unsigned int sr_value;
1696 unsigned int fpscr_c_value;
1697 unsigned int fpscr_c_part1_value;
1698 unsigned int fpscr_c_part2_value;
1700 fpscr_base_regnum = FPSCR_REGNUM;
1701 sr_base_regnum = SR_REGNUM;
1703 /* Build the value in the provided buffer. */
1704 /* FPSCR_C is a very weird register that contains sparse bits
1705 from the FPSCR and the SR architectural registers.
1712 2-17 Bit 2-18 of FPSCR
1713 18-20 Bits 12,13,14 of SR
1717 /* Get FPSCR into a local buffer */
1718 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1719 /* Get value as an int. */
1720 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
1721 /* Get SR into a local buffer */
1722 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1723 /* Get value as an int. */
1724 sr_value = extract_unsigned_integer (temp_buffer, 4);
1725 /* Build the new value. */
1726 fpscr_c_part1_value = fpscr_value & 0x3fffd;
1727 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
1728 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
1729 /* Store that in out buffer!!! */
1730 store_unsigned_integer (buffer, 4, fpscr_c_value);
1731 /* FIXME There is surely an endianness gotcha here. */
1734 else if (reg_nr == FPUL_C_REGNUM)
1736 base_regnum = sh64_compact_reg_base_num (reg_nr);
1738 /* FPUL_C register is floating point register 32,
1739 same size, same endianness. */
1740 regcache_raw_read (regcache, base_regnum, buffer);
1745 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1746 int reg_nr, const void *buffer)
1748 int base_regnum, portion;
1750 char temp_buffer[MAX_REGISTER_SIZE];
1752 if (reg_nr >= DR0_REGNUM
1753 && reg_nr <= DR_LAST_REGNUM)
1755 base_regnum = sh64_dr_reg_base_num (reg_nr);
1756 /* We must pay attention to the endianness. */
1757 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1759 buffer, temp_buffer);
1761 /* Write the real regs for which this one is an alias. */
1762 for (portion = 0; portion < 2; portion++)
1763 regcache_raw_write (regcache, base_regnum + portion,
1765 + register_size (gdbarch,
1766 base_regnum) * portion));
1769 else if (reg_nr >= FPP0_REGNUM
1770 && reg_nr <= FPP_LAST_REGNUM)
1772 base_regnum = sh64_fpp_reg_base_num (reg_nr);
1774 /* Write the real regs for which this one is an alias. */
1775 for (portion = 0; portion < 2; portion++)
1776 regcache_raw_write (regcache, base_regnum + portion,
1778 + register_size (gdbarch,
1779 base_regnum) * portion));
1782 else if (reg_nr >= FV0_REGNUM
1783 && reg_nr <= FV_LAST_REGNUM)
1785 base_regnum = sh64_fv_reg_base_num (reg_nr);
1787 /* Write the real regs for which this one is an alias. */
1788 for (portion = 0; portion < 4; portion++)
1789 regcache_raw_write (regcache, base_regnum + portion,
1791 + register_size (gdbarch,
1792 base_regnum) * portion));
1795 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1796 register but only 4 bytes of it. */
1797 else if (reg_nr >= R0_C_REGNUM
1798 && reg_nr <= T_C_REGNUM)
1800 base_regnum = sh64_compact_reg_base_num (reg_nr);
1801 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1802 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1806 /* Let's read the value of the base register into a temporary
1807 buffer, so that overwriting the last four bytes with the new
1808 value of the pseudo will leave the upper 4 bytes unchanged. */
1809 regcache_raw_read (regcache, base_regnum, temp_buffer);
1810 /* Write as an 8 byte quantity */
1811 memcpy (temp_buffer + offset, buffer, 4);
1812 regcache_raw_write (regcache, base_regnum, temp_buffer);
1815 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1816 registers. Both are 4 bytes. */
1817 else if (reg_nr >= FP0_C_REGNUM
1818 && reg_nr <= FP_LAST_C_REGNUM)
1820 base_regnum = sh64_compact_reg_base_num (reg_nr);
1821 regcache_raw_write (regcache, base_regnum, buffer);
1824 else if (reg_nr >= DR0_C_REGNUM
1825 && reg_nr <= DR_LAST_C_REGNUM)
1827 base_regnum = sh64_compact_reg_base_num (reg_nr);
1828 for (portion = 0; portion < 2; portion++)
1830 /* We must pay attention to the endianness. */
1831 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
1834 buffer, temp_buffer);
1836 regcache_raw_write (regcache, base_regnum + portion,
1838 + register_size (gdbarch,
1839 base_regnum) * portion));
1843 else if (reg_nr >= FV0_C_REGNUM
1844 && reg_nr <= FV_LAST_C_REGNUM)
1846 base_regnum = sh64_compact_reg_base_num (reg_nr);
1848 for (portion = 0; portion < 4; portion++)
1850 regcache_raw_write (regcache, base_regnum + portion,
1852 + register_size (gdbarch,
1853 base_regnum) * portion));
1857 else if (reg_nr == FPSCR_C_REGNUM)
1859 int fpscr_base_regnum;
1861 unsigned int fpscr_value;
1862 unsigned int sr_value;
1863 unsigned int old_fpscr_value;
1864 unsigned int old_sr_value;
1865 unsigned int fpscr_c_value;
1866 unsigned int fpscr_mask;
1867 unsigned int sr_mask;
1869 fpscr_base_regnum = FPSCR_REGNUM;
1870 sr_base_regnum = SR_REGNUM;
1872 /* FPSCR_C is a very weird register that contains sparse bits
1873 from the FPSCR and the SR architectural registers.
1880 2-17 Bit 2-18 of FPSCR
1881 18-20 Bits 12,13,14 of SR
1885 /* Get value as an int. */
1886 fpscr_c_value = extract_unsigned_integer (buffer, 4);
1888 /* Build the new values. */
1889 fpscr_mask = 0x0003fffd;
1890 sr_mask = 0x001c0000;
1892 fpscr_value = fpscr_c_value & fpscr_mask;
1893 sr_value = (fpscr_value & sr_mask) >> 6;
1895 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1896 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
1897 old_fpscr_value &= 0xfffc0002;
1898 fpscr_value |= old_fpscr_value;
1899 store_unsigned_integer (temp_buffer, 4, fpscr_value);
1900 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
1902 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1903 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
1904 old_sr_value &= 0xffff8fff;
1905 sr_value |= old_sr_value;
1906 store_unsigned_integer (temp_buffer, 4, sr_value);
1907 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
1910 else if (reg_nr == FPUL_C_REGNUM)
1912 base_regnum = sh64_compact_reg_base_num (reg_nr);
1913 regcache_raw_write (regcache, base_regnum, buffer);
1917 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1918 shmedia REGISTERS. */
1919 /* Control registers, compact mode. */
1921 sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame,
1924 switch (cr_c_regnum)
1927 fprintf_filtered (file, "pc_c\t0x%08x\n",
1928 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1931 fprintf_filtered (file, "gbr_c\t0x%08x\n",
1932 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1935 fprintf_filtered (file, "mach_c\t0x%08x\n",
1936 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1939 fprintf_filtered (file, "macl_c\t0x%08x\n",
1940 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1943 fprintf_filtered (file, "pr_c\t0x%08x\n",
1944 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1947 fprintf_filtered (file, "t_c\t0x%08x\n",
1948 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1950 case FPSCR_C_REGNUM:
1951 fprintf_filtered (file, "fpscr_c\t0x%08x\n",
1952 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1955 fprintf_filtered (file, "fpul_c\t0x%08x\n",
1956 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1962 sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file,
1963 struct frame_info *frame, int regnum)
1964 { /* do values for FP (float) regs */
1966 double flt; /* double extracted from raw hex data */
1970 /* Allocate space for the float. */
1971 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1973 /* Get the data in raw format. */
1974 if (!frame_register_read (frame, regnum, raw_buffer))
1975 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1977 /* Get the register as a number */
1978 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1980 /* Print the name and some spaces. */
1981 fputs_filtered (REGISTER_NAME (regnum), file);
1982 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1984 /* Print the value. */
1986 fprintf_filtered (file, "<invalid float>");
1988 fprintf_filtered (file, "%-10.9g", flt);
1990 /* Print the fp register as hex. */
1991 fprintf_filtered (file, "\t(raw 0x");
1992 for (j = 0; j < register_size (gdbarch, regnum); j++)
1994 int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
1995 : register_size (gdbarch, regnum) - 1 - j;
1996 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1998 fprintf_filtered (file, ")");
1999 fprintf_filtered (file, "\n");
2003 sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
2004 struct frame_info *frame, int regnum)
2006 /* All the sh64-compact mode registers are pseudo registers. */
2008 if (regnum < NUM_REGS
2009 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA
2010 + NUM_PSEUDO_REGS_SH_COMPACT)
2011 internal_error (__FILE__, __LINE__,
2012 _("Invalid pseudo register number %d\n"), regnum);
2014 else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM))
2016 int fp_regnum = sh64_dr_reg_base_num (regnum);
2017 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM,
2018 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2019 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2022 else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM))
2024 int fp_regnum = sh64_compact_reg_base_num (regnum);
2025 fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM,
2026 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2027 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2030 else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM))
2032 int fp_regnum = sh64_fv_reg_base_num (regnum);
2033 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2034 regnum - FV0_REGNUM,
2035 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2036 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2037 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2038 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2041 else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM))
2043 int fp_regnum = sh64_compact_reg_base_num (regnum);
2044 fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2045 regnum - FV0_C_REGNUM,
2046 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2047 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2048 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2049 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2052 else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM)
2054 int fp_regnum = sh64_fpp_reg_base_num (regnum);
2055 fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM,
2056 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2057 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2060 else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM)
2062 int c_regnum = sh64_compact_reg_base_num (regnum);
2063 fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM,
2064 (unsigned) get_frame_register_unsigned (frame, c_regnum));
2066 else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM)
2067 /* This should work also for pseudoregs. */
2068 sh64_do_fp_register (gdbarch, file, frame, regnum);
2069 else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM)
2070 sh64_do_cr_c_register_info (file, frame, regnum);
2074 sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file,
2075 struct frame_info *frame, int regnum)
2077 char raw_buffer[MAX_REGISTER_SIZE];
2079 fputs_filtered (REGISTER_NAME (regnum), file);
2080 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2082 /* Get the data in raw format. */
2083 if (!frame_register_read (frame, regnum, raw_buffer))
2084 fprintf_filtered (file, "*value not available*\n");
2086 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2087 file, 'x', 1, 0, Val_pretty_default);
2088 fprintf_filtered (file, "\t");
2089 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2090 file, 0, 1, 0, Val_pretty_default);
2091 fprintf_filtered (file, "\n");
2095 sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file,
2096 struct frame_info *frame, int regnum)
2098 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2099 internal_error (__FILE__, __LINE__,
2100 _("Invalid register number %d\n"), regnum);
2102 else if (regnum >= 0 && regnum < NUM_REGS)
2104 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2105 sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */
2107 sh64_do_register (gdbarch, file, frame, regnum);
2110 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2111 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2115 sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2116 struct frame_info *frame, int regnum,
2119 if (regnum != -1) /* do one specified register */
2121 if (*(REGISTER_NAME (regnum)) == '\0')
2122 error ("Not a valid register for the current processor type");
2124 sh64_print_register (gdbarch, file, frame, regnum);
2127 /* do all (or most) registers */
2130 while (regnum < NUM_REGS)
2132 /* If the register name is empty, it is undefined for this
2133 processor, so don't display anything. */
2134 if (REGISTER_NAME (regnum) == NULL
2135 || *(REGISTER_NAME (regnum)) == '\0')
2141 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum))
2146 /* true for "INFO ALL-REGISTERS" command */
2147 sh64_do_fp_register (gdbarch, file, frame, regnum);
2151 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2155 sh64_do_register (gdbarch, file, frame, regnum);
2161 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2163 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2170 sh64_compact_print_registers_info (struct gdbarch *gdbarch,
2171 struct ui_file *file,
2172 struct frame_info *frame, int regnum,
2175 if (regnum != -1) /* do one specified register */
2177 if (*(REGISTER_NAME (regnum)) == '\0')
2178 error ("Not a valid register for the current processor type");
2180 if (regnum >= 0 && regnum < R0_C_REGNUM)
2181 error ("Not a valid register for the current processor mode.");
2183 sh64_print_register (gdbarch, file, frame, regnum);
2186 /* do all compact registers */
2188 regnum = R0_C_REGNUM;
2189 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2191 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2198 sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2199 struct frame_info *frame, int regnum, int fpregs)
2201 if (pc_is_isa32 (get_frame_pc (frame)))
2202 sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2204 sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2207 static struct sh64_frame_cache *
2208 sh64_alloc_frame_cache (void)
2210 struct sh64_frame_cache *cache;
2213 cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache);
2217 cache->saved_sp = 0;
2218 cache->sp_offset = 0;
2221 /* Frameless until proven otherwise. */
2224 /* Saved registers. We initialize these to -1 since zero is a valid
2225 offset (that's where fp is supposed to be stored). */
2226 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2228 cache->saved_regs[i] = -1;
2234 static struct sh64_frame_cache *
2235 sh64_frame_cache (struct frame_info *next_frame, void **this_cache)
2237 struct sh64_frame_cache *cache;
2238 CORE_ADDR current_pc;
2244 cache = sh64_alloc_frame_cache ();
2245 *this_cache = cache;
2247 current_pc = frame_pc_unwind (next_frame);
2248 cache->media_mode = pc_is_isa32 (current_pc);
2250 /* In principle, for normal frames, fp holds the frame pointer,
2251 which holds the base address for the current stack frame.
2252 However, for functions that don't need it, the frame pointer is
2253 optional. For these "frameless" functions the frame pointer is
2254 actually the frame pointer of the calling frame. */
2255 cache->base = frame_unwind_register_unsigned (next_frame, MEDIA_FP_REGNUM);
2256 if (cache->base == 0)
2259 cache->pc = frame_func_unwind (next_frame);
2261 sh64_analyze_prologue (current_gdbarch, cache, cache->pc, current_pc);
2263 if (!cache->uses_fp)
2265 /* We didn't find a valid frame, which means that CACHE->base
2266 currently holds the frame pointer for our calling frame. If
2267 we're at the start of a function, or somewhere half-way its
2268 prologue, the function's frame probably hasn't been fully
2269 setup yet. Try to reconstruct the base address for the stack
2270 frame by looking at the stack pointer. For truly "frameless"
2271 functions this might work too. */
2272 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2275 /* Now that we have the base address for the stack frame we can
2276 calculate the value of sp in the calling frame. */
2277 cache->saved_sp = cache->base + cache->sp_offset;
2279 /* Adjust all the saved registers such that they contain addresses
2280 instead of offsets. */
2281 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2282 if (cache->saved_regs[i] != -1)
2283 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i];
2289 sh64_frame_prev_register (struct frame_info *next_frame, void **this_cache,
2290 int regnum, int *optimizedp,
2291 enum lval_type *lvalp, CORE_ADDR *addrp,
2292 int *realnump, void *valuep)
2294 struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache);
2296 gdb_assert (regnum >= 0);
2298 if (regnum == SP_REGNUM && cache->saved_sp)
2306 /* Store the value. */
2307 store_unsigned_integer (valuep,
2308 register_size (current_gdbarch, SP_REGNUM),
2314 /* The PC of the previous frame is stored in the PR register of
2315 the current frame. Frob regnum so that we pull the value from
2316 the correct place. */
2317 if (regnum == PC_REGNUM)
2320 if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1)
2322 int reg_size = register_size (current_gdbarch, regnum);
2326 *lvalp = lval_memory;
2327 *addrp = cache->saved_regs[regnum];
2329 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32
2330 && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM))
2336 memset (valuep, 0, reg_size);
2337 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2338 read_memory (*addrp, valuep, size);
2340 read_memory (*addrp, (char *) valuep + reg_size - size, size);
2346 *lvalp = lval_register;
2350 frame_unwind_register (next_frame, (*realnump), valuep);
2354 sh64_frame_this_id (struct frame_info *next_frame, void **this_cache,
2355 struct frame_id *this_id)
2357 struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache);
2359 /* This marks the outermost frame. */
2360 if (cache->base == 0)
2363 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2366 static const struct frame_unwind sh64_frame_unwind = {
2369 sh64_frame_prev_register
2372 static const struct frame_unwind *
2373 sh64_frame_sniffer (struct frame_info *next_frame)
2375 return &sh64_frame_unwind;
2379 sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2381 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2385 sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2387 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2390 static struct frame_id
2391 sh64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2393 return frame_id_build (sh64_unwind_sp (gdbarch, next_frame),
2394 frame_pc_unwind (next_frame));
2398 sh64_frame_base_address (struct frame_info *next_frame, void **this_cache)
2400 struct sh64_frame_cache *cache = sh64_frame_cache (next_frame, this_cache);
2405 static const struct frame_base sh64_frame_base = {
2407 sh64_frame_base_address,
2408 sh64_frame_base_address,
2409 sh64_frame_base_address
2414 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2416 struct gdbarch *gdbarch;
2417 struct gdbarch_tdep *tdep;
2419 /* If there is already a candidate, use it. */
2420 arches = gdbarch_list_lookup_by_info (arches, &info);
2422 return arches->gdbarch;
2424 /* None found, create a new architecture from the information
2426 tdep = XMALLOC (struct gdbarch_tdep);
2427 gdbarch = gdbarch_alloc (&info, tdep);
2429 /* Determine the ABI */
2430 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2432 /* If the ABI is the 64-bit one, it can only be sh-media. */
2433 tdep->sh_abi = SH_ABI_64;
2434 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2435 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2439 /* If the ABI is the 32-bit one it could be either media or
2441 tdep->sh_abi = SH_ABI_32;
2442 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2443 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2446 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2447 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2448 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2449 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2450 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2451 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2452 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2454 /* The number of real registers is the same whether we are in
2455 ISA16(compact) or ISA32(media). */
2456 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2457 set_gdbarch_sp_regnum (gdbarch, 15);
2458 set_gdbarch_pc_regnum (gdbarch, 64);
2459 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2460 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA
2461 + NUM_PSEUDO_REGS_SH_COMPACT);
2463 set_gdbarch_register_name (gdbarch, sh64_register_name);
2464 set_gdbarch_register_type (gdbarch, sh64_register_type);
2466 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2467 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2469 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
2471 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh64);
2472 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2474 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2476 set_gdbarch_return_value (gdbarch, sh64_return_value);
2477 set_gdbarch_deprecated_extract_struct_value_address (gdbarch,
2478 sh64_extract_struct_value_address);
2480 set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue);
2481 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2483 set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call);
2485 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2487 set_gdbarch_frame_align (gdbarch, sh64_frame_align);
2488 set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp);
2489 set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc);
2490 set_gdbarch_unwind_dummy_id (gdbarch, sh64_unwind_dummy_id);
2491 frame_base_set_default (gdbarch, &sh64_frame_base);
2493 set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info);
2495 set_gdbarch_elf_make_msymbol_special (gdbarch,
2496 sh64_elf_make_msymbol_special);
2498 /* Hook in ABI-specific overrides, if they have been registered. */
2499 gdbarch_init_osabi (info, gdbarch);
2501 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2502 frame_unwind_append_sniffer (gdbarch, sh64_frame_sniffer);