1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007, 2008, 2009, 2010, 2011
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 Contributed by Steve Chamberlain
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
39 #include "gdb_string.h"
40 #include "gdb_assert.h"
41 #include "arch-utils.h"
50 /* registers numbers shared with the simulator */
51 #include "gdb/sim-sh.h"
54 /* Information that is dependent on the processor variant. */
67 struct sh64_frame_cache
74 /* Flag showing that a frame has been created in the prologue code. */
79 /* Saved registers. */
80 CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
84 /* Registers of SH5 */
88 DEFAULT_RETURN_REGNUM = 2,
89 STRUCT_RETURN_REGNUM = 2,
92 FLOAT_ARGLAST_REGNUM = 11,
98 /* FPP stands for Floating Point Pair, to avoid confusion with
99 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
100 point register. Unfortunately on the sh5, the floating point
101 registers are called FR, and the floating point pairs are called FP. */
103 FPP_LAST_REGNUM = 204,
105 FV_LAST_REGNUM = 220,
107 R_LAST_C_REGNUM = 236,
114 FPSCR_C_REGNUM = 243,
117 FP_LAST_C_REGNUM = 260,
119 DR_LAST_C_REGNUM = 268,
121 FV_LAST_C_REGNUM = 272,
122 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
123 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
124 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
125 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
126 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
130 sh64_register_name (struct gdbarch *gdbarch, int reg_nr)
132 static char *register_names[] =
134 /* SH MEDIA MODE (ISA 32) */
135 /* general registers (64-bit) 0-63 */
136 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
137 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
138 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
139 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
140 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
141 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
142 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
143 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
148 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
151 /* target registers (64-bit) 68-75*/
152 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
154 /* floating point state control register (32-bit) 76 */
157 /* single precision floating point registers (32-bit) 77-140*/
158 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
159 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
160 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
161 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
162 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
163 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
164 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
165 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
167 /* double precision registers (pseudo) 141-172 */
168 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
169 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
170 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
171 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
173 /* floating point pairs (pseudo) 173-204*/
174 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
175 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
176 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
177 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
179 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
180 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
181 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
183 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
184 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
185 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
187 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
189 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
190 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
191 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
192 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
193 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return register_names[reg_nr];
203 #define NUM_PSEUDO_REGS_SH_MEDIA 80
204 #define NUM_PSEUDO_REGS_SH_COMPACT 51
206 /* Macros and functions for setting and testing a bit in a minimal
207 symbol that marks it as 32-bit function. The MSB of the minimal
208 symbol's "info" field is used for this purpose.
210 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
211 i.e. refers to a 32-bit function, and sets a "special" bit in a
212 minimal symbol to mark it as a 32-bit function
213 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
215 #define MSYMBOL_IS_SPECIAL(msym) \
216 MSYMBOL_TARGET_FLAG_1 (msym)
219 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
224 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
226 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
227 SYMBOL_VALUE_ADDRESS (msym) |= 1;
231 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
232 are some macros to test, set, or clear bit 0 of addresses. */
233 #define IS_ISA32_ADDR(addr) ((addr) & 1)
234 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
235 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
238 pc_is_isa32 (bfd_vma memaddr)
240 struct minimal_symbol *sym;
242 /* If bit 0 of the address is set, assume this is a
243 ISA32 (shmedia) address. */
244 if (IS_ISA32_ADDR (memaddr))
247 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
248 the high bit of the info field. Use this to decide if the function is
250 sym = lookup_minimal_symbol_by_pc (memaddr);
252 return MSYMBOL_IS_SPECIAL (sym);
257 static const unsigned char *
258 sh64_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
260 /* The BRK instruction for shmedia is
261 01101111 11110101 11111111 11110000
262 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
263 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
265 /* The BRK instruction for shcompact is
267 which translates in big endian mode to 0x0, 0x3b
268 and in little endian mode to 0x3b, 0x0*/
270 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
272 if (pc_is_isa32 (*pcptr))
274 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
275 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
276 *lenptr = sizeof (big_breakpoint_media);
277 return big_breakpoint_media;
281 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
282 *lenptr = sizeof (big_breakpoint_compact);
283 return big_breakpoint_compact;
288 if (pc_is_isa32 (*pcptr))
290 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
291 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
292 *lenptr = sizeof (little_breakpoint_media);
293 return little_breakpoint_media;
297 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
298 *lenptr = sizeof (little_breakpoint_compact);
299 return little_breakpoint_compact;
304 /* Prologue looks like
305 [mov.l <regs>,@-r15]...
310 Actually it can be more complicated than this. For instance, with
328 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
329 with l=1 and n = 18 0110101111110001010010100aaa0000 */
330 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
332 /* STS.L PR,@-r0 0100000000100010
333 r0-4-->r0, PR-->(r0) */
334 #define IS_STS_R0(x) ((x) == 0x4022)
336 /* STS PR, Rm 0000mmmm00101010
338 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
340 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
342 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
344 /* MOV.L R14,@(disp,r15) 000111111110dddd
345 R14-->(dispx4+r15) */
346 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
348 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
349 R18-->(dispx8+R14) */
350 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
352 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
353 R18-->(dispx8+R15) */
354 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
356 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
357 R18-->(dispx4+R15) */
358 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
360 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
361 R14-->(dispx8+R15) */
362 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
364 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
365 R14-->(dispx4+R15) */
366 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
368 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
370 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
372 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
374 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
376 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
378 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
380 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
382 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
384 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
386 /* MOV #imm, R0 1110 0000 ssss ssss
388 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
390 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
391 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
393 /* ADD r15,r0 0011 0000 1111 1100
395 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
397 /* MOV.L R14 @-R0 0010 0000 1110 0110
398 R14-->(R0-4), R0-4-->R0 */
399 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
401 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
402 where Rm is one of r2-r9 which are the argument registers. */
403 /* FIXME: Recognize the float and double register moves too! */
404 #define IS_MEDIA_IND_ARG_MOV(x) \
405 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
407 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
408 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
409 where Rm is one of r2-r9 which are the argument registers. */
410 #define IS_MEDIA_ARG_MOV(x) \
411 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
412 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
414 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
415 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
416 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
417 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
418 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
419 #define IS_MEDIA_MOV_TO_R14(x) \
420 ((((x) & 0xfffffc0f) == 0xa0e00000) \
421 || (((x) & 0xfffffc0f) == 0xa4e00000) \
422 || (((x) & 0xfffffc0f) == 0xa8e00000) \
423 || (((x) & 0xfffffc0f) == 0xb4e00000) \
424 || (((x) & 0xfffffc0f) == 0xbce00000))
426 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
428 #define IS_COMPACT_IND_ARG_MOV(x) \
429 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
431 /* compact direct arg move!
432 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
433 #define IS_COMPACT_ARG_MOV(x) \
434 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
436 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
437 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
438 #define IS_COMPACT_MOV_TO_R14(x) \
439 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
441 #define IS_JSR_R0(x) ((x) == 0x400b)
442 #define IS_NOP(x) ((x) == 0x0009)
445 /* MOV r15,r14 0110111011110011
447 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
449 /* ADD #imm,r15 01111111iiiiiiii
451 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
453 /* Skip any prologue before the guts of a function */
455 /* Skip the prologue using the debug information. If this fails we'll
456 fall back on the 'guess' method below. */
458 after_prologue (CORE_ADDR pc)
460 struct symtab_and_line sal;
461 CORE_ADDR func_addr, func_end;
463 /* If we can not find the symbol in the partial symbol table, then
464 there is no hope we can determine the function's start address
466 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
470 /* Get the line associated with FUNC_ADDR. */
471 sal = find_pc_line (func_addr, 0);
473 /* There are only two cases to consider. First, the end of the source line
474 is within the function bounds. In that case we return the end of the
475 source line. Second is the end of the source line extends beyond the
476 bounds of the current function. We need to use the slow code to
477 examine instructions in that case. */
478 if (sal.end < func_end)
485 look_for_args_moves (struct gdbarch *gdbarch,
486 CORE_ADDR start_pc, int media_mode)
488 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
491 int insn_size = (media_mode ? 4 : 2);
493 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
497 w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
498 insn_size, byte_order);
500 if (IS_MEDIA_IND_ARG_MOV (w))
502 /* This must be followed by a store to r14, so the argument
503 is where the debug info says it is. This can happen after
504 the SP has been saved, unfortunately. */
506 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
507 insn_size, byte_order);
509 if (IS_MEDIA_MOV_TO_R14 (next_insn))
512 else if (IS_MEDIA_ARG_MOV (w))
514 /* These instructions store directly the argument in r14. */
522 w = read_memory_integer (here, insn_size, byte_order);
525 if (IS_COMPACT_IND_ARG_MOV (w))
527 /* This must be followed by a store to r14, so the argument
528 is where the debug info says it is. This can happen after
529 the SP has been saved, unfortunately. */
531 int next_insn = 0xffff & read_memory_integer (here, insn_size,
534 if (IS_COMPACT_MOV_TO_R14 (next_insn))
537 else if (IS_COMPACT_ARG_MOV (w))
539 /* These instructions store directly the argument in r14. */
542 else if (IS_MOVL_R0 (w))
544 /* There is a function that gcc calls to get the arguments
545 passed correctly to the function. Only after this
546 function call the arguments will be found at the place
547 where they are supposed to be. This happens in case the
548 argument has to be stored into a 64-bit register (for
549 instance doubles, long longs). SHcompact doesn't have
550 access to the full 64-bits, so we store the register in
551 stack slot and store the address of the stack slot in
552 the register, then do a call through a wrapper that
553 loads the memory value into the register. A SHcompact
554 callee calls an argument decoder
555 (GCC_shcompact_incoming_args) that stores the 64-bit
556 value in a stack slot and stores the address of the
557 stack slot in the register. GCC thinks the argument is
558 just passed by transparent reference, but this is only
559 true after the argument decoder is called. Such a call
560 needs to be considered part of the prologue. */
562 /* This must be followed by a JSR @r0 instruction and by
563 a NOP instruction. After these, the prologue is over! */
565 int next_insn = 0xffff & read_memory_integer (here, insn_size,
568 if (IS_JSR_R0 (next_insn))
570 next_insn = 0xffff & read_memory_integer (here, insn_size,
574 if (IS_NOP (next_insn))
587 sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc)
589 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
598 if (pc_is_isa32 (start_pc) == 0)
604 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
609 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
610 insn_size, byte_order);
612 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
613 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
614 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
618 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
626 /* Don't bail out yet, we may have arguments stored in
627 registers here, according to the debug info, so that
628 gdb can print the frames correctly. */
629 start_pc = look_for_args_moves (gdbarch,
630 here - insn_size, media_mode);
636 int w = 0xffff & read_memory_integer (here, insn_size, byte_order);
639 if (IS_STS_R0 (w) || IS_STS_PR (w)
640 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
641 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
645 else if (IS_MOV_SP_FP (w))
653 /* Don't bail out yet, we may have arguments stored in
654 registers here, according to the debug info, so that
655 gdb can print the frames correctly. */
656 start_pc = look_for_args_moves (gdbarch,
657 here - insn_size, media_mode);
667 sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
669 CORE_ADDR post_prologue_pc;
671 /* See if we can determine the end of the prologue via the symbol table.
672 If so, then return either PC, or the PC after the prologue, whichever
674 post_prologue_pc = after_prologue (pc);
676 /* If after_prologue returned a useful address, then use it. Else
677 fall back on the instruction skipping code. */
678 if (post_prologue_pc != 0)
679 return max (pc, post_prologue_pc);
681 return sh64_skip_prologue_hard_way (gdbarch, pc);
684 /* Should call_function allocate stack space for a struct return? */
686 sh64_use_struct_convention (struct type *type)
688 return (TYPE_LENGTH (type) > 8);
691 /* For vectors of 4 floating point registers. */
693 sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
697 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4;
701 /* For double precision floating point registers, i.e 2 fp regs.*/
703 sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
707 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2;
711 /* For pairs of floating point registers */
713 sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum)
717 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2;
723 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
724 GDB_REGNUM BASE_REGNUM
784 sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr)
786 int base_regnum = reg_nr;
788 /* general register N maps to general register N */
789 if (reg_nr >= R0_C_REGNUM
790 && reg_nr <= R_LAST_C_REGNUM)
791 base_regnum = reg_nr - R0_C_REGNUM;
793 /* floating point register N maps to floating point register N */
794 else if (reg_nr >= FP0_C_REGNUM
795 && reg_nr <= FP_LAST_C_REGNUM)
796 base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch);
798 /* double prec register N maps to base regnum for double prec register N */
799 else if (reg_nr >= DR0_C_REGNUM
800 && reg_nr <= DR_LAST_C_REGNUM)
801 base_regnum = sh64_dr_reg_base_num (gdbarch,
802 DR0_REGNUM + reg_nr - DR0_C_REGNUM);
804 /* vector N maps to base regnum for vector register N */
805 else if (reg_nr >= FV0_C_REGNUM
806 && reg_nr <= FV_LAST_C_REGNUM)
807 base_regnum = sh64_fv_reg_base_num (gdbarch,
808 FV0_REGNUM + reg_nr - FV0_C_REGNUM);
810 else if (reg_nr == PC_C_REGNUM)
811 base_regnum = gdbarch_pc_regnum (gdbarch);
813 else if (reg_nr == GBR_C_REGNUM)
816 else if (reg_nr == MACH_C_REGNUM
817 || reg_nr == MACL_C_REGNUM)
820 else if (reg_nr == PR_C_REGNUM)
821 base_regnum = PR_REGNUM;
823 else if (reg_nr == T_C_REGNUM)
826 else if (reg_nr == FPSCR_C_REGNUM)
827 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
829 else if (reg_nr == FPUL_C_REGNUM)
830 base_regnum = gdbarch_fp0_regnum (gdbarch) + 32;
836 sign_extend (int value, int bits)
838 value = value & ((1 << bits) - 1);
839 return (value & (1 << (bits - 1))
840 ? value | (~((1 << bits) - 1))
845 sh64_analyze_prologue (struct gdbarch *gdbarch,
846 struct sh64_frame_cache *cache,
848 CORE_ADDR current_pc)
856 int gdb_register_number;
858 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
859 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
861 cache->sp_offset = 0;
863 /* Loop around examining the prologue insns until we find something
864 that does not appear to be part of the prologue. But give up
865 after 20 of them, since we're getting silly then. */
869 if (cache->media_mode)
874 opc = pc + (insn_size * 28);
875 if (opc > current_pc)
877 for ( ; pc <= opc; pc += insn_size)
879 insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
881 insn_size, byte_order);
883 if (!cache->media_mode)
885 if (IS_STS_PR (insn))
887 int next_insn = read_memory_integer (pc + insn_size,
888 insn_size, byte_order);
889 if (IS_MOV_TO_R15 (next_insn))
891 cache->saved_regs[PR_REGNUM] =
892 cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
897 else if (IS_MOV_R14 (insn))
898 cache->saved_regs[MEDIA_FP_REGNUM] =
899 cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
901 else if (IS_MOV_R0 (insn))
903 /* Put in R0 the offset from SP at which to store some
904 registers. We are interested in this value, because it
905 will tell us where the given registers are stored within
907 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
910 else if (IS_ADD_SP_R0 (insn))
912 /* This instruction still prepares r0, but we don't care.
913 We already have the offset in r0_val. */
916 else if (IS_STS_R0 (insn))
918 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
919 cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
923 else if (IS_MOV_R14_R0 (insn))
925 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
926 cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
931 else if (IS_ADD_SP (insn))
932 cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
934 else if (IS_MOV_SP_FP (insn))
939 if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
941 sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
943 else if (IS_STQ_R18_R15 (insn))
944 cache->saved_regs[PR_REGNUM] =
945 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
947 else if (IS_STL_R18_R15 (insn))
948 cache->saved_regs[PR_REGNUM] =
949 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
951 else if (IS_STQ_R14_R15 (insn))
952 cache->saved_regs[MEDIA_FP_REGNUM] =
953 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
955 else if (IS_STL_R14_R15 (insn))
956 cache->saved_regs[MEDIA_FP_REGNUM] =
957 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
959 else if (IS_MOV_SP_FP_MEDIA (insn))
964 if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0)
969 sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
974 /* Function: push_dummy_call
975 Setup the function arguments for calling a function in the inferior.
977 On the Renesas SH architecture, there are four registers (R4 to R7)
978 which are dedicated for passing function arguments. Up to the first
979 four arguments (depending on size) may go into these registers.
980 The rest go on the stack.
982 Arguments that are smaller than 4 bytes will still take up a whole
983 register or a whole 32-bit word on the stack, and will be
984 right-justified in the register or the stack word. This includes
985 chars, shorts, and small aggregate types.
987 Arguments that are larger than 4 bytes may be split between two or
988 more registers. If there are not enough registers free, an argument
989 may be passed partly in a register (or registers), and partly on the
990 stack. This includes doubles, long longs, and larger aggregates.
991 As far as I know, there is no upper limit to the size of aggregates
992 that will be passed in this way; in other words, the convention of
993 passing a pointer to a large aggregate instead of a copy is not used.
995 An exceptional case exists for struct arguments (and possibly other
996 aggregates such as arrays) if the size is larger than 4 bytes but
997 not a multiple of 4 bytes. In this case the argument is never split
998 between the registers and the stack, but instead is copied in its
999 entirety onto the stack, AND also copied into as many registers as
1000 there is room for. In other words, space in registers permitting,
1001 two copies of the same argument are passed in. As far as I can tell,
1002 only the one on the stack is used, although that may be a function
1003 of the level of compiler optimization. I suspect this is a compiler
1004 bug. Arguments of these odd sizes are left-justified within the
1005 word (as opposed to arguments smaller than 4 bytes, which are
1008 If the function is to return an aggregate type such as a struct, it
1009 is either returned in the normal return value register R0 (if its
1010 size is no greater than one byte), or else the caller must allocate
1011 space into which the callee will copy the return value (if the size
1012 is greater than one byte). In this case, a pointer to the return
1013 value location is passed into the callee in register R2, which does
1014 not displace any of the other arguments passed in via registers R4
1017 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1018 non-scalar (struct, union) elements (even if the elements are
1020 FR0-FR11 for single precision floating point (float)
1021 DR0-DR10 for double precision floating point (double)
1023 If a float is argument number 3 (for instance) and arguments number
1024 1,2, and 4 are integer, the mapping will be:
1025 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1027 If a float is argument number 10 (for instance) and arguments number
1028 1 through 10 are integer, the mapping will be:
1029 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1030 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1031 I.e. there is hole in the stack.
1033 Different rules apply for variable arguments functions, and for functions
1034 for which the prototype is not known. */
1037 sh64_push_dummy_call (struct gdbarch *gdbarch,
1038 struct value *function,
1039 struct regcache *regcache,
1041 int nargs, struct value **args,
1042 CORE_ADDR sp, int struct_return,
1043 CORE_ADDR struct_addr)
1045 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1046 int stack_offset, stack_alloc;
1050 int float_arg_index = 0;
1051 int double_arg_index = 0;
1062 memset (fp_args, 0, sizeof (fp_args));
1064 /* first force sp to a 8-byte alignment */
1065 sp = sh64_frame_align (gdbarch, sp);
1067 /* The "struct return pointer" pseudo-argument has its own dedicated
1071 regcache_cooked_write_unsigned (regcache,
1072 STRUCT_RETURN_REGNUM, struct_addr);
1074 /* Now make sure there's space on the stack */
1075 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1076 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
1077 sp -= stack_alloc; /* make room on stack for args */
1079 /* Now load as many as possible of the first arguments into
1080 registers, and push the rest onto the stack. There are 64 bytes
1081 in eight registers available. Loop thru args from first to last. */
1083 int_argreg = ARG0_REGNUM;
1084 float_argreg = gdbarch_fp0_regnum (gdbarch);
1085 double_argreg = DR0_REGNUM;
1087 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1089 type = value_type (args[argnum]);
1090 len = TYPE_LENGTH (type);
1091 memset (valbuf, 0, sizeof (valbuf));
1093 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1095 argreg_size = register_size (gdbarch, int_argreg);
1097 if (len < argreg_size)
1099 /* value gets right-justified in the register or stack word */
1100 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1101 memcpy (valbuf + argreg_size - len,
1102 (char *) value_contents (args[argnum]), len);
1104 memcpy (valbuf, (char *) value_contents (args[argnum]), len);
1109 val = (char *) value_contents (args[argnum]);
1113 if (int_argreg > ARGLAST_REGNUM)
1115 /* must go on the stack */
1116 write_memory (sp + stack_offset, (const bfd_byte *) val,
1118 stack_offset += 8;/*argreg_size;*/
1120 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1121 That's because some *&^%$ things get passed on the stack
1122 AND in the registers! */
1123 if (int_argreg <= ARGLAST_REGNUM)
1125 /* there's room in a register */
1126 regval = extract_unsigned_integer (val, argreg_size,
1128 regcache_cooked_write_unsigned (regcache, int_argreg, regval);
1130 /* Store the value 8 bytes at a time. This means that
1131 things larger than 8 bytes may go partly in registers
1132 and partly on the stack. FIXME: argreg is incremented
1133 before we use its size. */
1141 val = (char *) value_contents (args[argnum]);
1144 /* Where is it going to be stored? */
1145 while (fp_args[float_arg_index])
1148 /* Now float_argreg points to the register where it
1149 should be stored. Are we still within the allowed
1151 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1153 /* Goes in FR0...FR11 */
1154 regcache_cooked_write (regcache,
1155 gdbarch_fp0_regnum (gdbarch)
1158 fp_args[float_arg_index] = 1;
1159 /* Skip the corresponding general argument register. */
1164 /* Store it as the integers, 8 bytes at the time, if
1165 necessary spilling on the stack. */
1170 /* Where is it going to be stored? */
1171 while (fp_args[double_arg_index])
1172 double_arg_index += 2;
1173 /* Now double_argreg points to the register
1174 where it should be stored.
1175 Are we still within the allowed register set? */
1176 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1178 /* Goes in DR0...DR10 */
1179 /* The numbering of the DRi registers is consecutive,
1180 i.e. includes odd numbers. */
1181 int double_register_offset = double_arg_index / 2;
1182 int regnum = DR0_REGNUM + double_register_offset;
1183 regcache_cooked_write (regcache, regnum, val);
1184 fp_args[double_arg_index] = 1;
1185 fp_args[double_arg_index + 1] = 1;
1186 /* Skip the corresponding general argument register. */
1191 /* Store it as the integers, 8 bytes at the time, if
1192 necessary spilling on the stack. */
1196 /* Store return address. */
1197 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1199 /* Update stack pointer. */
1200 regcache_cooked_write_unsigned (regcache,
1201 gdbarch_sp_regnum (gdbarch), sp);
1206 /* Find a function's return value in the appropriate registers (in
1207 regbuf), and copy it into valbuf. Extract from an array REGBUF
1208 containing the (raw) register state a function return value of type
1209 TYPE, and copy that, in virtual format, into VALBUF. */
1211 sh64_extract_return_value (struct type *type, struct regcache *regcache,
1214 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1215 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1216 int len = TYPE_LENGTH (type);
1218 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1222 /* Return value stored in gdbarch_fp0_regnum */
1223 regcache_raw_read (regcache,
1224 gdbarch_fp0_regnum (gdbarch), valbuf);
1228 /* return value stored in DR0_REGNUM */
1232 regcache_cooked_read (regcache, DR0_REGNUM, buf);
1234 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1235 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1238 floatformat_to_doublest (&floatformat_ieee_double_big,
1240 store_typed_floating (valbuf, type, val);
1249 /* Result is in register 2. If smaller than 8 bytes, it is padded
1250 at the most significant end. */
1251 regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf);
1253 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1254 offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM)
1258 memcpy (valbuf, buf + offset, len);
1261 error (_("bad size for return value"));
1265 /* Write into appropriate registers a function return value
1266 of type TYPE, given in virtual format.
1267 If the architecture is sh4 or sh3e, store a function's return value
1268 in the R0 general register or in the FP0 floating point register,
1269 depending on the type of the return value. In all the other cases
1270 the result is stored in r0, left-justified. */
1273 sh64_store_return_value (struct type *type, struct regcache *regcache,
1276 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1277 char buf[64]; /* more than enough... */
1278 int len = TYPE_LENGTH (type);
1280 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1282 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1283 for (i = 0; i < len; i += 4)
1284 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1285 regcache_raw_write (regcache, regnum++,
1286 (char *) valbuf + len - 4 - i);
1288 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1292 int return_register = DEFAULT_RETURN_REGNUM;
1295 if (len <= register_size (gdbarch, return_register))
1297 /* Pad with zeros. */
1298 memset (buf, 0, register_size (gdbarch, return_register));
1299 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1300 offset = 0; /*register_size (gdbarch,
1301 return_register) - len;*/
1303 offset = register_size (gdbarch, return_register) - len;
1305 memcpy (buf + offset, valbuf, len);
1306 regcache_raw_write (regcache, return_register, buf);
1309 regcache_raw_write (regcache, return_register, valbuf);
1313 static enum return_value_convention
1314 sh64_return_value (struct gdbarch *gdbarch, struct type *func_type,
1315 struct type *type, struct regcache *regcache,
1316 gdb_byte *readbuf, const gdb_byte *writebuf)
1318 if (sh64_use_struct_convention (type))
1319 return RETURN_VALUE_STRUCT_CONVENTION;
1321 sh64_store_return_value (type, regcache, writebuf);
1323 sh64_extract_return_value (type, regcache, readbuf);
1324 return RETURN_VALUE_REGISTER_CONVENTION;
1328 sh64_show_media_regs (struct frame_info *frame)
1330 struct gdbarch *gdbarch = get_frame_arch (frame);
1335 phex (get_frame_register_unsigned (frame,
1336 gdbarch_pc_regnum (gdbarch)), 8),
1337 phex (get_frame_register_unsigned (frame, SR_REGNUM), 8));
1341 phex (get_frame_register_unsigned (frame, SSR_REGNUM), 8),
1342 phex (get_frame_register_unsigned (frame, SPC_REGNUM), 8));
1345 phex (get_frame_register_unsigned (frame, FPSCR_REGNUM), 8));
1347 for (i = 0; i < 64; i = i + 4)
1349 ("\nR%d-R%d %s %s %s %s\n",
1351 phex (get_frame_register_unsigned (frame, i + 0), 8),
1352 phex (get_frame_register_unsigned (frame, i + 1), 8),
1353 phex (get_frame_register_unsigned (frame, i + 2), 8),
1354 phex (get_frame_register_unsigned (frame, i + 3), 8));
1356 printf_filtered ("\n");
1358 for (i = 0; i < 64; i = i + 8)
1360 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1362 (long) get_frame_register_unsigned
1363 (frame, gdbarch_fp0_regnum (gdbarch) + i + 0),
1364 (long) get_frame_register_unsigned
1365 (frame, gdbarch_fp0_regnum (gdbarch) + i + 1),
1366 (long) get_frame_register_unsigned
1367 (frame, gdbarch_fp0_regnum (gdbarch) + i + 2),
1368 (long) get_frame_register_unsigned
1369 (frame, gdbarch_fp0_regnum (gdbarch) + i + 3),
1370 (long) get_frame_register_unsigned
1371 (frame, gdbarch_fp0_regnum (gdbarch) + i + 4),
1372 (long) get_frame_register_unsigned
1373 (frame, gdbarch_fp0_regnum (gdbarch) + i + 5),
1374 (long) get_frame_register_unsigned
1375 (frame, gdbarch_fp0_regnum (gdbarch) + i + 6),
1376 (long) get_frame_register_unsigned
1377 (frame, gdbarch_fp0_regnum (gdbarch) + i + 7));
1381 sh64_show_compact_regs (struct frame_info *frame)
1383 struct gdbarch *gdbarch = get_frame_arch (frame);
1388 phex (get_frame_register_unsigned (frame, PC_C_REGNUM), 8));
1391 ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1392 (long) get_frame_register_unsigned (frame, GBR_C_REGNUM),
1393 (long) get_frame_register_unsigned (frame, MACH_C_REGNUM),
1394 (long) get_frame_register_unsigned (frame, MACL_C_REGNUM),
1395 (long) get_frame_register_unsigned (frame, PR_C_REGNUM),
1396 (long) get_frame_register_unsigned (frame, T_C_REGNUM));
1398 ("FPSCR=%08lx FPUL=%08lx\n",
1399 (long) get_frame_register_unsigned (frame, FPSCR_C_REGNUM),
1400 (long) get_frame_register_unsigned (frame, FPUL_C_REGNUM));
1402 for (i = 0; i < 16; i = i + 4)
1404 ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1406 (long) get_frame_register_unsigned (frame, i + 0),
1407 (long) get_frame_register_unsigned (frame, i + 1),
1408 (long) get_frame_register_unsigned (frame, i + 2),
1409 (long) get_frame_register_unsigned (frame, i + 3));
1411 printf_filtered ("\n");
1413 for (i = 0; i < 16; i = i + 8)
1415 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1417 (long) get_frame_register_unsigned
1418 (frame, gdbarch_fp0_regnum (gdbarch) + i + 0),
1419 (long) get_frame_register_unsigned
1420 (frame, gdbarch_fp0_regnum (gdbarch) + i + 1),
1421 (long) get_frame_register_unsigned
1422 (frame, gdbarch_fp0_regnum (gdbarch) + i + 2),
1423 (long) get_frame_register_unsigned
1424 (frame, gdbarch_fp0_regnum (gdbarch) + i + 3),
1425 (long) get_frame_register_unsigned
1426 (frame, gdbarch_fp0_regnum (gdbarch) + i + 4),
1427 (long) get_frame_register_unsigned
1428 (frame, gdbarch_fp0_regnum (gdbarch) + i + 5),
1429 (long) get_frame_register_unsigned
1430 (frame, gdbarch_fp0_regnum (gdbarch) + i + 6),
1431 (long) get_frame_register_unsigned
1432 (frame, gdbarch_fp0_regnum (gdbarch) + i + 7));
1435 /* FIXME!!! This only shows the registers for shmedia, excluding the
1436 pseudo registers. */
1438 sh64_show_regs (struct frame_info *frame)
1440 if (pc_is_isa32 (get_frame_pc (frame)))
1441 sh64_show_media_regs (frame);
1443 sh64_show_compact_regs (frame);
1448 SH MEDIA MODE (ISA 32)
1449 general registers (64-bit) 0-63
1450 0 r0, r1, r2, r3, r4, r5, r6, r7,
1451 64 r8, r9, r10, r11, r12, r13, r14, r15,
1452 128 r16, r17, r18, r19, r20, r21, r22, r23,
1453 192 r24, r25, r26, r27, r28, r29, r30, r31,
1454 256 r32, r33, r34, r35, r36, r37, r38, r39,
1455 320 r40, r41, r42, r43, r44, r45, r46, r47,
1456 384 r48, r49, r50, r51, r52, r53, r54, r55,
1457 448 r56, r57, r58, r59, r60, r61, r62, r63,
1462 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1465 target registers (64-bit) 68-75
1466 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1468 floating point state control register (32-bit) 76
1471 single precision floating point registers (32-bit) 77-140
1472 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1473 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1474 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1475 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1476 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1477 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1478 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1479 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1481 TOTAL SPACE FOR REGISTERS: 868 bytes
1483 From here on they are all pseudo registers: no memory allocated.
1484 REGISTER_BYTE returns the register byte for the base register.
1486 double precision registers (pseudo) 141-172
1487 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1488 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1489 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1490 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1492 floating point pairs (pseudo) 173-204
1493 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1494 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1495 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1496 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1498 floating point vectors (4 floating point regs) (pseudo) 205-220
1499 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1500 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1502 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1503 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1504 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1506 gbr_c, mach_c, macl_c, pr_c, t_c,
1508 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1509 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1510 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1511 fv0_c, fv4_c, fv8_c, fv12_c
1514 static struct type *
1515 sh64_build_float_register_type (struct gdbarch *gdbarch, int high)
1517 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
1521 /* Return the GDB type object for the "standard" data type
1522 of data in register REG_NR. */
1523 static struct type *
1524 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
1526 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
1527 && reg_nr <= FP_LAST_REGNUM)
1528 || (reg_nr >= FP0_C_REGNUM
1529 && reg_nr <= FP_LAST_C_REGNUM))
1530 return builtin_type (gdbarch)->builtin_float;
1531 else if ((reg_nr >= DR0_REGNUM
1532 && reg_nr <= DR_LAST_REGNUM)
1533 || (reg_nr >= DR0_C_REGNUM
1534 && reg_nr <= DR_LAST_C_REGNUM))
1535 return builtin_type (gdbarch)->builtin_double;
1536 else if (reg_nr >= FPP0_REGNUM
1537 && reg_nr <= FPP_LAST_REGNUM)
1538 return sh64_build_float_register_type (gdbarch, 1);
1539 else if ((reg_nr >= FV0_REGNUM
1540 && reg_nr <= FV_LAST_REGNUM)
1541 ||(reg_nr >= FV0_C_REGNUM
1542 && reg_nr <= FV_LAST_C_REGNUM))
1543 return sh64_build_float_register_type (gdbarch, 3);
1544 else if (reg_nr == FPSCR_REGNUM)
1545 return builtin_type (gdbarch)->builtin_int;
1546 else if (reg_nr >= R0_C_REGNUM
1547 && reg_nr < FP0_C_REGNUM)
1548 return builtin_type (gdbarch)->builtin_int;
1550 return builtin_type (gdbarch)->builtin_long_long;
1554 sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum,
1555 struct type *type, char *from, char *to)
1557 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1559 /* It is a no-op. */
1560 memcpy (to, from, register_size (gdbarch, regnum));
1564 if ((regnum >= DR0_REGNUM
1565 && regnum <= DR_LAST_REGNUM)
1566 || (regnum >= DR0_C_REGNUM
1567 && regnum <= DR_LAST_C_REGNUM))
1570 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1572 store_typed_floating (to, type, val);
1575 error (_("sh64_register_convert_to_virtual "
1576 "called with non DR register number"));
1580 sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type,
1581 int regnum, const void *from, void *to)
1583 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1585 /* It is a no-op. */
1586 memcpy (to, from, register_size (gdbarch, regnum));
1590 if ((regnum >= DR0_REGNUM
1591 && regnum <= DR_LAST_REGNUM)
1592 || (regnum >= DR0_C_REGNUM
1593 && regnum <= DR_LAST_C_REGNUM))
1595 DOUBLEST val = extract_typed_floating (from, type);
1596 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1600 error (_("sh64_register_convert_to_raw called "
1601 "with non DR register number"));
1605 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1606 int reg_nr, gdb_byte *buffer)
1608 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1612 char temp_buffer[MAX_REGISTER_SIZE];
1614 if (reg_nr >= DR0_REGNUM
1615 && reg_nr <= DR_LAST_REGNUM)
1617 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1619 /* Build the value in the provided buffer. */
1620 /* DR regs are double precision registers obtained by
1621 concatenating 2 single precision floating point registers. */
1622 for (portion = 0; portion < 2; portion++)
1623 regcache_raw_read (regcache, base_regnum + portion,
1625 + register_size (gdbarch, base_regnum) * portion));
1627 /* We must pay attention to the endianness. */
1628 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1629 register_type (gdbarch, reg_nr),
1630 temp_buffer, buffer);
1634 else if (reg_nr >= FPP0_REGNUM
1635 && reg_nr <= FPP_LAST_REGNUM)
1637 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1639 /* Build the value in the provided buffer. */
1640 /* FPP regs are pairs of single precision registers obtained by
1641 concatenating 2 single precision floating point registers. */
1642 for (portion = 0; portion < 2; portion++)
1643 regcache_raw_read (regcache, base_regnum + portion,
1645 + register_size (gdbarch, base_regnum) * portion));
1648 else if (reg_nr >= FV0_REGNUM
1649 && reg_nr <= FV_LAST_REGNUM)
1651 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1653 /* Build the value in the provided buffer. */
1654 /* FV regs are vectors of single precision registers obtained by
1655 concatenating 4 single precision floating point registers. */
1656 for (portion = 0; portion < 4; portion++)
1657 regcache_raw_read (regcache, base_regnum + portion,
1659 + register_size (gdbarch, base_regnum) * portion));
1662 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
1663 else if (reg_nr >= R0_C_REGNUM
1664 && reg_nr <= T_C_REGNUM)
1666 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1668 /* Build the value in the provided buffer. */
1669 regcache_raw_read (regcache, base_regnum, temp_buffer);
1670 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1672 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
1675 else if (reg_nr >= FP0_C_REGNUM
1676 && reg_nr <= FP_LAST_C_REGNUM)
1678 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1680 /* Build the value in the provided buffer. */
1681 /* Floating point registers map 1-1 to the media fp regs,
1682 they have the same size and endianness. */
1683 regcache_raw_read (regcache, base_regnum, buffer);
1686 else if (reg_nr >= DR0_C_REGNUM
1687 && reg_nr <= DR_LAST_C_REGNUM)
1689 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1691 /* DR_C regs are double precision registers obtained by
1692 concatenating 2 single precision floating point registers. */
1693 for (portion = 0; portion < 2; portion++)
1694 regcache_raw_read (regcache, base_regnum + portion,
1696 + register_size (gdbarch, base_regnum) * portion));
1698 /* We must pay attention to the endianness. */
1699 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1700 register_type (gdbarch, reg_nr),
1701 temp_buffer, buffer);
1704 else if (reg_nr >= FV0_C_REGNUM
1705 && reg_nr <= FV_LAST_C_REGNUM)
1707 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1709 /* Build the value in the provided buffer. */
1710 /* FV_C regs are vectors of single precision registers obtained by
1711 concatenating 4 single precision floating point registers. */
1712 for (portion = 0; portion < 4; portion++)
1713 regcache_raw_read (regcache, base_regnum + portion,
1715 + register_size (gdbarch, base_regnum) * portion));
1718 else if (reg_nr == FPSCR_C_REGNUM)
1720 int fpscr_base_regnum;
1722 unsigned int fpscr_value;
1723 unsigned int sr_value;
1724 unsigned int fpscr_c_value;
1725 unsigned int fpscr_c_part1_value;
1726 unsigned int fpscr_c_part2_value;
1728 fpscr_base_regnum = FPSCR_REGNUM;
1729 sr_base_regnum = SR_REGNUM;
1731 /* Build the value in the provided buffer. */
1732 /* FPSCR_C is a very weird register that contains sparse bits
1733 from the FPSCR and the SR architectural registers.
1740 2-17 Bit 2-18 of FPSCR
1741 18-20 Bits 12,13,14 of SR
1745 /* Get FPSCR into a local buffer */
1746 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1747 /* Get value as an int. */
1748 fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1749 /* Get SR into a local buffer */
1750 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1751 /* Get value as an int. */
1752 sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1753 /* Build the new value. */
1754 fpscr_c_part1_value = fpscr_value & 0x3fffd;
1755 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
1756 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
1757 /* Store that in out buffer!!! */
1758 store_unsigned_integer (buffer, 4, byte_order, fpscr_c_value);
1759 /* FIXME There is surely an endianness gotcha here. */
1762 else if (reg_nr == FPUL_C_REGNUM)
1764 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1766 /* FPUL_C register is floating point register 32,
1767 same size, same endianness. */
1768 regcache_raw_read (regcache, base_regnum, buffer);
1773 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1774 int reg_nr, const gdb_byte *buffer)
1776 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1777 int base_regnum, portion;
1779 char temp_buffer[MAX_REGISTER_SIZE];
1781 if (reg_nr >= DR0_REGNUM
1782 && reg_nr <= DR_LAST_REGNUM)
1784 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1785 /* We must pay attention to the endianness. */
1786 sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr),
1788 buffer, temp_buffer);
1790 /* Write the real regs for which this one is an alias. */
1791 for (portion = 0; portion < 2; portion++)
1792 regcache_raw_write (regcache, base_regnum + portion,
1794 + register_size (gdbarch,
1795 base_regnum) * portion));
1798 else if (reg_nr >= FPP0_REGNUM
1799 && reg_nr <= FPP_LAST_REGNUM)
1801 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1803 /* Write the real regs for which this one is an alias. */
1804 for (portion = 0; portion < 2; portion++)
1805 regcache_raw_write (regcache, base_regnum + portion,
1807 + register_size (gdbarch,
1808 base_regnum) * portion));
1811 else if (reg_nr >= FV0_REGNUM
1812 && reg_nr <= FV_LAST_REGNUM)
1814 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1816 /* Write the real regs for which this one is an alias. */
1817 for (portion = 0; portion < 4; portion++)
1818 regcache_raw_write (regcache, base_regnum + portion,
1820 + register_size (gdbarch,
1821 base_regnum) * portion));
1824 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1825 register but only 4 bytes of it. */
1826 else if (reg_nr >= R0_C_REGNUM
1827 && reg_nr <= T_C_REGNUM)
1829 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1830 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1831 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1835 /* Let's read the value of the base register into a temporary
1836 buffer, so that overwriting the last four bytes with the new
1837 value of the pseudo will leave the upper 4 bytes unchanged. */
1838 regcache_raw_read (regcache, base_regnum, temp_buffer);
1839 /* Write as an 8 byte quantity */
1840 memcpy (temp_buffer + offset, buffer, 4);
1841 regcache_raw_write (regcache, base_regnum, temp_buffer);
1844 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1845 registers. Both are 4 bytes. */
1846 else if (reg_nr >= FP0_C_REGNUM
1847 && reg_nr <= FP_LAST_C_REGNUM)
1849 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1850 regcache_raw_write (regcache, base_regnum, buffer);
1853 else if (reg_nr >= DR0_C_REGNUM
1854 && reg_nr <= DR_LAST_C_REGNUM)
1856 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1857 for (portion = 0; portion < 2; portion++)
1859 /* We must pay attention to the endianness. */
1860 sh64_register_convert_to_raw (gdbarch,
1861 register_type (gdbarch, reg_nr),
1863 buffer, temp_buffer);
1865 regcache_raw_write (regcache, base_regnum + portion,
1867 + register_size (gdbarch,
1868 base_regnum) * portion));
1872 else if (reg_nr >= FV0_C_REGNUM
1873 && reg_nr <= FV_LAST_C_REGNUM)
1875 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1877 for (portion = 0; portion < 4; portion++)
1879 regcache_raw_write (regcache, base_regnum + portion,
1881 + register_size (gdbarch,
1882 base_regnum) * portion));
1886 else if (reg_nr == FPSCR_C_REGNUM)
1888 int fpscr_base_regnum;
1890 unsigned int fpscr_value;
1891 unsigned int sr_value;
1892 unsigned int old_fpscr_value;
1893 unsigned int old_sr_value;
1894 unsigned int fpscr_c_value;
1895 unsigned int fpscr_mask;
1896 unsigned int sr_mask;
1898 fpscr_base_regnum = FPSCR_REGNUM;
1899 sr_base_regnum = SR_REGNUM;
1901 /* FPSCR_C is a very weird register that contains sparse bits
1902 from the FPSCR and the SR architectural registers.
1909 2-17 Bit 2-18 of FPSCR
1910 18-20 Bits 12,13,14 of SR
1914 /* Get value as an int. */
1915 fpscr_c_value = extract_unsigned_integer (buffer, 4, byte_order);
1917 /* Build the new values. */
1918 fpscr_mask = 0x0003fffd;
1919 sr_mask = 0x001c0000;
1921 fpscr_value = fpscr_c_value & fpscr_mask;
1922 sr_value = (fpscr_value & sr_mask) >> 6;
1924 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1925 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1926 old_fpscr_value &= 0xfffc0002;
1927 fpscr_value |= old_fpscr_value;
1928 store_unsigned_integer (temp_buffer, 4, byte_order, fpscr_value);
1929 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
1931 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1932 old_sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1933 old_sr_value &= 0xffff8fff;
1934 sr_value |= old_sr_value;
1935 store_unsigned_integer (temp_buffer, 4, byte_order, sr_value);
1936 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
1939 else if (reg_nr == FPUL_C_REGNUM)
1941 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1942 regcache_raw_write (regcache, base_regnum, buffer);
1946 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1947 shmedia REGISTERS. */
1948 /* Control registers, compact mode. */
1950 sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame,
1953 switch (cr_c_regnum)
1956 fprintf_filtered (file, "pc_c\t0x%08x\n",
1957 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1960 fprintf_filtered (file, "gbr_c\t0x%08x\n",
1961 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1964 fprintf_filtered (file, "mach_c\t0x%08x\n",
1965 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1968 fprintf_filtered (file, "macl_c\t0x%08x\n",
1969 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1972 fprintf_filtered (file, "pr_c\t0x%08x\n",
1973 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1976 fprintf_filtered (file, "t_c\t0x%08x\n",
1977 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1979 case FPSCR_C_REGNUM:
1980 fprintf_filtered (file, "fpscr_c\t0x%08x\n",
1981 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1984 fprintf_filtered (file, "fpul_c\t0x%08x\n",
1985 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1991 sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file,
1992 struct frame_info *frame, int regnum)
1993 { /* do values for FP (float) regs */
1994 unsigned char *raw_buffer;
1995 double flt; /* double extracted from raw hex data */
1999 /* Allocate space for the float. */
2000 raw_buffer = (unsigned char *) alloca
2001 (register_size (gdbarch,
2005 /* Get the data in raw format. */
2006 if (!frame_register_read (frame, regnum, raw_buffer))
2007 error (_("can't read register %d (%s)"),
2008 regnum, gdbarch_register_name (gdbarch, regnum));
2010 /* Get the register as a number */
2011 flt = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer, &inv);
2013 /* Print the name and some spaces. */
2014 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
2015 print_spaces_filtered (15 - strlen (gdbarch_register_name
2016 (gdbarch, regnum)), file);
2018 /* Print the value. */
2020 fprintf_filtered (file, "<invalid float>");
2022 fprintf_filtered (file, "%-10.9g", flt);
2024 /* Print the fp register as hex. */
2025 fprintf_filtered (file, "\t(raw 0x");
2026 for (j = 0; j < register_size (gdbarch, regnum); j++)
2028 int idx = gdbarch_byte_order (gdbarch)
2029 == BFD_ENDIAN_BIG ? j : register_size
2030 (gdbarch, regnum) - 1 - j;
2031 fprintf_filtered (file, "%02x", raw_buffer[idx]);
2033 fprintf_filtered (file, ")");
2034 fprintf_filtered (file, "\n");
2038 sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
2039 struct frame_info *frame, int regnum)
2041 /* All the sh64-compact mode registers are pseudo registers. */
2043 if (regnum < gdbarch_num_regs (gdbarch)
2044 || regnum >= gdbarch_num_regs (gdbarch)
2045 + NUM_PSEUDO_REGS_SH_MEDIA
2046 + NUM_PSEUDO_REGS_SH_COMPACT)
2047 internal_error (__FILE__, __LINE__,
2048 _("Invalid pseudo register number %d\n"), regnum);
2050 else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM))
2052 int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum);
2053 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM,
2054 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2055 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2058 else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM))
2060 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2061 fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM,
2062 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2063 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2066 else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM))
2068 int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum);
2069 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2070 regnum - FV0_REGNUM,
2071 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2072 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2073 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2074 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2077 else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM))
2079 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2080 fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2081 regnum - FV0_C_REGNUM,
2082 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2083 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2084 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2085 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2088 else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM)
2090 int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum);
2091 fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM,
2092 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2093 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2096 else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM)
2098 int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2099 fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM,
2100 (unsigned) get_frame_register_unsigned (frame, c_regnum));
2102 else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM)
2103 /* This should work also for pseudoregs. */
2104 sh64_do_fp_register (gdbarch, file, frame, regnum);
2105 else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM)
2106 sh64_do_cr_c_register_info (file, frame, regnum);
2110 sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file,
2111 struct frame_info *frame, int regnum)
2113 unsigned char raw_buffer[MAX_REGISTER_SIZE];
2114 struct value_print_options opts;
2116 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
2117 print_spaces_filtered (15 - strlen (gdbarch_register_name
2118 (gdbarch, regnum)), file);
2120 /* Get the data in raw format. */
2121 if (!frame_register_read (frame, regnum, raw_buffer))
2122 fprintf_filtered (file, "*value not available*\n");
2124 get_formatted_print_options (&opts, 'x');
2126 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2127 file, 0, NULL, &opts, current_language);
2128 fprintf_filtered (file, "\t");
2129 get_formatted_print_options (&opts, 0);
2131 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2132 file, 0, NULL, &opts, current_language);
2133 fprintf_filtered (file, "\n");
2137 sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file,
2138 struct frame_info *frame, int regnum)
2140 if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch)
2141 + gdbarch_num_pseudo_regs (gdbarch))
2142 internal_error (__FILE__, __LINE__,
2143 _("Invalid register number %d\n"), regnum);
2145 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
2147 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2148 sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */
2150 sh64_do_register (gdbarch, file, frame, regnum);
2153 else if (regnum < gdbarch_num_regs (gdbarch)
2154 + gdbarch_num_pseudo_regs (gdbarch))
2155 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2159 sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2160 struct frame_info *frame, int regnum,
2163 if (regnum != -1) /* do one specified register */
2165 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2166 error (_("Not a valid register for the current processor type"));
2168 sh64_print_register (gdbarch, file, frame, regnum);
2171 /* do all (or most) registers */
2174 while (regnum < gdbarch_num_regs (gdbarch))
2176 /* If the register name is empty, it is undefined for this
2177 processor, so don't display anything. */
2178 if (gdbarch_register_name (gdbarch, regnum) == NULL
2179 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
2185 if (TYPE_CODE (register_type (gdbarch, regnum))
2190 /* true for "INFO ALL-REGISTERS" command */
2191 sh64_do_fp_register (gdbarch, file, frame, regnum);
2195 regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch);
2200 sh64_do_register (gdbarch, file, frame, regnum);
2206 while (regnum < gdbarch_num_regs (gdbarch)
2207 + gdbarch_num_pseudo_regs (gdbarch))
2209 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2216 sh64_compact_print_registers_info (struct gdbarch *gdbarch,
2217 struct ui_file *file,
2218 struct frame_info *frame, int regnum,
2221 if (regnum != -1) /* do one specified register */
2223 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2224 error (_("Not a valid register for the current processor type"));
2226 if (regnum >= 0 && regnum < R0_C_REGNUM)
2227 error (_("Not a valid register for the current processor mode."));
2229 sh64_print_register (gdbarch, file, frame, regnum);
2232 /* do all compact registers */
2234 regnum = R0_C_REGNUM;
2235 while (regnum < gdbarch_num_regs (gdbarch)
2236 + gdbarch_num_pseudo_regs (gdbarch))
2238 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2245 sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2246 struct frame_info *frame, int regnum, int fpregs)
2248 if (pc_is_isa32 (get_frame_pc (frame)))
2249 sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2251 sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2254 static struct sh64_frame_cache *
2255 sh64_alloc_frame_cache (void)
2257 struct sh64_frame_cache *cache;
2260 cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache);
2264 cache->saved_sp = 0;
2265 cache->sp_offset = 0;
2268 /* Frameless until proven otherwise. */
2271 /* Saved registers. We initialize these to -1 since zero is a valid
2272 offset (that's where fp is supposed to be stored). */
2273 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2275 cache->saved_regs[i] = -1;
2281 static struct sh64_frame_cache *
2282 sh64_frame_cache (struct frame_info *this_frame, void **this_cache)
2284 struct gdbarch *gdbarch;
2285 struct sh64_frame_cache *cache;
2286 CORE_ADDR current_pc;
2292 gdbarch = get_frame_arch (this_frame);
2293 cache = sh64_alloc_frame_cache ();
2294 *this_cache = cache;
2296 current_pc = get_frame_pc (this_frame);
2297 cache->media_mode = pc_is_isa32 (current_pc);
2299 /* In principle, for normal frames, fp holds the frame pointer,
2300 which holds the base address for the current stack frame.
2301 However, for functions that don't need it, the frame pointer is
2302 optional. For these "frameless" functions the frame pointer is
2303 actually the frame pointer of the calling frame. */
2304 cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM);
2305 if (cache->base == 0)
2308 cache->pc = get_frame_func (this_frame);
2310 sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc);
2312 if (!cache->uses_fp)
2314 /* We didn't find a valid frame, which means that CACHE->base
2315 currently holds the frame pointer for our calling frame. If
2316 we're at the start of a function, or somewhere half-way its
2317 prologue, the function's frame probably hasn't been fully
2318 setup yet. Try to reconstruct the base address for the stack
2319 frame by looking at the stack pointer. For truly "frameless"
2320 functions this might work too. */
2321 cache->base = get_frame_register_unsigned
2322 (this_frame, gdbarch_sp_regnum (gdbarch));
2325 /* Now that we have the base address for the stack frame we can
2326 calculate the value of sp in the calling frame. */
2327 cache->saved_sp = cache->base + cache->sp_offset;
2329 /* Adjust all the saved registers such that they contain addresses
2330 instead of offsets. */
2331 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2332 if (cache->saved_regs[i] != -1)
2333 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i];
2338 static struct value *
2339 sh64_frame_prev_register (struct frame_info *this_frame,
2340 void **this_cache, int regnum)
2342 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2343 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2344 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2346 gdb_assert (regnum >= 0);
2348 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2349 frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2351 /* The PC of the previous frame is stored in the PR register of
2352 the current frame. Frob regnum so that we pull the value from
2353 the correct place. */
2354 if (regnum == gdbarch_pc_regnum (gdbarch))
2357 if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1)
2359 if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32
2360 && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM))
2363 val = read_memory_unsigned_integer (cache->saved_regs[regnum],
2365 return frame_unwind_got_constant (this_frame, regnum, val);
2368 return frame_unwind_got_memory (this_frame, regnum,
2369 cache->saved_regs[regnum]);
2372 return frame_unwind_got_register (this_frame, regnum, regnum);
2376 sh64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2377 struct frame_id *this_id)
2379 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2381 /* This marks the outermost frame. */
2382 if (cache->base == 0)
2385 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2388 static const struct frame_unwind sh64_frame_unwind = {
2391 sh64_frame_prev_register,
2393 default_frame_sniffer
2397 sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2399 return frame_unwind_register_unsigned (next_frame,
2400 gdbarch_sp_regnum (gdbarch));
2404 sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2406 return frame_unwind_register_unsigned (next_frame,
2407 gdbarch_pc_regnum (gdbarch));
2410 static struct frame_id
2411 sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2413 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2414 gdbarch_sp_regnum (gdbarch));
2415 return frame_id_build (sp, get_frame_pc (this_frame));
2419 sh64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2421 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2426 static const struct frame_base sh64_frame_base = {
2428 sh64_frame_base_address,
2429 sh64_frame_base_address,
2430 sh64_frame_base_address
2435 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2437 struct gdbarch *gdbarch;
2438 struct gdbarch_tdep *tdep;
2440 /* If there is already a candidate, use it. */
2441 arches = gdbarch_list_lookup_by_info (arches, &info);
2443 return arches->gdbarch;
2445 /* None found, create a new architecture from the information
2447 tdep = XMALLOC (struct gdbarch_tdep);
2448 gdbarch = gdbarch_alloc (&info, tdep);
2450 /* Determine the ABI */
2451 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2453 /* If the ABI is the 64-bit one, it can only be sh-media. */
2454 tdep->sh_abi = SH_ABI_64;
2455 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2456 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2460 /* If the ABI is the 32-bit one it could be either media or
2462 tdep->sh_abi = SH_ABI_32;
2463 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2464 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2467 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2468 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2469 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2470 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2471 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2472 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2473 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2475 /* The number of real registers is the same whether we are in
2476 ISA16(compact) or ISA32(media). */
2477 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2478 set_gdbarch_sp_regnum (gdbarch, 15);
2479 set_gdbarch_pc_regnum (gdbarch, 64);
2480 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2481 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA
2482 + NUM_PSEUDO_REGS_SH_COMPACT);
2484 set_gdbarch_register_name (gdbarch, sh64_register_name);
2485 set_gdbarch_register_type (gdbarch, sh64_register_type);
2487 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2488 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2490 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
2492 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2493 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2495 set_gdbarch_return_value (gdbarch, sh64_return_value);
2497 set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue);
2498 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2500 set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call);
2502 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2504 set_gdbarch_frame_align (gdbarch, sh64_frame_align);
2505 set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp);
2506 set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc);
2507 set_gdbarch_dummy_id (gdbarch, sh64_dummy_id);
2508 frame_base_set_default (gdbarch, &sh64_frame_base);
2510 set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info);
2512 set_gdbarch_elf_make_msymbol_special (gdbarch,
2513 sh64_elf_make_msymbol_special);
2515 /* Hook in ABI-specific overrides, if they have been registered. */
2516 gdbarch_init_osabi (info, gdbarch);
2518 dwarf2_append_unwinders (gdbarch);
2519 frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind);