1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 Contributed by Steve Chamberlain
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
38 #include "gdb_string.h"
39 #include "gdb_assert.h"
40 #include "arch-utils.h"
49 /* registers numbers shared with the simulator */
50 #include "gdb/sim-sh.h"
53 /* Information that is dependent on the processor variant. */
66 struct sh64_frame_cache
73 /* Flag showing that a frame has been created in the prologue code. */
78 /* Saved registers. */
79 CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
83 /* Registers of SH5 */
87 DEFAULT_RETURN_REGNUM = 2,
88 STRUCT_RETURN_REGNUM = 2,
91 FLOAT_ARGLAST_REGNUM = 11,
97 /* FPP stands for Floating Point Pair, to avoid confusion with
98 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
99 point register. Unfortunately on the sh5, the floating point
100 registers are called FR, and the floating point pairs are called FP. */
102 FPP_LAST_REGNUM = 204,
104 FV_LAST_REGNUM = 220,
106 R_LAST_C_REGNUM = 236,
113 FPSCR_C_REGNUM = 243,
116 FP_LAST_C_REGNUM = 260,
118 DR_LAST_C_REGNUM = 268,
120 FV_LAST_C_REGNUM = 272,
121 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
122 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
123 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
124 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
125 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
129 sh64_register_name (struct gdbarch *gdbarch, int reg_nr)
131 static char *register_names[] =
133 /* SH MEDIA MODE (ISA 32) */
134 /* general registers (64-bit) 0-63 */
135 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
136 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
137 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
138 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
139 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
140 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
141 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
142 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
147 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
150 /* target registers (64-bit) 68-75*/
151 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
153 /* floating point state control register (32-bit) 76 */
156 /* single precision floating point registers (32-bit) 77-140*/
157 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
158 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
159 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
160 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
161 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
162 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
163 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
164 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
166 /* double precision registers (pseudo) 141-172 */
167 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
168 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
169 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
170 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
172 /* floating point pairs (pseudo) 173-204*/
173 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
174 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
175 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
176 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
178 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
179 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
180 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
182 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
183 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
184 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
186 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
188 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
189 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
190 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
191 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
192 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return register_names[reg_nr];
202 #define NUM_PSEUDO_REGS_SH_MEDIA 80
203 #define NUM_PSEUDO_REGS_SH_COMPACT 51
205 /* Macros and functions for setting and testing a bit in a minimal
206 symbol that marks it as 32-bit function. The MSB of the minimal
207 symbol's "info" field is used for this purpose.
209 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
210 i.e. refers to a 32-bit function, and sets a "special" bit in a
211 minimal symbol to mark it as a 32-bit function
212 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
214 #define MSYMBOL_IS_SPECIAL(msym) \
215 MSYMBOL_TARGET_FLAG_1 (msym)
218 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
223 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
225 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
226 SYMBOL_VALUE_ADDRESS (msym) |= 1;
230 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
231 are some macros to test, set, or clear bit 0 of addresses. */
232 #define IS_ISA32_ADDR(addr) ((addr) & 1)
233 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
234 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
237 pc_is_isa32 (bfd_vma memaddr)
239 struct minimal_symbol *sym;
241 /* If bit 0 of the address is set, assume this is a
242 ISA32 (shmedia) address. */
243 if (IS_ISA32_ADDR (memaddr))
246 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
247 the high bit of the info field. Use this to decide if the function is
249 sym = lookup_minimal_symbol_by_pc (memaddr);
251 return MSYMBOL_IS_SPECIAL (sym);
256 static const unsigned char *
257 sh64_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
259 /* The BRK instruction for shmedia is
260 01101111 11110101 11111111 11110000
261 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
262 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
264 /* The BRK instruction for shcompact is
266 which translates in big endian mode to 0x0, 0x3b
267 and in little endian mode to 0x3b, 0x0*/
269 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
271 if (pc_is_isa32 (*pcptr))
273 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
274 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
275 *lenptr = sizeof (big_breakpoint_media);
276 return big_breakpoint_media;
280 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
281 *lenptr = sizeof (big_breakpoint_compact);
282 return big_breakpoint_compact;
287 if (pc_is_isa32 (*pcptr))
289 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
290 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
291 *lenptr = sizeof (little_breakpoint_media);
292 return little_breakpoint_media;
296 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
297 *lenptr = sizeof (little_breakpoint_compact);
298 return little_breakpoint_compact;
303 /* Prologue looks like
304 [mov.l <regs>,@-r15]...
309 Actually it can be more complicated than this. For instance, with
327 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
328 with l=1 and n = 18 0110101111110001010010100aaa0000 */
329 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
331 /* STS.L PR,@-r0 0100000000100010
332 r0-4-->r0, PR-->(r0) */
333 #define IS_STS_R0(x) ((x) == 0x4022)
335 /* STS PR, Rm 0000mmmm00101010
337 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
339 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
341 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
343 /* MOV.L R14,@(disp,r15) 000111111110dddd
344 R14-->(dispx4+r15) */
345 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
347 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
348 R18-->(dispx8+R14) */
349 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
351 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
352 R18-->(dispx8+R15) */
353 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
355 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
356 R18-->(dispx4+R15) */
357 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
359 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
360 R14-->(dispx8+R15) */
361 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
363 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
364 R14-->(dispx4+R15) */
365 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
367 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
369 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
371 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
373 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
375 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
377 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
379 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
381 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
383 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
385 /* MOV #imm, R0 1110 0000 ssss ssss
387 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
389 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
390 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
392 /* ADD r15,r0 0011 0000 1111 1100
394 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
396 /* MOV.L R14 @-R0 0010 0000 1110 0110
397 R14-->(R0-4), R0-4-->R0 */
398 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
400 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
401 where Rm is one of r2-r9 which are the argument registers. */
402 /* FIXME: Recognize the float and double register moves too! */
403 #define IS_MEDIA_IND_ARG_MOV(x) \
404 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
406 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
407 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
408 where Rm is one of r2-r9 which are the argument registers. */
409 #define IS_MEDIA_ARG_MOV(x) \
410 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
411 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
413 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
414 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
415 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
416 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
417 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
418 #define IS_MEDIA_MOV_TO_R14(x) \
419 ((((x) & 0xfffffc0f) == 0xa0e00000) \
420 || (((x) & 0xfffffc0f) == 0xa4e00000) \
421 || (((x) & 0xfffffc0f) == 0xa8e00000) \
422 || (((x) & 0xfffffc0f) == 0xb4e00000) \
423 || (((x) & 0xfffffc0f) == 0xbce00000))
425 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
427 #define IS_COMPACT_IND_ARG_MOV(x) \
428 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
430 /* compact direct arg move!
431 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
432 #define IS_COMPACT_ARG_MOV(x) \
433 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
435 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
436 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
437 #define IS_COMPACT_MOV_TO_R14(x) \
438 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
440 #define IS_JSR_R0(x) ((x) == 0x400b)
441 #define IS_NOP(x) ((x) == 0x0009)
444 /* MOV r15,r14 0110111011110011
446 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
448 /* ADD #imm,r15 01111111iiiiiiii
450 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
452 /* Skip any prologue before the guts of a function */
454 /* Skip the prologue using the debug information. If this fails we'll
455 fall back on the 'guess' method below. */
457 after_prologue (CORE_ADDR pc)
459 struct symtab_and_line sal;
460 CORE_ADDR func_addr, func_end;
462 /* If we can not find the symbol in the partial symbol table, then
463 there is no hope we can determine the function's start address
465 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
469 /* Get the line associated with FUNC_ADDR. */
470 sal = find_pc_line (func_addr, 0);
472 /* There are only two cases to consider. First, the end of the source line
473 is within the function bounds. In that case we return the end of the
474 source line. Second is the end of the source line extends beyond the
475 bounds of the current function. We need to use the slow code to
476 examine instructions in that case. */
477 if (sal.end < func_end)
484 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
488 int insn_size = (media_mode ? 4 : 2);
490 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
494 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
496 if (IS_MEDIA_IND_ARG_MOV (w))
498 /* This must be followed by a store to r14, so the argument
499 is where the debug info says it is. This can happen after
500 the SP has been saved, unfortunately. */
502 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
505 if (IS_MEDIA_MOV_TO_R14 (next_insn))
508 else if (IS_MEDIA_ARG_MOV (w))
510 /* These instructions store directly the argument in r14. */
518 w = read_memory_integer (here, insn_size);
521 if (IS_COMPACT_IND_ARG_MOV (w))
523 /* This must be followed by a store to r14, so the argument
524 is where the debug info says it is. This can happen after
525 the SP has been saved, unfortunately. */
527 int next_insn = 0xffff & read_memory_integer (here, insn_size);
529 if (IS_COMPACT_MOV_TO_R14 (next_insn))
532 else if (IS_COMPACT_ARG_MOV (w))
534 /* These instructions store directly the argument in r14. */
537 else if (IS_MOVL_R0 (w))
539 /* There is a function that gcc calls to get the arguments
540 passed correctly to the function. Only after this
541 function call the arguments will be found at the place
542 where they are supposed to be. This happens in case the
543 argument has to be stored into a 64-bit register (for
544 instance doubles, long longs). SHcompact doesn't have
545 access to the full 64-bits, so we store the register in
546 stack slot and store the address of the stack slot in
547 the register, then do a call through a wrapper that
548 loads the memory value into the register. A SHcompact
549 callee calls an argument decoder
550 (GCC_shcompact_incoming_args) that stores the 64-bit
551 value in a stack slot and stores the address of the
552 stack slot in the register. GCC thinks the argument is
553 just passed by transparent reference, but this is only
554 true after the argument decoder is called. Such a call
555 needs to be considered part of the prologue. */
557 /* This must be followed by a JSR @r0 instruction and by
558 a NOP instruction. After these, the prologue is over! */
560 int next_insn = 0xffff & read_memory_integer (here, insn_size);
562 if (IS_JSR_R0 (next_insn))
564 next_insn = 0xffff & read_memory_integer (here, insn_size);
567 if (IS_NOP (next_insn))
580 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
590 if (pc_is_isa32 (start_pc) == 0)
596 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
601 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
603 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
604 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
605 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
609 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
617 /* Don't bail out yet, we may have arguments stored in
618 registers here, according to the debug info, so that
619 gdb can print the frames correctly. */
620 start_pc = look_for_args_moves (here - insn_size, media_mode);
626 int w = 0xffff & read_memory_integer (here, insn_size);
629 if (IS_STS_R0 (w) || IS_STS_PR (w)
630 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
631 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
635 else if (IS_MOV_SP_FP (w))
643 /* Don't bail out yet, we may have arguments stored in
644 registers here, according to the debug info, so that
645 gdb can print the frames correctly. */
646 start_pc = look_for_args_moves (here - insn_size, media_mode);
656 sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
658 CORE_ADDR post_prologue_pc;
660 /* See if we can determine the end of the prologue via the symbol table.
661 If so, then return either PC, or the PC after the prologue, whichever
663 post_prologue_pc = after_prologue (pc);
665 /* If after_prologue returned a useful address, then use it. Else
666 fall back on the instruction skipping code. */
667 if (post_prologue_pc != 0)
668 return max (pc, post_prologue_pc);
670 return sh64_skip_prologue_hard_way (pc);
673 /* Should call_function allocate stack space for a struct return? */
675 sh64_use_struct_convention (struct type *type)
677 return (TYPE_LENGTH (type) > 8);
680 /* For vectors of 4 floating point registers. */
682 sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
686 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4;
690 /* For double precision floating point registers, i.e 2 fp regs.*/
692 sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
696 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2;
700 /* For pairs of floating point registers */
702 sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum)
706 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2;
712 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
713 GDB_REGNUM BASE_REGNUM
773 sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr)
775 int base_regnum = reg_nr;
777 /* general register N maps to general register N */
778 if (reg_nr >= R0_C_REGNUM
779 && reg_nr <= R_LAST_C_REGNUM)
780 base_regnum = reg_nr - R0_C_REGNUM;
782 /* floating point register N maps to floating point register N */
783 else if (reg_nr >= FP0_C_REGNUM
784 && reg_nr <= FP_LAST_C_REGNUM)
785 base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch);
787 /* double prec register N maps to base regnum for double prec register N */
788 else if (reg_nr >= DR0_C_REGNUM
789 && reg_nr <= DR_LAST_C_REGNUM)
790 base_regnum = sh64_dr_reg_base_num (gdbarch,
791 DR0_REGNUM + reg_nr - DR0_C_REGNUM);
793 /* vector N maps to base regnum for vector register N */
794 else if (reg_nr >= FV0_C_REGNUM
795 && reg_nr <= FV_LAST_C_REGNUM)
796 base_regnum = sh64_fv_reg_base_num (gdbarch,
797 FV0_REGNUM + reg_nr - FV0_C_REGNUM);
799 else if (reg_nr == PC_C_REGNUM)
800 base_regnum = gdbarch_pc_regnum (gdbarch);
802 else if (reg_nr == GBR_C_REGNUM)
805 else if (reg_nr == MACH_C_REGNUM
806 || reg_nr == MACL_C_REGNUM)
809 else if (reg_nr == PR_C_REGNUM)
810 base_regnum = PR_REGNUM;
812 else if (reg_nr == T_C_REGNUM)
815 else if (reg_nr == FPSCR_C_REGNUM)
816 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
818 else if (reg_nr == FPUL_C_REGNUM)
819 base_regnum = gdbarch_fp0_regnum (gdbarch) + 32;
825 sign_extend (int value, int bits)
827 value = value & ((1 << bits) - 1);
828 return (value & (1 << (bits - 1))
829 ? value | (~((1 << bits) - 1))
834 sh64_analyze_prologue (struct gdbarch *gdbarch,
835 struct sh64_frame_cache *cache,
837 CORE_ADDR current_pc)
845 int gdb_register_number;
847 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
849 cache->sp_offset = 0;
851 /* Loop around examining the prologue insns until we find something
852 that does not appear to be part of the prologue. But give up
853 after 20 of them, since we're getting silly then. */
857 if (cache->media_mode)
862 opc = pc + (insn_size * 28);
863 if (opc > current_pc)
865 for ( ; pc <= opc; pc += insn_size)
867 insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
871 if (!cache->media_mode)
873 if (IS_STS_PR (insn))
875 int next_insn = read_memory_integer (pc + insn_size, insn_size);
876 if (IS_MOV_TO_R15 (next_insn))
878 cache->saved_regs[PR_REGNUM] =
879 cache->sp_offset - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
884 else if (IS_MOV_R14 (insn))
885 cache->saved_regs[MEDIA_FP_REGNUM] =
886 cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
888 else if (IS_MOV_R0 (insn))
890 /* Put in R0 the offset from SP at which to store some
891 registers. We are interested in this value, because it
892 will tell us where the given registers are stored within
894 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
897 else if (IS_ADD_SP_R0 (insn))
899 /* This instruction still prepares r0, but we don't care.
900 We already have the offset in r0_val. */
903 else if (IS_STS_R0 (insn))
905 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
906 cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
910 else if (IS_MOV_R14_R0 (insn))
912 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
913 cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
918 else if (IS_ADD_SP (insn))
919 cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
921 else if (IS_MOV_SP_FP (insn))
926 if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
928 sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
930 else if (IS_STQ_R18_R15 (insn))
931 cache->saved_regs[PR_REGNUM] =
932 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
934 else if (IS_STL_R18_R15 (insn))
935 cache->saved_regs[PR_REGNUM] =
936 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
938 else if (IS_STQ_R14_R15 (insn))
939 cache->saved_regs[MEDIA_FP_REGNUM] =
940 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
942 else if (IS_STL_R14_R15 (insn))
943 cache->saved_regs[MEDIA_FP_REGNUM] =
944 cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
946 else if (IS_MOV_SP_FP_MEDIA (insn))
951 if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0)
956 sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
961 /* Function: push_dummy_call
962 Setup the function arguments for calling a function in the inferior.
964 On the Renesas SH architecture, there are four registers (R4 to R7)
965 which are dedicated for passing function arguments. Up to the first
966 four arguments (depending on size) may go into these registers.
967 The rest go on the stack.
969 Arguments that are smaller than 4 bytes will still take up a whole
970 register or a whole 32-bit word on the stack, and will be
971 right-justified in the register or the stack word. This includes
972 chars, shorts, and small aggregate types.
974 Arguments that are larger than 4 bytes may be split between two or
975 more registers. If there are not enough registers free, an argument
976 may be passed partly in a register (or registers), and partly on the
977 stack. This includes doubles, long longs, and larger aggregates.
978 As far as I know, there is no upper limit to the size of aggregates
979 that will be passed in this way; in other words, the convention of
980 passing a pointer to a large aggregate instead of a copy is not used.
982 An exceptional case exists for struct arguments (and possibly other
983 aggregates such as arrays) if the size is larger than 4 bytes but
984 not a multiple of 4 bytes. In this case the argument is never split
985 between the registers and the stack, but instead is copied in its
986 entirety onto the stack, AND also copied into as many registers as
987 there is room for. In other words, space in registers permitting,
988 two copies of the same argument are passed in. As far as I can tell,
989 only the one on the stack is used, although that may be a function
990 of the level of compiler optimization. I suspect this is a compiler
991 bug. Arguments of these odd sizes are left-justified within the
992 word (as opposed to arguments smaller than 4 bytes, which are
995 If the function is to return an aggregate type such as a struct, it
996 is either returned in the normal return value register R0 (if its
997 size is no greater than one byte), or else the caller must allocate
998 space into which the callee will copy the return value (if the size
999 is greater than one byte). In this case, a pointer to the return
1000 value location is passed into the callee in register R2, which does
1001 not displace any of the other arguments passed in via registers R4
1004 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1005 non-scalar (struct, union) elements (even if the elements are
1007 FR0-FR11 for single precision floating point (float)
1008 DR0-DR10 for double precision floating point (double)
1010 If a float is argument number 3 (for instance) and arguments number
1011 1,2, and 4 are integer, the mapping will be:
1012 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1014 If a float is argument number 10 (for instance) and arguments number
1015 1 through 10 are integer, the mapping will be:
1016 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1017 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1018 I.e. there is hole in the stack.
1020 Different rules apply for variable arguments functions, and for functions
1021 for which the prototype is not known. */
1024 sh64_push_dummy_call (struct gdbarch *gdbarch,
1025 struct value *function,
1026 struct regcache *regcache,
1028 int nargs, struct value **args,
1029 CORE_ADDR sp, int struct_return,
1030 CORE_ADDR struct_addr)
1032 int stack_offset, stack_alloc;
1036 int float_arg_index = 0;
1037 int double_arg_index = 0;
1048 memset (fp_args, 0, sizeof (fp_args));
1050 /* first force sp to a 8-byte alignment */
1051 sp = sh64_frame_align (gdbarch, sp);
1053 /* The "struct return pointer" pseudo-argument has its own dedicated
1057 regcache_cooked_write_unsigned (regcache,
1058 STRUCT_RETURN_REGNUM, struct_addr);
1060 /* Now make sure there's space on the stack */
1061 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1062 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
1063 sp -= stack_alloc; /* make room on stack for args */
1065 /* Now load as many as possible of the first arguments into
1066 registers, and push the rest onto the stack. There are 64 bytes
1067 in eight registers available. Loop thru args from first to last. */
1069 int_argreg = ARG0_REGNUM;
1070 float_argreg = gdbarch_fp0_regnum (gdbarch);
1071 double_argreg = DR0_REGNUM;
1073 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1075 type = value_type (args[argnum]);
1076 len = TYPE_LENGTH (type);
1077 memset (valbuf, 0, sizeof (valbuf));
1079 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1081 argreg_size = register_size (gdbarch, int_argreg);
1083 if (len < argreg_size)
1085 /* value gets right-justified in the register or stack word */
1086 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1087 memcpy (valbuf + argreg_size - len,
1088 (char *) value_contents (args[argnum]), len);
1090 memcpy (valbuf, (char *) value_contents (args[argnum]), len);
1095 val = (char *) value_contents (args[argnum]);
1099 if (int_argreg > ARGLAST_REGNUM)
1101 /* must go on the stack */
1102 write_memory (sp + stack_offset, (const bfd_byte *) val,
1104 stack_offset += 8;/*argreg_size;*/
1106 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1107 That's because some *&^%$ things get passed on the stack
1108 AND in the registers! */
1109 if (int_argreg <= ARGLAST_REGNUM)
1111 /* there's room in a register */
1112 regval = extract_unsigned_integer (val, argreg_size);
1113 regcache_cooked_write_unsigned (regcache, int_argreg, regval);
1115 /* Store the value 8 bytes at a time. This means that
1116 things larger than 8 bytes may go partly in registers
1117 and partly on the stack. FIXME: argreg is incremented
1118 before we use its size. */
1126 val = (char *) value_contents (args[argnum]);
1129 /* Where is it going to be stored? */
1130 while (fp_args[float_arg_index])
1133 /* Now float_argreg points to the register where it
1134 should be stored. Are we still within the allowed
1136 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1138 /* Goes in FR0...FR11 */
1139 regcache_cooked_write (regcache,
1140 gdbarch_fp0_regnum (gdbarch)
1143 fp_args[float_arg_index] = 1;
1144 /* Skip the corresponding general argument register. */
1149 /* Store it as the integers, 8 bytes at the time, if
1150 necessary spilling on the stack. */
1155 /* Where is it going to be stored? */
1156 while (fp_args[double_arg_index])
1157 double_arg_index += 2;
1158 /* Now double_argreg points to the register
1159 where it should be stored.
1160 Are we still within the allowed register set? */
1161 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1163 /* Goes in DR0...DR10 */
1164 /* The numbering of the DRi registers is consecutive,
1165 i.e. includes odd numbers. */
1166 int double_register_offset = double_arg_index / 2;
1167 int regnum = DR0_REGNUM + double_register_offset;
1168 regcache_cooked_write (regcache, regnum, val);
1169 fp_args[double_arg_index] = 1;
1170 fp_args[double_arg_index + 1] = 1;
1171 /* Skip the corresponding general argument register. */
1176 /* Store it as the integers, 8 bytes at the time, if
1177 necessary spilling on the stack. */
1181 /* Store return address. */
1182 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1184 /* Update stack pointer. */
1185 regcache_cooked_write_unsigned (regcache,
1186 gdbarch_sp_regnum (gdbarch), sp);
1191 /* Find a function's return value in the appropriate registers (in
1192 regbuf), and copy it into valbuf. Extract from an array REGBUF
1193 containing the (raw) register state a function return value of type
1194 TYPE, and copy that, in virtual format, into VALBUF. */
1196 sh64_extract_return_value (struct type *type, struct regcache *regcache,
1199 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1200 int len = TYPE_LENGTH (type);
1202 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1206 /* Return value stored in gdbarch_fp0_regnum */
1207 regcache_raw_read (regcache,
1208 gdbarch_fp0_regnum (gdbarch), valbuf);
1212 /* return value stored in DR0_REGNUM */
1216 regcache_cooked_read (regcache, DR0_REGNUM, buf);
1218 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1219 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1222 floatformat_to_doublest (&floatformat_ieee_double_big,
1224 store_typed_floating (valbuf, type, val);
1233 /* Result is in register 2. If smaller than 8 bytes, it is padded
1234 at the most significant end. */
1235 regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf);
1237 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1238 offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM)
1242 memcpy (valbuf, buf + offset, len);
1245 error ("bad size for return value");
1249 /* Write into appropriate registers a function return value
1250 of type TYPE, given in virtual format.
1251 If the architecture is sh4 or sh3e, store a function's return value
1252 in the R0 general register or in the FP0 floating point register,
1253 depending on the type of the return value. In all the other cases
1254 the result is stored in r0, left-justified. */
1257 sh64_store_return_value (struct type *type, struct regcache *regcache,
1260 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1261 char buf[64]; /* more than enough... */
1262 int len = TYPE_LENGTH (type);
1264 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1266 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1267 for (i = 0; i < len; i += 4)
1268 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1269 regcache_raw_write (regcache, regnum++,
1270 (char *) valbuf + len - 4 - i);
1272 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1276 int return_register = DEFAULT_RETURN_REGNUM;
1279 if (len <= register_size (gdbarch, return_register))
1281 /* Pad with zeros. */
1282 memset (buf, 0, register_size (gdbarch, return_register));
1283 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1284 offset = 0; /*register_size (gdbarch,
1285 return_register) - len;*/
1287 offset = register_size (gdbarch, return_register) - len;
1289 memcpy (buf + offset, valbuf, len);
1290 regcache_raw_write (regcache, return_register, buf);
1293 regcache_raw_write (regcache, return_register, valbuf);
1297 static enum return_value_convention
1298 sh64_return_value (struct gdbarch *gdbarch, struct type *func_type,
1299 struct type *type, struct regcache *regcache,
1300 gdb_byte *readbuf, const gdb_byte *writebuf)
1302 if (sh64_use_struct_convention (type))
1303 return RETURN_VALUE_STRUCT_CONVENTION;
1305 sh64_store_return_value (type, regcache, writebuf);
1307 sh64_extract_return_value (type, regcache, readbuf);
1308 return RETURN_VALUE_REGISTER_CONVENTION;
1312 sh64_show_media_regs (struct frame_info *frame)
1314 struct gdbarch *gdbarch = get_frame_arch (frame);
1318 ("PC=%s SR=%016llx \n",
1319 paddr (get_frame_register_unsigned (frame,
1320 gdbarch_pc_regnum (gdbarch))),
1321 (long long) get_frame_register_unsigned (frame, SR_REGNUM));
1324 ("SSR=%016llx SPC=%016llx \n",
1325 (long long) get_frame_register_unsigned (frame, SSR_REGNUM),
1326 (long long) get_frame_register_unsigned (frame, SPC_REGNUM));
1329 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1331 for (i = 0; i < 64; i = i + 4)
1333 ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1335 (long long) get_frame_register_unsigned (frame, i + 0),
1336 (long long) get_frame_register_unsigned (frame, i + 1),
1337 (long long) get_frame_register_unsigned (frame, i + 2),
1338 (long long) get_frame_register_unsigned (frame, i + 3));
1340 printf_filtered ("\n");
1342 for (i = 0; i < 64; i = i + 8)
1344 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1346 (long) get_frame_register_unsigned
1347 (frame, gdbarch_fp0_regnum (gdbarch) + i + 0),
1348 (long) get_frame_register_unsigned
1349 (frame, gdbarch_fp0_regnum (gdbarch) + i + 1),
1350 (long) get_frame_register_unsigned
1351 (frame, gdbarch_fp0_regnum (gdbarch) + i + 2),
1352 (long) get_frame_register_unsigned
1353 (frame, gdbarch_fp0_regnum (gdbarch) + i + 3),
1354 (long) get_frame_register_unsigned
1355 (frame, gdbarch_fp0_regnum (gdbarch) + i + 4),
1356 (long) get_frame_register_unsigned
1357 (frame, gdbarch_fp0_regnum (gdbarch) + i + 5),
1358 (long) get_frame_register_unsigned
1359 (frame, gdbarch_fp0_regnum (gdbarch) + i + 6),
1360 (long) get_frame_register_unsigned
1361 (frame, gdbarch_fp0_regnum (gdbarch) + i + 7));
1365 sh64_show_compact_regs (struct frame_info *frame)
1367 struct gdbarch *gdbarch = get_frame_arch (frame);
1372 paddr (get_frame_register_unsigned (frame, PC_C_REGNUM)));
1375 ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1376 (long) get_frame_register_unsigned (frame, GBR_C_REGNUM),
1377 (long) get_frame_register_unsigned (frame, MACH_C_REGNUM),
1378 (long) get_frame_register_unsigned (frame, MACL_C_REGNUM),
1379 (long) get_frame_register_unsigned (frame, PR_C_REGNUM),
1380 (long) get_frame_register_unsigned (frame, T_C_REGNUM));
1382 ("FPSCR=%08lx FPUL=%08lx\n",
1383 (long) get_frame_register_unsigned (frame, FPSCR_C_REGNUM),
1384 (long) get_frame_register_unsigned (frame, FPUL_C_REGNUM));
1386 for (i = 0; i < 16; i = i + 4)
1388 ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1390 (long) get_frame_register_unsigned (frame, i + 0),
1391 (long) get_frame_register_unsigned (frame, i + 1),
1392 (long) get_frame_register_unsigned (frame, i + 2),
1393 (long) get_frame_register_unsigned (frame, i + 3));
1395 printf_filtered ("\n");
1397 for (i = 0; i < 16; i = i + 8)
1399 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1401 (long) get_frame_register_unsigned
1402 (frame, gdbarch_fp0_regnum (gdbarch) + i + 0),
1403 (long) get_frame_register_unsigned
1404 (frame, gdbarch_fp0_regnum (gdbarch) + i + 1),
1405 (long) get_frame_register_unsigned
1406 (frame, gdbarch_fp0_regnum (gdbarch) + i + 2),
1407 (long) get_frame_register_unsigned
1408 (frame, gdbarch_fp0_regnum (gdbarch) + i + 3),
1409 (long) get_frame_register_unsigned
1410 (frame, gdbarch_fp0_regnum (gdbarch) + i + 4),
1411 (long) get_frame_register_unsigned
1412 (frame, gdbarch_fp0_regnum (gdbarch) + i + 5),
1413 (long) get_frame_register_unsigned
1414 (frame, gdbarch_fp0_regnum (gdbarch) + i + 6),
1415 (long) get_frame_register_unsigned
1416 (frame, gdbarch_fp0_regnum (gdbarch) + i + 7));
1419 /* FIXME!!! This only shows the registers for shmedia, excluding the
1420 pseudo registers. */
1422 sh64_show_regs (struct frame_info *frame)
1424 if (pc_is_isa32 (get_frame_pc (frame)))
1425 sh64_show_media_regs (frame);
1427 sh64_show_compact_regs (frame);
1432 SH MEDIA MODE (ISA 32)
1433 general registers (64-bit) 0-63
1434 0 r0, r1, r2, r3, r4, r5, r6, r7,
1435 64 r8, r9, r10, r11, r12, r13, r14, r15,
1436 128 r16, r17, r18, r19, r20, r21, r22, r23,
1437 192 r24, r25, r26, r27, r28, r29, r30, r31,
1438 256 r32, r33, r34, r35, r36, r37, r38, r39,
1439 320 r40, r41, r42, r43, r44, r45, r46, r47,
1440 384 r48, r49, r50, r51, r52, r53, r54, r55,
1441 448 r56, r57, r58, r59, r60, r61, r62, r63,
1446 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1449 target registers (64-bit) 68-75
1450 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1452 floating point state control register (32-bit) 76
1455 single precision floating point registers (32-bit) 77-140
1456 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1457 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1458 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1459 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1460 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1461 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1462 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1463 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1465 TOTAL SPACE FOR REGISTERS: 868 bytes
1467 From here on they are all pseudo registers: no memory allocated.
1468 REGISTER_BYTE returns the register byte for the base register.
1470 double precision registers (pseudo) 141-172
1471 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1472 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1473 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1474 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1476 floating point pairs (pseudo) 173-204
1477 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1478 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1479 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1480 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1482 floating point vectors (4 floating point regs) (pseudo) 205-220
1483 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1484 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1486 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1487 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1488 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1490 gbr_c, mach_c, macl_c, pr_c, t_c,
1492 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1493 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1494 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1495 fv0_c, fv4_c, fv8_c, fv12_c
1498 static struct type *
1499 sh64_build_float_register_type (struct gdbarch *gdbarch, int high)
1503 temp = create_range_type (NULL, builtin_type_int32, 0, high);
1504 return create_array_type (NULL, builtin_type (gdbarch)->builtin_float, temp);
1507 /* Return the GDB type object for the "standard" data type
1508 of data in register REG_NR. */
1509 static struct type *
1510 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
1512 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
1513 && reg_nr <= FP_LAST_REGNUM)
1514 || (reg_nr >= FP0_C_REGNUM
1515 && reg_nr <= FP_LAST_C_REGNUM))
1516 return builtin_type (gdbarch)->builtin_float;
1517 else if ((reg_nr >= DR0_REGNUM
1518 && reg_nr <= DR_LAST_REGNUM)
1519 || (reg_nr >= DR0_C_REGNUM
1520 && reg_nr <= DR_LAST_C_REGNUM))
1521 return builtin_type (gdbarch)->builtin_double;
1522 else if (reg_nr >= FPP0_REGNUM
1523 && reg_nr <= FPP_LAST_REGNUM)
1524 return sh64_build_float_register_type (gdbarch, 1);
1525 else if ((reg_nr >= FV0_REGNUM
1526 && reg_nr <= FV_LAST_REGNUM)
1527 ||(reg_nr >= FV0_C_REGNUM
1528 && reg_nr <= FV_LAST_C_REGNUM))
1529 return sh64_build_float_register_type (gdbarch, 3);
1530 else if (reg_nr == FPSCR_REGNUM)
1531 return builtin_type (gdbarch)->builtin_int;
1532 else if (reg_nr >= R0_C_REGNUM
1533 && reg_nr < FP0_C_REGNUM)
1534 return builtin_type (gdbarch)->builtin_int;
1536 return builtin_type (gdbarch)->builtin_long_long;
1540 sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum,
1541 struct type *type, char *from, char *to)
1543 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1545 /* It is a no-op. */
1546 memcpy (to, from, register_size (gdbarch, regnum));
1550 if ((regnum >= DR0_REGNUM
1551 && regnum <= DR_LAST_REGNUM)
1552 || (regnum >= DR0_C_REGNUM
1553 && regnum <= DR_LAST_C_REGNUM))
1556 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1558 store_typed_floating (to, type, val);
1561 error ("sh64_register_convert_to_virtual called with non DR register number");
1565 sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type,
1566 int regnum, const void *from, void *to)
1568 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1570 /* It is a no-op. */
1571 memcpy (to, from, register_size (gdbarch, regnum));
1575 if ((regnum >= DR0_REGNUM
1576 && regnum <= DR_LAST_REGNUM)
1577 || (regnum >= DR0_C_REGNUM
1578 && regnum <= DR_LAST_C_REGNUM))
1580 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
1581 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1585 error ("sh64_register_convert_to_raw called with non DR register number");
1589 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1590 int reg_nr, gdb_byte *buffer)
1595 char temp_buffer[MAX_REGISTER_SIZE];
1597 if (reg_nr >= DR0_REGNUM
1598 && reg_nr <= DR_LAST_REGNUM)
1600 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1602 /* Build the value in the provided buffer. */
1603 /* DR regs are double precision registers obtained by
1604 concatenating 2 single precision floating point registers. */
1605 for (portion = 0; portion < 2; portion++)
1606 regcache_raw_read (regcache, base_regnum + portion,
1608 + register_size (gdbarch, base_regnum) * portion));
1610 /* We must pay attention to the endianness. */
1611 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1612 register_type (gdbarch, reg_nr),
1613 temp_buffer, buffer);
1617 else if (reg_nr >= FPP0_REGNUM
1618 && reg_nr <= FPP_LAST_REGNUM)
1620 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1622 /* Build the value in the provided buffer. */
1623 /* FPP regs are pairs of single precision registers obtained by
1624 concatenating 2 single precision floating point registers. */
1625 for (portion = 0; portion < 2; portion++)
1626 regcache_raw_read (regcache, base_regnum + portion,
1628 + register_size (gdbarch, base_regnum) * portion));
1631 else if (reg_nr >= FV0_REGNUM
1632 && reg_nr <= FV_LAST_REGNUM)
1634 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1636 /* Build the value in the provided buffer. */
1637 /* FV regs are vectors of single precision registers obtained by
1638 concatenating 4 single precision floating point registers. */
1639 for (portion = 0; portion < 4; portion++)
1640 regcache_raw_read (regcache, base_regnum + portion,
1642 + register_size (gdbarch, base_regnum) * portion));
1645 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
1646 else if (reg_nr >= R0_C_REGNUM
1647 && reg_nr <= T_C_REGNUM)
1649 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1651 /* Build the value in the provided buffer. */
1652 regcache_raw_read (regcache, base_regnum, temp_buffer);
1653 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1655 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
1658 else if (reg_nr >= FP0_C_REGNUM
1659 && reg_nr <= FP_LAST_C_REGNUM)
1661 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1663 /* Build the value in the provided buffer. */
1664 /* Floating point registers map 1-1 to the media fp regs,
1665 they have the same size and endianness. */
1666 regcache_raw_read (regcache, base_regnum, buffer);
1669 else if (reg_nr >= DR0_C_REGNUM
1670 && reg_nr <= DR_LAST_C_REGNUM)
1672 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1674 /* DR_C regs are double precision registers obtained by
1675 concatenating 2 single precision floating point registers. */
1676 for (portion = 0; portion < 2; portion++)
1677 regcache_raw_read (regcache, base_regnum + portion,
1679 + register_size (gdbarch, base_regnum) * portion));
1681 /* We must pay attention to the endianness. */
1682 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1683 register_type (gdbarch, reg_nr),
1684 temp_buffer, buffer);
1687 else if (reg_nr >= FV0_C_REGNUM
1688 && reg_nr <= FV_LAST_C_REGNUM)
1690 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1692 /* Build the value in the provided buffer. */
1693 /* FV_C regs are vectors of single precision registers obtained by
1694 concatenating 4 single precision floating point registers. */
1695 for (portion = 0; portion < 4; portion++)
1696 regcache_raw_read (regcache, base_regnum + portion,
1698 + register_size (gdbarch, base_regnum) * portion));
1701 else if (reg_nr == FPSCR_C_REGNUM)
1703 int fpscr_base_regnum;
1705 unsigned int fpscr_value;
1706 unsigned int sr_value;
1707 unsigned int fpscr_c_value;
1708 unsigned int fpscr_c_part1_value;
1709 unsigned int fpscr_c_part2_value;
1711 fpscr_base_regnum = FPSCR_REGNUM;
1712 sr_base_regnum = SR_REGNUM;
1714 /* Build the value in the provided buffer. */
1715 /* FPSCR_C is a very weird register that contains sparse bits
1716 from the FPSCR and the SR architectural registers.
1723 2-17 Bit 2-18 of FPSCR
1724 18-20 Bits 12,13,14 of SR
1728 /* Get FPSCR into a local buffer */
1729 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1730 /* Get value as an int. */
1731 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
1732 /* Get SR into a local buffer */
1733 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1734 /* Get value as an int. */
1735 sr_value = extract_unsigned_integer (temp_buffer, 4);
1736 /* Build the new value. */
1737 fpscr_c_part1_value = fpscr_value & 0x3fffd;
1738 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
1739 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
1740 /* Store that in out buffer!!! */
1741 store_unsigned_integer (buffer, 4, fpscr_c_value);
1742 /* FIXME There is surely an endianness gotcha here. */
1745 else if (reg_nr == FPUL_C_REGNUM)
1747 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1749 /* FPUL_C register is floating point register 32,
1750 same size, same endianness. */
1751 regcache_raw_read (regcache, base_regnum, buffer);
1756 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1757 int reg_nr, const gdb_byte *buffer)
1759 int base_regnum, portion;
1761 char temp_buffer[MAX_REGISTER_SIZE];
1763 if (reg_nr >= DR0_REGNUM
1764 && reg_nr <= DR_LAST_REGNUM)
1766 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1767 /* We must pay attention to the endianness. */
1768 sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr),
1770 buffer, temp_buffer);
1772 /* Write the real regs for which this one is an alias. */
1773 for (portion = 0; portion < 2; portion++)
1774 regcache_raw_write (regcache, base_regnum + portion,
1776 + register_size (gdbarch,
1777 base_regnum) * portion));
1780 else if (reg_nr >= FPP0_REGNUM
1781 && reg_nr <= FPP_LAST_REGNUM)
1783 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1785 /* Write the real regs for which this one is an alias. */
1786 for (portion = 0; portion < 2; portion++)
1787 regcache_raw_write (regcache, base_regnum + portion,
1789 + register_size (gdbarch,
1790 base_regnum) * portion));
1793 else if (reg_nr >= FV0_REGNUM
1794 && reg_nr <= FV_LAST_REGNUM)
1796 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1798 /* Write the real regs for which this one is an alias. */
1799 for (portion = 0; portion < 4; portion++)
1800 regcache_raw_write (regcache, base_regnum + portion,
1802 + register_size (gdbarch,
1803 base_regnum) * portion));
1806 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1807 register but only 4 bytes of it. */
1808 else if (reg_nr >= R0_C_REGNUM
1809 && reg_nr <= T_C_REGNUM)
1811 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1812 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1813 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1817 /* Let's read the value of the base register into a temporary
1818 buffer, so that overwriting the last four bytes with the new
1819 value of the pseudo will leave the upper 4 bytes unchanged. */
1820 regcache_raw_read (regcache, base_regnum, temp_buffer);
1821 /* Write as an 8 byte quantity */
1822 memcpy (temp_buffer + offset, buffer, 4);
1823 regcache_raw_write (regcache, base_regnum, temp_buffer);
1826 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1827 registers. Both are 4 bytes. */
1828 else if (reg_nr >= FP0_C_REGNUM
1829 && reg_nr <= FP_LAST_C_REGNUM)
1831 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1832 regcache_raw_write (regcache, base_regnum, buffer);
1835 else if (reg_nr >= DR0_C_REGNUM
1836 && reg_nr <= DR_LAST_C_REGNUM)
1838 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1839 for (portion = 0; portion < 2; portion++)
1841 /* We must pay attention to the endianness. */
1842 sh64_register_convert_to_raw (gdbarch,
1843 register_type (gdbarch, reg_nr),
1845 buffer, temp_buffer);
1847 regcache_raw_write (regcache, base_regnum + portion,
1849 + register_size (gdbarch,
1850 base_regnum) * portion));
1854 else if (reg_nr >= FV0_C_REGNUM
1855 && reg_nr <= FV_LAST_C_REGNUM)
1857 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1859 for (portion = 0; portion < 4; portion++)
1861 regcache_raw_write (regcache, base_regnum + portion,
1863 + register_size (gdbarch,
1864 base_regnum) * portion));
1868 else if (reg_nr == FPSCR_C_REGNUM)
1870 int fpscr_base_regnum;
1872 unsigned int fpscr_value;
1873 unsigned int sr_value;
1874 unsigned int old_fpscr_value;
1875 unsigned int old_sr_value;
1876 unsigned int fpscr_c_value;
1877 unsigned int fpscr_mask;
1878 unsigned int sr_mask;
1880 fpscr_base_regnum = FPSCR_REGNUM;
1881 sr_base_regnum = SR_REGNUM;
1883 /* FPSCR_C is a very weird register that contains sparse bits
1884 from the FPSCR and the SR architectural registers.
1891 2-17 Bit 2-18 of FPSCR
1892 18-20 Bits 12,13,14 of SR
1896 /* Get value as an int. */
1897 fpscr_c_value = extract_unsigned_integer (buffer, 4);
1899 /* Build the new values. */
1900 fpscr_mask = 0x0003fffd;
1901 sr_mask = 0x001c0000;
1903 fpscr_value = fpscr_c_value & fpscr_mask;
1904 sr_value = (fpscr_value & sr_mask) >> 6;
1906 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1907 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
1908 old_fpscr_value &= 0xfffc0002;
1909 fpscr_value |= old_fpscr_value;
1910 store_unsigned_integer (temp_buffer, 4, fpscr_value);
1911 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
1913 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1914 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
1915 old_sr_value &= 0xffff8fff;
1916 sr_value |= old_sr_value;
1917 store_unsigned_integer (temp_buffer, 4, sr_value);
1918 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
1921 else if (reg_nr == FPUL_C_REGNUM)
1923 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1924 regcache_raw_write (regcache, base_regnum, buffer);
1928 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1929 shmedia REGISTERS. */
1930 /* Control registers, compact mode. */
1932 sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame,
1935 switch (cr_c_regnum)
1938 fprintf_filtered (file, "pc_c\t0x%08x\n",
1939 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1942 fprintf_filtered (file, "gbr_c\t0x%08x\n",
1943 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1946 fprintf_filtered (file, "mach_c\t0x%08x\n",
1947 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1950 fprintf_filtered (file, "macl_c\t0x%08x\n",
1951 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1954 fprintf_filtered (file, "pr_c\t0x%08x\n",
1955 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1958 fprintf_filtered (file, "t_c\t0x%08x\n",
1959 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1961 case FPSCR_C_REGNUM:
1962 fprintf_filtered (file, "fpscr_c\t0x%08x\n",
1963 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1966 fprintf_filtered (file, "fpul_c\t0x%08x\n",
1967 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1973 sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file,
1974 struct frame_info *frame, int regnum)
1975 { /* do values for FP (float) regs */
1976 unsigned char *raw_buffer;
1977 double flt; /* double extracted from raw hex data */
1981 /* Allocate space for the float. */
1982 raw_buffer = (unsigned char *) alloca
1983 (register_size (gdbarch,
1987 /* Get the data in raw format. */
1988 if (!frame_register_read (frame, regnum, raw_buffer))
1989 error ("can't read register %d (%s)",
1990 regnum, gdbarch_register_name (gdbarch, regnum));
1992 /* Get the register as a number */
1993 flt = unpack_double (builtin_type (gdbarch)->builtin_float, raw_buffer, &inv);
1995 /* Print the name and some spaces. */
1996 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
1997 print_spaces_filtered (15 - strlen (gdbarch_register_name
1998 (gdbarch, regnum)), file);
2000 /* Print the value. */
2002 fprintf_filtered (file, "<invalid float>");
2004 fprintf_filtered (file, "%-10.9g", flt);
2006 /* Print the fp register as hex. */
2007 fprintf_filtered (file, "\t(raw 0x");
2008 for (j = 0; j < register_size (gdbarch, regnum); j++)
2010 int idx = gdbarch_byte_order (gdbarch)
2011 == BFD_ENDIAN_BIG ? j : register_size
2012 (gdbarch, regnum) - 1 - j;
2013 fprintf_filtered (file, "%02x", raw_buffer[idx]);
2015 fprintf_filtered (file, ")");
2016 fprintf_filtered (file, "\n");
2020 sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
2021 struct frame_info *frame, int regnum)
2023 /* All the sh64-compact mode registers are pseudo registers. */
2025 if (regnum < gdbarch_num_regs (gdbarch)
2026 || regnum >= gdbarch_num_regs (gdbarch)
2027 + NUM_PSEUDO_REGS_SH_MEDIA
2028 + NUM_PSEUDO_REGS_SH_COMPACT)
2029 internal_error (__FILE__, __LINE__,
2030 _("Invalid pseudo register number %d\n"), regnum);
2032 else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM))
2034 int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum);
2035 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM,
2036 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2037 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2040 else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM))
2042 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2043 fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM,
2044 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2045 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2048 else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM))
2050 int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum);
2051 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2052 regnum - FV0_REGNUM,
2053 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2054 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2055 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2056 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2059 else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM))
2061 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2062 fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2063 regnum - FV0_C_REGNUM,
2064 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2065 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2066 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2067 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2070 else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM)
2072 int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum);
2073 fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM,
2074 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2075 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2078 else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM)
2080 int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2081 fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM,
2082 (unsigned) get_frame_register_unsigned (frame, c_regnum));
2084 else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM)
2085 /* This should work also for pseudoregs. */
2086 sh64_do_fp_register (gdbarch, file, frame, regnum);
2087 else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM)
2088 sh64_do_cr_c_register_info (file, frame, regnum);
2092 sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file,
2093 struct frame_info *frame, int regnum)
2095 unsigned char raw_buffer[MAX_REGISTER_SIZE];
2096 struct value_print_options opts;
2098 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
2099 print_spaces_filtered (15 - strlen (gdbarch_register_name
2100 (gdbarch, regnum)), file);
2102 /* Get the data in raw format. */
2103 if (!frame_register_read (frame, regnum, raw_buffer))
2104 fprintf_filtered (file, "*value not available*\n");
2106 get_formatted_print_options (&opts, 'x');
2108 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2109 file, 0, &opts, current_language);
2110 fprintf_filtered (file, "\t");
2111 get_formatted_print_options (&opts, 0);
2113 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2114 file, 0, &opts, current_language);
2115 fprintf_filtered (file, "\n");
2119 sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file,
2120 struct frame_info *frame, int regnum)
2122 if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch)
2123 + gdbarch_num_pseudo_regs (gdbarch))
2124 internal_error (__FILE__, __LINE__,
2125 _("Invalid register number %d\n"), regnum);
2127 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
2129 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2130 sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */
2132 sh64_do_register (gdbarch, file, frame, regnum);
2135 else if (regnum < gdbarch_num_regs (gdbarch)
2136 + gdbarch_num_pseudo_regs (gdbarch))
2137 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2141 sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2142 struct frame_info *frame, int regnum,
2145 if (regnum != -1) /* do one specified register */
2147 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2148 error ("Not a valid register for the current processor type");
2150 sh64_print_register (gdbarch, file, frame, regnum);
2153 /* do all (or most) registers */
2156 while (regnum < gdbarch_num_regs (gdbarch))
2158 /* If the register name is empty, it is undefined for this
2159 processor, so don't display anything. */
2160 if (gdbarch_register_name (gdbarch, regnum) == NULL
2161 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
2167 if (TYPE_CODE (register_type (gdbarch, regnum))
2172 /* true for "INFO ALL-REGISTERS" command */
2173 sh64_do_fp_register (gdbarch, file, frame, regnum);
2177 regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch);
2182 sh64_do_register (gdbarch, file, frame, regnum);
2188 while (regnum < gdbarch_num_regs (gdbarch)
2189 + gdbarch_num_pseudo_regs (gdbarch))
2191 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2198 sh64_compact_print_registers_info (struct gdbarch *gdbarch,
2199 struct ui_file *file,
2200 struct frame_info *frame, int regnum,
2203 if (regnum != -1) /* do one specified register */
2205 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2206 error ("Not a valid register for the current processor type");
2208 if (regnum >= 0 && regnum < R0_C_REGNUM)
2209 error ("Not a valid register for the current processor mode.");
2211 sh64_print_register (gdbarch, file, frame, regnum);
2214 /* do all compact registers */
2216 regnum = R0_C_REGNUM;
2217 while (regnum < gdbarch_num_regs (gdbarch)
2218 + gdbarch_num_pseudo_regs (gdbarch))
2220 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2227 sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2228 struct frame_info *frame, int regnum, int fpregs)
2230 if (pc_is_isa32 (get_frame_pc (frame)))
2231 sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2233 sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2236 static struct sh64_frame_cache *
2237 sh64_alloc_frame_cache (void)
2239 struct sh64_frame_cache *cache;
2242 cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache);
2246 cache->saved_sp = 0;
2247 cache->sp_offset = 0;
2250 /* Frameless until proven otherwise. */
2253 /* Saved registers. We initialize these to -1 since zero is a valid
2254 offset (that's where fp is supposed to be stored). */
2255 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2257 cache->saved_regs[i] = -1;
2263 static struct sh64_frame_cache *
2264 sh64_frame_cache (struct frame_info *this_frame, void **this_cache)
2266 struct gdbarch *gdbarch;
2267 struct sh64_frame_cache *cache;
2268 CORE_ADDR current_pc;
2274 gdbarch = get_frame_arch (this_frame);
2275 cache = sh64_alloc_frame_cache ();
2276 *this_cache = cache;
2278 current_pc = get_frame_pc (this_frame);
2279 cache->media_mode = pc_is_isa32 (current_pc);
2281 /* In principle, for normal frames, fp holds the frame pointer,
2282 which holds the base address for the current stack frame.
2283 However, for functions that don't need it, the frame pointer is
2284 optional. For these "frameless" functions the frame pointer is
2285 actually the frame pointer of the calling frame. */
2286 cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM);
2287 if (cache->base == 0)
2290 cache->pc = get_frame_func (this_frame);
2292 sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc);
2294 if (!cache->uses_fp)
2296 /* We didn't find a valid frame, which means that CACHE->base
2297 currently holds the frame pointer for our calling frame. If
2298 we're at the start of a function, or somewhere half-way its
2299 prologue, the function's frame probably hasn't been fully
2300 setup yet. Try to reconstruct the base address for the stack
2301 frame by looking at the stack pointer. For truly "frameless"
2302 functions this might work too. */
2303 cache->base = get_frame_register_unsigned
2304 (this_frame, gdbarch_sp_regnum (gdbarch));
2307 /* Now that we have the base address for the stack frame we can
2308 calculate the value of sp in the calling frame. */
2309 cache->saved_sp = cache->base + cache->sp_offset;
2311 /* Adjust all the saved registers such that they contain addresses
2312 instead of offsets. */
2313 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2314 if (cache->saved_regs[i] != -1)
2315 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i];
2320 static struct value *
2321 sh64_frame_prev_register (struct frame_info *this_frame,
2322 void **this_cache, int regnum)
2324 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2325 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2327 gdb_assert (regnum >= 0);
2329 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2330 frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2332 /* The PC of the previous frame is stored in the PR register of
2333 the current frame. Frob regnum so that we pull the value from
2334 the correct place. */
2335 if (regnum == gdbarch_pc_regnum (gdbarch))
2338 if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1)
2340 if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32
2341 && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM))
2344 val = read_memory_unsigned_integer (cache->saved_regs[regnum], 4);
2345 return frame_unwind_got_constant (this_frame, regnum, val);
2348 return frame_unwind_got_memory (this_frame, regnum,
2349 cache->saved_regs[regnum]);
2352 return frame_unwind_got_register (this_frame, regnum, regnum);
2356 sh64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2357 struct frame_id *this_id)
2359 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2361 /* This marks the outermost frame. */
2362 if (cache->base == 0)
2365 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2368 static const struct frame_unwind sh64_frame_unwind = {
2371 sh64_frame_prev_register,
2373 default_frame_sniffer
2377 sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2379 return frame_unwind_register_unsigned (next_frame,
2380 gdbarch_sp_regnum (gdbarch));
2384 sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2386 return frame_unwind_register_unsigned (next_frame,
2387 gdbarch_pc_regnum (gdbarch));
2390 static struct frame_id
2391 sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2393 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2394 gdbarch_sp_regnum (gdbarch));
2395 return frame_id_build (sp, get_frame_pc (this_frame));
2399 sh64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2401 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2406 static const struct frame_base sh64_frame_base = {
2408 sh64_frame_base_address,
2409 sh64_frame_base_address,
2410 sh64_frame_base_address
2415 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2417 struct gdbarch *gdbarch;
2418 struct gdbarch_tdep *tdep;
2420 /* If there is already a candidate, use it. */
2421 arches = gdbarch_list_lookup_by_info (arches, &info);
2423 return arches->gdbarch;
2425 /* None found, create a new architecture from the information
2427 tdep = XMALLOC (struct gdbarch_tdep);
2428 gdbarch = gdbarch_alloc (&info, tdep);
2430 /* Determine the ABI */
2431 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2433 /* If the ABI is the 64-bit one, it can only be sh-media. */
2434 tdep->sh_abi = SH_ABI_64;
2435 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2436 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2440 /* If the ABI is the 32-bit one it could be either media or
2442 tdep->sh_abi = SH_ABI_32;
2443 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2444 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2447 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2448 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2449 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2450 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2451 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2452 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2453 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2455 /* The number of real registers is the same whether we are in
2456 ISA16(compact) or ISA32(media). */
2457 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2458 set_gdbarch_sp_regnum (gdbarch, 15);
2459 set_gdbarch_pc_regnum (gdbarch, 64);
2460 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2461 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA
2462 + NUM_PSEUDO_REGS_SH_COMPACT);
2464 set_gdbarch_register_name (gdbarch, sh64_register_name);
2465 set_gdbarch_register_type (gdbarch, sh64_register_type);
2467 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2468 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2470 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
2472 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2473 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2475 set_gdbarch_return_value (gdbarch, sh64_return_value);
2477 set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue);
2478 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2480 set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call);
2482 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2484 set_gdbarch_frame_align (gdbarch, sh64_frame_align);
2485 set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp);
2486 set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc);
2487 set_gdbarch_dummy_id (gdbarch, sh64_dummy_id);
2488 frame_base_set_default (gdbarch, &sh64_frame_base);
2490 set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info);
2492 set_gdbarch_elf_make_msymbol_special (gdbarch,
2493 sh64_elf_make_msymbol_special);
2495 /* Hook in ABI-specific overrides, if they have been registered. */
2496 gdbarch_init_osabi (info, gdbarch);
2498 dwarf2_append_unwinders (gdbarch);
2499 frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind);