1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2013 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
36 #include "gdb_assert.h"
37 #include "arch-utils.h"
46 /* Register numbers shared with the simulator. */
47 #include "gdb/sim-sh.h"
49 #include "sh64-tdep.h"
51 /* Information that is dependent on the processor variant. */
64 struct sh64_frame_cache
71 /* Flag showing that a frame has been created in the prologue code. */
76 /* Saved registers. */
77 CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
81 /* Registers of SH5 */
85 DEFAULT_RETURN_REGNUM = 2,
86 STRUCT_RETURN_REGNUM = 2,
89 FLOAT_ARGLAST_REGNUM = 11,
95 /* FPP stands for Floating Point Pair, to avoid confusion with
96 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
97 point register. Unfortunately on the sh5, the floating point
98 registers are called FR, and the floating point pairs are called FP. */
100 FPP_LAST_REGNUM = 204,
102 FV_LAST_REGNUM = 220,
104 R_LAST_C_REGNUM = 236,
111 FPSCR_C_REGNUM = 243,
114 FP_LAST_C_REGNUM = 260,
116 DR_LAST_C_REGNUM = 268,
118 FV_LAST_C_REGNUM = 272,
119 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
120 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
121 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
122 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
123 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
127 sh64_register_name (struct gdbarch *gdbarch, int reg_nr)
129 static char *register_names[] =
131 /* SH MEDIA MODE (ISA 32) */
132 /* general registers (64-bit) 0-63 */
133 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
134 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
135 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
136 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
137 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
138 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
139 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
140 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
145 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
148 /* target registers (64-bit) 68-75 */
149 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
151 /* floating point state control register (32-bit) 76 */
154 /* single precision floating point registers (32-bit) 77-140 */
155 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
156 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
157 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
158 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
159 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
160 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
161 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
162 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
164 /* double precision registers (pseudo) 141-172 */
165 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
166 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
167 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
168 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
170 /* floating point pairs (pseudo) 173-204 */
171 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
172 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
173 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
174 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
176 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
177 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
178 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
180 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
181 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
182 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
184 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
186 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
187 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
188 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
189 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
190 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
191 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
192 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
193 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return register_names[reg_nr];
203 #define NUM_PSEUDO_REGS_SH_MEDIA 80
204 #define NUM_PSEUDO_REGS_SH_COMPACT 51
206 /* Macros and functions for setting and testing a bit in a minimal
207 symbol that marks it as 32-bit function. The MSB of the minimal
208 symbol's "info" field is used for this purpose.
210 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
211 i.e. refers to a 32-bit function, and sets a "special" bit in a
212 minimal symbol to mark it as a 32-bit function
213 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
215 #define MSYMBOL_IS_SPECIAL(msym) \
216 MSYMBOL_TARGET_FLAG_1 (msym)
219 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
224 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
226 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
227 SYMBOL_VALUE_ADDRESS (msym) |= 1;
231 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
232 are some macros to test, set, or clear bit 0 of addresses. */
233 #define IS_ISA32_ADDR(addr) ((addr) & 1)
234 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
235 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
238 pc_is_isa32 (bfd_vma memaddr)
240 struct bound_minimal_symbol sym;
242 /* If bit 0 of the address is set, assume this is a
243 ISA32 (shmedia) address. */
244 if (IS_ISA32_ADDR (memaddr))
247 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
248 the high bit of the info field. Use this to decide if the function is
250 sym = lookup_minimal_symbol_by_pc (memaddr);
252 return MSYMBOL_IS_SPECIAL (sym.minsym);
257 static const unsigned char *
258 sh64_breakpoint_from_pc (struct gdbarch *gdbarch,
259 CORE_ADDR *pcptr, int *lenptr)
261 /* The BRK instruction for shmedia is
262 01101111 11110101 11111111 11110000
263 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
264 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
266 /* The BRK instruction for shcompact is
268 which translates in big endian mode to 0x0, 0x3b
269 and in little endian mode to 0x3b, 0x0 */
271 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
273 if (pc_is_isa32 (*pcptr))
275 static unsigned char big_breakpoint_media[] = {
276 0x6f, 0xf5, 0xff, 0xf0
278 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
279 *lenptr = sizeof (big_breakpoint_media);
280 return big_breakpoint_media;
284 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
285 *lenptr = sizeof (big_breakpoint_compact);
286 return big_breakpoint_compact;
291 if (pc_is_isa32 (*pcptr))
293 static unsigned char little_breakpoint_media[] = {
294 0xf0, 0xff, 0xf5, 0x6f
296 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
297 *lenptr = sizeof (little_breakpoint_media);
298 return little_breakpoint_media;
302 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
303 *lenptr = sizeof (little_breakpoint_compact);
304 return little_breakpoint_compact;
309 /* Prologue looks like
310 [mov.l <regs>,@-r15]...
315 Actually it can be more complicated than this. For instance, with
333 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
334 with l=1 and n = 18 0110101111110001010010100aaa0000 */
335 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
337 /* STS.L PR,@-r0 0100000000100010
338 r0-4-->r0, PR-->(r0) */
339 #define IS_STS_R0(x) ((x) == 0x4022)
341 /* STS PR, Rm 0000mmmm00101010
343 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
345 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
347 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
349 /* MOV.L R14,@(disp,r15) 000111111110dddd
350 R14-->(dispx4+r15) */
351 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
353 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
354 R18-->(dispx8+R14) */
355 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
357 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
358 R18-->(dispx8+R15) */
359 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
361 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
362 R18-->(dispx4+R15) */
363 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
365 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
366 R14-->(dispx8+R15) */
367 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
369 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
370 R14-->(dispx4+R15) */
371 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
373 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
375 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
377 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
379 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
381 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
383 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
385 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
387 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
389 #define IS_MOV_SP_FP_MEDIA(x) \
390 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
392 /* MOV #imm, R0 1110 0000 ssss ssss
394 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
396 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
397 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
399 /* ADD r15,r0 0011 0000 1111 1100
401 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
403 /* MOV.L R14 @-R0 0010 0000 1110 0110
404 R14-->(R0-4), R0-4-->R0 */
405 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
407 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
408 where Rm is one of r2-r9 which are the argument registers. */
409 /* FIXME: Recognize the float and double register moves too! */
410 #define IS_MEDIA_IND_ARG_MOV(x) \
411 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
412 && (((x) & 0x03f00000) >= 0x00200000 \
413 && ((x) & 0x03f00000) <= 0x00900000))
415 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
416 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
417 where Rm is one of r2-r9 which are the argument registers. */
418 #define IS_MEDIA_ARG_MOV(x) \
419 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
420 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
422 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
423 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
424 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
425 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
426 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
427 #define IS_MEDIA_MOV_TO_R14(x) \
428 ((((x) & 0xfffffc0f) == 0xa0e00000) \
429 || (((x) & 0xfffffc0f) == 0xa4e00000) \
430 || (((x) & 0xfffffc0f) == 0xa8e00000) \
431 || (((x) & 0xfffffc0f) == 0xb4e00000) \
432 || (((x) & 0xfffffc0f) == 0xbce00000))
434 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
436 #define IS_COMPACT_IND_ARG_MOV(x) \
437 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
438 && (((x) & 0x00f0) <= 0x0090))
440 /* compact direct arg move!
441 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
442 #define IS_COMPACT_ARG_MOV(x) \
443 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
444 && ((x) & 0x00f0) <= 0x0090))
446 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
447 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
448 #define IS_COMPACT_MOV_TO_R14(x) \
449 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
451 #define IS_JSR_R0(x) ((x) == 0x400b)
452 #define IS_NOP(x) ((x) == 0x0009)
455 /* MOV r15,r14 0110111011110011
457 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
459 /* ADD #imm,r15 01111111iiiiiiii
461 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
463 /* Skip any prologue before the guts of a function. */
465 /* Skip the prologue using the debug information. If this fails we'll
466 fall back on the 'guess' method below. */
468 after_prologue (CORE_ADDR pc)
470 struct symtab_and_line sal;
471 CORE_ADDR func_addr, func_end;
473 /* If we can not find the symbol in the partial symbol table, then
474 there is no hope we can determine the function's start address
476 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
480 /* Get the line associated with FUNC_ADDR. */
481 sal = find_pc_line (func_addr, 0);
483 /* There are only two cases to consider. First, the end of the source line
484 is within the function bounds. In that case we return the end of the
485 source line. Second is the end of the source line extends beyond the
486 bounds of the current function. We need to use the slow code to
487 examine instructions in that case. */
488 if (sal.end < func_end)
495 look_for_args_moves (struct gdbarch *gdbarch,
496 CORE_ADDR start_pc, int media_mode)
498 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
501 int insn_size = (media_mode ? 4 : 2);
503 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
507 w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
508 insn_size, byte_order);
510 if (IS_MEDIA_IND_ARG_MOV (w))
512 /* This must be followed by a store to r14, so the argument
513 is where the debug info says it is. This can happen after
514 the SP has been saved, unfortunately. */
516 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
517 insn_size, byte_order);
519 if (IS_MEDIA_MOV_TO_R14 (next_insn))
522 else if (IS_MEDIA_ARG_MOV (w))
524 /* These instructions store directly the argument in r14. */
532 w = read_memory_integer (here, insn_size, byte_order);
535 if (IS_COMPACT_IND_ARG_MOV (w))
537 /* This must be followed by a store to r14, so the argument
538 is where the debug info says it is. This can happen after
539 the SP has been saved, unfortunately. */
541 int next_insn = 0xffff & read_memory_integer (here, insn_size,
544 if (IS_COMPACT_MOV_TO_R14 (next_insn))
547 else if (IS_COMPACT_ARG_MOV (w))
549 /* These instructions store directly the argument in r14. */
552 else if (IS_MOVL_R0 (w))
554 /* There is a function that gcc calls to get the arguments
555 passed correctly to the function. Only after this
556 function call the arguments will be found at the place
557 where they are supposed to be. This happens in case the
558 argument has to be stored into a 64-bit register (for
559 instance doubles, long longs). SHcompact doesn't have
560 access to the full 64-bits, so we store the register in
561 stack slot and store the address of the stack slot in
562 the register, then do a call through a wrapper that
563 loads the memory value into the register. A SHcompact
564 callee calls an argument decoder
565 (GCC_shcompact_incoming_args) that stores the 64-bit
566 value in a stack slot and stores the address of the
567 stack slot in the register. GCC thinks the argument is
568 just passed by transparent reference, but this is only
569 true after the argument decoder is called. Such a call
570 needs to be considered part of the prologue. */
572 /* This must be followed by a JSR @r0 instruction and by
573 a NOP instruction. After these, the prologue is over! */
575 int next_insn = 0xffff & read_memory_integer (here, insn_size,
578 if (IS_JSR_R0 (next_insn))
580 next_insn = 0xffff & read_memory_integer (here, insn_size,
584 if (IS_NOP (next_insn))
597 sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc)
599 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
608 if (pc_is_isa32 (start_pc) == 0)
614 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
619 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
620 insn_size, byte_order);
622 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
623 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
624 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w)
625 || IS_PTABSL_R18 (w))
629 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
637 /* Don't bail out yet, we may have arguments stored in
638 registers here, according to the debug info, so that
639 gdb can print the frames correctly. */
640 start_pc = look_for_args_moves (gdbarch,
641 here - insn_size, media_mode);
647 int w = 0xffff & read_memory_integer (here, insn_size, byte_order);
650 if (IS_STS_R0 (w) || IS_STS_PR (w)
651 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
652 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
656 else if (IS_MOV_SP_FP (w))
664 /* Don't bail out yet, we may have arguments stored in
665 registers here, according to the debug info, so that
666 gdb can print the frames correctly. */
667 start_pc = look_for_args_moves (gdbarch,
668 here - insn_size, media_mode);
678 sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
680 CORE_ADDR post_prologue_pc;
682 /* See if we can determine the end of the prologue via the symbol table.
683 If so, then return either PC, or the PC after the prologue, whichever
685 post_prologue_pc = after_prologue (pc);
687 /* If after_prologue returned a useful address, then use it. Else
688 fall back on the instruction skipping code. */
689 if (post_prologue_pc != 0)
690 return max (pc, post_prologue_pc);
692 return sh64_skip_prologue_hard_way (gdbarch, pc);
695 /* Should call_function allocate stack space for a struct return? */
697 sh64_use_struct_convention (struct type *type)
699 return (TYPE_LENGTH (type) > 8);
702 /* For vectors of 4 floating point registers. */
704 sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
708 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4;
712 /* For double precision floating point registers, i.e 2 fp regs. */
714 sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
718 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2;
722 /* For pairs of floating point registers. */
724 sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum)
728 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2;
734 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
735 GDB_REGNUM BASE_REGNUM
795 sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr)
797 int base_regnum = reg_nr;
799 /* general register N maps to general register N */
800 if (reg_nr >= R0_C_REGNUM
801 && reg_nr <= R_LAST_C_REGNUM)
802 base_regnum = reg_nr - R0_C_REGNUM;
804 /* floating point register N maps to floating point register N */
805 else if (reg_nr >= FP0_C_REGNUM
806 && reg_nr <= FP_LAST_C_REGNUM)
807 base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch);
809 /* double prec register N maps to base regnum for double prec register N */
810 else if (reg_nr >= DR0_C_REGNUM
811 && reg_nr <= DR_LAST_C_REGNUM)
812 base_regnum = sh64_dr_reg_base_num (gdbarch,
813 DR0_REGNUM + reg_nr - DR0_C_REGNUM);
815 /* vector N maps to base regnum for vector register N */
816 else if (reg_nr >= FV0_C_REGNUM
817 && reg_nr <= FV_LAST_C_REGNUM)
818 base_regnum = sh64_fv_reg_base_num (gdbarch,
819 FV0_REGNUM + reg_nr - FV0_C_REGNUM);
821 else if (reg_nr == PC_C_REGNUM)
822 base_regnum = gdbarch_pc_regnum (gdbarch);
824 else if (reg_nr == GBR_C_REGNUM)
827 else if (reg_nr == MACH_C_REGNUM
828 || reg_nr == MACL_C_REGNUM)
831 else if (reg_nr == PR_C_REGNUM)
832 base_regnum = PR_REGNUM;
834 else if (reg_nr == T_C_REGNUM)
837 else if (reg_nr == FPSCR_C_REGNUM)
838 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
840 else if (reg_nr == FPUL_C_REGNUM)
841 base_regnum = gdbarch_fp0_regnum (gdbarch) + 32;
847 sign_extend (int value, int bits)
849 value = value & ((1 << bits) - 1);
850 return (value & (1 << (bits - 1))
851 ? value | (~((1 << bits) - 1))
856 sh64_analyze_prologue (struct gdbarch *gdbarch,
857 struct sh64_frame_cache *cache,
859 CORE_ADDR current_pc)
866 int gdb_register_number;
868 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
869 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
871 cache->sp_offset = 0;
873 /* Loop around examining the prologue insns until we find something
874 that does not appear to be part of the prologue. But give up
875 after 20 of them, since we're getting silly then. */
879 if (cache->media_mode)
884 opc = pc + (insn_size * 28);
885 if (opc > current_pc)
887 for ( ; pc <= opc; pc += insn_size)
889 insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
891 insn_size, byte_order);
893 if (!cache->media_mode)
895 if (IS_STS_PR (insn))
897 int next_insn = read_memory_integer (pc + insn_size,
898 insn_size, byte_order);
899 if (IS_MOV_TO_R15 (next_insn))
901 cache->saved_regs[PR_REGNUM]
902 = cache->sp_offset - ((((next_insn & 0xf) ^ 0x8)
908 else if (IS_MOV_R14 (insn))
909 cache->saved_regs[MEDIA_FP_REGNUM] =
910 cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
912 else if (IS_MOV_R0 (insn))
914 /* Put in R0 the offset from SP at which to store some
915 registers. We are interested in this value, because it
916 will tell us where the given registers are stored within
918 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
921 else if (IS_ADD_SP_R0 (insn))
923 /* This instruction still prepares r0, but we don't care.
924 We already have the offset in r0_val. */
927 else if (IS_STS_R0 (insn))
929 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
930 cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
934 else if (IS_MOV_R14_R0 (insn))
936 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
937 cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
942 else if (IS_ADD_SP (insn))
943 cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
945 else if (IS_MOV_SP_FP (insn))
950 if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
952 sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
954 else if (IS_STQ_R18_R15 (insn))
955 cache->saved_regs[PR_REGNUM]
956 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
959 else if (IS_STL_R18_R15 (insn))
960 cache->saved_regs[PR_REGNUM]
961 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
964 else if (IS_STQ_R14_R15 (insn))
965 cache->saved_regs[MEDIA_FP_REGNUM]
966 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
969 else if (IS_STL_R14_R15 (insn))
970 cache->saved_regs[MEDIA_FP_REGNUM]
971 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
974 else if (IS_MOV_SP_FP_MEDIA (insn))
979 if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0)
984 sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
989 /* Function: push_dummy_call
990 Setup the function arguments for calling a function in the inferior.
992 On the Renesas SH architecture, there are four registers (R4 to R7)
993 which are dedicated for passing function arguments. Up to the first
994 four arguments (depending on size) may go into these registers.
995 The rest go on the stack.
997 Arguments that are smaller than 4 bytes will still take up a whole
998 register or a whole 32-bit word on the stack, and will be
999 right-justified in the register or the stack word. This includes
1000 chars, shorts, and small aggregate types.
1002 Arguments that are larger than 4 bytes may be split between two or
1003 more registers. If there are not enough registers free, an argument
1004 may be passed partly in a register (or registers), and partly on the
1005 stack. This includes doubles, long longs, and larger aggregates.
1006 As far as I know, there is no upper limit to the size of aggregates
1007 that will be passed in this way; in other words, the convention of
1008 passing a pointer to a large aggregate instead of a copy is not used.
1010 An exceptional case exists for struct arguments (and possibly other
1011 aggregates such as arrays) if the size is larger than 4 bytes but
1012 not a multiple of 4 bytes. In this case the argument is never split
1013 between the registers and the stack, but instead is copied in its
1014 entirety onto the stack, AND also copied into as many registers as
1015 there is room for. In other words, space in registers permitting,
1016 two copies of the same argument are passed in. As far as I can tell,
1017 only the one on the stack is used, although that may be a function
1018 of the level of compiler optimization. I suspect this is a compiler
1019 bug. Arguments of these odd sizes are left-justified within the
1020 word (as opposed to arguments smaller than 4 bytes, which are
1023 If the function is to return an aggregate type such as a struct, it
1024 is either returned in the normal return value register R0 (if its
1025 size is no greater than one byte), or else the caller must allocate
1026 space into which the callee will copy the return value (if the size
1027 is greater than one byte). In this case, a pointer to the return
1028 value location is passed into the callee in register R2, which does
1029 not displace any of the other arguments passed in via registers R4
1032 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1033 non-scalar (struct, union) elements (even if the elements are
1035 FR0-FR11 for single precision floating point (float)
1036 DR0-DR10 for double precision floating point (double)
1038 If a float is argument number 3 (for instance) and arguments number
1039 1,2, and 4 are integer, the mapping will be:
1040 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1042 If a float is argument number 10 (for instance) and arguments number
1043 1 through 10 are integer, the mapping will be:
1044 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1045 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1046 arg11->stack(16,SP). I.e. there is hole in the stack.
1048 Different rules apply for variable arguments functions, and for functions
1049 for which the prototype is not known. */
1052 sh64_push_dummy_call (struct gdbarch *gdbarch,
1053 struct value *function,
1054 struct regcache *regcache,
1056 int nargs, struct value **args,
1057 CORE_ADDR sp, int struct_return,
1058 CORE_ADDR struct_addr)
1060 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1061 int stack_offset, stack_alloc;
1065 int float_arg_index = 0;
1066 int double_arg_index = 0;
1070 const gdb_byte *val;
1076 memset (fp_args, 0, sizeof (fp_args));
1078 /* First force sp to a 8-byte alignment. */
1079 sp = sh64_frame_align (gdbarch, sp);
1081 /* The "struct return pointer" pseudo-argument has its own dedicated
1085 regcache_cooked_write_unsigned (regcache,
1086 STRUCT_RETURN_REGNUM, struct_addr);
1088 /* Now make sure there's space on the stack. */
1089 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1090 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
1091 sp -= stack_alloc; /* Make room on stack for args. */
1093 /* Now load as many as possible of the first arguments into
1094 registers, and push the rest onto the stack. There are 64 bytes
1095 in eight registers available. Loop thru args from first to last. */
1097 int_argreg = ARG0_REGNUM;
1098 float_argreg = gdbarch_fp0_regnum (gdbarch);
1099 double_argreg = DR0_REGNUM;
1101 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1103 type = value_type (args[argnum]);
1104 len = TYPE_LENGTH (type);
1105 memset (valbuf, 0, sizeof (valbuf));
1107 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1109 argreg_size = register_size (gdbarch, int_argreg);
1111 if (len < argreg_size)
1113 /* value gets right-justified in the register or stack word. */
1114 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1115 memcpy (valbuf + argreg_size - len,
1116 value_contents (args[argnum]), len);
1118 memcpy (valbuf, value_contents (args[argnum]), len);
1123 val = value_contents (args[argnum]);
1127 if (int_argreg > ARGLAST_REGNUM)
1129 /* Must go on the stack. */
1130 write_memory (sp + stack_offset, val, argreg_size);
1131 stack_offset += 8;/*argreg_size;*/
1133 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1134 That's because some *&^%$ things get passed on the stack
1135 AND in the registers! */
1136 if (int_argreg <= ARGLAST_REGNUM)
1138 /* There's room in a register. */
1139 regval = extract_unsigned_integer (val, argreg_size,
1141 regcache_cooked_write_unsigned (regcache,
1142 int_argreg, regval);
1144 /* Store the value 8 bytes at a time. This means that
1145 things larger than 8 bytes may go partly in registers
1146 and partly on the stack. FIXME: argreg is incremented
1147 before we use its size. */
1155 val = value_contents (args[argnum]);
1158 /* Where is it going to be stored? */
1159 while (fp_args[float_arg_index])
1162 /* Now float_argreg points to the register where it
1163 should be stored. Are we still within the allowed
1165 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1167 /* Goes in FR0...FR11 */
1168 regcache_cooked_write (regcache,
1169 gdbarch_fp0_regnum (gdbarch)
1172 fp_args[float_arg_index] = 1;
1173 /* Skip the corresponding general argument register. */
1178 /* Store it as the integers, 8 bytes at the time, if
1179 necessary spilling on the stack. */
1184 /* Where is it going to be stored? */
1185 while (fp_args[double_arg_index])
1186 double_arg_index += 2;
1187 /* Now double_argreg points to the register
1188 where it should be stored.
1189 Are we still within the allowed register set? */
1190 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1192 /* Goes in DR0...DR10 */
1193 /* The numbering of the DRi registers is consecutive,
1194 i.e. includes odd numbers. */
1195 int double_register_offset = double_arg_index / 2;
1196 int regnum = DR0_REGNUM + double_register_offset;
1197 regcache_cooked_write (regcache, regnum, val);
1198 fp_args[double_arg_index] = 1;
1199 fp_args[double_arg_index + 1] = 1;
1200 /* Skip the corresponding general argument register. */
1205 /* Store it as the integers, 8 bytes at the time, if
1206 necessary spilling on the stack. */
1211 /* Store return address. */
1212 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1214 /* Update stack pointer. */
1215 regcache_cooked_write_unsigned (regcache,
1216 gdbarch_sp_regnum (gdbarch), sp);
1221 /* Find a function's return value in the appropriate registers (in
1222 regbuf), and copy it into valbuf. Extract from an array REGBUF
1223 containing the (raw) register state a function return value of type
1224 TYPE, and copy that, in virtual format, into VALBUF. */
1226 sh64_extract_return_value (struct type *type, struct regcache *regcache,
1229 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1230 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1231 int len = TYPE_LENGTH (type);
1233 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1237 /* Return value stored in gdbarch_fp0_regnum. */
1238 regcache_raw_read (regcache,
1239 gdbarch_fp0_regnum (gdbarch), valbuf);
1243 /* return value stored in DR0_REGNUM. */
1247 regcache_cooked_read (regcache, DR0_REGNUM, buf);
1249 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1250 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1253 floatformat_to_doublest (&floatformat_ieee_double_big,
1255 store_typed_floating (valbuf, type, val);
1264 /* Result is in register 2. If smaller than 8 bytes, it is padded
1265 at the most significant end. */
1266 regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf);
1268 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1269 offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM)
1273 memcpy (valbuf, buf + offset, len);
1276 error (_("bad size for return value"));
1280 /* Write into appropriate registers a function return value
1281 of type TYPE, given in virtual format.
1282 If the architecture is sh4 or sh3e, store a function's return value
1283 in the R0 general register or in the FP0 floating point register,
1284 depending on the type of the return value. In all the other cases
1285 the result is stored in r0, left-justified. */
1288 sh64_store_return_value (struct type *type, struct regcache *regcache,
1289 const gdb_byte *valbuf)
1291 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1292 gdb_byte buf[64]; /* more than enough... */
1293 int len = TYPE_LENGTH (type);
1295 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1297 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1298 for (i = 0; i < len; i += 4)
1299 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1300 regcache_raw_write (regcache, regnum++,
1301 valbuf + len - 4 - i);
1303 regcache_raw_write (regcache, regnum++, valbuf + i);
1307 int return_register = DEFAULT_RETURN_REGNUM;
1310 if (len <= register_size (gdbarch, return_register))
1312 /* Pad with zeros. */
1313 memset (buf, 0, register_size (gdbarch, return_register));
1314 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1315 offset = 0; /*register_size (gdbarch,
1316 return_register) - len;*/
1318 offset = register_size (gdbarch, return_register) - len;
1320 memcpy (buf + offset, valbuf, len);
1321 regcache_raw_write (regcache, return_register, buf);
1324 regcache_raw_write (regcache, return_register, valbuf);
1328 static enum return_value_convention
1329 sh64_return_value (struct gdbarch *gdbarch, struct value *function,
1330 struct type *type, struct regcache *regcache,
1331 gdb_byte *readbuf, const gdb_byte *writebuf)
1333 if (sh64_use_struct_convention (type))
1334 return RETURN_VALUE_STRUCT_CONVENTION;
1336 sh64_store_return_value (type, regcache, writebuf);
1338 sh64_extract_return_value (type, regcache, readbuf);
1339 return RETURN_VALUE_REGISTER_CONVENTION;
1344 SH MEDIA MODE (ISA 32)
1345 general registers (64-bit) 0-63
1346 0 r0, r1, r2, r3, r4, r5, r6, r7,
1347 64 r8, r9, r10, r11, r12, r13, r14, r15,
1348 128 r16, r17, r18, r19, r20, r21, r22, r23,
1349 192 r24, r25, r26, r27, r28, r29, r30, r31,
1350 256 r32, r33, r34, r35, r36, r37, r38, r39,
1351 320 r40, r41, r42, r43, r44, r45, r46, r47,
1352 384 r48, r49, r50, r51, r52, r53, r54, r55,
1353 448 r56, r57, r58, r59, r60, r61, r62, r63,
1358 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1361 target registers (64-bit) 68-75
1362 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1364 floating point state control register (32-bit) 76
1367 single precision floating point registers (32-bit) 77-140
1368 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1369 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1370 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1371 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1372 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1373 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1374 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1375 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1377 TOTAL SPACE FOR REGISTERS: 868 bytes
1379 From here on they are all pseudo registers: no memory allocated.
1380 REGISTER_BYTE returns the register byte for the base register.
1382 double precision registers (pseudo) 141-172
1383 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1384 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1385 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1386 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1388 floating point pairs (pseudo) 173-204
1389 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1390 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1391 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1392 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1394 floating point vectors (4 floating point regs) (pseudo) 205-220
1395 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1396 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1398 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1399 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1400 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1402 gbr_c, mach_c, macl_c, pr_c, t_c,
1404 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1405 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1406 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1407 fv0_c, fv4_c, fv8_c, fv12_c
1410 static struct type *
1411 sh64_build_float_register_type (struct gdbarch *gdbarch, int high)
1413 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
1417 /* Return the GDB type object for the "standard" data type
1418 of data in register REG_NR. */
1419 static struct type *
1420 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
1422 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
1423 && reg_nr <= FP_LAST_REGNUM)
1424 || (reg_nr >= FP0_C_REGNUM
1425 && reg_nr <= FP_LAST_C_REGNUM))
1426 return builtin_type (gdbarch)->builtin_float;
1427 else if ((reg_nr >= DR0_REGNUM
1428 && reg_nr <= DR_LAST_REGNUM)
1429 || (reg_nr >= DR0_C_REGNUM
1430 && reg_nr <= DR_LAST_C_REGNUM))
1431 return builtin_type (gdbarch)->builtin_double;
1432 else if (reg_nr >= FPP0_REGNUM
1433 && reg_nr <= FPP_LAST_REGNUM)
1434 return sh64_build_float_register_type (gdbarch, 1);
1435 else if ((reg_nr >= FV0_REGNUM
1436 && reg_nr <= FV_LAST_REGNUM)
1437 ||(reg_nr >= FV0_C_REGNUM
1438 && reg_nr <= FV_LAST_C_REGNUM))
1439 return sh64_build_float_register_type (gdbarch, 3);
1440 else if (reg_nr == FPSCR_REGNUM)
1441 return builtin_type (gdbarch)->builtin_int;
1442 else if (reg_nr >= R0_C_REGNUM
1443 && reg_nr < FP0_C_REGNUM)
1444 return builtin_type (gdbarch)->builtin_int;
1446 return builtin_type (gdbarch)->builtin_long_long;
1450 sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum,
1451 struct type *type, gdb_byte *from, gdb_byte *to)
1453 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1455 /* It is a no-op. */
1456 memcpy (to, from, register_size (gdbarch, regnum));
1460 if ((regnum >= DR0_REGNUM
1461 && regnum <= DR_LAST_REGNUM)
1462 || (regnum >= DR0_C_REGNUM
1463 && regnum <= DR_LAST_C_REGNUM))
1466 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1468 store_typed_floating (to, type, val);
1471 error (_("sh64_register_convert_to_virtual "
1472 "called with non DR register number"));
1476 sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type,
1477 int regnum, const void *from, void *to)
1479 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1481 /* It is a no-op. */
1482 memcpy (to, from, register_size (gdbarch, regnum));
1486 if ((regnum >= DR0_REGNUM
1487 && regnum <= DR_LAST_REGNUM)
1488 || (regnum >= DR0_C_REGNUM
1489 && regnum <= DR_LAST_C_REGNUM))
1491 DOUBLEST val = extract_typed_floating (from, type);
1492 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1496 error (_("sh64_register_convert_to_raw called "
1497 "with non DR register number"));
1500 /* Concatenate PORTIONS contiguous raw registers starting at
1501 BASE_REGNUM into BUFFER. */
1503 static enum register_status
1504 pseudo_register_read_portions (struct gdbarch *gdbarch,
1505 struct regcache *regcache,
1507 int base_regnum, gdb_byte *buffer)
1511 for (portion = 0; portion < portions; portion++)
1513 enum register_status status;
1516 b = buffer + register_size (gdbarch, base_regnum) * portion;
1517 status = regcache_raw_read (regcache, base_regnum + portion, b);
1518 if (status != REG_VALID)
1525 static enum register_status
1526 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1527 int reg_nr, gdb_byte *buffer)
1529 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1532 gdb_byte temp_buffer[MAX_REGISTER_SIZE];
1533 enum register_status status;
1535 if (reg_nr >= DR0_REGNUM
1536 && reg_nr <= DR_LAST_REGNUM)
1538 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1540 /* Build the value in the provided buffer. */
1541 /* DR regs are double precision registers obtained by
1542 concatenating 2 single precision floating point registers. */
1543 status = pseudo_register_read_portions (gdbarch, regcache,
1544 2, base_regnum, temp_buffer);
1545 if (status == REG_VALID)
1547 /* We must pay attention to the endianness. */
1548 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1549 register_type (gdbarch, reg_nr),
1550 temp_buffer, buffer);
1556 else if (reg_nr >= FPP0_REGNUM
1557 && reg_nr <= FPP_LAST_REGNUM)
1559 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1561 /* Build the value in the provided buffer. */
1562 /* FPP regs are pairs of single precision registers obtained by
1563 concatenating 2 single precision floating point registers. */
1564 return pseudo_register_read_portions (gdbarch, regcache,
1565 2, base_regnum, buffer);
1568 else if (reg_nr >= FV0_REGNUM
1569 && reg_nr <= FV_LAST_REGNUM)
1571 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1573 /* Build the value in the provided buffer. */
1574 /* FV regs are vectors of single precision registers obtained by
1575 concatenating 4 single precision floating point registers. */
1576 return pseudo_register_read_portions (gdbarch, regcache,
1577 4, base_regnum, buffer);
1580 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1581 else if (reg_nr >= R0_C_REGNUM
1582 && reg_nr <= T_C_REGNUM)
1584 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1586 /* Build the value in the provided buffer. */
1587 status = regcache_raw_read (regcache, base_regnum, temp_buffer);
1588 if (status != REG_VALID)
1590 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1593 temp_buffer + offset, 4); /* get LOWER 32 bits only???? */
1597 else if (reg_nr >= FP0_C_REGNUM
1598 && reg_nr <= FP_LAST_C_REGNUM)
1600 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1602 /* Build the value in the provided buffer. */
1603 /* Floating point registers map 1-1 to the media fp regs,
1604 they have the same size and endianness. */
1605 return regcache_raw_read (regcache, base_regnum, buffer);
1608 else if (reg_nr >= DR0_C_REGNUM
1609 && reg_nr <= DR_LAST_C_REGNUM)
1611 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1613 /* DR_C regs are double precision registers obtained by
1614 concatenating 2 single precision floating point registers. */
1615 status = pseudo_register_read_portions (gdbarch, regcache,
1616 2, base_regnum, temp_buffer);
1617 if (status == REG_VALID)
1619 /* We must pay attention to the endianness. */
1620 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1621 register_type (gdbarch, reg_nr),
1622 temp_buffer, buffer);
1627 else if (reg_nr >= FV0_C_REGNUM
1628 && reg_nr <= FV_LAST_C_REGNUM)
1630 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1632 /* Build the value in the provided buffer. */
1633 /* FV_C regs are vectors of single precision registers obtained by
1634 concatenating 4 single precision floating point registers. */
1635 return pseudo_register_read_portions (gdbarch, regcache,
1636 4, base_regnum, buffer);
1639 else if (reg_nr == FPSCR_C_REGNUM)
1641 int fpscr_base_regnum;
1643 unsigned int fpscr_value;
1644 unsigned int sr_value;
1645 unsigned int fpscr_c_value;
1646 unsigned int fpscr_c_part1_value;
1647 unsigned int fpscr_c_part2_value;
1649 fpscr_base_regnum = FPSCR_REGNUM;
1650 sr_base_regnum = SR_REGNUM;
1652 /* Build the value in the provided buffer. */
1653 /* FPSCR_C is a very weird register that contains sparse bits
1654 from the FPSCR and the SR architectural registers.
1661 2-17 Bit 2-18 of FPSCR
1662 18-20 Bits 12,13,14 of SR
1666 /* Get FPSCR into a local buffer. */
1667 status = regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1668 if (status != REG_VALID)
1670 /* Get value as an int. */
1671 fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1672 /* Get SR into a local buffer */
1673 status = regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1674 if (status != REG_VALID)
1676 /* Get value as an int. */
1677 sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1678 /* Build the new value. */
1679 fpscr_c_part1_value = fpscr_value & 0x3fffd;
1680 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
1681 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
1682 /* Store that in out buffer!!! */
1683 store_unsigned_integer (buffer, 4, byte_order, fpscr_c_value);
1684 /* FIXME There is surely an endianness gotcha here. */
1689 else if (reg_nr == FPUL_C_REGNUM)
1691 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1693 /* FPUL_C register is floating point register 32,
1694 same size, same endianness. */
1695 return regcache_raw_read (regcache, base_regnum, buffer);
1698 gdb_assert_not_reached ("invalid pseudo register number");
1702 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1703 int reg_nr, const gdb_byte *buffer)
1705 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1706 int base_regnum, portion;
1708 gdb_byte temp_buffer[MAX_REGISTER_SIZE];
1710 if (reg_nr >= DR0_REGNUM
1711 && reg_nr <= DR_LAST_REGNUM)
1713 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1714 /* We must pay attention to the endianness. */
1715 sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr),
1717 buffer, temp_buffer);
1719 /* Write the real regs for which this one is an alias. */
1720 for (portion = 0; portion < 2; portion++)
1721 regcache_raw_write (regcache, base_regnum + portion,
1723 + register_size (gdbarch,
1724 base_regnum) * portion));
1727 else if (reg_nr >= FPP0_REGNUM
1728 && reg_nr <= FPP_LAST_REGNUM)
1730 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1732 /* Write the real regs for which this one is an alias. */
1733 for (portion = 0; portion < 2; portion++)
1734 regcache_raw_write (regcache, base_regnum + portion,
1735 (buffer + register_size (gdbarch,
1736 base_regnum) * portion));
1739 else if (reg_nr >= FV0_REGNUM
1740 && reg_nr <= FV_LAST_REGNUM)
1742 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1744 /* Write the real regs for which this one is an alias. */
1745 for (portion = 0; portion < 4; portion++)
1746 regcache_raw_write (regcache, base_regnum + portion,
1747 (buffer + register_size (gdbarch,
1748 base_regnum) * portion));
1751 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1752 register but only 4 bytes of it. */
1753 else if (reg_nr >= R0_C_REGNUM
1754 && reg_nr <= T_C_REGNUM)
1756 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1757 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1758 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1762 /* Let's read the value of the base register into a temporary
1763 buffer, so that overwriting the last four bytes with the new
1764 value of the pseudo will leave the upper 4 bytes unchanged. */
1765 regcache_raw_read (regcache, base_regnum, temp_buffer);
1766 /* Write as an 8 byte quantity. */
1767 memcpy (temp_buffer + offset, buffer, 4);
1768 regcache_raw_write (regcache, base_regnum, temp_buffer);
1771 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1772 registers. Both are 4 bytes. */
1773 else if (reg_nr >= FP0_C_REGNUM
1774 && reg_nr <= FP_LAST_C_REGNUM)
1776 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1777 regcache_raw_write (regcache, base_regnum, buffer);
1780 else if (reg_nr >= DR0_C_REGNUM
1781 && reg_nr <= DR_LAST_C_REGNUM)
1783 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1784 for (portion = 0; portion < 2; portion++)
1786 /* We must pay attention to the endianness. */
1787 sh64_register_convert_to_raw (gdbarch,
1788 register_type (gdbarch, reg_nr),
1790 buffer, temp_buffer);
1792 regcache_raw_write (regcache, base_regnum + portion,
1794 + register_size (gdbarch,
1795 base_regnum) * portion));
1799 else if (reg_nr >= FV0_C_REGNUM
1800 && reg_nr <= FV_LAST_C_REGNUM)
1802 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1804 for (portion = 0; portion < 4; portion++)
1806 regcache_raw_write (regcache, base_regnum + portion,
1808 + register_size (gdbarch,
1809 base_regnum) * portion));
1813 else if (reg_nr == FPSCR_C_REGNUM)
1815 int fpscr_base_regnum;
1817 unsigned int fpscr_value;
1818 unsigned int sr_value;
1819 unsigned int old_fpscr_value;
1820 unsigned int old_sr_value;
1821 unsigned int fpscr_c_value;
1822 unsigned int fpscr_mask;
1823 unsigned int sr_mask;
1825 fpscr_base_regnum = FPSCR_REGNUM;
1826 sr_base_regnum = SR_REGNUM;
1828 /* FPSCR_C is a very weird register that contains sparse bits
1829 from the FPSCR and the SR architectural registers.
1836 2-17 Bit 2-18 of FPSCR
1837 18-20 Bits 12,13,14 of SR
1841 /* Get value as an int. */
1842 fpscr_c_value = extract_unsigned_integer (buffer, 4, byte_order);
1844 /* Build the new values. */
1845 fpscr_mask = 0x0003fffd;
1846 sr_mask = 0x001c0000;
1848 fpscr_value = fpscr_c_value & fpscr_mask;
1849 sr_value = (fpscr_value & sr_mask) >> 6;
1851 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1852 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1853 old_fpscr_value &= 0xfffc0002;
1854 fpscr_value |= old_fpscr_value;
1855 store_unsigned_integer (temp_buffer, 4, byte_order, fpscr_value);
1856 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
1858 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1859 old_sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1860 old_sr_value &= 0xffff8fff;
1861 sr_value |= old_sr_value;
1862 store_unsigned_integer (temp_buffer, 4, byte_order, sr_value);
1863 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
1866 else if (reg_nr == FPUL_C_REGNUM)
1868 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1869 regcache_raw_write (regcache, base_regnum, buffer);
1873 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1874 shmedia REGISTERS. */
1875 /* Control registers, compact mode. */
1877 sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame,
1880 switch (cr_c_regnum)
1883 fprintf_filtered (file, "pc_c\t0x%08x\n",
1884 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1887 fprintf_filtered (file, "gbr_c\t0x%08x\n",
1888 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1891 fprintf_filtered (file, "mach_c\t0x%08x\n",
1892 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1895 fprintf_filtered (file, "macl_c\t0x%08x\n",
1896 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1899 fprintf_filtered (file, "pr_c\t0x%08x\n",
1900 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1903 fprintf_filtered (file, "t_c\t0x%08x\n",
1904 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1906 case FPSCR_C_REGNUM:
1907 fprintf_filtered (file, "fpscr_c\t0x%08x\n",
1908 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1911 fprintf_filtered (file, "fpul_c\t0x%08x\n",
1912 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1918 sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file,
1919 struct frame_info *frame, int regnum)
1920 { /* Do values for FP (float) regs. */
1921 unsigned char *raw_buffer;
1922 double flt; /* Double extracted from raw hex data. */
1926 /* Allocate space for the float. */
1927 raw_buffer = (unsigned char *)
1928 alloca (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)));
1930 /* Get the data in raw format. */
1931 if (!deprecated_frame_register_read (frame, regnum, raw_buffer))
1932 error (_("can't read register %d (%s)"),
1933 regnum, gdbarch_register_name (gdbarch, regnum));
1935 /* Get the register as a number. */
1936 flt = unpack_double (builtin_type (gdbarch)->builtin_float,
1939 /* Print the name and some spaces. */
1940 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
1941 print_spaces_filtered (15 - strlen (gdbarch_register_name
1942 (gdbarch, regnum)), file);
1944 /* Print the value. */
1946 fprintf_filtered (file, "<invalid float>");
1948 fprintf_filtered (file, "%-10.9g", flt);
1950 /* Print the fp register as hex. */
1951 fprintf_filtered (file, "\t(raw ");
1952 print_hex_chars (file, raw_buffer,
1953 register_size (gdbarch, regnum),
1954 gdbarch_byte_order (gdbarch));
1955 fprintf_filtered (file, ")");
1956 fprintf_filtered (file, "\n");
1960 sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1961 struct frame_info *frame, int regnum)
1963 /* All the sh64-compact mode registers are pseudo registers. */
1965 if (regnum < gdbarch_num_regs (gdbarch)
1966 || regnum >= gdbarch_num_regs (gdbarch)
1967 + NUM_PSEUDO_REGS_SH_MEDIA
1968 + NUM_PSEUDO_REGS_SH_COMPACT)
1969 internal_error (__FILE__, __LINE__,
1970 _("Invalid pseudo register number %d\n"), regnum);
1972 else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM))
1974 int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum);
1975 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM,
1976 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1977 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
1980 else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM))
1982 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
1983 fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM,
1984 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1985 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
1988 else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM))
1990 int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum);
1991 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1992 regnum - FV0_REGNUM,
1993 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1994 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
1995 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
1996 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
1999 else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM))
2001 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2002 fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2003 regnum - FV0_C_REGNUM,
2004 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2005 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2006 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2007 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2010 else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM)
2012 int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum);
2013 fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM,
2014 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2015 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2018 else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM)
2020 int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2021 fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM,
2022 (unsigned) get_frame_register_unsigned (frame, c_regnum));
2024 else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM)
2025 /* This should work also for pseudoregs. */
2026 sh64_do_fp_register (gdbarch, file, frame, regnum);
2027 else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM)
2028 sh64_do_cr_c_register_info (file, frame, regnum);
2032 sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file,
2033 struct frame_info *frame, int regnum)
2035 unsigned char raw_buffer[MAX_REGISTER_SIZE];
2036 struct value_print_options opts;
2038 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
2039 print_spaces_filtered (15 - strlen (gdbarch_register_name
2040 (gdbarch, regnum)), file);
2042 /* Get the data in raw format. */
2043 if (!deprecated_frame_register_read (frame, regnum, raw_buffer))
2045 fprintf_filtered (file, "*value not available*\n");
2049 get_formatted_print_options (&opts, 'x');
2051 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2052 file, 0, NULL, &opts, current_language);
2053 fprintf_filtered (file, "\t");
2054 get_formatted_print_options (&opts, 0);
2056 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2057 file, 0, NULL, &opts, current_language);
2058 fprintf_filtered (file, "\n");
2062 sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file,
2063 struct frame_info *frame, int regnum)
2065 if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch)
2066 + gdbarch_num_pseudo_regs (gdbarch))
2067 internal_error (__FILE__, __LINE__,
2068 _("Invalid register number %d\n"), regnum);
2070 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
2072 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2073 sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */
2075 sh64_do_register (gdbarch, file, frame, regnum);
2078 else if (regnum < gdbarch_num_regs (gdbarch)
2079 + gdbarch_num_pseudo_regs (gdbarch))
2080 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2084 sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2085 struct frame_info *frame, int regnum,
2088 if (regnum != -1) /* Do one specified register. */
2090 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2091 error (_("Not a valid register for the current processor type"));
2093 sh64_print_register (gdbarch, file, frame, regnum);
2096 /* Do all (or most) registers. */
2099 while (regnum < gdbarch_num_regs (gdbarch))
2101 /* If the register name is empty, it is undefined for this
2102 processor, so don't display anything. */
2103 if (gdbarch_register_name (gdbarch, regnum) == NULL
2104 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
2110 if (TYPE_CODE (register_type (gdbarch, regnum))
2115 /* true for "INFO ALL-REGISTERS" command. */
2116 sh64_do_fp_register (gdbarch, file, frame, regnum);
2120 regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch);
2125 sh64_do_register (gdbarch, file, frame, regnum);
2131 while (regnum < gdbarch_num_regs (gdbarch)
2132 + gdbarch_num_pseudo_regs (gdbarch))
2134 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2141 sh64_compact_print_registers_info (struct gdbarch *gdbarch,
2142 struct ui_file *file,
2143 struct frame_info *frame, int regnum,
2146 if (regnum != -1) /* Do one specified register. */
2148 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2149 error (_("Not a valid register for the current processor type"));
2151 if (regnum >= 0 && regnum < R0_C_REGNUM)
2152 error (_("Not a valid register for the current processor mode."));
2154 sh64_print_register (gdbarch, file, frame, regnum);
2157 /* Do all compact registers. */
2159 regnum = R0_C_REGNUM;
2160 while (regnum < gdbarch_num_regs (gdbarch)
2161 + gdbarch_num_pseudo_regs (gdbarch))
2163 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2170 sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2171 struct frame_info *frame, int regnum, int fpregs)
2173 if (pc_is_isa32 (get_frame_pc (frame)))
2174 sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2176 sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2179 static struct sh64_frame_cache *
2180 sh64_alloc_frame_cache (void)
2182 struct sh64_frame_cache *cache;
2185 cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache);
2189 cache->saved_sp = 0;
2190 cache->sp_offset = 0;
2193 /* Frameless until proven otherwise. */
2196 /* Saved registers. We initialize these to -1 since zero is a valid
2197 offset (that's where fp is supposed to be stored). */
2198 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2200 cache->saved_regs[i] = -1;
2206 static struct sh64_frame_cache *
2207 sh64_frame_cache (struct frame_info *this_frame, void **this_cache)
2209 struct gdbarch *gdbarch;
2210 struct sh64_frame_cache *cache;
2211 CORE_ADDR current_pc;
2217 gdbarch = get_frame_arch (this_frame);
2218 cache = sh64_alloc_frame_cache ();
2219 *this_cache = cache;
2221 current_pc = get_frame_pc (this_frame);
2222 cache->media_mode = pc_is_isa32 (current_pc);
2224 /* In principle, for normal frames, fp holds the frame pointer,
2225 which holds the base address for the current stack frame.
2226 However, for functions that don't need it, the frame pointer is
2227 optional. For these "frameless" functions the frame pointer is
2228 actually the frame pointer of the calling frame. */
2229 cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM);
2230 if (cache->base == 0)
2233 cache->pc = get_frame_func (this_frame);
2235 sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc);
2237 if (!cache->uses_fp)
2239 /* We didn't find a valid frame, which means that CACHE->base
2240 currently holds the frame pointer for our calling frame. If
2241 we're at the start of a function, or somewhere half-way its
2242 prologue, the function's frame probably hasn't been fully
2243 setup yet. Try to reconstruct the base address for the stack
2244 frame by looking at the stack pointer. For truly "frameless"
2245 functions this might work too. */
2246 cache->base = get_frame_register_unsigned
2247 (this_frame, gdbarch_sp_regnum (gdbarch));
2250 /* Now that we have the base address for the stack frame we can
2251 calculate the value of sp in the calling frame. */
2252 cache->saved_sp = cache->base + cache->sp_offset;
2254 /* Adjust all the saved registers such that they contain addresses
2255 instead of offsets. */
2256 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2257 if (cache->saved_regs[i] != -1)
2258 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i];
2263 static struct value *
2264 sh64_frame_prev_register (struct frame_info *this_frame,
2265 void **this_cache, int regnum)
2267 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2268 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2269 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2271 gdb_assert (regnum >= 0);
2273 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2274 frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2276 /* The PC of the previous frame is stored in the PR register of
2277 the current frame. Frob regnum so that we pull the value from
2278 the correct place. */
2279 if (regnum == gdbarch_pc_regnum (gdbarch))
2282 if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1)
2284 if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32
2285 && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM))
2288 val = read_memory_unsigned_integer (cache->saved_regs[regnum],
2290 return frame_unwind_got_constant (this_frame, regnum, val);
2293 return frame_unwind_got_memory (this_frame, regnum,
2294 cache->saved_regs[regnum]);
2297 return frame_unwind_got_register (this_frame, regnum, regnum);
2301 sh64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2302 struct frame_id *this_id)
2304 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2306 /* This marks the outermost frame. */
2307 if (cache->base == 0)
2310 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2313 static const struct frame_unwind sh64_frame_unwind = {
2315 default_frame_unwind_stop_reason,
2317 sh64_frame_prev_register,
2319 default_frame_sniffer
2323 sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2325 return frame_unwind_register_unsigned (next_frame,
2326 gdbarch_sp_regnum (gdbarch));
2330 sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2332 return frame_unwind_register_unsigned (next_frame,
2333 gdbarch_pc_regnum (gdbarch));
2336 static struct frame_id
2337 sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2339 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2340 gdbarch_sp_regnum (gdbarch));
2341 return frame_id_build (sp, get_frame_pc (this_frame));
2345 sh64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2347 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2352 static const struct frame_base sh64_frame_base = {
2354 sh64_frame_base_address,
2355 sh64_frame_base_address,
2356 sh64_frame_base_address
2361 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2363 struct gdbarch *gdbarch;
2364 struct gdbarch_tdep *tdep;
2366 /* If there is already a candidate, use it. */
2367 arches = gdbarch_list_lookup_by_info (arches, &info);
2369 return arches->gdbarch;
2371 /* None found, create a new architecture from the information
2373 tdep = XMALLOC (struct gdbarch_tdep);
2374 gdbarch = gdbarch_alloc (&info, tdep);
2376 /* Determine the ABI */
2377 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2379 /* If the ABI is the 64-bit one, it can only be sh-media. */
2380 tdep->sh_abi = SH_ABI_64;
2381 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2382 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2386 /* If the ABI is the 32-bit one it could be either media or
2388 tdep->sh_abi = SH_ABI_32;
2389 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2390 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2393 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2394 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2395 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2396 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2397 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2398 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2399 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2401 /* The number of real registers is the same whether we are in
2402 ISA16(compact) or ISA32(media). */
2403 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2404 set_gdbarch_sp_regnum (gdbarch, 15);
2405 set_gdbarch_pc_regnum (gdbarch, 64);
2406 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2407 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA
2408 + NUM_PSEUDO_REGS_SH_COMPACT);
2410 set_gdbarch_register_name (gdbarch, sh64_register_name);
2411 set_gdbarch_register_type (gdbarch, sh64_register_type);
2413 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2414 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2416 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
2418 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2419 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2421 set_gdbarch_return_value (gdbarch, sh64_return_value);
2423 set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue);
2424 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2426 set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call);
2428 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2430 set_gdbarch_frame_align (gdbarch, sh64_frame_align);
2431 set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp);
2432 set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc);
2433 set_gdbarch_dummy_id (gdbarch, sh64_dummy_id);
2434 frame_base_set_default (gdbarch, &sh64_frame_base);
2436 set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info);
2438 set_gdbarch_elf_make_msymbol_special (gdbarch,
2439 sh64_elf_make_msymbol_special);
2441 /* Hook in ABI-specific overrides, if they have been registered. */
2442 gdbarch_init_osabi (info, gdbarch);
2444 dwarf2_append_unwinders (gdbarch);
2445 frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind);