1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
4 2002, 2003, 2004 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
24 Contributed by Steve Chamberlain
38 #include "gdb_string.h"
39 #include "arch-utils.h"
40 #include "floatformat.h"
46 #include "solib-svr4.h"
50 /* registers numbers shared with the simulator */
51 #include "gdb/sim-sh.h"
53 /* Information that is dependent on the processor variant. */
66 /* Registers of SH5 */
70 DEFAULT_RETURN_REGNUM = 2,
71 STRUCT_RETURN_REGNUM = 2,
74 FLOAT_ARGLAST_REGNUM = 11,
79 /* FPP stands for Floating Point Pair, to avoid confusion with
80 GDB's FP0_REGNUM, which is the number of the first Floating
81 point register. Unfortunately on the sh5, the floating point
82 registers are called FR, and the floating point pairs are called FP. */
84 FPP_LAST_REGNUM = 204,
88 R_LAST_C_REGNUM = 236,
98 FP_LAST_C_REGNUM = 260,
100 DR_LAST_C_REGNUM = 268,
102 FV_LAST_C_REGNUM = 272,
103 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
104 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
105 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
106 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
107 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
111 /* Define other aspects of the stack frame.
112 we keep a copy of the worked out return pc lying around, since it
113 is a useful bit of info */
115 struct frame_extra_info
123 sh64_register_name (int reg_nr)
125 static char *register_names[] =
127 /* SH MEDIA MODE (ISA 32) */
128 /* general registers (64-bit) 0-63 */
129 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
130 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
131 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
132 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
133 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
134 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
135 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
136 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
141 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
144 /* target registers (64-bit) 68-75*/
145 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
147 /* floating point state control register (32-bit) 76 */
150 /* single precision floating point registers (32-bit) 77-140*/
151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
153 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
154 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
155 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
156 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
157 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
158 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
160 /* double precision registers (pseudo) 141-172 */
161 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
162 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
163 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
164 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
166 /* floating point pairs (pseudo) 173-204*/
167 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
168 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
169 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
170 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
172 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
173 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
174 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
176 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
177 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
178 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
180 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
182 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
183 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
184 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
185 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
186 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
191 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
193 return register_names[reg_nr];
196 #define NUM_PSEUDO_REGS_SH_MEDIA 80
197 #define NUM_PSEUDO_REGS_SH_COMPACT 51
199 /* Macros and functions for setting and testing a bit in a minimal
200 symbol that marks it as 32-bit function. The MSB of the minimal
201 symbol's "info" field is used for this purpose.
203 ELF_MAKE_MSYMBOL_SPECIAL
204 tests whether an ELF symbol is "special", i.e. refers
205 to a 32-bit function, and sets a "special" bit in a
206 minimal symbol to mark it as a 32-bit function
207 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
209 #define MSYMBOL_IS_SPECIAL(msym) \
210 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
213 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
218 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
220 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
221 SYMBOL_VALUE_ADDRESS (msym) |= 1;
225 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
226 are some macros to test, set, or clear bit 0 of addresses. */
227 #define IS_ISA32_ADDR(addr) ((addr) & 1)
228 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
229 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
232 pc_is_isa32 (bfd_vma memaddr)
234 struct minimal_symbol *sym;
236 /* If bit 0 of the address is set, assume this is a
237 ISA32 (shmedia) address. */
238 if (IS_ISA32_ADDR (memaddr))
241 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
242 the high bit of the info field. Use this to decide if the function is
244 sym = lookup_minimal_symbol_by_pc (memaddr);
246 return MSYMBOL_IS_SPECIAL (sym);
251 static const unsigned char *
252 sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
254 /* The BRK instruction for shmedia is
255 01101111 11110101 11111111 11110000
256 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
257 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
259 /* The BRK instruction for shcompact is
261 which translates in big endian mode to 0x0, 0x3b
262 and in little endian mode to 0x3b, 0x0*/
264 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
266 if (pc_is_isa32 (*pcptr))
268 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
269 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
270 *lenptr = sizeof (big_breakpoint_media);
271 return big_breakpoint_media;
275 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
276 *lenptr = sizeof (big_breakpoint_compact);
277 return big_breakpoint_compact;
282 if (pc_is_isa32 (*pcptr))
284 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
285 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
286 *lenptr = sizeof (little_breakpoint_media);
287 return little_breakpoint_media;
291 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
292 *lenptr = sizeof (little_breakpoint_compact);
293 return little_breakpoint_compact;
298 /* Prologue looks like
299 [mov.l <regs>,@-r15]...
304 Actually it can be more complicated than this. For instance, with
322 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
323 with l=1 and n = 18 0110101111110001010010100aaa0000 */
324 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
326 /* STS.L PR,@-r0 0100000000100010
327 r0-4-->r0, PR-->(r0) */
328 #define IS_STS_R0(x) ((x) == 0x4022)
330 /* STS PR, Rm 0000mmmm00101010
332 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
334 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
336 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
338 /* MOV.L R14,@(disp,r15) 000111111110dddd
339 R14-->(dispx4+r15) */
340 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
342 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
343 R18-->(dispx8+R14) */
344 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
346 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
347 R18-->(dispx8+R15) */
348 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
350 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
351 R18-->(dispx4+R15) */
352 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
354 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
355 R14-->(dispx8+R15) */
356 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
358 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
359 R14-->(dispx4+R15) */
360 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
362 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
364 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
366 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
368 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
370 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
372 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
374 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
376 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
378 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
380 /* MOV #imm, R0 1110 0000 ssss ssss
382 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
384 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
385 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
387 /* ADD r15,r0 0011 0000 1111 1100
389 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
391 /* MOV.L R14 @-R0 0010 0000 1110 0110
392 R14-->(R0-4), R0-4-->R0 */
393 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
395 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
396 where Rm is one of r2-r9 which are the argument registers. */
397 /* FIXME: Recognize the float and double register moves too! */
398 #define IS_MEDIA_IND_ARG_MOV(x) \
399 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
401 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
402 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
403 where Rm is one of r2-r9 which are the argument registers. */
404 #define IS_MEDIA_ARG_MOV(x) \
405 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
406 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
408 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
409 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
410 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
411 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
412 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
413 #define IS_MEDIA_MOV_TO_R14(x) \
414 ((((x) & 0xfffffc0f) == 0xa0e00000) \
415 || (((x) & 0xfffffc0f) == 0xa4e00000) \
416 || (((x) & 0xfffffc0f) == 0xa8e00000) \
417 || (((x) & 0xfffffc0f) == 0xb4e00000) \
418 || (((x) & 0xfffffc0f) == 0xbce00000))
420 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
422 #define IS_COMPACT_IND_ARG_MOV(x) \
423 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
425 /* compact direct arg move!
426 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
427 #define IS_COMPACT_ARG_MOV(x) \
428 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
430 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
431 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
432 #define IS_COMPACT_MOV_TO_R14(x) \
433 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
435 #define IS_JSR_R0(x) ((x) == 0x400b)
436 #define IS_NOP(x) ((x) == 0x0009)
439 /* MOV r15,r14 0110111011110011
441 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
443 /* ADD #imm,r15 01111111iiiiiiii
445 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
447 /* Skip any prologue before the guts of a function */
449 /* Skip the prologue using the debug information. If this fails we'll
450 fall back on the 'guess' method below. */
452 after_prologue (CORE_ADDR pc)
454 struct symtab_and_line sal;
455 CORE_ADDR func_addr, func_end;
457 /* If we can not find the symbol in the partial symbol table, then
458 there is no hope we can determine the function's start address
460 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
463 /* Get the line associated with FUNC_ADDR. */
464 sal = find_pc_line (func_addr, 0);
466 /* There are only two cases to consider. First, the end of the source line
467 is within the function bounds. In that case we return the end of the
468 source line. Second is the end of the source line extends beyond the
469 bounds of the current function. We need to use the slow code to
470 examine instructions in that case. */
471 if (sal.end < func_end)
478 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
482 int insn_size = (media_mode ? 4 : 2);
484 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
488 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
490 if (IS_MEDIA_IND_ARG_MOV (w))
492 /* This must be followed by a store to r14, so the argument
493 is where the debug info says it is. This can happen after
494 the SP has been saved, unfortunately. */
496 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
499 if (IS_MEDIA_MOV_TO_R14 (next_insn))
502 else if (IS_MEDIA_ARG_MOV (w))
504 /* These instructions store directly the argument in r14. */
512 w = read_memory_integer (here, insn_size);
515 if (IS_COMPACT_IND_ARG_MOV (w))
517 /* This must be followed by a store to r14, so the argument
518 is where the debug info says it is. This can happen after
519 the SP has been saved, unfortunately. */
521 int next_insn = 0xffff & read_memory_integer (here, insn_size);
523 if (IS_COMPACT_MOV_TO_R14 (next_insn))
526 else if (IS_COMPACT_ARG_MOV (w))
528 /* These instructions store directly the argument in r14. */
531 else if (IS_MOVL_R0 (w))
533 /* There is a function that gcc calls to get the arguments
534 passed correctly to the function. Only after this
535 function call the arguments will be found at the place
536 where they are supposed to be. This happens in case the
537 argument has to be stored into a 64-bit register (for
538 instance doubles, long longs). SHcompact doesn't have
539 access to the full 64-bits, so we store the register in
540 stack slot and store the address of the stack slot in
541 the register, then do a call through a wrapper that
542 loads the memory value into the register. A SHcompact
543 callee calls an argument decoder
544 (GCC_shcompact_incoming_args) that stores the 64-bit
545 value in a stack slot and stores the address of the
546 stack slot in the register. GCC thinks the argument is
547 just passed by transparent reference, but this is only
548 true after the argument decoder is called. Such a call
549 needs to be considered part of the prologue. */
551 /* This must be followed by a JSR @r0 instruction and by
552 a NOP instruction. After these, the prologue is over! */
554 int next_insn = 0xffff & read_memory_integer (here, insn_size);
556 if (IS_JSR_R0 (next_insn))
558 next_insn = 0xffff & read_memory_integer (here, insn_size);
561 if (IS_NOP (next_insn))
574 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
584 if (pc_is_isa32 (start_pc) == 0)
590 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
595 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
597 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
598 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
599 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
603 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
611 /* Don't bail out yet, we may have arguments stored in
612 registers here, according to the debug info, so that
613 gdb can print the frames correctly. */
614 start_pc = look_for_args_moves (here - insn_size, media_mode);
620 int w = 0xffff & read_memory_integer (here, insn_size);
623 if (IS_STS_R0 (w) || IS_STS_PR (w)
624 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
625 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
629 else if (IS_MOV_SP_FP (w))
637 /* Don't bail out yet, we may have arguments stored in
638 registers here, according to the debug info, so that
639 gdb can print the frames correctly. */
640 start_pc = look_for_args_moves (here - insn_size, media_mode);
650 sh_skip_prologue (CORE_ADDR pc)
652 CORE_ADDR post_prologue_pc;
654 /* See if we can determine the end of the prologue via the symbol table.
655 If so, then return either PC, or the PC after the prologue, whichever
657 post_prologue_pc = after_prologue (pc);
659 /* If after_prologue returned a useful address, then use it. Else
660 fall back on the instruction skipping code. */
661 if (post_prologue_pc != 0)
662 return max (pc, post_prologue_pc);
664 return sh64_skip_prologue_hard_way (pc);
667 /* Immediately after a function call, return the saved pc.
668 Can't always go through the frames for this because on some machines
669 the new frame is not set up until the new function executes
672 The return address is the value saved in the PR register + 4 */
674 sh_saved_pc_after_call (struct frame_info *frame)
676 return (ADDR_BITS_REMOVE (read_register (PR_REGNUM)));
679 /* Should call_function allocate stack space for a struct return? */
681 sh64_use_struct_convention (int gcc_p, struct type *type)
683 return (TYPE_LENGTH (type) > 8);
686 /* Store the address of the place in which to copy the structure the
687 subroutine will return. This is called from call_function.
689 We store structs through a pointer passed in R2 */
691 sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
693 write_register (STRUCT_RETURN_REGNUM, (addr));
696 /* Disassemble an instruction. */
698 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
700 info->endian = TARGET_BYTE_ORDER;
701 return print_insn_sh (memaddr, info);
704 /* Given a register number RN as it appears in an assembly
705 instruction, find the corresponding register number in the GDB
708 translate_insn_rn (int rn, int media_mode)
710 /* FIXME: this assumes that the number rn is for a not pseudo
716 /* These registers don't have a corresponding compact one. */
717 /* FIXME: This is probably not enough. */
719 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
722 if (rn >= 0 && rn <= R0_C_REGNUM)
723 return R0_C_REGNUM + rn;
729 /* Given a GDB frame, determine the address of the calling function's
730 frame. This will be used to create a new GDB frame struct, and
731 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
732 will be called for the new frame.
734 For us, the frame address is its stack pointer value, so we look up
735 the function prologue to determine the caller's sp value, and return it. */
737 sh64_frame_chain (struct frame_info *frame)
739 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
740 get_frame_base (frame),
741 get_frame_base (frame)))
742 return get_frame_base (frame); /* dummy frame same as caller's frame */
743 if (get_frame_pc (frame)
744 && !deprecated_inside_entry_file (get_frame_pc (frame)))
746 int media_mode = pc_is_isa32 (get_frame_pc (frame));
748 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
751 size = register_size (current_gdbarch,
752 translate_insn_rn (DEPRECATED_FP_REGNUM,
754 return read_memory_integer (get_frame_base (frame)
755 + get_frame_extra_info (frame)->f_offset,
763 sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
767 for (; fi; fi = get_next_frame (fi))
768 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
769 get_frame_base (fi)))
770 /* When the caller requests PR from the dummy frame, we return
771 PC because that's where the previous routine appears to have
773 return deprecated_read_register_dummy (get_frame_pc (fi),
774 get_frame_base (fi), pr_regnum);
777 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
778 if (!get_frame_pc (fi))
781 media_mode = pc_is_isa32 (get_frame_pc (fi));
783 if (deprecated_get_frame_saved_regs (fi)[pr_regnum] != 0)
785 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
786 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
788 : register_size (current_gdbarch, gdb_reg_num));
789 return read_memory_integer (deprecated_get_frame_saved_regs (fi)[pr_regnum], size);
792 return read_register (pr_regnum);
795 /* For vectors of 4 floating point registers. */
797 fv_reg_base_num (int fv_regnum)
801 fp_regnum = FP0_REGNUM +
802 (fv_regnum - FV0_REGNUM) * 4;
806 /* For double precision floating point registers, i.e 2 fp regs.*/
808 dr_reg_base_num (int dr_regnum)
812 fp_regnum = FP0_REGNUM +
813 (dr_regnum - DR0_REGNUM) * 2;
817 /* For pairs of floating point registers */
819 fpp_reg_base_num (int fpp_regnum)
823 fp_regnum = FP0_REGNUM +
824 (fpp_regnum - FPP0_REGNUM) * 2;
829 is_media_pseudo (int rn)
831 return (rn >= DR0_REGNUM && rn <= FV_LAST_REGNUM);
835 sh64_media_reg_base_num (int reg_nr)
837 int base_regnum = -1;
839 if (reg_nr >= DR0_REGNUM
840 && reg_nr <= DR_LAST_REGNUM)
841 base_regnum = dr_reg_base_num (reg_nr);
843 else if (reg_nr >= FPP0_REGNUM
844 && reg_nr <= FPP_LAST_REGNUM)
845 base_regnum = fpp_reg_base_num (reg_nr);
847 else if (reg_nr >= FV0_REGNUM
848 && reg_nr <= FV_LAST_REGNUM)
849 base_regnum = fv_reg_base_num (reg_nr);
856 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
857 GDB_REGNUM BASE_REGNUM
917 sh64_compact_reg_base_num (int reg_nr)
919 int base_regnum = -1;
921 /* general register N maps to general register N */
922 if (reg_nr >= R0_C_REGNUM
923 && reg_nr <= R_LAST_C_REGNUM)
924 base_regnum = reg_nr - R0_C_REGNUM;
926 /* floating point register N maps to floating point register N */
927 else if (reg_nr >= FP0_C_REGNUM
928 && reg_nr <= FP_LAST_C_REGNUM)
929 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
931 /* double prec register N maps to base regnum for double prec register N */
932 else if (reg_nr >= DR0_C_REGNUM
933 && reg_nr <= DR_LAST_C_REGNUM)
934 base_regnum = dr_reg_base_num (DR0_REGNUM
935 + reg_nr - DR0_C_REGNUM);
937 /* vector N maps to base regnum for vector register N */
938 else if (reg_nr >= FV0_C_REGNUM
939 && reg_nr <= FV_LAST_C_REGNUM)
940 base_regnum = fv_reg_base_num (FV0_REGNUM
941 + reg_nr - FV0_C_REGNUM);
943 else if (reg_nr == PC_C_REGNUM)
944 base_regnum = PC_REGNUM;
946 else if (reg_nr == GBR_C_REGNUM)
949 else if (reg_nr == MACH_C_REGNUM
950 || reg_nr == MACL_C_REGNUM)
953 else if (reg_nr == PR_C_REGNUM)
956 else if (reg_nr == T_C_REGNUM)
959 else if (reg_nr == FPSCR_C_REGNUM)
960 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
962 else if (reg_nr == FPUL_C_REGNUM)
963 base_regnum = FP0_REGNUM + 32;
968 /* Given a register number RN (according to the gdb scheme) , return
969 its corresponding architectural register. In media mode, only a
970 subset of the registers is pseudo registers. For compact mode, all
971 the registers are pseudo. */
973 translate_rn_to_arch_reg_num (int rn, int media_mode)
978 if (!is_media_pseudo (rn))
981 return sh64_media_reg_base_num (rn);
984 /* All compact registers are pseudo. */
985 return sh64_compact_reg_base_num (rn);
989 sign_extend (int value, int bits)
991 value = value & ((1 << bits) - 1);
992 return (value & (1 << (bits - 1))
993 ? value | (~((1 << bits) - 1))
998 sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
1000 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1012 int gdb_register_number;
1013 int register_number;
1014 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi),
1015 get_frame_base (fi));
1016 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1018 if (deprecated_get_frame_saved_regs (fi) == NULL)
1019 frame_saved_regs_zalloc (fi);
1021 memset (deprecated_get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1025 /* DANGER! This is ONLY going to work if the char buffer format of
1026 the saved registers is byte-for-byte identical to the
1027 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1028 memcpy (deprecated_get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1032 get_frame_extra_info (fi)->leaf_function = 1;
1033 get_frame_extra_info (fi)->f_offset = 0;
1035 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1040 /* Loop around examining the prologue insns until we find something
1041 that does not appear to be part of the prologue. But give up
1042 after 20 of them, since we're getting silly then. */
1044 pc = get_frame_func (fi);
1047 deprecated_update_frame_pc_hack (fi, 0);
1051 if (pc_is_isa32 (pc))
1062 /* The frame pointer register is general register 14 in shmedia and
1063 shcompact modes. In sh compact it is a pseudo register. Same goes
1064 for the stack pointer register, which is register 15. */
1065 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1066 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1068 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1070 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1073 if (media_mode == 0)
1075 if (IS_STS_PR (insn))
1077 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1078 if (IS_MOV_TO_R15 (next_insn))
1080 int reg_nr = PR_C_REGNUM;
1082 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1083 get_frame_extra_info (fi)->leaf_function = 0;
1087 else if (IS_MOV_R14 (insn))
1089 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1092 else if (IS_MOV_R0 (insn))
1094 /* Put in R0 the offset from SP at which to store some
1095 registers. We are interested in this value, because it
1096 will tell us where the given registers are stored within
1098 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1100 else if (IS_ADD_SP_R0 (insn))
1102 /* This instruction still prepares r0, but we don't care.
1103 We already have the offset in r0_val. */
1105 else if (IS_STS_R0 (insn))
1107 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1108 int reg_nr = PR_C_REGNUM;
1109 where[reg_nr] = depth - (r0_val - 4);
1111 get_frame_extra_info (fi)->leaf_function = 0;
1113 else if (IS_MOV_R14_R0 (insn))
1115 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1116 where[fp_regnum] = depth - (r0_val - 4);
1120 else if (IS_ADD_SP (insn))
1122 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1124 else if (IS_MOV_SP_FP (insn))
1129 if (IS_ADDIL_SP_MEDIA (insn)
1130 || IS_ADDI_SP_MEDIA (insn))
1132 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1135 else if (IS_STQ_R18_R15 (insn))
1138 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1139 get_frame_extra_info (fi)->leaf_function = 0;
1142 else if (IS_STL_R18_R15 (insn))
1145 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1146 get_frame_extra_info (fi)->leaf_function = 0;
1149 else if (IS_STQ_R14_R15 (insn))
1151 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1154 else if (IS_STL_R14_R15 (insn))
1156 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1159 else if (IS_MOV_SP_FP_MEDIA (insn))
1164 /* Now we know how deep things are, we can work out their addresses. */
1165 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1167 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1171 if (rn == fp_regnum)
1174 /* Watch out! saved_regs is only for the real registers, and
1175 doesn't include space for the pseudo registers. */
1176 deprecated_get_frame_saved_regs (fi)[register_number]
1177 = get_frame_base (fi) - where[rn] + depth;
1180 deprecated_get_frame_saved_regs (fi)[register_number] = 0;
1185 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1186 shcompact 15 is the arch register corresponding to the pseudo
1187 register r15 which still is the SP register. */
1188 /* The place on the stack where fp is stored contains the sp of
1190 /* Again, saved_registers contains only space for the real
1191 registers, so we store in DEPRECATED_FP_REGNUM position. */
1193 if (tdep->sh_abi == SH_ABI_32)
1196 size = register_size (current_gdbarch, fp_regnum);
1197 deprecated_get_frame_saved_regs (fi)[sp_regnum]
1198 = read_memory_integer (deprecated_get_frame_saved_regs (fi)[fp_regnum],
1202 deprecated_get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
1204 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
1207 /* Initialize the extra info saved in a FRAME */
1209 sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1211 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1213 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1215 if (get_next_frame (fi))
1216 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1218 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1219 get_frame_base (fi)))
1221 /* We need to setup fi->frame here because call_function_by_hand
1222 gets it wrong by assuming it's always FP. */
1223 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1224 get_frame_extra_info (fi)->return_pc =
1225 deprecated_read_register_dummy (get_frame_pc (fi),
1226 get_frame_base (fi), PC_REGNUM);
1227 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1228 get_frame_extra_info (fi)->leaf_function = 0;
1233 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1234 get_frame_extra_info (fi)->return_pc =
1235 sh64_get_saved_pr (fi, PR_REGNUM);
1240 sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1241 struct frame_info *frame, int regnum,
1242 enum lval_type *lval)
1245 int live_regnum = regnum;
1246 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1248 if (!target_has_registers)
1249 error ("No registers.");
1251 /* Normal systems don't optimize out things with register numbers. */
1252 if (optimized != NULL)
1255 if (addrp) /* default assumption: not found in memory */
1259 memset (raw_buffer, 0, sizeof (raw_buffer));
1261 /* We must do this here, before the following while loop changes
1262 frame, and makes it NULL. If this is a media register number,
1263 but we are in compact mode, it will become the corresponding
1264 compact pseudo register. If there is no corresponding compact
1265 pseudo-register what do we do?*/
1266 media_mode = pc_is_isa32 (get_frame_pc (frame));
1267 live_regnum = translate_insn_rn (regnum, media_mode);
1269 /* Note: since the current frame's registers could only have been
1270 saved by frames INTERIOR TO the current frame, we skip examining
1271 the current frame itself: otherwise, we would be getting the
1272 previous frame's registers which were saved by the current frame. */
1274 while (frame && ((frame = get_next_frame (frame)) != NULL))
1276 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1277 get_frame_base (frame),
1278 get_frame_base (frame)))
1280 if (lval) /* found it in a CALL_DUMMY frame */
1284 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
1285 + DEPRECATED_REGISTER_BYTE (regnum)),
1286 register_size (current_gdbarch, regnum));
1290 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1291 if (deprecated_get_frame_saved_regs (frame) != NULL
1292 && deprecated_get_frame_saved_regs (frame)[regnum] != 0)
1294 if (lval) /* found it saved on the stack */
1295 *lval = lval_memory;
1296 if (regnum == SP_REGNUM)
1298 if (raw_buffer) /* SP register treated specially */
1299 store_unsigned_integer (raw_buffer,
1300 register_size (current_gdbarch,
1302 deprecated_get_frame_saved_regs (frame)[regnum]);
1305 { /* any other register */
1308 *addrp = deprecated_get_frame_saved_regs (frame)[regnum];
1312 if (tdep->sh_abi == SH_ABI_32
1313 && (live_regnum == DEPRECATED_FP_REGNUM
1314 || live_regnum == PR_REGNUM))
1317 size = register_size (current_gdbarch, live_regnum);
1318 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1319 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
1322 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
1324 + register_size (current_gdbarch, live_regnum)
1333 /* If we get thru the loop to this point, it means the register was
1334 not saved in any frame. Return the actual live-register value. */
1336 if (lval) /* found it in a live register */
1337 *lval = lval_register;
1339 *addrp = DEPRECATED_REGISTER_BYTE (live_regnum);
1341 deprecated_read_register_gen (live_regnum, raw_buffer);
1345 sh64_extract_struct_value_address (struct regcache *regcache)
1347 /* FIXME: cagney/2004-01-17: Does the ABI guarantee that the return
1348 address regster is preserved across function calls? Probably
1349 not, making this function wrong. */
1351 regcache_raw_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &val);
1356 sh_frame_saved_pc (struct frame_info *frame)
1358 return (get_frame_extra_info (frame)->return_pc);
1361 /* Discard from the stack the innermost frame, restoring all saved registers.
1362 Used in the 'return' command. */
1364 sh64_pop_frame (void)
1366 struct frame_info *frame = get_current_frame ();
1369 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1371 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1373 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1374 get_frame_base (frame),
1375 get_frame_base (frame)))
1376 generic_pop_dummy_frame ();
1379 fp = get_frame_base (frame);
1380 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1382 /* Copy regs from where they were saved in the frame */
1383 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1384 if (deprecated_get_frame_saved_regs (frame)[regnum])
1387 if (tdep->sh_abi == SH_ABI_32
1388 && (regnum == DEPRECATED_FP_REGNUM
1389 || regnum == PR_REGNUM))
1392 size = register_size (current_gdbarch,
1393 translate_insn_rn (regnum, media_mode));
1394 write_register (regnum,
1395 read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
1399 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1400 write_register (SP_REGNUM, fp + 8);
1402 flush_cached_frames ();
1406 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
1411 /* Function: push_arguments
1412 Setup the function arguments for calling a function in the inferior.
1414 On the Renesas SH architecture, there are four registers (R4 to R7)
1415 which are dedicated for passing function arguments. Up to the first
1416 four arguments (depending on size) may go into these registers.
1417 The rest go on the stack.
1419 Arguments that are smaller than 4 bytes will still take up a whole
1420 register or a whole 32-bit word on the stack, and will be
1421 right-justified in the register or the stack word. This includes
1422 chars, shorts, and small aggregate types.
1424 Arguments that are larger than 4 bytes may be split between two or
1425 more registers. If there are not enough registers free, an argument
1426 may be passed partly in a register (or registers), and partly on the
1427 stack. This includes doubles, long longs, and larger aggregates.
1428 As far as I know, there is no upper limit to the size of aggregates
1429 that will be passed in this way; in other words, the convention of
1430 passing a pointer to a large aggregate instead of a copy is not used.
1432 An exceptional case exists for struct arguments (and possibly other
1433 aggregates such as arrays) if the size is larger than 4 bytes but
1434 not a multiple of 4 bytes. In this case the argument is never split
1435 between the registers and the stack, but instead is copied in its
1436 entirety onto the stack, AND also copied into as many registers as
1437 there is room for. In other words, space in registers permitting,
1438 two copies of the same argument are passed in. As far as I can tell,
1439 only the one on the stack is used, although that may be a function
1440 of the level of compiler optimization. I suspect this is a compiler
1441 bug. Arguments of these odd sizes are left-justified within the
1442 word (as opposed to arguments smaller than 4 bytes, which are
1445 If the function is to return an aggregate type such as a struct, it
1446 is either returned in the normal return value register R0 (if its
1447 size is no greater than one byte), or else the caller must allocate
1448 space into which the callee will copy the return value (if the size
1449 is greater than one byte). In this case, a pointer to the return
1450 value location is passed into the callee in register R2, which does
1451 not displace any of the other arguments passed in via registers R4
1454 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1455 non-scalar (struct, union) elements (even if the elements are
1457 FR0-FR11 for single precision floating point (float)
1458 DR0-DR10 for double precision floating point (double)
1460 If a float is argument number 3 (for instance) and arguments number
1461 1,2, and 4 are integer, the mapping will be:
1462 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1464 If a float is argument number 10 (for instance) and arguments number
1465 1 through 10 are integer, the mapping will be:
1466 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1467 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1468 I.e. there is hole in the stack.
1470 Different rules apply for variable arguments functions, and for functions
1471 for which the prototype is not known. */
1474 sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1475 int struct_return, CORE_ADDR struct_addr)
1477 int stack_offset, stack_alloc;
1481 int float_arg_index = 0;
1482 int double_arg_index = 0;
1493 memset (fp_args, 0, sizeof (fp_args));
1495 /* first force sp to a 8-byte alignment */
1498 /* The "struct return pointer" pseudo-argument has its own dedicated
1502 write_register (STRUCT_RETURN_REGNUM, struct_addr);
1504 /* Now make sure there's space on the stack */
1505 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1506 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
1507 sp -= stack_alloc; /* make room on stack for args */
1509 /* Now load as many as possible of the first arguments into
1510 registers, and push the rest onto the stack. There are 64 bytes
1511 in eight registers available. Loop thru args from first to last. */
1513 int_argreg = ARG0_REGNUM;
1514 float_argreg = FP0_REGNUM;
1515 double_argreg = DR0_REGNUM;
1517 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1519 type = VALUE_TYPE (args[argnum]);
1520 len = TYPE_LENGTH (type);
1521 memset (valbuf, 0, sizeof (valbuf));
1523 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1525 argreg_size = register_size (current_gdbarch, int_argreg);
1527 if (len < argreg_size)
1529 /* value gets right-justified in the register or stack word */
1530 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1531 memcpy (valbuf + argreg_size - len,
1532 (char *) VALUE_CONTENTS (args[argnum]), len);
1534 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
1539 val = (char *) VALUE_CONTENTS (args[argnum]);
1543 if (int_argreg > ARGLAST_REGNUM)
1545 /* must go on the stack */
1546 write_memory (sp + stack_offset, val, argreg_size);
1547 stack_offset += 8;/*argreg_size;*/
1549 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1550 That's because some *&^%$ things get passed on the stack
1551 AND in the registers! */
1552 if (int_argreg <= ARGLAST_REGNUM)
1554 /* there's room in a register */
1555 regval = extract_unsigned_integer (val, argreg_size);
1556 write_register (int_argreg, regval);
1558 /* Store the value 8 bytes at a time. This means that
1559 things larger than 8 bytes may go partly in registers
1560 and partly on the stack. FIXME: argreg is incremented
1561 before we use its size. */
1569 val = (char *) VALUE_CONTENTS (args[argnum]);
1572 /* Where is it going to be stored? */
1573 while (fp_args[float_arg_index])
1576 /* Now float_argreg points to the register where it
1577 should be stored. Are we still within the allowed
1579 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1581 /* Goes in FR0...FR11 */
1582 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
1584 fp_args[float_arg_index] = 1;
1585 /* Skip the corresponding general argument register. */
1590 /* Store it as the integers, 8 bytes at the time, if
1591 necessary spilling on the stack. */
1596 /* Where is it going to be stored? */
1597 while (fp_args[double_arg_index])
1598 double_arg_index += 2;
1599 /* Now double_argreg points to the register
1600 where it should be stored.
1601 Are we still within the allowed register set? */
1602 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1604 /* Goes in DR0...DR10 */
1605 /* The numbering of the DRi registers is consecutive,
1606 i.e. includes odd numbers. */
1607 int double_register_offset = double_arg_index / 2;
1608 int regnum = DR0_REGNUM +
1609 double_register_offset;
1611 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1613 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
1614 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
1620 /* Note: must use write_register_gen here instead
1621 of regcache_raw_write, because
1622 regcache_raw_write works only for real
1623 registers, not pseudo. write_register_gen will
1624 call the gdbarch function to do register
1625 writes, and that will properly know how to deal
1627 deprecated_write_register_gen (regnum, val);
1628 fp_args[double_arg_index] = 1;
1629 fp_args[double_arg_index + 1] = 1;
1630 /* Skip the corresponding general argument register. */
1635 /* Store it as the integers, 8 bytes at the time, if
1636 necessary spilling on the stack. */
1643 /* Function: push_return_address (pc)
1644 Set up the return address for the inferior function call.
1645 Needed for targets where we don't actually execute a JSR/BSR instruction */
1648 sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1650 write_register (PR_REGNUM, entry_point_address ());
1654 /* Find a function's return value in the appropriate registers (in
1655 regbuf), and copy it into valbuf. Extract from an array REGBUF
1656 containing the (raw) register state a function return value of type
1657 TYPE, and copy that, in virtual format, into VALBUF. */
1659 sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1662 int return_register;
1663 int len = TYPE_LENGTH (type);
1665 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1669 /* Return value stored in FP0_REGNUM */
1670 return_register = FP0_REGNUM;
1671 offset = DEPRECATED_REGISTER_BYTE (return_register);
1672 memcpy (valbuf, (char *) regbuf + offset, len);
1676 /* return value stored in DR0_REGNUM */
1679 return_register = DR0_REGNUM;
1680 offset = DEPRECATED_REGISTER_BYTE (return_register);
1682 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1683 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1684 (char *) regbuf + offset, &val);
1686 floatformat_to_doublest (&floatformat_ieee_double_big,
1687 (char *) regbuf + offset, &val);
1688 store_typed_floating (valbuf, type, val);
1695 /* Result is in register 2. If smaller than 8 bytes, it is padded
1696 at the most significant end. */
1697 return_register = DEFAULT_RETURN_REGNUM;
1698 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1699 offset = DEPRECATED_REGISTER_BYTE (return_register) +
1700 register_size (current_gdbarch, return_register) - len;
1702 offset = DEPRECATED_REGISTER_BYTE (return_register);
1703 memcpy (valbuf, (char *) regbuf + offset, len);
1706 error ("bad size for return value");
1710 /* Write into appropriate registers a function return value
1711 of type TYPE, given in virtual format.
1712 If the architecture is sh4 or sh3e, store a function's return value
1713 in the R0 general register or in the FP0 floating point register,
1714 depending on the type of the return value. In all the other cases
1715 the result is stored in r0, left-justified. */
1718 sh64_store_return_value (struct type *type, char *valbuf)
1720 char buf[64]; /* more than enough... */
1721 int len = TYPE_LENGTH (type);
1723 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1727 /* Return value stored in FP0_REGNUM */
1728 deprecated_write_register_gen (FP0_REGNUM, valbuf);
1732 /* return value stored in DR0_REGNUM */
1733 /* FIXME: Implement */
1738 int return_register = DEFAULT_RETURN_REGNUM;
1741 if (len <= register_size (current_gdbarch, return_register))
1743 /* Pad with zeros. */
1744 memset (buf, 0, register_size (current_gdbarch, return_register));
1745 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1746 offset = 0; /*register_size (current_gdbarch,
1747 return_register) - len;*/
1749 offset = register_size (current_gdbarch, return_register) - len;
1751 memcpy (buf + offset, valbuf, len);
1752 deprecated_write_register_gen (return_register, buf);
1755 deprecated_write_register_gen (return_register, valbuf);
1760 sh64_show_media_regs (void)
1764 printf_filtered ("PC=%s SR=%016llx \n",
1765 paddr (read_register (PC_REGNUM)),
1766 (long long) read_register (SR_REGNUM));
1768 printf_filtered ("SSR=%016llx SPC=%016llx \n",
1769 (long long) read_register (SSR_REGNUM),
1770 (long long) read_register (SPC_REGNUM));
1771 printf_filtered ("FPSCR=%016lx\n ",
1772 (long) read_register (FPSCR_REGNUM));
1774 for (i = 0; i < 64; i = i + 4)
1775 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1777 (long long) read_register (i + 0),
1778 (long long) read_register (i + 1),
1779 (long long) read_register (i + 2),
1780 (long long) read_register (i + 3));
1782 printf_filtered ("\n");
1784 for (i = 0; i < 64; i = i + 8)
1785 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1787 (long) read_register (FP0_REGNUM + i + 0),
1788 (long) read_register (FP0_REGNUM + i + 1),
1789 (long) read_register (FP0_REGNUM + i + 2),
1790 (long) read_register (FP0_REGNUM + i + 3),
1791 (long) read_register (FP0_REGNUM + i + 4),
1792 (long) read_register (FP0_REGNUM + i + 5),
1793 (long) read_register (FP0_REGNUM + i + 6),
1794 (long) read_register (FP0_REGNUM + i + 7));
1798 sh64_show_compact_regs (void)
1802 printf_filtered ("PC=%s \n",
1803 paddr (read_register (PC_C_REGNUM)));
1805 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1806 (long) read_register (GBR_C_REGNUM),
1807 (long) read_register (MACH_C_REGNUM),
1808 (long) read_register (MACL_C_REGNUM),
1809 (long) read_register (PR_C_REGNUM),
1810 (long) read_register (T_C_REGNUM));
1811 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
1812 (long) read_register (FPSCR_C_REGNUM),
1813 (long) read_register (FPUL_C_REGNUM));
1815 for (i = 0; i < 16; i = i + 4)
1816 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1818 (long) read_register (i + 0),
1819 (long) read_register (i + 1),
1820 (long) read_register (i + 2),
1821 (long) read_register (i + 3));
1823 printf_filtered ("\n");
1825 for (i = 0; i < 16; i = i + 8)
1826 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1828 (long) read_register (FP0_REGNUM + i + 0),
1829 (long) read_register (FP0_REGNUM + i + 1),
1830 (long) read_register (FP0_REGNUM + i + 2),
1831 (long) read_register (FP0_REGNUM + i + 3),
1832 (long) read_register (FP0_REGNUM + i + 4),
1833 (long) read_register (FP0_REGNUM + i + 5),
1834 (long) read_register (FP0_REGNUM + i + 6),
1835 (long) read_register (FP0_REGNUM + i + 7));
1838 /* FIXME!!! This only shows the registers for shmedia, excluding the
1839 pseudo registers. */
1841 sh64_show_regs (void)
1843 if (deprecated_selected_frame
1844 && pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
1845 sh64_show_media_regs ();
1847 sh64_show_compact_regs ();
1852 SH MEDIA MODE (ISA 32)
1853 general registers (64-bit) 0-63
1854 0 r0, r1, r2, r3, r4, r5, r6, r7,
1855 64 r8, r9, r10, r11, r12, r13, r14, r15,
1856 128 r16, r17, r18, r19, r20, r21, r22, r23,
1857 192 r24, r25, r26, r27, r28, r29, r30, r31,
1858 256 r32, r33, r34, r35, r36, r37, r38, r39,
1859 320 r40, r41, r42, r43, r44, r45, r46, r47,
1860 384 r48, r49, r50, r51, r52, r53, r54, r55,
1861 448 r56, r57, r58, r59, r60, r61, r62, r63,
1866 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1869 target registers (64-bit) 68-75
1870 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1872 floating point state control register (32-bit) 76
1875 single precision floating point registers (32-bit) 77-140
1876 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1877 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1878 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1879 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1880 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1881 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1882 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1883 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1885 TOTAL SPACE FOR REGISTERS: 868 bytes
1887 From here on they are all pseudo registers: no memory allocated.
1888 REGISTER_BYTE returns the register byte for the base register.
1890 double precision registers (pseudo) 141-172
1891 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1892 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1893 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1894 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1896 floating point pairs (pseudo) 173-204
1897 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1898 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1899 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1900 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1902 floating point vectors (4 floating point regs) (pseudo) 205-220
1903 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1904 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1906 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1907 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1908 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1910 gbr_c, mach_c, macl_c, pr_c, t_c,
1912 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1913 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1914 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1915 fv0_c, fv4_c, fv8_c, fv12_c
1919 sh64_register_byte (int reg_nr)
1921 int base_regnum = -1;
1923 /* If it is a pseudo register, get the number of the first floating
1924 point register that is part of it. */
1925 if (reg_nr >= DR0_REGNUM
1926 && reg_nr <= DR_LAST_REGNUM)
1927 base_regnum = dr_reg_base_num (reg_nr);
1929 else if (reg_nr >= FPP0_REGNUM
1930 && reg_nr <= FPP_LAST_REGNUM)
1931 base_regnum = fpp_reg_base_num (reg_nr);
1933 else if (reg_nr >= FV0_REGNUM
1934 && reg_nr <= FV_LAST_REGNUM)
1935 base_regnum = fv_reg_base_num (reg_nr);
1937 /* sh compact pseudo register. FPSCR is a pathological case, need to
1938 treat it as special. */
1939 else if ((reg_nr >= R0_C_REGNUM
1940 && reg_nr <= FV_LAST_C_REGNUM)
1941 && reg_nr != FPSCR_C_REGNUM)
1942 base_regnum = sh64_compact_reg_base_num (reg_nr);
1944 /* Now return the offset in bytes within the register cache. */
1945 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
1946 if (reg_nr >= DR0_REGNUM
1947 && reg_nr <= FV_LAST_REGNUM)
1948 return (base_regnum - FP0_REGNUM + 1) * 4
1949 + (TR7_REGNUM + 1) * 8;
1951 /* sh compact pseudo register: general register */
1952 if ((reg_nr >= R0_C_REGNUM
1953 && reg_nr <= R_LAST_C_REGNUM))
1954 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1955 ? base_regnum * 8 + 4
1958 /* sh compact pseudo register: */
1959 if (reg_nr == PC_C_REGNUM
1960 || reg_nr == GBR_C_REGNUM
1961 || reg_nr == MACL_C_REGNUM
1962 || reg_nr == PR_C_REGNUM)
1963 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1964 ? base_regnum * 8 + 4
1967 if (reg_nr == MACH_C_REGNUM)
1968 return base_regnum * 8;
1970 if (reg_nr == T_C_REGNUM)
1971 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
1973 /* sh compact pseudo register: floating point register */
1974 else if (reg_nr >= FP0_C_REGNUM
1975 && reg_nr <= FV_LAST_C_REGNUM)
1976 return (base_regnum - FP0_REGNUM) * 4
1977 + (TR7_REGNUM + 1) * 8 + 4;
1979 else if (reg_nr == FPSCR_C_REGNUM)
1980 /* This is complicated, for now return the beginning of the
1981 architectural FPSCR register. */
1982 return (TR7_REGNUM + 1) * 8;
1984 else if (reg_nr == FPUL_C_REGNUM)
1985 return ((base_regnum - FP0_REGNUM) * 4 +
1986 (TR7_REGNUM + 1) * 8 + 4);
1988 /* It is not a pseudo register. */
1989 /* It is a 64 bit register. */
1990 else if (reg_nr <= TR7_REGNUM)
1993 /* It is a 32 bit register. */
1994 else if (reg_nr == FPSCR_REGNUM)
1995 return (FPSCR_REGNUM * 8);
1997 /* It is floating point 32-bit register */
1999 return ((TR7_REGNUM + 1) * 8
2000 + (reg_nr - FP0_REGNUM + 1) * 4);
2003 static struct type *
2004 sh64_build_float_register_type (int high)
2008 temp = create_range_type (NULL, builtin_type_int, 0, high);
2009 return create_array_type (NULL, builtin_type_float, temp);
2012 /* Return the GDB type object for the "standard" data type
2013 of data in register REG_NR. */
2014 static struct type *
2015 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
2017 if ((reg_nr >= FP0_REGNUM
2018 && reg_nr <= FP_LAST_REGNUM)
2019 || (reg_nr >= FP0_C_REGNUM
2020 && reg_nr <= FP_LAST_C_REGNUM))
2021 return builtin_type_float;
2022 else if ((reg_nr >= DR0_REGNUM
2023 && reg_nr <= DR_LAST_REGNUM)
2024 || (reg_nr >= DR0_C_REGNUM
2025 && reg_nr <= DR_LAST_C_REGNUM))
2026 return builtin_type_double;
2027 else if (reg_nr >= FPP0_REGNUM
2028 && reg_nr <= FPP_LAST_REGNUM)
2029 return sh64_build_float_register_type (1);
2030 else if ((reg_nr >= FV0_REGNUM
2031 && reg_nr <= FV_LAST_REGNUM)
2032 ||(reg_nr >= FV0_C_REGNUM
2033 && reg_nr <= FV_LAST_C_REGNUM))
2034 return sh64_build_float_register_type (3);
2035 else if (reg_nr == FPSCR_REGNUM)
2036 return builtin_type_int;
2037 else if (reg_nr >= R0_C_REGNUM
2038 && reg_nr < FP0_C_REGNUM)
2039 return builtin_type_int;
2041 return builtin_type_long_long;
2045 sh64_register_convert_to_virtual (int regnum, struct type *type,
2046 char *from, char *to)
2048 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2050 /* It is a no-op. */
2051 memcpy (to, from, register_size (current_gdbarch, regnum));
2055 if ((regnum >= DR0_REGNUM
2056 && regnum <= DR_LAST_REGNUM)
2057 || (regnum >= DR0_C_REGNUM
2058 && regnum <= DR_LAST_C_REGNUM))
2061 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2063 store_typed_floating (to, type, val);
2066 error ("sh64_register_convert_to_virtual called with non DR register number");
2070 sh64_register_convert_to_raw (struct type *type, int regnum,
2071 const void *from, void *to)
2073 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2075 /* It is a no-op. */
2076 memcpy (to, from, register_size (current_gdbarch, regnum));
2080 if ((regnum >= DR0_REGNUM
2081 && regnum <= DR_LAST_REGNUM)
2082 || (regnum >= DR0_C_REGNUM
2083 && regnum <= DR_LAST_C_REGNUM))
2085 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
2086 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2090 error ("sh64_register_convert_to_raw called with non DR register number");
2094 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2095 int reg_nr, void *buffer)
2100 char temp_buffer[MAX_REGISTER_SIZE];
2102 if (reg_nr >= DR0_REGNUM
2103 && reg_nr <= DR_LAST_REGNUM)
2105 base_regnum = dr_reg_base_num (reg_nr);
2107 /* Build the value in the provided buffer. */
2108 /* DR regs are double precision registers obtained by
2109 concatenating 2 single precision floating point registers. */
2110 for (portion = 0; portion < 2; portion++)
2111 regcache_raw_read (regcache, base_regnum + portion,
2113 + register_size (gdbarch, base_regnum) * portion));
2115 /* We must pay attention to the endianness. */
2116 sh64_register_convert_to_virtual (reg_nr,
2117 gdbarch_register_type (gdbarch,
2119 temp_buffer, buffer);
2123 else if (reg_nr >= FPP0_REGNUM
2124 && reg_nr <= FPP_LAST_REGNUM)
2126 base_regnum = fpp_reg_base_num (reg_nr);
2128 /* Build the value in the provided buffer. */
2129 /* FPP regs are pairs of single precision registers obtained by
2130 concatenating 2 single precision floating point registers. */
2131 for (portion = 0; portion < 2; portion++)
2132 regcache_raw_read (regcache, base_regnum + portion,
2134 + register_size (gdbarch, base_regnum) * portion));
2137 else if (reg_nr >= FV0_REGNUM
2138 && reg_nr <= FV_LAST_REGNUM)
2140 base_regnum = fv_reg_base_num (reg_nr);
2142 /* Build the value in the provided buffer. */
2143 /* FV regs are vectors of single precision registers obtained by
2144 concatenating 4 single precision floating point registers. */
2145 for (portion = 0; portion < 4; portion++)
2146 regcache_raw_read (regcache, base_regnum + portion,
2148 + register_size (gdbarch, base_regnum) * portion));
2151 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
2152 else if (reg_nr >= R0_C_REGNUM
2153 && reg_nr <= T_C_REGNUM)
2155 base_regnum = sh64_compact_reg_base_num (reg_nr);
2157 /* Build the value in the provided buffer. */
2158 regcache_raw_read (regcache, base_regnum, temp_buffer);
2159 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2161 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
2164 else if (reg_nr >= FP0_C_REGNUM
2165 && reg_nr <= FP_LAST_C_REGNUM)
2167 base_regnum = sh64_compact_reg_base_num (reg_nr);
2169 /* Build the value in the provided buffer. */
2170 /* Floating point registers map 1-1 to the media fp regs,
2171 they have the same size and endianness. */
2172 regcache_raw_read (regcache, base_regnum, buffer);
2175 else if (reg_nr >= DR0_C_REGNUM
2176 && reg_nr <= DR_LAST_C_REGNUM)
2178 base_regnum = sh64_compact_reg_base_num (reg_nr);
2180 /* DR_C regs are double precision registers obtained by
2181 concatenating 2 single precision floating point registers. */
2182 for (portion = 0; portion < 2; portion++)
2183 regcache_raw_read (regcache, base_regnum + portion,
2185 + register_size (gdbarch, base_regnum) * portion));
2187 /* We must pay attention to the endianness. */
2188 sh64_register_convert_to_virtual (reg_nr,
2189 gdbarch_register_type (gdbarch,
2191 temp_buffer, buffer);
2194 else if (reg_nr >= FV0_C_REGNUM
2195 && reg_nr <= FV_LAST_C_REGNUM)
2197 base_regnum = sh64_compact_reg_base_num (reg_nr);
2199 /* Build the value in the provided buffer. */
2200 /* FV_C regs are vectors of single precision registers obtained by
2201 concatenating 4 single precision floating point registers. */
2202 for (portion = 0; portion < 4; portion++)
2203 regcache_raw_read (regcache, base_regnum + portion,
2205 + register_size (gdbarch, base_regnum) * portion));
2208 else if (reg_nr == FPSCR_C_REGNUM)
2210 int fpscr_base_regnum;
2212 unsigned int fpscr_value;
2213 unsigned int sr_value;
2214 unsigned int fpscr_c_value;
2215 unsigned int fpscr_c_part1_value;
2216 unsigned int fpscr_c_part2_value;
2218 fpscr_base_regnum = FPSCR_REGNUM;
2219 sr_base_regnum = SR_REGNUM;
2221 /* Build the value in the provided buffer. */
2222 /* FPSCR_C is a very weird register that contains sparse bits
2223 from the FPSCR and the SR architectural registers.
2230 2-17 Bit 2-18 of FPSCR
2231 18-20 Bits 12,13,14 of SR
2235 /* Get FPSCR into a local buffer */
2236 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2237 /* Get value as an int. */
2238 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2239 /* Get SR into a local buffer */
2240 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2241 /* Get value as an int. */
2242 sr_value = extract_unsigned_integer (temp_buffer, 4);
2243 /* Build the new value. */
2244 fpscr_c_part1_value = fpscr_value & 0x3fffd;
2245 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
2246 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
2247 /* Store that in out buffer!!! */
2248 store_unsigned_integer (buffer, 4, fpscr_c_value);
2249 /* FIXME There is surely an endianness gotcha here. */
2252 else if (reg_nr == FPUL_C_REGNUM)
2254 base_regnum = sh64_compact_reg_base_num (reg_nr);
2256 /* FPUL_C register is floating point register 32,
2257 same size, same endianness. */
2258 regcache_raw_read (regcache, base_regnum, buffer);
2263 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2264 int reg_nr, const void *buffer)
2266 int base_regnum, portion;
2268 char temp_buffer[MAX_REGISTER_SIZE];
2270 if (reg_nr >= DR0_REGNUM
2271 && reg_nr <= DR_LAST_REGNUM)
2273 base_regnum = dr_reg_base_num (reg_nr);
2274 /* We must pay attention to the endianness. */
2275 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
2277 buffer, temp_buffer);
2279 /* Write the real regs for which this one is an alias. */
2280 for (portion = 0; portion < 2; portion++)
2281 regcache_raw_write (regcache, base_regnum + portion,
2283 + register_size (gdbarch,
2284 base_regnum) * portion));
2287 else if (reg_nr >= FPP0_REGNUM
2288 && reg_nr <= FPP_LAST_REGNUM)
2290 base_regnum = fpp_reg_base_num (reg_nr);
2292 /* Write the real regs for which this one is an alias. */
2293 for (portion = 0; portion < 2; portion++)
2294 regcache_raw_write (regcache, base_regnum + portion,
2296 + register_size (gdbarch,
2297 base_regnum) * portion));
2300 else if (reg_nr >= FV0_REGNUM
2301 && reg_nr <= FV_LAST_REGNUM)
2303 base_regnum = fv_reg_base_num (reg_nr);
2305 /* Write the real regs for which this one is an alias. */
2306 for (portion = 0; portion < 4; portion++)
2307 regcache_raw_write (regcache, base_regnum + portion,
2309 + register_size (gdbarch,
2310 base_regnum) * portion));
2313 /* sh compact general pseudo registers. 1-to-1 with a shmedia
2314 register but only 4 bytes of it. */
2315 else if (reg_nr >= R0_C_REGNUM
2316 && reg_nr <= T_C_REGNUM)
2318 base_regnum = sh64_compact_reg_base_num (reg_nr);
2319 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
2320 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2324 /* Let's read the value of the base register into a temporary
2325 buffer, so that overwriting the last four bytes with the new
2326 value of the pseudo will leave the upper 4 bytes unchanged. */
2327 regcache_raw_read (regcache, base_regnum, temp_buffer);
2328 /* Write as an 8 byte quantity */
2329 memcpy (temp_buffer + offset, buffer, 4);
2330 regcache_raw_write (regcache, base_regnum, temp_buffer);
2333 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
2334 registers. Both are 4 bytes. */
2335 else if (reg_nr >= FP0_C_REGNUM
2336 && reg_nr <= FP_LAST_C_REGNUM)
2338 base_regnum = sh64_compact_reg_base_num (reg_nr);
2339 regcache_raw_write (regcache, base_regnum, buffer);
2342 else if (reg_nr >= DR0_C_REGNUM
2343 && reg_nr <= DR_LAST_C_REGNUM)
2345 base_regnum = sh64_compact_reg_base_num (reg_nr);
2346 for (portion = 0; portion < 2; portion++)
2348 /* We must pay attention to the endianness. */
2349 sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
2352 buffer, temp_buffer);
2354 regcache_raw_write (regcache, base_regnum + portion,
2356 + register_size (gdbarch,
2357 base_regnum) * portion));
2361 else if (reg_nr >= FV0_C_REGNUM
2362 && reg_nr <= FV_LAST_C_REGNUM)
2364 base_regnum = sh64_compact_reg_base_num (reg_nr);
2366 for (portion = 0; portion < 4; portion++)
2368 regcache_raw_write (regcache, base_regnum + portion,
2370 + register_size (gdbarch,
2371 base_regnum) * portion));
2375 else if (reg_nr == FPSCR_C_REGNUM)
2377 int fpscr_base_regnum;
2379 unsigned int fpscr_value;
2380 unsigned int sr_value;
2381 unsigned int old_fpscr_value;
2382 unsigned int old_sr_value;
2383 unsigned int fpscr_c_value;
2384 unsigned int fpscr_mask;
2385 unsigned int sr_mask;
2387 fpscr_base_regnum = FPSCR_REGNUM;
2388 sr_base_regnum = SR_REGNUM;
2390 /* FPSCR_C is a very weird register that contains sparse bits
2391 from the FPSCR and the SR architectural registers.
2398 2-17 Bit 2-18 of FPSCR
2399 18-20 Bits 12,13,14 of SR
2403 /* Get value as an int. */
2404 fpscr_c_value = extract_unsigned_integer (buffer, 4);
2406 /* Build the new values. */
2407 fpscr_mask = 0x0003fffd;
2408 sr_mask = 0x001c0000;
2410 fpscr_value = fpscr_c_value & fpscr_mask;
2411 sr_value = (fpscr_value & sr_mask) >> 6;
2413 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2414 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2415 old_fpscr_value &= 0xfffc0002;
2416 fpscr_value |= old_fpscr_value;
2417 store_unsigned_integer (temp_buffer, 4, fpscr_value);
2418 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
2420 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2421 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
2422 old_sr_value &= 0xffff8fff;
2423 sr_value |= old_sr_value;
2424 store_unsigned_integer (temp_buffer, 4, sr_value);
2425 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
2428 else if (reg_nr == FPUL_C_REGNUM)
2430 base_regnum = sh64_compact_reg_base_num (reg_nr);
2431 regcache_raw_write (regcache, base_regnum, buffer);
2435 /* Floating point vector of 4 float registers. */
2437 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2440 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
2441 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2442 fv_regnum - FV0_REGNUM,
2443 (int) read_register (first_fp_reg_num),
2444 (int) read_register (first_fp_reg_num + 1),
2445 (int) read_register (first_fp_reg_num + 2),
2446 (int) read_register (first_fp_reg_num + 3));
2449 /* Floating point vector of 4 float registers, compact mode. */
2451 do_fv_c_register_info (int fv_regnum)
2453 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
2454 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2455 fv_regnum - FV0_C_REGNUM,
2456 (int) read_register (first_fp_reg_num),
2457 (int) read_register (first_fp_reg_num + 1),
2458 (int) read_register (first_fp_reg_num + 2),
2459 (int) read_register (first_fp_reg_num + 3));
2462 /* Pairs of single regs. The DR are instead double precision
2465 do_fpp_register_info (int fpp_regnum)
2467 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
2469 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
2470 fpp_regnum - FPP0_REGNUM,
2471 (int) read_register (first_fp_reg_num),
2472 (int) read_register (first_fp_reg_num + 1));
2475 /* Double precision registers. */
2477 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2480 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
2482 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
2483 dr_regnum - DR0_REGNUM,
2484 (int) read_register (first_fp_reg_num),
2485 (int) read_register (first_fp_reg_num + 1));
2488 /* Double precision registers, compact mode. */
2490 do_dr_c_register_info (int dr_regnum)
2492 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
2494 printf_filtered ("dr%d_c\t0x%08x%08x\n",
2495 dr_regnum - DR0_C_REGNUM,
2496 (int) read_register (first_fp_reg_num),
2497 (int) read_register (first_fp_reg_num +1));
2500 /* General register in compact mode. */
2502 do_r_c_register_info (int r_c_regnum)
2504 int regnum = sh64_compact_reg_base_num (r_c_regnum);
2506 printf_filtered ("r%d_c\t0x%08x\n",
2507 r_c_regnum - R0_C_REGNUM,
2508 /*FIXME!!!*/ (int) read_register (regnum));
2511 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
2512 shmedia REGISTERS. */
2513 /* Control registers, compact mode. */
2515 do_cr_c_register_info (int cr_c_regnum)
2517 switch (cr_c_regnum)
2519 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2521 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2523 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2525 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2527 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2529 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2531 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2533 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
2539 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2540 { /* do values for FP (float) regs */
2542 double flt; /* double extracted from raw hex data */
2546 /* Allocate space for the float. */
2547 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
2549 /* Get the data in raw format. */
2550 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2551 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2553 /* Get the register as a number */
2554 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
2556 /* Print the name and some spaces. */
2557 fputs_filtered (REGISTER_NAME (regnum), file);
2558 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2560 /* Print the value. */
2562 fprintf_filtered (file, "<invalid float>");
2564 fprintf_filtered (file, "%-10.9g", flt);
2566 /* Print the fp register as hex. */
2567 fprintf_filtered (file, "\t(raw 0x");
2568 for (j = 0; j < register_size (gdbarch, regnum); j++)
2570 int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
2571 : register_size (gdbarch, regnum) - 1 - j;
2572 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
2574 fprintf_filtered (file, ")");
2575 fprintf_filtered (file, "\n");
2579 sh64_do_pseudo_register (int regnum)
2581 /* All the sh64-compact mode registers are pseudo registers. */
2583 if (regnum < NUM_REGS
2584 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
2585 internal_error (__FILE__, __LINE__,
2586 "Invalid pseudo register number %d\n", regnum);
2588 else if ((regnum >= DR0_REGNUM
2589 && regnum <= DR_LAST_REGNUM))
2590 do_dr_register_info (current_gdbarch, gdb_stdout, regnum);
2592 else if ((regnum >= DR0_C_REGNUM
2593 && regnum <= DR_LAST_C_REGNUM))
2594 do_dr_c_register_info (regnum);
2596 else if ((regnum >= FV0_REGNUM
2597 && regnum <= FV_LAST_REGNUM))
2598 do_fv_register_info (current_gdbarch, gdb_stdout, regnum);
2600 else if ((regnum >= FV0_C_REGNUM
2601 && regnum <= FV_LAST_C_REGNUM))
2602 do_fv_c_register_info (regnum);
2604 else if (regnum >= FPP0_REGNUM
2605 && regnum <= FPP_LAST_REGNUM)
2606 do_fpp_register_info (regnum);
2608 else if (regnum >= R0_C_REGNUM
2609 && regnum <= R_LAST_C_REGNUM)
2610 /* FIXME, this function will not print the right format. */
2611 do_r_c_register_info (regnum);
2612 else if (regnum >= FP0_C_REGNUM
2613 && regnum <= FP_LAST_C_REGNUM)
2614 /* This should work also for pseudoregs. */
2615 sh_do_fp_register (current_gdbarch, gdb_stdout, regnum);
2616 else if (regnum >= PC_C_REGNUM
2617 && regnum <= FPUL_C_REGNUM)
2618 do_cr_c_register_info (regnum);
2622 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2624 char raw_buffer[MAX_REGISTER_SIZE];
2626 fputs_filtered (REGISTER_NAME (regnum), file);
2627 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2629 /* Get the data in raw format. */
2630 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2631 fprintf_filtered (file, "*value not available*\n");
2633 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2634 file, 'x', 1, 0, Val_pretty_default);
2635 fprintf_filtered (file, "\t");
2636 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2637 file, 0, 1, 0, Val_pretty_default);
2638 fprintf_filtered (file, "\n");
2642 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2644 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2645 internal_error (__FILE__, __LINE__,
2646 "Invalid register number %d\n", regnum);
2648 else if (regnum >= 0 && regnum < NUM_REGS)
2650 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2651 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2653 sh_do_register (gdbarch, file, regnum); /* All other regs */
2656 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2657 sh64_do_pseudo_register (regnum);
2661 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2662 struct frame_info *frame, int regnum, int fpregs)
2664 if (regnum != -1) /* do one specified register */
2666 if (*(REGISTER_NAME (regnum)) == '\0')
2667 error ("Not a valid register for the current processor type");
2669 sh_print_register (gdbarch, file, regnum);
2672 /* do all (or most) registers */
2675 while (regnum < NUM_REGS)
2677 /* If the register name is empty, it is undefined for this
2678 processor, so don't display anything. */
2679 if (REGISTER_NAME (regnum) == NULL
2680 || *(REGISTER_NAME (regnum)) == '\0')
2686 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2690 /* true for "INFO ALL-REGISTERS" command */
2691 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2695 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2699 sh_do_register (gdbarch, file, regnum); /* All other regs */
2705 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2707 sh64_do_pseudo_register (regnum);
2714 sh_compact_do_registers_info (int regnum, int fpregs)
2716 if (regnum != -1) /* do one specified register */
2718 if (*(REGISTER_NAME (regnum)) == '\0')
2719 error ("Not a valid register for the current processor type");
2721 if (regnum >= 0 && regnum < R0_C_REGNUM)
2722 error ("Not a valid register for the current processor mode.");
2724 sh_print_register (current_gdbarch, gdb_stdout, regnum);
2727 /* do all compact registers */
2729 regnum = R0_C_REGNUM;
2730 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2732 sh64_do_pseudo_register (regnum);
2739 sh64_do_registers_info (int regnum, int fpregs)
2741 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
2742 sh_print_registers_info (current_gdbarch, gdb_stdout,
2743 deprecated_selected_frame, regnum, fpregs);
2745 sh_compact_do_registers_info (regnum, fpregs);
2748 #ifdef SVR4_SHARED_LIBS
2750 /* Fetch (and possibly build) an appropriate link_map_offsets structure
2751 for native i386 linux targets using the struct offsets defined in
2752 link.h (but without actual reference to that file).
2754 This makes it possible to access i386-linux shared libraries from
2755 a gdb that was not built on an i386-linux host (for cross debugging).
2758 struct link_map_offsets *
2759 sh_linux_svr4_fetch_link_map_offsets (void)
2761 static struct link_map_offsets lmo;
2762 static struct link_map_offsets *lmp = 0;
2768 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2770 lmo.r_map_offset = 4;
2773 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2775 lmo.l_addr_offset = 0;
2776 lmo.l_addr_size = 4;
2778 lmo.l_name_offset = 4;
2779 lmo.l_name_size = 4;
2781 lmo.l_next_offset = 12;
2782 lmo.l_next_size = 4;
2784 lmo.l_prev_offset = 16;
2785 lmo.l_prev_size = 4;
2790 #endif /* SVR4_SHARED_LIBS */
2792 gdbarch_init_ftype sh64_gdbarch_init;
2795 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2797 static LONGEST sh64_call_dummy_words[] = {0};
2798 struct gdbarch *gdbarch;
2799 struct gdbarch_tdep *tdep;
2801 /* If there is already a candidate, use it. */
2802 arches = gdbarch_list_lookup_by_info (arches, &info);
2804 return arches->gdbarch;
2806 /* None found, create a new architecture from the information
2808 tdep = XMALLOC (struct gdbarch_tdep);
2809 gdbarch = gdbarch_alloc (&info, tdep);
2811 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2812 ready to unwind the PC first (see frame.c:get_prev_frame()). */
2813 set_gdbarch_deprecated_init_frame_pc (gdbarch, deprecated_init_frame_pc_default);
2815 /* Determine the ABI */
2816 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2818 /* If the ABI is the 64-bit one, it can only be sh-media. */
2819 tdep->sh_abi = SH_ABI_64;
2820 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2821 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2825 /* If the ABI is the 32-bit one it could be either media or
2827 tdep->sh_abi = SH_ABI_32;
2828 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2829 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2832 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2833 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2834 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2835 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2836 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2837 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2839 set_gdbarch_sp_regnum (gdbarch, 15);
2840 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
2842 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2843 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2845 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2847 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2848 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2850 set_gdbarch_frame_args_skip (gdbarch, 0);
2851 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2852 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2854 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2855 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2856 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2858 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
2859 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2860 set_gdbarch_pc_regnum (gdbarch, 64);
2862 /* The number of real registers is the same whether we are in
2863 ISA16(compact) or ISA32(media). */
2864 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2865 set_gdbarch_deprecated_register_bytes (gdbarch,
2866 ((SIM_SH64_NR_FP_REGS + 1) * 4)
2867 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
2869 set_gdbarch_register_name (gdbarch, sh64_register_name);
2870 set_gdbarch_register_type (gdbarch, sh64_register_type);
2871 set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value);
2872 set_gdbarch_deprecated_register_byte (gdbarch, sh64_register_byte);
2873 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2874 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2876 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
2877 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
2878 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
2879 set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words);
2880 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words));
2882 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
2883 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
2884 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
2885 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
2886 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
2887 set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address);
2888 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
2889 set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);
2890 set_gdbarch_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
2891 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
2892 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
2893 set_gdbarch_elf_make_msymbol_special (gdbarch,
2894 sh64_elf_make_msymbol_special);
2896 /* Hook in ABI-specific overrides, if they have been registered. */
2897 gdbarch_init_osabi (info, gdbarch);