1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2005, 2007-2012 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "gdb_string.h"
36 #include "gdb_assert.h"
37 #include "arch-utils.h"
46 /* Register numbers shared with the simulator. */
47 #include "gdb/sim-sh.h"
49 #include "sh64-tdep.h"
51 /* Information that is dependent on the processor variant. */
64 struct sh64_frame_cache
71 /* Flag showing that a frame has been created in the prologue code. */
76 /* Saved registers. */
77 CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
81 /* Registers of SH5 */
85 DEFAULT_RETURN_REGNUM = 2,
86 STRUCT_RETURN_REGNUM = 2,
89 FLOAT_ARGLAST_REGNUM = 11,
95 /* FPP stands for Floating Point Pair, to avoid confusion with
96 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
97 point register. Unfortunately on the sh5, the floating point
98 registers are called FR, and the floating point pairs are called FP. */
100 FPP_LAST_REGNUM = 204,
102 FV_LAST_REGNUM = 220,
104 R_LAST_C_REGNUM = 236,
111 FPSCR_C_REGNUM = 243,
114 FP_LAST_C_REGNUM = 260,
116 DR_LAST_C_REGNUM = 268,
118 FV_LAST_C_REGNUM = 272,
119 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
120 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
121 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
122 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
123 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
127 sh64_register_name (struct gdbarch *gdbarch, int reg_nr)
129 static char *register_names[] =
131 /* SH MEDIA MODE (ISA 32) */
132 /* general registers (64-bit) 0-63 */
133 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
134 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
135 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
136 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
137 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
138 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
139 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
140 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
145 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
148 /* target registers (64-bit) 68-75 */
149 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
151 /* floating point state control register (32-bit) 76 */
154 /* single precision floating point registers (32-bit) 77-140 */
155 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
156 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
157 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
158 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
159 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
160 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
161 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
162 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
164 /* double precision registers (pseudo) 141-172 */
165 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
166 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
167 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
168 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
170 /* floating point pairs (pseudo) 173-204 */
171 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
172 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
173 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
174 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
176 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
177 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
178 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
180 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
181 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
182 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
184 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
186 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
187 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
188 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
189 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
190 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
191 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
192 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
193 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return register_names[reg_nr];
203 #define NUM_PSEUDO_REGS_SH_MEDIA 80
204 #define NUM_PSEUDO_REGS_SH_COMPACT 51
206 /* Macros and functions for setting and testing a bit in a minimal
207 symbol that marks it as 32-bit function. The MSB of the minimal
208 symbol's "info" field is used for this purpose.
210 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
211 i.e. refers to a 32-bit function, and sets a "special" bit in a
212 minimal symbol to mark it as a 32-bit function
213 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
215 #define MSYMBOL_IS_SPECIAL(msym) \
216 MSYMBOL_TARGET_FLAG_1 (msym)
219 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
224 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
226 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
227 SYMBOL_VALUE_ADDRESS (msym) |= 1;
231 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
232 are some macros to test, set, or clear bit 0 of addresses. */
233 #define IS_ISA32_ADDR(addr) ((addr) & 1)
234 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
235 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
238 pc_is_isa32 (bfd_vma memaddr)
240 struct minimal_symbol *sym;
242 /* If bit 0 of the address is set, assume this is a
243 ISA32 (shmedia) address. */
244 if (IS_ISA32_ADDR (memaddr))
247 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
248 the high bit of the info field. Use this to decide if the function is
250 sym = lookup_minimal_symbol_by_pc (memaddr);
252 return MSYMBOL_IS_SPECIAL (sym);
257 static const unsigned char *
258 sh64_breakpoint_from_pc (struct gdbarch *gdbarch,
259 CORE_ADDR *pcptr, int *lenptr)
261 /* The BRK instruction for shmedia is
262 01101111 11110101 11111111 11110000
263 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
264 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
266 /* The BRK instruction for shcompact is
268 which translates in big endian mode to 0x0, 0x3b
269 and in little endian mode to 0x3b, 0x0 */
271 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
273 if (pc_is_isa32 (*pcptr))
275 static unsigned char big_breakpoint_media[] = {
276 0x6f, 0xf5, 0xff, 0xf0
278 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
279 *lenptr = sizeof (big_breakpoint_media);
280 return big_breakpoint_media;
284 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
285 *lenptr = sizeof (big_breakpoint_compact);
286 return big_breakpoint_compact;
291 if (pc_is_isa32 (*pcptr))
293 static unsigned char little_breakpoint_media[] = {
294 0xf0, 0xff, 0xf5, 0x6f
296 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
297 *lenptr = sizeof (little_breakpoint_media);
298 return little_breakpoint_media;
302 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
303 *lenptr = sizeof (little_breakpoint_compact);
304 return little_breakpoint_compact;
309 /* Prologue looks like
310 [mov.l <regs>,@-r15]...
315 Actually it can be more complicated than this. For instance, with
333 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
334 with l=1 and n = 18 0110101111110001010010100aaa0000 */
335 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
337 /* STS.L PR,@-r0 0100000000100010
338 r0-4-->r0, PR-->(r0) */
339 #define IS_STS_R0(x) ((x) == 0x4022)
341 /* STS PR, Rm 0000mmmm00101010
343 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
345 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
347 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
349 /* MOV.L R14,@(disp,r15) 000111111110dddd
350 R14-->(dispx4+r15) */
351 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
353 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
354 R18-->(dispx8+R14) */
355 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
357 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
358 R18-->(dispx8+R15) */
359 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
361 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
362 R18-->(dispx4+R15) */
363 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
365 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
366 R14-->(dispx8+R15) */
367 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
369 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
370 R14-->(dispx4+R15) */
371 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
373 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
375 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
377 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
379 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
381 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
383 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
385 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
387 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
389 #define IS_MOV_SP_FP_MEDIA(x) \
390 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
392 /* MOV #imm, R0 1110 0000 ssss ssss
394 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
396 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
397 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
399 /* ADD r15,r0 0011 0000 1111 1100
401 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
403 /* MOV.L R14 @-R0 0010 0000 1110 0110
404 R14-->(R0-4), R0-4-->R0 */
405 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
407 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
408 where Rm is one of r2-r9 which are the argument registers. */
409 /* FIXME: Recognize the float and double register moves too! */
410 #define IS_MEDIA_IND_ARG_MOV(x) \
411 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
412 && (((x) & 0x03f00000) >= 0x00200000 \
413 && ((x) & 0x03f00000) <= 0x00900000))
415 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
416 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
417 where Rm is one of r2-r9 which are the argument registers. */
418 #define IS_MEDIA_ARG_MOV(x) \
419 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
420 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
422 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
423 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
424 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
425 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
426 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
427 #define IS_MEDIA_MOV_TO_R14(x) \
428 ((((x) & 0xfffffc0f) == 0xa0e00000) \
429 || (((x) & 0xfffffc0f) == 0xa4e00000) \
430 || (((x) & 0xfffffc0f) == 0xa8e00000) \
431 || (((x) & 0xfffffc0f) == 0xb4e00000) \
432 || (((x) & 0xfffffc0f) == 0xbce00000))
434 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
436 #define IS_COMPACT_IND_ARG_MOV(x) \
437 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
438 && (((x) & 0x00f0) <= 0x0090))
440 /* compact direct arg move!
441 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
442 #define IS_COMPACT_ARG_MOV(x) \
443 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
444 && ((x) & 0x00f0) <= 0x0090))
446 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
447 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
448 #define IS_COMPACT_MOV_TO_R14(x) \
449 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
451 #define IS_JSR_R0(x) ((x) == 0x400b)
452 #define IS_NOP(x) ((x) == 0x0009)
455 /* MOV r15,r14 0110111011110011
457 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
459 /* ADD #imm,r15 01111111iiiiiiii
461 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
463 /* Skip any prologue before the guts of a function. */
465 /* Skip the prologue using the debug information. If this fails we'll
466 fall back on the 'guess' method below. */
468 after_prologue (CORE_ADDR pc)
470 struct symtab_and_line sal;
471 CORE_ADDR func_addr, func_end;
473 /* If we can not find the symbol in the partial symbol table, then
474 there is no hope we can determine the function's start address
476 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
480 /* Get the line associated with FUNC_ADDR. */
481 sal = find_pc_line (func_addr, 0);
483 /* There are only two cases to consider. First, the end of the source line
484 is within the function bounds. In that case we return the end of the
485 source line. Second is the end of the source line extends beyond the
486 bounds of the current function. We need to use the slow code to
487 examine instructions in that case. */
488 if (sal.end < func_end)
495 look_for_args_moves (struct gdbarch *gdbarch,
496 CORE_ADDR start_pc, int media_mode)
498 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
501 int insn_size = (media_mode ? 4 : 2);
503 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
507 w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
508 insn_size, byte_order);
510 if (IS_MEDIA_IND_ARG_MOV (w))
512 /* This must be followed by a store to r14, so the argument
513 is where the debug info says it is. This can happen after
514 the SP has been saved, unfortunately. */
516 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
517 insn_size, byte_order);
519 if (IS_MEDIA_MOV_TO_R14 (next_insn))
522 else if (IS_MEDIA_ARG_MOV (w))
524 /* These instructions store directly the argument in r14. */
532 w = read_memory_integer (here, insn_size, byte_order);
535 if (IS_COMPACT_IND_ARG_MOV (w))
537 /* This must be followed by a store to r14, so the argument
538 is where the debug info says it is. This can happen after
539 the SP has been saved, unfortunately. */
541 int next_insn = 0xffff & read_memory_integer (here, insn_size,
544 if (IS_COMPACT_MOV_TO_R14 (next_insn))
547 else if (IS_COMPACT_ARG_MOV (w))
549 /* These instructions store directly the argument in r14. */
552 else if (IS_MOVL_R0 (w))
554 /* There is a function that gcc calls to get the arguments
555 passed correctly to the function. Only after this
556 function call the arguments will be found at the place
557 where they are supposed to be. This happens in case the
558 argument has to be stored into a 64-bit register (for
559 instance doubles, long longs). SHcompact doesn't have
560 access to the full 64-bits, so we store the register in
561 stack slot and store the address of the stack slot in
562 the register, then do a call through a wrapper that
563 loads the memory value into the register. A SHcompact
564 callee calls an argument decoder
565 (GCC_shcompact_incoming_args) that stores the 64-bit
566 value in a stack slot and stores the address of the
567 stack slot in the register. GCC thinks the argument is
568 just passed by transparent reference, but this is only
569 true after the argument decoder is called. Such a call
570 needs to be considered part of the prologue. */
572 /* This must be followed by a JSR @r0 instruction and by
573 a NOP instruction. After these, the prologue is over! */
575 int next_insn = 0xffff & read_memory_integer (here, insn_size,
578 if (IS_JSR_R0 (next_insn))
580 next_insn = 0xffff & read_memory_integer (here, insn_size,
584 if (IS_NOP (next_insn))
597 sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc)
599 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
608 if (pc_is_isa32 (start_pc) == 0)
614 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
619 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
620 insn_size, byte_order);
622 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
623 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
624 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w)
625 || IS_PTABSL_R18 (w))
629 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
637 /* Don't bail out yet, we may have arguments stored in
638 registers here, according to the debug info, so that
639 gdb can print the frames correctly. */
640 start_pc = look_for_args_moves (gdbarch,
641 here - insn_size, media_mode);
647 int w = 0xffff & read_memory_integer (here, insn_size, byte_order);
650 if (IS_STS_R0 (w) || IS_STS_PR (w)
651 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
652 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
656 else if (IS_MOV_SP_FP (w))
664 /* Don't bail out yet, we may have arguments stored in
665 registers here, according to the debug info, so that
666 gdb can print the frames correctly. */
667 start_pc = look_for_args_moves (gdbarch,
668 here - insn_size, media_mode);
678 sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
680 CORE_ADDR post_prologue_pc;
682 /* See if we can determine the end of the prologue via the symbol table.
683 If so, then return either PC, or the PC after the prologue, whichever
685 post_prologue_pc = after_prologue (pc);
687 /* If after_prologue returned a useful address, then use it. Else
688 fall back on the instruction skipping code. */
689 if (post_prologue_pc != 0)
690 return max (pc, post_prologue_pc);
692 return sh64_skip_prologue_hard_way (gdbarch, pc);
695 /* Should call_function allocate stack space for a struct return? */
697 sh64_use_struct_convention (struct type *type)
699 return (TYPE_LENGTH (type) > 8);
702 /* For vectors of 4 floating point registers. */
704 sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
708 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4;
712 /* For double precision floating point registers, i.e 2 fp regs. */
714 sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
718 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2;
722 /* For pairs of floating point registers. */
724 sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum)
728 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2;
734 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
735 GDB_REGNUM BASE_REGNUM
795 sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr)
797 int base_regnum = reg_nr;
799 /* general register N maps to general register N */
800 if (reg_nr >= R0_C_REGNUM
801 && reg_nr <= R_LAST_C_REGNUM)
802 base_regnum = reg_nr - R0_C_REGNUM;
804 /* floating point register N maps to floating point register N */
805 else if (reg_nr >= FP0_C_REGNUM
806 && reg_nr <= FP_LAST_C_REGNUM)
807 base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch);
809 /* double prec register N maps to base regnum for double prec register N */
810 else if (reg_nr >= DR0_C_REGNUM
811 && reg_nr <= DR_LAST_C_REGNUM)
812 base_regnum = sh64_dr_reg_base_num (gdbarch,
813 DR0_REGNUM + reg_nr - DR0_C_REGNUM);
815 /* vector N maps to base regnum for vector register N */
816 else if (reg_nr >= FV0_C_REGNUM
817 && reg_nr <= FV_LAST_C_REGNUM)
818 base_regnum = sh64_fv_reg_base_num (gdbarch,
819 FV0_REGNUM + reg_nr - FV0_C_REGNUM);
821 else if (reg_nr == PC_C_REGNUM)
822 base_regnum = gdbarch_pc_regnum (gdbarch);
824 else if (reg_nr == GBR_C_REGNUM)
827 else if (reg_nr == MACH_C_REGNUM
828 || reg_nr == MACL_C_REGNUM)
831 else if (reg_nr == PR_C_REGNUM)
832 base_regnum = PR_REGNUM;
834 else if (reg_nr == T_C_REGNUM)
837 else if (reg_nr == FPSCR_C_REGNUM)
838 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
840 else if (reg_nr == FPUL_C_REGNUM)
841 base_regnum = gdbarch_fp0_regnum (gdbarch) + 32;
847 sign_extend (int value, int bits)
849 value = value & ((1 << bits) - 1);
850 return (value & (1 << (bits - 1))
851 ? value | (~((1 << bits) - 1))
856 sh64_analyze_prologue (struct gdbarch *gdbarch,
857 struct sh64_frame_cache *cache,
859 CORE_ADDR current_pc)
867 int gdb_register_number;
869 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
870 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
872 cache->sp_offset = 0;
874 /* Loop around examining the prologue insns until we find something
875 that does not appear to be part of the prologue. But give up
876 after 20 of them, since we're getting silly then. */
880 if (cache->media_mode)
885 opc = pc + (insn_size * 28);
886 if (opc > current_pc)
888 for ( ; pc <= opc; pc += insn_size)
890 insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
892 insn_size, byte_order);
894 if (!cache->media_mode)
896 if (IS_STS_PR (insn))
898 int next_insn = read_memory_integer (pc + insn_size,
899 insn_size, byte_order);
900 if (IS_MOV_TO_R15 (next_insn))
902 cache->saved_regs[PR_REGNUM]
903 = cache->sp_offset - ((((next_insn & 0xf) ^ 0x8)
909 else if (IS_MOV_R14 (insn))
910 cache->saved_regs[MEDIA_FP_REGNUM] =
911 cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
913 else if (IS_MOV_R0 (insn))
915 /* Put in R0 the offset from SP at which to store some
916 registers. We are interested in this value, because it
917 will tell us where the given registers are stored within
919 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
922 else if (IS_ADD_SP_R0 (insn))
924 /* This instruction still prepares r0, but we don't care.
925 We already have the offset in r0_val. */
928 else if (IS_STS_R0 (insn))
930 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
931 cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
935 else if (IS_MOV_R14_R0 (insn))
937 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
938 cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
943 else if (IS_ADD_SP (insn))
944 cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
946 else if (IS_MOV_SP_FP (insn))
951 if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
953 sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
955 else if (IS_STQ_R18_R15 (insn))
956 cache->saved_regs[PR_REGNUM]
957 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
960 else if (IS_STL_R18_R15 (insn))
961 cache->saved_regs[PR_REGNUM]
962 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
965 else if (IS_STQ_R14_R15 (insn))
966 cache->saved_regs[MEDIA_FP_REGNUM]
967 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
970 else if (IS_STL_R14_R15 (insn))
971 cache->saved_regs[MEDIA_FP_REGNUM]
972 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
975 else if (IS_MOV_SP_FP_MEDIA (insn))
980 if (cache->saved_regs[MEDIA_FP_REGNUM] >= 0)
985 sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
990 /* Function: push_dummy_call
991 Setup the function arguments for calling a function in the inferior.
993 On the Renesas SH architecture, there are four registers (R4 to R7)
994 which are dedicated for passing function arguments. Up to the first
995 four arguments (depending on size) may go into these registers.
996 The rest go on the stack.
998 Arguments that are smaller than 4 bytes will still take up a whole
999 register or a whole 32-bit word on the stack, and will be
1000 right-justified in the register or the stack word. This includes
1001 chars, shorts, and small aggregate types.
1003 Arguments that are larger than 4 bytes may be split between two or
1004 more registers. If there are not enough registers free, an argument
1005 may be passed partly in a register (or registers), and partly on the
1006 stack. This includes doubles, long longs, and larger aggregates.
1007 As far as I know, there is no upper limit to the size of aggregates
1008 that will be passed in this way; in other words, the convention of
1009 passing a pointer to a large aggregate instead of a copy is not used.
1011 An exceptional case exists for struct arguments (and possibly other
1012 aggregates such as arrays) if the size is larger than 4 bytes but
1013 not a multiple of 4 bytes. In this case the argument is never split
1014 between the registers and the stack, but instead is copied in its
1015 entirety onto the stack, AND also copied into as many registers as
1016 there is room for. In other words, space in registers permitting,
1017 two copies of the same argument are passed in. As far as I can tell,
1018 only the one on the stack is used, although that may be a function
1019 of the level of compiler optimization. I suspect this is a compiler
1020 bug. Arguments of these odd sizes are left-justified within the
1021 word (as opposed to arguments smaller than 4 bytes, which are
1024 If the function is to return an aggregate type such as a struct, it
1025 is either returned in the normal return value register R0 (if its
1026 size is no greater than one byte), or else the caller must allocate
1027 space into which the callee will copy the return value (if the size
1028 is greater than one byte). In this case, a pointer to the return
1029 value location is passed into the callee in register R2, which does
1030 not displace any of the other arguments passed in via registers R4
1033 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1034 non-scalar (struct, union) elements (even if the elements are
1036 FR0-FR11 for single precision floating point (float)
1037 DR0-DR10 for double precision floating point (double)
1039 If a float is argument number 3 (for instance) and arguments number
1040 1,2, and 4 are integer, the mapping will be:
1041 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1043 If a float is argument number 10 (for instance) and arguments number
1044 1 through 10 are integer, the mapping will be:
1045 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1046 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1047 arg11->stack(16,SP). I.e. there is hole in the stack.
1049 Different rules apply for variable arguments functions, and for functions
1050 for which the prototype is not known. */
1053 sh64_push_dummy_call (struct gdbarch *gdbarch,
1054 struct value *function,
1055 struct regcache *regcache,
1057 int nargs, struct value **args,
1058 CORE_ADDR sp, int struct_return,
1059 CORE_ADDR struct_addr)
1061 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1062 int stack_offset, stack_alloc;
1066 int float_arg_index = 0;
1067 int double_arg_index = 0;
1078 memset (fp_args, 0, sizeof (fp_args));
1080 /* First force sp to a 8-byte alignment. */
1081 sp = sh64_frame_align (gdbarch, sp);
1083 /* The "struct return pointer" pseudo-argument has its own dedicated
1087 regcache_cooked_write_unsigned (regcache,
1088 STRUCT_RETURN_REGNUM, struct_addr);
1090 /* Now make sure there's space on the stack. */
1091 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1092 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
1093 sp -= stack_alloc; /* Make room on stack for args. */
1095 /* Now load as many as possible of the first arguments into
1096 registers, and push the rest onto the stack. There are 64 bytes
1097 in eight registers available. Loop thru args from first to last. */
1099 int_argreg = ARG0_REGNUM;
1100 float_argreg = gdbarch_fp0_regnum (gdbarch);
1101 double_argreg = DR0_REGNUM;
1103 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1105 type = value_type (args[argnum]);
1106 len = TYPE_LENGTH (type);
1107 memset (valbuf, 0, sizeof (valbuf));
1109 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1111 argreg_size = register_size (gdbarch, int_argreg);
1113 if (len < argreg_size)
1115 /* value gets right-justified in the register or stack word. */
1116 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1117 memcpy (valbuf + argreg_size - len,
1118 (char *) value_contents (args[argnum]), len);
1120 memcpy (valbuf, (char *) value_contents (args[argnum]), len);
1125 val = (char *) value_contents (args[argnum]);
1129 if (int_argreg > ARGLAST_REGNUM)
1131 /* Must go on the stack. */
1132 write_memory (sp + stack_offset, (const bfd_byte *) val,
1134 stack_offset += 8;/*argreg_size;*/
1136 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1137 That's because some *&^%$ things get passed on the stack
1138 AND in the registers! */
1139 if (int_argreg <= ARGLAST_REGNUM)
1141 /* There's room in a register. */
1142 regval = extract_unsigned_integer (val, argreg_size,
1144 regcache_cooked_write_unsigned (regcache,
1145 int_argreg, regval);
1147 /* Store the value 8 bytes at a time. This means that
1148 things larger than 8 bytes may go partly in registers
1149 and partly on the stack. FIXME: argreg is incremented
1150 before we use its size. */
1158 val = (char *) value_contents (args[argnum]);
1161 /* Where is it going to be stored? */
1162 while (fp_args[float_arg_index])
1165 /* Now float_argreg points to the register where it
1166 should be stored. Are we still within the allowed
1168 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1170 /* Goes in FR0...FR11 */
1171 regcache_cooked_write (regcache,
1172 gdbarch_fp0_regnum (gdbarch)
1175 fp_args[float_arg_index] = 1;
1176 /* Skip the corresponding general argument register. */
1181 /* Store it as the integers, 8 bytes at the time, if
1182 necessary spilling on the stack. */
1187 /* Where is it going to be stored? */
1188 while (fp_args[double_arg_index])
1189 double_arg_index += 2;
1190 /* Now double_argreg points to the register
1191 where it should be stored.
1192 Are we still within the allowed register set? */
1193 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1195 /* Goes in DR0...DR10 */
1196 /* The numbering of the DRi registers is consecutive,
1197 i.e. includes odd numbers. */
1198 int double_register_offset = double_arg_index / 2;
1199 int regnum = DR0_REGNUM + double_register_offset;
1200 regcache_cooked_write (regcache, regnum, val);
1201 fp_args[double_arg_index] = 1;
1202 fp_args[double_arg_index + 1] = 1;
1203 /* Skip the corresponding general argument register. */
1208 /* Store it as the integers, 8 bytes at the time, if
1209 necessary spilling on the stack. */
1213 /* Store return address. */
1214 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1216 /* Update stack pointer. */
1217 regcache_cooked_write_unsigned (regcache,
1218 gdbarch_sp_regnum (gdbarch), sp);
1223 /* Find a function's return value in the appropriate registers (in
1224 regbuf), and copy it into valbuf. Extract from an array REGBUF
1225 containing the (raw) register state a function return value of type
1226 TYPE, and copy that, in virtual format, into VALBUF. */
1228 sh64_extract_return_value (struct type *type, struct regcache *regcache,
1231 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1232 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1233 int len = TYPE_LENGTH (type);
1235 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1239 /* Return value stored in gdbarch_fp0_regnum. */
1240 regcache_raw_read (regcache,
1241 gdbarch_fp0_regnum (gdbarch), valbuf);
1245 /* return value stored in DR0_REGNUM. */
1249 regcache_cooked_read (regcache, DR0_REGNUM, buf);
1251 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1252 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1255 floatformat_to_doublest (&floatformat_ieee_double_big,
1257 store_typed_floating (valbuf, type, val);
1266 /* Result is in register 2. If smaller than 8 bytes, it is padded
1267 at the most significant end. */
1268 regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf);
1270 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1271 offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM)
1275 memcpy (valbuf, buf + offset, len);
1278 error (_("bad size for return value"));
1282 /* Write into appropriate registers a function return value
1283 of type TYPE, given in virtual format.
1284 If the architecture is sh4 or sh3e, store a function's return value
1285 in the R0 general register or in the FP0 floating point register,
1286 depending on the type of the return value. In all the other cases
1287 the result is stored in r0, left-justified. */
1290 sh64_store_return_value (struct type *type, struct regcache *regcache,
1293 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1294 char buf[64]; /* more than enough... */
1295 int len = TYPE_LENGTH (type);
1297 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1299 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1300 for (i = 0; i < len; i += 4)
1301 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1302 regcache_raw_write (regcache, regnum++,
1303 (char *) valbuf + len - 4 - i);
1305 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1309 int return_register = DEFAULT_RETURN_REGNUM;
1312 if (len <= register_size (gdbarch, return_register))
1314 /* Pad with zeros. */
1315 memset (buf, 0, register_size (gdbarch, return_register));
1316 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1317 offset = 0; /*register_size (gdbarch,
1318 return_register) - len;*/
1320 offset = register_size (gdbarch, return_register) - len;
1322 memcpy (buf + offset, valbuf, len);
1323 regcache_raw_write (regcache, return_register, buf);
1326 regcache_raw_write (regcache, return_register, valbuf);
1330 static enum return_value_convention
1331 sh64_return_value (struct gdbarch *gdbarch, struct type *func_type,
1332 struct type *type, struct regcache *regcache,
1333 gdb_byte *readbuf, const gdb_byte *writebuf)
1335 if (sh64_use_struct_convention (type))
1336 return RETURN_VALUE_STRUCT_CONVENTION;
1338 sh64_store_return_value (type, regcache, writebuf);
1340 sh64_extract_return_value (type, regcache, readbuf);
1341 return RETURN_VALUE_REGISTER_CONVENTION;
1345 sh64_show_media_regs (struct frame_info *frame)
1347 struct gdbarch *gdbarch = get_frame_arch (frame);
1352 phex (get_frame_register_unsigned (frame,
1353 gdbarch_pc_regnum (gdbarch)), 8),
1354 phex (get_frame_register_unsigned (frame, SR_REGNUM), 8));
1358 phex (get_frame_register_unsigned (frame, SSR_REGNUM), 8),
1359 phex (get_frame_register_unsigned (frame, SPC_REGNUM), 8));
1362 phex (get_frame_register_unsigned (frame, FPSCR_REGNUM), 8));
1364 for (i = 0; i < 64; i = i + 4)
1366 ("\nR%d-R%d %s %s %s %s\n",
1368 phex (get_frame_register_unsigned (frame, i + 0), 8),
1369 phex (get_frame_register_unsigned (frame, i + 1), 8),
1370 phex (get_frame_register_unsigned (frame, i + 2), 8),
1371 phex (get_frame_register_unsigned (frame, i + 3), 8));
1373 printf_filtered ("\n");
1375 for (i = 0; i < 64; i = i + 8)
1377 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1379 (long) get_frame_register_unsigned
1380 (frame, gdbarch_fp0_regnum (gdbarch) + i + 0),
1381 (long) get_frame_register_unsigned
1382 (frame, gdbarch_fp0_regnum (gdbarch) + i + 1),
1383 (long) get_frame_register_unsigned
1384 (frame, gdbarch_fp0_regnum (gdbarch) + i + 2),
1385 (long) get_frame_register_unsigned
1386 (frame, gdbarch_fp0_regnum (gdbarch) + i + 3),
1387 (long) get_frame_register_unsigned
1388 (frame, gdbarch_fp0_regnum (gdbarch) + i + 4),
1389 (long) get_frame_register_unsigned
1390 (frame, gdbarch_fp0_regnum (gdbarch) + i + 5),
1391 (long) get_frame_register_unsigned
1392 (frame, gdbarch_fp0_regnum (gdbarch) + i + 6),
1393 (long) get_frame_register_unsigned
1394 (frame, gdbarch_fp0_regnum (gdbarch) + i + 7));
1398 sh64_show_compact_regs (struct frame_info *frame)
1400 struct gdbarch *gdbarch = get_frame_arch (frame);
1405 phex (get_frame_register_unsigned (frame, PC_C_REGNUM), 8));
1408 ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1409 (long) get_frame_register_unsigned (frame, GBR_C_REGNUM),
1410 (long) get_frame_register_unsigned (frame, MACH_C_REGNUM),
1411 (long) get_frame_register_unsigned (frame, MACL_C_REGNUM),
1412 (long) get_frame_register_unsigned (frame, PR_C_REGNUM),
1413 (long) get_frame_register_unsigned (frame, T_C_REGNUM));
1415 ("FPSCR=%08lx FPUL=%08lx\n",
1416 (long) get_frame_register_unsigned (frame, FPSCR_C_REGNUM),
1417 (long) get_frame_register_unsigned (frame, FPUL_C_REGNUM));
1419 for (i = 0; i < 16; i = i + 4)
1421 ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1423 (long) get_frame_register_unsigned (frame, i + 0),
1424 (long) get_frame_register_unsigned (frame, i + 1),
1425 (long) get_frame_register_unsigned (frame, i + 2),
1426 (long) get_frame_register_unsigned (frame, i + 3));
1428 printf_filtered ("\n");
1430 for (i = 0; i < 16; i = i + 8)
1432 ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1434 (long) get_frame_register_unsigned
1435 (frame, gdbarch_fp0_regnum (gdbarch) + i + 0),
1436 (long) get_frame_register_unsigned
1437 (frame, gdbarch_fp0_regnum (gdbarch) + i + 1),
1438 (long) get_frame_register_unsigned
1439 (frame, gdbarch_fp0_regnum (gdbarch) + i + 2),
1440 (long) get_frame_register_unsigned
1441 (frame, gdbarch_fp0_regnum (gdbarch) + i + 3),
1442 (long) get_frame_register_unsigned
1443 (frame, gdbarch_fp0_regnum (gdbarch) + i + 4),
1444 (long) get_frame_register_unsigned
1445 (frame, gdbarch_fp0_regnum (gdbarch) + i + 5),
1446 (long) get_frame_register_unsigned
1447 (frame, gdbarch_fp0_regnum (gdbarch) + i + 6),
1448 (long) get_frame_register_unsigned
1449 (frame, gdbarch_fp0_regnum (gdbarch) + i + 7));
1452 /* FIXME!!! This only shows the registers for shmedia, excluding the
1453 pseudo registers. */
1455 sh64_show_regs (struct frame_info *frame)
1457 if (pc_is_isa32 (get_frame_pc (frame)))
1458 sh64_show_media_regs (frame);
1460 sh64_show_compact_regs (frame);
1465 SH MEDIA MODE (ISA 32)
1466 general registers (64-bit) 0-63
1467 0 r0, r1, r2, r3, r4, r5, r6, r7,
1468 64 r8, r9, r10, r11, r12, r13, r14, r15,
1469 128 r16, r17, r18, r19, r20, r21, r22, r23,
1470 192 r24, r25, r26, r27, r28, r29, r30, r31,
1471 256 r32, r33, r34, r35, r36, r37, r38, r39,
1472 320 r40, r41, r42, r43, r44, r45, r46, r47,
1473 384 r48, r49, r50, r51, r52, r53, r54, r55,
1474 448 r56, r57, r58, r59, r60, r61, r62, r63,
1479 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1482 target registers (64-bit) 68-75
1483 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1485 floating point state control register (32-bit) 76
1488 single precision floating point registers (32-bit) 77-140
1489 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1490 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1491 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1492 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1493 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1494 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1495 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1496 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1498 TOTAL SPACE FOR REGISTERS: 868 bytes
1500 From here on they are all pseudo registers: no memory allocated.
1501 REGISTER_BYTE returns the register byte for the base register.
1503 double precision registers (pseudo) 141-172
1504 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1505 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1506 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1507 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1509 floating point pairs (pseudo) 173-204
1510 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1511 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1512 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1513 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1515 floating point vectors (4 floating point regs) (pseudo) 205-220
1516 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1517 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1519 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1520 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1521 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1523 gbr_c, mach_c, macl_c, pr_c, t_c,
1525 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1526 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1527 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1528 fv0_c, fv4_c, fv8_c, fv12_c
1531 static struct type *
1532 sh64_build_float_register_type (struct gdbarch *gdbarch, int high)
1534 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
1538 /* Return the GDB type object for the "standard" data type
1539 of data in register REG_NR. */
1540 static struct type *
1541 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
1543 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
1544 && reg_nr <= FP_LAST_REGNUM)
1545 || (reg_nr >= FP0_C_REGNUM
1546 && reg_nr <= FP_LAST_C_REGNUM))
1547 return builtin_type (gdbarch)->builtin_float;
1548 else if ((reg_nr >= DR0_REGNUM
1549 && reg_nr <= DR_LAST_REGNUM)
1550 || (reg_nr >= DR0_C_REGNUM
1551 && reg_nr <= DR_LAST_C_REGNUM))
1552 return builtin_type (gdbarch)->builtin_double;
1553 else if (reg_nr >= FPP0_REGNUM
1554 && reg_nr <= FPP_LAST_REGNUM)
1555 return sh64_build_float_register_type (gdbarch, 1);
1556 else if ((reg_nr >= FV0_REGNUM
1557 && reg_nr <= FV_LAST_REGNUM)
1558 ||(reg_nr >= FV0_C_REGNUM
1559 && reg_nr <= FV_LAST_C_REGNUM))
1560 return sh64_build_float_register_type (gdbarch, 3);
1561 else if (reg_nr == FPSCR_REGNUM)
1562 return builtin_type (gdbarch)->builtin_int;
1563 else if (reg_nr >= R0_C_REGNUM
1564 && reg_nr < FP0_C_REGNUM)
1565 return builtin_type (gdbarch)->builtin_int;
1567 return builtin_type (gdbarch)->builtin_long_long;
1571 sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum,
1572 struct type *type, char *from, char *to)
1574 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1576 /* It is a no-op. */
1577 memcpy (to, from, register_size (gdbarch, regnum));
1581 if ((regnum >= DR0_REGNUM
1582 && regnum <= DR_LAST_REGNUM)
1583 || (regnum >= DR0_C_REGNUM
1584 && regnum <= DR_LAST_C_REGNUM))
1587 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1589 store_typed_floating (to, type, val);
1592 error (_("sh64_register_convert_to_virtual "
1593 "called with non DR register number"));
1597 sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type,
1598 int regnum, const void *from, void *to)
1600 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1602 /* It is a no-op. */
1603 memcpy (to, from, register_size (gdbarch, regnum));
1607 if ((regnum >= DR0_REGNUM
1608 && regnum <= DR_LAST_REGNUM)
1609 || (regnum >= DR0_C_REGNUM
1610 && regnum <= DR_LAST_C_REGNUM))
1612 DOUBLEST val = extract_typed_floating (from, type);
1613 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1617 error (_("sh64_register_convert_to_raw called "
1618 "with non DR register number"));
1621 /* Concatenate PORTIONS contiguous raw registers starting at
1622 BASE_REGNUM into BUFFER. */
1624 static enum register_status
1625 pseudo_register_read_portions (struct gdbarch *gdbarch,
1626 struct regcache *regcache,
1628 int base_regnum, gdb_byte *buffer)
1632 for (portion = 0; portion < portions; portion++)
1634 enum register_status status;
1637 b = buffer + register_size (gdbarch, base_regnum) * portion;
1638 status = regcache_raw_read (regcache, base_regnum + portion, b);
1639 if (status != REG_VALID)
1646 static enum register_status
1647 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1648 int reg_nr, gdb_byte *buffer)
1650 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1653 char temp_buffer[MAX_REGISTER_SIZE];
1654 enum register_status status;
1656 if (reg_nr >= DR0_REGNUM
1657 && reg_nr <= DR_LAST_REGNUM)
1659 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1661 /* Build the value in the provided buffer. */
1662 /* DR regs are double precision registers obtained by
1663 concatenating 2 single precision floating point registers. */
1664 status = pseudo_register_read_portions (gdbarch, regcache,
1665 2, base_regnum, temp_buffer);
1666 if (status == REG_VALID)
1668 /* We must pay attention to the endianness. */
1669 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1670 register_type (gdbarch, reg_nr),
1671 temp_buffer, buffer);
1677 else if (reg_nr >= FPP0_REGNUM
1678 && reg_nr <= FPP_LAST_REGNUM)
1680 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1682 /* Build the value in the provided buffer. */
1683 /* FPP regs are pairs of single precision registers obtained by
1684 concatenating 2 single precision floating point registers. */
1685 return pseudo_register_read_portions (gdbarch, regcache,
1686 2, base_regnum, buffer);
1689 else if (reg_nr >= FV0_REGNUM
1690 && reg_nr <= FV_LAST_REGNUM)
1692 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1694 /* Build the value in the provided buffer. */
1695 /* FV regs are vectors of single precision registers obtained by
1696 concatenating 4 single precision floating point registers. */
1697 return pseudo_register_read_portions (gdbarch, regcache,
1698 4, base_regnum, buffer);
1701 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1702 else if (reg_nr >= R0_C_REGNUM
1703 && reg_nr <= T_C_REGNUM)
1705 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1707 /* Build the value in the provided buffer. */
1708 status = regcache_raw_read (regcache, base_regnum, temp_buffer);
1709 if (status != REG_VALID)
1711 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1714 temp_buffer + offset, 4); /* get LOWER 32 bits only???? */
1718 else if (reg_nr >= FP0_C_REGNUM
1719 && reg_nr <= FP_LAST_C_REGNUM)
1721 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1723 /* Build the value in the provided buffer. */
1724 /* Floating point registers map 1-1 to the media fp regs,
1725 they have the same size and endianness. */
1726 return regcache_raw_read (regcache, base_regnum, buffer);
1729 else if (reg_nr >= DR0_C_REGNUM
1730 && reg_nr <= DR_LAST_C_REGNUM)
1732 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1734 /* DR_C regs are double precision registers obtained by
1735 concatenating 2 single precision floating point registers. */
1736 status = pseudo_register_read_portions (gdbarch, regcache,
1737 2, base_regnum, temp_buffer);
1738 if (status == REG_VALID)
1740 /* We must pay attention to the endianness. */
1741 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1742 register_type (gdbarch, reg_nr),
1743 temp_buffer, buffer);
1748 else if (reg_nr >= FV0_C_REGNUM
1749 && reg_nr <= FV_LAST_C_REGNUM)
1751 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1753 /* Build the value in the provided buffer. */
1754 /* FV_C regs are vectors of single precision registers obtained by
1755 concatenating 4 single precision floating point registers. */
1756 return pseudo_register_read_portions (gdbarch, regcache,
1757 4, base_regnum, buffer);
1760 else if (reg_nr == FPSCR_C_REGNUM)
1762 int fpscr_base_regnum;
1764 unsigned int fpscr_value;
1765 unsigned int sr_value;
1766 unsigned int fpscr_c_value;
1767 unsigned int fpscr_c_part1_value;
1768 unsigned int fpscr_c_part2_value;
1770 fpscr_base_regnum = FPSCR_REGNUM;
1771 sr_base_regnum = SR_REGNUM;
1773 /* Build the value in the provided buffer. */
1774 /* FPSCR_C is a very weird register that contains sparse bits
1775 from the FPSCR and the SR architectural registers.
1782 2-17 Bit 2-18 of FPSCR
1783 18-20 Bits 12,13,14 of SR
1787 /* Get FPSCR into a local buffer. */
1788 status = regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1789 if (status != REG_VALID)
1791 /* Get value as an int. */
1792 fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1793 /* Get SR into a local buffer */
1794 status = regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1795 if (status != REG_VALID)
1797 /* Get value as an int. */
1798 sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1799 /* Build the new value. */
1800 fpscr_c_part1_value = fpscr_value & 0x3fffd;
1801 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
1802 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
1803 /* Store that in out buffer!!! */
1804 store_unsigned_integer (buffer, 4, byte_order, fpscr_c_value);
1805 /* FIXME There is surely an endianness gotcha here. */
1810 else if (reg_nr == FPUL_C_REGNUM)
1812 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1814 /* FPUL_C register is floating point register 32,
1815 same size, same endianness. */
1816 return regcache_raw_read (regcache, base_regnum, buffer);
1819 gdb_assert_not_reached ("invalid pseudo register number");
1823 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1824 int reg_nr, const gdb_byte *buffer)
1826 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1827 int base_regnum, portion;
1829 char temp_buffer[MAX_REGISTER_SIZE];
1831 if (reg_nr >= DR0_REGNUM
1832 && reg_nr <= DR_LAST_REGNUM)
1834 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1835 /* We must pay attention to the endianness. */
1836 sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr),
1838 buffer, temp_buffer);
1840 /* Write the real regs for which this one is an alias. */
1841 for (portion = 0; portion < 2; portion++)
1842 regcache_raw_write (regcache, base_regnum + portion,
1844 + register_size (gdbarch,
1845 base_regnum) * portion));
1848 else if (reg_nr >= FPP0_REGNUM
1849 && reg_nr <= FPP_LAST_REGNUM)
1851 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1853 /* Write the real regs for which this one is an alias. */
1854 for (portion = 0; portion < 2; portion++)
1855 regcache_raw_write (regcache, base_regnum + portion,
1857 + register_size (gdbarch,
1858 base_regnum) * portion));
1861 else if (reg_nr >= FV0_REGNUM
1862 && reg_nr <= FV_LAST_REGNUM)
1864 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1866 /* Write the real regs for which this one is an alias. */
1867 for (portion = 0; portion < 4; portion++)
1868 regcache_raw_write (regcache, base_regnum + portion,
1870 + register_size (gdbarch,
1871 base_regnum) * portion));
1874 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1875 register but only 4 bytes of it. */
1876 else if (reg_nr >= R0_C_REGNUM
1877 && reg_nr <= T_C_REGNUM)
1879 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1880 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1881 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1885 /* Let's read the value of the base register into a temporary
1886 buffer, so that overwriting the last four bytes with the new
1887 value of the pseudo will leave the upper 4 bytes unchanged. */
1888 regcache_raw_read (regcache, base_regnum, temp_buffer);
1889 /* Write as an 8 byte quantity. */
1890 memcpy (temp_buffer + offset, buffer, 4);
1891 regcache_raw_write (regcache, base_regnum, temp_buffer);
1894 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1895 registers. Both are 4 bytes. */
1896 else if (reg_nr >= FP0_C_REGNUM
1897 && reg_nr <= FP_LAST_C_REGNUM)
1899 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1900 regcache_raw_write (regcache, base_regnum, buffer);
1903 else if (reg_nr >= DR0_C_REGNUM
1904 && reg_nr <= DR_LAST_C_REGNUM)
1906 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1907 for (portion = 0; portion < 2; portion++)
1909 /* We must pay attention to the endianness. */
1910 sh64_register_convert_to_raw (gdbarch,
1911 register_type (gdbarch, reg_nr),
1913 buffer, temp_buffer);
1915 regcache_raw_write (regcache, base_regnum + portion,
1917 + register_size (gdbarch,
1918 base_regnum) * portion));
1922 else if (reg_nr >= FV0_C_REGNUM
1923 && reg_nr <= FV_LAST_C_REGNUM)
1925 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1927 for (portion = 0; portion < 4; portion++)
1929 regcache_raw_write (regcache, base_regnum + portion,
1931 + register_size (gdbarch,
1932 base_regnum) * portion));
1936 else if (reg_nr == FPSCR_C_REGNUM)
1938 int fpscr_base_regnum;
1940 unsigned int fpscr_value;
1941 unsigned int sr_value;
1942 unsigned int old_fpscr_value;
1943 unsigned int old_sr_value;
1944 unsigned int fpscr_c_value;
1945 unsigned int fpscr_mask;
1946 unsigned int sr_mask;
1948 fpscr_base_regnum = FPSCR_REGNUM;
1949 sr_base_regnum = SR_REGNUM;
1951 /* FPSCR_C is a very weird register that contains sparse bits
1952 from the FPSCR and the SR architectural registers.
1959 2-17 Bit 2-18 of FPSCR
1960 18-20 Bits 12,13,14 of SR
1964 /* Get value as an int. */
1965 fpscr_c_value = extract_unsigned_integer (buffer, 4, byte_order);
1967 /* Build the new values. */
1968 fpscr_mask = 0x0003fffd;
1969 sr_mask = 0x001c0000;
1971 fpscr_value = fpscr_c_value & fpscr_mask;
1972 sr_value = (fpscr_value & sr_mask) >> 6;
1974 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1975 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1976 old_fpscr_value &= 0xfffc0002;
1977 fpscr_value |= old_fpscr_value;
1978 store_unsigned_integer (temp_buffer, 4, byte_order, fpscr_value);
1979 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
1981 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1982 old_sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1983 old_sr_value &= 0xffff8fff;
1984 sr_value |= old_sr_value;
1985 store_unsigned_integer (temp_buffer, 4, byte_order, sr_value);
1986 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
1989 else if (reg_nr == FPUL_C_REGNUM)
1991 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1992 regcache_raw_write (regcache, base_regnum, buffer);
1996 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1997 shmedia REGISTERS. */
1998 /* Control registers, compact mode. */
2000 sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame,
2003 switch (cr_c_regnum)
2006 fprintf_filtered (file, "pc_c\t0x%08x\n",
2007 (int) get_frame_register_unsigned (frame, cr_c_regnum));
2010 fprintf_filtered (file, "gbr_c\t0x%08x\n",
2011 (int) get_frame_register_unsigned (frame, cr_c_regnum));
2014 fprintf_filtered (file, "mach_c\t0x%08x\n",
2015 (int) get_frame_register_unsigned (frame, cr_c_regnum));
2018 fprintf_filtered (file, "macl_c\t0x%08x\n",
2019 (int) get_frame_register_unsigned (frame, cr_c_regnum));
2022 fprintf_filtered (file, "pr_c\t0x%08x\n",
2023 (int) get_frame_register_unsigned (frame, cr_c_regnum));
2026 fprintf_filtered (file, "t_c\t0x%08x\n",
2027 (int) get_frame_register_unsigned (frame, cr_c_regnum));
2029 case FPSCR_C_REGNUM:
2030 fprintf_filtered (file, "fpscr_c\t0x%08x\n",
2031 (int) get_frame_register_unsigned (frame, cr_c_regnum));
2034 fprintf_filtered (file, "fpul_c\t0x%08x\n",
2035 (int) get_frame_register_unsigned (frame, cr_c_regnum));
2041 sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file,
2042 struct frame_info *frame, int regnum)
2043 { /* Do values for FP (float) regs. */
2044 unsigned char *raw_buffer;
2045 double flt; /* Double extracted from raw hex data. */
2049 /* Allocate space for the float. */
2050 raw_buffer = (unsigned char *)
2051 alloca (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)));
2053 /* Get the data in raw format. */
2054 if (!frame_register_read (frame, regnum, raw_buffer))
2055 error (_("can't read register %d (%s)"),
2056 regnum, gdbarch_register_name (gdbarch, regnum));
2058 /* Get the register as a number. */
2059 flt = unpack_double (builtin_type (gdbarch)->builtin_float,
2062 /* Print the name and some spaces. */
2063 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
2064 print_spaces_filtered (15 - strlen (gdbarch_register_name
2065 (gdbarch, regnum)), file);
2067 /* Print the value. */
2069 fprintf_filtered (file, "<invalid float>");
2071 fprintf_filtered (file, "%-10.9g", flt);
2073 /* Print the fp register as hex. */
2074 fprintf_filtered (file, "\t(raw 0x");
2075 for (j = 0; j < register_size (gdbarch, regnum); j++)
2077 int idx = gdbarch_byte_order (gdbarch)
2078 == BFD_ENDIAN_BIG ? j : register_size
2079 (gdbarch, regnum) - 1 - j;
2080 fprintf_filtered (file, "%02x", raw_buffer[idx]);
2082 fprintf_filtered (file, ")");
2083 fprintf_filtered (file, "\n");
2087 sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
2088 struct frame_info *frame, int regnum)
2090 /* All the sh64-compact mode registers are pseudo registers. */
2092 if (regnum < gdbarch_num_regs (gdbarch)
2093 || regnum >= gdbarch_num_regs (gdbarch)
2094 + NUM_PSEUDO_REGS_SH_MEDIA
2095 + NUM_PSEUDO_REGS_SH_COMPACT)
2096 internal_error (__FILE__, __LINE__,
2097 _("Invalid pseudo register number %d\n"), regnum);
2099 else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM))
2101 int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum);
2102 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM,
2103 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2104 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2107 else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM))
2109 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2110 fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM,
2111 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2112 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2115 else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM))
2117 int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum);
2118 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2119 regnum - FV0_REGNUM,
2120 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2121 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2122 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2123 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2126 else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM))
2128 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2129 fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2130 regnum - FV0_C_REGNUM,
2131 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2132 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2133 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2134 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2137 else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM)
2139 int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum);
2140 fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM,
2141 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2142 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2145 else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM)
2147 int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2148 fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM,
2149 (unsigned) get_frame_register_unsigned (frame, c_regnum));
2151 else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM)
2152 /* This should work also for pseudoregs. */
2153 sh64_do_fp_register (gdbarch, file, frame, regnum);
2154 else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM)
2155 sh64_do_cr_c_register_info (file, frame, regnum);
2159 sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file,
2160 struct frame_info *frame, int regnum)
2162 unsigned char raw_buffer[MAX_REGISTER_SIZE];
2163 struct value_print_options opts;
2165 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
2166 print_spaces_filtered (15 - strlen (gdbarch_register_name
2167 (gdbarch, regnum)), file);
2169 /* Get the data in raw format. */
2170 if (!frame_register_read (frame, regnum, raw_buffer))
2171 fprintf_filtered (file, "*value not available*\n");
2173 get_formatted_print_options (&opts, 'x');
2175 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2176 file, 0, NULL, &opts, current_language);
2177 fprintf_filtered (file, "\t");
2178 get_formatted_print_options (&opts, 0);
2180 val_print (register_type (gdbarch, regnum), raw_buffer, 0, 0,
2181 file, 0, NULL, &opts, current_language);
2182 fprintf_filtered (file, "\n");
2186 sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file,
2187 struct frame_info *frame, int regnum)
2189 if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch)
2190 + gdbarch_num_pseudo_regs (gdbarch))
2191 internal_error (__FILE__, __LINE__,
2192 _("Invalid register number %d\n"), regnum);
2194 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
2196 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2197 sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */
2199 sh64_do_register (gdbarch, file, frame, regnum);
2202 else if (regnum < gdbarch_num_regs (gdbarch)
2203 + gdbarch_num_pseudo_regs (gdbarch))
2204 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2208 sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2209 struct frame_info *frame, int regnum,
2212 if (regnum != -1) /* Do one specified register. */
2214 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2215 error (_("Not a valid register for the current processor type"));
2217 sh64_print_register (gdbarch, file, frame, regnum);
2220 /* Do all (or most) registers. */
2223 while (regnum < gdbarch_num_regs (gdbarch))
2225 /* If the register name is empty, it is undefined for this
2226 processor, so don't display anything. */
2227 if (gdbarch_register_name (gdbarch, regnum) == NULL
2228 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
2234 if (TYPE_CODE (register_type (gdbarch, regnum))
2239 /* true for "INFO ALL-REGISTERS" command. */
2240 sh64_do_fp_register (gdbarch, file, frame, regnum);
2244 regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch);
2249 sh64_do_register (gdbarch, file, frame, regnum);
2255 while (regnum < gdbarch_num_regs (gdbarch)
2256 + gdbarch_num_pseudo_regs (gdbarch))
2258 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2265 sh64_compact_print_registers_info (struct gdbarch *gdbarch,
2266 struct ui_file *file,
2267 struct frame_info *frame, int regnum,
2270 if (regnum != -1) /* Do one specified register. */
2272 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2273 error (_("Not a valid register for the current processor type"));
2275 if (regnum >= 0 && regnum < R0_C_REGNUM)
2276 error (_("Not a valid register for the current processor mode."));
2278 sh64_print_register (gdbarch, file, frame, regnum);
2281 /* Do all compact registers. */
2283 regnum = R0_C_REGNUM;
2284 while (regnum < gdbarch_num_regs (gdbarch)
2285 + gdbarch_num_pseudo_regs (gdbarch))
2287 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2294 sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2295 struct frame_info *frame, int regnum, int fpregs)
2297 if (pc_is_isa32 (get_frame_pc (frame)))
2298 sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2300 sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2303 static struct sh64_frame_cache *
2304 sh64_alloc_frame_cache (void)
2306 struct sh64_frame_cache *cache;
2309 cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache);
2313 cache->saved_sp = 0;
2314 cache->sp_offset = 0;
2317 /* Frameless until proven otherwise. */
2320 /* Saved registers. We initialize these to -1 since zero is a valid
2321 offset (that's where fp is supposed to be stored). */
2322 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2324 cache->saved_regs[i] = -1;
2330 static struct sh64_frame_cache *
2331 sh64_frame_cache (struct frame_info *this_frame, void **this_cache)
2333 struct gdbarch *gdbarch;
2334 struct sh64_frame_cache *cache;
2335 CORE_ADDR current_pc;
2341 gdbarch = get_frame_arch (this_frame);
2342 cache = sh64_alloc_frame_cache ();
2343 *this_cache = cache;
2345 current_pc = get_frame_pc (this_frame);
2346 cache->media_mode = pc_is_isa32 (current_pc);
2348 /* In principle, for normal frames, fp holds the frame pointer,
2349 which holds the base address for the current stack frame.
2350 However, for functions that don't need it, the frame pointer is
2351 optional. For these "frameless" functions the frame pointer is
2352 actually the frame pointer of the calling frame. */
2353 cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM);
2354 if (cache->base == 0)
2357 cache->pc = get_frame_func (this_frame);
2359 sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc);
2361 if (!cache->uses_fp)
2363 /* We didn't find a valid frame, which means that CACHE->base
2364 currently holds the frame pointer for our calling frame. If
2365 we're at the start of a function, or somewhere half-way its
2366 prologue, the function's frame probably hasn't been fully
2367 setup yet. Try to reconstruct the base address for the stack
2368 frame by looking at the stack pointer. For truly "frameless"
2369 functions this might work too. */
2370 cache->base = get_frame_register_unsigned
2371 (this_frame, gdbarch_sp_regnum (gdbarch));
2374 /* Now that we have the base address for the stack frame we can
2375 calculate the value of sp in the calling frame. */
2376 cache->saved_sp = cache->base + cache->sp_offset;
2378 /* Adjust all the saved registers such that they contain addresses
2379 instead of offsets. */
2380 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2381 if (cache->saved_regs[i] != -1)
2382 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i];
2387 static struct value *
2388 sh64_frame_prev_register (struct frame_info *this_frame,
2389 void **this_cache, int regnum)
2391 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2392 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2393 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2395 gdb_assert (regnum >= 0);
2397 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2398 frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2400 /* The PC of the previous frame is stored in the PR register of
2401 the current frame. Frob regnum so that we pull the value from
2402 the correct place. */
2403 if (regnum == gdbarch_pc_regnum (gdbarch))
2406 if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1)
2408 if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32
2409 && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM))
2412 val = read_memory_unsigned_integer (cache->saved_regs[regnum],
2414 return frame_unwind_got_constant (this_frame, regnum, val);
2417 return frame_unwind_got_memory (this_frame, regnum,
2418 cache->saved_regs[regnum]);
2421 return frame_unwind_got_register (this_frame, regnum, regnum);
2425 sh64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2426 struct frame_id *this_id)
2428 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2430 /* This marks the outermost frame. */
2431 if (cache->base == 0)
2434 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2437 static const struct frame_unwind sh64_frame_unwind = {
2439 default_frame_unwind_stop_reason,
2441 sh64_frame_prev_register,
2443 default_frame_sniffer
2447 sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2449 return frame_unwind_register_unsigned (next_frame,
2450 gdbarch_sp_regnum (gdbarch));
2454 sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2456 return frame_unwind_register_unsigned (next_frame,
2457 gdbarch_pc_regnum (gdbarch));
2460 static struct frame_id
2461 sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2463 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2464 gdbarch_sp_regnum (gdbarch));
2465 return frame_id_build (sp, get_frame_pc (this_frame));
2469 sh64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2471 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2476 static const struct frame_base sh64_frame_base = {
2478 sh64_frame_base_address,
2479 sh64_frame_base_address,
2480 sh64_frame_base_address
2485 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2487 struct gdbarch *gdbarch;
2488 struct gdbarch_tdep *tdep;
2490 /* If there is already a candidate, use it. */
2491 arches = gdbarch_list_lookup_by_info (arches, &info);
2493 return arches->gdbarch;
2495 /* None found, create a new architecture from the information
2497 tdep = XMALLOC (struct gdbarch_tdep);
2498 gdbarch = gdbarch_alloc (&info, tdep);
2500 /* Determine the ABI */
2501 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2503 /* If the ABI is the 64-bit one, it can only be sh-media. */
2504 tdep->sh_abi = SH_ABI_64;
2505 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2506 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2510 /* If the ABI is the 32-bit one it could be either media or
2512 tdep->sh_abi = SH_ABI_32;
2513 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2514 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2517 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2518 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2519 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2520 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2521 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2522 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2523 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2525 /* The number of real registers is the same whether we are in
2526 ISA16(compact) or ISA32(media). */
2527 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2528 set_gdbarch_sp_regnum (gdbarch, 15);
2529 set_gdbarch_pc_regnum (gdbarch, 64);
2530 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2531 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA
2532 + NUM_PSEUDO_REGS_SH_COMPACT);
2534 set_gdbarch_register_name (gdbarch, sh64_register_name);
2535 set_gdbarch_register_type (gdbarch, sh64_register_type);
2537 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2538 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2540 set_gdbarch_breakpoint_from_pc (gdbarch, sh64_breakpoint_from_pc);
2542 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2543 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2545 set_gdbarch_return_value (gdbarch, sh64_return_value);
2547 set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue);
2548 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2550 set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call);
2552 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2554 set_gdbarch_frame_align (gdbarch, sh64_frame_align);
2555 set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp);
2556 set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc);
2557 set_gdbarch_dummy_id (gdbarch, sh64_dummy_id);
2558 frame_base_set_default (gdbarch, &sh64_frame_base);
2560 set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info);
2562 set_gdbarch_elf_make_msymbol_special (gdbarch,
2563 sh64_elf_make_msymbol_special);
2565 /* Hook in ABI-specific overrides, if they have been registered. */
2566 gdbarch_init_osabi (info, gdbarch);
2568 dwarf2_append_unwinders (gdbarch);
2569 frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind);