1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "arch-utils.h"
44 /* Register numbers shared with the simulator. */
45 #include "gdb/sim-sh.h"
47 #include "sh64-tdep.h"
50 /* Information that is dependent on the processor variant. */
63 struct sh64_frame_cache
70 /* Flag showing that a frame has been created in the prologue code. */
75 /* Saved registers. */
76 CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
80 /* Registers of SH5 */
84 DEFAULT_RETURN_REGNUM = 2,
85 STRUCT_RETURN_REGNUM = 2,
88 FLOAT_ARGLAST_REGNUM = 11,
94 /* FPP stands for Floating Point Pair, to avoid confusion with
95 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
96 point register. Unfortunately on the sh5, the floating point
97 registers are called FR, and the floating point pairs are called FP. */
99 FPP_LAST_REGNUM = 204,
101 FV_LAST_REGNUM = 220,
103 R_LAST_C_REGNUM = 236,
110 FPSCR_C_REGNUM = 243,
113 FP_LAST_C_REGNUM = 260,
115 DR_LAST_C_REGNUM = 268,
117 FV_LAST_C_REGNUM = 272,
118 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
119 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
120 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
121 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
122 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
126 sh64_register_name (struct gdbarch *gdbarch, int reg_nr)
128 static char *register_names[] =
130 /* SH MEDIA MODE (ISA 32) */
131 /* general registers (64-bit) 0-63 */
132 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
133 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
134 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
135 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
136 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
137 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
138 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
139 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
144 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
147 /* target registers (64-bit) 68-75 */
148 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
150 /* floating point state control register (32-bit) 76 */
153 /* single precision floating point registers (32-bit) 77-140 */
154 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
155 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
156 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
157 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
158 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
159 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
160 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
161 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
163 /* double precision registers (pseudo) 141-172 */
164 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
165 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
166 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
167 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
169 /* floating point pairs (pseudo) 173-204 */
170 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
171 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
172 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
173 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
175 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
176 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
177 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
179 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
180 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
181 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
183 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
185 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
186 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
187 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
188 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
189 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
190 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
191 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
192 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return register_names[reg_nr];
202 #define NUM_PSEUDO_REGS_SH_MEDIA 80
203 #define NUM_PSEUDO_REGS_SH_COMPACT 51
205 /* Macros and functions for setting and testing a bit in a minimal
206 symbol that marks it as 32-bit function. The MSB of the minimal
207 symbol's "info" field is used for this purpose.
209 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
210 i.e. refers to a 32-bit function, and sets a "special" bit in a
211 minimal symbol to mark it as a 32-bit function
212 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
214 #define MSYMBOL_IS_SPECIAL(msym) \
215 MSYMBOL_TARGET_FLAG_1 (msym)
218 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
223 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
225 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
226 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
230 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
231 are some macros to test, set, or clear bit 0 of addresses. */
232 #define IS_ISA32_ADDR(addr) ((addr) & 1)
233 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
234 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
237 pc_is_isa32 (bfd_vma memaddr)
239 struct bound_minimal_symbol sym;
241 /* If bit 0 of the address is set, assume this is a
242 ISA32 (shmedia) address. */
243 if (IS_ISA32_ADDR (memaddr))
246 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
247 the high bit of the info field. Use this to decide if the function is
249 sym = lookup_minimal_symbol_by_pc (memaddr);
251 return MSYMBOL_IS_SPECIAL (sym.minsym);
257 sh64_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
259 if (pc_is_isa32 (*pcptr))
261 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
268 static const gdb_byte *
269 sh64_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
273 /* The BRK instruction for shmedia is
274 01101111 11110101 11111111 11110000
275 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
276 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
278 /* The BRK instruction for shcompact is
280 which translates in big endian mode to 0x0, 0x3b
281 and in little endian mode to 0x3b, 0x0 */
285 static unsigned char big_breakpoint_media[] = {
286 0x6f, 0xf5, 0xff, 0xf0
288 static unsigned char little_breakpoint_media[] = {
289 0xf0, 0xff, 0xf5, 0x6f
292 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
293 return big_breakpoint_media;
295 return little_breakpoint_media;
299 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
300 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
302 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
303 return big_breakpoint_compact;
305 return little_breakpoint_compact;
309 /* Prologue looks like
310 [mov.l <regs>,@-r15]...
315 Actually it can be more complicated than this. For instance, with
333 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
334 with l=1 and n = 18 0110101111110001010010100aaa0000 */
335 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
337 /* STS.L PR,@-r0 0100000000100010
338 r0-4-->r0, PR-->(r0) */
339 #define IS_STS_R0(x) ((x) == 0x4022)
341 /* STS PR, Rm 0000mmmm00101010
343 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
345 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
347 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
349 /* MOV.L R14,@(disp,r15) 000111111110dddd
350 R14-->(dispx4+r15) */
351 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
353 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
354 R18-->(dispx8+R14) */
355 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
357 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
358 R18-->(dispx8+R15) */
359 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
361 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
362 R18-->(dispx4+R15) */
363 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
365 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
366 R14-->(dispx8+R15) */
367 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
369 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
370 R14-->(dispx4+R15) */
371 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
373 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
375 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
377 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
379 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
381 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
383 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
385 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
387 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
389 #define IS_MOV_SP_FP_MEDIA(x) \
390 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
392 /* MOV #imm, R0 1110 0000 ssss ssss
394 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
396 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
397 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
399 /* ADD r15,r0 0011 0000 1111 1100
401 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
403 /* MOV.L R14 @-R0 0010 0000 1110 0110
404 R14-->(R0-4), R0-4-->R0 */
405 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
407 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
408 where Rm is one of r2-r9 which are the argument registers. */
409 /* FIXME: Recognize the float and double register moves too! */
410 #define IS_MEDIA_IND_ARG_MOV(x) \
411 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
412 && (((x) & 0x03f00000) >= 0x00200000 \
413 && ((x) & 0x03f00000) <= 0x00900000))
415 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
416 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
417 where Rm is one of r2-r9 which are the argument registers. */
418 #define IS_MEDIA_ARG_MOV(x) \
419 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
420 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
422 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
423 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
424 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
425 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
426 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
427 #define IS_MEDIA_MOV_TO_R14(x) \
428 ((((x) & 0xfffffc0f) == 0xa0e00000) \
429 || (((x) & 0xfffffc0f) == 0xa4e00000) \
430 || (((x) & 0xfffffc0f) == 0xa8e00000) \
431 || (((x) & 0xfffffc0f) == 0xb4e00000) \
432 || (((x) & 0xfffffc0f) == 0xbce00000))
434 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
436 #define IS_COMPACT_IND_ARG_MOV(x) \
437 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
438 && (((x) & 0x00f0) <= 0x0090))
440 /* compact direct arg move!
441 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
442 #define IS_COMPACT_ARG_MOV(x) \
443 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
444 && ((x) & 0x00f0) <= 0x0090))
446 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
447 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
448 #define IS_COMPACT_MOV_TO_R14(x) \
449 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
451 #define IS_JSR_R0(x) ((x) == 0x400b)
452 #define IS_NOP(x) ((x) == 0x0009)
455 /* MOV r15,r14 0110111011110011
457 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
459 /* ADD #imm,r15 01111111iiiiiiii
461 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
463 /* Skip any prologue before the guts of a function. */
465 /* Skip the prologue using the debug information. If this fails we'll
466 fall back on the 'guess' method below. */
468 after_prologue (CORE_ADDR pc)
470 struct symtab_and_line sal;
471 CORE_ADDR func_addr, func_end;
473 /* If we can not find the symbol in the partial symbol table, then
474 there is no hope we can determine the function's start address
476 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
480 /* Get the line associated with FUNC_ADDR. */
481 sal = find_pc_line (func_addr, 0);
483 /* There are only two cases to consider. First, the end of the source line
484 is within the function bounds. In that case we return the end of the
485 source line. Second is the end of the source line extends beyond the
486 bounds of the current function. We need to use the slow code to
487 examine instructions in that case. */
488 if (sal.end < func_end)
495 look_for_args_moves (struct gdbarch *gdbarch,
496 CORE_ADDR start_pc, int media_mode)
498 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
501 int insn_size = (media_mode ? 4 : 2);
503 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
507 w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
508 insn_size, byte_order);
510 if (IS_MEDIA_IND_ARG_MOV (w))
512 /* This must be followed by a store to r14, so the argument
513 is where the debug info says it is. This can happen after
514 the SP has been saved, unfortunately. */
516 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
517 insn_size, byte_order);
519 if (IS_MEDIA_MOV_TO_R14 (next_insn))
522 else if (IS_MEDIA_ARG_MOV (w))
524 /* These instructions store directly the argument in r14. */
532 w = read_memory_integer (here, insn_size, byte_order);
535 if (IS_COMPACT_IND_ARG_MOV (w))
537 /* This must be followed by a store to r14, so the argument
538 is where the debug info says it is. This can happen after
539 the SP has been saved, unfortunately. */
541 int next_insn = 0xffff & read_memory_integer (here, insn_size,
544 if (IS_COMPACT_MOV_TO_R14 (next_insn))
547 else if (IS_COMPACT_ARG_MOV (w))
549 /* These instructions store directly the argument in r14. */
552 else if (IS_MOVL_R0 (w))
554 /* There is a function that gcc calls to get the arguments
555 passed correctly to the function. Only after this
556 function call the arguments will be found at the place
557 where they are supposed to be. This happens in case the
558 argument has to be stored into a 64-bit register (for
559 instance doubles, long longs). SHcompact doesn't have
560 access to the full 64-bits, so we store the register in
561 stack slot and store the address of the stack slot in
562 the register, then do a call through a wrapper that
563 loads the memory value into the register. A SHcompact
564 callee calls an argument decoder
565 (GCC_shcompact_incoming_args) that stores the 64-bit
566 value in a stack slot and stores the address of the
567 stack slot in the register. GCC thinks the argument is
568 just passed by transparent reference, but this is only
569 true after the argument decoder is called. Such a call
570 needs to be considered part of the prologue. */
572 /* This must be followed by a JSR @r0 instruction and by
573 a NOP instruction. After these, the prologue is over! */
575 int next_insn = 0xffff & read_memory_integer (here, insn_size,
578 if (IS_JSR_R0 (next_insn))
580 next_insn = 0xffff & read_memory_integer (here, insn_size,
584 if (IS_NOP (next_insn))
597 sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc)
599 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
608 if (pc_is_isa32 (start_pc) == 0)
614 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
619 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
620 insn_size, byte_order);
622 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
623 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
624 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w)
625 || IS_PTABSL_R18 (w))
629 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
637 /* Don't bail out yet, we may have arguments stored in
638 registers here, according to the debug info, so that
639 gdb can print the frames correctly. */
640 start_pc = look_for_args_moves (gdbarch,
641 here - insn_size, media_mode);
647 int w = 0xffff & read_memory_integer (here, insn_size, byte_order);
650 if (IS_STS_R0 (w) || IS_STS_PR (w)
651 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
652 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
656 else if (IS_MOV_SP_FP (w))
664 /* Don't bail out yet, we may have arguments stored in
665 registers here, according to the debug info, so that
666 gdb can print the frames correctly. */
667 start_pc = look_for_args_moves (gdbarch,
668 here - insn_size, media_mode);
678 sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
680 CORE_ADDR post_prologue_pc;
682 /* See if we can determine the end of the prologue via the symbol table.
683 If so, then return either PC, or the PC after the prologue, whichever
685 post_prologue_pc = after_prologue (pc);
687 /* If after_prologue returned a useful address, then use it. Else
688 fall back on the instruction skipping code. */
689 if (post_prologue_pc != 0)
690 return std::max (pc, post_prologue_pc);
692 return sh64_skip_prologue_hard_way (gdbarch, pc);
695 /* Should call_function allocate stack space for a struct return? */
697 sh64_use_struct_convention (struct type *type)
699 return (TYPE_LENGTH (type) > 8);
702 /* For vectors of 4 floating point registers. */
704 sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
708 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4;
712 /* For double precision floating point registers, i.e 2 fp regs. */
714 sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
718 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2;
722 /* For pairs of floating point registers. */
724 sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum)
728 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2;
734 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
735 GDB_REGNUM BASE_REGNUM
795 sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr)
797 int base_regnum = reg_nr;
799 /* general register N maps to general register N */
800 if (reg_nr >= R0_C_REGNUM
801 && reg_nr <= R_LAST_C_REGNUM)
802 base_regnum = reg_nr - R0_C_REGNUM;
804 /* floating point register N maps to floating point register N */
805 else if (reg_nr >= FP0_C_REGNUM
806 && reg_nr <= FP_LAST_C_REGNUM)
807 base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch);
809 /* double prec register N maps to base regnum for double prec register N */
810 else if (reg_nr >= DR0_C_REGNUM
811 && reg_nr <= DR_LAST_C_REGNUM)
812 base_regnum = sh64_dr_reg_base_num (gdbarch,
813 DR0_REGNUM + reg_nr - DR0_C_REGNUM);
815 /* vector N maps to base regnum for vector register N */
816 else if (reg_nr >= FV0_C_REGNUM
817 && reg_nr <= FV_LAST_C_REGNUM)
818 base_regnum = sh64_fv_reg_base_num (gdbarch,
819 FV0_REGNUM + reg_nr - FV0_C_REGNUM);
821 else if (reg_nr == PC_C_REGNUM)
822 base_regnum = gdbarch_pc_regnum (gdbarch);
824 else if (reg_nr == GBR_C_REGNUM)
827 else if (reg_nr == MACH_C_REGNUM
828 || reg_nr == MACL_C_REGNUM)
831 else if (reg_nr == PR_C_REGNUM)
832 base_regnum = PR_REGNUM;
834 else if (reg_nr == T_C_REGNUM)
837 else if (reg_nr == FPSCR_C_REGNUM)
838 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
840 else if (reg_nr == FPUL_C_REGNUM)
841 base_regnum = gdbarch_fp0_regnum (gdbarch) + 32;
847 sign_extend (int value, int bits)
849 value = value & ((1 << bits) - 1);
850 return (value & (1 << (bits - 1))
851 ? value | (~((1 << bits) - 1))
856 sh64_analyze_prologue (struct gdbarch *gdbarch,
857 struct sh64_frame_cache *cache,
859 CORE_ADDR current_pc)
866 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
868 cache->sp_offset = 0;
870 /* Loop around examining the prologue insns until we find something
871 that does not appear to be part of the prologue. But give up
872 after 20 of them, since we're getting silly then. */
876 if (cache->media_mode)
881 opc = pc + (insn_size * 28);
882 if (opc > current_pc)
884 for ( ; pc <= opc; pc += insn_size)
886 insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
888 insn_size, byte_order);
890 if (!cache->media_mode)
892 if (IS_STS_PR (insn))
894 int next_insn = read_memory_integer (pc + insn_size,
895 insn_size, byte_order);
896 if (IS_MOV_TO_R15 (next_insn))
898 cache->saved_regs[PR_REGNUM]
899 = cache->sp_offset - ((((next_insn & 0xf) ^ 0x8)
905 else if (IS_MOV_R14 (insn))
907 cache->saved_regs[MEDIA_FP_REGNUM] =
908 cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
912 else if (IS_MOV_R0 (insn))
914 /* Put in R0 the offset from SP at which to store some
915 registers. We are interested in this value, because it
916 will tell us where the given registers are stored within
918 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
921 else if (IS_ADD_SP_R0 (insn))
923 /* This instruction still prepares r0, but we don't care.
924 We already have the offset in r0_val. */
927 else if (IS_STS_R0 (insn))
929 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
930 cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
934 else if (IS_MOV_R14_R0 (insn))
936 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
937 cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
943 else if (IS_ADD_SP (insn))
944 cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
946 else if (IS_MOV_SP_FP (insn))
951 if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
953 sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
955 else if (IS_STQ_R18_R15 (insn))
956 cache->saved_regs[PR_REGNUM]
957 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
960 else if (IS_STL_R18_R15 (insn))
961 cache->saved_regs[PR_REGNUM]
962 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
965 else if (IS_STQ_R14_R15 (insn))
967 cache->saved_regs[MEDIA_FP_REGNUM]
968 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
973 else if (IS_STL_R14_R15 (insn))
975 cache->saved_regs[MEDIA_FP_REGNUM]
976 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
981 else if (IS_MOV_SP_FP_MEDIA (insn))
988 sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
993 /* Function: push_dummy_call
994 Setup the function arguments for calling a function in the inferior.
996 On the Renesas SH architecture, there are four registers (R4 to R7)
997 which are dedicated for passing function arguments. Up to the first
998 four arguments (depending on size) may go into these registers.
999 The rest go on the stack.
1001 Arguments that are smaller than 4 bytes will still take up a whole
1002 register or a whole 32-bit word on the stack, and will be
1003 right-justified in the register or the stack word. This includes
1004 chars, shorts, and small aggregate types.
1006 Arguments that are larger than 4 bytes may be split between two or
1007 more registers. If there are not enough registers free, an argument
1008 may be passed partly in a register (or registers), and partly on the
1009 stack. This includes doubles, long longs, and larger aggregates.
1010 As far as I know, there is no upper limit to the size of aggregates
1011 that will be passed in this way; in other words, the convention of
1012 passing a pointer to a large aggregate instead of a copy is not used.
1014 An exceptional case exists for struct arguments (and possibly other
1015 aggregates such as arrays) if the size is larger than 4 bytes but
1016 not a multiple of 4 bytes. In this case the argument is never split
1017 between the registers and the stack, but instead is copied in its
1018 entirety onto the stack, AND also copied into as many registers as
1019 there is room for. In other words, space in registers permitting,
1020 two copies of the same argument are passed in. As far as I can tell,
1021 only the one on the stack is used, although that may be a function
1022 of the level of compiler optimization. I suspect this is a compiler
1023 bug. Arguments of these odd sizes are left-justified within the
1024 word (as opposed to arguments smaller than 4 bytes, which are
1027 If the function is to return an aggregate type such as a struct, it
1028 is either returned in the normal return value register R0 (if its
1029 size is no greater than one byte), or else the caller must allocate
1030 space into which the callee will copy the return value (if the size
1031 is greater than one byte). In this case, a pointer to the return
1032 value location is passed into the callee in register R2, which does
1033 not displace any of the other arguments passed in via registers R4
1036 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1037 non-scalar (struct, union) elements (even if the elements are
1039 FR0-FR11 for single precision floating point (float)
1040 DR0-DR10 for double precision floating point (double)
1042 If a float is argument number 3 (for instance) and arguments number
1043 1,2, and 4 are integer, the mapping will be:
1044 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1046 If a float is argument number 10 (for instance) and arguments number
1047 1 through 10 are integer, the mapping will be:
1048 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1049 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1050 arg11->stack(16,SP). I.e. there is hole in the stack.
1052 Different rules apply for variable arguments functions, and for functions
1053 for which the prototype is not known. */
1056 sh64_push_dummy_call (struct gdbarch *gdbarch,
1057 struct value *function,
1058 struct regcache *regcache,
1060 int nargs, struct value **args,
1061 CORE_ADDR sp, int struct_return,
1062 CORE_ADDR struct_addr)
1064 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1065 int stack_offset, stack_alloc;
1067 int float_arg_index = 0;
1068 int double_arg_index = 0;
1072 const gdb_byte *val;
1078 memset (fp_args, 0, sizeof (fp_args));
1080 /* First force sp to a 8-byte alignment. */
1081 sp = sh64_frame_align (gdbarch, sp);
1083 /* The "struct return pointer" pseudo-argument has its own dedicated
1087 regcache_cooked_write_unsigned (regcache,
1088 STRUCT_RETURN_REGNUM, struct_addr);
1090 /* Now make sure there's space on the stack. */
1091 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1092 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
1093 sp -= stack_alloc; /* Make room on stack for args. */
1095 /* Now load as many as possible of the first arguments into
1096 registers, and push the rest onto the stack. There are 64 bytes
1097 in eight registers available. Loop thru args from first to last. */
1099 int_argreg = ARG0_REGNUM;
1101 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1103 type = value_type (args[argnum]);
1104 len = TYPE_LENGTH (type);
1105 memset (valbuf, 0, sizeof (valbuf));
1107 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1109 argreg_size = register_size (gdbarch, int_argreg);
1111 if (len < argreg_size)
1113 /* value gets right-justified in the register or stack word. */
1114 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1115 memcpy (valbuf + argreg_size - len,
1116 value_contents (args[argnum]), len);
1118 memcpy (valbuf, value_contents (args[argnum]), len);
1123 val = value_contents (args[argnum]);
1127 if (int_argreg > ARGLAST_REGNUM)
1129 /* Must go on the stack. */
1130 write_memory (sp + stack_offset, val, argreg_size);
1131 stack_offset += 8;/*argreg_size;*/
1133 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1134 That's because some *&^%$ things get passed on the stack
1135 AND in the registers! */
1136 if (int_argreg <= ARGLAST_REGNUM)
1138 /* There's room in a register. */
1139 regval = extract_unsigned_integer (val, argreg_size,
1141 regcache_cooked_write_unsigned (regcache,
1142 int_argreg, regval);
1144 /* Store the value 8 bytes at a time. This means that
1145 things larger than 8 bytes may go partly in registers
1146 and partly on the stack. FIXME: argreg is incremented
1147 before we use its size. */
1155 val = value_contents (args[argnum]);
1158 /* Where is it going to be stored? */
1159 while (fp_args[float_arg_index])
1162 /* Now float_argreg points to the register where it
1163 should be stored. Are we still within the allowed
1165 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1167 /* Goes in FR0...FR11 */
1168 regcache_cooked_write (regcache,
1169 gdbarch_fp0_regnum (gdbarch)
1172 fp_args[float_arg_index] = 1;
1173 /* Skip the corresponding general argument register. */
1178 /* Store it as the integers, 8 bytes at the time, if
1179 necessary spilling on the stack. */
1184 /* Where is it going to be stored? */
1185 while (fp_args[double_arg_index])
1186 double_arg_index += 2;
1187 /* Now double_argreg points to the register
1188 where it should be stored.
1189 Are we still within the allowed register set? */
1190 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1192 /* Goes in DR0...DR10 */
1193 /* The numbering of the DRi registers is consecutive,
1194 i.e. includes odd numbers. */
1195 int double_register_offset = double_arg_index / 2;
1196 int regnum = DR0_REGNUM + double_register_offset;
1197 regcache_cooked_write (regcache, regnum, val);
1198 fp_args[double_arg_index] = 1;
1199 fp_args[double_arg_index + 1] = 1;
1200 /* Skip the corresponding general argument register. */
1205 /* Store it as the integers, 8 bytes at the time, if
1206 necessary spilling on the stack. */
1211 /* Store return address. */
1212 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1214 /* Update stack pointer. */
1215 regcache_cooked_write_unsigned (regcache,
1216 gdbarch_sp_regnum (gdbarch), sp);
1221 /* Find a function's return value in the appropriate registers (in
1222 regbuf), and copy it into valbuf. Extract from an array REGBUF
1223 containing the (raw) register state a function return value of type
1224 TYPE, and copy that, in virtual format, into VALBUF. */
1226 sh64_extract_return_value (struct type *type, struct regcache *regcache,
1229 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1230 int len = TYPE_LENGTH (type);
1232 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1236 /* Return value stored in gdbarch_fp0_regnum. */
1237 regcache_raw_read (regcache,
1238 gdbarch_fp0_regnum (gdbarch), valbuf);
1242 /* return value stored in DR0_REGNUM. */
1246 regcache_cooked_read (regcache, DR0_REGNUM, buf);
1248 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1249 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1252 floatformat_to_doublest (&floatformat_ieee_double_big,
1254 store_typed_floating (valbuf, type, val);
1263 /* Result is in register 2. If smaller than 8 bytes, it is padded
1264 at the most significant end. */
1265 regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf);
1267 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1268 offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM)
1272 memcpy (valbuf, buf + offset, len);
1275 error (_("bad size for return value"));
1279 /* Write into appropriate registers a function return value
1280 of type TYPE, given in virtual format.
1281 If the architecture is sh4 or sh3e, store a function's return value
1282 in the R0 general register or in the FP0 floating point register,
1283 depending on the type of the return value. In all the other cases
1284 the result is stored in r0, left-justified. */
1287 sh64_store_return_value (struct type *type, struct regcache *regcache,
1288 const gdb_byte *valbuf)
1290 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1291 gdb_byte buf[64]; /* more than enough... */
1292 int len = TYPE_LENGTH (type);
1294 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1296 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1297 for (i = 0; i < len; i += 4)
1298 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1299 regcache_raw_write (regcache, regnum++,
1300 valbuf + len - 4 - i);
1302 regcache_raw_write (regcache, regnum++, valbuf + i);
1306 int return_register = DEFAULT_RETURN_REGNUM;
1309 if (len <= register_size (gdbarch, return_register))
1311 /* Pad with zeros. */
1312 memset (buf, 0, register_size (gdbarch, return_register));
1313 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1314 offset = 0; /*register_size (gdbarch,
1315 return_register) - len;*/
1317 offset = register_size (gdbarch, return_register) - len;
1319 memcpy (buf + offset, valbuf, len);
1320 regcache_raw_write (regcache, return_register, buf);
1323 regcache_raw_write (regcache, return_register, valbuf);
1327 static enum return_value_convention
1328 sh64_return_value (struct gdbarch *gdbarch, struct value *function,
1329 struct type *type, struct regcache *regcache,
1330 gdb_byte *readbuf, const gdb_byte *writebuf)
1332 if (sh64_use_struct_convention (type))
1333 return RETURN_VALUE_STRUCT_CONVENTION;
1335 sh64_store_return_value (type, regcache, writebuf);
1337 sh64_extract_return_value (type, regcache, readbuf);
1338 return RETURN_VALUE_REGISTER_CONVENTION;
1343 SH MEDIA MODE (ISA 32)
1344 general registers (64-bit) 0-63
1345 0 r0, r1, r2, r3, r4, r5, r6, r7,
1346 64 r8, r9, r10, r11, r12, r13, r14, r15,
1347 128 r16, r17, r18, r19, r20, r21, r22, r23,
1348 192 r24, r25, r26, r27, r28, r29, r30, r31,
1349 256 r32, r33, r34, r35, r36, r37, r38, r39,
1350 320 r40, r41, r42, r43, r44, r45, r46, r47,
1351 384 r48, r49, r50, r51, r52, r53, r54, r55,
1352 448 r56, r57, r58, r59, r60, r61, r62, r63,
1357 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1360 target registers (64-bit) 68-75
1361 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1363 floating point state control register (32-bit) 76
1366 single precision floating point registers (32-bit) 77-140
1367 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1368 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1369 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1370 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1371 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1372 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1373 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1374 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1376 TOTAL SPACE FOR REGISTERS: 868 bytes
1378 From here on they are all pseudo registers: no memory allocated.
1379 REGISTER_BYTE returns the register byte for the base register.
1381 double precision registers (pseudo) 141-172
1382 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1383 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1384 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1385 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1387 floating point pairs (pseudo) 173-204
1388 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1389 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1390 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1391 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1393 floating point vectors (4 floating point regs) (pseudo) 205-220
1394 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1395 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1397 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1398 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1399 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1401 gbr_c, mach_c, macl_c, pr_c, t_c,
1403 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1404 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1405 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1406 fv0_c, fv4_c, fv8_c, fv12_c
1409 static struct type *
1410 sh64_build_float_register_type (struct gdbarch *gdbarch, int high)
1412 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
1416 /* Return the GDB type object for the "standard" data type
1417 of data in register REG_NR. */
1418 static struct type *
1419 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
1421 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
1422 && reg_nr <= FP_LAST_REGNUM)
1423 || (reg_nr >= FP0_C_REGNUM
1424 && reg_nr <= FP_LAST_C_REGNUM))
1425 return builtin_type (gdbarch)->builtin_float;
1426 else if ((reg_nr >= DR0_REGNUM
1427 && reg_nr <= DR_LAST_REGNUM)
1428 || (reg_nr >= DR0_C_REGNUM
1429 && reg_nr <= DR_LAST_C_REGNUM))
1430 return builtin_type (gdbarch)->builtin_double;
1431 else if (reg_nr >= FPP0_REGNUM
1432 && reg_nr <= FPP_LAST_REGNUM)
1433 return sh64_build_float_register_type (gdbarch, 1);
1434 else if ((reg_nr >= FV0_REGNUM
1435 && reg_nr <= FV_LAST_REGNUM)
1436 ||(reg_nr >= FV0_C_REGNUM
1437 && reg_nr <= FV_LAST_C_REGNUM))
1438 return sh64_build_float_register_type (gdbarch, 3);
1439 else if (reg_nr == FPSCR_REGNUM)
1440 return builtin_type (gdbarch)->builtin_int;
1441 else if (reg_nr >= R0_C_REGNUM
1442 && reg_nr < FP0_C_REGNUM)
1443 return builtin_type (gdbarch)->builtin_int;
1445 return builtin_type (gdbarch)->builtin_long_long;
1449 sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum,
1450 struct type *type, gdb_byte *from, gdb_byte *to)
1452 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1454 /* It is a no-op. */
1455 memcpy (to, from, register_size (gdbarch, regnum));
1459 if ((regnum >= DR0_REGNUM
1460 && regnum <= DR_LAST_REGNUM)
1461 || (regnum >= DR0_C_REGNUM
1462 && regnum <= DR_LAST_C_REGNUM))
1465 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1467 store_typed_floating (to, type, val);
1470 error (_("sh64_register_convert_to_virtual "
1471 "called with non DR register number"));
1475 sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type,
1476 int regnum, const void *from, void *to)
1478 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1480 /* It is a no-op. */
1481 memcpy (to, from, register_size (gdbarch, regnum));
1485 if ((regnum >= DR0_REGNUM
1486 && regnum <= DR_LAST_REGNUM)
1487 || (regnum >= DR0_C_REGNUM
1488 && regnum <= DR_LAST_C_REGNUM))
1490 DOUBLEST val = extract_typed_floating (from, type);
1491 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1495 error (_("sh64_register_convert_to_raw called "
1496 "with non DR register number"));
1499 /* Concatenate PORTIONS contiguous raw registers starting at
1500 BASE_REGNUM into BUFFER. */
1502 static enum register_status
1503 pseudo_register_read_portions (struct gdbarch *gdbarch,
1504 struct regcache *regcache,
1506 int base_regnum, gdb_byte *buffer)
1510 for (portion = 0; portion < portions; portion++)
1512 enum register_status status;
1515 b = buffer + register_size (gdbarch, base_regnum) * portion;
1516 status = regcache_raw_read (regcache, base_regnum + portion, b);
1517 if (status != REG_VALID)
1524 static enum register_status
1525 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1526 int reg_nr, gdb_byte *buffer)
1528 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1531 gdb_byte temp_buffer[MAX_REGISTER_SIZE];
1532 enum register_status status;
1534 if (reg_nr >= DR0_REGNUM
1535 && reg_nr <= DR_LAST_REGNUM)
1537 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1539 /* Build the value in the provided buffer. */
1540 /* DR regs are double precision registers obtained by
1541 concatenating 2 single precision floating point registers. */
1542 status = pseudo_register_read_portions (gdbarch, regcache,
1543 2, base_regnum, temp_buffer);
1544 if (status == REG_VALID)
1546 /* We must pay attention to the endianness. */
1547 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1548 register_type (gdbarch, reg_nr),
1549 temp_buffer, buffer);
1555 else if (reg_nr >= FPP0_REGNUM
1556 && reg_nr <= FPP_LAST_REGNUM)
1558 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1560 /* Build the value in the provided buffer. */
1561 /* FPP regs are pairs of single precision registers obtained by
1562 concatenating 2 single precision floating point registers. */
1563 return pseudo_register_read_portions (gdbarch, regcache,
1564 2, base_regnum, buffer);
1567 else if (reg_nr >= FV0_REGNUM
1568 && reg_nr <= FV_LAST_REGNUM)
1570 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1572 /* Build the value in the provided buffer. */
1573 /* FV regs are vectors of single precision registers obtained by
1574 concatenating 4 single precision floating point registers. */
1575 return pseudo_register_read_portions (gdbarch, regcache,
1576 4, base_regnum, buffer);
1579 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1580 else if (reg_nr >= R0_C_REGNUM
1581 && reg_nr <= T_C_REGNUM)
1583 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1585 /* Build the value in the provided buffer. */
1586 status = regcache_raw_read (regcache, base_regnum, temp_buffer);
1587 if (status != REG_VALID)
1589 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1592 temp_buffer + offset, 4); /* get LOWER 32 bits only???? */
1596 else if (reg_nr >= FP0_C_REGNUM
1597 && reg_nr <= FP_LAST_C_REGNUM)
1599 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1601 /* Build the value in the provided buffer. */
1602 /* Floating point registers map 1-1 to the media fp regs,
1603 they have the same size and endianness. */
1604 return regcache_raw_read (regcache, base_regnum, buffer);
1607 else if (reg_nr >= DR0_C_REGNUM
1608 && reg_nr <= DR_LAST_C_REGNUM)
1610 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1612 /* DR_C regs are double precision registers obtained by
1613 concatenating 2 single precision floating point registers. */
1614 status = pseudo_register_read_portions (gdbarch, regcache,
1615 2, base_regnum, temp_buffer);
1616 if (status == REG_VALID)
1618 /* We must pay attention to the endianness. */
1619 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1620 register_type (gdbarch, reg_nr),
1621 temp_buffer, buffer);
1626 else if (reg_nr >= FV0_C_REGNUM
1627 && reg_nr <= FV_LAST_C_REGNUM)
1629 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1631 /* Build the value in the provided buffer. */
1632 /* FV_C regs are vectors of single precision registers obtained by
1633 concatenating 4 single precision floating point registers. */
1634 return pseudo_register_read_portions (gdbarch, regcache,
1635 4, base_regnum, buffer);
1638 else if (reg_nr == FPSCR_C_REGNUM)
1640 int fpscr_base_regnum;
1642 unsigned int fpscr_value;
1643 unsigned int sr_value;
1644 unsigned int fpscr_c_value;
1645 unsigned int fpscr_c_part1_value;
1646 unsigned int fpscr_c_part2_value;
1648 fpscr_base_regnum = FPSCR_REGNUM;
1649 sr_base_regnum = SR_REGNUM;
1651 /* Build the value in the provided buffer. */
1652 /* FPSCR_C is a very weird register that contains sparse bits
1653 from the FPSCR and the SR architectural registers.
1660 2-17 Bit 2-18 of FPSCR
1661 18-20 Bits 12,13,14 of SR
1665 /* Get FPSCR into a local buffer. */
1666 status = regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1667 if (status != REG_VALID)
1669 /* Get value as an int. */
1670 fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1671 /* Get SR into a local buffer */
1672 status = regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1673 if (status != REG_VALID)
1675 /* Get value as an int. */
1676 sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1677 /* Build the new value. */
1678 fpscr_c_part1_value = fpscr_value & 0x3fffd;
1679 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
1680 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
1681 /* Store that in out buffer!!! */
1682 store_unsigned_integer (buffer, 4, byte_order, fpscr_c_value);
1683 /* FIXME There is surely an endianness gotcha here. */
1688 else if (reg_nr == FPUL_C_REGNUM)
1690 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1692 /* FPUL_C register is floating point register 32,
1693 same size, same endianness. */
1694 return regcache_raw_read (regcache, base_regnum, buffer);
1697 gdb_assert_not_reached ("invalid pseudo register number");
1701 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1702 int reg_nr, const gdb_byte *buffer)
1704 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1705 int base_regnum, portion;
1707 gdb_byte temp_buffer[MAX_REGISTER_SIZE];
1709 if (reg_nr >= DR0_REGNUM
1710 && reg_nr <= DR_LAST_REGNUM)
1712 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1713 /* We must pay attention to the endianness. */
1714 sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr),
1716 buffer, temp_buffer);
1718 /* Write the real regs for which this one is an alias. */
1719 for (portion = 0; portion < 2; portion++)
1720 regcache_raw_write (regcache, base_regnum + portion,
1722 + register_size (gdbarch,
1723 base_regnum) * portion));
1726 else if (reg_nr >= FPP0_REGNUM
1727 && reg_nr <= FPP_LAST_REGNUM)
1729 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1731 /* Write the real regs for which this one is an alias. */
1732 for (portion = 0; portion < 2; portion++)
1733 regcache_raw_write (regcache, base_regnum + portion,
1734 (buffer + register_size (gdbarch,
1735 base_regnum) * portion));
1738 else if (reg_nr >= FV0_REGNUM
1739 && reg_nr <= FV_LAST_REGNUM)
1741 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1743 /* Write the real regs for which this one is an alias. */
1744 for (portion = 0; portion < 4; portion++)
1745 regcache_raw_write (regcache, base_regnum + portion,
1746 (buffer + register_size (gdbarch,
1747 base_regnum) * portion));
1750 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1751 register but only 4 bytes of it. */
1752 else if (reg_nr >= R0_C_REGNUM
1753 && reg_nr <= T_C_REGNUM)
1755 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1756 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1757 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1761 /* Let's read the value of the base register into a temporary
1762 buffer, so that overwriting the last four bytes with the new
1763 value of the pseudo will leave the upper 4 bytes unchanged. */
1764 regcache_raw_read (regcache, base_regnum, temp_buffer);
1765 /* Write as an 8 byte quantity. */
1766 memcpy (temp_buffer + offset, buffer, 4);
1767 regcache_raw_write (regcache, base_regnum, temp_buffer);
1770 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1771 registers. Both are 4 bytes. */
1772 else if (reg_nr >= FP0_C_REGNUM
1773 && reg_nr <= FP_LAST_C_REGNUM)
1775 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1776 regcache_raw_write (regcache, base_regnum, buffer);
1779 else if (reg_nr >= DR0_C_REGNUM
1780 && reg_nr <= DR_LAST_C_REGNUM)
1782 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1783 for (portion = 0; portion < 2; portion++)
1785 /* We must pay attention to the endianness. */
1786 sh64_register_convert_to_raw (gdbarch,
1787 register_type (gdbarch, reg_nr),
1789 buffer, temp_buffer);
1791 regcache_raw_write (regcache, base_regnum + portion,
1793 + register_size (gdbarch,
1794 base_regnum) * portion));
1798 else if (reg_nr >= FV0_C_REGNUM
1799 && reg_nr <= FV_LAST_C_REGNUM)
1801 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1803 for (portion = 0; portion < 4; portion++)
1805 regcache_raw_write (regcache, base_regnum + portion,
1807 + register_size (gdbarch,
1808 base_regnum) * portion));
1812 else if (reg_nr == FPSCR_C_REGNUM)
1814 int fpscr_base_regnum;
1816 unsigned int fpscr_value;
1817 unsigned int sr_value;
1818 unsigned int old_fpscr_value;
1819 unsigned int old_sr_value;
1820 unsigned int fpscr_c_value;
1821 unsigned int fpscr_mask;
1822 unsigned int sr_mask;
1824 fpscr_base_regnum = FPSCR_REGNUM;
1825 sr_base_regnum = SR_REGNUM;
1827 /* FPSCR_C is a very weird register that contains sparse bits
1828 from the FPSCR and the SR architectural registers.
1835 2-17 Bit 2-18 of FPSCR
1836 18-20 Bits 12,13,14 of SR
1840 /* Get value as an int. */
1841 fpscr_c_value = extract_unsigned_integer (buffer, 4, byte_order);
1843 /* Build the new values. */
1844 fpscr_mask = 0x0003fffd;
1845 sr_mask = 0x001c0000;
1847 fpscr_value = fpscr_c_value & fpscr_mask;
1848 sr_value = (fpscr_value & sr_mask) >> 6;
1850 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
1851 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1852 old_fpscr_value &= 0xfffc0002;
1853 fpscr_value |= old_fpscr_value;
1854 store_unsigned_integer (temp_buffer, 4, byte_order, fpscr_value);
1855 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
1857 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
1858 old_sr_value = extract_unsigned_integer (temp_buffer, 4, byte_order);
1859 old_sr_value &= 0xffff8fff;
1860 sr_value |= old_sr_value;
1861 store_unsigned_integer (temp_buffer, 4, byte_order, sr_value);
1862 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
1865 else if (reg_nr == FPUL_C_REGNUM)
1867 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1868 regcache_raw_write (regcache, base_regnum, buffer);
1872 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1873 shmedia REGISTERS. */
1874 /* Control registers, compact mode. */
1876 sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame,
1879 switch (cr_c_regnum)
1882 fprintf_filtered (file, "pc_c\t0x%08x\n",
1883 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1886 fprintf_filtered (file, "gbr_c\t0x%08x\n",
1887 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1890 fprintf_filtered (file, "mach_c\t0x%08x\n",
1891 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1894 fprintf_filtered (file, "macl_c\t0x%08x\n",
1895 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1898 fprintf_filtered (file, "pr_c\t0x%08x\n",
1899 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1902 fprintf_filtered (file, "t_c\t0x%08x\n",
1903 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1905 case FPSCR_C_REGNUM:
1906 fprintf_filtered (file, "fpscr_c\t0x%08x\n",
1907 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1910 fprintf_filtered (file, "fpul_c\t0x%08x\n",
1911 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1917 sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file,
1918 struct frame_info *frame, int regnum)
1919 { /* Do values for FP (float) regs. */
1920 unsigned char *raw_buffer;
1921 double flt; /* Double extracted from raw hex data. */
1924 /* Allocate space for the float. */
1925 raw_buffer = (unsigned char *)
1926 alloca (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)));
1928 /* Get the data in raw format. */
1929 if (!deprecated_frame_register_read (frame, regnum, raw_buffer))
1930 error (_("can't read register %d (%s)"),
1931 regnum, gdbarch_register_name (gdbarch, regnum));
1933 /* Get the register as a number. */
1934 flt = unpack_double (builtin_type (gdbarch)->builtin_float,
1937 /* Print the name and some spaces. */
1938 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
1939 print_spaces_filtered (15 - strlen (gdbarch_register_name
1940 (gdbarch, regnum)), file);
1942 /* Print the value. */
1944 fprintf_filtered (file, "<invalid float>");
1946 fprintf_filtered (file, "%-10.9g", flt);
1948 /* Print the fp register as hex. */
1949 fprintf_filtered (file, "\t(raw ");
1950 print_hex_chars (file, raw_buffer,
1951 register_size (gdbarch, regnum),
1952 gdbarch_byte_order (gdbarch));
1953 fprintf_filtered (file, ")");
1954 fprintf_filtered (file, "\n");
1958 sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1959 struct frame_info *frame, int regnum)
1961 /* All the sh64-compact mode registers are pseudo registers. */
1963 if (regnum < gdbarch_num_regs (gdbarch)
1964 || regnum >= gdbarch_num_regs (gdbarch)
1965 + NUM_PSEUDO_REGS_SH_MEDIA
1966 + NUM_PSEUDO_REGS_SH_COMPACT)
1967 internal_error (__FILE__, __LINE__,
1968 _("Invalid pseudo register number %d\n"), regnum);
1970 else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM))
1972 int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum);
1973 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM,
1974 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1975 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
1978 else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM))
1980 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
1981 fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM,
1982 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1983 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
1986 else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM))
1988 int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum);
1989 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1990 regnum - FV0_REGNUM,
1991 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1992 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
1993 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
1994 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
1997 else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM))
1999 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2000 fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2001 regnum - FV0_C_REGNUM,
2002 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2003 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
2004 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
2005 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2008 else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM)
2010 int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum);
2011 fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM,
2012 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2013 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2016 else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM)
2018 int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2019 fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM,
2020 (unsigned) get_frame_register_unsigned (frame, c_regnum));
2022 else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM)
2023 /* This should work also for pseudoregs. */
2024 sh64_do_fp_register (gdbarch, file, frame, regnum);
2025 else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM)
2026 sh64_do_cr_c_register_info (file, frame, regnum);
2030 sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file,
2031 struct frame_info *frame, int regnum)
2033 struct value_print_options opts;
2036 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
2037 print_spaces_filtered (15 - strlen (gdbarch_register_name
2038 (gdbarch, regnum)), file);
2040 /* Get the data in raw format. */
2041 val = get_frame_register_value (frame, regnum);
2042 if (value_optimized_out (val) || !value_entirely_available (val))
2044 fprintf_filtered (file, "*value not available*\n");
2048 get_formatted_print_options (&opts, 'x');
2050 val_print (register_type (gdbarch, regnum),
2052 file, 0, val, &opts, current_language);
2053 fprintf_filtered (file, "\t");
2054 get_formatted_print_options (&opts, 0);
2056 val_print (register_type (gdbarch, regnum),
2058 file, 0, val, &opts, current_language);
2059 fprintf_filtered (file, "\n");
2063 sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file,
2064 struct frame_info *frame, int regnum)
2066 if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch)
2067 + gdbarch_num_pseudo_regs (gdbarch))
2068 internal_error (__FILE__, __LINE__,
2069 _("Invalid register number %d\n"), regnum);
2071 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
2073 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2074 sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */
2076 sh64_do_register (gdbarch, file, frame, regnum);
2079 else if (regnum < gdbarch_num_regs (gdbarch)
2080 + gdbarch_num_pseudo_regs (gdbarch))
2081 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2085 sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2086 struct frame_info *frame, int regnum,
2089 if (regnum != -1) /* Do one specified register. */
2091 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2092 error (_("Not a valid register for the current processor type"));
2094 sh64_print_register (gdbarch, file, frame, regnum);
2097 /* Do all (or most) registers. */
2100 while (regnum < gdbarch_num_regs (gdbarch))
2102 /* If the register name is empty, it is undefined for this
2103 processor, so don't display anything. */
2104 if (gdbarch_register_name (gdbarch, regnum) == NULL
2105 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
2111 if (TYPE_CODE (register_type (gdbarch, regnum))
2116 /* true for "INFO ALL-REGISTERS" command. */
2117 sh64_do_fp_register (gdbarch, file, frame, regnum);
2121 regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch);
2126 sh64_do_register (gdbarch, file, frame, regnum);
2132 while (regnum < gdbarch_num_regs (gdbarch)
2133 + gdbarch_num_pseudo_regs (gdbarch))
2135 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2142 sh64_compact_print_registers_info (struct gdbarch *gdbarch,
2143 struct ui_file *file,
2144 struct frame_info *frame, int regnum,
2147 if (regnum != -1) /* Do one specified register. */
2149 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2150 error (_("Not a valid register for the current processor type"));
2152 if (regnum >= 0 && regnum < R0_C_REGNUM)
2153 error (_("Not a valid register for the current processor mode."));
2155 sh64_print_register (gdbarch, file, frame, regnum);
2158 /* Do all compact registers. */
2160 regnum = R0_C_REGNUM;
2161 while (regnum < gdbarch_num_regs (gdbarch)
2162 + gdbarch_num_pseudo_regs (gdbarch))
2164 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2171 sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2172 struct frame_info *frame, int regnum, int fpregs)
2174 if (pc_is_isa32 (get_frame_pc (frame)))
2175 sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2177 sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2180 static struct sh64_frame_cache *
2181 sh64_alloc_frame_cache (void)
2183 struct sh64_frame_cache *cache;
2186 cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache);
2190 cache->saved_sp = 0;
2191 cache->sp_offset = 0;
2194 /* Frameless until proven otherwise. */
2197 /* Saved registers. We initialize these to -1 since zero is a valid
2198 offset (that's where fp is supposed to be stored). */
2199 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2201 cache->saved_regs[i] = -1;
2207 static struct sh64_frame_cache *
2208 sh64_frame_cache (struct frame_info *this_frame, void **this_cache)
2210 struct gdbarch *gdbarch;
2211 struct sh64_frame_cache *cache;
2212 CORE_ADDR current_pc;
2216 return (struct sh64_frame_cache *) *this_cache;
2218 gdbarch = get_frame_arch (this_frame);
2219 cache = sh64_alloc_frame_cache ();
2220 *this_cache = cache;
2222 current_pc = get_frame_pc (this_frame);
2223 cache->media_mode = pc_is_isa32 (current_pc);
2225 /* In principle, for normal frames, fp holds the frame pointer,
2226 which holds the base address for the current stack frame.
2227 However, for functions that don't need it, the frame pointer is
2228 optional. For these "frameless" functions the frame pointer is
2229 actually the frame pointer of the calling frame. */
2230 cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM);
2231 if (cache->base == 0)
2234 cache->pc = get_frame_func (this_frame);
2236 sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc);
2238 if (!cache->uses_fp)
2240 /* We didn't find a valid frame, which means that CACHE->base
2241 currently holds the frame pointer for our calling frame. If
2242 we're at the start of a function, or somewhere half-way its
2243 prologue, the function's frame probably hasn't been fully
2244 setup yet. Try to reconstruct the base address for the stack
2245 frame by looking at the stack pointer. For truly "frameless"
2246 functions this might work too. */
2247 cache->base = get_frame_register_unsigned
2248 (this_frame, gdbarch_sp_regnum (gdbarch));
2251 /* Now that we have the base address for the stack frame we can
2252 calculate the value of sp in the calling frame. */
2253 cache->saved_sp = cache->base + cache->sp_offset;
2255 /* Adjust all the saved registers such that they contain addresses
2256 instead of offsets. */
2257 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2258 if (cache->saved_regs[i] != -1)
2259 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i];
2264 static struct value *
2265 sh64_frame_prev_register (struct frame_info *this_frame,
2266 void **this_cache, int regnum)
2268 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2269 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2270 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2272 gdb_assert (regnum >= 0);
2274 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2275 frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2277 /* The PC of the previous frame is stored in the PR register of
2278 the current frame. Frob regnum so that we pull the value from
2279 the correct place. */
2280 if (regnum == gdbarch_pc_regnum (gdbarch))
2283 if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1)
2285 if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32
2286 && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM))
2289 val = read_memory_unsigned_integer (cache->saved_regs[regnum],
2291 return frame_unwind_got_constant (this_frame, regnum, val);
2294 return frame_unwind_got_memory (this_frame, regnum,
2295 cache->saved_regs[regnum]);
2298 return frame_unwind_got_register (this_frame, regnum, regnum);
2302 sh64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2303 struct frame_id *this_id)
2305 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2307 /* This marks the outermost frame. */
2308 if (cache->base == 0)
2311 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2314 static const struct frame_unwind sh64_frame_unwind = {
2316 default_frame_unwind_stop_reason,
2318 sh64_frame_prev_register,
2320 default_frame_sniffer
2324 sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2326 return frame_unwind_register_unsigned (next_frame,
2327 gdbarch_sp_regnum (gdbarch));
2331 sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2333 return frame_unwind_register_unsigned (next_frame,
2334 gdbarch_pc_regnum (gdbarch));
2337 static struct frame_id
2338 sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2340 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2341 gdbarch_sp_regnum (gdbarch));
2342 return frame_id_build (sp, get_frame_pc (this_frame));
2346 sh64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2348 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2353 static const struct frame_base sh64_frame_base = {
2355 sh64_frame_base_address,
2356 sh64_frame_base_address,
2357 sh64_frame_base_address
2362 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2364 struct gdbarch *gdbarch;
2365 struct gdbarch_tdep *tdep;
2367 /* If there is already a candidate, use it. */
2368 arches = gdbarch_list_lookup_by_info (arches, &info);
2370 return arches->gdbarch;
2372 /* None found, create a new architecture from the information
2374 tdep = XNEW (struct gdbarch_tdep);
2375 gdbarch = gdbarch_alloc (&info, tdep);
2377 /* Determine the ABI */
2378 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2380 /* If the ABI is the 64-bit one, it can only be sh-media. */
2381 tdep->sh_abi = SH_ABI_64;
2382 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2383 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2387 /* If the ABI is the 32-bit one it could be either media or
2389 tdep->sh_abi = SH_ABI_32;
2390 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2391 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2394 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2395 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2396 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2397 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2398 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2399 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2400 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2402 /* The number of real registers is the same whether we are in
2403 ISA16(compact) or ISA32(media). */
2404 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2405 set_gdbarch_sp_regnum (gdbarch, 15);
2406 set_gdbarch_pc_regnum (gdbarch, 64);
2407 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2408 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA
2409 + NUM_PSEUDO_REGS_SH_COMPACT);
2411 set_gdbarch_register_name (gdbarch, sh64_register_name);
2412 set_gdbarch_register_type (gdbarch, sh64_register_type);
2414 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2415 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2417 set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh64_breakpoint_kind_from_pc);
2418 set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh64_sw_breakpoint_from_kind);
2420 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2421 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2423 set_gdbarch_return_value (gdbarch, sh64_return_value);
2425 set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue);
2426 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2428 set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call);
2430 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2432 set_gdbarch_frame_align (gdbarch, sh64_frame_align);
2433 set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp);
2434 set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc);
2435 set_gdbarch_dummy_id (gdbarch, sh64_dummy_id);
2436 frame_base_set_default (gdbarch, &sh64_frame_base);
2438 set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info);
2440 set_gdbarch_elf_make_msymbol_special (gdbarch,
2441 sh64_elf_make_msymbol_special);
2443 /* Hook in ABI-specific overrides, if they have been registered. */
2444 gdbarch_init_osabi (info, gdbarch);
2446 dwarf2_append_unwinders (gdbarch);
2447 frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind);