1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
37 #include "gdb_string.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
45 #include "solib-svr4.h"
49 /* registers numbers shared with the simulator */
50 #include "gdb/sim-sh.h"
52 /* Information that is dependent on the processor variant. */
65 /* Registers of SH5 */
69 DEFAULT_RETURN_REGNUM = 2,
70 STRUCT_RETURN_REGNUM = 2,
73 FLOAT_ARGLAST_REGNUM = 11,
78 /* FPP stands for Floating Point Pair, to avoid confusion with
79 GDB's FP0_REGNUM, which is the number of the first Floating
80 point register. Unfortunately on the sh5, the floating point
81 registers are called FR, and the floating point pairs are called FP. */
83 FPP_LAST_REGNUM = 204,
87 R_LAST_C_REGNUM = 236,
97 FP_LAST_C_REGNUM = 260,
99 DR_LAST_C_REGNUM = 268,
101 FV_LAST_C_REGNUM = 272,
102 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
103 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
104 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
105 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
106 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
110 /* Define other aspects of the stack frame.
111 we keep a copy of the worked out return pc lying around, since it
112 is a useful bit of info */
114 struct frame_extra_info
122 sh_sh64_register_name (int reg_nr)
124 static char *register_names[] =
126 /* SH MEDIA MODE (ISA 32) */
127 /* general registers (64-bit) 0-63 */
128 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
129 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
130 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
131 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
132 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
133 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
134 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
135 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
140 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
143 /* target registers (64-bit) 68-75*/
144 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
146 /* floating point state control register (32-bit) 76 */
149 /* single precision floating point registers (32-bit) 77-140*/
150 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
151 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
152 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
153 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
154 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
155 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
156 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
157 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
159 /* double precision registers (pseudo) 141-172 */
160 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
161 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
162 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
163 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
165 /* floating point pairs (pseudo) 173-204*/
166 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
167 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
168 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
169 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
171 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
172 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
173 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
175 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
176 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
177 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
179 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
181 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
182 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
183 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
184 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
185 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
190 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
192 return register_names[reg_nr];
195 #define NUM_PSEUDO_REGS_SH_MEDIA 80
196 #define NUM_PSEUDO_REGS_SH_COMPACT 51
198 /* Macros and functions for setting and testing a bit in a minimal
199 symbol that marks it as 32-bit function. The MSB of the minimal
200 symbol's "info" field is used for this purpose.
202 ELF_MAKE_MSYMBOL_SPECIAL
203 tests whether an ELF symbol is "special", i.e. refers
204 to a 32-bit function, and sets a "special" bit in a
205 minimal symbol to mark it as a 32-bit function
206 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
208 #define MSYMBOL_IS_SPECIAL(msym) \
209 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
212 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
217 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
219 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
220 SYMBOL_VALUE_ADDRESS (msym) |= 1;
224 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
225 are some macros to test, set, or clear bit 0 of addresses. */
226 #define IS_ISA32_ADDR(addr) ((addr) & 1)
227 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
228 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
231 pc_is_isa32 (bfd_vma memaddr)
233 struct minimal_symbol *sym;
235 /* If bit 0 of the address is set, assume this is a
236 ISA32 (shmedia) address. */
237 if (IS_ISA32_ADDR (memaddr))
240 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
241 the high bit of the info field. Use this to decide if the function is
243 sym = lookup_minimal_symbol_by_pc (memaddr);
245 return MSYMBOL_IS_SPECIAL (sym);
250 static const unsigned char *
251 sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
253 /* The BRK instruction for shmedia is
254 01101111 11110101 11111111 11110000
255 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
256 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
258 /* The BRK instruction for shcompact is
260 which translates in big endian mode to 0x0, 0x3b
261 and in little endian mode to 0x3b, 0x0*/
263 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
265 if (pc_is_isa32 (*pcptr))
267 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
268 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
269 *lenptr = sizeof (big_breakpoint_media);
270 return big_breakpoint_media;
274 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
275 *lenptr = sizeof (big_breakpoint_compact);
276 return big_breakpoint_compact;
281 if (pc_is_isa32 (*pcptr))
283 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
284 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
285 *lenptr = sizeof (little_breakpoint_media);
286 return little_breakpoint_media;
290 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
291 *lenptr = sizeof (little_breakpoint_compact);
292 return little_breakpoint_compact;
297 /* Prologue looks like
298 [mov.l <regs>,@-r15]...
303 Actually it can be more complicated than this. For instance, with
321 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
322 with l=1 and n = 18 0110101111110001010010100aaa0000 */
323 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
325 /* STS.L PR,@-r0 0100000000100010
326 r0-4-->r0, PR-->(r0) */
327 #define IS_STS_R0(x) ((x) == 0x4022)
329 /* STS PR, Rm 0000mmmm00101010
331 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
333 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
335 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
337 /* MOV.L R14,@(disp,r15) 000111111110dddd
338 R14-->(dispx4+r15) */
339 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
341 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
342 R18-->(dispx8+R14) */
343 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
345 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
346 R18-->(dispx8+R15) */
347 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
349 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
350 R18-->(dispx4+R15) */
351 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
353 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
354 R14-->(dispx8+R15) */
355 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
357 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
358 R14-->(dispx4+R15) */
359 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
361 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
363 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
365 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
367 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
369 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
371 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
373 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
375 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
377 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
379 /* MOV #imm, R0 1110 0000 ssss ssss
381 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
383 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
384 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
386 /* ADD r15,r0 0011 0000 1111 1100
388 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
390 /* MOV.L R14 @-R0 0010 0000 1110 0110
391 R14-->(R0-4), R0-4-->R0 */
392 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
394 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
395 where Rm is one of r2-r9 which are the argument registers. */
396 /* FIXME: Recognize the float and double register moves too! */
397 #define IS_MEDIA_IND_ARG_MOV(x) \
398 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
400 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
401 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
402 where Rm is one of r2-r9 which are the argument registers. */
403 #define IS_MEDIA_ARG_MOV(x) \
404 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
405 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
407 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
408 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
409 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
410 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
411 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
412 #define IS_MEDIA_MOV_TO_R14(x) \
413 ((((x) & 0xfffffc0f) == 0xa0e00000) \
414 || (((x) & 0xfffffc0f) == 0xa4e00000) \
415 || (((x) & 0xfffffc0f) == 0xa8e00000) \
416 || (((x) & 0xfffffc0f) == 0xb4e00000) \
417 || (((x) & 0xfffffc0f) == 0xbce00000))
419 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
421 #define IS_COMPACT_IND_ARG_MOV(x) \
422 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
424 /* compact direct arg move!
425 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
426 #define IS_COMPACT_ARG_MOV(x) \
427 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
429 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
430 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
431 #define IS_COMPACT_MOV_TO_R14(x) \
432 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
434 #define IS_JSR_R0(x) ((x) == 0x400b)
435 #define IS_NOP(x) ((x) == 0x0009)
438 /* MOV r15,r14 0110111011110011
440 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
442 /* ADD #imm,r15 01111111iiiiiiii
444 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
446 /* Skip any prologue before the guts of a function */
448 /* Skip the prologue using the debug information. If this fails we'll
449 fall back on the 'guess' method below. */
451 after_prologue (CORE_ADDR pc)
453 struct symtab_and_line sal;
454 CORE_ADDR func_addr, func_end;
456 /* If we can not find the symbol in the partial symbol table, then
457 there is no hope we can determine the function's start address
459 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
462 /* Get the line associated with FUNC_ADDR. */
463 sal = find_pc_line (func_addr, 0);
465 /* There are only two cases to consider. First, the end of the source line
466 is within the function bounds. In that case we return the end of the
467 source line. Second is the end of the source line extends beyond the
468 bounds of the current function. We need to use the slow code to
469 examine instructions in that case. */
470 if (sal.end < func_end)
477 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
481 int insn_size = (media_mode ? 4 : 2);
483 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
487 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
489 if (IS_MEDIA_IND_ARG_MOV (w))
491 /* This must be followed by a store to r14, so the argument
492 is where the debug info says it is. This can happen after
493 the SP has been saved, unfortunately. */
495 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
498 if (IS_MEDIA_MOV_TO_R14 (next_insn))
501 else if (IS_MEDIA_ARG_MOV (w))
503 /* These instructions store directly the argument in r14. */
511 w = read_memory_integer (here, insn_size);
514 if (IS_COMPACT_IND_ARG_MOV (w))
516 /* This must be followed by a store to r14, so the argument
517 is where the debug info says it is. This can happen after
518 the SP has been saved, unfortunately. */
520 int next_insn = 0xffff & read_memory_integer (here, insn_size);
522 if (IS_COMPACT_MOV_TO_R14 (next_insn))
525 else if (IS_COMPACT_ARG_MOV (w))
527 /* These instructions store directly the argument in r14. */
530 else if (IS_MOVL_R0 (w))
532 /* There is a function that gcc calls to get the arguments
533 passed correctly to the function. Only after this
534 function call the arguments will be found at the place
535 where they are supposed to be. This happens in case the
536 argument has to be stored into a 64-bit register (for
537 instance doubles, long longs). SHcompact doesn't have
538 access to the full 64-bits, so we store the register in
539 stack slot and store the address of the stack slot in
540 the register, then do a call through a wrapper that
541 loads the memory value into the register. A SHcompact
542 callee calls an argument decoder
543 (GCC_shcompact_incoming_args) that stores the 64-bit
544 value in a stack slot and stores the address of the
545 stack slot in the register. GCC thinks the argument is
546 just passed by transparent reference, but this is only
547 true after the argument decoder is called. Such a call
548 needs to be considered part of the prologue. */
550 /* This must be followed by a JSR @r0 instruction and by
551 a NOP instruction. After these, the prologue is over! */
553 int next_insn = 0xffff & read_memory_integer (here, insn_size);
555 if (IS_JSR_R0 (next_insn))
557 next_insn = 0xffff & read_memory_integer (here, insn_size);
560 if (IS_NOP (next_insn))
573 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
583 if (pc_is_isa32 (start_pc) == 0)
589 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
594 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
596 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
597 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
598 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
602 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
610 /* Don't bail out yet, we may have arguments stored in
611 registers here, according to the debug info, so that
612 gdb can print the frames correctly. */
613 start_pc = look_for_args_moves (here - insn_size, media_mode);
619 int w = 0xffff & read_memory_integer (here, insn_size);
622 if (IS_STS_R0 (w) || IS_STS_PR (w)
623 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
624 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
628 else if (IS_MOV_SP_FP (w))
636 /* Don't bail out yet, we may have arguments stored in
637 registers here, according to the debug info, so that
638 gdb can print the frames correctly. */
639 start_pc = look_for_args_moves (here - insn_size, media_mode);
649 sh_skip_prologue (CORE_ADDR pc)
651 CORE_ADDR post_prologue_pc;
653 /* See if we can determine the end of the prologue via the symbol table.
654 If so, then return either PC, or the PC after the prologue, whichever
656 post_prologue_pc = after_prologue (pc);
658 /* If after_prologue returned a useful address, then use it. Else
659 fall back on the instruction skipping code. */
660 if (post_prologue_pc != 0)
661 return max (pc, post_prologue_pc);
663 return sh64_skip_prologue_hard_way (pc);
666 /* Immediately after a function call, return the saved pc.
667 Can't always go through the frames for this because on some machines
668 the new frame is not set up until the new function executes
671 The return address is the value saved in the PR register + 4 */
673 sh_saved_pc_after_call (struct frame_info *frame)
675 return (ADDR_BITS_REMOVE (read_register (PR_REGNUM)));
678 /* Should call_function allocate stack space for a struct return? */
680 sh64_use_struct_convention (int gcc_p, struct type *type)
682 return (TYPE_LENGTH (type) > 8);
685 /* Store the address of the place in which to copy the structure the
686 subroutine will return. This is called from call_function.
688 We store structs through a pointer passed in R2 */
690 sh64_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
692 write_register (STRUCT_RETURN_REGNUM, (addr));
695 /* Disassemble an instruction. */
697 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
699 info->endian = TARGET_BYTE_ORDER;
700 return print_insn_sh (memaddr, info);
703 /* Given a register number RN as it appears in an assembly
704 instruction, find the corresponding register number in the GDB
707 translate_insn_rn (int rn, int media_mode)
709 /* FIXME: this assumes that the number rn is for a not pseudo
715 /* These registers don't have a corresponding compact one. */
716 /* FIXME: This is probably not enough. */
718 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
721 if (rn >= 0 && rn <= R0_C_REGNUM)
722 return R0_C_REGNUM + rn;
728 /* Given a GDB frame, determine the address of the calling function's
729 frame. This will be used to create a new GDB frame struct, and
730 then DEPRECATED_INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC
731 will be called for the new frame.
733 For us, the frame address is its stack pointer value, so we look up
734 the function prologue to determine the caller's sp value, and return it. */
736 sh64_frame_chain (struct frame_info *frame)
738 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
739 get_frame_base (frame),
740 get_frame_base (frame)))
741 return get_frame_base (frame); /* dummy frame same as caller's frame */
742 if (get_frame_pc (frame)
743 && !deprecated_inside_entry_file (get_frame_pc (frame)))
745 int media_mode = pc_is_isa32 (get_frame_pc (frame));
747 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
750 size = register_size (current_gdbarch,
751 translate_insn_rn (DEPRECATED_FP_REGNUM,
753 return read_memory_integer (get_frame_base (frame)
754 + get_frame_extra_info (frame)->f_offset,
762 sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
766 for (; fi; fi = get_next_frame (fi))
767 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
768 get_frame_base (fi)))
769 /* When the caller requests PR from the dummy frame, we return
770 PC because that's where the previous routine appears to have
772 return deprecated_read_register_dummy (get_frame_pc (fi),
773 get_frame_base (fi), pr_regnum);
776 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
777 if (!get_frame_pc (fi))
780 media_mode = pc_is_isa32 (get_frame_pc (fi));
782 if (deprecated_get_frame_saved_regs (fi)[pr_regnum] != 0)
784 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
785 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
787 : register_size (current_gdbarch, gdb_reg_num));
788 return read_memory_integer (deprecated_get_frame_saved_regs (fi)[pr_regnum], size);
791 return read_register (pr_regnum);
794 /* For vectors of 4 floating point registers. */
796 fv_reg_base_num (int fv_regnum)
800 fp_regnum = FP0_REGNUM +
801 (fv_regnum - FV0_REGNUM) * 4;
805 /* For double precision floating point registers, i.e 2 fp regs.*/
807 dr_reg_base_num (int dr_regnum)
811 fp_regnum = FP0_REGNUM +
812 (dr_regnum - DR0_REGNUM) * 2;
816 /* For pairs of floating point registers */
818 fpp_reg_base_num (int fpp_regnum)
822 fp_regnum = FP0_REGNUM +
823 (fpp_regnum - FPP0_REGNUM) * 2;
828 is_media_pseudo (int rn)
830 return (rn >= DR0_REGNUM && rn <= FV_LAST_REGNUM);
834 sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
836 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
840 sh64_media_reg_base_num (int reg_nr)
842 int base_regnum = -1;
844 if (reg_nr >= DR0_REGNUM
845 && reg_nr <= DR_LAST_REGNUM)
846 base_regnum = dr_reg_base_num (reg_nr);
848 else if (reg_nr >= FPP0_REGNUM
849 && reg_nr <= FPP_LAST_REGNUM)
850 base_regnum = fpp_reg_base_num (reg_nr);
852 else if (reg_nr >= FV0_REGNUM
853 && reg_nr <= FV_LAST_REGNUM)
854 base_regnum = fv_reg_base_num (reg_nr);
861 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
862 GDB_REGNUM BASE_REGNUM
922 sh64_compact_reg_base_num (int reg_nr)
924 int base_regnum = -1;
926 /* general register N maps to general register N */
927 if (reg_nr >= R0_C_REGNUM
928 && reg_nr <= R_LAST_C_REGNUM)
929 base_regnum = reg_nr - R0_C_REGNUM;
931 /* floating point register N maps to floating point register N */
932 else if (reg_nr >= FP0_C_REGNUM
933 && reg_nr <= FP_LAST_C_REGNUM)
934 base_regnum = reg_nr - FP0_C_REGNUM + FP0_REGNUM;
936 /* double prec register N maps to base regnum for double prec register N */
937 else if (reg_nr >= DR0_C_REGNUM
938 && reg_nr <= DR_LAST_C_REGNUM)
939 base_regnum = dr_reg_base_num (DR0_REGNUM
940 + reg_nr - DR0_C_REGNUM);
942 /* vector N maps to base regnum for vector register N */
943 else if (reg_nr >= FV0_C_REGNUM
944 && reg_nr <= FV_LAST_C_REGNUM)
945 base_regnum = fv_reg_base_num (FV0_REGNUM
946 + reg_nr - FV0_C_REGNUM);
948 else if (reg_nr == PC_C_REGNUM)
949 base_regnum = PC_REGNUM;
951 else if (reg_nr == GBR_C_REGNUM)
954 else if (reg_nr == MACH_C_REGNUM
955 || reg_nr == MACL_C_REGNUM)
958 else if (reg_nr == PR_C_REGNUM)
961 else if (reg_nr == T_C_REGNUM)
964 else if (reg_nr == FPSCR_C_REGNUM)
965 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
967 else if (reg_nr == FPUL_C_REGNUM)
968 base_regnum = FP0_REGNUM + 32;
973 /* Given a register number RN (according to the gdb scheme) , return
974 its corresponding architectural register. In media mode, only a
975 subset of the registers is pseudo registers. For compact mode, all
976 the registers are pseudo. */
978 translate_rn_to_arch_reg_num (int rn, int media_mode)
983 if (!is_media_pseudo (rn))
986 return sh64_media_reg_base_num (rn);
989 /* All compact registers are pseudo. */
990 return sh64_compact_reg_base_num (rn);
994 sign_extend (int value, int bits)
996 value = value & ((1 << bits) - 1);
997 return (value & (1 << (bits - 1))
998 ? value | (~((1 << bits) - 1))
1003 sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
1005 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1017 int gdb_register_number;
1018 int register_number;
1019 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi),
1020 get_frame_base (fi));
1021 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1023 if (deprecated_get_frame_saved_regs (fi) == NULL)
1024 frame_saved_regs_zalloc (fi);
1026 memset (deprecated_get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1030 /* DANGER! This is ONLY going to work if the char buffer format of
1031 the saved registers is byte-for-byte identical to the
1032 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1033 memcpy (deprecated_get_frame_saved_regs (fi), dummy_regs, SIZEOF_FRAME_SAVED_REGS);
1037 get_frame_extra_info (fi)->leaf_function = 1;
1038 get_frame_extra_info (fi)->f_offset = 0;
1040 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1045 /* Loop around examining the prologue insns until we find something
1046 that does not appear to be part of the prologue. But give up
1047 after 20 of them, since we're getting silly then. */
1049 pc = get_frame_func (fi);
1052 deprecated_update_frame_pc_hack (fi, 0);
1056 if (pc_is_isa32 (pc))
1067 /* The frame pointer register is general register 14 in shmedia and
1068 shcompact modes. In sh compact it is a pseudo register. Same goes
1069 for the stack pointer register, which is register 15. */
1070 fp_regnum = translate_insn_rn (DEPRECATED_FP_REGNUM, media_mode);
1071 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1073 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1075 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1078 if (media_mode == 0)
1080 if (IS_STS_PR (insn))
1082 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1083 if (IS_MOV_TO_R15 (next_insn))
1085 int reg_nr = PR_C_REGNUM;
1087 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1088 get_frame_extra_info (fi)->leaf_function = 0;
1092 else if (IS_MOV_R14 (insn))
1094 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1097 else if (IS_MOV_R0 (insn))
1099 /* Put in R0 the offset from SP at which to store some
1100 registers. We are interested in this value, because it
1101 will tell us where the given registers are stored within
1103 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1105 else if (IS_ADD_SP_R0 (insn))
1107 /* This instruction still prepares r0, but we don't care.
1108 We already have the offset in r0_val. */
1110 else if (IS_STS_R0 (insn))
1112 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1113 int reg_nr = PR_C_REGNUM;
1114 where[reg_nr] = depth - (r0_val - 4);
1116 get_frame_extra_info (fi)->leaf_function = 0;
1118 else if (IS_MOV_R14_R0 (insn))
1120 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1121 where[fp_regnum] = depth - (r0_val - 4);
1125 else if (IS_ADD_SP (insn))
1127 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1129 else if (IS_MOV_SP_FP (insn))
1134 if (IS_ADDIL_SP_MEDIA (insn)
1135 || IS_ADDI_SP_MEDIA (insn))
1137 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1140 else if (IS_STQ_R18_R15 (insn))
1143 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1144 get_frame_extra_info (fi)->leaf_function = 0;
1147 else if (IS_STL_R18_R15 (insn))
1150 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1151 get_frame_extra_info (fi)->leaf_function = 0;
1154 else if (IS_STQ_R14_R15 (insn))
1156 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1159 else if (IS_STL_R14_R15 (insn))
1161 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1164 else if (IS_MOV_SP_FP_MEDIA (insn))
1169 /* Now we know how deep things are, we can work out their addresses. */
1170 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1172 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1176 if (rn == fp_regnum)
1179 /* Watch out! saved_regs is only for the real registers, and
1180 doesn't include space for the pseudo registers. */
1181 deprecated_get_frame_saved_regs (fi)[register_number]
1182 = get_frame_base (fi) - where[rn] + depth;
1185 deprecated_get_frame_saved_regs (fi)[register_number] = 0;
1190 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1191 shcompact 15 is the arch register corresponding to the pseudo
1192 register r15 which still is the SP register. */
1193 /* The place on the stack where fp is stored contains the sp of
1195 /* Again, saved_registers contains only space for the real
1196 registers, so we store in DEPRECATED_FP_REGNUM position. */
1198 if (tdep->sh_abi == SH_ABI_32)
1201 size = register_size (current_gdbarch, fp_regnum);
1202 deprecated_get_frame_saved_regs (fi)[sp_regnum]
1203 = read_memory_integer (deprecated_get_frame_saved_regs (fi)[fp_regnum],
1207 deprecated_get_frame_saved_regs (fi)[sp_regnum] = get_frame_base (fi);
1209 get_frame_extra_info (fi)->f_offset = depth - where[fp_regnum];
1212 /* Initialize the extra info saved in a FRAME */
1214 sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1216 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1218 frame_extra_info_zalloc (fi, sizeof (struct frame_extra_info));
1220 if (get_next_frame (fi))
1221 deprecated_update_frame_pc_hack (fi, DEPRECATED_FRAME_SAVED_PC (get_next_frame (fi)));
1223 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), get_frame_base (fi),
1224 get_frame_base (fi)))
1226 /* We need to setup fi->frame here because call_function_by_hand
1227 gets it wrong by assuming it's always FP. */
1228 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), get_frame_base (fi), SP_REGNUM));
1229 get_frame_extra_info (fi)->return_pc =
1230 deprecated_read_register_dummy (get_frame_pc (fi),
1231 get_frame_base (fi), PC_REGNUM);
1232 get_frame_extra_info (fi)->f_offset = -(DEPRECATED_CALL_DUMMY_LENGTH + 4);
1233 get_frame_extra_info (fi)->leaf_function = 0;
1238 DEPRECATED_FRAME_INIT_SAVED_REGS (fi);
1239 get_frame_extra_info (fi)->return_pc =
1240 sh64_get_saved_pr (fi, PR_REGNUM);
1245 sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1246 struct frame_info *frame, int regnum,
1247 enum lval_type *lval)
1250 int live_regnum = regnum;
1251 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1253 if (!target_has_registers)
1254 error ("No registers.");
1256 /* Normal systems don't optimize out things with register numbers. */
1257 if (optimized != NULL)
1260 if (addrp) /* default assumption: not found in memory */
1264 memset (raw_buffer, 0, sizeof (raw_buffer));
1266 /* We must do this here, before the following while loop changes
1267 frame, and makes it NULL. If this is a media register number,
1268 but we are in compact mode, it will become the corresponding
1269 compact pseudo register. If there is no corresponding compact
1270 pseudo-register what do we do?*/
1271 media_mode = pc_is_isa32 (get_frame_pc (frame));
1272 live_regnum = translate_insn_rn (regnum, media_mode);
1274 /* Note: since the current frame's registers could only have been
1275 saved by frames INTERIOR TO the current frame, we skip examining
1276 the current frame itself: otherwise, we would be getting the
1277 previous frame's registers which were saved by the current frame. */
1279 while (frame && ((frame = get_next_frame (frame)) != NULL))
1281 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1282 get_frame_base (frame),
1283 get_frame_base (frame)))
1285 if (lval) /* found it in a CALL_DUMMY frame */
1289 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), get_frame_base (frame))
1290 + DEPRECATED_REGISTER_BYTE (regnum)),
1291 register_size (current_gdbarch, regnum));
1295 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1296 if (deprecated_get_frame_saved_regs (frame) != NULL
1297 && deprecated_get_frame_saved_regs (frame)[regnum] != 0)
1299 if (lval) /* found it saved on the stack */
1300 *lval = lval_memory;
1301 if (regnum == SP_REGNUM)
1303 if (raw_buffer) /* SP register treated specially */
1304 store_unsigned_integer (raw_buffer,
1305 register_size (current_gdbarch,
1307 deprecated_get_frame_saved_regs (frame)[regnum]);
1310 { /* any other register */
1313 *addrp = deprecated_get_frame_saved_regs (frame)[regnum];
1317 if (tdep->sh_abi == SH_ABI_32
1318 && (live_regnum == DEPRECATED_FP_REGNUM
1319 || live_regnum == PR_REGNUM))
1322 size = register_size (current_gdbarch, live_regnum);
1323 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1324 read_memory (deprecated_get_frame_saved_regs (frame)[regnum], raw_buffer, size);
1326 read_memory (deprecated_get_frame_saved_regs (frame)[regnum],
1328 + register_size (current_gdbarch, live_regnum)
1337 /* If we get thru the loop to this point, it means the register was
1338 not saved in any frame. Return the actual live-register value. */
1340 if (lval) /* found it in a live register */
1341 *lval = lval_register;
1343 *addrp = DEPRECATED_REGISTER_BYTE (live_regnum);
1345 deprecated_read_register_gen (live_regnum, raw_buffer);
1349 sh64_extract_struct_value_address (char *regbuf)
1351 return (extract_unsigned_integer ((regbuf + DEPRECATED_REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
1352 register_size (current_gdbarch,
1353 STRUCT_RETURN_REGNUM)));
1357 sh_frame_saved_pc (struct frame_info *frame)
1359 return (get_frame_extra_info (frame)->return_pc);
1362 /* Discard from the stack the innermost frame, restoring all saved registers.
1363 Used in the 'return' command. */
1365 sh64_pop_frame (void)
1367 struct frame_info *frame = get_current_frame ();
1370 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1372 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1374 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame),
1375 get_frame_base (frame),
1376 get_frame_base (frame)))
1377 generic_pop_dummy_frame ();
1380 fp = get_frame_base (frame);
1381 DEPRECATED_FRAME_INIT_SAVED_REGS (frame);
1383 /* Copy regs from where they were saved in the frame */
1384 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1385 if (deprecated_get_frame_saved_regs (frame)[regnum])
1388 if (tdep->sh_abi == SH_ABI_32
1389 && (regnum == DEPRECATED_FP_REGNUM
1390 || regnum == PR_REGNUM))
1393 size = register_size (current_gdbarch,
1394 translate_insn_rn (regnum, media_mode));
1395 write_register (regnum,
1396 read_memory_integer (deprecated_get_frame_saved_regs (frame)[regnum],
1400 write_register (PC_REGNUM, get_frame_extra_info (frame)->return_pc);
1401 write_register (SP_REGNUM, fp + 8);
1403 flush_cached_frames ();
1407 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
1412 /* Function: push_arguments
1413 Setup the function arguments for calling a function in the inferior.
1415 On the Renesas SH architecture, there are four registers (R4 to R7)
1416 which are dedicated for passing function arguments. Up to the first
1417 four arguments (depending on size) may go into these registers.
1418 The rest go on the stack.
1420 Arguments that are smaller than 4 bytes will still take up a whole
1421 register or a whole 32-bit word on the stack, and will be
1422 right-justified in the register or the stack word. This includes
1423 chars, shorts, and small aggregate types.
1425 Arguments that are larger than 4 bytes may be split between two or
1426 more registers. If there are not enough registers free, an argument
1427 may be passed partly in a register (or registers), and partly on the
1428 stack. This includes doubles, long longs, and larger aggregates.
1429 As far as I know, there is no upper limit to the size of aggregates
1430 that will be passed in this way; in other words, the convention of
1431 passing a pointer to a large aggregate instead of a copy is not used.
1433 An exceptional case exists for struct arguments (and possibly other
1434 aggregates such as arrays) if the size is larger than 4 bytes but
1435 not a multiple of 4 bytes. In this case the argument is never split
1436 between the registers and the stack, but instead is copied in its
1437 entirety onto the stack, AND also copied into as many registers as
1438 there is room for. In other words, space in registers permitting,
1439 two copies of the same argument are passed in. As far as I can tell,
1440 only the one on the stack is used, although that may be a function
1441 of the level of compiler optimization. I suspect this is a compiler
1442 bug. Arguments of these odd sizes are left-justified within the
1443 word (as opposed to arguments smaller than 4 bytes, which are
1446 If the function is to return an aggregate type such as a struct, it
1447 is either returned in the normal return value register R0 (if its
1448 size is no greater than one byte), or else the caller must allocate
1449 space into which the callee will copy the return value (if the size
1450 is greater than one byte). In this case, a pointer to the return
1451 value location is passed into the callee in register R2, which does
1452 not displace any of the other arguments passed in via registers R4
1455 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1456 non-scalar (struct, union) elements (even if the elements are
1458 FR0-FR11 for single precision floating point (float)
1459 DR0-DR10 for double precision floating point (double)
1461 If a float is argument number 3 (for instance) and arguments number
1462 1,2, and 4 are integer, the mapping will be:
1463 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1465 If a float is argument number 10 (for instance) and arguments number
1466 1 through 10 are integer, the mapping will be:
1467 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1468 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
1469 I.e. there is hole in the stack.
1471 Different rules apply for variable arguments functions, and for functions
1472 for which the prototype is not known. */
1475 sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
1476 int struct_return, CORE_ADDR struct_addr)
1478 int stack_offset, stack_alloc;
1482 int float_arg_index = 0;
1483 int double_arg_index = 0;
1494 memset (fp_args, 0, sizeof (fp_args));
1496 /* first force sp to a 8-byte alignment */
1499 /* The "struct return pointer" pseudo-argument has its own dedicated
1503 write_register (STRUCT_RETURN_REGNUM, struct_addr);
1505 /* Now make sure there's space on the stack */
1506 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1507 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
1508 sp -= stack_alloc; /* make room on stack for args */
1510 /* Now load as many as possible of the first arguments into
1511 registers, and push the rest onto the stack. There are 64 bytes
1512 in eight registers available. Loop thru args from first to last. */
1514 int_argreg = ARG0_REGNUM;
1515 float_argreg = FP0_REGNUM;
1516 double_argreg = DR0_REGNUM;
1518 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1520 type = VALUE_TYPE (args[argnum]);
1521 len = TYPE_LENGTH (type);
1522 memset (valbuf, 0, sizeof (valbuf));
1524 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1526 argreg_size = register_size (current_gdbarch, int_argreg);
1528 if (len < argreg_size)
1530 /* value gets right-justified in the register or stack word */
1531 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1532 memcpy (valbuf + argreg_size - len,
1533 (char *) VALUE_CONTENTS (args[argnum]), len);
1535 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
1540 val = (char *) VALUE_CONTENTS (args[argnum]);
1544 if (int_argreg > ARGLAST_REGNUM)
1546 /* must go on the stack */
1547 write_memory (sp + stack_offset, val, argreg_size);
1548 stack_offset += 8;/*argreg_size;*/
1550 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1551 That's because some *&^%$ things get passed on the stack
1552 AND in the registers! */
1553 if (int_argreg <= ARGLAST_REGNUM)
1555 /* there's room in a register */
1556 regval = extract_unsigned_integer (val, argreg_size);
1557 write_register (int_argreg, regval);
1559 /* Store the value 8 bytes at a time. This means that
1560 things larger than 8 bytes may go partly in registers
1561 and partly on the stack. FIXME: argreg is incremented
1562 before we use its size. */
1570 val = (char *) VALUE_CONTENTS (args[argnum]);
1573 /* Where is it going to be stored? */
1574 while (fp_args[float_arg_index])
1577 /* Now float_argreg points to the register where it
1578 should be stored. Are we still within the allowed
1580 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1582 /* Goes in FR0...FR11 */
1583 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
1585 fp_args[float_arg_index] = 1;
1586 /* Skip the corresponding general argument register. */
1591 /* Store it as the integers, 8 bytes at the time, if
1592 necessary spilling on the stack. */
1597 /* Where is it going to be stored? */
1598 while (fp_args[double_arg_index])
1599 double_arg_index += 2;
1600 /* Now double_argreg points to the register
1601 where it should be stored.
1602 Are we still within the allowed register set? */
1603 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1605 /* Goes in DR0...DR10 */
1606 /* The numbering of the DRi registers is consecutive,
1607 i.e. includes odd numbers. */
1608 int double_register_offset = double_arg_index / 2;
1609 int regnum = DR0_REGNUM +
1610 double_register_offset;
1612 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1614 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
1615 DEPRECATED_REGISTER_CONVERT_TO_VIRTUAL (regnum,
1621 /* Note: must use write_register_gen here instead
1622 of regcache_raw_write, because
1623 regcache_raw_write works only for real
1624 registers, not pseudo. write_register_gen will
1625 call the gdbarch function to do register
1626 writes, and that will properly know how to deal
1628 deprecated_write_register_gen (regnum, val);
1629 fp_args[double_arg_index] = 1;
1630 fp_args[double_arg_index + 1] = 1;
1631 /* Skip the corresponding general argument register. */
1636 /* Store it as the integers, 8 bytes at the time, if
1637 necessary spilling on the stack. */
1644 /* Function: push_return_address (pc)
1645 Set up the return address for the inferior function call.
1646 Needed for targets where we don't actually execute a JSR/BSR instruction */
1649 sh64_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
1651 write_register (PR_REGNUM, entry_point_address ());
1655 /* Find a function's return value in the appropriate registers (in
1656 regbuf), and copy it into valbuf. Extract from an array REGBUF
1657 containing the (raw) register state a function return value of type
1658 TYPE, and copy that, in virtual format, into VALBUF. */
1660 sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
1663 int return_register;
1664 int len = TYPE_LENGTH (type);
1666 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1670 /* Return value stored in FP0_REGNUM */
1671 return_register = FP0_REGNUM;
1672 offset = DEPRECATED_REGISTER_BYTE (return_register);
1673 memcpy (valbuf, (char *) regbuf + offset, len);
1677 /* return value stored in DR0_REGNUM */
1680 return_register = DR0_REGNUM;
1681 offset = DEPRECATED_REGISTER_BYTE (return_register);
1683 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1684 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1685 (char *) regbuf + offset, &val);
1687 floatformat_to_doublest (&floatformat_ieee_double_big,
1688 (char *) regbuf + offset, &val);
1689 store_typed_floating (valbuf, type, val);
1696 /* Result is in register 2. If smaller than 8 bytes, it is padded
1697 at the most significant end. */
1698 return_register = DEFAULT_RETURN_REGNUM;
1699 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1700 offset = DEPRECATED_REGISTER_BYTE (return_register) +
1701 register_size (current_gdbarch, return_register) - len;
1703 offset = DEPRECATED_REGISTER_BYTE (return_register);
1704 memcpy (valbuf, (char *) regbuf + offset, len);
1707 error ("bad size for return value");
1711 /* Write into appropriate registers a function return value
1712 of type TYPE, given in virtual format.
1713 If the architecture is sh4 or sh3e, store a function's return value
1714 in the R0 general register or in the FP0 floating point register,
1715 depending on the type of the return value. In all the other cases
1716 the result is stored in r0, left-justified. */
1719 sh64_store_return_value (struct type *type, char *valbuf)
1721 char buf[64]; /* more than enough... */
1722 int len = TYPE_LENGTH (type);
1724 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1728 /* Return value stored in FP0_REGNUM */
1729 deprecated_write_register_gen (FP0_REGNUM, valbuf);
1733 /* return value stored in DR0_REGNUM */
1734 /* FIXME: Implement */
1739 int return_register = DEFAULT_RETURN_REGNUM;
1742 if (len <= register_size (current_gdbarch, return_register))
1744 /* Pad with zeros. */
1745 memset (buf, 0, register_size (current_gdbarch, return_register));
1746 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1747 offset = 0; /*register_size (current_gdbarch,
1748 return_register) - len;*/
1750 offset = register_size (current_gdbarch, return_register) - len;
1752 memcpy (buf + offset, valbuf, len);
1753 deprecated_write_register_gen (return_register, buf);
1756 deprecated_write_register_gen (return_register, valbuf);
1761 sh64_show_media_regs (void)
1765 printf_filtered ("PC=%s SR=%016llx \n",
1766 paddr (read_register (PC_REGNUM)),
1767 (long long) read_register (SR_REGNUM));
1769 printf_filtered ("SSR=%016llx SPC=%016llx \n",
1770 (long long) read_register (SSR_REGNUM),
1771 (long long) read_register (SPC_REGNUM));
1772 printf_filtered ("FPSCR=%016lx\n ",
1773 (long) read_register (FPSCR_REGNUM));
1775 for (i = 0; i < 64; i = i + 4)
1776 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
1778 (long long) read_register (i + 0),
1779 (long long) read_register (i + 1),
1780 (long long) read_register (i + 2),
1781 (long long) read_register (i + 3));
1783 printf_filtered ("\n");
1785 for (i = 0; i < 64; i = i + 8)
1786 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1788 (long) read_register (FP0_REGNUM + i + 0),
1789 (long) read_register (FP0_REGNUM + i + 1),
1790 (long) read_register (FP0_REGNUM + i + 2),
1791 (long) read_register (FP0_REGNUM + i + 3),
1792 (long) read_register (FP0_REGNUM + i + 4),
1793 (long) read_register (FP0_REGNUM + i + 5),
1794 (long) read_register (FP0_REGNUM + i + 6),
1795 (long) read_register (FP0_REGNUM + i + 7));
1799 sh64_show_compact_regs (void)
1803 printf_filtered ("PC=%s \n",
1804 paddr (read_register (PC_C_REGNUM)));
1806 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
1807 (long) read_register (GBR_C_REGNUM),
1808 (long) read_register (MACH_C_REGNUM),
1809 (long) read_register (MACL_C_REGNUM),
1810 (long) read_register (PR_C_REGNUM),
1811 (long) read_register (T_C_REGNUM));
1812 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
1813 (long) read_register (FPSCR_C_REGNUM),
1814 (long) read_register (FPUL_C_REGNUM));
1816 for (i = 0; i < 16; i = i + 4)
1817 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
1819 (long) read_register (i + 0),
1820 (long) read_register (i + 1),
1821 (long) read_register (i + 2),
1822 (long) read_register (i + 3));
1824 printf_filtered ("\n");
1826 for (i = 0; i < 16; i = i + 8)
1827 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1829 (long) read_register (FP0_REGNUM + i + 0),
1830 (long) read_register (FP0_REGNUM + i + 1),
1831 (long) read_register (FP0_REGNUM + i + 2),
1832 (long) read_register (FP0_REGNUM + i + 3),
1833 (long) read_register (FP0_REGNUM + i + 4),
1834 (long) read_register (FP0_REGNUM + i + 5),
1835 (long) read_register (FP0_REGNUM + i + 6),
1836 (long) read_register (FP0_REGNUM + i + 7));
1839 /* FIXME!!! This only shows the registers for shmedia, excluding the
1840 pseudo registers. */
1842 sh64_show_regs (void)
1844 if (deprecated_selected_frame
1845 && pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
1846 sh64_show_media_regs ();
1848 sh64_show_compact_regs ();
1853 SH MEDIA MODE (ISA 32)
1854 general registers (64-bit) 0-63
1855 0 r0, r1, r2, r3, r4, r5, r6, r7,
1856 64 r8, r9, r10, r11, r12, r13, r14, r15,
1857 128 r16, r17, r18, r19, r20, r21, r22, r23,
1858 192 r24, r25, r26, r27, r28, r29, r30, r31,
1859 256 r32, r33, r34, r35, r36, r37, r38, r39,
1860 320 r40, r41, r42, r43, r44, r45, r46, r47,
1861 384 r48, r49, r50, r51, r52, r53, r54, r55,
1862 448 r56, r57, r58, r59, r60, r61, r62, r63,
1867 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1870 target registers (64-bit) 68-75
1871 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1873 floating point state control register (32-bit) 76
1876 single precision floating point registers (32-bit) 77-140
1877 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1878 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1879 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1880 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1881 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1882 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1883 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1884 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1886 TOTAL SPACE FOR REGISTERS: 868 bytes
1888 From here on they are all pseudo registers: no memory allocated.
1889 REGISTER_BYTE returns the register byte for the base register.
1891 double precision registers (pseudo) 141-172
1892 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1893 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1894 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1895 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1897 floating point pairs (pseudo) 173-204
1898 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1899 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1900 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1901 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1903 floating point vectors (4 floating point regs) (pseudo) 205-220
1904 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1905 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1907 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1908 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1909 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1911 gbr_c, mach_c, macl_c, pr_c, t_c,
1913 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1914 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1915 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1916 fv0_c, fv4_c, fv8_c, fv12_c
1920 sh_sh64_register_byte (int reg_nr)
1922 int base_regnum = -1;
1924 /* If it is a pseudo register, get the number of the first floating
1925 point register that is part of it. */
1926 if (reg_nr >= DR0_REGNUM
1927 && reg_nr <= DR_LAST_REGNUM)
1928 base_regnum = dr_reg_base_num (reg_nr);
1930 else if (reg_nr >= FPP0_REGNUM
1931 && reg_nr <= FPP_LAST_REGNUM)
1932 base_regnum = fpp_reg_base_num (reg_nr);
1934 else if (reg_nr >= FV0_REGNUM
1935 && reg_nr <= FV_LAST_REGNUM)
1936 base_regnum = fv_reg_base_num (reg_nr);
1938 /* sh compact pseudo register. FPSCR is a pathological case, need to
1939 treat it as special. */
1940 else if ((reg_nr >= R0_C_REGNUM
1941 && reg_nr <= FV_LAST_C_REGNUM)
1942 && reg_nr != FPSCR_C_REGNUM)
1943 base_regnum = sh64_compact_reg_base_num (reg_nr);
1945 /* Now return the offset in bytes within the register cache. */
1946 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
1947 if (reg_nr >= DR0_REGNUM
1948 && reg_nr <= FV_LAST_REGNUM)
1949 return (base_regnum - FP0_REGNUM + 1) * 4
1950 + (TR7_REGNUM + 1) * 8;
1952 /* sh compact pseudo register: general register */
1953 if ((reg_nr >= R0_C_REGNUM
1954 && reg_nr <= R_LAST_C_REGNUM))
1955 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1956 ? base_regnum * 8 + 4
1959 /* sh compact pseudo register: */
1960 if (reg_nr == PC_C_REGNUM
1961 || reg_nr == GBR_C_REGNUM
1962 || reg_nr == MACL_C_REGNUM
1963 || reg_nr == PR_C_REGNUM)
1964 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1965 ? base_regnum * 8 + 4
1968 if (reg_nr == MACH_C_REGNUM)
1969 return base_regnum * 8;
1971 if (reg_nr == T_C_REGNUM)
1972 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
1974 /* sh compact pseudo register: floating point register */
1975 else if (reg_nr >= FP0_C_REGNUM
1976 && reg_nr <= FV_LAST_C_REGNUM)
1977 return (base_regnum - FP0_REGNUM) * 4
1978 + (TR7_REGNUM + 1) * 8 + 4;
1980 else if (reg_nr == FPSCR_C_REGNUM)
1981 /* This is complicated, for now return the beginning of the
1982 architectural FPSCR register. */
1983 return (TR7_REGNUM + 1) * 8;
1985 else if (reg_nr == FPUL_C_REGNUM)
1986 return ((base_regnum - FP0_REGNUM) * 4 +
1987 (TR7_REGNUM + 1) * 8 + 4);
1989 /* It is not a pseudo register. */
1990 /* It is a 64 bit register. */
1991 else if (reg_nr <= TR7_REGNUM)
1994 /* It is a 32 bit register. */
1995 else if (reg_nr == FPSCR_REGNUM)
1996 return (FPSCR_REGNUM * 8);
1998 /* It is floating point 32-bit register */
2000 return ((TR7_REGNUM + 1) * 8
2001 + (reg_nr - FP0_REGNUM + 1) * 4);
2004 static struct type *
2005 sh_sh64_build_float_register_type (int high)
2009 temp = create_range_type (NULL, builtin_type_int, 0, high);
2010 return create_array_type (NULL, builtin_type_float, temp);
2013 /* Return the GDB type object for the "standard" data type
2014 of data in register REG_NR. */
2015 static struct type *
2016 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
2018 if ((reg_nr >= FP0_REGNUM
2019 && reg_nr <= FP_LAST_REGNUM)
2020 || (reg_nr >= FP0_C_REGNUM
2021 && reg_nr <= FP_LAST_C_REGNUM))
2022 return builtin_type_float;
2023 else if ((reg_nr >= DR0_REGNUM
2024 && reg_nr <= DR_LAST_REGNUM)
2025 || (reg_nr >= DR0_C_REGNUM
2026 && reg_nr <= DR_LAST_C_REGNUM))
2027 return builtin_type_double;
2028 else if (reg_nr >= FPP0_REGNUM
2029 && reg_nr <= FPP_LAST_REGNUM)
2030 return sh_sh64_build_float_register_type (1);
2031 else if ((reg_nr >= FV0_REGNUM
2032 && reg_nr <= FV_LAST_REGNUM)
2033 ||(reg_nr >= FV0_C_REGNUM
2034 && reg_nr <= FV_LAST_C_REGNUM))
2035 return sh_sh64_build_float_register_type (3);
2036 else if (reg_nr == FPSCR_REGNUM)
2037 return builtin_type_int;
2038 else if (reg_nr >= R0_C_REGNUM
2039 && reg_nr < FP0_C_REGNUM)
2040 return builtin_type_int;
2042 return builtin_type_long_long;
2046 sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
2047 char *from, char *to)
2049 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2051 /* It is a no-op. */
2052 memcpy (to, from, register_size (current_gdbarch, regnum));
2056 if ((regnum >= DR0_REGNUM
2057 && regnum <= DR_LAST_REGNUM)
2058 || (regnum >= DR0_C_REGNUM
2059 && regnum <= DR_LAST_C_REGNUM))
2062 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2064 store_typed_floating(to, type, val);
2067 error("sh64_register_convert_to_virtual called with non DR register number");
2071 sh_sh64_register_convert_to_raw (struct type *type, int regnum,
2072 const void *from, void *to)
2074 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
2076 /* It is a no-op. */
2077 memcpy (to, from, register_size (current_gdbarch, regnum));
2081 if ((regnum >= DR0_REGNUM
2082 && regnum <= DR_LAST_REGNUM)
2083 || (regnum >= DR0_C_REGNUM
2084 && regnum <= DR_LAST_C_REGNUM))
2086 DOUBLEST val = deprecated_extract_floating (from, TYPE_LENGTH(type));
2087 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2091 error("sh64_register_convert_to_raw called with non DR register number");
2095 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2096 int reg_nr, void *buffer)
2101 char temp_buffer[MAX_REGISTER_SIZE];
2103 if (reg_nr >= DR0_REGNUM
2104 && reg_nr <= DR_LAST_REGNUM)
2106 base_regnum = dr_reg_base_num (reg_nr);
2108 /* Build the value in the provided buffer. */
2109 /* DR regs are double precision registers obtained by
2110 concatenating 2 single precision floating point registers. */
2111 for (portion = 0; portion < 2; portion++)
2112 regcache_raw_read (regcache, base_regnum + portion,
2114 + register_size (gdbarch, base_regnum) * portion));
2116 /* We must pay attention to the endianness. */
2117 sh_sh64_register_convert_to_virtual (reg_nr,
2118 gdbarch_register_type (gdbarch,
2120 temp_buffer, buffer);
2124 else if (reg_nr >= FPP0_REGNUM
2125 && reg_nr <= FPP_LAST_REGNUM)
2127 base_regnum = fpp_reg_base_num (reg_nr);
2129 /* Build the value in the provided buffer. */
2130 /* FPP regs are pairs of single precision registers obtained by
2131 concatenating 2 single precision floating point registers. */
2132 for (portion = 0; portion < 2; portion++)
2133 regcache_raw_read (regcache, base_regnum + portion,
2135 + register_size (gdbarch, base_regnum) * portion));
2138 else if (reg_nr >= FV0_REGNUM
2139 && reg_nr <= FV_LAST_REGNUM)
2141 base_regnum = fv_reg_base_num (reg_nr);
2143 /* Build the value in the provided buffer. */
2144 /* FV regs are vectors of single precision registers obtained by
2145 concatenating 4 single precision floating point registers. */
2146 for (portion = 0; portion < 4; portion++)
2147 regcache_raw_read (regcache, base_regnum + portion,
2149 + register_size (gdbarch, base_regnum) * portion));
2152 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
2153 else if (reg_nr >= R0_C_REGNUM
2154 && reg_nr <= T_C_REGNUM)
2156 base_regnum = sh64_compact_reg_base_num (reg_nr);
2158 /* Build the value in the provided buffer. */
2159 regcache_raw_read (regcache, base_regnum, temp_buffer);
2160 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2162 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
2165 else if (reg_nr >= FP0_C_REGNUM
2166 && reg_nr <= FP_LAST_C_REGNUM)
2168 base_regnum = sh64_compact_reg_base_num (reg_nr);
2170 /* Build the value in the provided buffer. */
2171 /* Floating point registers map 1-1 to the media fp regs,
2172 they have the same size and endianness. */
2173 regcache_raw_read (regcache, base_regnum, buffer);
2176 else if (reg_nr >= DR0_C_REGNUM
2177 && reg_nr <= DR_LAST_C_REGNUM)
2179 base_regnum = sh64_compact_reg_base_num (reg_nr);
2181 /* DR_C regs are double precision registers obtained by
2182 concatenating 2 single precision floating point registers. */
2183 for (portion = 0; portion < 2; portion++)
2184 regcache_raw_read (regcache, base_regnum + portion,
2186 + register_size (gdbarch, base_regnum) * portion));
2188 /* We must pay attention to the endianness. */
2189 sh_sh64_register_convert_to_virtual (reg_nr,
2190 gdbarch_register_type (gdbarch,
2192 temp_buffer, buffer);
2195 else if (reg_nr >= FV0_C_REGNUM
2196 && reg_nr <= FV_LAST_C_REGNUM)
2198 base_regnum = sh64_compact_reg_base_num (reg_nr);
2200 /* Build the value in the provided buffer. */
2201 /* FV_C regs are vectors of single precision registers obtained by
2202 concatenating 4 single precision floating point registers. */
2203 for (portion = 0; portion < 4; portion++)
2204 regcache_raw_read (regcache, base_regnum + portion,
2206 + register_size (gdbarch, base_regnum) * portion));
2209 else if (reg_nr == FPSCR_C_REGNUM)
2211 int fpscr_base_regnum;
2213 unsigned int fpscr_value;
2214 unsigned int sr_value;
2215 unsigned int fpscr_c_value;
2216 unsigned int fpscr_c_part1_value;
2217 unsigned int fpscr_c_part2_value;
2219 fpscr_base_regnum = FPSCR_REGNUM;
2220 sr_base_regnum = SR_REGNUM;
2222 /* Build the value in the provided buffer. */
2223 /* FPSCR_C is a very weird register that contains sparse bits
2224 from the FPSCR and the SR architectural registers.
2231 2-17 Bit 2-18 of FPSCR
2232 18-20 Bits 12,13,14 of SR
2236 /* Get FPSCR into a local buffer */
2237 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2238 /* Get value as an int. */
2239 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2240 /* Get SR into a local buffer */
2241 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2242 /* Get value as an int. */
2243 sr_value = extract_unsigned_integer (temp_buffer, 4);
2244 /* Build the new value. */
2245 fpscr_c_part1_value = fpscr_value & 0x3fffd;
2246 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
2247 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
2248 /* Store that in out buffer!!! */
2249 store_unsigned_integer (buffer, 4, fpscr_c_value);
2250 /* FIXME There is surely an endianness gotcha here. */
2253 else if (reg_nr == FPUL_C_REGNUM)
2255 base_regnum = sh64_compact_reg_base_num (reg_nr);
2257 /* FPUL_C register is floating point register 32,
2258 same size, same endianness. */
2259 regcache_raw_read (regcache, base_regnum, buffer);
2264 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2265 int reg_nr, const void *buffer)
2267 int base_regnum, portion;
2269 char temp_buffer[MAX_REGISTER_SIZE];
2271 if (reg_nr >= DR0_REGNUM
2272 && reg_nr <= DR_LAST_REGNUM)
2274 base_regnum = dr_reg_base_num (reg_nr);
2275 /* We must pay attention to the endianness. */
2276 sh_sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
2278 buffer, temp_buffer);
2281 /* Write the real regs for which this one is an alias. */
2282 for (portion = 0; portion < 2; portion++)
2283 regcache_raw_write (regcache, base_regnum + portion,
2285 + register_size (gdbarch,
2286 base_regnum) * portion));
2289 else if (reg_nr >= FPP0_REGNUM
2290 && reg_nr <= FPP_LAST_REGNUM)
2292 base_regnum = fpp_reg_base_num (reg_nr);
2294 /* Write the real regs for which this one is an alias. */
2295 for (portion = 0; portion < 2; portion++)
2296 regcache_raw_write (regcache, base_regnum + portion,
2298 + register_size (gdbarch,
2299 base_regnum) * portion));
2302 else if (reg_nr >= FV0_REGNUM
2303 && reg_nr <= FV_LAST_REGNUM)
2305 base_regnum = fv_reg_base_num (reg_nr);
2307 /* Write the real regs for which this one is an alias. */
2308 for (portion = 0; portion < 4; portion++)
2309 regcache_raw_write (regcache, base_regnum + portion,
2311 + register_size (gdbarch,
2312 base_regnum) * portion));
2315 /* sh compact general pseudo registers. 1-to-1 with a shmedia
2316 register but only 4 bytes of it. */
2317 else if (reg_nr >= R0_C_REGNUM
2318 && reg_nr <= T_C_REGNUM)
2320 base_regnum = sh64_compact_reg_base_num (reg_nr);
2321 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
2322 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2326 /* Let's read the value of the base register into a temporary
2327 buffer, so that overwriting the last four bytes with the new
2328 value of the pseudo will leave the upper 4 bytes unchanged. */
2329 regcache_raw_read (regcache, base_regnum, temp_buffer);
2330 /* Write as an 8 byte quantity */
2331 memcpy (temp_buffer + offset, buffer, 4);
2332 regcache_raw_write (regcache, base_regnum, temp_buffer);
2335 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
2336 registers. Both are 4 bytes. */
2337 else if (reg_nr >= FP0_C_REGNUM
2338 && reg_nr <= FP_LAST_C_REGNUM)
2340 base_regnum = sh64_compact_reg_base_num (reg_nr);
2341 regcache_raw_write (regcache, base_regnum, buffer);
2344 else if (reg_nr >= DR0_C_REGNUM
2345 && reg_nr <= DR_LAST_C_REGNUM)
2347 base_regnum = sh64_compact_reg_base_num (reg_nr);
2348 for (portion = 0; portion < 2; portion++)
2350 /* We must pay attention to the endianness. */
2351 sh_sh64_register_convert_to_raw (gdbarch_register_type (gdbarch,
2354 buffer, temp_buffer);
2356 regcache_raw_write (regcache, base_regnum + portion,
2358 + register_size (gdbarch,
2359 base_regnum) * portion));
2363 else if (reg_nr >= FV0_C_REGNUM
2364 && reg_nr <= FV_LAST_C_REGNUM)
2366 base_regnum = sh64_compact_reg_base_num (reg_nr);
2368 for (portion = 0; portion < 4; portion++)
2370 regcache_raw_write (regcache, base_regnum + portion,
2372 + register_size (gdbarch,
2373 base_regnum) * portion));
2377 else if (reg_nr == FPSCR_C_REGNUM)
2379 int fpscr_base_regnum;
2381 unsigned int fpscr_value;
2382 unsigned int sr_value;
2383 unsigned int old_fpscr_value;
2384 unsigned int old_sr_value;
2385 unsigned int fpscr_c_value;
2386 unsigned int fpscr_mask;
2387 unsigned int sr_mask;
2389 fpscr_base_regnum = FPSCR_REGNUM;
2390 sr_base_regnum = SR_REGNUM;
2392 /* FPSCR_C is a very weird register that contains sparse bits
2393 from the FPSCR and the SR architectural registers.
2400 2-17 Bit 2-18 of FPSCR
2401 18-20 Bits 12,13,14 of SR
2405 /* Get value as an int. */
2406 fpscr_c_value = extract_unsigned_integer (buffer, 4);
2408 /* Build the new values. */
2409 fpscr_mask = 0x0003fffd;
2410 sr_mask = 0x001c0000;
2412 fpscr_value = fpscr_c_value & fpscr_mask;
2413 sr_value = (fpscr_value & sr_mask) >> 6;
2415 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
2416 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
2417 old_fpscr_value &= 0xfffc0002;
2418 fpscr_value |= old_fpscr_value;
2419 store_unsigned_integer (temp_buffer, 4, fpscr_value);
2420 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
2422 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
2423 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
2424 old_sr_value &= 0xffff8fff;
2425 sr_value |= old_sr_value;
2426 store_unsigned_integer (temp_buffer, 4, sr_value);
2427 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
2430 else if (reg_nr == FPUL_C_REGNUM)
2432 base_regnum = sh64_compact_reg_base_num (reg_nr);
2433 regcache_raw_write (regcache, base_regnum, buffer);
2437 /* Floating point vector of 4 float registers. */
2439 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2442 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
2443 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2444 fv_regnum - FV0_REGNUM,
2445 (int) read_register (first_fp_reg_num),
2446 (int) read_register (first_fp_reg_num + 1),
2447 (int) read_register (first_fp_reg_num + 2),
2448 (int) read_register (first_fp_reg_num + 3));
2451 /* Floating point vector of 4 float registers, compact mode. */
2453 do_fv_c_register_info (int fv_regnum)
2455 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
2456 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
2457 fv_regnum - FV0_C_REGNUM,
2458 (int) read_register (first_fp_reg_num),
2459 (int) read_register (first_fp_reg_num + 1),
2460 (int) read_register (first_fp_reg_num + 2),
2461 (int) read_register (first_fp_reg_num + 3));
2464 /* Pairs of single regs. The DR are instead double precision
2467 do_fpp_register_info (int fpp_regnum)
2469 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
2471 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
2472 fpp_regnum - FPP0_REGNUM,
2473 (int) read_register (first_fp_reg_num),
2474 (int) read_register (first_fp_reg_num + 1));
2477 /* Double precision registers. */
2479 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
2482 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
2484 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
2485 dr_regnum - DR0_REGNUM,
2486 (int) read_register (first_fp_reg_num),
2487 (int) read_register (first_fp_reg_num + 1));
2490 /* Double precision registers, compact mode. */
2492 do_dr_c_register_info (int dr_regnum)
2494 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
2496 printf_filtered ("dr%d_c\t0x%08x%08x\n",
2497 dr_regnum - DR0_C_REGNUM,
2498 (int) read_register (first_fp_reg_num),
2499 (int) read_register (first_fp_reg_num +1));
2502 /* General register in compact mode. */
2504 do_r_c_register_info (int r_c_regnum)
2506 int regnum = sh64_compact_reg_base_num (r_c_regnum);
2508 printf_filtered ("r%d_c\t0x%08x\n",
2509 r_c_regnum - R0_C_REGNUM,
2510 /*FIXME!!!*/ (int) read_register (regnum));
2513 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
2514 shmedia REGISTERS. */
2515 /* Control registers, compact mode. */
2517 do_cr_c_register_info (int cr_c_regnum)
2519 switch (cr_c_regnum)
2521 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2523 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2525 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2527 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2529 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2531 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2533 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
2535 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
2541 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2542 { /* do values for FP (float) regs */
2544 double flt; /* double extracted from raw hex data */
2548 /* Allocate space for the float. */
2549 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
2551 /* Get the data in raw format. */
2552 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2553 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
2555 /* Get the register as a number */
2556 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
2558 /* Print the name and some spaces. */
2559 fputs_filtered (REGISTER_NAME (regnum), file);
2560 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2562 /* Print the value. */
2564 fprintf_filtered (file, "<invalid float>");
2566 fprintf_filtered (file, "%-10.9g", flt);
2568 /* Print the fp register as hex. */
2569 fprintf_filtered (file, "\t(raw 0x");
2570 for (j = 0; j < register_size (gdbarch, regnum); j++)
2572 int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
2573 : register_size (gdbarch, regnum) - 1 - j;
2574 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
2576 fprintf_filtered (file, ")");
2577 fprintf_filtered (file, "\n");
2581 sh64_do_pseudo_register (int regnum)
2583 /* All the sh64-compact mode registers are pseudo registers. */
2585 if (regnum < NUM_REGS
2586 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
2587 internal_error (__FILE__, __LINE__,
2588 "Invalid pseudo register number %d\n", regnum);
2590 else if ((regnum >= DR0_REGNUM
2591 && regnum <= DR_LAST_REGNUM))
2592 do_dr_register_info (current_gdbarch, gdb_stdout, regnum);
2594 else if ((regnum >= DR0_C_REGNUM
2595 && regnum <= DR_LAST_C_REGNUM))
2596 do_dr_c_register_info (regnum);
2598 else if ((regnum >= FV0_REGNUM
2599 && regnum <= FV_LAST_REGNUM))
2600 do_fv_register_info (current_gdbarch, gdb_stdout, regnum);
2602 else if ((regnum >= FV0_C_REGNUM
2603 && regnum <= FV_LAST_C_REGNUM))
2604 do_fv_c_register_info (regnum);
2606 else if (regnum >= FPP0_REGNUM
2607 && regnum <= FPP_LAST_REGNUM)
2608 do_fpp_register_info (regnum);
2610 else if (regnum >= R0_C_REGNUM
2611 && regnum <= R_LAST_C_REGNUM)
2612 /* FIXME, this function will not print the right format. */
2613 do_r_c_register_info (regnum);
2614 else if (regnum >= FP0_C_REGNUM
2615 && regnum <= FP_LAST_C_REGNUM)
2616 /* This should work also for pseudoregs. */
2617 sh_do_fp_register (current_gdbarch, gdb_stdout, regnum);
2618 else if (regnum >= PC_C_REGNUM
2619 && regnum <= FPUL_C_REGNUM)
2620 do_cr_c_register_info (regnum);
2624 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2626 char raw_buffer[MAX_REGISTER_SIZE];
2628 fputs_filtered (REGISTER_NAME (regnum), file);
2629 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
2631 /* Get the data in raw format. */
2632 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
2633 fprintf_filtered (file, "*value not available*\n");
2635 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2636 file, 'x', 1, 0, Val_pretty_default);
2637 fprintf_filtered (file, "\t");
2638 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
2639 file, 0, 1, 0, Val_pretty_default);
2640 fprintf_filtered (file, "\n");
2644 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
2646 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
2647 internal_error (__FILE__, __LINE__,
2648 "Invalid register number %d\n", regnum);
2650 else if (regnum >= 0 && regnum < NUM_REGS)
2652 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2653 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2655 sh_do_register (gdbarch, file, regnum); /* All other regs */
2658 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2659 sh64_do_pseudo_register (regnum);
2663 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2664 struct frame_info *frame, int regnum, int fpregs)
2666 if (regnum != -1) /* do one specified register */
2668 if (*(REGISTER_NAME (regnum)) == '\0')
2669 error ("Not a valid register for the current processor type");
2671 sh_print_register (gdbarch, file, regnum);
2674 /* do all (or most) registers */
2677 while (regnum < NUM_REGS)
2679 /* If the register name is empty, it is undefined for this
2680 processor, so don't display anything. */
2681 if (REGISTER_NAME (regnum) == NULL
2682 || *(REGISTER_NAME (regnum)) == '\0')
2688 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2692 /* true for "INFO ALL-REGISTERS" command */
2693 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
2697 regnum += FP_LAST_REGNUM - FP0_REGNUM; /* skip FP regs */
2701 sh_do_register (gdbarch, file, regnum); /* All other regs */
2707 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2709 sh64_do_pseudo_register (regnum);
2716 sh_compact_do_registers_info (int regnum, int fpregs)
2718 if (regnum != -1) /* do one specified register */
2720 if (*(REGISTER_NAME (regnum)) == '\0')
2721 error ("Not a valid register for the current processor type");
2723 if (regnum >= 0 && regnum < R0_C_REGNUM)
2724 error ("Not a valid register for the current processor mode.");
2726 sh_print_register (current_gdbarch, gdb_stdout, regnum);
2729 /* do all compact registers */
2731 regnum = R0_C_REGNUM;
2732 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
2734 sh64_do_pseudo_register (regnum);
2741 sh64_do_registers_info (int regnum, int fpregs)
2743 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
2744 sh_print_registers_info (current_gdbarch, gdb_stdout,
2745 deprecated_selected_frame, regnum, fpregs);
2747 sh_compact_do_registers_info (regnum, fpregs);
2750 #ifdef SVR4_SHARED_LIBS
2752 /* Fetch (and possibly build) an appropriate link_map_offsets structure
2753 for native i386 linux targets using the struct offsets defined in
2754 link.h (but without actual reference to that file).
2756 This makes it possible to access i386-linux shared libraries from
2757 a gdb that was not built on an i386-linux host (for cross debugging).
2760 struct link_map_offsets *
2761 sh_linux_svr4_fetch_link_map_offsets (void)
2763 static struct link_map_offsets lmo;
2764 static struct link_map_offsets *lmp = 0;
2770 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
2772 lmo.r_map_offset = 4;
2775 lmo.link_map_size = 20; /* 552 not actual size but all we need */
2777 lmo.l_addr_offset = 0;
2778 lmo.l_addr_size = 4;
2780 lmo.l_name_offset = 4;
2781 lmo.l_name_size = 4;
2783 lmo.l_next_offset = 12;
2784 lmo.l_next_size = 4;
2786 lmo.l_prev_offset = 16;
2787 lmo.l_prev_size = 4;
2792 #endif /* SVR4_SHARED_LIBS */
2794 gdbarch_init_ftype sh64_gdbarch_init;
2797 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2799 static LONGEST sh64_call_dummy_words[] = {0};
2800 struct gdbarch *gdbarch;
2801 struct gdbarch_tdep *tdep;
2803 /* If there is already a candidate, use it. */
2804 arches = gdbarch_list_lookup_by_info (arches, &info);
2806 return arches->gdbarch;
2808 /* None found, create a new architecture from the information
2810 tdep = XMALLOC (struct gdbarch_tdep);
2811 gdbarch = gdbarch_alloc (&info, tdep);
2813 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
2814 ready to unwind the PC first (see frame.c:get_prev_frame()). */
2815 set_gdbarch_deprecated_init_frame_pc (gdbarch, deprecated_init_frame_pc_default);
2817 /* Determine the ABI */
2818 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2820 /* If the ABI is the 64-bit one, it can only be sh-media. */
2821 tdep->sh_abi = SH_ABI_64;
2822 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2823 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2827 /* If the ABI is the 32-bit one it could be either media or
2829 tdep->sh_abi = SH_ABI_32;
2830 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2831 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2834 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2835 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2836 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2837 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2838 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2839 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2841 set_gdbarch_sp_regnum (gdbarch, 15);
2842 set_gdbarch_deprecated_fp_regnum (gdbarch, 14);
2844 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2845 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2847 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2849 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2850 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2851 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2852 set_gdbarch_function_start_offset (gdbarch, 0);
2854 set_gdbarch_frame_args_skip (gdbarch, 0);
2855 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
2856 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2858 set_gdbarch_deprecated_frame_saved_pc (gdbarch, sh_frame_saved_pc);
2859 set_gdbarch_deprecated_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
2860 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2862 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
2863 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2864 set_gdbarch_pc_regnum (gdbarch, 64);
2866 /* The number of real registers is the same whether we are in
2867 ISA16(compact) or ISA32(media). */
2868 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2869 set_gdbarch_deprecated_register_bytes (gdbarch,
2870 ((SIM_SH64_NR_FP_REGS + 1) * 4)
2871 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
2873 set_gdbarch_register_name (gdbarch, sh_sh64_register_name);
2874 set_gdbarch_register_type (gdbarch, sh64_register_type);
2875 set_gdbarch_deprecated_store_return_value (gdbarch, sh64_store_return_value);
2876 set_gdbarch_deprecated_register_byte (gdbarch, sh_sh64_register_byte);
2877 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2878 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2880 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
2881 set_gdbarch_deprecated_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
2882 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
2883 set_gdbarch_deprecated_call_dummy_words (gdbarch, sh64_call_dummy_words);
2884 set_gdbarch_deprecated_sizeof_call_dummy_words (gdbarch, sizeof (sh64_call_dummy_words));
2886 set_gdbarch_deprecated_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
2887 set_gdbarch_deprecated_frame_chain (gdbarch, sh64_frame_chain);
2888 set_gdbarch_deprecated_get_saved_register (gdbarch, sh64_get_saved_register);
2889 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
2890 set_gdbarch_deprecated_push_arguments (gdbarch, sh64_push_arguments);
2891 set_gdbarch_deprecated_push_return_address (gdbarch, sh64_push_return_address);
2892 set_gdbarch_deprecated_dummy_write_sp (gdbarch, deprecated_write_sp);
2893 set_gdbarch_deprecated_store_struct_return (gdbarch, sh64_store_struct_return);
2894 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
2895 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
2896 set_gdbarch_deprecated_pop_frame (gdbarch, sh64_pop_frame);
2897 set_gdbarch_elf_make_msymbol_special (gdbarch,
2898 sh64_elf_make_msymbol_special);
2900 /* Hook in ABI-specific overrides, if they have been registered. */
2901 gdbarch_init_osabi (info, gdbarch);