1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993-2017 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 /* Contributed by Steve Chamberlain
25 #include "frame-base.h"
26 #include "frame-unwind.h"
27 #include "dwarf2-frame.h"
35 #include "arch-utils.h"
38 #include "target-float.h"
40 #include "target-float.h"
46 /* Register numbers shared with the simulator. */
47 #include "gdb/sim-sh.h"
49 #include "sh64-tdep.h"
52 /* Information that is dependent on the processor variant. */
63 /* ISA-specific data types. */
64 struct type *sh_littlebyte_bigword_type;
68 sh64_littlebyte_bigword_type (struct gdbarch *gdbarch)
70 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
72 if (tdep->sh_littlebyte_bigword_type == NULL)
73 tdep->sh_littlebyte_bigword_type
74 = arch_float_type (gdbarch, -1, "builtin_type_sh_littlebyte_bigword",
75 floatformats_ieee_double_littlebyte_bigword);
77 return tdep->sh_littlebyte_bigword_type;
80 struct sh64_frame_cache
87 /* Flag showing that a frame has been created in the prologue code. */
92 /* Saved registers. */
93 CORE_ADDR saved_regs[SIM_SH64_NR_REGS];
97 /* Registers of SH5 */
101 DEFAULT_RETURN_REGNUM = 2,
102 STRUCT_RETURN_REGNUM = 2,
105 FLOAT_ARGLAST_REGNUM = 11,
106 MEDIA_FP_REGNUM = 14,
110 DR_LAST_REGNUM = 172,
111 /* FPP stands for Floating Point Pair, to avoid confusion with
112 GDB's gdbarch_fp0_regnum, which is the number of the first Floating
113 point register. Unfortunately on the sh5, the floating point
114 registers are called FR, and the floating point pairs are called FP. */
116 FPP_LAST_REGNUM = 204,
118 FV_LAST_REGNUM = 220,
120 R_LAST_C_REGNUM = 236,
127 FPSCR_C_REGNUM = 243,
130 FP_LAST_C_REGNUM = 260,
132 DR_LAST_C_REGNUM = 268,
134 FV_LAST_C_REGNUM = 272,
135 FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM,
136 SSR_REGNUM = SIM_SH64_SSR_REGNUM,
137 SPC_REGNUM = SIM_SH64_SPC_REGNUM,
138 TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7,
139 FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1
143 sh64_register_name (struct gdbarch *gdbarch, int reg_nr)
145 static const char *register_names[] =
147 /* SH MEDIA MODE (ISA 32) */
148 /* general registers (64-bit) 0-63 */
149 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
150 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
151 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
152 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
153 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
154 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
155 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
156 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
161 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
164 /* target registers (64-bit) 68-75 */
165 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
167 /* floating point state control register (32-bit) 76 */
170 /* single precision floating point registers (32-bit) 77-140 */
171 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
172 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
173 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
174 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
175 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
176 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
177 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
178 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
180 /* double precision registers (pseudo) 141-172 */
181 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
182 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
183 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
184 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
186 /* floating point pairs (pseudo) 173-204 */
187 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
188 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
189 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
190 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
192 /* floating point vectors (4 floating point regs) (pseudo) 205-220 */
193 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
194 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
196 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272 */
197 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
198 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
200 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
202 "fr0_c", "fr1_c", "fr2_c", "fr3_c",
203 "fr4_c", "fr5_c", "fr6_c", "fr7_c",
204 "fr8_c", "fr9_c", "fr10_c", "fr11_c",
205 "fr12_c", "fr13_c", "fr14_c", "fr15_c",
206 "dr0_c", "dr2_c", "dr4_c", "dr6_c",
207 "dr8_c", "dr10_c", "dr12_c", "dr14_c",
208 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
209 /* FIXME!!!! XF0 XF15, XD0 XD14 ????? */
214 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
216 return register_names[reg_nr];
219 #define NUM_PSEUDO_REGS_SH_MEDIA 80
220 #define NUM_PSEUDO_REGS_SH_COMPACT 51
222 /* Macros and functions for setting and testing a bit in a minimal
223 symbol that marks it as 32-bit function. The MSB of the minimal
224 symbol's "info" field is used for this purpose.
226 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is "special",
227 i.e. refers to a 32-bit function, and sets a "special" bit in a
228 minimal symbol to mark it as a 32-bit function
229 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol */
231 #define MSYMBOL_IS_SPECIAL(msym) \
232 MSYMBOL_TARGET_FLAG_1 (msym)
235 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
240 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
242 MSYMBOL_TARGET_FLAG_1 (msym) = 1;
243 SET_MSYMBOL_VALUE_ADDRESS (msym, MSYMBOL_VALUE_RAW_ADDRESS (msym) | 1);
247 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
248 are some macros to test, set, or clear bit 0 of addresses. */
249 #define IS_ISA32_ADDR(addr) ((addr) & 1)
250 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
251 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
254 pc_is_isa32 (bfd_vma memaddr)
256 struct bound_minimal_symbol sym;
258 /* If bit 0 of the address is set, assume this is a
259 ISA32 (shmedia) address. */
260 if (IS_ISA32_ADDR (memaddr))
263 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
264 the high bit of the info field. Use this to decide if the function is
266 sym = lookup_minimal_symbol_by_pc (memaddr);
268 return MSYMBOL_IS_SPECIAL (sym.minsym);
274 sh64_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
276 if (pc_is_isa32 (*pcptr))
278 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
285 static const gdb_byte *
286 sh64_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
290 /* The BRK instruction for shmedia is
291 01101111 11110101 11111111 11110000
292 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
293 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
295 /* The BRK instruction for shcompact is
297 which translates in big endian mode to 0x0, 0x3b
298 and in little endian mode to 0x3b, 0x0 */
302 static unsigned char big_breakpoint_media[] = {
303 0x6f, 0xf5, 0xff, 0xf0
305 static unsigned char little_breakpoint_media[] = {
306 0xf0, 0xff, 0xf5, 0x6f
309 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
310 return big_breakpoint_media;
312 return little_breakpoint_media;
316 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
317 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
319 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
320 return big_breakpoint_compact;
322 return little_breakpoint_compact;
326 /* Prologue looks like
327 [mov.l <regs>,@-r15]...
332 Actually it can be more complicated than this. For instance, with
350 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
351 with l=1 and n = 18 0110101111110001010010100aaa0000 */
352 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
354 /* STS.L PR,@-r0 0100000000100010
355 r0-4-->r0, PR-->(r0) */
356 #define IS_STS_R0(x) ((x) == 0x4022)
358 /* STS PR, Rm 0000mmmm00101010
360 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
362 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
364 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
366 /* MOV.L R14,@(disp,r15) 000111111110dddd
367 R14-->(dispx4+r15) */
368 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
370 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
371 R18-->(dispx8+R14) */
372 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
374 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
375 R18-->(dispx8+R15) */
376 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
378 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
379 R18-->(dispx4+R15) */
380 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
382 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
383 R14-->(dispx8+R15) */
384 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
386 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
387 R14-->(dispx4+R15) */
388 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
390 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
392 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
394 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
396 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
398 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
400 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
402 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
404 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
406 #define IS_MOV_SP_FP_MEDIA(x) \
407 (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
409 /* MOV #imm, R0 1110 0000 ssss ssss
411 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
413 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
414 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
416 /* ADD r15,r0 0011 0000 1111 1100
418 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
420 /* MOV.L R14 @-R0 0010 0000 1110 0110
421 R14-->(R0-4), R0-4-->R0 */
422 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
424 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
425 where Rm is one of r2-r9 which are the argument registers. */
426 /* FIXME: Recognize the float and double register moves too! */
427 #define IS_MEDIA_IND_ARG_MOV(x) \
428 ((((x) & 0xfc0ffc0f) == 0x0009fc00) \
429 && (((x) & 0x03f00000) >= 0x00200000 \
430 && ((x) & 0x03f00000) <= 0x00900000))
432 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
433 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
434 where Rm is one of r2-r9 which are the argument registers. */
435 #define IS_MEDIA_ARG_MOV(x) \
436 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
437 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
439 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000 */
440 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000 */
441 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000 */
442 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000 */
443 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000 */
444 #define IS_MEDIA_MOV_TO_R14(x) \
445 ((((x) & 0xfffffc0f) == 0xa0e00000) \
446 || (((x) & 0xfffffc0f) == 0xa4e00000) \
447 || (((x) & 0xfffffc0f) == 0xa8e00000) \
448 || (((x) & 0xfffffc0f) == 0xb4e00000) \
449 || (((x) & 0xfffffc0f) == 0xbce00000))
451 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
453 #define IS_COMPACT_IND_ARG_MOV(x) \
454 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) \
455 && (((x) & 0x00f0) <= 0x0090))
457 /* compact direct arg move!
458 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
459 #define IS_COMPACT_ARG_MOV(x) \
460 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) \
461 && ((x) & 0x00f0) <= 0x0090))
463 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
464 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
465 #define IS_COMPACT_MOV_TO_R14(x) \
466 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
468 #define IS_JSR_R0(x) ((x) == 0x400b)
469 #define IS_NOP(x) ((x) == 0x0009)
472 /* MOV r15,r14 0110111011110011
474 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
476 /* ADD #imm,r15 01111111iiiiiiii
478 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
480 /* Skip any prologue before the guts of a function. */
482 /* Skip the prologue using the debug information. If this fails we'll
483 fall back on the 'guess' method below. */
485 after_prologue (CORE_ADDR pc)
487 struct symtab_and_line sal;
488 CORE_ADDR func_addr, func_end;
490 /* If we can not find the symbol in the partial symbol table, then
491 there is no hope we can determine the function's start address
493 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
497 /* Get the line associated with FUNC_ADDR. */
498 sal = find_pc_line (func_addr, 0);
500 /* There are only two cases to consider. First, the end of the source line
501 is within the function bounds. In that case we return the end of the
502 source line. Second is the end of the source line extends beyond the
503 bounds of the current function. We need to use the slow code to
504 examine instructions in that case. */
505 if (sal.end < func_end)
512 look_for_args_moves (struct gdbarch *gdbarch,
513 CORE_ADDR start_pc, int media_mode)
515 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
518 int insn_size = (media_mode ? 4 : 2);
520 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
524 w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
525 insn_size, byte_order);
527 if (IS_MEDIA_IND_ARG_MOV (w))
529 /* This must be followed by a store to r14, so the argument
530 is where the debug info says it is. This can happen after
531 the SP has been saved, unfortunately. */
533 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
534 insn_size, byte_order);
536 if (IS_MEDIA_MOV_TO_R14 (next_insn))
539 else if (IS_MEDIA_ARG_MOV (w))
541 /* These instructions store directly the argument in r14. */
549 w = read_memory_integer (here, insn_size, byte_order);
552 if (IS_COMPACT_IND_ARG_MOV (w))
554 /* This must be followed by a store to r14, so the argument
555 is where the debug info says it is. This can happen after
556 the SP has been saved, unfortunately. */
558 int next_insn = 0xffff & read_memory_integer (here, insn_size,
561 if (IS_COMPACT_MOV_TO_R14 (next_insn))
564 else if (IS_COMPACT_ARG_MOV (w))
566 /* These instructions store directly the argument in r14. */
569 else if (IS_MOVL_R0 (w))
571 /* There is a function that gcc calls to get the arguments
572 passed correctly to the function. Only after this
573 function call the arguments will be found at the place
574 where they are supposed to be. This happens in case the
575 argument has to be stored into a 64-bit register (for
576 instance doubles, long longs). SHcompact doesn't have
577 access to the full 64-bits, so we store the register in
578 stack slot and store the address of the stack slot in
579 the register, then do a call through a wrapper that
580 loads the memory value into the register. A SHcompact
581 callee calls an argument decoder
582 (GCC_shcompact_incoming_args) that stores the 64-bit
583 value in a stack slot and stores the address of the
584 stack slot in the register. GCC thinks the argument is
585 just passed by transparent reference, but this is only
586 true after the argument decoder is called. Such a call
587 needs to be considered part of the prologue. */
589 /* This must be followed by a JSR @r0 instruction and by
590 a NOP instruction. After these, the prologue is over! */
592 int next_insn = 0xffff & read_memory_integer (here, insn_size,
595 if (IS_JSR_R0 (next_insn))
597 next_insn = 0xffff & read_memory_integer (here, insn_size,
601 if (IS_NOP (next_insn))
614 sh64_skip_prologue_hard_way (struct gdbarch *gdbarch, CORE_ADDR start_pc)
616 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
625 if (pc_is_isa32 (start_pc) == 0)
631 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
636 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here),
637 insn_size, byte_order);
639 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
640 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
641 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w)
642 || IS_PTABSL_R18 (w))
646 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
654 /* Don't bail out yet, we may have arguments stored in
655 registers here, according to the debug info, so that
656 gdb can print the frames correctly. */
657 start_pc = look_for_args_moves (gdbarch,
658 here - insn_size, media_mode);
664 int w = 0xffff & read_memory_integer (here, insn_size, byte_order);
667 if (IS_STS_R0 (w) || IS_STS_PR (w)
668 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
669 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
673 else if (IS_MOV_SP_FP (w))
681 /* Don't bail out yet, we may have arguments stored in
682 registers here, according to the debug info, so that
683 gdb can print the frames correctly. */
684 start_pc = look_for_args_moves (gdbarch,
685 here - insn_size, media_mode);
695 sh64_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
697 CORE_ADDR post_prologue_pc;
699 /* See if we can determine the end of the prologue via the symbol table.
700 If so, then return either PC, or the PC after the prologue, whichever
702 post_prologue_pc = after_prologue (pc);
704 /* If after_prologue returned a useful address, then use it. Else
705 fall back on the instruction skipping code. */
706 if (post_prologue_pc != 0)
707 return std::max (pc, post_prologue_pc);
709 return sh64_skip_prologue_hard_way (gdbarch, pc);
712 /* Should call_function allocate stack space for a struct return? */
714 sh64_use_struct_convention (struct type *type)
716 return (TYPE_LENGTH (type) > 8);
719 /* For vectors of 4 floating point registers. */
721 sh64_fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
725 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fv_regnum - FV0_REGNUM) * 4;
729 /* For double precision floating point registers, i.e 2 fp regs. */
731 sh64_dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
735 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (dr_regnum - DR0_REGNUM) * 2;
739 /* For pairs of floating point registers. */
741 sh64_fpp_reg_base_num (struct gdbarch *gdbarch, int fpp_regnum)
745 fp_regnum = gdbarch_fp0_regnum (gdbarch) + (fpp_regnum - FPP0_REGNUM) * 2;
751 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
752 GDB_REGNUM BASE_REGNUM
812 sh64_compact_reg_base_num (struct gdbarch *gdbarch, int reg_nr)
814 int base_regnum = reg_nr;
816 /* general register N maps to general register N */
817 if (reg_nr >= R0_C_REGNUM
818 && reg_nr <= R_LAST_C_REGNUM)
819 base_regnum = reg_nr - R0_C_REGNUM;
821 /* floating point register N maps to floating point register N */
822 else if (reg_nr >= FP0_C_REGNUM
823 && reg_nr <= FP_LAST_C_REGNUM)
824 base_regnum = reg_nr - FP0_C_REGNUM + gdbarch_fp0_regnum (gdbarch);
826 /* double prec register N maps to base regnum for double prec register N */
827 else if (reg_nr >= DR0_C_REGNUM
828 && reg_nr <= DR_LAST_C_REGNUM)
829 base_regnum = sh64_dr_reg_base_num (gdbarch,
830 DR0_REGNUM + reg_nr - DR0_C_REGNUM);
832 /* vector N maps to base regnum for vector register N */
833 else if (reg_nr >= FV0_C_REGNUM
834 && reg_nr <= FV_LAST_C_REGNUM)
835 base_regnum = sh64_fv_reg_base_num (gdbarch,
836 FV0_REGNUM + reg_nr - FV0_C_REGNUM);
838 else if (reg_nr == PC_C_REGNUM)
839 base_regnum = gdbarch_pc_regnum (gdbarch);
841 else if (reg_nr == GBR_C_REGNUM)
844 else if (reg_nr == MACH_C_REGNUM
845 || reg_nr == MACL_C_REGNUM)
848 else if (reg_nr == PR_C_REGNUM)
849 base_regnum = PR_REGNUM;
851 else if (reg_nr == T_C_REGNUM)
854 else if (reg_nr == FPSCR_C_REGNUM)
855 base_regnum = FPSCR_REGNUM; /*???? this register is a mess. */
857 else if (reg_nr == FPUL_C_REGNUM)
858 base_regnum = gdbarch_fp0_regnum (gdbarch) + 32;
864 sign_extend (int value, int bits)
866 value = value & ((1 << bits) - 1);
867 return (value & (1 << (bits - 1))
868 ? value | (~((1 << bits) - 1))
873 sh64_analyze_prologue (struct gdbarch *gdbarch,
874 struct sh64_frame_cache *cache,
876 CORE_ADDR current_pc)
883 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
885 cache->sp_offset = 0;
887 /* Loop around examining the prologue insns until we find something
888 that does not appear to be part of the prologue. But give up
889 after 20 of them, since we're getting silly then. */
893 if (cache->media_mode)
898 opc = pc + (insn_size * 28);
899 if (opc > current_pc)
901 for ( ; pc <= opc; pc += insn_size)
903 insn = read_memory_integer (cache->media_mode ? UNMAKE_ISA32_ADDR (pc)
905 insn_size, byte_order);
907 if (!cache->media_mode)
909 if (IS_STS_PR (insn))
911 int next_insn = read_memory_integer (pc + insn_size,
912 insn_size, byte_order);
913 if (IS_MOV_TO_R15 (next_insn))
915 cache->saved_regs[PR_REGNUM]
916 = cache->sp_offset - ((((next_insn & 0xf) ^ 0x8)
922 else if (IS_MOV_R14 (insn))
924 cache->saved_regs[MEDIA_FP_REGNUM] =
925 cache->sp_offset - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
929 else if (IS_MOV_R0 (insn))
931 /* Put in R0 the offset from SP at which to store some
932 registers. We are interested in this value, because it
933 will tell us where the given registers are stored within
935 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
938 else if (IS_ADD_SP_R0 (insn))
940 /* This instruction still prepares r0, but we don't care.
941 We already have the offset in r0_val. */
944 else if (IS_STS_R0 (insn))
946 /* Store PR at r0_val-4 from SP. Decrement r0 by 4. */
947 cache->saved_regs[PR_REGNUM] = cache->sp_offset - (r0_val - 4);
951 else if (IS_MOV_R14_R0 (insn))
953 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4. */
954 cache->saved_regs[MEDIA_FP_REGNUM] = cache->sp_offset
960 else if (IS_ADD_SP (insn))
961 cache->sp_offset -= ((insn & 0xff) ^ 0x80) - 0x80;
963 else if (IS_MOV_SP_FP (insn))
968 if (IS_ADDIL_SP_MEDIA (insn) || IS_ADDI_SP_MEDIA (insn))
970 sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
972 else if (IS_STQ_R18_R15 (insn))
973 cache->saved_regs[PR_REGNUM]
974 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
977 else if (IS_STL_R18_R15 (insn))
978 cache->saved_regs[PR_REGNUM]
979 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
982 else if (IS_STQ_R14_R15 (insn))
984 cache->saved_regs[MEDIA_FP_REGNUM]
985 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
990 else if (IS_STL_R14_R15 (insn))
992 cache->saved_regs[MEDIA_FP_REGNUM]
993 = cache->sp_offset - (sign_extend ((insn & 0xffc00) >> 10,
998 else if (IS_MOV_SP_FP_MEDIA (insn))
1005 sh64_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
1010 /* Function: push_dummy_call
1011 Setup the function arguments for calling a function in the inferior.
1013 On the Renesas SH architecture, there are four registers (R4 to R7)
1014 which are dedicated for passing function arguments. Up to the first
1015 four arguments (depending on size) may go into these registers.
1016 The rest go on the stack.
1018 Arguments that are smaller than 4 bytes will still take up a whole
1019 register or a whole 32-bit word on the stack, and will be
1020 right-justified in the register or the stack word. This includes
1021 chars, shorts, and small aggregate types.
1023 Arguments that are larger than 4 bytes may be split between two or
1024 more registers. If there are not enough registers free, an argument
1025 may be passed partly in a register (or registers), and partly on the
1026 stack. This includes doubles, long longs, and larger aggregates.
1027 As far as I know, there is no upper limit to the size of aggregates
1028 that will be passed in this way; in other words, the convention of
1029 passing a pointer to a large aggregate instead of a copy is not used.
1031 An exceptional case exists for struct arguments (and possibly other
1032 aggregates such as arrays) if the size is larger than 4 bytes but
1033 not a multiple of 4 bytes. In this case the argument is never split
1034 between the registers and the stack, but instead is copied in its
1035 entirety onto the stack, AND also copied into as many registers as
1036 there is room for. In other words, space in registers permitting,
1037 two copies of the same argument are passed in. As far as I can tell,
1038 only the one on the stack is used, although that may be a function
1039 of the level of compiler optimization. I suspect this is a compiler
1040 bug. Arguments of these odd sizes are left-justified within the
1041 word (as opposed to arguments smaller than 4 bytes, which are
1044 If the function is to return an aggregate type such as a struct, it
1045 is either returned in the normal return value register R0 (if its
1046 size is no greater than one byte), or else the caller must allocate
1047 space into which the callee will copy the return value (if the size
1048 is greater than one byte). In this case, a pointer to the return
1049 value location is passed into the callee in register R2, which does
1050 not displace any of the other arguments passed in via registers R4
1053 /* R2-R9 for integer types and integer equivalent (char, pointers) and
1054 non-scalar (struct, union) elements (even if the elements are
1056 FR0-FR11 for single precision floating point (float)
1057 DR0-DR10 for double precision floating point (double)
1059 If a float is argument number 3 (for instance) and arguments number
1060 1,2, and 4 are integer, the mapping will be:
1061 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
1063 If a float is argument number 10 (for instance) and arguments number
1064 1 through 10 are integer, the mapping will be:
1065 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
1066 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0,
1067 arg11->stack(16,SP). I.e. there is hole in the stack.
1069 Different rules apply for variable arguments functions, and for functions
1070 for which the prototype is not known. */
1073 sh64_push_dummy_call (struct gdbarch *gdbarch,
1074 struct value *function,
1075 struct regcache *regcache,
1077 int nargs, struct value **args,
1078 CORE_ADDR sp, int struct_return,
1079 CORE_ADDR struct_addr)
1081 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1082 int stack_offset, stack_alloc;
1084 int float_arg_index = 0;
1085 int double_arg_index = 0;
1089 const gdb_byte *val;
1095 memset (fp_args, 0, sizeof (fp_args));
1097 /* First force sp to a 8-byte alignment. */
1098 sp = sh64_frame_align (gdbarch, sp);
1100 /* The "struct return pointer" pseudo-argument has its own dedicated
1104 regcache_cooked_write_unsigned (regcache,
1105 STRUCT_RETURN_REGNUM, struct_addr);
1107 /* Now make sure there's space on the stack. */
1108 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
1109 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 7) & ~7);
1110 sp -= stack_alloc; /* Make room on stack for args. */
1112 /* Now load as many as possible of the first arguments into
1113 registers, and push the rest onto the stack. There are 64 bytes
1114 in eight registers available. Loop thru args from first to last. */
1116 int_argreg = ARG0_REGNUM;
1118 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
1120 type = value_type (args[argnum]);
1121 len = TYPE_LENGTH (type);
1122 memset (valbuf, 0, sizeof (valbuf));
1124 if (TYPE_CODE (type) != TYPE_CODE_FLT)
1126 argreg_size = register_size (gdbarch, int_argreg);
1128 if (len < argreg_size)
1130 /* value gets right-justified in the register or stack word. */
1131 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1132 memcpy (valbuf + argreg_size - len,
1133 value_contents (args[argnum]), len);
1135 memcpy (valbuf, value_contents (args[argnum]), len);
1140 val = value_contents (args[argnum]);
1144 if (int_argreg > ARGLAST_REGNUM)
1146 /* Must go on the stack. */
1147 write_memory (sp + stack_offset, val, argreg_size);
1148 stack_offset += 8;/*argreg_size;*/
1150 /* NOTE WELL!!!!! This is not an "else if" clause!!!
1151 That's because some *&^%$ things get passed on the stack
1152 AND in the registers! */
1153 if (int_argreg <= ARGLAST_REGNUM)
1155 /* There's room in a register. */
1156 regval = extract_unsigned_integer (val, argreg_size,
1158 regcache_cooked_write_unsigned (regcache,
1159 int_argreg, regval);
1161 /* Store the value 8 bytes at a time. This means that
1162 things larger than 8 bytes may go partly in registers
1163 and partly on the stack. FIXME: argreg is incremented
1164 before we use its size. */
1172 val = value_contents (args[argnum]);
1175 /* Where is it going to be stored? */
1176 while (fp_args[float_arg_index])
1179 /* Now float_argreg points to the register where it
1180 should be stored. Are we still within the allowed
1182 if (float_arg_index <= FLOAT_ARGLAST_REGNUM)
1184 /* Goes in FR0...FR11 */
1185 regcache_cooked_write (regcache,
1186 gdbarch_fp0_regnum (gdbarch)
1189 fp_args[float_arg_index] = 1;
1190 /* Skip the corresponding general argument register. */
1195 /* Store it as the integers, 8 bytes at the time, if
1196 necessary spilling on the stack. */
1201 /* Where is it going to be stored? */
1202 while (fp_args[double_arg_index])
1203 double_arg_index += 2;
1204 /* Now double_argreg points to the register
1205 where it should be stored.
1206 Are we still within the allowed register set? */
1207 if (double_arg_index < FLOAT_ARGLAST_REGNUM)
1209 /* Goes in DR0...DR10 */
1210 /* The numbering of the DRi registers is consecutive,
1211 i.e. includes odd numbers. */
1212 int double_register_offset = double_arg_index / 2;
1213 int regnum = DR0_REGNUM + double_register_offset;
1214 regcache_cooked_write (regcache, regnum, val);
1215 fp_args[double_arg_index] = 1;
1216 fp_args[double_arg_index + 1] = 1;
1217 /* Skip the corresponding general argument register. */
1222 /* Store it as the integers, 8 bytes at the time, if
1223 necessary spilling on the stack. */
1228 /* Store return address. */
1229 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1231 /* Update stack pointer. */
1232 regcache_cooked_write_unsigned (regcache,
1233 gdbarch_sp_regnum (gdbarch), sp);
1238 /* Find a function's return value in the appropriate registers (in
1239 regbuf), and copy it into valbuf. Extract from an array REGBUF
1240 containing the (raw) register state a function return value of type
1241 TYPE, and copy that, in virtual format, into VALBUF. */
1243 sh64_extract_return_value (struct type *type, struct regcache *regcache,
1246 struct gdbarch *gdbarch = regcache->arch ();
1247 int len = TYPE_LENGTH (type);
1249 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1253 /* Return value stored in gdbarch_fp0_regnum. */
1254 regcache_raw_read (regcache,
1255 gdbarch_fp0_regnum (gdbarch), valbuf);
1259 /* return value stored in DR0_REGNUM. */
1261 regcache_cooked_read (regcache, DR0_REGNUM, buf);
1263 target_float_convert (buf, sh64_littlebyte_bigword_type (gdbarch),
1273 /* Result is in register 2. If smaller than 8 bytes, it is padded
1274 at the most significant end. */
1275 regcache_raw_read (regcache, DEFAULT_RETURN_REGNUM, buf);
1277 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1278 offset = register_size (gdbarch, DEFAULT_RETURN_REGNUM)
1282 memcpy (valbuf, buf + offset, len);
1285 error (_("bad size for return value"));
1289 /* Write into appropriate registers a function return value
1290 of type TYPE, given in virtual format.
1291 If the architecture is sh4 or sh3e, store a function's return value
1292 in the R0 general register or in the FP0 floating point register,
1293 depending on the type of the return value. In all the other cases
1294 the result is stored in r0, left-justified. */
1297 sh64_store_return_value (struct type *type, struct regcache *regcache,
1298 const gdb_byte *valbuf)
1300 struct gdbarch *gdbarch = regcache->arch ();
1301 gdb_byte buf[64]; /* more than enough... */
1302 int len = TYPE_LENGTH (type);
1304 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1306 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1307 for (i = 0; i < len; i += 4)
1308 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1309 regcache_raw_write (regcache, regnum++,
1310 valbuf + len - 4 - i);
1312 regcache_raw_write (regcache, regnum++, valbuf + i);
1316 int return_register = DEFAULT_RETURN_REGNUM;
1319 if (len <= register_size (gdbarch, return_register))
1321 /* Pad with zeros. */
1322 memset (buf, 0, register_size (gdbarch, return_register));
1323 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1324 offset = 0; /*register_size (gdbarch,
1325 return_register) - len;*/
1327 offset = register_size (gdbarch, return_register) - len;
1329 memcpy (buf + offset, valbuf, len);
1330 regcache_raw_write (regcache, return_register, buf);
1333 regcache_raw_write (regcache, return_register, valbuf);
1337 static enum return_value_convention
1338 sh64_return_value (struct gdbarch *gdbarch, struct value *function,
1339 struct type *type, struct regcache *regcache,
1340 gdb_byte *readbuf, const gdb_byte *writebuf)
1342 if (sh64_use_struct_convention (type))
1343 return RETURN_VALUE_STRUCT_CONVENTION;
1345 sh64_store_return_value (type, regcache, writebuf);
1347 sh64_extract_return_value (type, regcache, readbuf);
1348 return RETURN_VALUE_REGISTER_CONVENTION;
1353 SH MEDIA MODE (ISA 32)
1354 general registers (64-bit) 0-63
1355 0 r0, r1, r2, r3, r4, r5, r6, r7,
1356 64 r8, r9, r10, r11, r12, r13, r14, r15,
1357 128 r16, r17, r18, r19, r20, r21, r22, r23,
1358 192 r24, r25, r26, r27, r28, r29, r30, r31,
1359 256 r32, r33, r34, r35, r36, r37, r38, r39,
1360 320 r40, r41, r42, r43, r44, r45, r46, r47,
1361 384 r48, r49, r50, r51, r52, r53, r54, r55,
1362 448 r56, r57, r58, r59, r60, r61, r62, r63,
1367 status reg., saved status reg., saved pc reg. (64-bit) 65-67
1370 target registers (64-bit) 68-75
1371 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
1373 floating point state control register (32-bit) 76
1376 single precision floating point registers (32-bit) 77-140
1377 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
1378 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
1379 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
1380 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
1381 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
1382 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
1383 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
1384 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
1386 TOTAL SPACE FOR REGISTERS: 868 bytes
1388 From here on they are all pseudo registers: no memory allocated.
1389 REGISTER_BYTE returns the register byte for the base register.
1391 double precision registers (pseudo) 141-172
1392 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
1393 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
1394 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
1395 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
1397 floating point pairs (pseudo) 173-204
1398 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
1399 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
1400 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
1401 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
1403 floating point vectors (4 floating point regs) (pseudo) 205-220
1404 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
1405 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
1407 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1408 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
1409 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
1411 gbr_c, mach_c, macl_c, pr_c, t_c,
1413 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
1414 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
1415 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
1416 fv0_c, fv4_c, fv8_c, fv12_c
1419 static struct type *
1420 sh64_build_float_register_type (struct gdbarch *gdbarch, int high)
1422 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
1426 /* Return the GDB type object for the "standard" data type
1427 of data in register REG_NR. */
1428 static struct type *
1429 sh64_register_type (struct gdbarch *gdbarch, int reg_nr)
1431 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
1432 && reg_nr <= FP_LAST_REGNUM)
1433 || (reg_nr >= FP0_C_REGNUM
1434 && reg_nr <= FP_LAST_C_REGNUM))
1435 return builtin_type (gdbarch)->builtin_float;
1436 else if ((reg_nr >= DR0_REGNUM
1437 && reg_nr <= DR_LAST_REGNUM)
1438 || (reg_nr >= DR0_C_REGNUM
1439 && reg_nr <= DR_LAST_C_REGNUM))
1440 return builtin_type (gdbarch)->builtin_double;
1441 else if (reg_nr >= FPP0_REGNUM
1442 && reg_nr <= FPP_LAST_REGNUM)
1443 return sh64_build_float_register_type (gdbarch, 1);
1444 else if ((reg_nr >= FV0_REGNUM
1445 && reg_nr <= FV_LAST_REGNUM)
1446 ||(reg_nr >= FV0_C_REGNUM
1447 && reg_nr <= FV_LAST_C_REGNUM))
1448 return sh64_build_float_register_type (gdbarch, 3);
1449 else if (reg_nr == FPSCR_REGNUM)
1450 return builtin_type (gdbarch)->builtin_int;
1451 else if (reg_nr >= R0_C_REGNUM
1452 && reg_nr < FP0_C_REGNUM)
1453 return builtin_type (gdbarch)->builtin_int;
1455 return builtin_type (gdbarch)->builtin_long_long;
1459 sh64_register_convert_to_virtual (struct gdbarch *gdbarch, int regnum,
1460 struct type *type, gdb_byte *from, gdb_byte *to)
1462 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1464 /* It is a no-op. */
1465 memcpy (to, from, register_size (gdbarch, regnum));
1469 if ((regnum >= DR0_REGNUM
1470 && regnum <= DR_LAST_REGNUM)
1471 || (regnum >= DR0_C_REGNUM
1472 && regnum <= DR_LAST_C_REGNUM))
1473 target_float_convert (from, sh64_littlebyte_bigword_type (gdbarch),
1476 error (_("sh64_register_convert_to_virtual "
1477 "called with non DR register number"));
1481 sh64_register_convert_to_raw (struct gdbarch *gdbarch, struct type *type,
1482 int regnum, const gdb_byte *from, gdb_byte *to)
1484 if (gdbarch_byte_order (gdbarch) != BFD_ENDIAN_LITTLE)
1486 /* It is a no-op. */
1487 memcpy (to, from, register_size (gdbarch, regnum));
1491 if ((regnum >= DR0_REGNUM
1492 && regnum <= DR_LAST_REGNUM)
1493 || (regnum >= DR0_C_REGNUM
1494 && regnum <= DR_LAST_C_REGNUM))
1495 target_float_convert (from, type,
1496 to, sh64_littlebyte_bigword_type (gdbarch));
1498 error (_("sh64_register_convert_to_raw called "
1499 "with non DR register number"));
1502 /* Concatenate PORTIONS contiguous raw registers starting at
1503 BASE_REGNUM into BUFFER. */
1505 static enum register_status
1506 pseudo_register_read_portions (struct gdbarch *gdbarch,
1507 struct regcache *regcache,
1509 int base_regnum, gdb_byte *buffer)
1513 for (portion = 0; portion < portions; portion++)
1515 enum register_status status;
1518 b = buffer + register_size (gdbarch, base_regnum) * portion;
1519 status = regcache_raw_read (regcache, base_regnum + portion, b);
1520 if (status != REG_VALID)
1527 static enum register_status
1528 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1529 int reg_nr, gdb_byte *buffer)
1531 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1534 enum register_status status;
1536 if (reg_nr >= DR0_REGNUM
1537 && reg_nr <= DR_LAST_REGNUM)
1539 gdb_byte temp_buffer[8];
1540 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1542 /* Build the value in the provided buffer. */
1543 /* DR regs are double precision registers obtained by
1544 concatenating 2 single precision floating point registers. */
1545 status = pseudo_register_read_portions (gdbarch, regcache,
1546 2, base_regnum, temp_buffer);
1547 if (status == REG_VALID)
1549 /* We must pay attention to the endianness. */
1550 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1551 register_type (gdbarch, reg_nr),
1552 temp_buffer, buffer);
1558 else if (reg_nr >= FPP0_REGNUM
1559 && reg_nr <= FPP_LAST_REGNUM)
1561 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1563 /* Build the value in the provided buffer. */
1564 /* FPP regs are pairs of single precision registers obtained by
1565 concatenating 2 single precision floating point registers. */
1566 return pseudo_register_read_portions (gdbarch, regcache,
1567 2, base_regnum, buffer);
1570 else if (reg_nr >= FV0_REGNUM
1571 && reg_nr <= FV_LAST_REGNUM)
1573 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1575 /* Build the value in the provided buffer. */
1576 /* FV regs are vectors of single precision registers obtained by
1577 concatenating 4 single precision floating point registers. */
1578 return pseudo_register_read_portions (gdbarch, regcache,
1579 4, base_regnum, buffer);
1582 /* sh compact pseudo registers. 1-to-1 with a shmedia register. */
1583 else if (reg_nr >= R0_C_REGNUM
1584 && reg_nr <= T_C_REGNUM)
1586 gdb_byte temp_buffer[8];
1587 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1589 /* Build the value in the provided buffer. */
1590 status = regcache_raw_read (regcache, base_regnum, temp_buffer);
1591 if (status != REG_VALID)
1593 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1596 temp_buffer + offset, 4); /* get LOWER 32 bits only???? */
1600 else if (reg_nr >= FP0_C_REGNUM
1601 && reg_nr <= FP_LAST_C_REGNUM)
1603 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1605 /* Build the value in the provided buffer. */
1606 /* Floating point registers map 1-1 to the media fp regs,
1607 they have the same size and endianness. */
1608 return regcache_raw_read (regcache, base_regnum, buffer);
1611 else if (reg_nr >= DR0_C_REGNUM
1612 && reg_nr <= DR_LAST_C_REGNUM)
1614 gdb_byte temp_buffer[8];
1615 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1617 /* DR_C regs are double precision registers obtained by
1618 concatenating 2 single precision floating point registers. */
1619 status = pseudo_register_read_portions (gdbarch, regcache,
1620 2, base_regnum, temp_buffer);
1621 if (status == REG_VALID)
1623 /* We must pay attention to the endianness. */
1624 sh64_register_convert_to_virtual (gdbarch, reg_nr,
1625 register_type (gdbarch, reg_nr),
1626 temp_buffer, buffer);
1631 else if (reg_nr >= FV0_C_REGNUM
1632 && reg_nr <= FV_LAST_C_REGNUM)
1634 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1636 /* Build the value in the provided buffer. */
1637 /* FV_C regs are vectors of single precision registers obtained by
1638 concatenating 4 single precision floating point registers. */
1639 return pseudo_register_read_portions (gdbarch, regcache,
1640 4, base_regnum, buffer);
1643 else if (reg_nr == FPSCR_C_REGNUM)
1645 int fpscr_base_regnum;
1647 ULONGEST fpscr_value;
1649 unsigned int fpscr_c_value;
1650 unsigned int fpscr_c_part1_value;
1651 unsigned int fpscr_c_part2_value;
1653 fpscr_base_regnum = FPSCR_REGNUM;
1654 sr_base_regnum = SR_REGNUM;
1656 /* Build the value in the provided buffer. */
1657 /* FPSCR_C is a very weird register that contains sparse bits
1658 from the FPSCR and the SR architectural registers.
1665 2-17 Bit 2-18 of FPSCR
1666 18-20 Bits 12,13,14 of SR
1670 /* Get FPSCR as an int. */
1671 status = regcache->raw_read (fpscr_base_regnum, &fpscr_value);
1672 if (status != REG_VALID)
1674 /* Get SR as an int. */
1675 status = regcache->raw_read (sr_base_regnum, &sr_value);
1676 if (status != REG_VALID)
1678 /* Build the new value. */
1679 fpscr_c_part1_value = fpscr_value & 0x3fffd;
1680 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
1681 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
1682 /* Store that in out buffer!!! */
1683 store_unsigned_integer (buffer, 4, byte_order, fpscr_c_value);
1684 /* FIXME There is surely an endianness gotcha here. */
1689 else if (reg_nr == FPUL_C_REGNUM)
1691 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1693 /* FPUL_C register is floating point register 32,
1694 same size, same endianness. */
1695 return regcache_raw_read (regcache, base_regnum, buffer);
1698 gdb_assert_not_reached ("invalid pseudo register number");
1702 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1703 int reg_nr, const gdb_byte *buffer)
1705 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1706 int base_regnum, portion;
1709 if (reg_nr >= DR0_REGNUM
1710 && reg_nr <= DR_LAST_REGNUM)
1712 gdb_byte temp_buffer[8];
1713 base_regnum = sh64_dr_reg_base_num (gdbarch, reg_nr);
1714 /* We must pay attention to the endianness. */
1715 sh64_register_convert_to_raw (gdbarch, register_type (gdbarch, reg_nr),
1717 buffer, temp_buffer);
1719 /* Write the real regs for which this one is an alias. */
1720 for (portion = 0; portion < 2; portion++)
1721 regcache_raw_write (regcache, base_regnum + portion,
1723 + register_size (gdbarch,
1724 base_regnum) * portion));
1727 else if (reg_nr >= FPP0_REGNUM
1728 && reg_nr <= FPP_LAST_REGNUM)
1730 base_regnum = sh64_fpp_reg_base_num (gdbarch, reg_nr);
1732 /* Write the real regs for which this one is an alias. */
1733 for (portion = 0; portion < 2; portion++)
1734 regcache_raw_write (regcache, base_regnum + portion,
1735 (buffer + register_size (gdbarch,
1736 base_regnum) * portion));
1739 else if (reg_nr >= FV0_REGNUM
1740 && reg_nr <= FV_LAST_REGNUM)
1742 base_regnum = sh64_fv_reg_base_num (gdbarch, reg_nr);
1744 /* Write the real regs for which this one is an alias. */
1745 for (portion = 0; portion < 4; portion++)
1746 regcache_raw_write (regcache, base_regnum + portion,
1747 (buffer + register_size (gdbarch,
1748 base_regnum) * portion));
1751 /* sh compact general pseudo registers. 1-to-1 with a shmedia
1752 register but only 4 bytes of it. */
1753 else if (reg_nr >= R0_C_REGNUM
1754 && reg_nr <= T_C_REGNUM)
1756 gdb_byte temp_buffer[8];
1757 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1758 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1759 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1763 /* Let's read the value of the base register into a temporary
1764 buffer, so that overwriting the last four bytes with the new
1765 value of the pseudo will leave the upper 4 bytes unchanged. */
1766 regcache_raw_read (regcache, base_regnum, temp_buffer);
1767 /* Write as an 8 byte quantity. */
1768 memcpy (temp_buffer + offset, buffer, 4);
1769 regcache_raw_write (regcache, base_regnum, temp_buffer);
1772 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
1773 registers. Both are 4 bytes. */
1774 else if (reg_nr >= FP0_C_REGNUM
1775 && reg_nr <= FP_LAST_C_REGNUM)
1777 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1778 regcache_raw_write (regcache, base_regnum, buffer);
1781 else if (reg_nr >= DR0_C_REGNUM
1782 && reg_nr <= DR_LAST_C_REGNUM)
1784 gdb_byte temp_buffer[8];
1785 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1786 for (portion = 0; portion < 2; portion++)
1788 /* We must pay attention to the endianness. */
1789 sh64_register_convert_to_raw (gdbarch,
1790 register_type (gdbarch, reg_nr),
1792 buffer, temp_buffer);
1794 regcache_raw_write (regcache, base_regnum + portion,
1796 + register_size (gdbarch,
1797 base_regnum) * portion));
1801 else if (reg_nr >= FV0_C_REGNUM
1802 && reg_nr <= FV_LAST_C_REGNUM)
1804 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1806 for (portion = 0; portion < 4; portion++)
1808 regcache_raw_write (regcache, base_regnum + portion,
1810 + register_size (gdbarch,
1811 base_regnum) * portion));
1815 else if (reg_nr == FPSCR_C_REGNUM)
1817 int fpscr_base_regnum;
1819 ULONGEST fpscr_value;
1821 ULONGEST old_fpscr_value;
1822 ULONGEST old_sr_value;
1823 unsigned int fpscr_c_value;
1824 unsigned int fpscr_mask;
1825 unsigned int sr_mask;
1827 fpscr_base_regnum = FPSCR_REGNUM;
1828 sr_base_regnum = SR_REGNUM;
1830 /* FPSCR_C is a very weird register that contains sparse bits
1831 from the FPSCR and the SR architectural registers.
1838 2-17 Bit 2-18 of FPSCR
1839 18-20 Bits 12,13,14 of SR
1843 /* Get value as an int. */
1844 fpscr_c_value = extract_unsigned_integer (buffer, 4, byte_order);
1846 /* Build the new values. */
1847 fpscr_mask = 0x0003fffd;
1848 sr_mask = 0x001c0000;
1850 fpscr_value = fpscr_c_value & fpscr_mask;
1851 sr_value = (fpscr_value & sr_mask) >> 6;
1853 regcache->raw_read (fpscr_base_regnum, &old_fpscr_value);
1854 old_fpscr_value &= 0xfffc0002;
1855 fpscr_value |= old_fpscr_value;
1856 regcache->raw_write (fpscr_base_regnum, fpscr_value);
1858 regcache->raw_read (sr_base_regnum, &old_sr_value);
1859 old_sr_value &= 0xffff8fff;
1860 sr_value |= old_sr_value;
1861 regcache->raw_write (sr_base_regnum, sr_value);
1864 else if (reg_nr == FPUL_C_REGNUM)
1866 base_regnum = sh64_compact_reg_base_num (gdbarch, reg_nr);
1867 regcache_raw_write (regcache, base_regnum, buffer);
1871 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
1872 shmedia REGISTERS. */
1873 /* Control registers, compact mode. */
1875 sh64_do_cr_c_register_info (struct ui_file *file, struct frame_info *frame,
1878 switch (cr_c_regnum)
1881 fprintf_filtered (file, "pc_c\t0x%08x\n",
1882 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1885 fprintf_filtered (file, "gbr_c\t0x%08x\n",
1886 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1889 fprintf_filtered (file, "mach_c\t0x%08x\n",
1890 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1893 fprintf_filtered (file, "macl_c\t0x%08x\n",
1894 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1897 fprintf_filtered (file, "pr_c\t0x%08x\n",
1898 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1901 fprintf_filtered (file, "t_c\t0x%08x\n",
1902 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1904 case FPSCR_C_REGNUM:
1905 fprintf_filtered (file, "fpscr_c\t0x%08x\n",
1906 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1909 fprintf_filtered (file, "fpul_c\t0x%08x\n",
1910 (int) get_frame_register_unsigned (frame, cr_c_regnum));
1916 sh64_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file,
1917 struct frame_info *frame, int regnum)
1918 { /* Do values for FP (float) regs. */
1919 unsigned char *raw_buffer;
1921 /* Allocate space for the float. */
1922 raw_buffer = (unsigned char *)
1923 alloca (register_size (gdbarch, gdbarch_fp0_regnum (gdbarch)));
1925 /* Get the data in raw format. */
1926 if (!deprecated_frame_register_read (frame, regnum, raw_buffer))
1927 error (_("can't read register %d (%s)"),
1928 regnum, gdbarch_register_name (gdbarch, regnum));
1930 /* Print the name and some spaces. */
1931 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
1932 print_spaces_filtered (15 - strlen (gdbarch_register_name
1933 (gdbarch, regnum)), file);
1935 /* Print the value. */
1936 const struct type *flt_type = builtin_type (gdbarch)->builtin_float;
1937 std::string str = target_float_to_string (raw_buffer, flt_type, "%-10.9g");
1938 fprintf_filtered (file, "%s", str.c_str ());
1940 /* Print the fp register as hex. */
1941 fprintf_filtered (file, "\t(raw ");
1942 print_hex_chars (file, raw_buffer,
1943 register_size (gdbarch, regnum),
1944 gdbarch_byte_order (gdbarch), true);
1945 fprintf_filtered (file, ")");
1946 fprintf_filtered (file, "\n");
1950 sh64_do_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1951 struct frame_info *frame, int regnum)
1953 /* All the sh64-compact mode registers are pseudo registers. */
1955 if (regnum < gdbarch_num_regs (gdbarch)
1956 || regnum >= gdbarch_num_regs (gdbarch)
1957 + NUM_PSEUDO_REGS_SH_MEDIA
1958 + NUM_PSEUDO_REGS_SH_COMPACT)
1959 internal_error (__FILE__, __LINE__,
1960 _("Invalid pseudo register number %d\n"), regnum);
1962 else if ((regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM))
1964 int fp_regnum = sh64_dr_reg_base_num (gdbarch, regnum);
1965 fprintf_filtered (file, "dr%d\t0x%08x%08x\n", regnum - DR0_REGNUM,
1966 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1967 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
1970 else if ((regnum >= DR0_C_REGNUM && regnum <= DR_LAST_C_REGNUM))
1972 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
1973 fprintf_filtered (file, "dr%d_c\t0x%08x%08x\n", regnum - DR0_C_REGNUM,
1974 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1975 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
1978 else if ((regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM))
1980 int fp_regnum = sh64_fv_reg_base_num (gdbarch, regnum);
1981 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1982 regnum - FV0_REGNUM,
1983 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1984 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
1985 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
1986 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
1989 else if ((regnum >= FV0_C_REGNUM && regnum <= FV_LAST_C_REGNUM))
1991 int fp_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
1992 fprintf_filtered (file, "fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1993 regnum - FV0_C_REGNUM,
1994 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
1995 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1),
1996 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 2),
1997 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 3));
2000 else if (regnum >= FPP0_REGNUM && regnum <= FPP_LAST_REGNUM)
2002 int fp_regnum = sh64_fpp_reg_base_num (gdbarch, regnum);
2003 fprintf_filtered (file, "fpp%d\t0x%08x\t0x%08x\n", regnum - FPP0_REGNUM,
2004 (unsigned) get_frame_register_unsigned (frame, fp_regnum),
2005 (unsigned) get_frame_register_unsigned (frame, fp_regnum + 1));
2008 else if (regnum >= R0_C_REGNUM && regnum <= R_LAST_C_REGNUM)
2010 int c_regnum = sh64_compact_reg_base_num (gdbarch, regnum);
2011 fprintf_filtered (file, "r%d_c\t0x%08x\n", regnum - R0_C_REGNUM,
2012 (unsigned) get_frame_register_unsigned (frame, c_regnum));
2014 else if (regnum >= FP0_C_REGNUM && regnum <= FP_LAST_C_REGNUM)
2015 /* This should work also for pseudoregs. */
2016 sh64_do_fp_register (gdbarch, file, frame, regnum);
2017 else if (regnum >= PC_C_REGNUM && regnum <= FPUL_C_REGNUM)
2018 sh64_do_cr_c_register_info (file, frame, regnum);
2022 sh64_do_register (struct gdbarch *gdbarch, struct ui_file *file,
2023 struct frame_info *frame, int regnum)
2025 struct value_print_options opts;
2028 fputs_filtered (gdbarch_register_name (gdbarch, regnum), file);
2029 print_spaces_filtered (15 - strlen (gdbarch_register_name
2030 (gdbarch, regnum)), file);
2032 /* Get the data in raw format. */
2033 val = get_frame_register_value (frame, regnum);
2034 if (value_optimized_out (val) || !value_entirely_available (val))
2036 fprintf_filtered (file, "*value not available*\n");
2040 get_formatted_print_options (&opts, 'x');
2042 val_print (register_type (gdbarch, regnum),
2044 file, 0, val, &opts, current_language);
2045 fprintf_filtered (file, "\t");
2046 get_formatted_print_options (&opts, 0);
2048 val_print (register_type (gdbarch, regnum),
2050 file, 0, val, &opts, current_language);
2051 fprintf_filtered (file, "\n");
2055 sh64_print_register (struct gdbarch *gdbarch, struct ui_file *file,
2056 struct frame_info *frame, int regnum)
2058 if (regnum < 0 || regnum >= gdbarch_num_regs (gdbarch)
2059 + gdbarch_num_pseudo_regs (gdbarch))
2060 internal_error (__FILE__, __LINE__,
2061 _("Invalid register number %d\n"), regnum);
2063 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
2065 if (TYPE_CODE (register_type (gdbarch, regnum)) == TYPE_CODE_FLT)
2066 sh64_do_fp_register (gdbarch, file, frame, regnum); /* FP regs */
2068 sh64_do_register (gdbarch, file, frame, regnum);
2071 else if (regnum < gdbarch_num_regs (gdbarch)
2072 + gdbarch_num_pseudo_regs (gdbarch))
2073 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2077 sh64_media_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2078 struct frame_info *frame, int regnum,
2081 if (regnum != -1) /* Do one specified register. */
2083 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2084 error (_("Not a valid register for the current processor type"));
2086 sh64_print_register (gdbarch, file, frame, regnum);
2089 /* Do all (or most) registers. */
2092 while (regnum < gdbarch_num_regs (gdbarch))
2094 /* If the register name is empty, it is undefined for this
2095 processor, so don't display anything. */
2096 if (gdbarch_register_name (gdbarch, regnum) == NULL
2097 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
2103 if (TYPE_CODE (register_type (gdbarch, regnum))
2108 /* true for "INFO ALL-REGISTERS" command. */
2109 sh64_do_fp_register (gdbarch, file, frame, regnum);
2113 regnum += FP_LAST_REGNUM - gdbarch_fp0_regnum (gdbarch);
2118 sh64_do_register (gdbarch, file, frame, regnum);
2124 while (regnum < gdbarch_num_regs (gdbarch)
2125 + gdbarch_num_pseudo_regs (gdbarch))
2127 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2134 sh64_compact_print_registers_info (struct gdbarch *gdbarch,
2135 struct ui_file *file,
2136 struct frame_info *frame, int regnum,
2139 if (regnum != -1) /* Do one specified register. */
2141 if (*(gdbarch_register_name (gdbarch, regnum)) == '\0')
2142 error (_("Not a valid register for the current processor type"));
2144 if (regnum >= 0 && regnum < R0_C_REGNUM)
2145 error (_("Not a valid register for the current processor mode."));
2147 sh64_print_register (gdbarch, file, frame, regnum);
2150 /* Do all compact registers. */
2152 regnum = R0_C_REGNUM;
2153 while (regnum < gdbarch_num_regs (gdbarch)
2154 + gdbarch_num_pseudo_regs (gdbarch))
2156 sh64_do_pseudo_register (gdbarch, file, frame, regnum);
2163 sh64_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
2164 struct frame_info *frame, int regnum, int fpregs)
2166 if (pc_is_isa32 (get_frame_pc (frame)))
2167 sh64_media_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2169 sh64_compact_print_registers_info (gdbarch, file, frame, regnum, fpregs);
2172 static struct sh64_frame_cache *
2173 sh64_alloc_frame_cache (void)
2175 struct sh64_frame_cache *cache;
2178 cache = FRAME_OBSTACK_ZALLOC (struct sh64_frame_cache);
2182 cache->saved_sp = 0;
2183 cache->sp_offset = 0;
2186 /* Frameless until proven otherwise. */
2189 /* Saved registers. We initialize these to -1 since zero is a valid
2190 offset (that's where fp is supposed to be stored). */
2191 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2193 cache->saved_regs[i] = -1;
2199 static struct sh64_frame_cache *
2200 sh64_frame_cache (struct frame_info *this_frame, void **this_cache)
2202 struct gdbarch *gdbarch;
2203 struct sh64_frame_cache *cache;
2204 CORE_ADDR current_pc;
2208 return (struct sh64_frame_cache *) *this_cache;
2210 gdbarch = get_frame_arch (this_frame);
2211 cache = sh64_alloc_frame_cache ();
2212 *this_cache = cache;
2214 current_pc = get_frame_pc (this_frame);
2215 cache->media_mode = pc_is_isa32 (current_pc);
2217 /* In principle, for normal frames, fp holds the frame pointer,
2218 which holds the base address for the current stack frame.
2219 However, for functions that don't need it, the frame pointer is
2220 optional. For these "frameless" functions the frame pointer is
2221 actually the frame pointer of the calling frame. */
2222 cache->base = get_frame_register_unsigned (this_frame, MEDIA_FP_REGNUM);
2223 if (cache->base == 0)
2226 cache->pc = get_frame_func (this_frame);
2228 sh64_analyze_prologue (gdbarch, cache, cache->pc, current_pc);
2230 if (!cache->uses_fp)
2232 /* We didn't find a valid frame, which means that CACHE->base
2233 currently holds the frame pointer for our calling frame. If
2234 we're at the start of a function, or somewhere half-way its
2235 prologue, the function's frame probably hasn't been fully
2236 setup yet. Try to reconstruct the base address for the stack
2237 frame by looking at the stack pointer. For truly "frameless"
2238 functions this might work too. */
2239 cache->base = get_frame_register_unsigned
2240 (this_frame, gdbarch_sp_regnum (gdbarch));
2243 /* Now that we have the base address for the stack frame we can
2244 calculate the value of sp in the calling frame. */
2245 cache->saved_sp = cache->base + cache->sp_offset;
2247 /* Adjust all the saved registers such that they contain addresses
2248 instead of offsets. */
2249 for (i = 0; i < SIM_SH64_NR_REGS; i++)
2250 if (cache->saved_regs[i] != -1)
2251 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i];
2256 static struct value *
2257 sh64_frame_prev_register (struct frame_info *this_frame,
2258 void **this_cache, int regnum)
2260 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2261 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2262 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2264 gdb_assert (regnum >= 0);
2266 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2267 frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2269 /* The PC of the previous frame is stored in the PR register of
2270 the current frame. Frob regnum so that we pull the value from
2271 the correct place. */
2272 if (regnum == gdbarch_pc_regnum (gdbarch))
2275 if (regnum < SIM_SH64_NR_REGS && cache->saved_regs[regnum] != -1)
2277 if (gdbarch_tdep (gdbarch)->sh_abi == SH_ABI_32
2278 && (regnum == MEDIA_FP_REGNUM || regnum == PR_REGNUM))
2281 val = read_memory_unsigned_integer (cache->saved_regs[regnum],
2283 return frame_unwind_got_constant (this_frame, regnum, val);
2286 return frame_unwind_got_memory (this_frame, regnum,
2287 cache->saved_regs[regnum]);
2290 return frame_unwind_got_register (this_frame, regnum, regnum);
2294 sh64_frame_this_id (struct frame_info *this_frame, void **this_cache,
2295 struct frame_id *this_id)
2297 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2299 /* This marks the outermost frame. */
2300 if (cache->base == 0)
2303 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2306 static const struct frame_unwind sh64_frame_unwind = {
2308 default_frame_unwind_stop_reason,
2310 sh64_frame_prev_register,
2312 default_frame_sniffer
2316 sh64_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2318 return frame_unwind_register_unsigned (next_frame,
2319 gdbarch_sp_regnum (gdbarch));
2323 sh64_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2325 return frame_unwind_register_unsigned (next_frame,
2326 gdbarch_pc_regnum (gdbarch));
2329 static struct frame_id
2330 sh64_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2332 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2333 gdbarch_sp_regnum (gdbarch));
2334 return frame_id_build (sp, get_frame_pc (this_frame));
2338 sh64_frame_base_address (struct frame_info *this_frame, void **this_cache)
2340 struct sh64_frame_cache *cache = sh64_frame_cache (this_frame, this_cache);
2345 static const struct frame_base sh64_frame_base = {
2347 sh64_frame_base_address,
2348 sh64_frame_base_address,
2349 sh64_frame_base_address
2354 sh64_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2356 struct gdbarch *gdbarch;
2357 struct gdbarch_tdep *tdep;
2359 /* If there is already a candidate, use it. */
2360 arches = gdbarch_list_lookup_by_info (arches, &info);
2362 return arches->gdbarch;
2364 /* None found, create a new architecture from the information
2366 tdep = XCNEW (struct gdbarch_tdep);
2367 gdbarch = gdbarch_alloc (&info, tdep);
2369 /* Determine the ABI */
2370 if (info.abfd && bfd_get_arch_size (info.abfd) == 64)
2372 /* If the ABI is the 64-bit one, it can only be sh-media. */
2373 tdep->sh_abi = SH_ABI_64;
2374 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2375 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2379 /* If the ABI is the 32-bit one it could be either media or
2381 tdep->sh_abi = SH_ABI_32;
2382 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2383 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2386 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2387 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2388 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2389 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2390 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2391 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2392 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2394 /* The number of real registers is the same whether we are in
2395 ISA16(compact) or ISA32(media). */
2396 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
2397 set_gdbarch_sp_regnum (gdbarch, 15);
2398 set_gdbarch_pc_regnum (gdbarch, 64);
2399 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
2400 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA
2401 + NUM_PSEUDO_REGS_SH_COMPACT);
2403 set_gdbarch_register_name (gdbarch, sh64_register_name);
2404 set_gdbarch_register_type (gdbarch, sh64_register_type);
2406 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
2407 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
2409 set_gdbarch_breakpoint_kind_from_pc (gdbarch, sh64_breakpoint_kind_from_pc);
2410 set_gdbarch_sw_breakpoint_from_kind (gdbarch, sh64_sw_breakpoint_from_kind);
2411 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2413 set_gdbarch_return_value (gdbarch, sh64_return_value);
2415 set_gdbarch_skip_prologue (gdbarch, sh64_skip_prologue);
2416 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2418 set_gdbarch_push_dummy_call (gdbarch, sh64_push_dummy_call);
2420 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2422 set_gdbarch_frame_align (gdbarch, sh64_frame_align);
2423 set_gdbarch_unwind_sp (gdbarch, sh64_unwind_sp);
2424 set_gdbarch_unwind_pc (gdbarch, sh64_unwind_pc);
2425 set_gdbarch_dummy_id (gdbarch, sh64_dummy_id);
2426 frame_base_set_default (gdbarch, &sh64_frame_base);
2428 set_gdbarch_print_registers_info (gdbarch, sh64_print_registers_info);
2430 set_gdbarch_elf_make_msymbol_special (gdbarch,
2431 sh64_elf_make_msymbol_special);
2433 /* Hook in ABI-specific overrides, if they have been registered. */
2434 gdbarch_init_osabi (info, gdbarch);
2436 dwarf2_append_unwinders (gdbarch);
2437 frame_unwind_append_unwinder (gdbarch, &sh64_frame_unwind);