1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
40 #include "gdb_string.h"
41 #include "gdb_assert.h"
42 #include "arch-utils.h"
43 #include "floatformat.h"
51 #include "solib-svr4.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
58 static void (*sh_show_regs) (void);
60 #define SH_NUM_REGS 59
69 /* Flag showing that a frame has been created in the prologue code. */
72 /* Saved registers. */
73 CORE_ADDR saved_regs[SH_NUM_REGS];
78 sh_generic_register_name (int reg_nr)
80 static char *register_names[] = {
81 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
82 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
83 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
85 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
86 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
88 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
89 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
93 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
95 return register_names[reg_nr];
99 sh_sh_register_name (int reg_nr)
101 static char *register_names[] = {
102 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
103 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
104 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
106 "", "", "", "", "", "", "", "",
107 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
114 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
116 return register_names[reg_nr];
120 sh_sh3_register_name (int reg_nr)
122 static char *register_names[] = {
123 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
124 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
125 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
127 "", "", "", "", "", "", "", "",
128 "", "", "", "", "", "", "", "",
130 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
131 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
135 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
137 return register_names[reg_nr];
141 sh_sh3e_register_name (int reg_nr)
143 static char *register_names[] = {
144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
146 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
148 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
149 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
151 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
152 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
156 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
158 return register_names[reg_nr];
162 sh_sh2e_register_name (int reg_nr)
164 static char *register_names[] = {
165 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
166 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
167 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
169 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
170 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
172 "", "", "", "", "", "", "", "",
173 "", "", "", "", "", "", "", "",
177 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
179 return register_names[reg_nr];
183 sh_sh_dsp_register_name (int reg_nr)
185 static char *register_names[] = {
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
193 "rs", "re", "", "", "", "", "", "",
194 "", "", "", "", "", "", "", "",
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return register_names[reg_nr];
204 sh_sh3_dsp_register_name (int reg_nr)
206 static char *register_names[] = {
207 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
208 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
209 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
211 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
212 "y0", "y1", "", "", "", "", "", "mod",
214 "rs", "re", "", "", "", "", "", "",
215 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
216 "", "", "", "", "", "", "", "",
220 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
222 return register_names[reg_nr];
226 sh_sh4_register_name (int reg_nr)
228 static char *register_names[] = {
229 /* general registers 0-15 */
230 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
231 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
233 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
236 /* floating point registers 25 - 40 */
237 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
238 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
242 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
244 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
245 /* double precision (pseudo) 59 - 66 */
246 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
247 /* vectors (pseudo) 67 - 70 */
248 "fv0", "fv4", "fv8", "fv12",
249 /* FIXME: missing XF 71 - 86 */
250 /* FIXME: missing XD 87 - 94 */
254 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
256 return register_names[reg_nr];
259 static const unsigned char *
260 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
262 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
263 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
265 *lenptr = sizeof (breakpoint);
269 /* Prologue looks like
273 sub <room_for_loca_vars>,r15
276 Actually it can be more complicated than this but that's it, basically.
279 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
280 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
282 /* STS.L PR,@-r15 0100111100100010
283 r15-4-->r15, PR-->(r15) */
284 #define IS_STS(x) ((x) == 0x4f22)
286 /* MOV.L Rm,@-r15 00101111mmmm0110
287 r15-4-->r15, Rm-->(R15) */
288 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
290 /* MOV r15,r14 0110111011110011
292 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
294 /* ADD #imm,r15 01111111iiiiiiii
296 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
298 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
299 #define IS_SHLL_R3(x) ((x) == 0x4300)
301 /* ADD r3,r15 0011111100111100
303 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
305 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
306 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
307 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
308 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
309 make this entirely clear. */
310 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
311 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
313 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
314 #define IS_MOV_ARG_TO_REG(x) \
315 (((x) & 0xf00f) == 0x6003 && \
316 ((x) & 0x00f0) >= 0x0040 && \
317 ((x) & 0x00f0) <= 0x0070)
318 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
319 #define IS_MOV_ARG_TO_IND_R14(x) \
320 (((x) & 0xff0f) == 0x2e02 && \
321 ((x) & 0x00f0) >= 0x0040 && \
322 ((x) & 0x00f0) <= 0x0070)
323 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
324 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
325 (((x) & 0xff00) == 0x1e00 && \
326 ((x) & 0x00f0) >= 0x0040 && \
327 ((x) & 0x00f0) <= 0x0070)
329 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
330 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
331 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
332 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
333 /* SUB Rn,R15 00111111nnnn1000 */
334 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
336 #define FPSCR_SZ (1 << 20)
338 /* The following instructions are used for epilogue testing. */
339 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
340 #define IS_RTS(x) ((x) == 0x000b)
341 #define IS_LDS(x) ((x) == 0x4f26)
342 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
343 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
344 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
346 /* Disassemble an instruction. */
348 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
350 info->endian = TARGET_BYTE_ORDER;
351 return print_insn_sh (memaddr, info);
355 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
356 struct sh_frame_cache *cache)
363 int reg, sav_reg = -1;
365 if (pc >= current_pc)
369 for (opc = pc + (2 * 28); pc < opc; pc += 2)
371 inst = read_memory_unsigned_integer (pc, 2);
372 /* See where the registers will be saved to */
375 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
376 cache->sp_offset += 4;
378 else if (IS_STS (inst))
380 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
381 cache->sp_offset += 4;
383 else if (IS_MOV_R3 (inst))
385 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
387 else if (IS_SHLL_R3 (inst))
391 else if (IS_ADD_R3SP (inst))
393 cache->sp_offset += -r3_val;
395 else if (IS_ADD_IMM_SP (inst))
397 offset = ((inst & 0xff) ^ 0x80) - 0x80;
398 cache->sp_offset -= offset;
400 else if (IS_MOVW_PCREL_TO_REG (inst))
404 reg = GET_TARGET_REG (inst);
408 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
410 read_memory_integer (((pc + 4) & ~3) + offset, 2);
414 else if (IS_MOVL_PCREL_TO_REG (inst))
418 reg = (inst & 0x0f00) >> 8;
422 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
424 read_memory_integer (((pc + 4) & ~3) + offset, 4);
428 else if (IS_SUB_REG_FROM_SP (inst))
430 reg = GET_SOURCE_REG (inst);
431 if (sav_reg > 0 && reg == sav_reg)
435 cache->sp_offset += sav_offset;
437 else if (IS_FPUSH (inst))
439 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
441 cache->sp_offset += 8;
445 cache->sp_offset += 4;
448 else if (IS_MOV_SP_FP (inst))
452 /* At this point, only allow argument register moves to other
453 registers or argument register moves to @(X,fp) which are
454 moving the register arguments onto the stack area allocated
455 by a former add somenumber to SP call. Don't allow moving
456 to an fp indirect address above fp + cache->sp_offset. */
458 for (opc = pc + 12; pc < opc; pc += 2)
460 inst = read_memory_integer (pc, 2);
461 if (IS_MOV_ARG_TO_IND_R14 (inst))
463 reg = GET_SOURCE_REG (inst);
464 if (cache->sp_offset > 0)
465 cache->saved_regs[reg] = cache->sp_offset;
467 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
469 reg = GET_SOURCE_REG (inst);
470 offset = (inst & 0xf) * 4;
471 if (cache->sp_offset > offset)
472 cache->saved_regs[reg] = cache->sp_offset - offset;
474 else if (IS_MOV_ARG_TO_REG (inst))
481 #if 0 /* This used to just stop when it found an instruction that
482 was not considered part of the prologue. Now, we just
483 keep going looking for likely instructions. */
492 /* Skip any prologue before the guts of a function */
494 /* Skip the prologue using the debug information. If this fails we'll
495 fall back on the 'guess' method below. */
497 after_prologue (CORE_ADDR pc)
499 struct symtab_and_line sal;
500 CORE_ADDR func_addr, func_end;
502 /* If we can not find the symbol in the partial symbol table, then
503 there is no hope we can determine the function's start address
505 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
508 /* Get the line associated with FUNC_ADDR. */
509 sal = find_pc_line (func_addr, 0);
511 /* There are only two cases to consider. First, the end of the source line
512 is within the function bounds. In that case we return the end of the
513 source line. Second is the end of the source line extends beyond the
514 bounds of the current function. We need to use the slow code to
515 examine instructions in that case. */
516 if (sal.end < func_end)
523 sh_skip_prologue (CORE_ADDR start_pc)
526 struct sh_frame_cache cache;
528 /* See if we can determine the end of the prologue via the symbol table.
529 If so, then return either PC, or the PC after the prologue, whichever
531 pc = after_prologue (start_pc);
533 /* If after_prologue returned a useful address, then use it. Else
534 fall back on the instruction skipping code. */
536 return max (pc, start_pc);
538 cache.sp_offset = -4;
539 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
546 /* Should call_function allocate stack space for a struct return?
550 Aggregate types not bigger than 8 bytes that have the same size and
551 alignment as one of the integer scalar types are returned in the
552 same registers as the integer type they match.
554 For example, a 2-byte aligned structure with size 2 bytes has the
555 same size and alignment as a short int, and will be returned in R0.
556 A 4-byte aligned structure with size 8 bytes has the same size and
557 alignment as a long long int, and will be returned in R0 and R1.
559 When an aggregate type is returned in R0 and R1, R0 contains the
560 first four bytes of the aggregate, and R1 contains the
561 remainder. If the size of the aggregate type is not a multiple of 4
562 bytes, the aggregate is tail-padded up to a multiple of 4
563 bytes. The value of the padding is undefined. For little-endian
564 targets the padding will appear at the most significant end of the
565 last element, for big-endian targets the padding appears at the
566 least significant end of the last element.
568 All other aggregate types are returned by address. The caller
569 function passes the address of an area large enough to hold the
570 aggregate value in R2. The called function stores the result in
573 To reiterate, structs smaller than 8 bytes could also be returned
574 in memory, if they don't pass the "same size and alignment as an
579 struct s { char c[3]; } wibble;
580 struct s foo(void) { return wibble; }
582 the return value from foo() will be in memory, not
583 in R0, because there is no 3-byte integer type.
587 struct s { char c[2]; } wibble;
588 struct s foo(void) { return wibble; }
590 because a struct containing two chars has alignment 1, that matches
591 type char, but size 2, that matches type short. There's no integer
592 type that has alignment 1 and size 2, so the struct is returned in
598 sh_use_struct_convention (int gcc_p, struct type *type)
600 int len = TYPE_LENGTH (type);
601 int nelem = TYPE_NFIELDS (type);
603 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
604 fit in two registers anyway) use struct convention. */
605 if (len != 1 && len != 2 && len != 4 && len != 8)
608 /* Scalar types and aggregate types with exactly one field are aligned
609 by definition. They are returned in registers. */
613 /* If the first field in the aggregate has the same length as the entire
614 aggregate type, the type is returned in registers. */
615 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
618 /* If the size of the aggregate is 8 bytes and the first field is
619 of size 4 bytes its alignment is equal to long long's alignment,
620 so it's returned in registers. */
621 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
624 /* Otherwise use struct convention. */
628 /* Extract from an array REGBUF containing the (raw) register state
629 the address in which a function should return its structure value,
630 as a CORE_ADDR (or an expression that can be used as one). */
632 sh_extract_struct_value_address (struct regcache *regcache)
636 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
641 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
646 /* Function: push_dummy_call (formerly push_arguments)
647 Setup the function arguments for calling a function in the inferior.
649 On the Renesas SH architecture, there are four registers (R4 to R7)
650 which are dedicated for passing function arguments. Up to the first
651 four arguments (depending on size) may go into these registers.
652 The rest go on the stack.
654 MVS: Except on SH variants that have floating point registers.
655 In that case, float and double arguments are passed in the same
656 manner, but using FP registers instead of GP registers.
658 Arguments that are smaller than 4 bytes will still take up a whole
659 register or a whole 32-bit word on the stack, and will be
660 right-justified in the register or the stack word. This includes
661 chars, shorts, and small aggregate types.
663 Arguments that are larger than 4 bytes may be split between two or
664 more registers. If there are not enough registers free, an argument
665 may be passed partly in a register (or registers), and partly on the
666 stack. This includes doubles, long longs, and larger aggregates.
667 As far as I know, there is no upper limit to the size of aggregates
668 that will be passed in this way; in other words, the convention of
669 passing a pointer to a large aggregate instead of a copy is not used.
671 MVS: The above appears to be true for the SH variants that do not
672 have an FPU, however those that have an FPU appear to copy the
673 aggregate argument onto the stack (and not place it in registers)
674 if it is larger than 16 bytes (four GP registers).
676 An exceptional case exists for struct arguments (and possibly other
677 aggregates such as arrays) if the size is larger than 4 bytes but
678 not a multiple of 4 bytes. In this case the argument is never split
679 between the registers and the stack, but instead is copied in its
680 entirety onto the stack, AND also copied into as many registers as
681 there is room for. In other words, space in registers permitting,
682 two copies of the same argument are passed in. As far as I can tell,
683 only the one on the stack is used, although that may be a function
684 of the level of compiler optimization. I suspect this is a compiler
685 bug. Arguments of these odd sizes are left-justified within the
686 word (as opposed to arguments smaller than 4 bytes, which are
689 If the function is to return an aggregate type such as a struct, it
690 is either returned in the normal return value register R0 (if its
691 size is no greater than one byte), or else the caller must allocate
692 space into which the callee will copy the return value (if the size
693 is greater than one byte). In this case, a pointer to the return
694 value location is passed into the callee in register R2, which does
695 not displace any of the other arguments passed in via registers R4
698 /* Helper function to justify value in register according to endianess. */
700 sh_justify_value_in_reg (struct value *val, int len)
702 static char valbuf[4];
704 memset (valbuf, 0, sizeof (valbuf));
707 /* value gets right-justified in the register or stack word */
708 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
709 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
711 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
714 return (char *) VALUE_CONTENTS (val);
717 /* Helper function to eval number of bytes to allocate on stack. */
719 sh_stack_allocsize (int nargs, struct value **args)
723 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
727 /* Helper functions for getting the float arguments right. Registers usage
728 depends on the ABI and the endianess. The comments should enlighten how
729 it's intended to work. */
731 /* This array stores which of the float arg registers are already in use. */
732 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
734 /* This function just resets the above array to "no reg used so far". */
736 sh_init_flt_argreg (void)
738 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
741 /* This function returns the next register to use for float arg passing.
742 It returns either a valid value between FLOAT_ARG0_REGNUM and
743 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
744 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
746 Note that register number 0 in flt_argreg_array corresponds with the
747 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
748 29) the parity of the register number is preserved, which is important
749 for the double register passing test (see the "argreg & 1" test below). */
751 sh_next_flt_argreg (int len)
755 /* First search for the next free register. */
756 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
758 if (!flt_argreg_array[argreg])
761 /* No register left? */
762 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
763 return FLOAT_ARGLAST_REGNUM + 1;
767 /* Doubles are always starting in a even register number. */
770 flt_argreg_array[argreg] = 1;
774 /* No register left? */
775 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
776 return FLOAT_ARGLAST_REGNUM + 1;
778 /* Also mark the next register as used. */
779 flt_argreg_array[argreg + 1] = 1;
781 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
783 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
784 if (!flt_argreg_array[argreg + 1])
787 flt_argreg_array[argreg] = 1;
788 return FLOAT_ARG0_REGNUM + argreg;
791 /* Helper function which figures out, if a type is treated like a float type.
793 Second, the FPU ABIs have a special way how to treat types as float types.
794 Structures with exactly one member, which is of type float or double, are
795 treated exactly as the base types float or double:
805 are handled the same way as just
811 As a result, arguments of these struct types are pushed into floating point
812 registers exactly as floats or doubles, using the same decision algorithm.
814 The same is valid if these types are used as function return types. The
815 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
816 or even using struct convention as it is for other structs. */
819 sh_treat_as_flt_p (struct type *type)
821 int len = TYPE_LENGTH (type);
823 /* Ordinary float types are obviously treated as float. */
824 if (TYPE_CODE (type) == TYPE_CODE_FLT)
826 /* Otherwise non-struct types are not treated as float. */
827 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
829 /* Otherwise structs with more than one memeber are not treated as float. */
830 if (TYPE_NFIELDS (type) != 1)
832 /* Otherwise if the type of that member is float, the whole type is
834 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
836 /* Otherwise it's not treated as float. */
841 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
843 struct regcache *regcache,
844 CORE_ADDR bp_addr, int nargs,
846 CORE_ADDR sp, int struct_return,
847 CORE_ADDR struct_addr)
849 int stack_offset = 0;
850 int argreg = ARG0_REGNUM;
856 int len, reg_size = 0;
857 int pass_on_stack = 0;
860 /* first force sp to a 4-byte alignment */
861 sp = sh_frame_align (gdbarch, sp);
864 regcache_cooked_write_unsigned (regcache,
865 STRUCT_RETURN_REGNUM, struct_addr);
867 /* make room on stack for args */
868 sp -= sh_stack_allocsize (nargs, args);
870 /* Initialize float argument mechanism. */
871 sh_init_flt_argreg ();
873 /* Now load as many as possible of the first arguments into
874 registers, and push the rest onto the stack. There are 16 bytes
875 in four registers available. Loop thru args from first to last. */
876 for (argnum = 0; argnum < nargs; argnum++)
878 type = VALUE_TYPE (args[argnum]);
879 len = TYPE_LENGTH (type);
880 val = sh_justify_value_in_reg (args[argnum], len);
882 /* Some decisions have to be made how various types are handled.
883 This also differs in different ABIs. */
886 /* Find out the next register to use for a floating point value. */
887 treat_as_flt = sh_treat_as_flt_p (type);
889 flt_argreg = sh_next_flt_argreg (len);
890 /* In contrast to non-FPU CPUs, arguments are never split between
891 registers and stack. If an argument doesn't fit in the remaining
892 registers it's always pushed entirely on the stack. */
893 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
898 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
899 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
902 /* The data goes entirely on the stack, 4-byte aligned. */
903 reg_size = (len + 3) & ~3;
904 write_memory (sp + stack_offset, val, reg_size);
905 stack_offset += reg_size;
907 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
909 /* Argument goes in a float argument register. */
910 reg_size = register_size (gdbarch, flt_argreg);
911 regval = extract_unsigned_integer (val, reg_size);
912 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
914 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
916 /* there's room in a register */
917 reg_size = register_size (gdbarch, argreg);
918 regval = extract_unsigned_integer (val, reg_size);
919 regcache_cooked_write_unsigned (regcache, argreg++, regval);
921 /* Store the value one register at a time or in one step on stack. */
927 /* Store return address. */
928 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
930 /* Update stack pointer. */
931 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
937 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
939 struct regcache *regcache,
941 int nargs, struct value **args,
942 CORE_ADDR sp, int struct_return,
943 CORE_ADDR struct_addr)
945 int stack_offset = 0;
946 int argreg = ARG0_REGNUM;
953 /* first force sp to a 4-byte alignment */
954 sp = sh_frame_align (gdbarch, sp);
957 regcache_cooked_write_unsigned (regcache,
958 STRUCT_RETURN_REGNUM, struct_addr);
960 /* make room on stack for args */
961 sp -= sh_stack_allocsize (nargs, args);
963 /* Now load as many as possible of the first arguments into
964 registers, and push the rest onto the stack. There are 16 bytes
965 in four registers available. Loop thru args from first to last. */
966 for (argnum = 0; argnum < nargs; argnum++)
968 type = VALUE_TYPE (args[argnum]);
969 len = TYPE_LENGTH (type);
970 val = sh_justify_value_in_reg (args[argnum], len);
974 if (argreg > ARGLAST_REGNUM)
976 /* The remainder of the data goes entirely on the stack,
978 reg_size = (len + 3) & ~3;
979 write_memory (sp + stack_offset, val, reg_size);
980 stack_offset += reg_size;
982 else if (argreg <= ARGLAST_REGNUM)
984 /* there's room in a register */
985 reg_size = register_size (gdbarch, argreg);
986 regval = extract_unsigned_integer (val, reg_size);
987 regcache_cooked_write_unsigned (regcache, argreg++, regval);
989 /* Store the value reg_size bytes at a time. This means that things
990 larger than reg_size bytes may go partly in registers and partly
997 /* Store return address. */
998 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1000 /* Update stack pointer. */
1001 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1006 /* Find a function's return value in the appropriate registers (in
1007 regbuf), and copy it into valbuf. Extract from an array REGBUF
1008 containing the (raw) register state a function return value of type
1009 TYPE, and copy that, in virtual format, into VALBUF. */
1011 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1014 int len = TYPE_LENGTH (type);
1015 int return_register = R0_REGNUM;
1022 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1023 store_unsigned_integer (valbuf, len, c);
1027 int i, regnum = R0_REGNUM;
1028 for (i = 0; i < len; i += 4)
1029 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1032 error ("bad size for return value");
1036 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1039 if (sh_treat_as_flt_p (type))
1041 int len = TYPE_LENGTH (type);
1042 int i, regnum = FP0_REGNUM;
1043 for (i = 0; i < len; i += 4)
1044 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1047 sh_default_extract_return_value (type, regcache, valbuf);
1050 /* Write into appropriate registers a function return value
1051 of type TYPE, given in virtual format.
1052 If the architecture is sh4 or sh3e, store a function's return value
1053 in the R0 general register or in the FP0 floating point register,
1054 depending on the type of the return value. In all the other cases
1055 the result is stored in r0, left-justified. */
1057 sh_default_store_return_value (struct type *type, struct regcache *regcache,
1061 int len = TYPE_LENGTH (type);
1065 val = extract_unsigned_integer (valbuf, len);
1066 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1070 int i, regnum = R0_REGNUM;
1071 for (i = 0; i < len; i += 4)
1072 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1077 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1080 if (sh_treat_as_flt_p (type))
1082 int len = TYPE_LENGTH (type);
1083 int i, regnum = FP0_REGNUM;
1084 for (i = 0; i < len; i += 4)
1085 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1088 sh_default_store_return_value (type, regcache, valbuf);
1091 /* Print the registers in a form similar to the E7000 */
1094 sh_generic_show_regs (void)
1096 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1097 paddr (read_register (PC_REGNUM)),
1098 (long) read_register (SR_REGNUM),
1099 (long) read_register (PR_REGNUM),
1100 (long) read_register (MACH_REGNUM),
1101 (long) read_register (MACL_REGNUM));
1103 printf_filtered ("GBR=%08lx VBR=%08lx",
1104 (long) read_register (GBR_REGNUM),
1105 (long) read_register (VBR_REGNUM));
1108 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1109 (long) read_register (0), (long) read_register (1),
1110 (long) read_register (2), (long) read_register (3),
1111 (long) read_register (4), (long) read_register (5),
1112 (long) read_register (6), (long) read_register (7));
1113 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1114 (long) read_register (8), (long) read_register (9),
1115 (long) read_register (10), (long) read_register (11),
1116 (long) read_register (12), (long) read_register (13),
1117 (long) read_register (14), (long) read_register (15));
1121 sh3_show_regs (void)
1123 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1124 paddr (read_register (PC_REGNUM)),
1125 (long) read_register (SR_REGNUM),
1126 (long) read_register (PR_REGNUM),
1127 (long) read_register (MACH_REGNUM),
1128 (long) read_register (MACL_REGNUM));
1130 printf_filtered ("GBR=%08lx VBR=%08lx",
1131 (long) read_register (GBR_REGNUM),
1132 (long) read_register (VBR_REGNUM));
1133 printf_filtered (" SSR=%08lx SPC=%08lx",
1134 (long) read_register (SSR_REGNUM),
1135 (long) read_register (SPC_REGNUM));
1138 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1139 (long) read_register (0), (long) read_register (1),
1140 (long) read_register (2), (long) read_register (3),
1141 (long) read_register (4), (long) read_register (5),
1142 (long) read_register (6), (long) read_register (7));
1143 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1144 (long) read_register (8), (long) read_register (9),
1145 (long) read_register (10), (long) read_register (11),
1146 (long) read_register (12), (long) read_register (13),
1147 (long) read_register (14), (long) read_register (15));
1152 sh2e_show_regs (void)
1154 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1155 paddr (read_register (PC_REGNUM)),
1156 (long) read_register (SR_REGNUM),
1157 (long) read_register (PR_REGNUM),
1158 (long) read_register (MACH_REGNUM),
1159 (long) read_register (MACL_REGNUM));
1161 printf_filtered ("GBR=%08lx VBR=%08lx",
1162 (long) read_register (GBR_REGNUM),
1163 (long) read_register (VBR_REGNUM));
1164 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1165 (long) read_register (FPUL_REGNUM),
1166 (long) read_register (FPSCR_REGNUM));
1169 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1170 (long) read_register (0), (long) read_register (1),
1171 (long) read_register (2), (long) read_register (3),
1172 (long) read_register (4), (long) read_register (5),
1173 (long) read_register (6), (long) read_register (7));
1174 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1175 (long) read_register (8), (long) read_register (9),
1176 (long) read_register (10), (long) read_register (11),
1177 (long) read_register (12), (long) read_register (13),
1178 (long) read_register (14), (long) read_register (15));
1180 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1181 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1185 sh3e_show_regs (void)
1187 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1188 paddr (read_register (PC_REGNUM)),
1189 (long) read_register (SR_REGNUM),
1190 (long) read_register (PR_REGNUM),
1191 (long) read_register (MACH_REGNUM),
1192 (long) read_register (MACL_REGNUM));
1194 printf_filtered ("GBR=%08lx VBR=%08lx",
1195 (long) read_register (GBR_REGNUM),
1196 (long) read_register (VBR_REGNUM));
1197 printf_filtered (" SSR=%08lx SPC=%08lx",
1198 (long) read_register (SSR_REGNUM),
1199 (long) read_register (SPC_REGNUM));
1200 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1201 (long) read_register (FPUL_REGNUM),
1202 (long) read_register (FPSCR_REGNUM));
1205 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1206 (long) read_register (0), (long) read_register (1),
1207 (long) read_register (2), (long) read_register (3),
1208 (long) read_register (4), (long) read_register (5),
1209 (long) read_register (6), (long) read_register (7));
1210 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1211 (long) read_register (8), (long) read_register (9),
1212 (long) read_register (10), (long) read_register (11),
1213 (long) read_register (12), (long) read_register (13),
1214 (long) read_register (14), (long) read_register (15));
1216 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1217 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1221 sh3_dsp_show_regs (void)
1223 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1224 paddr (read_register (PC_REGNUM)),
1225 (long) read_register (SR_REGNUM),
1226 (long) read_register (PR_REGNUM),
1227 (long) read_register (MACH_REGNUM),
1228 (long) read_register (MACL_REGNUM));
1230 printf_filtered ("GBR=%08lx VBR=%08lx",
1231 (long) read_register (GBR_REGNUM),
1232 (long) read_register (VBR_REGNUM));
1234 printf_filtered (" SSR=%08lx SPC=%08lx",
1235 (long) read_register (SSR_REGNUM),
1236 (long) read_register (SPC_REGNUM));
1238 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1241 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1242 (long) read_register (0), (long) read_register (1),
1243 (long) read_register (2), (long) read_register (3),
1244 (long) read_register (4), (long) read_register (5),
1245 (long) read_register (6), (long) read_register (7));
1246 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1247 (long) read_register (8), (long) read_register (9),
1248 (long) read_register (10), (long) read_register (11),
1249 (long) read_register (12), (long) read_register (13),
1250 (long) read_register (14), (long) read_register (15));
1253 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1254 (long) read_register (A0G_REGNUM) & 0xff,
1255 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1256 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1257 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1258 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1259 (long) read_register (A1G_REGNUM) & 0xff,
1260 (long) read_register (A1_REGNUM),
1261 (long) read_register (M1_REGNUM),
1262 (long) read_register (X1_REGNUM),
1263 (long) read_register (Y1_REGNUM),
1264 (long) read_register (RE_REGNUM));
1268 sh4_show_regs (void)
1270 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1271 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1272 paddr (read_register (PC_REGNUM)),
1273 (long) read_register (SR_REGNUM),
1274 (long) read_register (PR_REGNUM),
1275 (long) read_register (MACH_REGNUM),
1276 (long) read_register (MACL_REGNUM));
1278 printf_filtered ("GBR=%08lx VBR=%08lx",
1279 (long) read_register (GBR_REGNUM),
1280 (long) read_register (VBR_REGNUM));
1281 printf_filtered (" SSR=%08lx SPC=%08lx",
1282 (long) read_register (SSR_REGNUM),
1283 (long) read_register (SPC_REGNUM));
1284 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1285 (long) read_register (FPUL_REGNUM),
1286 (long) read_register (FPSCR_REGNUM));
1289 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1290 (long) read_register (0), (long) read_register (1),
1291 (long) read_register (2), (long) read_register (3),
1292 (long) read_register (4), (long) read_register (5),
1293 (long) read_register (6), (long) read_register (7));
1294 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1295 (long) read_register (8), (long) read_register (9),
1296 (long) read_register (10), (long) read_register (11),
1297 (long) read_register (12), (long) read_register (13),
1298 (long) read_register (14), (long) read_register (15));
1300 printf_filtered ((pr
1301 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1303 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1304 (long) read_register (FP0_REGNUM + 0),
1305 (long) read_register (FP0_REGNUM + 1),
1306 (long) read_register (FP0_REGNUM + 2),
1307 (long) read_register (FP0_REGNUM + 3),
1308 (long) read_register (FP0_REGNUM + 4),
1309 (long) read_register (FP0_REGNUM + 5),
1310 (long) read_register (FP0_REGNUM + 6),
1311 (long) read_register (FP0_REGNUM + 7));
1312 printf_filtered ((pr ?
1313 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1314 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1315 (long) read_register (FP0_REGNUM + 8),
1316 (long) read_register (FP0_REGNUM + 9),
1317 (long) read_register (FP0_REGNUM + 10),
1318 (long) read_register (FP0_REGNUM + 11),
1319 (long) read_register (FP0_REGNUM + 12),
1320 (long) read_register (FP0_REGNUM + 13),
1321 (long) read_register (FP0_REGNUM + 14),
1322 (long) read_register (FP0_REGNUM + 15));
1326 sh_dsp_show_regs (void)
1328 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1329 paddr (read_register (PC_REGNUM)),
1330 (long) read_register (SR_REGNUM),
1331 (long) read_register (PR_REGNUM),
1332 (long) read_register (MACH_REGNUM),
1333 (long) read_register (MACL_REGNUM));
1335 printf_filtered ("GBR=%08lx VBR=%08lx",
1336 (long) read_register (GBR_REGNUM),
1337 (long) read_register (VBR_REGNUM));
1339 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1342 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1343 (long) read_register (0), (long) read_register (1),
1344 (long) read_register (2), (long) read_register (3),
1345 (long) read_register (4), (long) read_register (5),
1346 (long) read_register (6), (long) read_register (7));
1347 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1348 (long) read_register (8), (long) read_register (9),
1349 (long) read_register (10), (long) read_register (11),
1350 (long) read_register (12), (long) read_register (13),
1351 (long) read_register (14), (long) read_register (15));
1354 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1355 (long) read_register (A0G_REGNUM) & 0xff,
1356 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1357 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1358 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1359 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1360 (long) read_register (A1G_REGNUM) & 0xff,
1361 (long) read_register (A1_REGNUM),
1362 (long) read_register (M1_REGNUM),
1363 (long) read_register (X1_REGNUM),
1364 (long) read_register (Y1_REGNUM),
1365 (long) read_register (RE_REGNUM));
1369 sh_show_regs_command (char *args, int from_tty)
1375 /* Return the GDB type object for the "standard" data type
1376 of data in register N. */
1377 static struct type *
1378 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1380 if ((reg_nr >= FP0_REGNUM
1381 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1382 return builtin_type_float;
1384 return builtin_type_int;
1387 static struct type *
1388 sh_sh4_build_float_register_type (int high)
1392 temp = create_range_type (NULL, builtin_type_int, 0, high);
1393 return create_array_type (NULL, builtin_type_float, temp);
1396 static struct type *
1397 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1399 if ((reg_nr >= FP0_REGNUM
1400 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1401 return builtin_type_float;
1402 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1403 return builtin_type_double;
1404 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1405 return sh_sh4_build_float_register_type (3);
1407 return builtin_type_int;
1410 static struct type *
1411 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1413 return builtin_type_int;
1416 /* On the sh4, the DRi pseudo registers are problematic if the target
1417 is little endian. When the user writes one of those registers, for
1418 instance with 'ser var $dr0=1', we want the double to be stored
1420 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1421 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1423 This corresponds to little endian byte order & big endian word
1424 order. However if we let gdb write the register w/o conversion, it
1425 will write fr0 and fr1 this way:
1426 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1427 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1428 because it will consider fr0 and fr1 as a single LE stretch of memory.
1430 To achieve what we want we must force gdb to store things in
1431 floatformat_ieee_double_littlebyte_bigword (which is defined in
1432 include/floatformat.h and libiberty/floatformat.c.
1434 In case the target is big endian, there is no problem, the
1435 raw bytes will look like:
1436 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1437 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1439 The other pseudo registers (the FVs) also don't pose a problem
1440 because they are stored as 4 individual FP elements. */
1443 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1444 char *from, char *to)
1446 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1449 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1451 store_typed_floating (to, type, val);
1455 ("sh_register_convert_to_virtual called with non DR register number");
1459 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1460 const void *from, void *to)
1462 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1464 DOUBLEST val = extract_typed_floating (from, type);
1465 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1469 error ("sh_register_convert_to_raw called with non DR register number");
1472 /* For vectors of 4 floating point registers. */
1474 fv_reg_base_num (int fv_regnum)
1478 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1482 /* For double precision floating point registers, i.e 2 fp regs.*/
1484 dr_reg_base_num (int dr_regnum)
1488 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1493 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1494 int reg_nr, void *buffer)
1496 int base_regnum, portion;
1497 char temp_buffer[MAX_REGISTER_SIZE];
1499 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1501 base_regnum = dr_reg_base_num (reg_nr);
1503 /* Build the value in the provided buffer. */
1504 /* Read the real regs for which this one is an alias. */
1505 for (portion = 0; portion < 2; portion++)
1506 regcache_raw_read (regcache, base_regnum + portion,
1508 + register_size (gdbarch,
1509 base_regnum) * portion));
1510 /* We must pay attention to the endiannes. */
1511 sh_sh4_register_convert_to_virtual (reg_nr,
1512 gdbarch_register_type (gdbarch,
1514 temp_buffer, buffer);
1516 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1518 base_regnum = fv_reg_base_num (reg_nr);
1520 /* Read the real regs for which this one is an alias. */
1521 for (portion = 0; portion < 4; portion++)
1522 regcache_raw_read (regcache, base_regnum + portion,
1524 + register_size (gdbarch,
1525 base_regnum) * portion));
1530 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1531 int reg_nr, const void *buffer)
1533 int base_regnum, portion;
1534 char temp_buffer[MAX_REGISTER_SIZE];
1536 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1538 base_regnum = dr_reg_base_num (reg_nr);
1540 /* We must pay attention to the endiannes. */
1541 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1542 reg_nr, buffer, temp_buffer);
1544 /* Write the real regs for which this one is an alias. */
1545 for (portion = 0; portion < 2; portion++)
1546 regcache_raw_write (regcache, base_regnum + portion,
1548 + register_size (gdbarch,
1549 base_regnum) * portion));
1551 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1553 base_regnum = fv_reg_base_num (reg_nr);
1555 /* Write the real regs for which this one is an alias. */
1556 for (portion = 0; portion < 4; portion++)
1557 regcache_raw_write (regcache, base_regnum + portion,
1559 + register_size (gdbarch,
1560 base_regnum) * portion));
1564 /* Floating point vector of 4 float registers. */
1566 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1569 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1570 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1571 fv_regnum - FV0_REGNUM,
1572 (int) read_register (first_fp_reg_num),
1573 (int) read_register (first_fp_reg_num + 1),
1574 (int) read_register (first_fp_reg_num + 2),
1575 (int) read_register (first_fp_reg_num + 3));
1578 /* Double precision registers. */
1580 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1583 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1585 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1586 dr_regnum - DR0_REGNUM,
1587 (int) read_register (first_fp_reg_num),
1588 (int) read_register (first_fp_reg_num + 1));
1592 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1595 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1596 internal_error (__FILE__, __LINE__,
1597 "Invalid pseudo register number %d\n", regnum);
1598 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1599 do_dr_register_info (gdbarch, file, regnum);
1600 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1601 do_fv_register_info (gdbarch, file, regnum);
1605 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1606 { /* do values for FP (float) regs */
1608 double flt; /* double extracted from raw hex data */
1612 /* Allocate space for the float. */
1613 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1615 /* Get the data in raw format. */
1616 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1617 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1619 /* Get the register as a number */
1620 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1622 /* Print the name and some spaces. */
1623 fputs_filtered (REGISTER_NAME (regnum), file);
1624 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1626 /* Print the value. */
1628 fprintf_filtered (file, "<invalid float>");
1630 fprintf_filtered (file, "%-10.9g", flt);
1632 /* Print the fp register as hex. */
1633 fprintf_filtered (file, "\t(raw 0x");
1634 for (j = 0; j < register_size (gdbarch, regnum); j++)
1636 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1638 : register_size (gdbarch, regnum) - 1 - j);
1639 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1641 fprintf_filtered (file, ")");
1642 fprintf_filtered (file, "\n");
1646 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1648 char raw_buffer[MAX_REGISTER_SIZE];
1650 fputs_filtered (REGISTER_NAME (regnum), file);
1651 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1653 /* Get the data in raw format. */
1654 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1655 fprintf_filtered (file, "*value not available*\n");
1657 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1658 file, 'x', 1, 0, Val_pretty_default);
1659 fprintf_filtered (file, "\t");
1660 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1661 file, 0, 1, 0, Val_pretty_default);
1662 fprintf_filtered (file, "\n");
1666 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1668 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1669 internal_error (__FILE__, __LINE__,
1670 "Invalid register number %d\n", regnum);
1672 else if (regnum >= 0 && regnum < NUM_REGS)
1674 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1676 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1678 sh_do_register (gdbarch, file, regnum); /* All other regs */
1681 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1683 sh_print_pseudo_register (gdbarch, file, regnum);
1688 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1689 struct frame_info *frame, int regnum, int fpregs)
1691 if (regnum != -1) /* do one specified register */
1693 if (*(REGISTER_NAME (regnum)) == '\0')
1694 error ("Not a valid register for the current processor type");
1696 sh_print_register (gdbarch, file, regnum);
1699 /* do all (or most) registers */
1702 while (regnum < NUM_REGS)
1704 /* If the register name is empty, it is undefined for this
1705 processor, so don't display anything. */
1706 if (REGISTER_NAME (regnum) == NULL
1707 || *(REGISTER_NAME (regnum)) == '\0')
1713 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1718 /* true for "INFO ALL-REGISTERS" command */
1719 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1723 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
1727 sh_do_register (gdbarch, file, regnum); /* All other regs */
1733 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1735 sh_print_pseudo_register (gdbarch, file, regnum);
1741 #ifdef SVR4_SHARED_LIBS
1743 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1744 for native i386 linux targets using the struct offsets defined in
1745 link.h (but without actual reference to that file).
1747 This makes it possible to access i386-linux shared libraries from
1748 a gdb that was not built on an i386-linux host (for cross debugging).
1751 struct link_map_offsets *
1752 sh_linux_svr4_fetch_link_map_offsets (void)
1754 static struct link_map_offsets lmo;
1755 static struct link_map_offsets *lmp = 0;
1761 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1763 lmo.r_map_offset = 4;
1766 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1768 lmo.l_addr_offset = 0;
1769 lmo.l_addr_size = 4;
1771 lmo.l_name_offset = 4;
1772 lmo.l_name_size = 4;
1774 lmo.l_next_offset = 12;
1775 lmo.l_next_size = 4;
1777 lmo.l_prev_offset = 16;
1778 lmo.l_prev_size = 4;
1783 #endif /* SVR4_SHARED_LIBS */
1786 sh_dsp_register_sim_regno (int nr)
1788 if (legacy_register_sim_regno (nr) < 0)
1789 return legacy_register_sim_regno (nr);
1790 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1791 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1792 if (nr == MOD_REGNUM)
1793 return SIM_SH_MOD_REGNUM;
1794 if (nr == RS_REGNUM)
1795 return SIM_SH_RS_REGNUM;
1796 if (nr == RE_REGNUM)
1797 return SIM_SH_RE_REGNUM;
1798 if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1799 return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1803 static struct sh_frame_cache *
1804 sh_alloc_frame_cache (void)
1806 struct sh_frame_cache *cache;
1809 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1813 cache->saved_sp = 0;
1814 cache->sp_offset = 0;
1817 /* Frameless until proven otherwise. */
1820 /* Saved registers. We initialize these to -1 since zero is a valid
1821 offset (that's where fp is supposed to be stored). */
1822 for (i = 0; i < SH_NUM_REGS; i++)
1824 cache->saved_regs[i] = -1;
1830 static struct sh_frame_cache *
1831 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1833 struct sh_frame_cache *cache;
1834 CORE_ADDR current_pc;
1840 cache = sh_alloc_frame_cache ();
1841 *this_cache = cache;
1843 /* In principle, for normal frames, fp holds the frame pointer,
1844 which holds the base address for the current stack frame.
1845 However, for functions that don't need it, the frame pointer is
1846 optional. For these "frameless" functions the frame pointer is
1847 actually the frame pointer of the calling frame. */
1848 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1849 if (cache->base == 0)
1852 cache->pc = frame_func_unwind (next_frame);
1853 current_pc = frame_pc_unwind (next_frame);
1855 sh_analyze_prologue (cache->pc, current_pc, cache);
1857 if (!cache->uses_fp)
1859 /* We didn't find a valid frame, which means that CACHE->base
1860 currently holds the frame pointer for our calling frame. If
1861 we're at the start of a function, or somewhere half-way its
1862 prologue, the function's frame probably hasn't been fully
1863 setup yet. Try to reconstruct the base address for the stack
1864 frame by looking at the stack pointer. For truly "frameless"
1865 functions this might work too. */
1866 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1869 /* Now that we have the base address for the stack frame we can
1870 calculate the value of sp in the calling frame. */
1871 cache->saved_sp = cache->base + cache->sp_offset;
1873 /* Adjust all the saved registers such that they contain addresses
1874 instead of offsets. */
1875 for (i = 0; i < SH_NUM_REGS; i++)
1876 if (cache->saved_regs[i] != -1)
1877 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1883 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1884 int regnum, int *optimizedp,
1885 enum lval_type *lvalp, CORE_ADDR *addrp,
1886 int *realnump, void *valuep)
1888 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1890 gdb_assert (regnum >= 0);
1892 if (regnum == SP_REGNUM && cache->saved_sp)
1900 /* Store the value. */
1901 store_unsigned_integer (valuep, 4, cache->saved_sp);
1906 /* The PC of the previous frame is stored in the PR register of
1907 the current frame. Frob regnum so that we pull the value from
1908 the correct place. */
1909 if (regnum == PC_REGNUM)
1912 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
1915 *lvalp = lval_memory;
1916 *addrp = cache->saved_regs[regnum];
1920 /* Read the value in from memory. */
1921 read_memory (*addrp, valuep,
1922 register_size (current_gdbarch, regnum));
1927 frame_register_unwind (next_frame, regnum,
1928 optimizedp, lvalp, addrp, realnump, valuep);
1932 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
1933 struct frame_id *this_id)
1935 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1937 /* This marks the outermost frame. */
1938 if (cache->base == 0)
1941 *this_id = frame_id_build (cache->saved_sp, cache->pc);
1944 static const struct frame_unwind sh_frame_unwind = {
1947 sh_frame_prev_register
1950 static const struct frame_unwind *
1951 sh_frame_sniffer (struct frame_info *next_frame)
1953 return &sh_frame_unwind;
1957 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1959 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1963 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1965 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
1968 static struct frame_id
1969 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
1971 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
1972 frame_pc_unwind (next_frame));
1976 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
1978 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1983 static const struct frame_base sh_frame_base = {
1985 sh_frame_base_address,
1986 sh_frame_base_address,
1987 sh_frame_base_address
1990 /* The epilogue is defined here as the area at the end of a function,
1991 either on the `ret' instruction itself or after an instruction which
1992 destroys the function's stack frame. */
1994 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1996 CORE_ADDR func_addr = 0, func_end = 0;
1998 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2001 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2002 for a nop and some fixed data (e.g. big offsets) which are
2003 unfortunately also treated as part of the function (which
2004 means, they are below func_end. */
2005 CORE_ADDR addr = func_end - 28;
2006 if (addr < func_addr + 4)
2007 addr = func_addr + 4;
2011 /* First search forward until hitting an rts. */
2012 while (addr < func_end
2013 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2015 if (addr >= func_end)
2018 /* At this point we should find a mov.l @r15+,r14 instruction,
2019 either before or after the rts. If not, then the function has
2020 probably no "normal" epilogue and we bail out here. */
2021 inst = read_memory_unsigned_integer (addr - 2, 2);
2022 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2024 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2027 /* Step over possible lds.l @r15+,pr. */
2028 inst = read_memory_unsigned_integer (addr - 2, 2);
2032 inst = read_memory_unsigned_integer (addr - 2, 2);
2035 /* Step over possible mov r14,r15. */
2036 if (IS_MOV_FP_SP (inst))
2039 inst = read_memory_unsigned_integer (addr - 2, 2);
2042 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2044 while (addr > func_addr + 4
2045 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2048 inst = read_memory_unsigned_integer (addr - 2, 2);
2057 static gdbarch_init_ftype sh_gdbarch_init;
2059 static struct gdbarch *
2060 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2062 struct gdbarch *gdbarch;
2064 sh_show_regs = sh_generic_show_regs;
2065 switch (info.bfd_arch_info->mach)
2068 sh_show_regs = sh2e_show_regs;
2070 case bfd_mach_sh_dsp:
2071 sh_show_regs = sh_dsp_show_regs;
2075 sh_show_regs = sh3_show_regs;
2079 sh_show_regs = sh3e_show_regs;
2082 case bfd_mach_sh3_dsp:
2083 sh_show_regs = sh3_dsp_show_regs;
2087 sh_show_regs = sh4_show_regs;
2091 sh_show_regs = sh64_show_regs;
2092 /* SH5 is handled entirely in sh64-tdep.c */
2093 return sh64_gdbarch_init (info, arches);
2096 /* If there is already a candidate, use it. */
2097 arches = gdbarch_list_lookup_by_info (arches, &info);
2099 return arches->gdbarch;
2101 /* None found, create a new architecture from the information
2103 gdbarch = gdbarch_alloc (&info, NULL);
2105 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2106 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2107 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2108 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2109 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2110 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2111 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2112 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2114 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2115 set_gdbarch_sp_regnum (gdbarch, 15);
2116 set_gdbarch_pc_regnum (gdbarch, 16);
2117 set_gdbarch_fp0_regnum (gdbarch, -1);
2118 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2120 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2122 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2124 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2125 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2127 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2128 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2130 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2132 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2133 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2134 set_gdbarch_extract_struct_value_address (gdbarch,
2135 sh_extract_struct_value_address);
2137 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2138 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2139 set_gdbarch_decr_pc_after_break (gdbarch, 0);
2140 set_gdbarch_function_start_offset (gdbarch, 0);
2142 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2144 set_gdbarch_frame_args_skip (gdbarch, 0);
2145 set_gdbarch_frameless_function_invocation (gdbarch,
2146 frameless_look_for_prologue);
2147 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2149 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2150 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2151 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2152 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2153 frame_base_set_default (gdbarch, &sh_frame_base);
2155 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2157 switch (info.bfd_arch_info->mach)
2160 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2164 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2168 /* doubles on sh2e and sh3e are actually 4 byte. */
2169 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2171 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2172 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2173 set_gdbarch_fp0_regnum (gdbarch, 25);
2174 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2175 set_gdbarch_extract_return_value (gdbarch,
2176 sh3e_sh4_extract_return_value);
2177 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2180 case bfd_mach_sh_dsp:
2181 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2182 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2186 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2190 /* doubles on sh2e and sh3e are actually 4 byte. */
2191 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2193 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2194 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2195 set_gdbarch_fp0_regnum (gdbarch, 25);
2196 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2197 set_gdbarch_extract_return_value (gdbarch,
2198 sh3e_sh4_extract_return_value);
2199 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2202 case bfd_mach_sh3_dsp:
2203 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2204 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2208 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2209 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2210 set_gdbarch_fp0_regnum (gdbarch, 25);
2211 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2212 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2213 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2214 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2215 set_gdbarch_extract_return_value (gdbarch,
2216 sh3e_sh4_extract_return_value);
2217 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2221 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
2225 /* Hook in ABI-specific overrides, if they have been registered. */
2226 gdbarch_init_osabi (info, gdbarch);
2228 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2229 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2234 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2237 _initialize_sh_tdep (void)
2239 struct cmd_list_element *c;
2241 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2243 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");