1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
39 #include "gdb_string.h"
40 #include "gdb_assert.h"
41 #include "arch-utils.h"
42 #include "floatformat.h"
50 #include "solib-svr4.h"
54 /* registers numbers shared with the simulator */
55 #include "gdb/sim-sh.h"
57 static void (*sh_show_regs) (void);
59 #define SH_NUM_REGS 59
68 /* Flag showing that a frame has been created in the prologue code. */
71 /* Saved registers. */
72 CORE_ADDR saved_regs[SH_NUM_REGS];
77 sh_generic_register_name (int reg_nr)
79 static char *register_names[] = {
80 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
81 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
82 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
84 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
85 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
87 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
88 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
92 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return register_names[reg_nr];
98 sh_sh_register_name (int reg_nr)
100 static char *register_names[] = {
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
108 "", "", "", "", "", "", "", "",
109 "", "", "", "", "", "", "", "",
113 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
115 return register_names[reg_nr];
119 sh_sh3_register_name (int reg_nr)
121 static char *register_names[] = {
122 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
123 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
124 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
126 "", "", "", "", "", "", "", "",
127 "", "", "", "", "", "", "", "",
129 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
130 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
134 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
136 return register_names[reg_nr];
140 sh_sh3e_register_name (int reg_nr)
142 static char *register_names[] = {
143 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
144 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
145 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
147 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
148 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
150 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
151 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
155 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
157 return register_names[reg_nr];
161 sh_sh2e_register_name (int reg_nr)
163 static char *register_names[] = {
164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
169 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
171 "", "", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
176 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
178 return register_names[reg_nr];
182 sh_sh_dsp_register_name (int reg_nr)
184 static char *register_names[] = {
185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
192 "rs", "re", "", "", "", "", "", "",
193 "", "", "", "", "", "", "", "",
197 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
199 return register_names[reg_nr];
203 sh_sh3_dsp_register_name (int reg_nr)
205 static char *register_names[] = {
206 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
207 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
208 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
210 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
211 "y0", "y1", "", "", "", "", "", "mod",
213 "rs", "re", "", "", "", "", "", "",
214 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
215 "", "", "", "", "", "", "", "",
219 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
221 return register_names[reg_nr];
225 sh_sh4_register_name (int reg_nr)
227 static char *register_names[] = {
228 /* general registers 0-15 */
229 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
230 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
232 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
235 /* floating point registers 25 - 40 */
236 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
237 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
241 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
243 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
244 /* double precision (pseudo) 59 - 66 */
245 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
246 /* vectors (pseudo) 67 - 70 */
247 "fv0", "fv4", "fv8", "fv12",
248 /* FIXME: missing XF 71 - 86 */
249 /* FIXME: missing XD 87 - 94 */
253 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
255 return register_names[reg_nr];
259 sh_sh4_nofpu_register_name (int reg_nr)
261 static char *register_names[] = {
262 /* general registers 0-15 */
263 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
264 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
266 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
269 /* floating point registers 25 - 40 -- not for nofpu target */
270 "", "", "", "", "", "", "", "",
271 "", "", "", "", "", "", "", "",
275 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
277 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
278 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
279 "", "", "", "", "", "", "", "",
280 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
285 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
287 return register_names[reg_nr];
291 sh_sh4al_dsp_register_name (int reg_nr)
293 static char *register_names[] = {
294 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
295 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
296 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
298 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
299 "y0", "y1", "", "", "", "", "", "mod",
301 "rs", "re", "", "", "", "", "", "",
302 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
303 "", "", "", "", "", "", "", "",
307 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
309 return register_names[reg_nr];
312 static const unsigned char *
313 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
315 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
316 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
318 *lenptr = sizeof (breakpoint);
322 /* Prologue looks like
326 sub <room_for_loca_vars>,r15
329 Actually it can be more complicated than this but that's it, basically.
332 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
333 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
335 /* STS.L PR,@-r15 0100111100100010
336 r15-4-->r15, PR-->(r15) */
337 #define IS_STS(x) ((x) == 0x4f22)
339 /* MOV.L Rm,@-r15 00101111mmmm0110
340 r15-4-->r15, Rm-->(R15) */
341 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
343 /* MOV r15,r14 0110111011110011
345 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
347 /* ADD #imm,r15 01111111iiiiiiii
349 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
351 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
352 #define IS_SHLL_R3(x) ((x) == 0x4300)
354 /* ADD r3,r15 0011111100111100
356 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
358 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
359 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
360 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
361 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
362 make this entirely clear. */
363 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
364 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
366 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
367 #define IS_MOV_ARG_TO_REG(x) \
368 (((x) & 0xf00f) == 0x6003 && \
369 ((x) & 0x00f0) >= 0x0040 && \
370 ((x) & 0x00f0) <= 0x0070)
371 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
372 #define IS_MOV_ARG_TO_IND_R14(x) \
373 (((x) & 0xff0f) == 0x2e02 && \
374 ((x) & 0x00f0) >= 0x0040 && \
375 ((x) & 0x00f0) <= 0x0070)
376 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
377 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
378 (((x) & 0xff00) == 0x1e00 && \
379 ((x) & 0x00f0) >= 0x0040 && \
380 ((x) & 0x00f0) <= 0x0070)
382 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
383 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
384 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
385 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
386 /* SUB Rn,R15 00111111nnnn1000 */
387 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
389 #define FPSCR_SZ (1 << 20)
391 /* The following instructions are used for epilogue testing. */
392 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
393 #define IS_RTS(x) ((x) == 0x000b)
394 #define IS_LDS(x) ((x) == 0x4f26)
395 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
396 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
397 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
399 /* Disassemble an instruction. */
401 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
403 info->endian = TARGET_BYTE_ORDER;
404 return print_insn_sh (memaddr, info);
408 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
409 struct sh_frame_cache *cache)
416 int reg, sav_reg = -1;
418 if (pc >= current_pc)
422 for (opc = pc + (2 * 28); pc < opc; pc += 2)
424 inst = read_memory_unsigned_integer (pc, 2);
425 /* See where the registers will be saved to */
428 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
429 cache->sp_offset += 4;
431 else if (IS_STS (inst))
433 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
434 cache->sp_offset += 4;
436 else if (IS_MOV_R3 (inst))
438 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
440 else if (IS_SHLL_R3 (inst))
444 else if (IS_ADD_R3SP (inst))
446 cache->sp_offset += -r3_val;
448 else if (IS_ADD_IMM_SP (inst))
450 offset = ((inst & 0xff) ^ 0x80) - 0x80;
451 cache->sp_offset -= offset;
453 else if (IS_MOVW_PCREL_TO_REG (inst))
457 reg = GET_TARGET_REG (inst);
461 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
463 read_memory_integer (((pc + 4) & ~3) + offset, 2);
467 else if (IS_MOVL_PCREL_TO_REG (inst))
471 reg = (inst & 0x0f00) >> 8;
475 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
477 read_memory_integer (((pc + 4) & ~3) + offset, 4);
481 else if (IS_SUB_REG_FROM_SP (inst))
483 reg = GET_SOURCE_REG (inst);
484 if (sav_reg > 0 && reg == sav_reg)
488 cache->sp_offset += sav_offset;
490 else if (IS_FPUSH (inst))
492 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
494 cache->sp_offset += 8;
498 cache->sp_offset += 4;
501 else if (IS_MOV_SP_FP (inst))
505 /* At this point, only allow argument register moves to other
506 registers or argument register moves to @(X,fp) which are
507 moving the register arguments onto the stack area allocated
508 by a former add somenumber to SP call. Don't allow moving
509 to an fp indirect address above fp + cache->sp_offset. */
511 for (opc = pc + 12; pc < opc; pc += 2)
513 inst = read_memory_integer (pc, 2);
514 if (IS_MOV_ARG_TO_IND_R14 (inst))
516 reg = GET_SOURCE_REG (inst);
517 if (cache->sp_offset > 0)
518 cache->saved_regs[reg] = cache->sp_offset;
520 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
522 reg = GET_SOURCE_REG (inst);
523 offset = (inst & 0xf) * 4;
524 if (cache->sp_offset > offset)
525 cache->saved_regs[reg] = cache->sp_offset - offset;
527 else if (IS_MOV_ARG_TO_REG (inst))
534 #if 0 /* This used to just stop when it found an instruction that
535 was not considered part of the prologue. Now, we just
536 keep going looking for likely instructions. */
545 /* Skip any prologue before the guts of a function */
547 /* Skip the prologue using the debug information. If this fails we'll
548 fall back on the 'guess' method below. */
550 after_prologue (CORE_ADDR pc)
552 struct symtab_and_line sal;
553 CORE_ADDR func_addr, func_end;
555 /* If we can not find the symbol in the partial symbol table, then
556 there is no hope we can determine the function's start address
558 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
561 /* Get the line associated with FUNC_ADDR. */
562 sal = find_pc_line (func_addr, 0);
564 /* There are only two cases to consider. First, the end of the source line
565 is within the function bounds. In that case we return the end of the
566 source line. Second is the end of the source line extends beyond the
567 bounds of the current function. We need to use the slow code to
568 examine instructions in that case. */
569 if (sal.end < func_end)
576 sh_skip_prologue (CORE_ADDR start_pc)
579 struct sh_frame_cache cache;
581 /* See if we can determine the end of the prologue via the symbol table.
582 If so, then return either PC, or the PC after the prologue, whichever
584 pc = after_prologue (start_pc);
586 /* If after_prologue returned a useful address, then use it. Else
587 fall back on the instruction skipping code. */
589 return max (pc, start_pc);
591 cache.sp_offset = -4;
592 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
601 Aggregate types not bigger than 8 bytes that have the same size and
602 alignment as one of the integer scalar types are returned in the
603 same registers as the integer type they match.
605 For example, a 2-byte aligned structure with size 2 bytes has the
606 same size and alignment as a short int, and will be returned in R0.
607 A 4-byte aligned structure with size 8 bytes has the same size and
608 alignment as a long long int, and will be returned in R0 and R1.
610 When an aggregate type is returned in R0 and R1, R0 contains the
611 first four bytes of the aggregate, and R1 contains the
612 remainder. If the size of the aggregate type is not a multiple of 4
613 bytes, the aggregate is tail-padded up to a multiple of 4
614 bytes. The value of the padding is undefined. For little-endian
615 targets the padding will appear at the most significant end of the
616 last element, for big-endian targets the padding appears at the
617 least significant end of the last element.
619 All other aggregate types are returned by address. The caller
620 function passes the address of an area large enough to hold the
621 aggregate value in R2. The called function stores the result in
624 To reiterate, structs smaller than 8 bytes could also be returned
625 in memory, if they don't pass the "same size and alignment as an
630 struct s { char c[3]; } wibble;
631 struct s foo(void) { return wibble; }
633 the return value from foo() will be in memory, not
634 in R0, because there is no 3-byte integer type.
638 struct s { char c[2]; } wibble;
639 struct s foo(void) { return wibble; }
641 because a struct containing two chars has alignment 1, that matches
642 type char, but size 2, that matches type short. There's no integer
643 type that has alignment 1 and size 2, so the struct is returned in
649 sh_use_struct_convention (int gcc_p, struct type *type)
651 int len = TYPE_LENGTH (type);
652 int nelem = TYPE_NFIELDS (type);
654 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
655 fit in two registers anyway) use struct convention. */
656 if (len != 1 && len != 2 && len != 4 && len != 8)
659 /* Scalar types and aggregate types with exactly one field are aligned
660 by definition. They are returned in registers. */
664 /* If the first field in the aggregate has the same length as the entire
665 aggregate type, the type is returned in registers. */
666 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
669 /* If the size of the aggregate is 8 bytes and the first field is
670 of size 4 bytes its alignment is equal to long long's alignment,
671 so it's returned in registers. */
672 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
675 /* Otherwise use struct convention. */
679 /* Extract from an array REGBUF containing the (raw) register state
680 the address in which a function should return its structure value,
681 as a CORE_ADDR (or an expression that can be used as one). */
683 sh_extract_struct_value_address (struct regcache *regcache)
687 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
692 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
697 /* Function: push_dummy_call (formerly push_arguments)
698 Setup the function arguments for calling a function in the inferior.
700 On the Renesas SH architecture, there are four registers (R4 to R7)
701 which are dedicated for passing function arguments. Up to the first
702 four arguments (depending on size) may go into these registers.
703 The rest go on the stack.
705 MVS: Except on SH variants that have floating point registers.
706 In that case, float and double arguments are passed in the same
707 manner, but using FP registers instead of GP registers.
709 Arguments that are smaller than 4 bytes will still take up a whole
710 register or a whole 32-bit word on the stack, and will be
711 right-justified in the register or the stack word. This includes
712 chars, shorts, and small aggregate types.
714 Arguments that are larger than 4 bytes may be split between two or
715 more registers. If there are not enough registers free, an argument
716 may be passed partly in a register (or registers), and partly on the
717 stack. This includes doubles, long longs, and larger aggregates.
718 As far as I know, there is no upper limit to the size of aggregates
719 that will be passed in this way; in other words, the convention of
720 passing a pointer to a large aggregate instead of a copy is not used.
722 MVS: The above appears to be true for the SH variants that do not
723 have an FPU, however those that have an FPU appear to copy the
724 aggregate argument onto the stack (and not place it in registers)
725 if it is larger than 16 bytes (four GP registers).
727 An exceptional case exists for struct arguments (and possibly other
728 aggregates such as arrays) if the size is larger than 4 bytes but
729 not a multiple of 4 bytes. In this case the argument is never split
730 between the registers and the stack, but instead is copied in its
731 entirety onto the stack, AND also copied into as many registers as
732 there is room for. In other words, space in registers permitting,
733 two copies of the same argument are passed in. As far as I can tell,
734 only the one on the stack is used, although that may be a function
735 of the level of compiler optimization. I suspect this is a compiler
736 bug. Arguments of these odd sizes are left-justified within the
737 word (as opposed to arguments smaller than 4 bytes, which are
740 If the function is to return an aggregate type such as a struct, it
741 is either returned in the normal return value register R0 (if its
742 size is no greater than one byte), or else the caller must allocate
743 space into which the callee will copy the return value (if the size
744 is greater than one byte). In this case, a pointer to the return
745 value location is passed into the callee in register R2, which does
746 not displace any of the other arguments passed in via registers R4
749 /* Helper function to justify value in register according to endianess. */
751 sh_justify_value_in_reg (struct value *val, int len)
753 static char valbuf[4];
755 memset (valbuf, 0, sizeof (valbuf));
758 /* value gets right-justified in the register or stack word */
759 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
760 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
762 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
765 return (char *) VALUE_CONTENTS (val);
768 /* Helper function to eval number of bytes to allocate on stack. */
770 sh_stack_allocsize (int nargs, struct value **args)
774 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
778 /* Helper functions for getting the float arguments right. Registers usage
779 depends on the ABI and the endianess. The comments should enlighten how
780 it's intended to work. */
782 /* This array stores which of the float arg registers are already in use. */
783 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
785 /* This function just resets the above array to "no reg used so far". */
787 sh_init_flt_argreg (void)
789 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
792 /* This function returns the next register to use for float arg passing.
793 It returns either a valid value between FLOAT_ARG0_REGNUM and
794 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
795 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
797 Note that register number 0 in flt_argreg_array corresponds with the
798 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
799 29) the parity of the register number is preserved, which is important
800 for the double register passing test (see the "argreg & 1" test below). */
802 sh_next_flt_argreg (int len)
806 /* First search for the next free register. */
807 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
809 if (!flt_argreg_array[argreg])
812 /* No register left? */
813 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
814 return FLOAT_ARGLAST_REGNUM + 1;
818 /* Doubles are always starting in a even register number. */
821 flt_argreg_array[argreg] = 1;
825 /* No register left? */
826 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
827 return FLOAT_ARGLAST_REGNUM + 1;
829 /* Also mark the next register as used. */
830 flt_argreg_array[argreg + 1] = 1;
832 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
834 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
835 if (!flt_argreg_array[argreg + 1])
838 flt_argreg_array[argreg] = 1;
839 return FLOAT_ARG0_REGNUM + argreg;
842 /* Helper function which figures out, if a type is treated like a float type.
844 The FPU ABIs have a special way how to treat types as float types.
845 Structures with exactly one member, which is of type float or double, are
846 treated exactly as the base types float or double:
856 are handled the same way as just
862 As a result, arguments of these struct types are pushed into floating point
863 registers exactly as floats or doubles, using the same decision algorithm.
865 The same is valid if these types are used as function return types. The
866 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
867 or even using struct convention as it is for other structs. */
870 sh_treat_as_flt_p (struct type *type)
872 int len = TYPE_LENGTH (type);
874 /* Ordinary float types are obviously treated as float. */
875 if (TYPE_CODE (type) == TYPE_CODE_FLT)
877 /* Otherwise non-struct types are not treated as float. */
878 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
880 /* Otherwise structs with more than one memeber are not treated as float. */
881 if (TYPE_NFIELDS (type) != 1)
883 /* Otherwise if the type of that member is float, the whole type is
885 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
887 /* Otherwise it's not treated as float. */
892 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
894 struct regcache *regcache,
895 CORE_ADDR bp_addr, int nargs,
897 CORE_ADDR sp, int struct_return,
898 CORE_ADDR struct_addr)
900 int stack_offset = 0;
901 int argreg = ARG0_REGNUM;
907 int len, reg_size = 0;
908 int pass_on_stack = 0;
911 /* first force sp to a 4-byte alignment */
912 sp = sh_frame_align (gdbarch, sp);
915 regcache_cooked_write_unsigned (regcache,
916 STRUCT_RETURN_REGNUM, struct_addr);
918 /* make room on stack for args */
919 sp -= sh_stack_allocsize (nargs, args);
921 /* Initialize float argument mechanism. */
922 sh_init_flt_argreg ();
924 /* Now load as many as possible of the first arguments into
925 registers, and push the rest onto the stack. There are 16 bytes
926 in four registers available. Loop thru args from first to last. */
927 for (argnum = 0; argnum < nargs; argnum++)
929 type = VALUE_TYPE (args[argnum]);
930 len = TYPE_LENGTH (type);
931 val = sh_justify_value_in_reg (args[argnum], len);
933 /* Some decisions have to be made how various types are handled.
934 This also differs in different ABIs. */
937 /* Find out the next register to use for a floating point value. */
938 treat_as_flt = sh_treat_as_flt_p (type);
940 flt_argreg = sh_next_flt_argreg (len);
941 /* In contrast to non-FPU CPUs, arguments are never split between
942 registers and stack. If an argument doesn't fit in the remaining
943 registers it's always pushed entirely on the stack. */
944 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
949 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
950 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
953 /* The data goes entirely on the stack, 4-byte aligned. */
954 reg_size = (len + 3) & ~3;
955 write_memory (sp + stack_offset, val, reg_size);
956 stack_offset += reg_size;
958 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
960 /* Argument goes in a float argument register. */
961 reg_size = register_size (gdbarch, flt_argreg);
962 regval = extract_unsigned_integer (val, reg_size);
963 /* In little endian mode, float types taking two registers
964 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
965 be stored swapped in the argument registers. The below
966 code first writes the first 32 bits in the next but one
967 register, increments the val and len values accordingly
968 and then proceeds as normal by writing the second 32 bits
969 into the next register. */
970 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
971 && TYPE_LENGTH (type) == 2 * reg_size)
973 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
977 regval = extract_unsigned_integer (val, reg_size);
979 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
981 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
983 /* there's room in a register */
984 reg_size = register_size (gdbarch, argreg);
985 regval = extract_unsigned_integer (val, reg_size);
986 regcache_cooked_write_unsigned (regcache, argreg++, regval);
988 /* Store the value one register at a time or in one step on stack. */
994 /* Store return address. */
995 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
997 /* Update stack pointer. */
998 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1004 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1005 CORE_ADDR func_addr,
1006 struct regcache *regcache,
1008 int nargs, struct value **args,
1009 CORE_ADDR sp, int struct_return,
1010 CORE_ADDR struct_addr)
1012 int stack_offset = 0;
1013 int argreg = ARG0_REGNUM;
1020 /* first force sp to a 4-byte alignment */
1021 sp = sh_frame_align (gdbarch, sp);
1024 regcache_cooked_write_unsigned (regcache,
1025 STRUCT_RETURN_REGNUM, struct_addr);
1027 /* make room on stack for args */
1028 sp -= sh_stack_allocsize (nargs, args);
1030 /* Now load as many as possible of the first arguments into
1031 registers, and push the rest onto the stack. There are 16 bytes
1032 in four registers available. Loop thru args from first to last. */
1033 for (argnum = 0; argnum < nargs; argnum++)
1035 type = VALUE_TYPE (args[argnum]);
1036 len = TYPE_LENGTH (type);
1037 val = sh_justify_value_in_reg (args[argnum], len);
1041 if (argreg > ARGLAST_REGNUM)
1043 /* The remainder of the data goes entirely on the stack,
1045 reg_size = (len + 3) & ~3;
1046 write_memory (sp + stack_offset, val, reg_size);
1047 stack_offset += reg_size;
1049 else if (argreg <= ARGLAST_REGNUM)
1051 /* there's room in a register */
1052 reg_size = register_size (gdbarch, argreg);
1053 regval = extract_unsigned_integer (val, reg_size);
1054 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1056 /* Store the value reg_size bytes at a time. This means that things
1057 larger than reg_size bytes may go partly in registers and partly
1064 /* Store return address. */
1065 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1067 /* Update stack pointer. */
1068 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1073 /* Find a function's return value in the appropriate registers (in
1074 regbuf), and copy it into valbuf. Extract from an array REGBUF
1075 containing the (raw) register state a function return value of type
1076 TYPE, and copy that, in virtual format, into VALBUF. */
1078 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1081 int len = TYPE_LENGTH (type);
1082 int return_register = R0_REGNUM;
1089 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1090 store_unsigned_integer (valbuf, len, c);
1094 int i, regnum = R0_REGNUM;
1095 for (i = 0; i < len; i += 4)
1096 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1099 error ("bad size for return value");
1103 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1106 if (sh_treat_as_flt_p (type))
1108 int len = TYPE_LENGTH (type);
1109 int i, regnum = FP0_REGNUM;
1110 for (i = 0; i < len; i += 4)
1111 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1112 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1114 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1117 sh_default_extract_return_value (type, regcache, valbuf);
1120 /* Write into appropriate registers a function return value
1121 of type TYPE, given in virtual format.
1122 If the architecture is sh4 or sh3e, store a function's return value
1123 in the R0 general register or in the FP0 floating point register,
1124 depending on the type of the return value. In all the other cases
1125 the result is stored in r0, left-justified. */
1127 sh_default_store_return_value (struct type *type, struct regcache *regcache,
1131 int len = TYPE_LENGTH (type);
1135 val = extract_unsigned_integer (valbuf, len);
1136 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1140 int i, regnum = R0_REGNUM;
1141 for (i = 0; i < len; i += 4)
1142 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1147 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1150 if (sh_treat_as_flt_p (type))
1152 int len = TYPE_LENGTH (type);
1153 int i, regnum = FP0_REGNUM;
1154 for (i = 0; i < len; i += 4)
1155 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1158 sh_default_store_return_value (type, regcache, valbuf);
1161 /* Print the registers in a form similar to the E7000 */
1164 sh_generic_show_regs (void)
1166 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1167 paddr (read_register (PC_REGNUM)),
1168 (long) read_register (SR_REGNUM),
1169 (long) read_register (PR_REGNUM),
1170 (long) read_register (MACH_REGNUM),
1171 (long) read_register (MACL_REGNUM));
1173 printf_filtered ("GBR=%08lx VBR=%08lx",
1174 (long) read_register (GBR_REGNUM),
1175 (long) read_register (VBR_REGNUM));
1178 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1179 (long) read_register (0), (long) read_register (1),
1180 (long) read_register (2), (long) read_register (3),
1181 (long) read_register (4), (long) read_register (5),
1182 (long) read_register (6), (long) read_register (7));
1183 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1184 (long) read_register (8), (long) read_register (9),
1185 (long) read_register (10), (long) read_register (11),
1186 (long) read_register (12), (long) read_register (13),
1187 (long) read_register (14), (long) read_register (15));
1191 sh3_show_regs (void)
1193 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1194 paddr (read_register (PC_REGNUM)),
1195 (long) read_register (SR_REGNUM),
1196 (long) read_register (PR_REGNUM),
1197 (long) read_register (MACH_REGNUM),
1198 (long) read_register (MACL_REGNUM));
1200 printf_filtered ("GBR=%08lx VBR=%08lx",
1201 (long) read_register (GBR_REGNUM),
1202 (long) read_register (VBR_REGNUM));
1203 printf_filtered (" SSR=%08lx SPC=%08lx",
1204 (long) read_register (SSR_REGNUM),
1205 (long) read_register (SPC_REGNUM));
1208 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1209 (long) read_register (0), (long) read_register (1),
1210 (long) read_register (2), (long) read_register (3),
1211 (long) read_register (4), (long) read_register (5),
1212 (long) read_register (6), (long) read_register (7));
1213 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1214 (long) read_register (8), (long) read_register (9),
1215 (long) read_register (10), (long) read_register (11),
1216 (long) read_register (12), (long) read_register (13),
1217 (long) read_register (14), (long) read_register (15));
1222 sh2e_show_regs (void)
1224 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1225 paddr (read_register (PC_REGNUM)),
1226 (long) read_register (SR_REGNUM),
1227 (long) read_register (PR_REGNUM),
1228 (long) read_register (MACH_REGNUM),
1229 (long) read_register (MACL_REGNUM));
1231 printf_filtered ("GBR=%08lx VBR=%08lx",
1232 (long) read_register (GBR_REGNUM),
1233 (long) read_register (VBR_REGNUM));
1234 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1235 (long) read_register (FPUL_REGNUM),
1236 (long) read_register (FPSCR_REGNUM));
1239 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1240 (long) read_register (0), (long) read_register (1),
1241 (long) read_register (2), (long) read_register (3),
1242 (long) read_register (4), (long) read_register (5),
1243 (long) read_register (6), (long) read_register (7));
1244 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1245 (long) read_register (8), (long) read_register (9),
1246 (long) read_register (10), (long) read_register (11),
1247 (long) read_register (12), (long) read_register (13),
1248 (long) read_register (14), (long) read_register (15));
1250 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1251 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1255 sh3e_show_regs (void)
1257 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1258 paddr (read_register (PC_REGNUM)),
1259 (long) read_register (SR_REGNUM),
1260 (long) read_register (PR_REGNUM),
1261 (long) read_register (MACH_REGNUM),
1262 (long) read_register (MACL_REGNUM));
1264 printf_filtered ("GBR=%08lx VBR=%08lx",
1265 (long) read_register (GBR_REGNUM),
1266 (long) read_register (VBR_REGNUM));
1267 printf_filtered (" SSR=%08lx SPC=%08lx",
1268 (long) read_register (SSR_REGNUM),
1269 (long) read_register (SPC_REGNUM));
1270 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1271 (long) read_register (FPUL_REGNUM),
1272 (long) read_register (FPSCR_REGNUM));
1275 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1276 (long) read_register (0), (long) read_register (1),
1277 (long) read_register (2), (long) read_register (3),
1278 (long) read_register (4), (long) read_register (5),
1279 (long) read_register (6), (long) read_register (7));
1280 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1281 (long) read_register (8), (long) read_register (9),
1282 (long) read_register (10), (long) read_register (11),
1283 (long) read_register (12), (long) read_register (13),
1284 (long) read_register (14), (long) read_register (15));
1286 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1287 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1291 sh3_dsp_show_regs (void)
1293 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1294 paddr (read_register (PC_REGNUM)),
1295 (long) read_register (SR_REGNUM),
1296 (long) read_register (PR_REGNUM),
1297 (long) read_register (MACH_REGNUM),
1298 (long) read_register (MACL_REGNUM));
1300 printf_filtered ("GBR=%08lx VBR=%08lx",
1301 (long) read_register (GBR_REGNUM),
1302 (long) read_register (VBR_REGNUM));
1304 printf_filtered (" SSR=%08lx SPC=%08lx",
1305 (long) read_register (SSR_REGNUM),
1306 (long) read_register (SPC_REGNUM));
1308 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1311 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1312 (long) read_register (0), (long) read_register (1),
1313 (long) read_register (2), (long) read_register (3),
1314 (long) read_register (4), (long) read_register (5),
1315 (long) read_register (6), (long) read_register (7));
1316 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1317 (long) read_register (8), (long) read_register (9),
1318 (long) read_register (10), (long) read_register (11),
1319 (long) read_register (12), (long) read_register (13),
1320 (long) read_register (14), (long) read_register (15));
1323 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1324 (long) read_register (A0G_REGNUM) & 0xff,
1325 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1326 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1327 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1328 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1329 (long) read_register (A1G_REGNUM) & 0xff,
1330 (long) read_register (A1_REGNUM),
1331 (long) read_register (M1_REGNUM),
1332 (long) read_register (X1_REGNUM),
1333 (long) read_register (Y1_REGNUM),
1334 (long) read_register (RE_REGNUM));
1338 sh4_show_regs (void)
1340 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1341 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1342 paddr (read_register (PC_REGNUM)),
1343 (long) read_register (SR_REGNUM),
1344 (long) read_register (PR_REGNUM),
1345 (long) read_register (MACH_REGNUM),
1346 (long) read_register (MACL_REGNUM));
1348 printf_filtered ("GBR=%08lx VBR=%08lx",
1349 (long) read_register (GBR_REGNUM),
1350 (long) read_register (VBR_REGNUM));
1351 printf_filtered (" SSR=%08lx SPC=%08lx",
1352 (long) read_register (SSR_REGNUM),
1353 (long) read_register (SPC_REGNUM));
1354 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1355 (long) read_register (FPUL_REGNUM),
1356 (long) read_register (FPSCR_REGNUM));
1359 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1360 (long) read_register (0), (long) read_register (1),
1361 (long) read_register (2), (long) read_register (3),
1362 (long) read_register (4), (long) read_register (5),
1363 (long) read_register (6), (long) read_register (7));
1364 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1365 (long) read_register (8), (long) read_register (9),
1366 (long) read_register (10), (long) read_register (11),
1367 (long) read_register (12), (long) read_register (13),
1368 (long) read_register (14), (long) read_register (15));
1370 printf_filtered ((pr
1371 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1373 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1374 (long) read_register (FP0_REGNUM + 0),
1375 (long) read_register (FP0_REGNUM + 1),
1376 (long) read_register (FP0_REGNUM + 2),
1377 (long) read_register (FP0_REGNUM + 3),
1378 (long) read_register (FP0_REGNUM + 4),
1379 (long) read_register (FP0_REGNUM + 5),
1380 (long) read_register (FP0_REGNUM + 6),
1381 (long) read_register (FP0_REGNUM + 7));
1382 printf_filtered ((pr ?
1383 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1384 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1385 (long) read_register (FP0_REGNUM + 8),
1386 (long) read_register (FP0_REGNUM + 9),
1387 (long) read_register (FP0_REGNUM + 10),
1388 (long) read_register (FP0_REGNUM + 11),
1389 (long) read_register (FP0_REGNUM + 12),
1390 (long) read_register (FP0_REGNUM + 13),
1391 (long) read_register (FP0_REGNUM + 14),
1392 (long) read_register (FP0_REGNUM + 15));
1396 sh4_nofpu_show_regs (void)
1398 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1399 paddr (read_register (PC_REGNUM)),
1400 (long) read_register (SR_REGNUM),
1401 (long) read_register (PR_REGNUM),
1402 (long) read_register (MACH_REGNUM),
1403 (long) read_register (MACL_REGNUM));
1405 printf_filtered ("GBR=%08lx VBR=%08lx",
1406 (long) read_register (GBR_REGNUM),
1407 (long) read_register (VBR_REGNUM));
1408 printf_filtered (" SSR=%08lx SPC=%08lx",
1409 (long) read_register (SSR_REGNUM),
1410 (long) read_register (SPC_REGNUM));
1413 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1414 (long) read_register (0), (long) read_register (1),
1415 (long) read_register (2), (long) read_register (3),
1416 (long) read_register (4), (long) read_register (5),
1417 (long) read_register (6), (long) read_register (7));
1418 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1419 (long) read_register (8), (long) read_register (9),
1420 (long) read_register (10), (long) read_register (11),
1421 (long) read_register (12), (long) read_register (13),
1422 (long) read_register (14), (long) read_register (15));
1426 sh_dsp_show_regs (void)
1428 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1429 paddr (read_register (PC_REGNUM)),
1430 (long) read_register (SR_REGNUM),
1431 (long) read_register (PR_REGNUM),
1432 (long) read_register (MACH_REGNUM),
1433 (long) read_register (MACL_REGNUM));
1435 printf_filtered ("GBR=%08lx VBR=%08lx",
1436 (long) read_register (GBR_REGNUM),
1437 (long) read_register (VBR_REGNUM));
1439 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1442 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1443 (long) read_register (0), (long) read_register (1),
1444 (long) read_register (2), (long) read_register (3),
1445 (long) read_register (4), (long) read_register (5),
1446 (long) read_register (6), (long) read_register (7));
1447 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1448 (long) read_register (8), (long) read_register (9),
1449 (long) read_register (10), (long) read_register (11),
1450 (long) read_register (12), (long) read_register (13),
1451 (long) read_register (14), (long) read_register (15));
1454 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1455 (long) read_register (A0G_REGNUM) & 0xff,
1456 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1457 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1458 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1459 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1460 (long) read_register (A1G_REGNUM) & 0xff,
1461 (long) read_register (A1_REGNUM),
1462 (long) read_register (M1_REGNUM),
1463 (long) read_register (X1_REGNUM),
1464 (long) read_register (Y1_REGNUM),
1465 (long) read_register (RE_REGNUM));
1469 sh_show_regs_command (char *args, int from_tty)
1475 /* Return the GDB type object for the "standard" data type
1476 of data in register N. */
1477 static struct type *
1478 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1480 if ((reg_nr >= FP0_REGNUM
1481 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1482 return builtin_type_float;
1484 return builtin_type_int;
1487 static struct type *
1488 sh_sh4_build_float_register_type (int high)
1492 temp = create_range_type (NULL, builtin_type_int, 0, high);
1493 return create_array_type (NULL, builtin_type_float, temp);
1496 static struct type *
1497 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1499 if ((reg_nr >= FP0_REGNUM
1500 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1501 return builtin_type_float;
1502 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1503 return builtin_type_double;
1504 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1505 return sh_sh4_build_float_register_type (3);
1507 return builtin_type_int;
1510 static struct type *
1511 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1513 return builtin_type_int;
1516 /* On the sh4, the DRi pseudo registers are problematic if the target
1517 is little endian. When the user writes one of those registers, for
1518 instance with 'ser var $dr0=1', we want the double to be stored
1520 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1521 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1523 This corresponds to little endian byte order & big endian word
1524 order. However if we let gdb write the register w/o conversion, it
1525 will write fr0 and fr1 this way:
1526 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1527 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1528 because it will consider fr0 and fr1 as a single LE stretch of memory.
1530 To achieve what we want we must force gdb to store things in
1531 floatformat_ieee_double_littlebyte_bigword (which is defined in
1532 include/floatformat.h and libiberty/floatformat.c.
1534 In case the target is big endian, there is no problem, the
1535 raw bytes will look like:
1536 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1537 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1539 The other pseudo registers (the FVs) also don't pose a problem
1540 because they are stored as 4 individual FP elements. */
1543 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
1544 char *from, char *to)
1546 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1549 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1551 store_typed_floating (to, type, val);
1555 ("sh_register_convert_to_virtual called with non DR register number");
1559 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
1560 const void *from, void *to)
1562 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1564 DOUBLEST val = extract_typed_floating (from, type);
1565 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1569 error ("sh_register_convert_to_raw called with non DR register number");
1572 /* For vectors of 4 floating point registers. */
1574 fv_reg_base_num (int fv_regnum)
1578 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1582 /* For double precision floating point registers, i.e 2 fp regs.*/
1584 dr_reg_base_num (int dr_regnum)
1588 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1593 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1594 int reg_nr, void *buffer)
1596 int base_regnum, portion;
1597 char temp_buffer[MAX_REGISTER_SIZE];
1599 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1601 base_regnum = dr_reg_base_num (reg_nr);
1603 /* Build the value in the provided buffer. */
1604 /* Read the real regs for which this one is an alias. */
1605 for (portion = 0; portion < 2; portion++)
1606 regcache_raw_read (regcache, base_regnum + portion,
1608 + register_size (gdbarch,
1609 base_regnum) * portion));
1610 /* We must pay attention to the endiannes. */
1611 sh_sh4_register_convert_to_virtual (reg_nr,
1612 gdbarch_register_type (gdbarch,
1614 temp_buffer, buffer);
1616 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1618 base_regnum = fv_reg_base_num (reg_nr);
1620 /* Read the real regs for which this one is an alias. */
1621 for (portion = 0; portion < 4; portion++)
1622 regcache_raw_read (regcache, base_regnum + portion,
1624 + register_size (gdbarch,
1625 base_regnum) * portion));
1630 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1631 int reg_nr, const void *buffer)
1633 int base_regnum, portion;
1634 char temp_buffer[MAX_REGISTER_SIZE];
1636 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1638 base_regnum = dr_reg_base_num (reg_nr);
1640 /* We must pay attention to the endiannes. */
1641 sh_sh4_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1642 reg_nr, buffer, temp_buffer);
1644 /* Write the real regs for which this one is an alias. */
1645 for (portion = 0; portion < 2; portion++)
1646 regcache_raw_write (regcache, base_regnum + portion,
1648 + register_size (gdbarch,
1649 base_regnum) * portion));
1651 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1653 base_regnum = fv_reg_base_num (reg_nr);
1655 /* Write the real regs for which this one is an alias. */
1656 for (portion = 0; portion < 4; portion++)
1657 regcache_raw_write (regcache, base_regnum + portion,
1659 + register_size (gdbarch,
1660 base_regnum) * portion));
1664 /* Floating point vector of 4 float registers. */
1666 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1669 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1670 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1671 fv_regnum - FV0_REGNUM,
1672 (int) read_register (first_fp_reg_num),
1673 (int) read_register (first_fp_reg_num + 1),
1674 (int) read_register (first_fp_reg_num + 2),
1675 (int) read_register (first_fp_reg_num + 3));
1678 /* Double precision registers. */
1680 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1683 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1685 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1686 dr_regnum - DR0_REGNUM,
1687 (int) read_register (first_fp_reg_num),
1688 (int) read_register (first_fp_reg_num + 1));
1692 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1695 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1696 internal_error (__FILE__, __LINE__,
1697 "Invalid pseudo register number %d\n", regnum);
1698 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1699 do_dr_register_info (gdbarch, file, regnum);
1700 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1701 do_fv_register_info (gdbarch, file, regnum);
1705 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1706 { /* do values for FP (float) regs */
1708 double flt; /* double extracted from raw hex data */
1712 /* Allocate space for the float. */
1713 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1715 /* Get the data in raw format. */
1716 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1717 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1719 /* Get the register as a number */
1720 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1722 /* Print the name and some spaces. */
1723 fputs_filtered (REGISTER_NAME (regnum), file);
1724 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1726 /* Print the value. */
1728 fprintf_filtered (file, "<invalid float>");
1730 fprintf_filtered (file, "%-10.9g", flt);
1732 /* Print the fp register as hex. */
1733 fprintf_filtered (file, "\t(raw 0x");
1734 for (j = 0; j < register_size (gdbarch, regnum); j++)
1736 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1738 : register_size (gdbarch, regnum) - 1 - j);
1739 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1741 fprintf_filtered (file, ")");
1742 fprintf_filtered (file, "\n");
1746 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1748 char raw_buffer[MAX_REGISTER_SIZE];
1750 fputs_filtered (REGISTER_NAME (regnum), file);
1751 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1753 /* Get the data in raw format. */
1754 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1755 fprintf_filtered (file, "*value not available*\n");
1757 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1758 file, 'x', 1, 0, Val_pretty_default);
1759 fprintf_filtered (file, "\t");
1760 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1761 file, 0, 1, 0, Val_pretty_default);
1762 fprintf_filtered (file, "\n");
1766 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1768 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1769 internal_error (__FILE__, __LINE__,
1770 "Invalid register number %d\n", regnum);
1772 else if (regnum >= 0 && regnum < NUM_REGS)
1774 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1776 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1778 sh_do_register (gdbarch, file, regnum); /* All other regs */
1781 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1783 sh_print_pseudo_register (gdbarch, file, regnum);
1788 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1789 struct frame_info *frame, int regnum, int fpregs)
1791 if (regnum != -1) /* do one specified register */
1793 if (*(REGISTER_NAME (regnum)) == '\0')
1794 error ("Not a valid register for the current processor type");
1796 sh_print_register (gdbarch, file, regnum);
1799 /* do all (or most) registers */
1802 while (regnum < NUM_REGS)
1804 /* If the register name is empty, it is undefined for this
1805 processor, so don't display anything. */
1806 if (REGISTER_NAME (regnum) == NULL
1807 || *(REGISTER_NAME (regnum)) == '\0')
1813 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1818 /* true for "INFO ALL-REGISTERS" command */
1819 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1823 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
1827 sh_do_register (gdbarch, file, regnum); /* All other regs */
1833 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1835 sh_print_pseudo_register (gdbarch, file, regnum);
1841 #ifdef SVR4_SHARED_LIBS
1843 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1844 for native i386 linux targets using the struct offsets defined in
1845 link.h (but without actual reference to that file).
1847 This makes it possible to access i386-linux shared libraries from
1848 a gdb that was not built on an i386-linux host (for cross debugging).
1851 struct link_map_offsets *
1852 sh_linux_svr4_fetch_link_map_offsets (void)
1854 static struct link_map_offsets lmo;
1855 static struct link_map_offsets *lmp = 0;
1861 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1863 lmo.r_map_offset = 4;
1866 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1868 lmo.l_addr_offset = 0;
1869 lmo.l_addr_size = 4;
1871 lmo.l_name_offset = 4;
1872 lmo.l_name_size = 4;
1874 lmo.l_next_offset = 12;
1875 lmo.l_next_size = 4;
1877 lmo.l_prev_offset = 16;
1878 lmo.l_prev_size = 4;
1883 #endif /* SVR4_SHARED_LIBS */
1886 sh_dsp_register_sim_regno (int nr)
1888 if (legacy_register_sim_regno (nr) < 0)
1889 return legacy_register_sim_regno (nr);
1890 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1891 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1892 if (nr == MOD_REGNUM)
1893 return SIM_SH_MOD_REGNUM;
1894 if (nr == RS_REGNUM)
1895 return SIM_SH_RS_REGNUM;
1896 if (nr == RE_REGNUM)
1897 return SIM_SH_RE_REGNUM;
1898 if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1899 return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1903 static struct sh_frame_cache *
1904 sh_alloc_frame_cache (void)
1906 struct sh_frame_cache *cache;
1909 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1913 cache->saved_sp = 0;
1914 cache->sp_offset = 0;
1917 /* Frameless until proven otherwise. */
1920 /* Saved registers. We initialize these to -1 since zero is a valid
1921 offset (that's where fp is supposed to be stored). */
1922 for (i = 0; i < SH_NUM_REGS; i++)
1924 cache->saved_regs[i] = -1;
1930 static struct sh_frame_cache *
1931 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1933 struct sh_frame_cache *cache;
1934 CORE_ADDR current_pc;
1940 cache = sh_alloc_frame_cache ();
1941 *this_cache = cache;
1943 /* In principle, for normal frames, fp holds the frame pointer,
1944 which holds the base address for the current stack frame.
1945 However, for functions that don't need it, the frame pointer is
1946 optional. For these "frameless" functions the frame pointer is
1947 actually the frame pointer of the calling frame. */
1948 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1949 if (cache->base == 0)
1952 cache->pc = frame_func_unwind (next_frame);
1953 current_pc = frame_pc_unwind (next_frame);
1955 sh_analyze_prologue (cache->pc, current_pc, cache);
1957 if (!cache->uses_fp)
1959 /* We didn't find a valid frame, which means that CACHE->base
1960 currently holds the frame pointer for our calling frame. If
1961 we're at the start of a function, or somewhere half-way its
1962 prologue, the function's frame probably hasn't been fully
1963 setup yet. Try to reconstruct the base address for the stack
1964 frame by looking at the stack pointer. For truly "frameless"
1965 functions this might work too. */
1966 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1969 /* Now that we have the base address for the stack frame we can
1970 calculate the value of sp in the calling frame. */
1971 cache->saved_sp = cache->base + cache->sp_offset;
1973 /* Adjust all the saved registers such that they contain addresses
1974 instead of offsets. */
1975 for (i = 0; i < SH_NUM_REGS; i++)
1976 if (cache->saved_regs[i] != -1)
1977 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1983 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1984 int regnum, int *optimizedp,
1985 enum lval_type *lvalp, CORE_ADDR *addrp,
1986 int *realnump, void *valuep)
1988 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1990 gdb_assert (regnum >= 0);
1992 if (regnum == SP_REGNUM && cache->saved_sp)
2000 /* Store the value. */
2001 store_unsigned_integer (valuep, 4, cache->saved_sp);
2006 /* The PC of the previous frame is stored in the PR register of
2007 the current frame. Frob regnum so that we pull the value from
2008 the correct place. */
2009 if (regnum == PC_REGNUM)
2012 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2015 *lvalp = lval_memory;
2016 *addrp = cache->saved_regs[regnum];
2020 /* Read the value in from memory. */
2021 read_memory (*addrp, valuep,
2022 register_size (current_gdbarch, regnum));
2027 frame_register_unwind (next_frame, regnum,
2028 optimizedp, lvalp, addrp, realnump, valuep);
2032 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2033 struct frame_id *this_id)
2035 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2037 /* This marks the outermost frame. */
2038 if (cache->base == 0)
2041 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2044 static const struct frame_unwind sh_frame_unwind = {
2047 sh_frame_prev_register
2050 static const struct frame_unwind *
2051 sh_frame_sniffer (struct frame_info *next_frame)
2053 return &sh_frame_unwind;
2057 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2059 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2063 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2065 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2068 static struct frame_id
2069 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2071 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2072 frame_pc_unwind (next_frame));
2076 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2078 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2083 static const struct frame_base sh_frame_base = {
2085 sh_frame_base_address,
2086 sh_frame_base_address,
2087 sh_frame_base_address
2090 /* The epilogue is defined here as the area at the end of a function,
2091 either on the `ret' instruction itself or after an instruction which
2092 destroys the function's stack frame. */
2094 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2096 CORE_ADDR func_addr = 0, func_end = 0;
2098 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2101 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2102 for a nop and some fixed data (e.g. big offsets) which are
2103 unfortunately also treated as part of the function (which
2104 means, they are below func_end. */
2105 CORE_ADDR addr = func_end - 28;
2106 if (addr < func_addr + 4)
2107 addr = func_addr + 4;
2111 /* First search forward until hitting an rts. */
2112 while (addr < func_end
2113 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2115 if (addr >= func_end)
2118 /* At this point we should find a mov.l @r15+,r14 instruction,
2119 either before or after the rts. If not, then the function has
2120 probably no "normal" epilogue and we bail out here. */
2121 inst = read_memory_unsigned_integer (addr - 2, 2);
2122 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2124 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2127 /* Step over possible lds.l @r15+,pr. */
2128 inst = read_memory_unsigned_integer (addr - 2, 2);
2132 inst = read_memory_unsigned_integer (addr - 2, 2);
2135 /* Step over possible mov r14,r15. */
2136 if (IS_MOV_FP_SP (inst))
2139 inst = read_memory_unsigned_integer (addr - 2, 2);
2142 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2144 while (addr > func_addr + 4
2145 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2148 inst = read_memory_unsigned_integer (addr - 2, 2);
2157 static gdbarch_init_ftype sh_gdbarch_init;
2159 static struct gdbarch *
2160 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2162 struct gdbarch *gdbarch;
2164 sh_show_regs = sh_generic_show_regs;
2165 switch (info.bfd_arch_info->mach)
2168 sh_show_regs = sh2e_show_regs;
2170 case bfd_mach_sh_dsp:
2171 sh_show_regs = sh_dsp_show_regs;
2175 sh_show_regs = sh3_show_regs;
2179 sh_show_regs = sh3e_show_regs;
2182 case bfd_mach_sh3_dsp:
2183 case bfd_mach_sh4al_dsp:
2184 sh_show_regs = sh3_dsp_show_regs;
2189 sh_show_regs = sh4_show_regs;
2192 case bfd_mach_sh4_nofpu:
2193 case bfd_mach_sh4a_nofpu:
2194 sh_show_regs = sh4_nofpu_show_regs;
2198 sh_show_regs = sh64_show_regs;
2199 /* SH5 is handled entirely in sh64-tdep.c */
2200 return sh64_gdbarch_init (info, arches);
2203 /* If there is already a candidate, use it. */
2204 arches = gdbarch_list_lookup_by_info (arches, &info);
2206 return arches->gdbarch;
2208 /* None found, create a new architecture from the information
2210 gdbarch = gdbarch_alloc (&info, NULL);
2212 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2213 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2214 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2215 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2216 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2217 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2218 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2219 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2221 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2222 set_gdbarch_sp_regnum (gdbarch, 15);
2223 set_gdbarch_pc_regnum (gdbarch, 16);
2224 set_gdbarch_fp0_regnum (gdbarch, -1);
2225 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2227 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2229 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2231 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2232 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2234 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2235 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2237 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2239 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2240 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2241 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2243 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2244 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2246 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2248 set_gdbarch_frameless_function_invocation (gdbarch,
2249 frameless_look_for_prologue);
2250 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2252 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2253 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2254 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2255 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2256 frame_base_set_default (gdbarch, &sh_frame_base);
2258 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2260 switch (info.bfd_arch_info->mach)
2263 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2267 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2271 /* doubles on sh2e and sh3e are actually 4 byte. */
2272 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2274 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2275 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2276 set_gdbarch_fp0_regnum (gdbarch, 25);
2277 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2278 set_gdbarch_extract_return_value (gdbarch,
2279 sh3e_sh4_extract_return_value);
2280 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2283 case bfd_mach_sh_dsp:
2284 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2285 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2289 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2293 /* doubles on sh2e and sh3e are actually 4 byte. */
2294 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2296 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2297 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2298 set_gdbarch_fp0_regnum (gdbarch, 25);
2299 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2300 set_gdbarch_extract_return_value (gdbarch,
2301 sh3e_sh4_extract_return_value);
2302 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2305 case bfd_mach_sh3_dsp:
2306 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2307 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2312 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2313 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2314 set_gdbarch_fp0_regnum (gdbarch, 25);
2315 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2316 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2317 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2318 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2319 set_gdbarch_extract_return_value (gdbarch,
2320 sh3e_sh4_extract_return_value);
2321 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2324 case bfd_mach_sh4_nofpu:
2325 case bfd_mach_sh4a_nofpu:
2326 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2329 case bfd_mach_sh4al_dsp:
2330 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2331 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2335 set_gdbarch_register_name (gdbarch, sh_generic_register_name);
2339 /* Hook in ABI-specific overrides, if they have been registered. */
2340 gdbarch_init_osabi (info, gdbarch);
2342 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2343 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2348 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2351 _initialize_sh_tdep (void)
2353 struct cmd_list_element *c;
2355 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2357 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");