1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
36 #include "inferior.h" /* for BEFORE_TEXT_END etc. */
37 #include "gdb_string.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
46 #include "solib-svr4.h"
50 /* registers numbers shared with the simulator */
51 #include "gdb/sim-sh.h"
53 void (*sh_show_regs) (void);
54 CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
55 void (*do_pseudo_register) (int);
57 #define SH_DEFAULT_NUM_REGS 59
59 /* Define other aspects of the stack frame.
60 we keep a copy of the worked out return pc lying around, since it
61 is a useful bit of info */
63 struct frame_extra_info
71 sh_generic_register_name (int reg_nr)
73 static char *register_names[] =
75 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
76 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
77 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
79 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
80 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
82 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
83 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
87 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
89 return register_names[reg_nr];
93 sh_sh_register_name (int reg_nr)
95 static char *register_names[] =
97 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
98 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
99 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
101 "", "", "", "", "", "", "", "",
102 "", "", "", "", "", "", "", "",
104 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
109 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
111 return register_names[reg_nr];
115 sh_sh3_register_name (int reg_nr)
117 static char *register_names[] =
119 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
120 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
121 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
123 "", "", "", "", "", "", "", "",
124 "", "", "", "", "", "", "", "",
126 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
127 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
131 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
133 return register_names[reg_nr];
137 sh_sh3e_register_name (int reg_nr)
139 static char *register_names[] =
141 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
142 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
143 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
145 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
146 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
148 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
149 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
153 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
155 return register_names[reg_nr];
159 sh_sh_dsp_register_name (int reg_nr)
161 static char *register_names[] =
163 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
164 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
165 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
167 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
168 "y0", "y1", "", "", "", "", "", "mod",
170 "rs", "re", "", "", "", "", "", "",
171 "", "", "", "", "", "", "", "",
175 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
177 return register_names[reg_nr];
181 sh_sh3_dsp_register_name (int reg_nr)
183 static char *register_names[] =
185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
192 "rs", "re", "", "", "", "", "", "",
193 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
194 "", "", "", "", "", "", "", "",
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return register_names[reg_nr];
204 sh_sh4_register_name (int reg_nr)
206 static char *register_names[] =
208 /* general registers 0-15 */
209 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
210 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
212 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
215 /* floating point registers 25 - 40 */
216 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
217 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
221 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
223 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
224 /* double precision (pseudo) 59 - 66 */
225 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
226 /* vectors (pseudo) 67 - 70 */
227 "fv0", "fv4", "fv8", "fv12",
228 /* FIXME: missing XF 71 - 86 */
229 /* FIXME: missing XD 87 - 94 */
233 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
235 return register_names[reg_nr];
239 sh_sh64_register_name (int reg_nr)
241 static char *register_names[] =
243 /* SH MEDIA MODE (ISA 32) */
244 /* general registers (64-bit) 0-63 */
245 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
246 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
247 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
248 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
249 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
250 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
251 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
252 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
257 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
260 /* target registers (64-bit) 68-75*/
261 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
263 /* floating point state control register (32-bit) 76 */
266 /* single precision floating point registers (32-bit) 77-140*/
267 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
268 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
269 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
270 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
271 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
272 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
273 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
274 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
276 /* double precision registers (pseudo) 141-172 */
277 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
278 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
279 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
280 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
282 /* floating point pairs (pseudo) 173-204*/
283 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
284 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
285 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
286 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
288 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
289 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
290 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
292 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
293 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
294 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
296 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
298 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
299 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
300 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
301 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
302 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
307 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
309 return register_names[reg_nr];
312 #define NUM_PSEUDO_REGS_SH_MEDIA 80
313 #define NUM_PSEUDO_REGS_SH_COMPACT 51
315 static const unsigned char *
316 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
318 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
319 static unsigned char breakpoint[] = {0xc3, 0xc3};
321 *lenptr = sizeof (breakpoint);
325 /* Macros and functions for setting and testing a bit in a minimal
326 symbol that marks it as 32-bit function. The MSB of the minimal
327 symbol's "info" field is used for this purpose. This field is
328 already being used to store the symbol size, so the assumption is
329 that the symbol size cannot exceed 2^31.
331 ELF_MAKE_MSYMBOL_SPECIAL
332 tests whether an ELF symbol is "special", i.e. refers
333 to a 32-bit function, and sets a "special" bit in a
334 minimal symbol to mark it as a 32-bit function
335 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
336 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
337 the "info" field with the "special" bit masked out */
339 #define MSYMBOL_IS_SPECIAL(msym) \
340 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
343 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
348 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
350 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
351 SYMBOL_VALUE_ADDRESS (msym) |= 1;
355 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
356 are some macros to test, set, or clear bit 0 of addresses. */
357 #define IS_ISA32_ADDR(addr) ((addr) & 1)
358 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
359 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
362 pc_is_isa32 (bfd_vma memaddr)
364 struct minimal_symbol *sym;
366 /* If bit 0 of the address is set, assume this is a
367 ISA32 (shmedia) address. */
368 if (IS_ISA32_ADDR (memaddr))
371 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
372 the high bit of the info field. Use this to decide if the function is
374 sym = lookup_minimal_symbol_by_pc (memaddr);
376 return MSYMBOL_IS_SPECIAL (sym);
381 static const unsigned char *
382 sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
384 /* The BRK instruction for shmedia is
385 01101111 11110101 11111111 11110000
386 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
387 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
389 /* The BRK instruction for shcompact is
391 which translates in big endian mode to 0x0, 0x3b
392 and in little endian mode to 0x3b, 0x0*/
394 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
396 if (pc_is_isa32 (*pcptr))
398 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
399 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
400 *lenptr = sizeof (big_breakpoint_media);
401 return big_breakpoint_media;
405 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
406 *lenptr = sizeof (big_breakpoint_compact);
407 return big_breakpoint_compact;
412 if (pc_is_isa32 (*pcptr))
414 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
415 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
416 *lenptr = sizeof (little_breakpoint_media);
417 return little_breakpoint_media;
421 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
422 *lenptr = sizeof (little_breakpoint_compact);
423 return little_breakpoint_compact;
428 /* Prologue looks like
429 [mov.l <regs>,@-r15]...
434 Actually it can be more complicated than this. For instance, with
452 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
453 with l=1 and n = 18 0110101111110001010010100aaa0000 */
454 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
456 /* STS.L PR,@-r0 0100000000100010
457 r0-4-->r0, PR-->(r0) */
458 #define IS_STS_R0(x) ((x) == 0x4022)
460 /* STS PR, Rm 0000mmmm00101010
462 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
464 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
466 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
468 /* MOV.L R14,@(disp,r15) 000111111110dddd
469 R14-->(dispx4+r15) */
470 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
472 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
473 R18-->(dispx8+R14) */
474 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
476 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
477 R18-->(dispx8+R15) */
478 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
480 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
481 R18-->(dispx4+R15) */
482 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
484 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
485 R14-->(dispx8+R15) */
486 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
488 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
489 R14-->(dispx4+R15) */
490 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
492 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
494 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
496 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
498 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
500 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
502 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
504 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
506 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
508 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
510 /* MOV #imm, R0 1110 0000 ssss ssss
512 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
514 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
515 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
517 /* ADD r15,r0 0011 0000 1111 1100
519 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
521 /* MOV.L R14 @-R0 0010 0000 1110 0110
522 R14-->(R0-4), R0-4-->R0 */
523 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
525 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
526 where Rm is one of r2-r9 which are the argument registers. */
527 /* FIXME: Recognize the float and double register moves too! */
528 #define IS_MEDIA_IND_ARG_MOV(x) \
529 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
531 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
532 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
533 where Rm is one of r2-r9 which are the argument registers. */
534 #define IS_MEDIA_ARG_MOV(x) \
535 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
536 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
538 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
539 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
540 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
541 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
542 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
543 #define IS_MEDIA_MOV_TO_R14(x) \
544 ((((x) & 0xfffffc0f) == 0xa0e00000) \
545 || (((x) & 0xfffffc0f) == 0xa4e00000) \
546 || (((x) & 0xfffffc0f) == 0xa8e00000) \
547 || (((x) & 0xfffffc0f) == 0xb4e00000) \
548 || (((x) & 0xfffffc0f) == 0xbce00000))
550 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
552 #define IS_COMPACT_IND_ARG_MOV(x) \
553 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
555 /* compact direct arg move!
556 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
557 #define IS_COMPACT_ARG_MOV(x) \
558 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
560 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
561 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
562 #define IS_COMPACT_MOV_TO_R14(x) \
563 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
565 #define IS_JSR_R0(x) ((x) == 0x400b)
566 #define IS_NOP(x) ((x) == 0x0009)
569 /* STS.L PR,@-r15 0100111100100010
570 r15-4-->r15, PR-->(r15) */
571 #define IS_STS(x) ((x) == 0x4f22)
573 /* MOV.L Rm,@-r15 00101111mmmm0110
574 r15-4-->r15, Rm-->(R15) */
575 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
577 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
579 /* MOV r15,r14 0110111011110011
581 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
583 /* ADD #imm,r15 01111111iiiiiiii
585 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
587 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
588 #define IS_SHLL_R3(x) ((x) == 0x4300)
590 /* ADD r3,r15 0011111100111100
592 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
594 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
595 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
596 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
597 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
599 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
600 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
601 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
602 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
603 #define IS_ARG_MOV(x) \
604 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
605 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
606 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
608 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
609 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
610 #define IS_MOV_TO_R14(x) \
611 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
613 #define FPSCR_SZ (1 << 20)
615 /* Skip any prologue before the guts of a function */
617 /* Skip the prologue using the debug information. If this fails we'll
618 fall back on the 'guess' method below. */
620 after_prologue (CORE_ADDR pc)
622 struct symtab_and_line sal;
623 CORE_ADDR func_addr, func_end;
625 /* If we can not find the symbol in the partial symbol table, then
626 there is no hope we can determine the function's start address
628 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
631 /* Get the line associated with FUNC_ADDR. */
632 sal = find_pc_line (func_addr, 0);
634 /* There are only two cases to consider. First, the end of the source line
635 is within the function bounds. In that case we return the end of the
636 source line. Second is the end of the source line extends beyond the
637 bounds of the current function. We need to use the slow code to
638 examine instructions in that case. */
639 if (sal.end < func_end)
645 /* Here we look at each instruction in the function, and try to guess
646 where the prologue ends. Unfortunately this is not always
649 sh_skip_prologue_hard_way (CORE_ADDR start_pc)
657 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
659 int w = read_memory_integer (here, 2);
661 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
662 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
663 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
667 else if (IS_MOV_SP_FP (w))
673 /* Don't bail out yet, if we are before the copy of sp. */
682 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
686 int insn_size = (media_mode ? 4 : 2);
688 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
692 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
694 if (IS_MEDIA_IND_ARG_MOV (w))
696 /* This must be followed by a store to r14, so the argument
697 is where the debug info says it is. This can happen after
698 the SP has been saved, unfortunately. */
700 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
703 if (IS_MEDIA_MOV_TO_R14 (next_insn))
706 else if (IS_MEDIA_ARG_MOV (w))
708 /* These instructions store directly the argument in r14. */
716 w = read_memory_integer (here, insn_size);
719 if (IS_COMPACT_IND_ARG_MOV (w))
721 /* This must be followed by a store to r14, so the argument
722 is where the debug info says it is. This can happen after
723 the SP has been saved, unfortunately. */
725 int next_insn = 0xffff & read_memory_integer (here, insn_size);
727 if (IS_COMPACT_MOV_TO_R14 (next_insn))
730 else if (IS_COMPACT_ARG_MOV (w))
732 /* These instructions store directly the argument in r14. */
735 else if (IS_MOVL_R0 (w))
737 /* There is a function that gcc calls to get the arguments
738 passed correctly to the function. Only after this
739 function call the arguments will be found at the place
740 where they are supposed to be. This happens in case the
741 argument has to be stored into a 64-bit register (for
742 instance doubles, long longs). SHcompact doesn't have
743 access to the full 64-bits, so we store the register in
744 stack slot and store the address of the stack slot in
745 the register, then do a call through a wrapper that
746 loads the memory value into the register. A SHcompact
747 callee calls an argument decoder
748 (GCC_shcompact_incoming_args) that stores the 64-bit
749 value in a stack slot and stores the address of the
750 stack slot in the register. GCC thinks the argument is
751 just passed by transparent reference, but this is only
752 true after the argument decoder is called. Such a call
753 needs to be considered part of the prologue. */
755 /* This must be followed by a JSR @r0 instruction and by
756 a NOP instruction. After these, the prologue is over! */
758 int next_insn = 0xffff & read_memory_integer (here, insn_size);
760 if (IS_JSR_R0 (next_insn))
762 next_insn = 0xffff & read_memory_integer (here, insn_size);
765 if (IS_NOP (next_insn))
778 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
788 if (pc_is_isa32 (start_pc) == 0)
794 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
799 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
801 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
802 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
803 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
807 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
815 /* Don't bail out yet, we may have arguments stored in
816 registers here, according to the debug info, so that
817 gdb can print the frames correctly. */
818 start_pc = look_for_args_moves (here - insn_size, media_mode);
824 int w = 0xffff & read_memory_integer (here, insn_size);
827 if (IS_STS_R0 (w) || IS_STS_PR (w)
828 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
829 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
833 else if (IS_MOV_SP_FP (w))
841 /* Don't bail out yet, we may have arguments stored in
842 registers here, according to the debug info, so that
843 gdb can print the frames correctly. */
844 start_pc = look_for_args_moves (here - insn_size, media_mode);
854 sh_skip_prologue (CORE_ADDR pc)
856 CORE_ADDR post_prologue_pc;
858 /* See if we can determine the end of the prologue via the symbol table.
859 If so, then return either PC, or the PC after the prologue, whichever
861 post_prologue_pc = after_prologue (pc);
863 /* If after_prologue returned a useful address, then use it. Else
864 fall back on the instruction skipping code. */
865 if (post_prologue_pc != 0)
866 return max (pc, post_prologue_pc);
868 return (skip_prologue_hard_way (pc));
871 /* Immediately after a function call, return the saved pc.
872 Can't always go through the frames for this because on some machines
873 the new frame is not set up until the new function executes
876 The return address is the value saved in the PR register + 4 */
878 sh_saved_pc_after_call (struct frame_info *frame)
880 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
883 /* Should call_function allocate stack space for a struct return? */
885 sh_use_struct_convention (int gcc_p, struct type *type)
888 return (TYPE_LENGTH (type) > 1);
890 int len = TYPE_LENGTH (type);
891 int nelem = TYPE_NFIELDS (type);
892 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
893 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
898 sh64_use_struct_convention (int gcc_p, struct type *type)
900 return (TYPE_LENGTH (type) > 8);
903 /* Store the address of the place in which to copy the structure the
904 subroutine will return. This is called from call_function.
906 We store structs through a pointer passed in R2 */
908 sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
910 write_register (STRUCT_RETURN_REGNUM, (addr));
913 /* Disassemble an instruction. */
915 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
917 info->endian = TARGET_BYTE_ORDER;
918 return print_insn_sh (memaddr, info);
921 /* Given a GDB frame, determine the address of the calling function's frame.
922 This will be used to create a new GDB frame struct, and then
923 INIT_EXTRA_FRAME_INFO and INIT_FRAME_PC will be called for the new frame.
925 For us, the frame address is its stack pointer value, so we look up
926 the function prologue to determine the caller's sp value, and return it. */
928 sh_frame_chain (struct frame_info *frame)
930 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
931 return frame->frame; /* dummy frame same as caller's frame */
932 if (frame->pc && !inside_entry_file (frame->pc))
933 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, 4);
938 /* Given a register number RN as it appears in an assembly
939 instruction, find the corresponding register number in the GDB
942 translate_insn_rn (int rn, int media_mode)
944 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
946 /* FIXME: this assumes that the number rn is for a not pseudo
952 /* These registers don't have a corresponding compact one. */
953 /* FIXME: This is probably not enough. */
955 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
958 if (rn >= 0 && rn <= tdep->R0_C_REGNUM)
959 return tdep->R0_C_REGNUM + rn;
966 sh64_frame_chain (struct frame_info *frame)
968 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
969 return frame->frame; /* dummy frame same as caller's frame */
970 if (frame->pc && !inside_entry_file (frame->pc))
972 int media_mode = pc_is_isa32 (frame->pc);
974 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
977 size = REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM, media_mode));
978 return read_memory_integer (FRAME_FP (frame) + frame->extra_info->f_offset, size);
984 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
985 we might want to do here is to check REGNUM against the clobber mask, and
986 somehow flag it as invalid if it isn't saved on the stack somewhere. This
987 would provide a graceful failure mode when trying to get the value of
988 caller-saves registers for an inner frame. */
990 sh_find_callers_reg (struct frame_info *fi, int regnum)
992 for (; fi; fi = fi->next)
993 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
994 /* When the caller requests PR from the dummy frame, we return PC because
995 that's where the previous routine appears to have done a call from. */
996 return deprecated_read_register_dummy (fi->pc, fi->frame, regnum);
999 FRAME_INIT_SAVED_REGS (fi);
1002 if (fi->saved_regs[regnum] != 0)
1003 return read_memory_integer (fi->saved_regs[regnum],
1004 REGISTER_RAW_SIZE (regnum));
1006 return read_register (regnum);
1010 sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
1014 for (; fi; fi = fi->next)
1015 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1016 /* When the caller requests PR from the dummy frame, we return PC because
1017 that's where the previous routine appears to have done a call from. */
1018 return deprecated_read_register_dummy (fi->pc, fi->frame, pr_regnum);
1021 FRAME_INIT_SAVED_REGS (fi);
1025 media_mode = pc_is_isa32 (fi->pc);
1027 if (fi->saved_regs[pr_regnum] != 0)
1029 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
1030 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1032 : REGISTER_RAW_SIZE (gdb_reg_num));
1033 return read_memory_integer (fi->saved_regs[pr_regnum], size);
1036 return read_register (pr_regnum);
1039 /* Put here the code to store, into a struct frame_saved_regs, the
1040 addresses of the saved registers of frame described by FRAME_INFO.
1041 This includes special registers such as pc and fp saved in special
1042 ways in the stack frame. sp is even more special: the address we
1043 return for it IS the sp for the next frame. */
1045 sh_nofp_frame_init_saved_regs (struct frame_info *fi)
1047 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
1055 char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame);
1057 if (fi->saved_regs == NULL)
1058 frame_saved_regs_zalloc (fi);
1060 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
1064 /* DANGER! This is ONLY going to work if the char buffer format of
1065 the saved registers is byte-for-byte identical to the
1066 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1067 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1071 fi->extra_info->leaf_function = 1;
1072 fi->extra_info->f_offset = 0;
1074 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1079 /* Loop around examining the prologue insns until we find something
1080 that does not appear to be part of the prologue. But give up
1081 after 20 of them, since we're getting silly then. */
1083 pc = get_pc_function_start (fi->pc);
1090 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1092 insn = read_memory_integer (pc, 2);
1093 /* See where the registers will be saved to */
1096 rn = GET_PUSHED_REG (insn);
1100 else if (IS_STS (insn))
1102 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
1103 /* If we're storing the pr then this isn't a leaf */
1104 fi->extra_info->leaf_function = 0;
1107 else if (IS_MOV_R3 (insn))
1109 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1111 else if (IS_SHLL_R3 (insn))
1115 else if (IS_ADD_R3SP (insn))
1119 else if (IS_ADD_SP (insn))
1121 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1123 else if (IS_MOV_SP_FP (insn))
1125 #if 0 /* This used to just stop when it found an instruction that
1126 was not considered part of the prologue. Now, we just
1127 keep going looking for likely instructions. */
1133 /* Now we know how deep things are, we can work out their addresses */
1135 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1139 if (rn == FP_REGNUM)
1142 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
1146 fi->saved_regs[rn] = 0;
1152 fi->saved_regs[SP_REGNUM] = read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
1156 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
1159 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
1160 /* Work out the return pc - either from the saved pr or the pr
1164 /* For vectors of 4 floating point registers. */
1166 fv_reg_base_num (int fv_regnum)
1170 fp_regnum = FP0_REGNUM +
1171 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1175 /* For double precision floating point registers, i.e 2 fp regs.*/
1177 dr_reg_base_num (int dr_regnum)
1181 fp_regnum = FP0_REGNUM +
1182 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1186 /* For pairs of floating point registers */
1188 fpp_reg_base_num (int fpp_regnum)
1192 fp_regnum = FP0_REGNUM +
1193 (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2;
1198 is_media_pseudo (int rn)
1200 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1202 return (rn >= tdep->DR0_REGNUM
1203 && rn <= tdep->FV_LAST_REGNUM);
1207 sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
1209 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
1213 sh64_media_reg_base_num (int reg_nr)
1215 int base_regnum = -1;
1216 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1218 if (reg_nr >= tdep->DR0_REGNUM
1219 && reg_nr <= tdep->DR_LAST_REGNUM)
1220 base_regnum = dr_reg_base_num (reg_nr);
1222 else if (reg_nr >= tdep->FPP0_REGNUM
1223 && reg_nr <= tdep->FPP_LAST_REGNUM)
1224 base_regnum = fpp_reg_base_num (reg_nr);
1226 else if (reg_nr >= tdep->FV0_REGNUM
1227 && reg_nr <= tdep->FV_LAST_REGNUM)
1228 base_regnum = fv_reg_base_num (reg_nr);
1235 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1236 GDB_REGNUM BASE_REGNUM
1296 sh64_compact_reg_base_num (int reg_nr)
1298 int base_regnum = -1;
1299 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1301 /* general register N maps to general register N */
1302 if (reg_nr >= tdep->R0_C_REGNUM
1303 && reg_nr <= tdep->R_LAST_C_REGNUM)
1304 base_regnum = reg_nr - tdep->R0_C_REGNUM;
1306 /* floating point register N maps to floating point register N */
1307 else if (reg_nr >= tdep->FP0_C_REGNUM
1308 && reg_nr <= tdep->FP_LAST_C_REGNUM)
1309 base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM;
1311 /* double prec register N maps to base regnum for double prec register N */
1312 else if (reg_nr >= tdep->DR0_C_REGNUM
1313 && reg_nr <= tdep->DR_LAST_C_REGNUM)
1314 base_regnum = dr_reg_base_num (tdep->DR0_REGNUM
1315 + reg_nr - tdep->DR0_C_REGNUM);
1317 /* vector N maps to base regnum for vector register N */
1318 else if (reg_nr >= tdep->FV0_C_REGNUM
1319 && reg_nr <= tdep->FV_LAST_C_REGNUM)
1320 base_regnum = fv_reg_base_num (tdep->FV0_REGNUM
1321 + reg_nr - tdep->FV0_C_REGNUM);
1323 else if (reg_nr == tdep->PC_C_REGNUM)
1324 base_regnum = PC_REGNUM;
1326 else if (reg_nr == tdep->GBR_C_REGNUM)
1329 else if (reg_nr == tdep->MACH_C_REGNUM
1330 || reg_nr == tdep->MACL_C_REGNUM)
1333 else if (reg_nr == tdep->PR_C_REGNUM)
1336 else if (reg_nr == tdep->T_C_REGNUM)
1339 else if (reg_nr == tdep->FPSCR_C_REGNUM)
1340 base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */
1342 else if (reg_nr == tdep->FPUL_C_REGNUM)
1343 base_regnum = FP0_REGNUM + 32;
1348 /* Given a register number RN (according to the gdb scheme) , return
1349 its corresponding architectural register. In media mode, only a
1350 subset of the registers is pseudo registers. For compact mode, all
1351 the registers are pseudo. */
1353 translate_rn_to_arch_reg_num (int rn, int media_mode)
1358 if (!is_media_pseudo (rn))
1361 return sh64_media_reg_base_num (rn);
1364 /* All compact registers are pseudo. */
1365 return sh64_compact_reg_base_num (rn);
1369 sign_extend (int value, int bits)
1371 value = value & ((1 << bits) - 1);
1372 return (value & (1 << (bits - 1))
1373 ? value | (~((1 << bits) - 1))
1378 sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
1380 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1392 int gdb_register_number;
1393 int register_number;
1394 char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame);
1395 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1397 if (fi->saved_regs == NULL)
1398 frame_saved_regs_zalloc (fi);
1400 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
1404 /* DANGER! This is ONLY going to work if the char buffer format of
1405 the saved registers is byte-for-byte identical to the
1406 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1407 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1411 fi->extra_info->leaf_function = 1;
1412 fi->extra_info->f_offset = 0;
1414 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1419 /* Loop around examining the prologue insns until we find something
1420 that does not appear to be part of the prologue. But give up
1421 after 20 of them, since we're getting silly then. */
1423 pc = get_pc_function_start (fi->pc);
1430 if (pc_is_isa32 (pc))
1441 /* The frame pointer register is general register 14 in shmedia and
1442 shcompact modes. In sh compact it is a pseudo register. Same goes
1443 for the stack pointer register, which is register 15. */
1444 fp_regnum = translate_insn_rn (FP_REGNUM, media_mode);
1445 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1447 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1449 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1452 if (media_mode == 0)
1454 if (IS_STS_PR (insn))
1456 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1457 if (IS_MOV_TO_R15 (next_insn))
1459 int reg_nr = tdep->PR_C_REGNUM;
1461 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1462 fi->extra_info->leaf_function = 0;
1466 else if (IS_MOV_R14 (insn))
1468 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1471 else if (IS_MOV_R0 (insn))
1473 /* Put in R0 the offset from SP at which to store some
1474 registers. We are interested in this value, because it
1475 will tell us where the given registers are stored within
1477 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1479 else if (IS_ADD_SP_R0 (insn))
1481 /* This instruction still prepares r0, but we don't care.
1482 We already have the offset in r0_val. */
1484 else if (IS_STS_R0 (insn))
1486 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1487 int reg_nr = tdep->PR_C_REGNUM;
1488 where[reg_nr] = depth - (r0_val - 4);
1490 fi->extra_info->leaf_function = 0;
1492 else if (IS_MOV_R14_R0 (insn))
1494 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1495 where[fp_regnum] = depth - (r0_val - 4);
1499 else if (IS_ADD_SP (insn))
1501 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1503 else if (IS_MOV_SP_FP (insn))
1508 if (IS_ADDIL_SP_MEDIA (insn)
1509 || IS_ADDI_SP_MEDIA (insn))
1511 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1514 else if (IS_STQ_R18_R15 (insn))
1516 where[tdep->PR_REGNUM] =
1517 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1518 fi->extra_info->leaf_function = 0;
1521 else if (IS_STL_R18_R15 (insn))
1523 where[tdep->PR_REGNUM] =
1524 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1525 fi->extra_info->leaf_function = 0;
1528 else if (IS_STQ_R14_R15 (insn))
1530 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1533 else if (IS_STL_R14_R15 (insn))
1535 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1538 else if (IS_MOV_SP_FP_MEDIA (insn))
1543 /* Now we know how deep things are, we can work out their addresses. */
1544 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1546 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1550 if (rn == fp_regnum)
1553 /* Watch out! saved_regs is only for the real registers, and
1554 doesn't include space for the pseudo registers. */
1555 fi->saved_regs[register_number]= fi->frame - where[rn] + depth;
1559 fi->saved_regs[register_number] = 0;
1564 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1565 shcompact 15 is the arch register corresponding to the pseudo
1566 register r15 which still is the SP register. */
1567 /* The place on the stack where fp is stored contains the sp of
1569 /* Again, saved_registers contains only space for the real registers,
1570 so we store in FP_REGNUM position. */
1572 if (tdep->sh_abi == SH_ABI_32)
1575 size = REGISTER_RAW_SIZE (fp_regnum);
1576 fi->saved_regs[sp_regnum] = read_memory_integer (fi->saved_regs[fp_regnum], size);
1579 fi->saved_regs[sp_regnum] = fi->frame;
1581 fi->extra_info->f_offset = depth - where[fp_regnum];
1585 sh_fp_frame_init_saved_regs (struct frame_info *fi)
1587 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1595 char *dummy_regs = deprecated_generic_find_dummy_frame (fi->pc, fi->frame);
1596 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1598 if (fi->saved_regs == NULL)
1599 frame_saved_regs_zalloc (fi);
1601 memset (fi->saved_regs, 0, SIZEOF_FRAME_SAVED_REGS);
1605 /* DANGER! This is ONLY going to work if the char buffer format of
1606 the saved registers is byte-for-byte identical to the
1607 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1608 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1612 fi->extra_info->leaf_function = 1;
1613 fi->extra_info->f_offset = 0;
1615 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1620 /* Loop around examining the prologue insns until we find something
1621 that does not appear to be part of the prologue. But give up
1622 after 20 of them, since we're getting silly then. */
1624 pc = get_pc_function_start (fi->pc);
1631 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1633 insn = read_memory_integer (pc, 2);
1634 /* See where the registers will be saved to */
1637 rn = GET_PUSHED_REG (insn);
1641 else if (IS_STS (insn))
1643 where[tdep->PR_REGNUM] = depth;
1644 /* If we're storing the pr then this isn't a leaf */
1645 fi->extra_info->leaf_function = 0;
1648 else if (IS_MOV_R3 (insn))
1650 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1652 else if (IS_SHLL_R3 (insn))
1656 else if (IS_ADD_R3SP (insn))
1660 else if (IS_ADD_SP (insn))
1662 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1664 else if (IS_FMOV (insn))
1666 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
1675 else if (IS_MOV_SP_FP (insn))
1677 #if 0 /* This used to just stop when it found an instruction that
1678 was not considered part of the prologue. Now, we just
1679 keep going looking for likely instructions. */
1685 /* Now we know how deep things are, we can work out their addresses */
1687 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1691 if (rn == FP_REGNUM)
1694 fi->saved_regs[rn] = fi->frame - where[rn] + depth - 4;
1698 fi->saved_regs[rn] = 0;
1704 fi->saved_regs[SP_REGNUM] =
1705 read_memory_integer (fi->saved_regs[FP_REGNUM], 4);
1709 fi->saved_regs[SP_REGNUM] = fi->frame - 4;
1712 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
1713 /* Work out the return pc - either from the saved pr or the pr
1717 /* Initialize the extra info saved in a FRAME */
1719 sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1722 fi->extra_info = (struct frame_extra_info *)
1723 frame_obstack_alloc (sizeof (struct frame_extra_info));
1726 fi->pc = FRAME_SAVED_PC (fi->next);
1728 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1730 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1731 by assuming it's always FP. */
1732 fi->frame = deprecated_read_register_dummy (fi->pc, fi->frame,
1734 fi->extra_info->return_pc = deprecated_read_register_dummy (fi->pc,
1737 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1738 fi->extra_info->leaf_function = 0;
1743 FRAME_INIT_SAVED_REGS (fi);
1744 fi->extra_info->return_pc =
1745 sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1750 sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1752 int media_mode = pc_is_isa32 (fi->pc);
1754 fi->extra_info = (struct frame_extra_info *)
1755 frame_obstack_alloc (sizeof (struct frame_extra_info));
1758 fi->pc = FRAME_SAVED_PC (fi->next);
1760 if (PC_IN_CALL_DUMMY (fi->pc, fi->frame, fi->frame))
1762 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1763 by assuming it's always FP. */
1764 fi->frame = deprecated_read_register_dummy (fi->pc, fi->frame,
1766 fi->extra_info->return_pc =
1767 deprecated_read_register_dummy (fi->pc, fi->frame, PC_REGNUM);
1768 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1769 fi->extra_info->leaf_function = 0;
1774 FRAME_INIT_SAVED_REGS (fi);
1775 fi->extra_info->return_pc =
1776 sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1781 sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1782 struct frame_info *frame, int regnum,
1783 enum lval_type *lval)
1786 int live_regnum = regnum;
1787 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1789 if (!target_has_registers)
1790 error ("No registers.");
1792 /* Normal systems don't optimize out things with register numbers. */
1793 if (optimized != NULL)
1796 if (addrp) /* default assumption: not found in memory */
1800 memset (raw_buffer, 0, sizeof (raw_buffer));
1802 /* We must do this here, before the following while loop changes
1803 frame, and makes it NULL. If this is a media register number,
1804 but we are in compact mode, it will become the corresponding
1805 compact pseudo register. If there is no corresponding compact
1806 pseudo-register what do we do?*/
1807 media_mode = pc_is_isa32 (frame->pc);
1808 live_regnum = translate_insn_rn (regnum, media_mode);
1810 /* Note: since the current frame's registers could only have been
1811 saved by frames INTERIOR TO the current frame, we skip examining
1812 the current frame itself: otherwise, we would be getting the
1813 previous frame's registers which were saved by the current frame. */
1815 while (frame && ((frame = frame->next) != NULL))
1817 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1819 if (lval) /* found it in a CALL_DUMMY frame */
1823 (deprecated_generic_find_dummy_frame (frame->pc, frame->frame)
1824 + REGISTER_BYTE (regnum)),
1825 REGISTER_RAW_SIZE (regnum));
1829 FRAME_INIT_SAVED_REGS (frame);
1830 if (frame->saved_regs != NULL
1831 && frame->saved_regs[regnum] != 0)
1833 if (lval) /* found it saved on the stack */
1834 *lval = lval_memory;
1835 if (regnum == SP_REGNUM)
1837 if (raw_buffer) /* SP register treated specially */
1838 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
1839 frame->saved_regs[regnum]);
1842 { /* any other register */
1845 *addrp = frame->saved_regs[regnum];
1849 if (tdep->sh_abi == SH_ABI_32
1850 && (live_regnum == FP_REGNUM
1851 || live_regnum == tdep->PR_REGNUM))
1854 size = REGISTER_RAW_SIZE (live_regnum);
1855 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1856 read_memory (frame->saved_regs[regnum], raw_buffer, size);
1858 read_memory (frame->saved_regs[regnum],
1860 + REGISTER_RAW_SIZE (live_regnum)
1869 /* If we get thru the loop to this point, it means the register was
1870 not saved in any frame. Return the actual live-register value. */
1872 if (lval) /* found it in a live register */
1873 *lval = lval_register;
1875 *addrp = REGISTER_BYTE (live_regnum);
1877 deprecated_read_register_gen (live_regnum, raw_buffer);
1880 /* Extract from an array REGBUF containing the (raw) register state
1881 the address in which a function should return its structure value,
1882 as a CORE_ADDR (or an expression that can be used as one). */
1884 sh_extract_struct_value_address (char *regbuf)
1886 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
1890 sh64_extract_struct_value_address (char *regbuf)
1892 return (extract_address ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
1893 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
1897 sh_frame_saved_pc (struct frame_info *frame)
1899 return ((frame)->extra_info->return_pc);
1902 /* Discard from the stack the innermost frame,
1903 restoring all saved registers. */
1907 register struct frame_info *frame = get_current_frame ();
1908 register CORE_ADDR fp;
1909 register int regnum;
1911 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1912 generic_pop_dummy_frame ();
1915 fp = FRAME_FP (frame);
1916 FRAME_INIT_SAVED_REGS (frame);
1918 /* Copy regs from where they were saved in the frame */
1919 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1920 if (frame->saved_regs[regnum])
1921 write_register (regnum,
1922 read_memory_integer (frame->saved_regs[regnum], 4));
1924 write_register (PC_REGNUM, frame->extra_info->return_pc);
1925 write_register (SP_REGNUM, fp + 4);
1927 flush_cached_frames ();
1930 /* Used in the 'return' command. */
1932 sh64_pop_frame (void)
1934 register struct frame_info *frame = get_current_frame ();
1935 register CORE_ADDR fp;
1936 register int regnum;
1937 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1939 int media_mode = pc_is_isa32 (frame->pc);
1941 if (PC_IN_CALL_DUMMY (frame->pc, frame->frame, frame->frame))
1942 generic_pop_dummy_frame ();
1945 fp = FRAME_FP (frame);
1946 FRAME_INIT_SAVED_REGS (frame);
1948 /* Copy regs from where they were saved in the frame */
1949 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1950 if (frame->saved_regs[regnum])
1953 if (tdep->sh_abi == SH_ABI_32
1954 && (regnum == FP_REGNUM
1955 || regnum == tdep->PR_REGNUM))
1958 size = REGISTER_RAW_SIZE (translate_insn_rn (regnum,
1960 write_register (regnum,
1961 read_memory_integer (frame->saved_regs[regnum],
1965 write_register (PC_REGNUM, frame->extra_info->return_pc);
1966 write_register (SP_REGNUM, fp + 8);
1968 flush_cached_frames ();
1971 /* Function: push_arguments
1972 Setup the function arguments for calling a function in the inferior.
1974 On the Hitachi SH architecture, there are four registers (R4 to R7)
1975 which are dedicated for passing function arguments. Up to the first
1976 four arguments (depending on size) may go into these registers.
1977 The rest go on the stack.
1979 Arguments that are smaller than 4 bytes will still take up a whole
1980 register or a whole 32-bit word on the stack, and will be
1981 right-justified in the register or the stack word. This includes
1982 chars, shorts, and small aggregate types.
1984 Arguments that are larger than 4 bytes may be split between two or
1985 more registers. If there are not enough registers free, an argument
1986 may be passed partly in a register (or registers), and partly on the
1987 stack. This includes doubles, long longs, and larger aggregates.
1988 As far as I know, there is no upper limit to the size of aggregates
1989 that will be passed in this way; in other words, the convention of
1990 passing a pointer to a large aggregate instead of a copy is not used.
1992 An exceptional case exists for struct arguments (and possibly other
1993 aggregates such as arrays) if the size is larger than 4 bytes but
1994 not a multiple of 4 bytes. In this case the argument is never split
1995 between the registers and the stack, but instead is copied in its
1996 entirety onto the stack, AND also copied into as many registers as
1997 there is room for. In other words, space in registers permitting,
1998 two copies of the same argument are passed in. As far as I can tell,
1999 only the one on the stack is used, although that may be a function
2000 of the level of compiler optimization. I suspect this is a compiler
2001 bug. Arguments of these odd sizes are left-justified within the
2002 word (as opposed to arguments smaller than 4 bytes, which are
2005 If the function is to return an aggregate type such as a struct, it
2006 is either returned in the normal return value register R0 (if its
2007 size is no greater than one byte), or else the caller must allocate
2008 space into which the callee will copy the return value (if the size
2009 is greater than one byte). In this case, a pointer to the return
2010 value location is passed into the callee in register R2, which does
2011 not displace any of the other arguments passed in via registers R4
2015 sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2016 int struct_return, CORE_ADDR struct_addr)
2018 int stack_offset, stack_alloc;
2026 int odd_sized_struct;
2027 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2029 /* first force sp to a 4-byte alignment */
2032 /* The "struct return pointer" pseudo-argument has its own dedicated
2035 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2037 /* Now make sure there's space on the stack */
2038 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2039 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
2040 sp -= stack_alloc; /* make room on stack for args */
2042 /* Now load as many as possible of the first arguments into
2043 registers, and push the rest onto the stack. There are 16 bytes
2044 in four registers available. Loop thru args from first to last. */
2046 argreg = tdep->ARG0_REGNUM;
2047 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2049 type = VALUE_TYPE (args[argnum]);
2050 len = TYPE_LENGTH (type);
2051 memset (valbuf, 0, sizeof (valbuf));
2054 /* value gets right-justified in the register or stack word */
2055 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2056 memcpy (valbuf + (4 - len),
2057 (char *) VALUE_CONTENTS (args[argnum]), len);
2059 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2063 val = (char *) VALUE_CONTENTS (args[argnum]);
2065 if (len > 4 && (len & 3) != 0)
2066 odd_sized_struct = 1; /* such structs go entirely on stack */
2068 odd_sized_struct = 0;
2071 if (argreg > tdep->ARGLAST_REGNUM
2072 || odd_sized_struct)
2074 /* must go on the stack */
2075 write_memory (sp + stack_offset, val, 4);
2078 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2079 That's because some *&^%$ things get passed on the stack
2080 AND in the registers! */
2081 if (argreg <= tdep->ARGLAST_REGNUM)
2083 /* there's room in a register */
2084 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
2085 write_register (argreg++, regval);
2087 /* Store the value 4 bytes at a time. This means that things
2088 larger than 4 bytes may go partly in registers and partly
2090 len -= REGISTER_RAW_SIZE (argreg);
2091 val += REGISTER_RAW_SIZE (argreg);
2097 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2098 non-scalar (struct, union) elements (even if the elements are
2100 FR0-FR11 for single precision floating point (float)
2101 DR0-DR10 for double precision floating point (double)
2103 If a float is argument number 3 (for instance) and arguments number
2104 1,2, and 4 are integer, the mapping will be:
2105 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2107 If a float is argument number 10 (for instance) and arguments number
2108 1 through 10 are integer, the mapping will be:
2109 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2110 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2111 I.e. there is hole in the stack.
2113 Different rules apply for variable arguments functions, and for functions
2114 for which the prototype is not known. */
2117 sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2118 int struct_return, CORE_ADDR struct_addr)
2120 int stack_offset, stack_alloc;
2124 int float_arg_index = 0;
2125 int double_arg_index = 0;
2135 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2137 memset (fp_args, 0, sizeof (fp_args));
2139 /* first force sp to a 8-byte alignment */
2142 /* The "struct return pointer" pseudo-argument has its own dedicated
2146 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2148 /* Now make sure there's space on the stack */
2149 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2150 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
2151 sp -= stack_alloc; /* make room on stack for args */
2153 /* Now load as many as possible of the first arguments into
2154 registers, and push the rest onto the stack. There are 64 bytes
2155 in eight registers available. Loop thru args from first to last. */
2157 int_argreg = tdep->ARG0_REGNUM;
2158 float_argreg = FP0_REGNUM;
2159 double_argreg = tdep->DR0_REGNUM;
2161 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2163 type = VALUE_TYPE (args[argnum]);
2164 len = TYPE_LENGTH (type);
2165 memset (valbuf, 0, sizeof (valbuf));
2167 if (TYPE_CODE (type) != TYPE_CODE_FLT)
2169 argreg_size = REGISTER_RAW_SIZE (int_argreg);
2171 if (len < argreg_size)
2173 /* value gets right-justified in the register or stack word */
2174 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2175 memcpy (valbuf + argreg_size - len,
2176 (char *) VALUE_CONTENTS (args[argnum]), len);
2178 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2183 val = (char *) VALUE_CONTENTS (args[argnum]);
2187 if (int_argreg > tdep->ARGLAST_REGNUM)
2189 /* must go on the stack */
2190 write_memory (sp + stack_offset, val, argreg_size);
2191 stack_offset += 8;/*argreg_size;*/
2193 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2194 That's because some *&^%$ things get passed on the stack
2195 AND in the registers! */
2196 if (int_argreg <= tdep->ARGLAST_REGNUM)
2198 /* there's room in a register */
2199 regval = extract_address (val, argreg_size);
2200 write_register (int_argreg, regval);
2202 /* Store the value 8 bytes at a time. This means that
2203 things larger than 8 bytes may go partly in registers
2204 and partly on the stack. FIXME: argreg is incremented
2205 before we use its size. */
2213 val = (char *) VALUE_CONTENTS (args[argnum]);
2216 /* Where is it going to be stored? */
2217 while (fp_args[float_arg_index])
2220 /* Now float_argreg points to the register where it
2221 should be stored. Are we still within the allowed
2223 if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM)
2225 /* Goes in FR0...FR11 */
2226 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
2228 fp_args[float_arg_index] = 1;
2229 /* Skip the corresponding general argument register. */
2234 /* Store it as the integers, 8 bytes at the time, if
2235 necessary spilling on the stack. */
2240 /* Where is it going to be stored? */
2241 while (fp_args[double_arg_index])
2242 double_arg_index += 2;
2243 /* Now double_argreg points to the register
2244 where it should be stored.
2245 Are we still within the allowed register set? */
2246 if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM)
2248 /* Goes in DR0...DR10 */
2249 /* The numbering of the DRi registers is consecutive,
2250 i.e. includes odd numbers. */
2251 int double_register_offset = double_arg_index / 2;
2252 int regnum = tdep->DR0_REGNUM +
2253 double_register_offset;
2255 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2257 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
2258 REGISTER_CONVERT_TO_VIRTUAL (regnum,
2259 type, val, valbuf_tmp);
2263 /* Note: must use write_register_gen here instead
2264 of regcache_raw_write, because
2265 regcache_raw_write works only for real
2266 registers, not pseudo. write_register_gen will
2267 call the gdbarch function to do register
2268 writes, and that will properly know how to deal
2270 deprecated_write_register_gen (regnum, val);
2271 fp_args[double_arg_index] = 1;
2272 fp_args[double_arg_index + 1] = 1;
2273 /* Skip the corresponding general argument register. */
2278 /* Store it as the integers, 8 bytes at the time, if
2279 necessary spilling on the stack. */
2286 /* Function: push_return_address (pc)
2287 Set up the return address for the inferior function call.
2288 Needed for targets where we don't actually execute a JSR/BSR instruction */
2291 sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
2293 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM,
2294 CALL_DUMMY_ADDRESS ());
2298 /* Function: fix_call_dummy
2299 Poke the callee function's address into the destination part of
2300 the CALL_DUMMY. The address is actually stored in a data word
2301 following the actualy CALL_DUMMY instructions, which will load
2302 it into a register using PC-relative addressing. This function
2303 expects the CALL_DUMMY to look like this:
2314 sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
2315 struct value **args, struct type *type, int gcc_p)
2317 *(unsigned long *) (dummy + 8) = fun;
2322 sh_coerce_float_to_double (struct type *formal, struct type *actual)
2327 /* Find a function's return value in the appropriate registers (in
2328 regbuf), and copy it into valbuf. Extract from an array REGBUF
2329 containing the (raw) register state a function return value of type
2330 TYPE, and copy that, in virtual format, into VALBUF. */
2332 sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2334 int len = TYPE_LENGTH (type);
2335 int return_register = R0_REGNUM;
2340 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2341 offset = REGISTER_BYTE (return_register) + 4 - len;
2343 offset = REGISTER_BYTE (return_register);
2344 memcpy (valbuf, regbuf + offset, len);
2348 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2349 offset = REGISTER_BYTE (return_register) + 8 - len;
2351 offset = REGISTER_BYTE (return_register);
2352 memcpy (valbuf, regbuf + offset, len);
2355 error ("bad size for return value");
2359 sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2361 int return_register;
2363 int len = TYPE_LENGTH (type);
2365 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2366 return_register = FP0_REGNUM;
2368 return_register = R0_REGNUM;
2370 if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT)
2373 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2374 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2375 (char *) regbuf + REGISTER_BYTE (return_register),
2378 floatformat_to_doublest (&floatformat_ieee_double_big,
2379 (char *) regbuf + REGISTER_BYTE (return_register),
2381 store_floating (valbuf, len, val);
2385 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2386 offset = REGISTER_BYTE (return_register) + 4 - len;
2388 offset = REGISTER_BYTE (return_register);
2389 memcpy (valbuf, regbuf + offset, len);
2393 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2394 offset = REGISTER_BYTE (return_register) + 8 - len;
2396 offset = REGISTER_BYTE (return_register);
2397 memcpy (valbuf, regbuf + offset, len);
2400 error ("bad size for return value");
2404 sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2407 int return_register;
2408 int len = TYPE_LENGTH (type);
2409 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2411 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2415 /* Return value stored in FP0_REGNUM */
2416 return_register = FP0_REGNUM;
2417 offset = REGISTER_BYTE (return_register);
2418 memcpy (valbuf, (char *) regbuf + offset, len);
2422 /* return value stored in DR0_REGNUM */
2425 return_register = tdep->DR0_REGNUM;
2426 offset = REGISTER_BYTE (return_register);
2428 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2429 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2430 (char *) regbuf + offset, &val);
2432 floatformat_to_doublest (&floatformat_ieee_double_big,
2433 (char *) regbuf + offset, &val);
2434 store_floating (valbuf, len, val);
2441 /* Result is in register 2. If smaller than 8 bytes, it is padded
2442 at the most significant end. */
2443 return_register = tdep->RETURN_REGNUM;
2444 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2445 offset = REGISTER_BYTE (return_register) +
2446 REGISTER_RAW_SIZE (return_register) - len;
2448 offset = REGISTER_BYTE (return_register);
2449 memcpy (valbuf, (char *) regbuf + offset, len);
2452 error ("bad size for return value");
2456 /* Write into appropriate registers a function return value
2457 of type TYPE, given in virtual format.
2458 If the architecture is sh4 or sh3e, store a function's return value
2459 in the R0 general register or in the FP0 floating point register,
2460 depending on the type of the return value. In all the other cases
2461 the result is stored in r0, left-justified. */
2463 sh_default_store_return_value (struct type *type, char *valbuf)
2465 char buf[32]; /* more than enough... */
2467 if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM))
2469 /* Add leading zeros to the value. */
2470 memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM));
2471 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2472 memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type),
2473 valbuf, TYPE_LENGTH (type));
2475 memcpy (buf, valbuf, TYPE_LENGTH (type));
2476 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf,
2477 REGISTER_RAW_SIZE (R0_REGNUM));
2480 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf,
2481 TYPE_LENGTH (type));
2485 sh3e_sh4_store_return_value (struct type *type, char *valbuf)
2487 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2488 deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
2489 valbuf, TYPE_LENGTH (type));
2491 sh_default_store_return_value (type, valbuf);
2495 sh64_store_return_value (struct type *type, char *valbuf)
2497 char buf[64]; /* more than enough... */
2498 int len = TYPE_LENGTH (type);
2500 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2504 /* Return value stored in FP0_REGNUM */
2505 deprecated_write_register_gen (FP0_REGNUM, valbuf);
2509 /* return value stored in DR0_REGNUM */
2510 /* FIXME: Implement */
2515 int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM;
2518 if (len <= REGISTER_RAW_SIZE (return_register))
2520 /* Pad with zeros. */
2521 memset (buf, 0, REGISTER_RAW_SIZE (return_register));
2522 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2523 offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2525 offset = REGISTER_RAW_SIZE (return_register) - len;
2527 memcpy (buf + offset, valbuf, len);
2528 deprecated_write_register_gen (return_register, buf);
2531 deprecated_write_register_gen (return_register, valbuf);
2535 /* Print the registers in a form similar to the E7000 */
2538 sh_generic_show_regs (void)
2540 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2542 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2543 paddr (read_register (PC_REGNUM)),
2544 (long) read_register (tdep->SR_REGNUM),
2545 (long) read_register (tdep->PR_REGNUM),
2546 (long) read_register (MACH_REGNUM),
2547 (long) read_register (MACL_REGNUM));
2549 printf_filtered ("GBR=%08lx VBR=%08lx",
2550 (long) read_register (GBR_REGNUM),
2551 (long) read_register (VBR_REGNUM));
2553 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2554 (long) read_register (0),
2555 (long) read_register (1),
2556 (long) read_register (2),
2557 (long) read_register (3),
2558 (long) read_register (4),
2559 (long) read_register (5),
2560 (long) read_register (6),
2561 (long) read_register (7));
2562 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2563 (long) read_register (8),
2564 (long) read_register (9),
2565 (long) read_register (10),
2566 (long) read_register (11),
2567 (long) read_register (12),
2568 (long) read_register (13),
2569 (long) read_register (14),
2570 (long) read_register (15));
2574 sh3_show_regs (void)
2576 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2578 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2579 paddr (read_register (PC_REGNUM)),
2580 (long) read_register (tdep->SR_REGNUM),
2581 (long) read_register (tdep->PR_REGNUM),
2582 (long) read_register (MACH_REGNUM),
2583 (long) read_register (MACL_REGNUM));
2585 printf_filtered ("GBR=%08lx VBR=%08lx",
2586 (long) read_register (GBR_REGNUM),
2587 (long) read_register (VBR_REGNUM));
2588 printf_filtered (" SSR=%08lx SPC=%08lx",
2589 (long) read_register (tdep->SSR_REGNUM),
2590 (long) read_register (tdep->SPC_REGNUM));
2592 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2593 (long) read_register (0),
2594 (long) read_register (1),
2595 (long) read_register (2),
2596 (long) read_register (3),
2597 (long) read_register (4),
2598 (long) read_register (5),
2599 (long) read_register (6),
2600 (long) read_register (7));
2601 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2602 (long) read_register (8),
2603 (long) read_register (9),
2604 (long) read_register (10),
2605 (long) read_register (11),
2606 (long) read_register (12),
2607 (long) read_register (13),
2608 (long) read_register (14),
2609 (long) read_register (15));
2614 sh3e_show_regs (void)
2616 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2618 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2619 paddr (read_register (PC_REGNUM)),
2620 (long) read_register (tdep->SR_REGNUM),
2621 (long) read_register (tdep->PR_REGNUM),
2622 (long) read_register (MACH_REGNUM),
2623 (long) read_register (MACL_REGNUM));
2625 printf_filtered ("GBR=%08lx VBR=%08lx",
2626 (long) read_register (GBR_REGNUM),
2627 (long) read_register (VBR_REGNUM));
2628 printf_filtered (" SSR=%08lx SPC=%08lx",
2629 (long) read_register (tdep->SSR_REGNUM),
2630 (long) read_register (tdep->SPC_REGNUM));
2631 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2632 (long) read_register (tdep->FPUL_REGNUM),
2633 (long) read_register (tdep->FPSCR_REGNUM));
2635 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2636 (long) read_register (0),
2637 (long) read_register (1),
2638 (long) read_register (2),
2639 (long) read_register (3),
2640 (long) read_register (4),
2641 (long) read_register (5),
2642 (long) read_register (6),
2643 (long) read_register (7));
2644 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2645 (long) read_register (8),
2646 (long) read_register (9),
2647 (long) read_register (10),
2648 (long) read_register (11),
2649 (long) read_register (12),
2650 (long) read_register (13),
2651 (long) read_register (14),
2652 (long) read_register (15));
2654 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2655 (long) read_register (FP0_REGNUM + 0),
2656 (long) read_register (FP0_REGNUM + 1),
2657 (long) read_register (FP0_REGNUM + 2),
2658 (long) read_register (FP0_REGNUM + 3),
2659 (long) read_register (FP0_REGNUM + 4),
2660 (long) read_register (FP0_REGNUM + 5),
2661 (long) read_register (FP0_REGNUM + 6),
2662 (long) read_register (FP0_REGNUM + 7));
2663 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2664 (long) read_register (FP0_REGNUM + 8),
2665 (long) read_register (FP0_REGNUM + 9),
2666 (long) read_register (FP0_REGNUM + 10),
2667 (long) read_register (FP0_REGNUM + 11),
2668 (long) read_register (FP0_REGNUM + 12),
2669 (long) read_register (FP0_REGNUM + 13),
2670 (long) read_register (FP0_REGNUM + 14),
2671 (long) read_register (FP0_REGNUM + 15));
2675 sh3_dsp_show_regs (void)
2677 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2679 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2680 paddr (read_register (PC_REGNUM)),
2681 (long) read_register (tdep->SR_REGNUM),
2682 (long) read_register (tdep->PR_REGNUM),
2683 (long) read_register (MACH_REGNUM),
2684 (long) read_register (MACL_REGNUM));
2686 printf_filtered ("GBR=%08lx VBR=%08lx",
2687 (long) read_register (GBR_REGNUM),
2688 (long) read_register (VBR_REGNUM));
2690 printf_filtered (" SSR=%08lx SPC=%08lx",
2691 (long) read_register (tdep->SSR_REGNUM),
2692 (long) read_register (tdep->SPC_REGNUM));
2694 printf_filtered (" DSR=%08lx",
2695 (long) read_register (tdep->DSR_REGNUM));
2697 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2698 (long) read_register (0),
2699 (long) read_register (1),
2700 (long) read_register (2),
2701 (long) read_register (3),
2702 (long) read_register (4),
2703 (long) read_register (5),
2704 (long) read_register (6),
2705 (long) read_register (7));
2706 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2707 (long) read_register (8),
2708 (long) read_register (9),
2709 (long) read_register (10),
2710 (long) read_register (11),
2711 (long) read_register (12),
2712 (long) read_register (13),
2713 (long) read_register (14),
2714 (long) read_register (15));
2716 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2717 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2718 (long) read_register (tdep->A0_REGNUM),
2719 (long) read_register (tdep->M0_REGNUM),
2720 (long) read_register (tdep->X0_REGNUM),
2721 (long) read_register (tdep->Y0_REGNUM),
2722 (long) read_register (tdep->RS_REGNUM),
2723 (long) read_register (tdep->MOD_REGNUM));
2724 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2725 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2726 (long) read_register (tdep->A1_REGNUM),
2727 (long) read_register (tdep->M1_REGNUM),
2728 (long) read_register (tdep->X1_REGNUM),
2729 (long) read_register (tdep->Y1_REGNUM),
2730 (long) read_register (tdep->RE_REGNUM));
2734 sh4_show_regs (void)
2736 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2738 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
2739 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2740 paddr (read_register (PC_REGNUM)),
2741 (long) read_register (tdep->SR_REGNUM),
2742 (long) read_register (tdep->PR_REGNUM),
2743 (long) read_register (MACH_REGNUM),
2744 (long) read_register (MACL_REGNUM));
2746 printf_filtered ("GBR=%08lx VBR=%08lx",
2747 (long) read_register (GBR_REGNUM),
2748 (long) read_register (VBR_REGNUM));
2749 printf_filtered (" SSR=%08lx SPC=%08lx",
2750 (long) read_register (tdep->SSR_REGNUM),
2751 (long) read_register (tdep->SPC_REGNUM));
2752 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2753 (long) read_register (tdep->FPUL_REGNUM),
2754 (long) read_register (tdep->FPSCR_REGNUM));
2756 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2757 (long) read_register (0),
2758 (long) read_register (1),
2759 (long) read_register (2),
2760 (long) read_register (3),
2761 (long) read_register (4),
2762 (long) read_register (5),
2763 (long) read_register (6),
2764 (long) read_register (7));
2765 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2766 (long) read_register (8),
2767 (long) read_register (9),
2768 (long) read_register (10),
2769 (long) read_register (11),
2770 (long) read_register (12),
2771 (long) read_register (13),
2772 (long) read_register (14),
2773 (long) read_register (15));
2775 printf_filtered ((pr
2776 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2777 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2778 (long) read_register (FP0_REGNUM + 0),
2779 (long) read_register (FP0_REGNUM + 1),
2780 (long) read_register (FP0_REGNUM + 2),
2781 (long) read_register (FP0_REGNUM + 3),
2782 (long) read_register (FP0_REGNUM + 4),
2783 (long) read_register (FP0_REGNUM + 5),
2784 (long) read_register (FP0_REGNUM + 6),
2785 (long) read_register (FP0_REGNUM + 7));
2786 printf_filtered ((pr
2787 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2788 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2789 (long) read_register (FP0_REGNUM + 8),
2790 (long) read_register (FP0_REGNUM + 9),
2791 (long) read_register (FP0_REGNUM + 10),
2792 (long) read_register (FP0_REGNUM + 11),
2793 (long) read_register (FP0_REGNUM + 12),
2794 (long) read_register (FP0_REGNUM + 13),
2795 (long) read_register (FP0_REGNUM + 14),
2796 (long) read_register (FP0_REGNUM + 15));
2800 sh_dsp_show_regs (void)
2802 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2804 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2805 paddr (read_register (PC_REGNUM)),
2806 (long) read_register (tdep->SR_REGNUM),
2807 (long) read_register (tdep->PR_REGNUM),
2808 (long) read_register (MACH_REGNUM),
2809 (long) read_register (MACL_REGNUM));
2811 printf_filtered ("GBR=%08lx VBR=%08lx",
2812 (long) read_register (GBR_REGNUM),
2813 (long) read_register (VBR_REGNUM));
2815 printf_filtered (" DSR=%08lx",
2816 (long) read_register (tdep->DSR_REGNUM));
2818 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2819 (long) read_register (0),
2820 (long) read_register (1),
2821 (long) read_register (2),
2822 (long) read_register (3),
2823 (long) read_register (4),
2824 (long) read_register (5),
2825 (long) read_register (6),
2826 (long) read_register (7));
2827 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2828 (long) read_register (8),
2829 (long) read_register (9),
2830 (long) read_register (10),
2831 (long) read_register (11),
2832 (long) read_register (12),
2833 (long) read_register (13),
2834 (long) read_register (14),
2835 (long) read_register (15));
2837 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2838 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2839 (long) read_register (tdep->A0_REGNUM),
2840 (long) read_register (tdep->M0_REGNUM),
2841 (long) read_register (tdep->X0_REGNUM),
2842 (long) read_register (tdep->Y0_REGNUM),
2843 (long) read_register (tdep->RS_REGNUM),
2844 (long) read_register (tdep->MOD_REGNUM));
2845 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2846 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2847 (long) read_register (tdep->A1_REGNUM),
2848 (long) read_register (tdep->M1_REGNUM),
2849 (long) read_register (tdep->X1_REGNUM),
2850 (long) read_register (tdep->Y1_REGNUM),
2851 (long) read_register (tdep->RE_REGNUM));
2855 sh64_show_media_regs (void)
2858 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2860 printf_filtered ("PC=%s SR=%016llx \n",
2861 paddr (read_register (PC_REGNUM)),
2862 (long long) read_register (tdep->SR_REGNUM));
2864 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2865 (long long) read_register (tdep->SSR_REGNUM),
2866 (long long) read_register (tdep->SPC_REGNUM));
2867 printf_filtered ("FPSCR=%016lx\n ",
2868 (long) read_register (tdep->FPSCR_REGNUM));
2870 for (i = 0; i < 64; i = i + 4)
2871 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2873 (long long) read_register (i + 0),
2874 (long long) read_register (i + 1),
2875 (long long) read_register (i + 2),
2876 (long long) read_register (i + 3));
2878 printf_filtered ("\n");
2880 for (i = 0; i < 64; i = i + 8)
2881 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2883 (long) read_register (FP0_REGNUM + i + 0),
2884 (long) read_register (FP0_REGNUM + i + 1),
2885 (long) read_register (FP0_REGNUM + i + 2),
2886 (long) read_register (FP0_REGNUM + i + 3),
2887 (long) read_register (FP0_REGNUM + i + 4),
2888 (long) read_register (FP0_REGNUM + i + 5),
2889 (long) read_register (FP0_REGNUM + i + 6),
2890 (long) read_register (FP0_REGNUM + i + 7));
2894 sh64_show_compact_regs (void)
2897 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2899 printf_filtered ("PC=%s \n",
2900 paddr (read_register (tdep->PC_C_REGNUM)));
2902 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2903 (long) read_register (tdep->GBR_C_REGNUM),
2904 (long) read_register (tdep->MACH_C_REGNUM),
2905 (long) read_register (tdep->MACL_C_REGNUM),
2906 (long) read_register (tdep->PR_C_REGNUM),
2907 (long) read_register (tdep->T_C_REGNUM));
2908 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2909 (long) read_register (tdep->FPSCR_REGNUM),
2910 (long) read_register (tdep->FPUL_REGNUM));
2912 for (i = 0; i < 16; i = i + 4)
2913 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2915 (long) read_register (i + 0),
2916 (long) read_register (i + 1),
2917 (long) read_register (i + 2),
2918 (long) read_register (i + 3));
2920 printf_filtered ("\n");
2922 for (i = 0; i < 16; i = i + 8)
2923 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2925 (long) read_register (FP0_REGNUM + i + 0),
2926 (long) read_register (FP0_REGNUM + i + 1),
2927 (long) read_register (FP0_REGNUM + i + 2),
2928 (long) read_register (FP0_REGNUM + i + 3),
2929 (long) read_register (FP0_REGNUM + i + 4),
2930 (long) read_register (FP0_REGNUM + i + 5),
2931 (long) read_register (FP0_REGNUM + i + 6),
2932 (long) read_register (FP0_REGNUM + i + 7));
2935 /*FIXME!!! This only shows the registers for shmedia, excluding the
2936 pseudo registers. */
2938 sh64_show_regs (void)
2940 if (pc_is_isa32 (selected_frame->pc))
2941 sh64_show_media_regs ();
2943 sh64_show_compact_regs ();
2946 void sh_show_regs_command (char *args, int from_tty)
2952 /* Index within `registers' of the first byte of the space for
2955 sh_default_register_byte (int reg_nr)
2957 return (reg_nr * 4);
2961 sh_sh4_register_byte (int reg_nr)
2963 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2965 if (reg_nr >= tdep->DR0_REGNUM
2966 && reg_nr <= tdep->DR_LAST_REGNUM)
2967 return (dr_reg_base_num (reg_nr) * 4);
2968 else if (reg_nr >= tdep->FV0_REGNUM
2969 && reg_nr <= tdep->FV_LAST_REGNUM)
2970 return (fv_reg_base_num (reg_nr) * 4);
2972 return (reg_nr * 4);
2977 SH MEDIA MODE (ISA 32)
2978 general registers (64-bit) 0-63
2979 0 r0, r1, r2, r3, r4, r5, r6, r7,
2980 64 r8, r9, r10, r11, r12, r13, r14, r15,
2981 128 r16, r17, r18, r19, r20, r21, r22, r23,
2982 192 r24, r25, r26, r27, r28, r29, r30, r31,
2983 256 r32, r33, r34, r35, r36, r37, r38, r39,
2984 320 r40, r41, r42, r43, r44, r45, r46, r47,
2985 384 r48, r49, r50, r51, r52, r53, r54, r55,
2986 448 r56, r57, r58, r59, r60, r61, r62, r63,
2991 status reg., saved status reg., saved pc reg. (64-bit) 65-67
2994 target registers (64-bit) 68-75
2995 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
2997 floating point state control register (32-bit) 76
3000 single precision floating point registers (32-bit) 77-140
3001 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
3002 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
3003 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
3004 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3005 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3006 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3007 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3008 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3010 TOTAL SPACE FOR REGISTERS: 868 bytes
3012 From here on they are all pseudo registers: no memory allocated.
3013 REGISTER_BYTE returns the register byte for the base register.
3015 double precision registers (pseudo) 141-172
3016 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3017 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3018 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3019 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3021 floating point pairs (pseudo) 173-204
3022 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3023 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3024 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3025 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3027 floating point vectors (4 floating point regs) (pseudo) 205-220
3028 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3029 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3031 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3032 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3033 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3035 gbr_c, mach_c, macl_c, pr_c, t_c,
3037 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3038 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3039 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3040 fv0_c, fv4_c, fv8_c, fv12_c
3044 sh_sh64_register_byte (int reg_nr)
3046 int base_regnum = -1;
3047 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3049 /* If it is a pseudo register, get the number of the first floating
3050 point register that is part of it. */
3051 if (reg_nr >= tdep->DR0_REGNUM
3052 && reg_nr <= tdep->DR_LAST_REGNUM)
3053 base_regnum = dr_reg_base_num (reg_nr);
3055 else if (reg_nr >= tdep->FPP0_REGNUM
3056 && reg_nr <= tdep->FPP_LAST_REGNUM)
3057 base_regnum = fpp_reg_base_num (reg_nr);
3059 else if (reg_nr >= tdep->FV0_REGNUM
3060 && reg_nr <= tdep->FV_LAST_REGNUM)
3061 base_regnum = fv_reg_base_num (reg_nr);
3063 /* sh compact pseudo register. FPSCR is a pathological case, need to
3064 treat it as special. */
3065 else if ((reg_nr >= tdep->R0_C_REGNUM
3066 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3067 && reg_nr != tdep->FPSCR_C_REGNUM)
3068 base_regnum = sh64_compact_reg_base_num (reg_nr);
3070 /* Now return the offset in bytes within the register cache. */
3071 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3072 if (reg_nr >= tdep->DR0_REGNUM
3073 && reg_nr <= tdep->FV_LAST_REGNUM)
3074 return (base_regnum - FP0_REGNUM + 1) * 4
3075 + (tdep->TR7_REGNUM + 1) * 8;
3077 /* sh compact pseudo register: general register */
3078 if ((reg_nr >= tdep->R0_C_REGNUM
3079 && reg_nr <= tdep->R_LAST_C_REGNUM))
3080 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3081 ? base_regnum * 8 + 4
3084 /* sh compact pseudo register: */
3085 if (reg_nr == tdep->PC_C_REGNUM
3086 || reg_nr == tdep->GBR_C_REGNUM
3087 || reg_nr == tdep->MACL_C_REGNUM
3088 || reg_nr == tdep->PR_C_REGNUM)
3089 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3090 ? base_regnum * 8 + 4
3093 if (reg_nr == tdep->MACH_C_REGNUM)
3094 return base_regnum * 8;
3096 if (reg_nr == tdep->T_C_REGNUM)
3097 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
3099 /* sh compact pseudo register: floating point register */
3100 else if (reg_nr >=tdep->FP0_C_REGNUM
3101 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3102 return (base_regnum - FP0_REGNUM) * 4
3103 + (tdep->TR7_REGNUM + 1) * 8 + 4;
3105 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3106 /* This is complicated, for now return the beginning of the
3107 architectural FPSCR register. */
3108 return (tdep->TR7_REGNUM + 1) * 8;
3110 else if (reg_nr == tdep->FPUL_C_REGNUM)
3111 return ((base_regnum - FP0_REGNUM) * 4 +
3112 (tdep->TR7_REGNUM + 1) * 8 + 4);
3114 /* It is not a pseudo register. */
3115 /* It is a 64 bit register. */
3116 else if (reg_nr <= tdep->TR7_REGNUM)
3119 /* It is a 32 bit register. */
3121 if (reg_nr == tdep->FPSCR_REGNUM)
3122 return (tdep->FPSCR_REGNUM * 8);
3124 /* It is floating point 32-bit register */
3126 return ((tdep->TR7_REGNUM + 1) * 8
3127 + (reg_nr - FP0_REGNUM + 1) * 4);
3130 /* Number of bytes of storage in the actual machine representation for
3133 sh_default_register_raw_size (int reg_nr)
3139 sh_sh4_register_raw_size (int reg_nr)
3141 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3143 if (reg_nr >= tdep->DR0_REGNUM
3144 && reg_nr <= tdep->DR_LAST_REGNUM)
3146 else if (reg_nr >= tdep->FV0_REGNUM
3147 && reg_nr <= tdep->FV_LAST_REGNUM)
3154 sh_sh64_register_raw_size (int reg_nr)
3156 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3158 if ((reg_nr >= tdep->DR0_REGNUM
3159 && reg_nr <= tdep->DR_LAST_REGNUM)
3160 || (reg_nr >= tdep->FPP0_REGNUM
3161 && reg_nr <= tdep->FPP_LAST_REGNUM)
3162 || (reg_nr >= tdep->DR0_C_REGNUM
3163 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3164 || (reg_nr <= tdep->TR7_REGNUM))
3167 else if ((reg_nr >= tdep->FV0_REGNUM
3168 && reg_nr <= tdep->FV_LAST_REGNUM)
3169 || (reg_nr >= tdep->FV0_C_REGNUM
3170 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3173 else /* this covers also the 32-bit SH compact registers. */
3177 /* Number of bytes of storage in the program's representation
3180 sh_register_virtual_size (int reg_nr)
3187 sh_sh64_register_virtual_size (int reg_nr)
3189 if (reg_nr >= FP0_REGNUM
3190 && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)
3196 /* Return the GDB type object for the "standard" data type
3197 of data in register N. */
3198 static struct type *
3199 sh_sh3e_register_virtual_type (int reg_nr)
3201 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3203 if ((reg_nr >= FP0_REGNUM
3204 && (reg_nr <= tdep->FP_LAST_REGNUM))
3205 || (reg_nr == tdep->FPUL_REGNUM))
3206 return builtin_type_float;
3208 return builtin_type_int;
3211 static struct type *
3212 sh_sh4_build_float_register_type (int high)
3216 temp = create_range_type (NULL, builtin_type_int, 0, high);
3217 return create_array_type (NULL, builtin_type_float, temp);
3220 static struct type *
3221 sh_sh4_register_virtual_type (int reg_nr)
3223 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3225 if ((reg_nr >= FP0_REGNUM
3226 && (reg_nr <= tdep->FP_LAST_REGNUM))
3227 || (reg_nr == tdep->FPUL_REGNUM))
3228 return builtin_type_float;
3229 else if (reg_nr >= tdep->DR0_REGNUM
3230 && reg_nr <= tdep->DR_LAST_REGNUM)
3231 return builtin_type_double;
3232 else if (reg_nr >= tdep->FV0_REGNUM
3233 && reg_nr <= tdep->FV_LAST_REGNUM)
3234 return sh_sh4_build_float_register_type (3);
3236 return builtin_type_int;
3239 static struct type *
3240 sh_sh64_register_virtual_type (int reg_nr)
3242 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3244 if ((reg_nr >= FP0_REGNUM
3245 && reg_nr <= tdep->FP_LAST_REGNUM)
3246 || (reg_nr >= tdep->FP0_C_REGNUM
3247 && reg_nr <= tdep->FP_LAST_C_REGNUM))
3248 return builtin_type_float;
3249 else if ((reg_nr >= tdep->DR0_REGNUM
3250 && reg_nr <= tdep->DR_LAST_REGNUM)
3251 || (reg_nr >= tdep->DR0_C_REGNUM
3252 && reg_nr <= tdep->DR_LAST_C_REGNUM))
3253 return builtin_type_double;
3254 else if (reg_nr >= tdep->FPP0_REGNUM
3255 && reg_nr <= tdep->FPP_LAST_REGNUM)
3256 return sh_sh4_build_float_register_type (1);
3257 else if ((reg_nr >= tdep->FV0_REGNUM
3258 && reg_nr <= tdep->FV_LAST_REGNUM)
3259 ||(reg_nr >= tdep->FV0_C_REGNUM
3260 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3261 return sh_sh4_build_float_register_type (3);
3262 else if (reg_nr == tdep->FPSCR_REGNUM)
3263 return builtin_type_int;
3264 else if (reg_nr >= tdep->R0_C_REGNUM
3265 && reg_nr < tdep->FP0_C_REGNUM)
3266 return builtin_type_int;
3268 return builtin_type_long_long;
3271 static struct type *
3272 sh_default_register_virtual_type (int reg_nr)
3274 return builtin_type_int;
3277 /* On the sh4, the DRi pseudo registers are problematic if the target
3278 is little endian. When the user writes one of those registers, for
3279 instance with 'ser var $dr0=1', we want the double to be stored
3281 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3282 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3284 This corresponds to little endian byte order & big endian word
3285 order. However if we let gdb write the register w/o conversion, it
3286 will write fr0 and fr1 this way:
3287 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3288 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3289 because it will consider fr0 and fr1 as a single LE stretch of memory.
3291 To achieve what we want we must force gdb to store things in
3292 floatformat_ieee_double_littlebyte_bigword (which is defined in
3293 include/floatformat.h and libiberty/floatformat.c.
3295 In case the target is big endian, there is no problem, the
3296 raw bytes will look like:
3297 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3298 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3300 The other pseudo registers (the FVs) also don't pose a problem
3301 because they are stored as 4 individual FP elements. */
3304 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
3305 char *from, char *to)
3307 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3309 if (regnum >= tdep->DR0_REGNUM
3310 && regnum <= tdep->DR_LAST_REGNUM)
3313 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3314 store_floating (to, TYPE_LENGTH (type), val);
3317 error ("sh_register_convert_to_virtual called with non DR register number");
3321 sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
3322 char *from, char *to)
3324 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3326 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3328 /* It is a no-op. */
3329 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3333 if ((regnum >= tdep->DR0_REGNUM
3334 && regnum <= tdep->DR_LAST_REGNUM)
3335 || (regnum >= tdep->DR0_C_REGNUM
3336 && regnum <= tdep->DR_LAST_C_REGNUM))
3339 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3340 store_floating(to, TYPE_LENGTH(type), val);
3343 error("sh_register_convert_to_virtual called with non DR register number");
3347 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
3348 const void *from, void *to)
3350 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3352 if (regnum >= tdep->DR0_REGNUM
3353 && regnum <= tdep->DR_LAST_REGNUM)
3355 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3356 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3359 error("sh_register_convert_to_raw called with non DR register number");
3363 sh_sh64_register_convert_to_raw (struct type *type, int regnum,
3364 const void *from, void *to)
3366 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3368 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3370 /* It is a no-op. */
3371 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3375 if ((regnum >= tdep->DR0_REGNUM
3376 && regnum <= tdep->DR_LAST_REGNUM)
3377 || (regnum >= tdep->DR0_C_REGNUM
3378 && regnum <= tdep->DR_LAST_C_REGNUM))
3380 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3381 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3384 error("sh_register_convert_to_raw called with non DR register number");
3388 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3389 int reg_nr, void *buffer)
3391 int base_regnum, portion;
3392 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3393 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3395 if (reg_nr >= tdep->DR0_REGNUM
3396 && reg_nr <= tdep->DR_LAST_REGNUM)
3398 base_regnum = dr_reg_base_num (reg_nr);
3400 /* Build the value in the provided buffer. */
3401 /* Read the real regs for which this one is an alias. */
3402 for (portion = 0; portion < 2; portion++)
3403 regcache_raw_read (regcache, base_regnum + portion,
3405 + REGISTER_RAW_SIZE (base_regnum) * portion));
3406 /* We must pay attention to the endiannes. */
3407 sh_sh4_register_convert_to_virtual (reg_nr,
3408 REGISTER_VIRTUAL_TYPE (reg_nr),
3409 temp_buffer, buffer);
3411 else if (reg_nr >= tdep->FV0_REGNUM
3412 && reg_nr <= tdep->FV_LAST_REGNUM)
3414 base_regnum = fv_reg_base_num (reg_nr);
3416 /* Read the real regs for which this one is an alias. */
3417 for (portion = 0; portion < 4; portion++)
3418 regcache_raw_read (regcache, base_regnum + portion,
3420 + REGISTER_RAW_SIZE (base_regnum) * portion));
3425 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3426 int reg_nr, void *buffer)
3431 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3432 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3434 if (reg_nr >= tdep->DR0_REGNUM
3435 && reg_nr <= tdep->DR_LAST_REGNUM)
3437 base_regnum = dr_reg_base_num (reg_nr);
3439 /* Build the value in the provided buffer. */
3440 /* DR regs are double precision registers obtained by
3441 concatenating 2 single precision floating point registers. */
3442 for (portion = 0; portion < 2; portion++)
3443 regcache_raw_read (regcache, base_regnum + portion,
3445 + REGISTER_RAW_SIZE (base_regnum) * portion));
3447 /* We must pay attention to the endiannes. */
3448 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3449 temp_buffer, buffer);
3453 else if (reg_nr >= tdep->FPP0_REGNUM
3454 && reg_nr <= tdep->FPP_LAST_REGNUM)
3456 base_regnum = fpp_reg_base_num (reg_nr);
3458 /* Build the value in the provided buffer. */
3459 /* FPP regs are pairs of single precision registers obtained by
3460 concatenating 2 single precision floating point registers. */
3461 for (portion = 0; portion < 2; portion++)
3462 regcache_raw_read (regcache, base_regnum + portion,
3464 + REGISTER_RAW_SIZE (base_regnum) * portion));
3467 else if (reg_nr >= tdep->FV0_REGNUM
3468 && reg_nr <= tdep->FV_LAST_REGNUM)
3470 base_regnum = fv_reg_base_num (reg_nr);
3472 /* Build the value in the provided buffer. */
3473 /* FV regs are vectors of single precision registers obtained by
3474 concatenating 4 single precision floating point registers. */
3475 for (portion = 0; portion < 4; portion++)
3476 regcache_raw_read (regcache, base_regnum + portion,
3478 + REGISTER_RAW_SIZE (base_regnum) * portion));
3481 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3482 else if (reg_nr >= tdep->R0_C_REGNUM
3483 && reg_nr <= tdep->T_C_REGNUM)
3485 base_regnum = sh64_compact_reg_base_num (reg_nr);
3487 /* Build the value in the provided buffer. */
3488 regcache_raw_read (regcache, base_regnum, temp_buffer);
3489 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3491 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
3494 else if (reg_nr >= tdep->FP0_C_REGNUM
3495 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3497 base_regnum = sh64_compact_reg_base_num (reg_nr);
3499 /* Build the value in the provided buffer. */
3500 /* Floating point registers map 1-1 to the media fp regs,
3501 they have the same size and endienness. */
3502 regcache_raw_read (regcache, base_regnum, buffer);
3505 else if (reg_nr >= tdep->DR0_C_REGNUM
3506 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3508 base_regnum = sh64_compact_reg_base_num (reg_nr);
3510 /* DR_C regs are double precision registers obtained by
3511 concatenating 2 single precision floating point registers. */
3512 for (portion = 0; portion < 2; portion++)
3513 regcache_raw_read (regcache, base_regnum + portion,
3515 + REGISTER_RAW_SIZE (base_regnum) * portion));
3517 /* We must pay attention to the endiannes. */
3518 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3519 temp_buffer, buffer);
3522 else if (reg_nr >= tdep->FV0_C_REGNUM
3523 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3525 base_regnum = sh64_compact_reg_base_num (reg_nr);
3527 /* Build the value in the provided buffer. */
3528 /* FV_C regs are vectors of single precision registers obtained by
3529 concatenating 4 single precision floating point registers. */
3530 for (portion = 0; portion < 4; portion++)
3531 regcache_raw_read (regcache, base_regnum + portion,
3533 + REGISTER_RAW_SIZE (base_regnum) * portion));
3536 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3538 int fpscr_base_regnum;
3540 unsigned int fpscr_value;
3541 unsigned int sr_value;
3542 unsigned int fpscr_c_value;
3543 unsigned int fpscr_c_part1_value;
3544 unsigned int fpscr_c_part2_value;
3546 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3547 sr_base_regnum = tdep->SR_REGNUM;
3549 /* Build the value in the provided buffer. */
3550 /* FPSCR_C is a very weird register that contains sparse bits
3551 from the FPSCR and the SR architectural registers.
3558 2-17 Bit 2-18 of FPSCR
3559 18-20 Bits 12,13,14 of SR
3563 /* Get FPSCR into a local buffer */
3564 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3565 /* Get value as an int. */
3566 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3567 /* Get SR into a local buffer */
3568 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3569 /* Get value as an int. */
3570 sr_value = extract_unsigned_integer (temp_buffer, 4);
3571 /* Build the new value. */
3572 fpscr_c_part1_value = fpscr_value & 0x3fffd;
3573 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
3574 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
3575 /* Store that in out buffer!!! */
3576 store_unsigned_integer (buffer, 4, fpscr_c_value);
3577 /* FIXME There is surely an endianness gotcha here. */
3580 else if (reg_nr == tdep->FPUL_C_REGNUM)
3582 base_regnum = sh64_compact_reg_base_num (reg_nr);
3584 /* FPUL_C register is floating point register 32,
3585 same size, same endianness. */
3586 regcache_raw_read (regcache, base_regnum, buffer);
3591 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3592 int reg_nr, const void *buffer)
3594 int base_regnum, portion;
3595 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3596 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3598 if (reg_nr >= tdep->DR0_REGNUM
3599 && reg_nr <= tdep->DR_LAST_REGNUM)
3601 base_regnum = dr_reg_base_num (reg_nr);
3603 /* We must pay attention to the endiannes. */
3604 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3605 buffer, temp_buffer);
3607 /* Write the real regs for which this one is an alias. */
3608 for (portion = 0; portion < 2; portion++)
3609 regcache_raw_write (regcache, base_regnum + portion,
3611 + REGISTER_RAW_SIZE (base_regnum) * portion));
3613 else if (reg_nr >= tdep->FV0_REGNUM
3614 && reg_nr <= tdep->FV_LAST_REGNUM)
3616 base_regnum = fv_reg_base_num (reg_nr);
3618 /* Write the real regs for which this one is an alias. */
3619 for (portion = 0; portion < 4; portion++)
3620 regcache_raw_write (regcache, base_regnum + portion,
3622 + REGISTER_RAW_SIZE (base_regnum) * portion));
3627 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3628 int reg_nr, const void *buffer)
3630 int base_regnum, portion;
3632 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3633 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3635 if (reg_nr >= tdep->DR0_REGNUM
3636 && reg_nr <= tdep->DR_LAST_REGNUM)
3638 base_regnum = dr_reg_base_num (reg_nr);
3639 /* We must pay attention to the endiannes. */
3640 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3641 buffer, temp_buffer);
3644 /* Write the real regs for which this one is an alias. */
3645 for (portion = 0; portion < 2; portion++)
3646 regcache_raw_write (regcache, base_regnum + portion,
3648 + REGISTER_RAW_SIZE (base_regnum) * portion));
3651 else if (reg_nr >= tdep->FPP0_REGNUM
3652 && reg_nr <= tdep->FPP_LAST_REGNUM)
3654 base_regnum = fpp_reg_base_num (reg_nr);
3656 /* Write the real regs for which this one is an alias. */
3657 for (portion = 0; portion < 2; portion++)
3658 regcache_raw_write (regcache, base_regnum + portion,
3660 + REGISTER_RAW_SIZE (base_regnum) * portion));
3663 else if (reg_nr >= tdep->FV0_REGNUM
3664 && reg_nr <= tdep->FV_LAST_REGNUM)
3666 base_regnum = fv_reg_base_num (reg_nr);
3668 /* Write the real regs for which this one is an alias. */
3669 for (portion = 0; portion < 4; portion++)
3670 regcache_raw_write (regcache, base_regnum + portion,
3672 + REGISTER_RAW_SIZE (base_regnum) * portion));
3675 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3676 register but only 4 bytes of it. */
3677 else if (reg_nr >= tdep->R0_C_REGNUM
3678 && reg_nr <= tdep->T_C_REGNUM)
3680 base_regnum = sh64_compact_reg_base_num (reg_nr);
3681 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3682 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3686 /* Let's read the value of the base register into a temporary
3687 buffer, so that overwriting the last four bytes with the new
3688 value of the pseudo will leave the upper 4 bytes unchanged. */
3689 regcache_raw_read (regcache, base_regnum, temp_buffer);
3690 /* Write as an 8 byte quantity */
3691 memcpy (temp_buffer + offset, buffer, 4);
3692 regcache_raw_write (regcache, base_regnum, temp_buffer);
3695 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3696 registers. Both are 4 bytes. */
3697 else if (reg_nr >= tdep->FP0_C_REGNUM
3698 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3700 base_regnum = sh64_compact_reg_base_num (reg_nr);
3701 regcache_raw_write (regcache, base_regnum, buffer);
3704 else if (reg_nr >= tdep->DR0_C_REGNUM
3705 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3707 base_regnum = sh64_compact_reg_base_num (reg_nr);
3708 for (portion = 0; portion < 2; portion++)
3710 /* We must pay attention to the endiannes. */
3711 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3712 buffer, temp_buffer);
3714 regcache_raw_write (regcache, base_regnum + portion,
3716 + REGISTER_RAW_SIZE (base_regnum) * portion));
3720 else if (reg_nr >= tdep->FV0_C_REGNUM
3721 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3723 base_regnum = sh64_compact_reg_base_num (reg_nr);
3725 for (portion = 0; portion < 4; portion++)
3727 regcache_raw_write (regcache, base_regnum + portion,
3729 + REGISTER_RAW_SIZE (base_regnum) * portion));
3733 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3735 int fpscr_base_regnum;
3737 unsigned int fpscr_value;
3738 unsigned int sr_value;
3739 unsigned int old_fpscr_value;
3740 unsigned int old_sr_value;
3741 unsigned int fpscr_c_value;
3742 unsigned int fpscr_mask;
3743 unsigned int sr_mask;
3745 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3746 sr_base_regnum = tdep->SR_REGNUM;
3748 /* FPSCR_C is a very weird register that contains sparse bits
3749 from the FPSCR and the SR architectural registers.
3756 2-17 Bit 2-18 of FPSCR
3757 18-20 Bits 12,13,14 of SR
3761 /* Get value as an int. */
3762 fpscr_c_value = extract_unsigned_integer (buffer, 4);
3764 /* Build the new values. */
3765 fpscr_mask = 0x0003fffd;
3766 sr_mask = 0x001c0000;
3768 fpscr_value = fpscr_c_value & fpscr_mask;
3769 sr_value = (fpscr_value & sr_mask) >> 6;
3771 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3772 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3773 old_fpscr_value &= 0xfffc0002;
3774 fpscr_value |= old_fpscr_value;
3775 store_unsigned_integer (temp_buffer, 4, fpscr_value);
3776 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
3778 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3779 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
3780 old_sr_value &= 0xffff8fff;
3781 sr_value |= old_sr_value;
3782 store_unsigned_integer (temp_buffer, 4, sr_value);
3783 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
3786 else if (reg_nr == tdep->FPUL_C_REGNUM)
3788 base_regnum = sh64_compact_reg_base_num (reg_nr);
3789 regcache_raw_write (regcache, base_regnum, buffer);
3793 /* Floating point vector of 4 float registers. */
3795 do_fv_register_info (int fv_regnum)
3797 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
3798 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3799 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
3800 (int) read_register (first_fp_reg_num),
3801 (int) read_register (first_fp_reg_num + 1),
3802 (int) read_register (first_fp_reg_num + 2),
3803 (int) read_register (first_fp_reg_num + 3));
3806 /* Floating point vector of 4 float registers, compact mode. */
3808 do_fv_c_register_info (int fv_regnum)
3810 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
3811 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3812 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM,
3813 (int) read_register (first_fp_reg_num),
3814 (int) read_register (first_fp_reg_num + 1),
3815 (int) read_register (first_fp_reg_num + 2),
3816 (int) read_register (first_fp_reg_num + 3));
3819 /* Pairs of single regs. The DR are instead double precision
3822 do_fpp_register_info (int fpp_regnum)
3824 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
3826 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3827 fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM,
3828 (int) read_register (first_fp_reg_num),
3829 (int) read_register (first_fp_reg_num + 1));
3832 /* Double precision registers. */
3834 do_dr_register_info (int dr_regnum)
3836 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
3838 printf_filtered ("dr%d\t0x%08x%08x\n",
3839 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
3840 (int) read_register (first_fp_reg_num),
3841 (int) read_register (first_fp_reg_num + 1));
3844 /* Double precision registers, compact mode. */
3846 do_dr_c_register_info (int dr_regnum)
3848 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
3850 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3851 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM,
3852 (int) read_register (first_fp_reg_num),
3853 (int) read_register (first_fp_reg_num +1));
3856 /* General register in compact mode. */
3858 do_r_c_register_info (int r_c_regnum)
3860 int regnum = sh64_compact_reg_base_num (r_c_regnum);
3862 printf_filtered ("r%d_c\t0x%08x\n",
3863 r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM,
3864 /*FIXME!!!*/ (int) read_register (regnum));
3867 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3868 shmedia REGISTERS. */
3869 /* Control registers, compact mode. */
3871 do_cr_c_register_info (int cr_c_regnum)
3873 switch (cr_c_regnum)
3875 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3877 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3879 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3881 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3883 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3885 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3887 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3889 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
3895 sh_do_pseudo_register (int regnum)
3897 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3899 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
3900 internal_error (__FILE__, __LINE__,
3901 "Invalid pseudo register number %d\n", regnum);
3902 else if (regnum >= tdep->DR0_REGNUM
3903 && regnum < tdep->DR_LAST_REGNUM)
3904 do_dr_register_info (regnum);
3905 else if (regnum >= tdep->FV0_REGNUM
3906 && regnum <= tdep->FV_LAST_REGNUM)
3907 do_fv_register_info (regnum);
3911 sh_do_fp_register (int regnum)
3912 { /* do values for FP (float) regs */
3914 double flt; /* double extracted from raw hex data */
3918 /* Allocate space for the float. */
3919 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
3921 /* Get the data in raw format. */
3922 if (!frame_register_read (selected_frame, regnum, raw_buffer))
3923 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3925 /* Get the register as a number */
3926 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
3928 /* Print the name and some spaces. */
3929 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3930 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
3932 /* Print the value. */
3934 printf_filtered ("<invalid float>");
3936 printf_filtered ("%-10.9g", flt);
3938 /* Print the fp register as hex. */
3939 printf_filtered ("\t(raw 0x");
3940 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
3942 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
3943 : REGISTER_RAW_SIZE (regnum) - 1 - j;
3944 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
3946 printf_filtered (")");
3947 printf_filtered ("\n");
3951 sh64_do_pseudo_register (int regnum)
3953 /* All the sh64-compact mode registers are pseudo registers. */
3954 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3956 if (regnum < NUM_REGS
3957 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
3958 internal_error (__FILE__, __LINE__,
3959 "Invalid pseudo register number %d\n", regnum);
3961 else if ((regnum >= tdep->DR0_REGNUM
3962 && regnum <= tdep->DR_LAST_REGNUM))
3963 do_dr_register_info (regnum);
3965 else if ((regnum >= tdep->DR0_C_REGNUM
3966 && regnum <= tdep->DR_LAST_C_REGNUM))
3967 do_dr_c_register_info (regnum);
3969 else if ((regnum >= tdep->FV0_REGNUM
3970 && regnum <= tdep->FV_LAST_REGNUM))
3971 do_fv_register_info (regnum);
3973 else if ((regnum >= tdep->FV0_C_REGNUM
3974 && regnum <= tdep->FV_LAST_C_REGNUM))
3975 do_fv_c_register_info (regnum);
3977 else if (regnum >= tdep->FPP0_REGNUM
3978 && regnum <= tdep->FPP_LAST_REGNUM)
3979 do_fpp_register_info (regnum);
3981 else if (regnum >= tdep->R0_C_REGNUM
3982 && regnum <= tdep->R_LAST_C_REGNUM)
3983 do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */
3985 else if (regnum >= tdep->FP0_C_REGNUM
3986 && regnum <= tdep->FP_LAST_C_REGNUM)
3987 sh_do_fp_register (regnum); /* this should work also for pseudoregs */
3989 else if (regnum >= tdep->PC_C_REGNUM
3990 && regnum <= tdep->FPUL_C_REGNUM)
3991 do_cr_c_register_info (regnum);
3996 sh_do_register (int regnum)
3998 char raw_buffer[MAX_REGISTER_RAW_SIZE];
4000 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
4001 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
4003 /* Get the data in raw format. */
4004 if (!frame_register_read (selected_frame, regnum, raw_buffer))
4005 printf_filtered ("*value not available*\n");
4007 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4008 gdb_stdout, 'x', 1, 0, Val_pretty_default);
4009 printf_filtered ("\t");
4010 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4011 gdb_stdout, 0, 1, 0, Val_pretty_default);
4012 printf_filtered ("\n");
4016 sh_print_register (int regnum)
4018 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
4019 internal_error (__FILE__, __LINE__,
4020 "Invalid register number %d\n", regnum);
4022 else if (regnum >= 0 && regnum < NUM_REGS)
4024 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4025 sh_do_fp_register (regnum); /* FP regs */
4027 sh_do_register (regnum); /* All other regs */
4030 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4031 do_pseudo_register (regnum);
4035 sh_do_registers_info (int regnum, int fpregs)
4037 if (regnum != -1) /* do one specified register */
4039 if (*(REGISTER_NAME (regnum)) == '\0')
4040 error ("Not a valid register for the current processor type");
4042 sh_print_register (regnum);
4045 /* do all (or most) registers */
4048 while (regnum < NUM_REGS)
4050 /* If the register name is empty, it is undefined for this
4051 processor, so don't display anything. */
4052 if (REGISTER_NAME (regnum) == NULL
4053 || *(REGISTER_NAME (regnum)) == '\0')
4059 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4063 /* true for "INFO ALL-REGISTERS" command */
4064 sh_do_fp_register (regnum); /* FP regs */
4068 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
4072 sh_do_register (regnum); /* All other regs */
4078 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4080 do_pseudo_register (regnum);
4087 sh_compact_do_registers_info (int regnum, int fpregs)
4089 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4090 if (regnum != -1) /* do one specified register */
4092 if (*(REGISTER_NAME (regnum)) == '\0')
4093 error ("Not a valid register for the current processor type");
4095 if (regnum >= 0 && regnum < tdep->R0_C_REGNUM)
4096 error ("Not a valid register for the current processor mode.");
4098 sh_print_register (regnum);
4101 /* do all compact registers */
4103 regnum = tdep->R0_C_REGNUM;
4104 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4106 do_pseudo_register (regnum);
4113 sh64_do_registers_info (int regnum, int fpregs)
4115 if (pc_is_isa32 (selected_frame->pc))
4116 sh_do_registers_info (regnum, fpregs);
4118 sh_compact_do_registers_info (regnum, fpregs);
4121 #ifdef SVR4_SHARED_LIBS
4123 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4124 for native i386 linux targets using the struct offsets defined in
4125 link.h (but without actual reference to that file).
4127 This makes it possible to access i386-linux shared libraries from
4128 a gdb that was not built on an i386-linux host (for cross debugging).
4131 struct link_map_offsets *
4132 sh_linux_svr4_fetch_link_map_offsets (void)
4134 static struct link_map_offsets lmo;
4135 static struct link_map_offsets *lmp = 0;
4141 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
4143 lmo.r_map_offset = 4;
4146 lmo.link_map_size = 20; /* 552 not actual size but all we need */
4148 lmo.l_addr_offset = 0;
4149 lmo.l_addr_size = 4;
4151 lmo.l_name_offset = 4;
4152 lmo.l_name_size = 4;
4154 lmo.l_next_offset = 12;
4155 lmo.l_next_size = 4;
4157 lmo.l_prev_offset = 16;
4158 lmo.l_prev_size = 4;
4163 #endif /* SVR4_SHARED_LIBS */
4168 DSP_DSR_REGNUM = 24,
4180 DSP_MOD_REGNUM = 40,
4185 DSP_R0_BANK_REGNUM = 51,
4186 DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7
4190 sh_dsp_register_sim_regno (int nr)
4192 if (legacy_register_sim_regno (nr) < 0)
4193 return legacy_register_sim_regno (nr);
4194 if (nr >= DSP_DSR_REGNUM && nr < DSP_Y1_REGNUM)
4195 return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM;
4196 if (nr == DSP_MOD_REGNUM)
4197 return SIM_SH_MOD_REGNUM;
4198 if (nr == DSP_RS_REGNUM)
4199 return SIM_SH_RS_REGNUM;
4200 if (nr == DSP_RE_REGNUM)
4201 return SIM_SH_RE_REGNUM;
4202 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
4203 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
4207 static gdbarch_init_ftype sh_gdbarch_init;
4209 static struct gdbarch *
4210 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4212 static LONGEST sh_call_dummy_words[] = {0};
4213 struct gdbarch *gdbarch;
4214 struct gdbarch_tdep *tdep;
4215 gdbarch_register_name_ftype *sh_register_name;
4216 gdbarch_deprecated_store_return_value_ftype *sh_store_return_value;
4217 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
4218 enum gdb_osabi osabi = GDB_OSABI_UNKNOWN;
4220 /* Try to determine the ABI of the object we are loading. */
4222 if (info.abfd != NULL)
4224 osabi = gdbarch_lookup_osabi (info.abfd);
4225 /* If we get "unknown" back, just leave it that way. */
4228 /* Find a candidate among the list of pre-declared architectures. */
4229 for (arches = gdbarch_list_lookup_by_info (arches, &info);
4231 arches = gdbarch_list_lookup_by_info (arches->next, &info))
4233 /* Make sure the ABI selection matches. */
4234 tdep = gdbarch_tdep (arches->gdbarch);
4235 if (tdep && tdep->osabi == osabi)
4236 return arches->gdbarch;
4239 /* None found, create a new architecture from the information
4241 tdep = XMALLOC (struct gdbarch_tdep);
4242 gdbarch = gdbarch_alloc (&info, tdep);
4244 tdep->osabi = osabi;
4246 /* Initialize the register numbers that are not common to all the
4247 variants to -1, if necessary thse will be overwritten in the case
4249 tdep->FPUL_REGNUM = -1;
4250 tdep->FPSCR_REGNUM = -1;
4251 tdep->PR_REGNUM = 17;
4252 tdep->SR_REGNUM = 22;
4253 tdep->DSR_REGNUM = -1;
4254 tdep->FP_LAST_REGNUM = -1;
4255 tdep->A0G_REGNUM = -1;
4256 tdep->A0_REGNUM = -1;
4257 tdep->A1G_REGNUM = -1;
4258 tdep->A1_REGNUM = -1;
4259 tdep->M0_REGNUM = -1;
4260 tdep->M1_REGNUM = -1;
4261 tdep->X0_REGNUM = -1;
4262 tdep->X1_REGNUM = -1;
4263 tdep->Y0_REGNUM = -1;
4264 tdep->Y1_REGNUM = -1;
4265 tdep->MOD_REGNUM = -1;
4266 tdep->RS_REGNUM = -1;
4267 tdep->RE_REGNUM = -1;
4268 tdep->SSR_REGNUM = -1;
4269 tdep->SPC_REGNUM = -1;
4270 tdep->DR0_REGNUM = -1;
4271 tdep->DR_LAST_REGNUM = -1;
4272 tdep->FV0_REGNUM = -1;
4273 tdep->FV_LAST_REGNUM = -1;
4274 tdep->ARG0_REGNUM = 4;
4275 tdep->ARGLAST_REGNUM = 7;
4276 tdep->RETURN_REGNUM = 0;
4277 tdep->FLOAT_ARGLAST_REGNUM = -1;
4279 tdep->sh_abi = SH_ABI_UNKNOWN;
4281 set_gdbarch_fp0_regnum (gdbarch, -1);
4282 set_gdbarch_num_pseudo_regs (gdbarch, 0);
4283 set_gdbarch_max_register_raw_size (gdbarch, 4);
4284 set_gdbarch_max_register_virtual_size (gdbarch, 4);
4285 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4286 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4287 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
4288 set_gdbarch_sp_regnum (gdbarch, 15);
4289 set_gdbarch_fp_regnum (gdbarch, 14);
4290 set_gdbarch_pc_regnum (gdbarch, 16);
4291 set_gdbarch_register_size (gdbarch, 4);
4292 set_gdbarch_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4);
4293 set_gdbarch_deprecated_do_registers_info (gdbarch, sh_do_registers_info);
4294 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
4295 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
4296 set_gdbarch_get_saved_register (gdbarch, deprecated_generic_get_saved_register);
4297 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
4298 set_gdbarch_deprecated_extract_return_value (gdbarch, sh_extract_return_value);
4299 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
4300 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
4301 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
4302 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4303 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
4304 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
4305 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
4306 skip_prologue_hard_way = sh_skip_prologue_hard_way;
4307 do_pseudo_register = sh_do_pseudo_register;
4309 switch (info.bfd_arch_info->mach)
4312 sh_register_name = sh_sh_register_name;
4313 sh_show_regs = sh_generic_show_regs;
4314 sh_store_return_value = sh_default_store_return_value;
4315 sh_register_virtual_type = sh_default_register_virtual_type;
4316 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4317 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4318 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4319 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4322 sh_register_name = sh_sh_register_name;
4323 sh_show_regs = sh_generic_show_regs;
4324 sh_store_return_value = sh_default_store_return_value;
4325 sh_register_virtual_type = sh_default_register_virtual_type;
4326 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4327 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4328 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4329 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4331 case bfd_mach_sh_dsp:
4332 sh_register_name = sh_sh_dsp_register_name;
4333 sh_show_regs = sh_dsp_show_regs;
4334 sh_store_return_value = sh_default_store_return_value;
4335 sh_register_virtual_type = sh_default_register_virtual_type;
4336 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4337 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4338 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4339 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4340 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
4341 tdep->DSR_REGNUM = 24;
4342 tdep->A0G_REGNUM = 25;
4343 tdep->A0_REGNUM = 26;
4344 tdep->A1G_REGNUM = 27;
4345 tdep->A1_REGNUM = 28;
4346 tdep->M0_REGNUM = 29;
4347 tdep->M1_REGNUM = 30;
4348 tdep->X0_REGNUM = 31;
4349 tdep->X1_REGNUM = 32;
4350 tdep->Y0_REGNUM = 33;
4351 tdep->Y1_REGNUM = 34;
4352 tdep->MOD_REGNUM = 40;
4353 tdep->RS_REGNUM = 43;
4354 tdep->RE_REGNUM = 44;
4357 sh_register_name = sh_sh3_register_name;
4358 sh_show_regs = sh3_show_regs;
4359 sh_store_return_value = sh_default_store_return_value;
4360 sh_register_virtual_type = sh_default_register_virtual_type;
4361 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4362 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4363 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4364 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4365 tdep->SSR_REGNUM = 41;
4366 tdep->SPC_REGNUM = 42;
4369 sh_register_name = sh_sh3e_register_name;
4370 sh_show_regs = sh3e_show_regs;
4371 sh_store_return_value = sh3e_sh4_store_return_value;
4372 sh_register_virtual_type = sh_sh3e_register_virtual_type;
4373 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4374 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4375 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4376 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4377 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4378 set_gdbarch_fp0_regnum (gdbarch, 25);
4379 tdep->FPUL_REGNUM = 23;
4380 tdep->FPSCR_REGNUM = 24;
4381 tdep->FP_LAST_REGNUM = 40;
4382 tdep->SSR_REGNUM = 41;
4383 tdep->SPC_REGNUM = 42;
4385 case bfd_mach_sh3_dsp:
4386 sh_register_name = sh_sh3_dsp_register_name;
4387 sh_show_regs = sh3_dsp_show_regs;
4388 sh_store_return_value = sh_default_store_return_value;
4389 sh_register_virtual_type = sh_default_register_virtual_type;
4390 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4391 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4392 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4393 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4394 tdep->DSR_REGNUM = 24;
4395 tdep->A0G_REGNUM = 25;
4396 tdep->A0_REGNUM = 26;
4397 tdep->A1G_REGNUM = 27;
4398 tdep->A1_REGNUM = 28;
4399 tdep->M0_REGNUM = 29;
4400 tdep->M1_REGNUM = 30;
4401 tdep->X0_REGNUM = 31;
4402 tdep->X1_REGNUM = 32;
4403 tdep->Y0_REGNUM = 33;
4404 tdep->Y1_REGNUM = 34;
4405 tdep->MOD_REGNUM = 40;
4406 tdep->RS_REGNUM = 43;
4407 tdep->RE_REGNUM = 44;
4408 tdep->SSR_REGNUM = 41;
4409 tdep->SPC_REGNUM = 42;
4412 sh_register_name = sh_sh4_register_name;
4413 sh_show_regs = sh4_show_regs;
4414 sh_store_return_value = sh3e_sh4_store_return_value;
4415 sh_register_virtual_type = sh_sh4_register_virtual_type;
4416 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4417 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4418 set_gdbarch_fp0_regnum (gdbarch, 25);
4419 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
4420 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
4421 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
4422 set_gdbarch_num_pseudo_regs (gdbarch, 12);
4423 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4424 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
4425 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
4426 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
4427 tdep->FPUL_REGNUM = 23;
4428 tdep->FPSCR_REGNUM = 24;
4429 tdep->FP_LAST_REGNUM = 40;
4430 tdep->SSR_REGNUM = 41;
4431 tdep->SPC_REGNUM = 42;
4432 tdep->DR0_REGNUM = 59;
4433 tdep->DR_LAST_REGNUM = 66;
4434 tdep->FV0_REGNUM = 67;
4435 tdep->FV_LAST_REGNUM = 70;
4438 tdep->PR_REGNUM = 18;
4439 tdep->SR_REGNUM = 65;
4440 tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM;
4441 tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1;
4442 tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM;
4443 tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM;
4444 tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7;
4445 tdep->FPP0_REGNUM = 173;
4446 tdep->FPP_LAST_REGNUM = 204;
4447 tdep->DR0_REGNUM = 141;
4448 tdep->DR_LAST_REGNUM = 172;
4449 tdep->FV0_REGNUM = 205;
4450 tdep->FV_LAST_REGNUM = 220;
4451 tdep->R0_C_REGNUM = 221;
4452 tdep->R_LAST_C_REGNUM = 236;
4453 tdep->PC_C_REGNUM = 237;
4454 tdep->GBR_C_REGNUM = 238;
4455 tdep->MACH_C_REGNUM = 239;
4456 tdep->MACL_C_REGNUM = 240;
4457 tdep->PR_C_REGNUM = 241;
4458 tdep->T_C_REGNUM = 242;
4459 tdep->FPSCR_C_REGNUM = 243;
4460 tdep->FPUL_C_REGNUM = 244;
4461 tdep->FP0_C_REGNUM = 245;
4462 tdep->FP_LAST_C_REGNUM = 260;
4463 tdep->DR0_C_REGNUM = 261;
4464 tdep->DR_LAST_C_REGNUM = 268;
4465 tdep->FV0_C_REGNUM = 269;
4466 tdep->FV_LAST_C_REGNUM = 272;
4467 tdep->ARG0_REGNUM = 2;
4468 tdep->ARGLAST_REGNUM = 9;
4469 tdep->RETURN_REGNUM = 2;
4470 tdep->FLOAT_ARGLAST_REGNUM = 11;
4472 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
4473 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
4474 set_gdbarch_pc_regnum (gdbarch, 64);
4476 /* Determine the ABI */
4477 if (bfd_get_arch_size (info.abfd) == 64)
4479 /* If the ABI is the 64-bit one, it can only be sh-media. */
4480 tdep->sh_abi = SH_ABI_64;
4481 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4482 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4486 /* If the ABI is the 32-bit one it could be either media or
4488 tdep->sh_abi = SH_ABI_32;
4489 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4490 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4493 /* the number of real registers is the same whether we are in
4494 ISA16(compact) or ISA32(media). */
4495 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
4496 set_gdbarch_register_size (gdbarch, 8); /*????*/
4497 set_gdbarch_register_bytes (gdbarch,
4498 ((SIM_SH64_NR_FP_REGS + 1) * 4)
4499 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
4501 sh_register_name = sh_sh64_register_name;
4502 sh_show_regs = sh64_show_regs;
4503 sh_register_virtual_type = sh_sh64_register_virtual_type;
4504 sh_store_return_value = sh64_store_return_value;
4505 skip_prologue_hard_way = sh64_skip_prologue_hard_way;
4506 do_pseudo_register = sh64_do_pseudo_register;
4507 set_gdbarch_register_raw_size (gdbarch, sh_sh64_register_raw_size);
4508 set_gdbarch_register_virtual_size (gdbarch, sh_sh64_register_raw_size);
4509 set_gdbarch_register_byte (gdbarch, sh_sh64_register_byte);
4510 /* This seems awfully wrong!*/
4511 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4512 /* should include the size of the pseudo regs. */
4513 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4514 /* Or should that go in the virtual_size? */
4515 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4516 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
4517 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
4518 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
4520 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
4521 set_gdbarch_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
4522 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
4523 set_gdbarch_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
4524 set_gdbarch_frame_chain (gdbarch, sh64_frame_chain);
4525 set_gdbarch_get_saved_register (gdbarch, sh64_get_saved_register);
4526 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
4527 set_gdbarch_push_arguments (gdbarch, sh64_push_arguments);
4528 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
4529 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
4530 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
4531 set_gdbarch_pop_frame (gdbarch, sh64_pop_frame);
4532 set_gdbarch_elf_make_msymbol_special (gdbarch,
4533 sh64_elf_make_msymbol_special);
4536 sh_register_name = sh_generic_register_name;
4537 sh_show_regs = sh_generic_show_regs;
4538 sh_store_return_value = sh_default_store_return_value;
4539 sh_register_virtual_type = sh_default_register_virtual_type;
4540 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4541 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4542 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4543 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4547 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
4548 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4549 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
4550 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
4551 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
4553 set_gdbarch_register_name (gdbarch, sh_register_name);
4554 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
4556 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4557 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4558 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4559 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4560 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4561 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4563 set_gdbarch_use_generic_dummy_frames (gdbarch, 1);
4564 set_gdbarch_call_dummy_length (gdbarch, 0);
4565 set_gdbarch_call_dummy_location (gdbarch, AT_ENTRY_POINT);
4566 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
4567 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
4568 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
4569 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
4570 set_gdbarch_pc_in_call_dummy (gdbarch, generic_pc_in_call_dummy);
4571 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
4572 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
4573 set_gdbarch_call_dummy_p (gdbarch, 1);
4574 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
4575 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
4576 set_gdbarch_coerce_float_to_double (gdbarch,
4577 sh_coerce_float_to_double);
4579 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
4580 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
4582 set_gdbarch_deprecated_store_return_value (gdbarch, sh_store_return_value);
4583 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
4584 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4585 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4586 set_gdbarch_function_start_offset (gdbarch, 0);
4588 set_gdbarch_frame_args_skip (gdbarch, 0);
4589 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
4590 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
4591 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
4592 set_gdbarch_frame_args_address (gdbarch, default_frame_address);
4593 set_gdbarch_frame_locals_address (gdbarch, default_frame_address);
4594 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
4595 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
4596 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
4598 /* Hook in ABI-specific overrides, if they have been registered.
4600 FIXME: if the ABI is unknown, this is probably an embedded target,
4601 so we should not warn about this situation. */
4602 gdbarch_init_osabi (info, gdbarch, osabi);
4608 sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4610 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4615 fprintf_unfiltered (file, "sh_dump_tdep: OS ABI = %s\n",
4616 gdbarch_osabi_name (tdep->osabi));
4620 _initialize_sh_tdep (void)
4622 struct cmd_list_element *c;
4624 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep);
4626 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");