1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
39 #include "gdb_string.h"
40 #include "gdb_assert.h"
41 #include "arch-utils.h"
42 #include "floatformat.h"
50 #include "solib-svr4.h"
54 /* registers numbers shared with the simulator */
55 #include "gdb/sim-sh.h"
57 static void (*sh_show_regs) (void);
59 #define SH_NUM_REGS 59
68 /* Flag showing that a frame has been created in the prologue code. */
71 /* Saved registers. */
72 CORE_ADDR saved_regs[SH_NUM_REGS];
77 sh_sh_register_name (int reg_nr)
79 static char *register_names[] = {
80 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
81 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
82 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
84 "", "", "", "", "", "", "", "",
85 "", "", "", "", "", "", "", "",
87 "", "", "", "", "", "", "", "",
88 "", "", "", "", "", "", "", "",
92 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return register_names[reg_nr];
98 sh_sh3_register_name (int reg_nr)
100 static char *register_names[] = {
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
108 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
109 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
113 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
115 return register_names[reg_nr];
119 sh_sh3e_register_name (int reg_nr)
121 static char *register_names[] = {
122 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
123 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
124 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
126 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
127 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
129 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
130 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
134 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
136 return register_names[reg_nr];
140 sh_sh2e_register_name (int reg_nr)
142 static char *register_names[] = {
143 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
144 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
145 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
147 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
148 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
155 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
157 return register_names[reg_nr];
161 sh_sh_dsp_register_name (int reg_nr)
163 static char *register_names[] = {
164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
169 "y0", "y1", "", "", "", "", "", "mod",
171 "rs", "re", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
176 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
178 return register_names[reg_nr];
182 sh_sh3_dsp_register_name (int reg_nr)
184 static char *register_names[] = {
185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
192 "rs", "re", "", "", "", "", "", "",
193 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
194 "", "", "", "", "", "", "", "",
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return register_names[reg_nr];
204 sh_sh4_register_name (int reg_nr)
206 static char *register_names[] = {
207 /* general registers 0-15 */
208 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
209 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
211 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
214 /* floating point registers 25 - 40 */
215 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
216 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
220 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
222 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
223 /* double precision (pseudo) 59 - 66 */
224 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
225 /* vectors (pseudo) 67 - 70 */
226 "fv0", "fv4", "fv8", "fv12",
227 /* FIXME: missing XF 71 - 86 */
228 /* FIXME: missing XD 87 - 94 */
232 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
234 return register_names[reg_nr];
238 sh_sh4_nofpu_register_name (int reg_nr)
240 static char *register_names[] = {
241 /* general registers 0-15 */
242 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
243 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
245 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
248 /* floating point registers 25 - 40 -- not for nofpu target */
249 "", "", "", "", "", "", "", "",
250 "", "", "", "", "", "", "", "",
254 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
256 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
257 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
258 "", "", "", "", "", "", "", "",
259 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
264 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
266 return register_names[reg_nr];
270 sh_sh4al_dsp_register_name (int reg_nr)
272 static char *register_names[] = {
273 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
274 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
275 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
277 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
278 "y0", "y1", "", "", "", "", "", "mod",
280 "rs", "re", "", "", "", "", "", "",
281 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
282 "", "", "", "", "", "", "", "",
286 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
288 return register_names[reg_nr];
291 static const unsigned char *
292 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
294 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
295 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
297 *lenptr = sizeof (breakpoint);
301 /* Prologue looks like
305 sub <room_for_loca_vars>,r15
308 Actually it can be more complicated than this but that's it, basically.
311 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
312 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
314 /* JSR @Rm 0100mmmm00001011 */
315 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
317 /* STS.L PR,@-r15 0100111100100010
318 r15-4-->r15, PR-->(r15) */
319 #define IS_STS(x) ((x) == 0x4f22)
321 /* MOV.L Rm,@-r15 00101111mmmm0110
322 r15-4-->r15, Rm-->(R15) */
323 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
325 /* MOV r15,r14 0110111011110011
327 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
329 /* ADD #imm,r15 01111111iiiiiiii
331 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
333 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
334 #define IS_SHLL_R3(x) ((x) == 0x4300)
336 /* ADD r3,r15 0011111100111100
338 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
340 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
341 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
342 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
343 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
344 make this entirely clear. */
345 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
346 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
348 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
349 #define IS_MOV_ARG_TO_REG(x) \
350 (((x) & 0xf00f) == 0x6003 && \
351 ((x) & 0x00f0) >= 0x0040 && \
352 ((x) & 0x00f0) <= 0x0070)
353 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
354 #define IS_MOV_ARG_TO_IND_R14(x) \
355 (((x) & 0xff0f) == 0x2e02 && \
356 ((x) & 0x00f0) >= 0x0040 && \
357 ((x) & 0x00f0) <= 0x0070)
358 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
359 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
360 (((x) & 0xff00) == 0x1e00 && \
361 ((x) & 0x00f0) >= 0x0040 && \
362 ((x) & 0x00f0) <= 0x0070)
364 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
365 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
366 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
367 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
368 /* SUB Rn,R15 00111111nnnn1000 */
369 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
371 #define FPSCR_SZ (1 << 20)
373 /* The following instructions are used for epilogue testing. */
374 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
375 #define IS_RTS(x) ((x) == 0x000b)
376 #define IS_LDS(x) ((x) == 0x4f26)
377 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
378 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
379 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
381 /* Disassemble an instruction. */
383 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
385 info->endian = TARGET_BYTE_ORDER;
386 return print_insn_sh (memaddr, info);
390 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
391 struct sh_frame_cache *cache)
398 int reg, sav_reg = -1;
400 if (pc >= current_pc)
404 for (opc = pc + (2 * 28); pc < opc; pc += 2)
406 inst = read_memory_unsigned_integer (pc, 2);
407 /* See where the registers will be saved to */
410 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
411 cache->sp_offset += 4;
413 else if (IS_STS (inst))
415 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
416 cache->sp_offset += 4;
418 else if (IS_MOV_R3 (inst))
420 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
422 else if (IS_SHLL_R3 (inst))
426 else if (IS_ADD_R3SP (inst))
428 cache->sp_offset += -r3_val;
430 else if (IS_ADD_IMM_SP (inst))
432 offset = ((inst & 0xff) ^ 0x80) - 0x80;
433 cache->sp_offset -= offset;
435 else if (IS_MOVW_PCREL_TO_REG (inst))
439 reg = GET_TARGET_REG (inst);
443 offset = (inst & 0xff) << 1;
445 read_memory_integer ((pc + 4) + offset, 2);
449 else if (IS_MOVL_PCREL_TO_REG (inst))
453 reg = GET_TARGET_REG (inst);
457 offset = (inst & 0xff) << 2;
459 read_memory_integer (((pc & 0xfffffffc) + 4) + offset, 4);
463 else if (IS_SUB_REG_FROM_SP (inst))
465 reg = GET_SOURCE_REG (inst);
466 if (sav_reg > 0 && reg == sav_reg)
470 cache->sp_offset += sav_offset;
472 else if (IS_FPUSH (inst))
474 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
476 cache->sp_offset += 8;
480 cache->sp_offset += 4;
483 else if (IS_MOV_SP_FP (inst))
486 /* At this point, only allow argument register moves to other
487 registers or argument register moves to @(X,fp) which are
488 moving the register arguments onto the stack area allocated
489 by a former add somenumber to SP call. Don't allow moving
490 to an fp indirect address above fp + cache->sp_offset. */
492 for (opc = pc + 12; pc < opc; pc += 2)
494 inst = read_memory_integer (pc, 2);
495 if (IS_MOV_ARG_TO_IND_R14 (inst))
497 reg = GET_SOURCE_REG (inst);
498 if (cache->sp_offset > 0)
499 cache->saved_regs[reg] = cache->sp_offset;
501 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
503 reg = GET_SOURCE_REG (inst);
504 offset = (inst & 0xf) * 4;
505 if (cache->sp_offset > offset)
506 cache->saved_regs[reg] = cache->sp_offset - offset;
508 else if (IS_MOV_ARG_TO_REG (inst))
515 else if (IS_JSR (inst))
517 /* We have found a jsr that has been scheduled into the prologue.
518 If we continue the scan and return a pc someplace after this,
519 then setting a breakpoint on this function will cause it to
520 appear to be called after the function it is calling via the
521 jsr, which will be very confusing. Most likely the next
522 instruction is going to be IS_MOV_SP_FP in the delay slot. If
523 so, note that before returning the current pc. */
524 inst = read_memory_integer (pc + 2, 2);
525 if (IS_MOV_SP_FP (inst))
529 #if 0 /* This used to just stop when it found an instruction that
530 was not considered part of the prologue. Now, we just
531 keep going looking for likely instructions. */
540 /* Skip any prologue before the guts of a function */
542 /* Skip the prologue using the debug information. If this fails we'll
543 fall back on the 'guess' method below. */
545 after_prologue (CORE_ADDR pc)
547 struct symtab_and_line sal;
548 CORE_ADDR func_addr, func_end;
550 /* If we can not find the symbol in the partial symbol table, then
551 there is no hope we can determine the function's start address
553 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
556 /* Get the line associated with FUNC_ADDR. */
557 sal = find_pc_line (func_addr, 0);
559 /* There are only two cases to consider. First, the end of the source line
560 is within the function bounds. In that case we return the end of the
561 source line. Second is the end of the source line extends beyond the
562 bounds of the current function. We need to use the slow code to
563 examine instructions in that case. */
564 if (sal.end < func_end)
571 sh_skip_prologue (CORE_ADDR start_pc)
574 struct sh_frame_cache cache;
576 /* See if we can determine the end of the prologue via the symbol table.
577 If so, then return either PC, or the PC after the prologue, whichever
579 pc = after_prologue (start_pc);
581 /* If after_prologue returned a useful address, then use it. Else
582 fall back on the instruction skipping code. */
584 return max (pc, start_pc);
586 cache.sp_offset = -4;
587 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
596 Aggregate types not bigger than 8 bytes that have the same size and
597 alignment as one of the integer scalar types are returned in the
598 same registers as the integer type they match.
600 For example, a 2-byte aligned structure with size 2 bytes has the
601 same size and alignment as a short int, and will be returned in R0.
602 A 4-byte aligned structure with size 8 bytes has the same size and
603 alignment as a long long int, and will be returned in R0 and R1.
605 When an aggregate type is returned in R0 and R1, R0 contains the
606 first four bytes of the aggregate, and R1 contains the
607 remainder. If the size of the aggregate type is not a multiple of 4
608 bytes, the aggregate is tail-padded up to a multiple of 4
609 bytes. The value of the padding is undefined. For little-endian
610 targets the padding will appear at the most significant end of the
611 last element, for big-endian targets the padding appears at the
612 least significant end of the last element.
614 All other aggregate types are returned by address. The caller
615 function passes the address of an area large enough to hold the
616 aggregate value in R2. The called function stores the result in
619 To reiterate, structs smaller than 8 bytes could also be returned
620 in memory, if they don't pass the "same size and alignment as an
625 struct s { char c[3]; } wibble;
626 struct s foo(void) { return wibble; }
628 the return value from foo() will be in memory, not
629 in R0, because there is no 3-byte integer type.
633 struct s { char c[2]; } wibble;
634 struct s foo(void) { return wibble; }
636 because a struct containing two chars has alignment 1, that matches
637 type char, but size 2, that matches type short. There's no integer
638 type that has alignment 1 and size 2, so the struct is returned in
644 sh_use_struct_convention (int gcc_p, struct type *type)
646 int len = TYPE_LENGTH (type);
647 int nelem = TYPE_NFIELDS (type);
649 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
650 fit in two registers anyway) use struct convention. */
651 if (len != 1 && len != 2 && len != 4 && len != 8)
654 /* Scalar types and aggregate types with exactly one field are aligned
655 by definition. They are returned in registers. */
659 /* If the first field in the aggregate has the same length as the entire
660 aggregate type, the type is returned in registers. */
661 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
664 /* If the size of the aggregate is 8 bytes and the first field is
665 of size 4 bytes its alignment is equal to long long's alignment,
666 so it's returned in registers. */
667 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
670 /* Otherwise use struct convention. */
674 /* Extract from an array REGBUF containing the (raw) register state
675 the address in which a function should return its structure value,
676 as a CORE_ADDR (or an expression that can be used as one). */
678 sh_extract_struct_value_address (struct regcache *regcache)
682 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
687 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
692 /* Function: push_dummy_call (formerly push_arguments)
693 Setup the function arguments for calling a function in the inferior.
695 On the Renesas SH architecture, there are four registers (R4 to R7)
696 which are dedicated for passing function arguments. Up to the first
697 four arguments (depending on size) may go into these registers.
698 The rest go on the stack.
700 MVS: Except on SH variants that have floating point registers.
701 In that case, float and double arguments are passed in the same
702 manner, but using FP registers instead of GP registers.
704 Arguments that are smaller than 4 bytes will still take up a whole
705 register or a whole 32-bit word on the stack, and will be
706 right-justified in the register or the stack word. This includes
707 chars, shorts, and small aggregate types.
709 Arguments that are larger than 4 bytes may be split between two or
710 more registers. If there are not enough registers free, an argument
711 may be passed partly in a register (or registers), and partly on the
712 stack. This includes doubles, long longs, and larger aggregates.
713 As far as I know, there is no upper limit to the size of aggregates
714 that will be passed in this way; in other words, the convention of
715 passing a pointer to a large aggregate instead of a copy is not used.
717 MVS: The above appears to be true for the SH variants that do not
718 have an FPU, however those that have an FPU appear to copy the
719 aggregate argument onto the stack (and not place it in registers)
720 if it is larger than 16 bytes (four GP registers).
722 An exceptional case exists for struct arguments (and possibly other
723 aggregates such as arrays) if the size is larger than 4 bytes but
724 not a multiple of 4 bytes. In this case the argument is never split
725 between the registers and the stack, but instead is copied in its
726 entirety onto the stack, AND also copied into as many registers as
727 there is room for. In other words, space in registers permitting,
728 two copies of the same argument are passed in. As far as I can tell,
729 only the one on the stack is used, although that may be a function
730 of the level of compiler optimization. I suspect this is a compiler
731 bug. Arguments of these odd sizes are left-justified within the
732 word (as opposed to arguments smaller than 4 bytes, which are
735 If the function is to return an aggregate type such as a struct, it
736 is either returned in the normal return value register R0 (if its
737 size is no greater than one byte), or else the caller must allocate
738 space into which the callee will copy the return value (if the size
739 is greater than one byte). In this case, a pointer to the return
740 value location is passed into the callee in register R2, which does
741 not displace any of the other arguments passed in via registers R4
744 /* Helper function to justify value in register according to endianess. */
746 sh_justify_value_in_reg (struct value *val, int len)
748 static char valbuf[4];
750 memset (valbuf, 0, sizeof (valbuf));
753 /* value gets right-justified in the register or stack word */
754 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
755 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
757 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
760 return (char *) VALUE_CONTENTS (val);
763 /* Helper function to eval number of bytes to allocate on stack. */
765 sh_stack_allocsize (int nargs, struct value **args)
769 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
773 /* Helper functions for getting the float arguments right. Registers usage
774 depends on the ABI and the endianess. The comments should enlighten how
775 it's intended to work. */
777 /* This array stores which of the float arg registers are already in use. */
778 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
780 /* This function just resets the above array to "no reg used so far". */
782 sh_init_flt_argreg (void)
784 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
787 /* This function returns the next register to use for float arg passing.
788 It returns either a valid value between FLOAT_ARG0_REGNUM and
789 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
790 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
792 Note that register number 0 in flt_argreg_array corresponds with the
793 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
794 29) the parity of the register number is preserved, which is important
795 for the double register passing test (see the "argreg & 1" test below). */
797 sh_next_flt_argreg (int len)
801 /* First search for the next free register. */
802 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
804 if (!flt_argreg_array[argreg])
807 /* No register left? */
808 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
809 return FLOAT_ARGLAST_REGNUM + 1;
813 /* Doubles are always starting in a even register number. */
816 flt_argreg_array[argreg] = 1;
820 /* No register left? */
821 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
822 return FLOAT_ARGLAST_REGNUM + 1;
824 /* Also mark the next register as used. */
825 flt_argreg_array[argreg + 1] = 1;
827 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
829 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
830 if (!flt_argreg_array[argreg + 1])
833 flt_argreg_array[argreg] = 1;
834 return FLOAT_ARG0_REGNUM + argreg;
837 /* Helper function which figures out, if a type is treated like a float type.
839 The FPU ABIs have a special way how to treat types as float types.
840 Structures with exactly one member, which is of type float or double, are
841 treated exactly as the base types float or double:
851 are handled the same way as just
857 As a result, arguments of these struct types are pushed into floating point
858 registers exactly as floats or doubles, using the same decision algorithm.
860 The same is valid if these types are used as function return types. The
861 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
862 or even using struct convention as it is for other structs. */
865 sh_treat_as_flt_p (struct type *type)
867 int len = TYPE_LENGTH (type);
869 /* Ordinary float types are obviously treated as float. */
870 if (TYPE_CODE (type) == TYPE_CODE_FLT)
872 /* Otherwise non-struct types are not treated as float. */
873 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
875 /* Otherwise structs with more than one memeber are not treated as float. */
876 if (TYPE_NFIELDS (type) != 1)
878 /* Otherwise if the type of that member is float, the whole type is
880 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
882 /* Otherwise it's not treated as float. */
887 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
888 struct value *function,
889 struct regcache *regcache,
890 CORE_ADDR bp_addr, int nargs,
892 CORE_ADDR sp, int struct_return,
893 CORE_ADDR struct_addr)
895 int stack_offset = 0;
896 int argreg = ARG0_REGNUM;
902 int len, reg_size = 0;
903 int pass_on_stack = 0;
906 /* first force sp to a 4-byte alignment */
907 sp = sh_frame_align (gdbarch, sp);
910 regcache_cooked_write_unsigned (regcache,
911 STRUCT_RETURN_REGNUM, struct_addr);
913 /* make room on stack for args */
914 sp -= sh_stack_allocsize (nargs, args);
916 /* Initialize float argument mechanism. */
917 sh_init_flt_argreg ();
919 /* Now load as many as possible of the first arguments into
920 registers, and push the rest onto the stack. There are 16 bytes
921 in four registers available. Loop thru args from first to last. */
922 for (argnum = 0; argnum < nargs; argnum++)
924 type = VALUE_TYPE (args[argnum]);
925 len = TYPE_LENGTH (type);
926 val = sh_justify_value_in_reg (args[argnum], len);
928 /* Some decisions have to be made how various types are handled.
929 This also differs in different ABIs. */
932 /* Find out the next register to use for a floating point value. */
933 treat_as_flt = sh_treat_as_flt_p (type);
935 flt_argreg = sh_next_flt_argreg (len);
936 /* In contrast to non-FPU CPUs, arguments are never split between
937 registers and stack. If an argument doesn't fit in the remaining
938 registers it's always pushed entirely on the stack. */
939 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
944 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
945 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
948 /* The data goes entirely on the stack, 4-byte aligned. */
949 reg_size = (len + 3) & ~3;
950 write_memory (sp + stack_offset, val, reg_size);
951 stack_offset += reg_size;
953 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
955 /* Argument goes in a float argument register. */
956 reg_size = register_size (gdbarch, flt_argreg);
957 regval = extract_unsigned_integer (val, reg_size);
958 /* In little endian mode, float types taking two registers
959 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
960 be stored swapped in the argument registers. The below
961 code first writes the first 32 bits in the next but one
962 register, increments the val and len values accordingly
963 and then proceeds as normal by writing the second 32 bits
964 into the next register. */
965 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
966 && TYPE_LENGTH (type) == 2 * reg_size)
968 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
972 regval = extract_unsigned_integer (val, reg_size);
974 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
976 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
978 /* there's room in a register */
979 reg_size = register_size (gdbarch, argreg);
980 regval = extract_unsigned_integer (val, reg_size);
981 regcache_cooked_write_unsigned (regcache, argreg++, regval);
983 /* Store the value one register at a time or in one step on stack. */
989 /* Store return address. */
990 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
992 /* Update stack pointer. */
993 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
999 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1000 struct value *function,
1001 struct regcache *regcache,
1003 int nargs, struct value **args,
1004 CORE_ADDR sp, int struct_return,
1005 CORE_ADDR struct_addr)
1007 int stack_offset = 0;
1008 int argreg = ARG0_REGNUM;
1015 /* first force sp to a 4-byte alignment */
1016 sp = sh_frame_align (gdbarch, sp);
1019 regcache_cooked_write_unsigned (regcache,
1020 STRUCT_RETURN_REGNUM, struct_addr);
1022 /* make room on stack for args */
1023 sp -= sh_stack_allocsize (nargs, args);
1025 /* Now load as many as possible of the first arguments into
1026 registers, and push the rest onto the stack. There are 16 bytes
1027 in four registers available. Loop thru args from first to last. */
1028 for (argnum = 0; argnum < nargs; argnum++)
1030 type = VALUE_TYPE (args[argnum]);
1031 len = TYPE_LENGTH (type);
1032 val = sh_justify_value_in_reg (args[argnum], len);
1036 if (argreg > ARGLAST_REGNUM)
1038 /* The remainder of the data goes entirely on the stack,
1040 reg_size = (len + 3) & ~3;
1041 write_memory (sp + stack_offset, val, reg_size);
1042 stack_offset += reg_size;
1044 else if (argreg <= ARGLAST_REGNUM)
1046 /* there's room in a register */
1047 reg_size = register_size (gdbarch, argreg);
1048 regval = extract_unsigned_integer (val, reg_size);
1049 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1051 /* Store the value reg_size bytes at a time. This means that things
1052 larger than reg_size bytes may go partly in registers and partly
1059 /* Store return address. */
1060 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1062 /* Update stack pointer. */
1063 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1068 /* Find a function's return value in the appropriate registers (in
1069 regbuf), and copy it into valbuf. Extract from an array REGBUF
1070 containing the (raw) register state a function return value of type
1071 TYPE, and copy that, in virtual format, into VALBUF. */
1073 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1076 int len = TYPE_LENGTH (type);
1077 int return_register = R0_REGNUM;
1084 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1085 store_unsigned_integer (valbuf, len, c);
1089 int i, regnum = R0_REGNUM;
1090 for (i = 0; i < len; i += 4)
1091 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1094 error ("bad size for return value");
1098 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1101 if (sh_treat_as_flt_p (type))
1103 int len = TYPE_LENGTH (type);
1104 int i, regnum = FP0_REGNUM;
1105 for (i = 0; i < len; i += 4)
1106 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1107 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1109 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1112 sh_default_extract_return_value (type, regcache, valbuf);
1115 /* Write into appropriate registers a function return value
1116 of type TYPE, given in virtual format.
1117 If the architecture is sh4 or sh3e, store a function's return value
1118 in the R0 general register or in the FP0 floating point register,
1119 depending on the type of the return value. In all the other cases
1120 the result is stored in r0, left-justified. */
1122 sh_default_store_return_value (struct type *type, struct regcache *regcache,
1126 int len = TYPE_LENGTH (type);
1130 val = extract_unsigned_integer (valbuf, len);
1131 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1135 int i, regnum = R0_REGNUM;
1136 for (i = 0; i < len; i += 4)
1137 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1142 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1145 if (sh_treat_as_flt_p (type))
1147 int len = TYPE_LENGTH (type);
1148 int i, regnum = FP0_REGNUM;
1149 for (i = 0; i < len; i += 4)
1150 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1151 regcache_raw_write (regcache, regnum++,
1152 (char *) valbuf + len - 4 - i);
1154 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1157 sh_default_store_return_value (type, regcache, valbuf);
1160 /* Print the registers in a form similar to the E7000 */
1163 sh_generic_show_regs (void)
1165 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1166 paddr (read_register (PC_REGNUM)),
1167 (long) read_register (SR_REGNUM),
1168 (long) read_register (PR_REGNUM),
1169 (long) read_register (MACH_REGNUM),
1170 (long) read_register (MACL_REGNUM));
1172 printf_filtered ("GBR=%08lx VBR=%08lx",
1173 (long) read_register (GBR_REGNUM),
1174 (long) read_register (VBR_REGNUM));
1177 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1178 (long) read_register (0), (long) read_register (1),
1179 (long) read_register (2), (long) read_register (3),
1180 (long) read_register (4), (long) read_register (5),
1181 (long) read_register (6), (long) read_register (7));
1182 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1183 (long) read_register (8), (long) read_register (9),
1184 (long) read_register (10), (long) read_register (11),
1185 (long) read_register (12), (long) read_register (13),
1186 (long) read_register (14), (long) read_register (15));
1190 sh3_show_regs (void)
1192 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1193 paddr (read_register (PC_REGNUM)),
1194 (long) read_register (SR_REGNUM),
1195 (long) read_register (PR_REGNUM),
1196 (long) read_register (MACH_REGNUM),
1197 (long) read_register (MACL_REGNUM));
1199 printf_filtered ("GBR=%08lx VBR=%08lx",
1200 (long) read_register (GBR_REGNUM),
1201 (long) read_register (VBR_REGNUM));
1202 printf_filtered (" SSR=%08lx SPC=%08lx",
1203 (long) read_register (SSR_REGNUM),
1204 (long) read_register (SPC_REGNUM));
1207 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1208 (long) read_register (0), (long) read_register (1),
1209 (long) read_register (2), (long) read_register (3),
1210 (long) read_register (4), (long) read_register (5),
1211 (long) read_register (6), (long) read_register (7));
1212 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1213 (long) read_register (8), (long) read_register (9),
1214 (long) read_register (10), (long) read_register (11),
1215 (long) read_register (12), (long) read_register (13),
1216 (long) read_register (14), (long) read_register (15));
1221 sh2e_show_regs (void)
1223 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1224 paddr (read_register (PC_REGNUM)),
1225 (long) read_register (SR_REGNUM),
1226 (long) read_register (PR_REGNUM),
1227 (long) read_register (MACH_REGNUM),
1228 (long) read_register (MACL_REGNUM));
1230 printf_filtered ("GBR=%08lx VBR=%08lx",
1231 (long) read_register (GBR_REGNUM),
1232 (long) read_register (VBR_REGNUM));
1233 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1234 (long) read_register (FPUL_REGNUM),
1235 (long) read_register (FPSCR_REGNUM));
1238 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1239 (long) read_register (0), (long) read_register (1),
1240 (long) read_register (2), (long) read_register (3),
1241 (long) read_register (4), (long) read_register (5),
1242 (long) read_register (6), (long) read_register (7));
1243 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1244 (long) read_register (8), (long) read_register (9),
1245 (long) read_register (10), (long) read_register (11),
1246 (long) read_register (12), (long) read_register (13),
1247 (long) read_register (14), (long) read_register (15));
1249 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1250 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1254 sh3e_show_regs (void)
1256 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1257 paddr (read_register (PC_REGNUM)),
1258 (long) read_register (SR_REGNUM),
1259 (long) read_register (PR_REGNUM),
1260 (long) read_register (MACH_REGNUM),
1261 (long) read_register (MACL_REGNUM));
1263 printf_filtered ("GBR=%08lx VBR=%08lx",
1264 (long) read_register (GBR_REGNUM),
1265 (long) read_register (VBR_REGNUM));
1266 printf_filtered (" SSR=%08lx SPC=%08lx",
1267 (long) read_register (SSR_REGNUM),
1268 (long) read_register (SPC_REGNUM));
1269 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1270 (long) read_register (FPUL_REGNUM),
1271 (long) read_register (FPSCR_REGNUM));
1274 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1275 (long) read_register (0), (long) read_register (1),
1276 (long) read_register (2), (long) read_register (3),
1277 (long) read_register (4), (long) read_register (5),
1278 (long) read_register (6), (long) read_register (7));
1279 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1280 (long) read_register (8), (long) read_register (9),
1281 (long) read_register (10), (long) read_register (11),
1282 (long) read_register (12), (long) read_register (13),
1283 (long) read_register (14), (long) read_register (15));
1285 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1286 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1290 sh3_dsp_show_regs (void)
1292 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1293 paddr (read_register (PC_REGNUM)),
1294 (long) read_register (SR_REGNUM),
1295 (long) read_register (PR_REGNUM),
1296 (long) read_register (MACH_REGNUM),
1297 (long) read_register (MACL_REGNUM));
1299 printf_filtered ("GBR=%08lx VBR=%08lx",
1300 (long) read_register (GBR_REGNUM),
1301 (long) read_register (VBR_REGNUM));
1303 printf_filtered (" SSR=%08lx SPC=%08lx",
1304 (long) read_register (SSR_REGNUM),
1305 (long) read_register (SPC_REGNUM));
1307 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1310 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1311 (long) read_register (0), (long) read_register (1),
1312 (long) read_register (2), (long) read_register (3),
1313 (long) read_register (4), (long) read_register (5),
1314 (long) read_register (6), (long) read_register (7));
1315 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1316 (long) read_register (8), (long) read_register (9),
1317 (long) read_register (10), (long) read_register (11),
1318 (long) read_register (12), (long) read_register (13),
1319 (long) read_register (14), (long) read_register (15));
1322 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1323 (long) read_register (A0G_REGNUM) & 0xff,
1324 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1325 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1326 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1327 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1328 (long) read_register (A1G_REGNUM) & 0xff,
1329 (long) read_register (A1_REGNUM),
1330 (long) read_register (M1_REGNUM),
1331 (long) read_register (X1_REGNUM),
1332 (long) read_register (Y1_REGNUM),
1333 (long) read_register (RE_REGNUM));
1337 sh4_show_regs (void)
1339 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1340 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1341 paddr (read_register (PC_REGNUM)),
1342 (long) read_register (SR_REGNUM),
1343 (long) read_register (PR_REGNUM),
1344 (long) read_register (MACH_REGNUM),
1345 (long) read_register (MACL_REGNUM));
1347 printf_filtered ("GBR=%08lx VBR=%08lx",
1348 (long) read_register (GBR_REGNUM),
1349 (long) read_register (VBR_REGNUM));
1350 printf_filtered (" SSR=%08lx SPC=%08lx",
1351 (long) read_register (SSR_REGNUM),
1352 (long) read_register (SPC_REGNUM));
1353 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1354 (long) read_register (FPUL_REGNUM),
1355 (long) read_register (FPSCR_REGNUM));
1358 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1359 (long) read_register (0), (long) read_register (1),
1360 (long) read_register (2), (long) read_register (3),
1361 (long) read_register (4), (long) read_register (5),
1362 (long) read_register (6), (long) read_register (7));
1363 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1364 (long) read_register (8), (long) read_register (9),
1365 (long) read_register (10), (long) read_register (11),
1366 (long) read_register (12), (long) read_register (13),
1367 (long) read_register (14), (long) read_register (15));
1369 printf_filtered ((pr
1370 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1372 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1373 (long) read_register (FP0_REGNUM + 0),
1374 (long) read_register (FP0_REGNUM + 1),
1375 (long) read_register (FP0_REGNUM + 2),
1376 (long) read_register (FP0_REGNUM + 3),
1377 (long) read_register (FP0_REGNUM + 4),
1378 (long) read_register (FP0_REGNUM + 5),
1379 (long) read_register (FP0_REGNUM + 6),
1380 (long) read_register (FP0_REGNUM + 7));
1381 printf_filtered ((pr ?
1382 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1383 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1384 (long) read_register (FP0_REGNUM + 8),
1385 (long) read_register (FP0_REGNUM + 9),
1386 (long) read_register (FP0_REGNUM + 10),
1387 (long) read_register (FP0_REGNUM + 11),
1388 (long) read_register (FP0_REGNUM + 12),
1389 (long) read_register (FP0_REGNUM + 13),
1390 (long) read_register (FP0_REGNUM + 14),
1391 (long) read_register (FP0_REGNUM + 15));
1395 sh4_nofpu_show_regs (void)
1397 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1398 paddr (read_register (PC_REGNUM)),
1399 (long) read_register (SR_REGNUM),
1400 (long) read_register (PR_REGNUM),
1401 (long) read_register (MACH_REGNUM),
1402 (long) read_register (MACL_REGNUM));
1404 printf_filtered ("GBR=%08lx VBR=%08lx",
1405 (long) read_register (GBR_REGNUM),
1406 (long) read_register (VBR_REGNUM));
1407 printf_filtered (" SSR=%08lx SPC=%08lx",
1408 (long) read_register (SSR_REGNUM),
1409 (long) read_register (SPC_REGNUM));
1412 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1413 (long) read_register (0), (long) read_register (1),
1414 (long) read_register (2), (long) read_register (3),
1415 (long) read_register (4), (long) read_register (5),
1416 (long) read_register (6), (long) read_register (7));
1417 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1418 (long) read_register (8), (long) read_register (9),
1419 (long) read_register (10), (long) read_register (11),
1420 (long) read_register (12), (long) read_register (13),
1421 (long) read_register (14), (long) read_register (15));
1425 sh_dsp_show_regs (void)
1427 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1428 paddr (read_register (PC_REGNUM)),
1429 (long) read_register (SR_REGNUM),
1430 (long) read_register (PR_REGNUM),
1431 (long) read_register (MACH_REGNUM),
1432 (long) read_register (MACL_REGNUM));
1434 printf_filtered ("GBR=%08lx VBR=%08lx",
1435 (long) read_register (GBR_REGNUM),
1436 (long) read_register (VBR_REGNUM));
1438 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1441 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1442 (long) read_register (0), (long) read_register (1),
1443 (long) read_register (2), (long) read_register (3),
1444 (long) read_register (4), (long) read_register (5),
1445 (long) read_register (6), (long) read_register (7));
1446 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1447 (long) read_register (8), (long) read_register (9),
1448 (long) read_register (10), (long) read_register (11),
1449 (long) read_register (12), (long) read_register (13),
1450 (long) read_register (14), (long) read_register (15));
1453 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1454 (long) read_register (A0G_REGNUM) & 0xff,
1455 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1456 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1457 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1458 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1459 (long) read_register (A1G_REGNUM) & 0xff,
1460 (long) read_register (A1_REGNUM),
1461 (long) read_register (M1_REGNUM),
1462 (long) read_register (X1_REGNUM),
1463 (long) read_register (Y1_REGNUM),
1464 (long) read_register (RE_REGNUM));
1468 sh_show_regs_command (char *args, int from_tty)
1474 /* Return the GDB type object for the "standard" data type
1475 of data in register N. */
1476 static struct type *
1477 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1479 if ((reg_nr >= FP0_REGNUM
1480 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1481 return builtin_type_float;
1483 return builtin_type_int;
1486 static struct type *
1487 sh_sh4_build_float_register_type (int high)
1491 temp = create_range_type (NULL, builtin_type_int, 0, high);
1492 return create_array_type (NULL, builtin_type_float, temp);
1495 static struct type *
1496 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1498 if ((reg_nr >= FP0_REGNUM
1499 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1500 return builtin_type_float;
1501 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1502 return builtin_type_double;
1503 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1504 return sh_sh4_build_float_register_type (3);
1506 return builtin_type_int;
1509 static struct type *
1510 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1512 return builtin_type_int;
1515 /* On the sh4, the DRi pseudo registers are problematic if the target
1516 is little endian. When the user writes one of those registers, for
1517 instance with 'ser var $dr0=1', we want the double to be stored
1519 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1520 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1522 This corresponds to little endian byte order & big endian word
1523 order. However if we let gdb write the register w/o conversion, it
1524 will write fr0 and fr1 this way:
1525 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1526 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1527 because it will consider fr0 and fr1 as a single LE stretch of memory.
1529 To achieve what we want we must force gdb to store things in
1530 floatformat_ieee_double_littlebyte_bigword (which is defined in
1531 include/floatformat.h and libiberty/floatformat.c.
1533 In case the target is big endian, there is no problem, the
1534 raw bytes will look like:
1535 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1536 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1538 The other pseudo registers (the FVs) also don't pose a problem
1539 because they are stored as 4 individual FP elements. */
1542 sh_register_convert_to_virtual (int regnum, struct type *type,
1543 char *from, char *to)
1545 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1548 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1550 store_typed_floating (to, type, val);
1554 ("sh_register_convert_to_virtual called with non DR register number");
1558 sh_register_convert_to_raw (struct type *type, int regnum,
1559 const void *from, void *to)
1561 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1563 DOUBLEST val = extract_typed_floating (from, type);
1564 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1568 error ("sh_register_convert_to_raw called with non DR register number");
1571 /* For vectors of 4 floating point registers. */
1573 fv_reg_base_num (int fv_regnum)
1577 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1581 /* For double precision floating point registers, i.e 2 fp regs.*/
1583 dr_reg_base_num (int dr_regnum)
1587 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1592 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1593 int reg_nr, void *buffer)
1595 int base_regnum, portion;
1596 char temp_buffer[MAX_REGISTER_SIZE];
1598 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1600 base_regnum = dr_reg_base_num (reg_nr);
1602 /* Build the value in the provided buffer. */
1603 /* Read the real regs for which this one is an alias. */
1604 for (portion = 0; portion < 2; portion++)
1605 regcache_raw_read (regcache, base_regnum + portion,
1607 + register_size (gdbarch,
1608 base_regnum) * portion));
1609 /* We must pay attention to the endiannes. */
1610 sh_register_convert_to_virtual (reg_nr,
1611 gdbarch_register_type (gdbarch, reg_nr),
1612 temp_buffer, buffer);
1614 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1616 base_regnum = fv_reg_base_num (reg_nr);
1618 /* Read the real regs for which this one is an alias. */
1619 for (portion = 0; portion < 4; portion++)
1620 regcache_raw_read (regcache, base_regnum + portion,
1622 + register_size (gdbarch,
1623 base_regnum) * portion));
1628 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1629 int reg_nr, const void *buffer)
1631 int base_regnum, portion;
1632 char temp_buffer[MAX_REGISTER_SIZE];
1634 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1636 base_regnum = dr_reg_base_num (reg_nr);
1638 /* We must pay attention to the endiannes. */
1639 sh_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1640 reg_nr, buffer, temp_buffer);
1642 /* Write the real regs for which this one is an alias. */
1643 for (portion = 0; portion < 2; portion++)
1644 regcache_raw_write (regcache, base_regnum + portion,
1646 + register_size (gdbarch,
1647 base_regnum) * portion));
1649 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1651 base_regnum = fv_reg_base_num (reg_nr);
1653 /* Write the real regs for which this one is an alias. */
1654 for (portion = 0; portion < 4; portion++)
1655 regcache_raw_write (regcache, base_regnum + portion,
1657 + register_size (gdbarch,
1658 base_regnum) * portion));
1662 /* Floating point vector of 4 float registers. */
1664 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1667 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1668 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1669 fv_regnum - FV0_REGNUM,
1670 (int) read_register (first_fp_reg_num),
1671 (int) read_register (first_fp_reg_num + 1),
1672 (int) read_register (first_fp_reg_num + 2),
1673 (int) read_register (first_fp_reg_num + 3));
1676 /* Double precision registers. */
1678 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1681 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1683 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1684 dr_regnum - DR0_REGNUM,
1685 (int) read_register (first_fp_reg_num),
1686 (int) read_register (first_fp_reg_num + 1));
1690 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1693 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1694 internal_error (__FILE__, __LINE__,
1695 "Invalid pseudo register number %d\n", regnum);
1696 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1697 do_dr_register_info (gdbarch, file, regnum);
1698 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1699 do_fv_register_info (gdbarch, file, regnum);
1703 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1704 { /* do values for FP (float) regs */
1706 double flt; /* double extracted from raw hex data */
1710 /* Allocate space for the float. */
1711 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1713 /* Get the data in raw format. */
1714 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1715 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1717 /* Get the register as a number */
1718 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1720 /* Print the name and some spaces. */
1721 fputs_filtered (REGISTER_NAME (regnum), file);
1722 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1724 /* Print the value. */
1726 fprintf_filtered (file, "<invalid float>");
1728 fprintf_filtered (file, "%-10.9g", flt);
1730 /* Print the fp register as hex. */
1731 fprintf_filtered (file, "\t(raw 0x");
1732 for (j = 0; j < register_size (gdbarch, regnum); j++)
1734 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1736 : register_size (gdbarch, regnum) - 1 - j);
1737 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1739 fprintf_filtered (file, ")");
1740 fprintf_filtered (file, "\n");
1744 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1746 char raw_buffer[MAX_REGISTER_SIZE];
1748 fputs_filtered (REGISTER_NAME (regnum), file);
1749 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1751 /* Get the data in raw format. */
1752 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1753 fprintf_filtered (file, "*value not available*\n");
1755 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1756 file, 'x', 1, 0, Val_pretty_default);
1757 fprintf_filtered (file, "\t");
1758 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1759 file, 0, 1, 0, Val_pretty_default);
1760 fprintf_filtered (file, "\n");
1764 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1766 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1767 internal_error (__FILE__, __LINE__,
1768 "Invalid register number %d\n", regnum);
1770 else if (regnum >= 0 && regnum < NUM_REGS)
1772 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1774 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1776 sh_do_register (gdbarch, file, regnum); /* All other regs */
1779 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1781 sh_print_pseudo_register (gdbarch, file, regnum);
1786 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1787 struct frame_info *frame, int regnum, int fpregs)
1789 if (regnum != -1) /* do one specified register */
1791 if (*(REGISTER_NAME (regnum)) == '\0')
1792 error ("Not a valid register for the current processor type");
1794 sh_print_register (gdbarch, file, regnum);
1797 /* do all (or most) registers */
1799 for (regnum = 0; regnum < NUM_REGS; ++regnum)
1801 /* If the register name is empty, it is undefined for this
1802 processor, so don't display anything. */
1803 if (REGISTER_NAME (regnum) == NULL
1804 || *(REGISTER_NAME (regnum)) == '\0')
1807 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1810 /* true for "INFO ALL-REGISTERS" command */
1812 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1815 sh_do_register (gdbarch, file, regnum); /* All other regs */
1819 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1821 sh_print_pseudo_register (gdbarch, file, regnum);
1827 #ifdef SVR4_SHARED_LIBS
1829 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1830 for native i386 linux targets using the struct offsets defined in
1831 link.h (but without actual reference to that file).
1833 This makes it possible to access i386-linux shared libraries from
1834 a gdb that was not built on an i386-linux host (for cross debugging).
1837 struct link_map_offsets *
1838 sh_linux_svr4_fetch_link_map_offsets (void)
1840 static struct link_map_offsets lmo;
1841 static struct link_map_offsets *lmp = 0;
1847 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1849 lmo.r_map_offset = 4;
1852 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1854 lmo.l_addr_offset = 0;
1855 lmo.l_addr_size = 4;
1857 lmo.l_name_offset = 4;
1858 lmo.l_name_size = 4;
1860 lmo.l_next_offset = 12;
1861 lmo.l_next_size = 4;
1863 lmo.l_prev_offset = 16;
1864 lmo.l_prev_size = 4;
1869 #endif /* SVR4_SHARED_LIBS */
1872 sh_dsp_register_sim_regno (int nr)
1874 if (legacy_register_sim_regno (nr) < 0)
1875 return legacy_register_sim_regno (nr);
1876 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1877 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1878 if (nr == MOD_REGNUM)
1879 return SIM_SH_MOD_REGNUM;
1880 if (nr == RS_REGNUM)
1881 return SIM_SH_RS_REGNUM;
1882 if (nr == RE_REGNUM)
1883 return SIM_SH_RE_REGNUM;
1884 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
1885 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1889 static struct sh_frame_cache *
1890 sh_alloc_frame_cache (void)
1892 struct sh_frame_cache *cache;
1895 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1899 cache->saved_sp = 0;
1900 cache->sp_offset = 0;
1903 /* Frameless until proven otherwise. */
1906 /* Saved registers. We initialize these to -1 since zero is a valid
1907 offset (that's where fp is supposed to be stored). */
1908 for (i = 0; i < SH_NUM_REGS; i++)
1910 cache->saved_regs[i] = -1;
1916 static struct sh_frame_cache *
1917 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1919 struct sh_frame_cache *cache;
1920 CORE_ADDR current_pc;
1926 cache = sh_alloc_frame_cache ();
1927 *this_cache = cache;
1929 /* In principle, for normal frames, fp holds the frame pointer,
1930 which holds the base address for the current stack frame.
1931 However, for functions that don't need it, the frame pointer is
1932 optional. For these "frameless" functions the frame pointer is
1933 actually the frame pointer of the calling frame. */
1934 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1935 if (cache->base == 0)
1938 cache->pc = frame_func_unwind (next_frame);
1939 current_pc = frame_pc_unwind (next_frame);
1941 sh_analyze_prologue (cache->pc, current_pc, cache);
1943 if (!cache->uses_fp)
1945 /* We didn't find a valid frame, which means that CACHE->base
1946 currently holds the frame pointer for our calling frame. If
1947 we're at the start of a function, or somewhere half-way its
1948 prologue, the function's frame probably hasn't been fully
1949 setup yet. Try to reconstruct the base address for the stack
1950 frame by looking at the stack pointer. For truly "frameless"
1951 functions this might work too. */
1952 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1955 /* Now that we have the base address for the stack frame we can
1956 calculate the value of sp in the calling frame. */
1957 cache->saved_sp = cache->base + cache->sp_offset;
1959 /* Adjust all the saved registers such that they contain addresses
1960 instead of offsets. */
1961 for (i = 0; i < SH_NUM_REGS; i++)
1962 if (cache->saved_regs[i] != -1)
1963 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1969 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1970 int regnum, int *optimizedp,
1971 enum lval_type *lvalp, CORE_ADDR *addrp,
1972 int *realnump, void *valuep)
1974 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1976 gdb_assert (regnum >= 0);
1978 if (regnum == SP_REGNUM && cache->saved_sp)
1986 /* Store the value. */
1987 store_unsigned_integer (valuep, 4, cache->saved_sp);
1992 /* The PC of the previous frame is stored in the PR register of
1993 the current frame. Frob regnum so that we pull the value from
1994 the correct place. */
1995 if (regnum == PC_REGNUM)
1998 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2001 *lvalp = lval_memory;
2002 *addrp = cache->saved_regs[regnum];
2006 /* Read the value in from memory. */
2007 read_memory (*addrp, valuep,
2008 register_size (current_gdbarch, regnum));
2013 frame_register_unwind (next_frame, regnum,
2014 optimizedp, lvalp, addrp, realnump, valuep);
2018 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2019 struct frame_id *this_id)
2021 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2023 /* This marks the outermost frame. */
2024 if (cache->base == 0)
2027 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2030 static const struct frame_unwind sh_frame_unwind = {
2033 sh_frame_prev_register
2036 static const struct frame_unwind *
2037 sh_frame_sniffer (struct frame_info *next_frame)
2039 return &sh_frame_unwind;
2043 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2045 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2049 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2051 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2054 static struct frame_id
2055 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2057 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2058 frame_pc_unwind (next_frame));
2062 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2064 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2069 static const struct frame_base sh_frame_base = {
2071 sh_frame_base_address,
2072 sh_frame_base_address,
2073 sh_frame_base_address
2076 /* The epilogue is defined here as the area at the end of a function,
2077 either on the `ret' instruction itself or after an instruction which
2078 destroys the function's stack frame. */
2080 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2082 CORE_ADDR func_addr = 0, func_end = 0;
2084 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2087 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2088 for a nop and some fixed data (e.g. big offsets) which are
2089 unfortunately also treated as part of the function (which
2090 means, they are below func_end. */
2091 CORE_ADDR addr = func_end - 28;
2092 if (addr < func_addr + 4)
2093 addr = func_addr + 4;
2097 /* First search forward until hitting an rts. */
2098 while (addr < func_end
2099 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2101 if (addr >= func_end)
2104 /* At this point we should find a mov.l @r15+,r14 instruction,
2105 either before or after the rts. If not, then the function has
2106 probably no "normal" epilogue and we bail out here. */
2107 inst = read_memory_unsigned_integer (addr - 2, 2);
2108 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2110 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2113 /* Step over possible lds.l @r15+,pr. */
2114 inst = read_memory_unsigned_integer (addr - 2, 2);
2118 inst = read_memory_unsigned_integer (addr - 2, 2);
2121 /* Step over possible mov r14,r15. */
2122 if (IS_MOV_FP_SP (inst))
2125 inst = read_memory_unsigned_integer (addr - 2, 2);
2128 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2130 while (addr > func_addr + 4
2131 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2134 inst = read_memory_unsigned_integer (addr - 2, 2);
2143 static gdbarch_init_ftype sh_gdbarch_init;
2145 static struct gdbarch *
2146 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2148 struct gdbarch *gdbarch;
2150 sh_show_regs = sh_generic_show_regs;
2151 switch (info.bfd_arch_info->mach)
2154 sh_show_regs = sh2e_show_regs;
2156 case bfd_mach_sh_dsp:
2157 sh_show_regs = sh_dsp_show_regs;
2161 sh_show_regs = sh3_show_regs;
2165 sh_show_regs = sh3e_show_regs;
2168 case bfd_mach_sh3_dsp:
2169 case bfd_mach_sh4al_dsp:
2170 sh_show_regs = sh3_dsp_show_regs;
2175 sh_show_regs = sh4_show_regs;
2178 case bfd_mach_sh4_nofpu:
2179 case bfd_mach_sh4a_nofpu:
2180 sh_show_regs = sh4_nofpu_show_regs;
2185 sh_show_regs = sh64_show_regs;
2186 /* SH5 is handled entirely in sh64-tdep.c */
2187 return sh64_gdbarch_init (info, arches);
2191 /* If there is already a candidate, use it. */
2192 arches = gdbarch_list_lookup_by_info (arches, &info);
2194 return arches->gdbarch;
2196 /* None found, create a new architecture from the information
2198 gdbarch = gdbarch_alloc (&info, NULL);
2200 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2201 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2202 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2203 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2204 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2205 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2206 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2207 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2209 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2210 set_gdbarch_sp_regnum (gdbarch, 15);
2211 set_gdbarch_pc_regnum (gdbarch, 16);
2212 set_gdbarch_fp0_regnum (gdbarch, -1);
2213 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2215 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2217 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2219 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2220 set_gdbarch_deprecated_use_struct_convention (gdbarch, sh_use_struct_convention);
2222 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2223 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2225 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2227 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2228 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2229 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2231 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2232 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2234 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2236 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2238 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2239 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2240 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2241 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2242 frame_base_set_default (gdbarch, &sh_frame_base);
2244 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2246 switch (info.bfd_arch_info->mach)
2249 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2253 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2257 /* doubles on sh2e and sh3e are actually 4 byte. */
2258 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2260 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2261 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2262 set_gdbarch_fp0_regnum (gdbarch, 25);
2263 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2264 set_gdbarch_extract_return_value (gdbarch,
2265 sh3e_sh4_extract_return_value);
2266 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2269 case bfd_mach_sh_dsp:
2270 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2271 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2275 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2279 /* doubles on sh2e and sh3e are actually 4 byte. */
2280 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2282 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2283 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2284 set_gdbarch_fp0_regnum (gdbarch, 25);
2285 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2286 set_gdbarch_extract_return_value (gdbarch,
2287 sh3e_sh4_extract_return_value);
2288 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2291 case bfd_mach_sh3_dsp:
2292 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2293 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2298 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2299 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2300 set_gdbarch_fp0_regnum (gdbarch, 25);
2301 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2302 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2303 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2304 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2305 set_gdbarch_extract_return_value (gdbarch,
2306 sh3e_sh4_extract_return_value);
2307 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2310 case bfd_mach_sh4_nofpu:
2311 case bfd_mach_sh4a_nofpu:
2312 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2315 case bfd_mach_sh4al_dsp:
2316 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2317 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2321 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2325 /* Hook in ABI-specific overrides, if they have been registered. */
2326 gdbarch_init_osabi (info, gdbarch);
2328 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2329 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2334 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2337 _initialize_sh_tdep (void)
2339 struct cmd_list_element *c;
2341 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2343 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");