1 /* Target-dependent code for Renesas Super-H, for GDB.
3 Copyright (C) 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
4 2003, 2004, 2005, 2007, 2008, 2009 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 Contributed by Steve Chamberlain
28 #include "frame-base.h"
29 #include "frame-unwind.h"
30 #include "dwarf2-frame.h"
38 #include "gdb_string.h"
39 #include "gdb_assert.h"
40 #include "arch-utils.h"
41 #include "floatformat.h"
45 #include "reggroups.h"
50 #include "solib-svr4.h"
55 /* registers numbers shared with the simulator */
56 #include "gdb/sim-sh.h"
58 /* List of "set sh ..." and "show sh ..." commands. */
59 static struct cmd_list_element *setshcmdlist = NULL;
60 static struct cmd_list_element *showshcmdlist = NULL;
62 static const char sh_cc_gcc[] = "gcc";
63 static const char sh_cc_renesas[] = "renesas";
64 static const char *sh_cc_enum[] = {
70 static const char *sh_active_calling_convention = sh_cc_gcc;
72 static void (*sh_show_regs) (struct frame_info *);
74 #define SH_NUM_REGS 67
83 /* Flag showing that a frame has been created in the prologue code. */
86 /* Saved registers. */
87 CORE_ADDR saved_regs[SH_NUM_REGS];
92 sh_is_renesas_calling_convention (struct type *func_type)
95 && TYPE_CALLING_CONVENTION (func_type) == DW_CC_GNU_renesas_sh)
96 || sh_active_calling_convention == sh_cc_renesas);
100 sh_sh_register_name (struct gdbarch *gdbarch, int reg_nr)
102 static char *register_names[] = {
103 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
104 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
105 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
107 "", "", "", "", "", "", "", "",
108 "", "", "", "", "", "", "", "",
110 "", "", "", "", "", "", "", "",
111 "", "", "", "", "", "", "", "",
112 "", "", "", "", "", "", "", "",
116 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
118 return register_names[reg_nr];
122 sh_sh3_register_name (struct gdbarch *gdbarch, int reg_nr)
124 static char *register_names[] = {
125 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
126 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
127 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
129 "", "", "", "", "", "", "", "",
130 "", "", "", "", "", "", "", "",
132 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
133 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
134 "", "", "", "", "", "", "", "",
138 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
140 return register_names[reg_nr];
144 sh_sh3e_register_name (struct gdbarch *gdbarch, int reg_nr)
146 static char *register_names[] = {
147 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
148 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
149 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
151 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
152 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
154 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
155 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
156 "", "", "", "", "", "", "", "",
160 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
162 return register_names[reg_nr];
166 sh_sh2e_register_name (struct gdbarch *gdbarch, int reg_nr)
168 static char *register_names[] = {
169 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
170 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
171 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
173 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
174 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
176 "", "", "", "", "", "", "", "",
177 "", "", "", "", "", "", "", "",
178 "", "", "", "", "", "", "", "",
182 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
184 return register_names[reg_nr];
188 sh_sh2a_register_name (struct gdbarch *gdbarch, int reg_nr)
190 static char *register_names[] = {
191 /* general registers 0-15 */
192 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
193 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
195 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
198 /* floating point registers 25 - 40 */
199 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
200 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
203 /* 43 - 62. Banked registers. The bank number used is determined by
204 the bank register (63). */
205 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
206 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
207 "machb", "ivnb", "prb", "gbrb", "maclb",
208 /* 63: register bank number, not a real register but used to
209 communicate the register bank currently get/set. This register
210 is hidden to the user, who manipulates it using the pseudo
211 register called "bank" (67). See below. */
214 "ibcr", "ibnr", "tbr",
215 /* 67: register bank number, the user visible pseudo register. */
217 /* double precision (pseudo) 68 - 75 */
218 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
222 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
224 return register_names[reg_nr];
228 sh_sh2a_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
230 static char *register_names[] = {
231 /* general registers 0-15 */
232 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
233 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
235 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
238 /* floating point registers 25 - 40 */
239 "", "", "", "", "", "", "", "",
240 "", "", "", "", "", "", "", "",
243 /* 43 - 62. Banked registers. The bank number used is determined by
244 the bank register (63). */
245 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
246 "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b",
247 "machb", "ivnb", "prb", "gbrb", "maclb",
248 /* 63: register bank number, not a real register but used to
249 communicate the register bank currently get/set. This register
250 is hidden to the user, who manipulates it using the pseudo
251 register called "bank" (67). See below. */
254 "ibcr", "ibnr", "tbr",
255 /* 67: register bank number, the user visible pseudo register. */
257 /* double precision (pseudo) 68 - 75 */
258 "", "", "", "", "", "", "", "",
262 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
264 return register_names[reg_nr];
268 sh_sh_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
270 static char *register_names[] = {
271 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
272 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
273 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
275 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
276 "y0", "y1", "", "", "", "", "", "mod",
278 "rs", "re", "", "", "", "", "", "",
279 "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "",
284 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
286 return register_names[reg_nr];
290 sh_sh3_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
292 static char *register_names[] = {
293 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
294 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
295 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
297 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
298 "y0", "y1", "", "", "", "", "", "mod",
300 "rs", "re", "", "", "", "", "", "",
301 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
302 "", "", "", "", "", "", "", "",
303 "", "", "", "", "", "", "", "",
307 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
309 return register_names[reg_nr];
313 sh_sh4_register_name (struct gdbarch *gdbarch, int reg_nr)
315 static char *register_names[] = {
316 /* general registers 0-15 */
317 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
318 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
320 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
323 /* floating point registers 25 - 40 */
324 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
325 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
329 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
331 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
332 "", "", "", "", "", "", "", "",
333 /* pseudo bank register. */
335 /* double precision (pseudo) 59 - 66 */
336 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
337 /* vectors (pseudo) 67 - 70 */
338 "fv0", "fv4", "fv8", "fv12",
339 /* FIXME: missing XF 71 - 86 */
340 /* FIXME: missing XD 87 - 94 */
344 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
346 return register_names[reg_nr];
350 sh_sh4_nofpu_register_name (struct gdbarch *gdbarch, int reg_nr)
352 static char *register_names[] = {
353 /* general registers 0-15 */
354 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
355 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
357 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
360 /* floating point registers 25 - 40 -- not for nofpu target */
361 "", "", "", "", "", "", "", "",
362 "", "", "", "", "", "", "", "",
366 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
368 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
369 "", "", "", "", "", "", "", "",
370 /* pseudo bank register. */
372 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
373 "", "", "", "", "", "", "", "",
374 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
379 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
381 return register_names[reg_nr];
385 sh_sh4al_dsp_register_name (struct gdbarch *gdbarch, int reg_nr)
387 static char *register_names[] = {
388 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
389 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
390 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
392 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
393 "y0", "y1", "", "", "", "", "", "mod",
395 "rs", "re", "", "", "", "", "", "",
396 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
397 "", "", "", "", "", "", "", "",
398 "", "", "", "", "", "", "", "",
402 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
404 return register_names[reg_nr];
407 static const unsigned char *
408 sh_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr, int *lenptr)
410 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
411 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
413 /* For remote stub targets, trapa #20 is used. */
414 if (strcmp (target_shortname, "remote") == 0)
416 static unsigned char big_remote_breakpoint[] = { 0xc3, 0x20 };
417 static unsigned char little_remote_breakpoint[] = { 0x20, 0xc3 };
419 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
421 *lenptr = sizeof (big_remote_breakpoint);
422 return big_remote_breakpoint;
426 *lenptr = sizeof (little_remote_breakpoint);
427 return little_remote_breakpoint;
431 *lenptr = sizeof (breakpoint);
435 /* Prologue looks like
439 sub <room_for_loca_vars>,r15
442 Actually it can be more complicated than this but that's it, basically.
445 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
446 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
448 /* JSR @Rm 0100mmmm00001011 */
449 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
451 /* STS.L PR,@-r15 0100111100100010
452 r15-4-->r15, PR-->(r15) */
453 #define IS_STS(x) ((x) == 0x4f22)
455 /* STS.L MACL,@-r15 0100111100010010
456 r15-4-->r15, MACL-->(r15) */
457 #define IS_MACL_STS(x) ((x) == 0x4f12)
459 /* MOV.L Rm,@-r15 00101111mmmm0110
460 r15-4-->r15, Rm-->(R15) */
461 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
463 /* MOV r15,r14 0110111011110011
465 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
467 /* ADD #imm,r15 01111111iiiiiiii
469 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
471 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
472 #define IS_SHLL_R3(x) ((x) == 0x4300)
474 /* ADD r3,r15 0011111100111100
476 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
478 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
479 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
480 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
481 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
482 make this entirely clear. */
483 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
484 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
486 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
487 #define IS_MOV_ARG_TO_REG(x) \
488 (((x) & 0xf00f) == 0x6003 && \
489 ((x) & 0x00f0) >= 0x0040 && \
490 ((x) & 0x00f0) <= 0x0070)
491 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
492 #define IS_MOV_ARG_TO_IND_R14(x) \
493 (((x) & 0xff0f) == 0x2e02 && \
494 ((x) & 0x00f0) >= 0x0040 && \
495 ((x) & 0x00f0) <= 0x0070)
496 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
497 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
498 (((x) & 0xff00) == 0x1e00 && \
499 ((x) & 0x00f0) >= 0x0040 && \
500 ((x) & 0x00f0) <= 0x0070)
502 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
503 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
504 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
505 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
506 /* MOVI20 #imm20,Rn 0000nnnniiii0000 */
507 #define IS_MOVI20(x) (((x) & 0xf00f) == 0x0000)
508 /* SUB Rn,R15 00111111nnnn1000 */
509 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
511 #define FPSCR_SZ (1 << 20)
513 /* The following instructions are used for epilogue testing. */
514 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
515 #define IS_RTS(x) ((x) == 0x000b)
516 #define IS_LDS(x) ((x) == 0x4f26)
517 #define IS_MACL_LDS(x) ((x) == 0x4f16)
518 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
519 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
520 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
523 sh_analyze_prologue (struct gdbarch *gdbarch,
524 CORE_ADDR pc, CORE_ADDR current_pc,
525 struct sh_frame_cache *cache, ULONGEST fpscr)
527 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
533 int reg, sav_reg = -1;
535 if (pc >= current_pc)
539 for (opc = pc + (2 * 28); pc < opc; pc += 2)
541 inst = read_memory_unsigned_integer (pc, 2, byte_order);
542 /* See where the registers will be saved to */
545 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
546 cache->sp_offset += 4;
548 else if (IS_STS (inst))
550 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
551 cache->sp_offset += 4;
553 else if (IS_MACL_STS (inst))
555 cache->saved_regs[MACL_REGNUM] = cache->sp_offset;
556 cache->sp_offset += 4;
558 else if (IS_MOV_R3 (inst))
560 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
562 else if (IS_SHLL_R3 (inst))
566 else if (IS_ADD_R3SP (inst))
568 cache->sp_offset += -r3_val;
570 else if (IS_ADD_IMM_SP (inst))
572 offset = ((inst & 0xff) ^ 0x80) - 0x80;
573 cache->sp_offset -= offset;
575 else if (IS_MOVW_PCREL_TO_REG (inst))
579 reg = GET_TARGET_REG (inst);
583 offset = (inst & 0xff) << 1;
585 read_memory_integer ((pc + 4) + offset, 2, byte_order);
589 else if (IS_MOVL_PCREL_TO_REG (inst))
593 reg = GET_TARGET_REG (inst);
597 offset = (inst & 0xff) << 2;
599 read_memory_integer (((pc & 0xfffffffc) + 4) + offset,
604 else if (IS_MOVI20 (inst))
608 reg = GET_TARGET_REG (inst);
612 sav_offset = GET_SOURCE_REG (inst) << 16;
613 /* MOVI20 is a 32 bit instruction! */
616 |= read_memory_unsigned_integer (pc, 2, byte_order);
617 /* Now sav_offset contains an unsigned 20 bit value.
618 It must still get sign extended. */
619 if (sav_offset & 0x00080000)
620 sav_offset |= 0xfff00000;
624 else if (IS_SUB_REG_FROM_SP (inst))
626 reg = GET_SOURCE_REG (inst);
627 if (sav_reg > 0 && reg == sav_reg)
631 cache->sp_offset += sav_offset;
633 else if (IS_FPUSH (inst))
635 if (fpscr & FPSCR_SZ)
637 cache->sp_offset += 8;
641 cache->sp_offset += 4;
644 else if (IS_MOV_SP_FP (inst))
647 /* At this point, only allow argument register moves to other
648 registers or argument register moves to @(X,fp) which are
649 moving the register arguments onto the stack area allocated
650 by a former add somenumber to SP call. Don't allow moving
651 to an fp indirect address above fp + cache->sp_offset. */
653 for (opc = pc + 12; pc < opc; pc += 2)
655 inst = read_memory_integer (pc, 2, byte_order);
656 if (IS_MOV_ARG_TO_IND_R14 (inst))
658 reg = GET_SOURCE_REG (inst);
659 if (cache->sp_offset > 0)
660 cache->saved_regs[reg] = cache->sp_offset;
662 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
664 reg = GET_SOURCE_REG (inst);
665 offset = (inst & 0xf) * 4;
666 if (cache->sp_offset > offset)
667 cache->saved_regs[reg] = cache->sp_offset - offset;
669 else if (IS_MOV_ARG_TO_REG (inst))
676 else if (IS_JSR (inst))
678 /* We have found a jsr that has been scheduled into the prologue.
679 If we continue the scan and return a pc someplace after this,
680 then setting a breakpoint on this function will cause it to
681 appear to be called after the function it is calling via the
682 jsr, which will be very confusing. Most likely the next
683 instruction is going to be IS_MOV_SP_FP in the delay slot. If
684 so, note that before returning the current pc. */
685 inst = read_memory_integer (pc + 2, 2, byte_order);
686 if (IS_MOV_SP_FP (inst))
690 #if 0 /* This used to just stop when it found an instruction that
691 was not considered part of the prologue. Now, we just
692 keep going looking for likely instructions. */
701 /* Skip any prologue before the guts of a function */
703 /* Skip the prologue using the debug information. If this fails we'll
704 fall back on the 'guess' method below. */
706 after_prologue (CORE_ADDR pc)
708 struct symtab_and_line sal;
709 CORE_ADDR func_addr, func_end;
711 /* If we can not find the symbol in the partial symbol table, then
712 there is no hope we can determine the function's start address
714 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
717 /* Get the line associated with FUNC_ADDR. */
718 sal = find_pc_line (func_addr, 0);
720 /* There are only two cases to consider. First, the end of the source line
721 is within the function bounds. In that case we return the end of the
722 source line. Second is the end of the source line extends beyond the
723 bounds of the current function. We need to use the slow code to
724 examine instructions in that case. */
725 if (sal.end < func_end)
732 sh_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
735 struct sh_frame_cache cache;
737 /* See if we can determine the end of the prologue via the symbol table.
738 If so, then return either PC, or the PC after the prologue, whichever
740 pc = after_prologue (start_pc);
742 /* If after_prologue returned a useful address, then use it. Else
743 fall back on the instruction skipping code. */
745 return max (pc, start_pc);
747 cache.sp_offset = -4;
748 pc = sh_analyze_prologue (gdbarch, start_pc, (CORE_ADDR) -1, &cache, 0);
757 Aggregate types not bigger than 8 bytes that have the same size and
758 alignment as one of the integer scalar types are returned in the
759 same registers as the integer type they match.
761 For example, a 2-byte aligned structure with size 2 bytes has the
762 same size and alignment as a short int, and will be returned in R0.
763 A 4-byte aligned structure with size 8 bytes has the same size and
764 alignment as a long long int, and will be returned in R0 and R1.
766 When an aggregate type is returned in R0 and R1, R0 contains the
767 first four bytes of the aggregate, and R1 contains the
768 remainder. If the size of the aggregate type is not a multiple of 4
769 bytes, the aggregate is tail-padded up to a multiple of 4
770 bytes. The value of the padding is undefined. For little-endian
771 targets the padding will appear at the most significant end of the
772 last element, for big-endian targets the padding appears at the
773 least significant end of the last element.
775 All other aggregate types are returned by address. The caller
776 function passes the address of an area large enough to hold the
777 aggregate value in R2. The called function stores the result in
780 To reiterate, structs smaller than 8 bytes could also be returned
781 in memory, if they don't pass the "same size and alignment as an
786 struct s { char c[3]; } wibble;
787 struct s foo(void) { return wibble; }
789 the return value from foo() will be in memory, not
790 in R0, because there is no 3-byte integer type.
794 struct s { char c[2]; } wibble;
795 struct s foo(void) { return wibble; }
797 because a struct containing two chars has alignment 1, that matches
798 type char, but size 2, that matches type short. There's no integer
799 type that has alignment 1 and size 2, so the struct is returned in
805 sh_use_struct_convention (int renesas_abi, struct type *type)
807 int len = TYPE_LENGTH (type);
808 int nelem = TYPE_NFIELDS (type);
810 /* The Renesas ABI returns aggregate types always on stack. */
811 if (renesas_abi && (TYPE_CODE (type) == TYPE_CODE_STRUCT
812 || TYPE_CODE (type) == TYPE_CODE_UNION))
815 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
816 fit in two registers anyway) use struct convention. */
817 if (len != 1 && len != 2 && len != 4 && len != 8)
820 /* Scalar types and aggregate types with exactly one field are aligned
821 by definition. They are returned in registers. */
825 /* If the first field in the aggregate has the same length as the entire
826 aggregate type, the type is returned in registers. */
827 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
830 /* If the size of the aggregate is 8 bytes and the first field is
831 of size 4 bytes its alignment is equal to long long's alignment,
832 so it's returned in registers. */
833 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
836 /* Otherwise use struct convention. */
841 sh_use_struct_convention_nofpu (int renesas_abi, struct type *type)
843 /* The Renesas ABI returns long longs/doubles etc. always on stack. */
844 if (renesas_abi && TYPE_NFIELDS (type) == 0 && TYPE_LENGTH (type) >= 8)
846 return sh_use_struct_convention (renesas_abi, type);
850 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
855 /* Function: push_dummy_call (formerly push_arguments)
856 Setup the function arguments for calling a function in the inferior.
858 On the Renesas SH architecture, there are four registers (R4 to R7)
859 which are dedicated for passing function arguments. Up to the first
860 four arguments (depending on size) may go into these registers.
861 The rest go on the stack.
863 MVS: Except on SH variants that have floating point registers.
864 In that case, float and double arguments are passed in the same
865 manner, but using FP registers instead of GP registers.
867 Arguments that are smaller than 4 bytes will still take up a whole
868 register or a whole 32-bit word on the stack, and will be
869 right-justified in the register or the stack word. This includes
870 chars, shorts, and small aggregate types.
872 Arguments that are larger than 4 bytes may be split between two or
873 more registers. If there are not enough registers free, an argument
874 may be passed partly in a register (or registers), and partly on the
875 stack. This includes doubles, long longs, and larger aggregates.
876 As far as I know, there is no upper limit to the size of aggregates
877 that will be passed in this way; in other words, the convention of
878 passing a pointer to a large aggregate instead of a copy is not used.
880 MVS: The above appears to be true for the SH variants that do not
881 have an FPU, however those that have an FPU appear to copy the
882 aggregate argument onto the stack (and not place it in registers)
883 if it is larger than 16 bytes (four GP registers).
885 An exceptional case exists for struct arguments (and possibly other
886 aggregates such as arrays) if the size is larger than 4 bytes but
887 not a multiple of 4 bytes. In this case the argument is never split
888 between the registers and the stack, but instead is copied in its
889 entirety onto the stack, AND also copied into as many registers as
890 there is room for. In other words, space in registers permitting,
891 two copies of the same argument are passed in. As far as I can tell,
892 only the one on the stack is used, although that may be a function
893 of the level of compiler optimization. I suspect this is a compiler
894 bug. Arguments of these odd sizes are left-justified within the
895 word (as opposed to arguments smaller than 4 bytes, which are
898 If the function is to return an aggregate type such as a struct, it
899 is either returned in the normal return value register R0 (if its
900 size is no greater than one byte), or else the caller must allocate
901 space into which the callee will copy the return value (if the size
902 is greater than one byte). In this case, a pointer to the return
903 value location is passed into the callee in register R2, which does
904 not displace any of the other arguments passed in via registers R4
907 /* Helper function to justify value in register according to endianess. */
909 sh_justify_value_in_reg (struct gdbarch *gdbarch, struct value *val, int len)
911 static char valbuf[4];
913 memset (valbuf, 0, sizeof (valbuf));
916 /* value gets right-justified in the register or stack word */
917 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
918 memcpy (valbuf + (4 - len), (char *) value_contents (val), len);
920 memcpy (valbuf, (char *) value_contents (val), len);
923 return (char *) value_contents (val);
926 /* Helper function to eval number of bytes to allocate on stack. */
928 sh_stack_allocsize (int nargs, struct value **args)
932 stack_alloc += ((TYPE_LENGTH (value_type (args[nargs])) + 3) & ~3);
936 /* Helper functions for getting the float arguments right. Registers usage
937 depends on the ABI and the endianess. The comments should enlighten how
938 it's intended to work. */
940 /* This array stores which of the float arg registers are already in use. */
941 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
943 /* This function just resets the above array to "no reg used so far". */
945 sh_init_flt_argreg (void)
947 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
950 /* This function returns the next register to use for float arg passing.
951 It returns either a valid value between FLOAT_ARG0_REGNUM and
952 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
953 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
955 Note that register number 0 in flt_argreg_array corresponds with the
956 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
957 29) the parity of the register number is preserved, which is important
958 for the double register passing test (see the "argreg & 1" test below). */
960 sh_next_flt_argreg (struct gdbarch *gdbarch, int len, struct type *func_type)
964 /* First search for the next free register. */
965 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
967 if (!flt_argreg_array[argreg])
970 /* No register left? */
971 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
972 return FLOAT_ARGLAST_REGNUM + 1;
976 /* Doubles are always starting in a even register number. */
979 /* In gcc ABI, the skipped register is lost for further argument
980 passing now. Not so in Renesas ABI. */
981 if (!sh_is_renesas_calling_convention (func_type))
982 flt_argreg_array[argreg] = 1;
986 /* No register left? */
987 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
988 return FLOAT_ARGLAST_REGNUM + 1;
990 /* Also mark the next register as used. */
991 flt_argreg_array[argreg + 1] = 1;
993 else if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
994 && !sh_is_renesas_calling_convention (func_type))
996 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
997 if (!flt_argreg_array[argreg + 1])
1000 flt_argreg_array[argreg] = 1;
1001 return FLOAT_ARG0_REGNUM + argreg;
1004 /* Helper function which figures out, if a type is treated like a float type.
1006 The FPU ABIs have a special way how to treat types as float types.
1007 Structures with exactly one member, which is of type float or double, are
1008 treated exactly as the base types float or double:
1018 are handled the same way as just
1024 As a result, arguments of these struct types are pushed into floating point
1025 registers exactly as floats or doubles, using the same decision algorithm.
1027 The same is valid if these types are used as function return types. The
1028 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
1029 or even using struct convention as it is for other structs. */
1032 sh_treat_as_flt_p (struct type *type)
1034 int len = TYPE_LENGTH (type);
1036 /* Ordinary float types are obviously treated as float. */
1037 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1039 /* Otherwise non-struct types are not treated as float. */
1040 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
1042 /* Otherwise structs with more than one memeber are not treated as float. */
1043 if (TYPE_NFIELDS (type) != 1)
1045 /* Otherwise if the type of that member is float, the whole type is
1046 treated as float. */
1047 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
1049 /* Otherwise it's not treated as float. */
1054 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
1055 struct value *function,
1056 struct regcache *regcache,
1057 CORE_ADDR bp_addr, int nargs,
1058 struct value **args,
1059 CORE_ADDR sp, int struct_return,
1060 CORE_ADDR struct_addr)
1062 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1063 int stack_offset = 0;
1064 int argreg = ARG0_REGNUM;
1067 struct type *func_type = value_type (function);
1071 int len, reg_size = 0;
1072 int pass_on_stack = 0;
1074 int last_reg_arg = INT_MAX;
1076 /* The Renesas ABI expects all varargs arguments, plus the last
1077 non-vararg argument to be on the stack, no matter how many
1078 registers have been used so far. */
1079 if (sh_is_renesas_calling_convention (func_type)
1080 && TYPE_VARARGS (func_type))
1081 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1083 /* first force sp to a 4-byte alignment */
1084 sp = sh_frame_align (gdbarch, sp);
1086 /* make room on stack for args */
1087 sp -= sh_stack_allocsize (nargs, args);
1089 /* Initialize float argument mechanism. */
1090 sh_init_flt_argreg ();
1092 /* Now load as many as possible of the first arguments into
1093 registers, and push the rest onto the stack. There are 16 bytes
1094 in four registers available. Loop thru args from first to last. */
1095 for (argnum = 0; argnum < nargs; argnum++)
1097 type = value_type (args[argnum]);
1098 len = TYPE_LENGTH (type);
1099 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1101 /* Some decisions have to be made how various types are handled.
1102 This also differs in different ABIs. */
1105 /* Find out the next register to use for a floating point value. */
1106 treat_as_flt = sh_treat_as_flt_p (type);
1108 flt_argreg = sh_next_flt_argreg (gdbarch, len, func_type);
1109 /* In Renesas ABI, long longs and aggregate types are always passed
1111 else if (sh_is_renesas_calling_convention (func_type)
1112 && ((TYPE_CODE (type) == TYPE_CODE_INT && len == 8)
1113 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1114 || TYPE_CODE (type) == TYPE_CODE_UNION))
1116 /* In contrast to non-FPU CPUs, arguments are never split between
1117 registers and stack. If an argument doesn't fit in the remaining
1118 registers it's always pushed entirely on the stack. */
1119 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
1124 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
1125 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
1127 || argnum > last_reg_arg)
1129 /* The data goes entirely on the stack, 4-byte aligned. */
1130 reg_size = (len + 3) & ~3;
1131 write_memory (sp + stack_offset, val, reg_size);
1132 stack_offset += reg_size;
1134 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
1136 /* Argument goes in a float argument register. */
1137 reg_size = register_size (gdbarch, flt_argreg);
1138 regval = extract_unsigned_integer (val, reg_size, byte_order);
1139 /* In little endian mode, float types taking two registers
1140 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
1141 be stored swapped in the argument registers. The below
1142 code first writes the first 32 bits in the next but one
1143 register, increments the val and len values accordingly
1144 and then proceeds as normal by writing the second 32 bits
1145 into the next register. */
1146 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE
1147 && TYPE_LENGTH (type) == 2 * reg_size)
1149 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
1153 regval = extract_unsigned_integer (val, reg_size, byte_order);
1155 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
1157 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
1159 /* there's room in a register */
1160 reg_size = register_size (gdbarch, argreg);
1161 regval = extract_unsigned_integer (val, reg_size, byte_order);
1162 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1164 /* Store the value one register at a time or in one step on stack. */
1172 if (sh_is_renesas_calling_convention (func_type))
1173 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1174 the stack and store the struct return address there. */
1175 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
1177 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1178 its own dedicated register. */
1179 regcache_cooked_write_unsigned (regcache,
1180 STRUCT_RETURN_REGNUM, struct_addr);
1183 /* Store return address. */
1184 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1186 /* Update stack pointer. */
1187 regcache_cooked_write_unsigned (regcache,
1188 gdbarch_sp_regnum (gdbarch), sp);
1194 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1195 struct value *function,
1196 struct regcache *regcache,
1198 int nargs, struct value **args,
1199 CORE_ADDR sp, int struct_return,
1200 CORE_ADDR struct_addr)
1202 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1203 int stack_offset = 0;
1204 int argreg = ARG0_REGNUM;
1206 struct type *func_type = value_type (function);
1210 int len, reg_size = 0;
1211 int pass_on_stack = 0;
1212 int last_reg_arg = INT_MAX;
1214 /* The Renesas ABI expects all varargs arguments, plus the last
1215 non-vararg argument to be on the stack, no matter how many
1216 registers have been used so far. */
1217 if (sh_is_renesas_calling_convention (func_type)
1218 && TYPE_VARARGS (func_type))
1219 last_reg_arg = TYPE_NFIELDS (func_type) - 2;
1221 /* first force sp to a 4-byte alignment */
1222 sp = sh_frame_align (gdbarch, sp);
1224 /* make room on stack for args */
1225 sp -= sh_stack_allocsize (nargs, args);
1227 /* Now load as many as possible of the first arguments into
1228 registers, and push the rest onto the stack. There are 16 bytes
1229 in four registers available. Loop thru args from first to last. */
1230 for (argnum = 0; argnum < nargs; argnum++)
1232 type = value_type (args[argnum]);
1233 len = TYPE_LENGTH (type);
1234 val = sh_justify_value_in_reg (gdbarch, args[argnum], len);
1236 /* Some decisions have to be made how various types are handled.
1237 This also differs in different ABIs. */
1239 /* Renesas ABI pushes doubles and long longs entirely on stack.
1240 Same goes for aggregate types. */
1241 if (sh_is_renesas_calling_convention (func_type)
1242 && ((TYPE_CODE (type) == TYPE_CODE_INT && len >= 8)
1243 || (TYPE_CODE (type) == TYPE_CODE_FLT && len >= 8)
1244 || TYPE_CODE (type) == TYPE_CODE_STRUCT
1245 || TYPE_CODE (type) == TYPE_CODE_UNION))
1249 if (argreg > ARGLAST_REGNUM || pass_on_stack
1250 || argnum > last_reg_arg)
1252 /* The remainder of the data goes entirely on the stack,
1254 reg_size = (len + 3) & ~3;
1255 write_memory (sp + stack_offset, val, reg_size);
1256 stack_offset += reg_size;
1258 else if (argreg <= ARGLAST_REGNUM)
1260 /* there's room in a register */
1261 reg_size = register_size (gdbarch, argreg);
1262 regval = extract_unsigned_integer (val, reg_size, byte_order);
1263 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1265 /* Store the value reg_size bytes at a time. This means that things
1266 larger than reg_size bytes may go partly in registers and partly
1275 if (sh_is_renesas_calling_convention (func_type))
1276 /* If the function uses the Renesas ABI, subtract another 4 bytes from
1277 the stack and store the struct return address there. */
1278 write_memory_unsigned_integer (sp -= 4, 4, byte_order, struct_addr);
1280 /* Using the gcc ABI, the "struct return pointer" pseudo-argument has
1281 its own dedicated register. */
1282 regcache_cooked_write_unsigned (regcache,
1283 STRUCT_RETURN_REGNUM, struct_addr);
1286 /* Store return address. */
1287 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1289 /* Update stack pointer. */
1290 regcache_cooked_write_unsigned (regcache,
1291 gdbarch_sp_regnum (gdbarch), sp);
1296 /* Find a function's return value in the appropriate registers (in
1297 regbuf), and copy it into valbuf. Extract from an array REGBUF
1298 containing the (raw) register state a function return value of type
1299 TYPE, and copy that, in virtual format, into VALBUF. */
1301 sh_extract_return_value_nofpu (struct type *type, struct regcache *regcache,
1304 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1305 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1306 int len = TYPE_LENGTH (type);
1307 int return_register = R0_REGNUM;
1314 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1315 store_unsigned_integer (valbuf, len, byte_order, c);
1319 int i, regnum = R0_REGNUM;
1320 for (i = 0; i < len; i += 4)
1321 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1324 error (_("bad size for return value"));
1328 sh_extract_return_value_fpu (struct type *type, struct regcache *regcache,
1331 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1332 if (sh_treat_as_flt_p (type))
1334 int len = TYPE_LENGTH (type);
1335 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1336 for (i = 0; i < len; i += 4)
1337 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1338 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1340 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1343 sh_extract_return_value_nofpu (type, regcache, valbuf);
1346 /* Write into appropriate registers a function return value
1347 of type TYPE, given in virtual format.
1348 If the architecture is sh4 or sh3e, store a function's return value
1349 in the R0 general register or in the FP0 floating point register,
1350 depending on the type of the return value. In all the other cases
1351 the result is stored in r0, left-justified. */
1353 sh_store_return_value_nofpu (struct type *type, struct regcache *regcache,
1356 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1357 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1359 int len = TYPE_LENGTH (type);
1363 val = extract_unsigned_integer (valbuf, len, byte_order);
1364 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1368 int i, regnum = R0_REGNUM;
1369 for (i = 0; i < len; i += 4)
1370 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1375 sh_store_return_value_fpu (struct type *type, struct regcache *regcache,
1378 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1379 if (sh_treat_as_flt_p (type))
1381 int len = TYPE_LENGTH (type);
1382 int i, regnum = gdbarch_fp0_regnum (gdbarch);
1383 for (i = 0; i < len; i += 4)
1384 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_LITTLE)
1385 regcache_raw_write (regcache, regnum++,
1386 (char *) valbuf + len - 4 - i);
1388 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1391 sh_store_return_value_nofpu (type, regcache, valbuf);
1394 static enum return_value_convention
1395 sh_return_value_nofpu (struct gdbarch *gdbarch, struct type *func_type,
1396 struct type *type, struct regcache *regcache,
1397 gdb_byte *readbuf, const gdb_byte *writebuf)
1399 if (sh_use_struct_convention_nofpu (
1400 sh_is_renesas_calling_convention (func_type), type))
1401 return RETURN_VALUE_STRUCT_CONVENTION;
1403 sh_store_return_value_nofpu (type, regcache, writebuf);
1405 sh_extract_return_value_nofpu (type, regcache, readbuf);
1406 return RETURN_VALUE_REGISTER_CONVENTION;
1409 static enum return_value_convention
1410 sh_return_value_fpu (struct gdbarch *gdbarch, struct type *func_type,
1411 struct type *type, struct regcache *regcache,
1412 gdb_byte *readbuf, const gdb_byte *writebuf)
1414 if (sh_use_struct_convention (
1415 sh_is_renesas_calling_convention (func_type), type))
1416 return RETURN_VALUE_STRUCT_CONVENTION;
1418 sh_store_return_value_fpu (type, regcache, writebuf);
1420 sh_extract_return_value_fpu (type, regcache, readbuf);
1421 return RETURN_VALUE_REGISTER_CONVENTION;
1424 /* Print the registers in a form similar to the E7000 */
1427 sh_generic_show_regs (struct frame_info *frame)
1430 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1431 phex (get_frame_register_unsigned (frame,
1433 (get_frame_arch (frame))), 4),
1434 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1435 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1436 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1439 (" GBR %08lx VBR %08lx MACL %08lx\n",
1440 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1441 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1442 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1445 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1446 (long) get_frame_register_unsigned (frame, 0),
1447 (long) get_frame_register_unsigned (frame, 1),
1448 (long) get_frame_register_unsigned (frame, 2),
1449 (long) get_frame_register_unsigned (frame, 3),
1450 (long) get_frame_register_unsigned (frame, 4),
1451 (long) get_frame_register_unsigned (frame, 5),
1452 (long) get_frame_register_unsigned (frame, 6),
1453 (long) get_frame_register_unsigned (frame, 7));
1455 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1456 (long) get_frame_register_unsigned (frame, 8),
1457 (long) get_frame_register_unsigned (frame, 9),
1458 (long) get_frame_register_unsigned (frame, 10),
1459 (long) get_frame_register_unsigned (frame, 11),
1460 (long) get_frame_register_unsigned (frame, 12),
1461 (long) get_frame_register_unsigned (frame, 13),
1462 (long) get_frame_register_unsigned (frame, 14),
1463 (long) get_frame_register_unsigned (frame, 15));
1467 sh3_show_regs (struct frame_info *frame)
1470 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1471 phex (get_frame_register_unsigned (frame,
1473 (get_frame_arch (frame))), 4),
1474 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1475 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1476 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1479 (" GBR %08lx VBR %08lx MACL %08lx\n",
1480 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1481 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1482 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1484 (" SSR %08lx SPC %08lx\n",
1485 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1486 (long) get_frame_register_unsigned (frame, SPC_REGNUM));
1489 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1490 (long) get_frame_register_unsigned (frame, 0),
1491 (long) get_frame_register_unsigned (frame, 1),
1492 (long) get_frame_register_unsigned (frame, 2),
1493 (long) get_frame_register_unsigned (frame, 3),
1494 (long) get_frame_register_unsigned (frame, 4),
1495 (long) get_frame_register_unsigned (frame, 5),
1496 (long) get_frame_register_unsigned (frame, 6),
1497 (long) get_frame_register_unsigned (frame, 7));
1499 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1500 (long) get_frame_register_unsigned (frame, 8),
1501 (long) get_frame_register_unsigned (frame, 9),
1502 (long) get_frame_register_unsigned (frame, 10),
1503 (long) get_frame_register_unsigned (frame, 11),
1504 (long) get_frame_register_unsigned (frame, 12),
1505 (long) get_frame_register_unsigned (frame, 13),
1506 (long) get_frame_register_unsigned (frame, 14),
1507 (long) get_frame_register_unsigned (frame, 15));
1511 sh2e_show_regs (struct frame_info *frame)
1513 struct gdbarch *gdbarch = get_frame_arch (frame);
1515 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1516 phex (get_frame_register_unsigned (frame,
1517 gdbarch_pc_regnum (gdbarch)), 4),
1518 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1519 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1520 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1523 (" GBR %08lx VBR %08lx MACL %08lx\n",
1524 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1525 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1526 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1528 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1529 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1530 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1531 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1532 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1535 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1536 (long) get_frame_register_unsigned (frame, 0),
1537 (long) get_frame_register_unsigned (frame, 1),
1538 (long) get_frame_register_unsigned (frame, 2),
1539 (long) get_frame_register_unsigned (frame, 3),
1540 (long) get_frame_register_unsigned (frame, 4),
1541 (long) get_frame_register_unsigned (frame, 5),
1542 (long) get_frame_register_unsigned (frame, 6),
1543 (long) get_frame_register_unsigned (frame, 7));
1545 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1546 (long) get_frame_register_unsigned (frame, 8),
1547 (long) get_frame_register_unsigned (frame, 9),
1548 (long) get_frame_register_unsigned (frame, 10),
1549 (long) get_frame_register_unsigned (frame, 11),
1550 (long) get_frame_register_unsigned (frame, 12),
1551 (long) get_frame_register_unsigned (frame, 13),
1552 (long) get_frame_register_unsigned (frame, 14),
1553 (long) get_frame_register_unsigned (frame, 15));
1556 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1557 (long) get_frame_register_unsigned
1558 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1559 (long) get_frame_register_unsigned
1560 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1561 (long) get_frame_register_unsigned
1562 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1563 (long) get_frame_register_unsigned
1564 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1565 (long) get_frame_register_unsigned
1566 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1567 (long) get_frame_register_unsigned
1568 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1569 (long) get_frame_register_unsigned
1570 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1571 (long) get_frame_register_unsigned
1572 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1574 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1575 (long) get_frame_register_unsigned
1576 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1577 (long) get_frame_register_unsigned
1578 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1579 (long) get_frame_register_unsigned
1580 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1581 (long) get_frame_register_unsigned
1582 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1583 (long) get_frame_register_unsigned
1584 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1585 (long) get_frame_register_unsigned
1586 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1587 (long) get_frame_register_unsigned
1588 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1589 (long) get_frame_register_unsigned
1590 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1594 sh2a_show_regs (struct frame_info *frame)
1596 struct gdbarch *gdbarch = get_frame_arch (frame);
1597 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1600 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1601 phex (get_frame_register_unsigned (frame,
1602 gdbarch_pc_regnum (gdbarch)), 4),
1603 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1604 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1605 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1608 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1609 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1610 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1611 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1612 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1614 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1615 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1616 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1617 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1618 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1621 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1622 (long) get_frame_register_unsigned (frame, 0),
1623 (long) get_frame_register_unsigned (frame, 1),
1624 (long) get_frame_register_unsigned (frame, 2),
1625 (long) get_frame_register_unsigned (frame, 3),
1626 (long) get_frame_register_unsigned (frame, 4),
1627 (long) get_frame_register_unsigned (frame, 5),
1628 (long) get_frame_register_unsigned (frame, 6),
1629 (long) get_frame_register_unsigned (frame, 7));
1631 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1632 (long) get_frame_register_unsigned (frame, 8),
1633 (long) get_frame_register_unsigned (frame, 9),
1634 (long) get_frame_register_unsigned (frame, 10),
1635 (long) get_frame_register_unsigned (frame, 11),
1636 (long) get_frame_register_unsigned (frame, 12),
1637 (long) get_frame_register_unsigned (frame, 13),
1638 (long) get_frame_register_unsigned (frame, 14),
1639 (long) get_frame_register_unsigned (frame, 15));
1642 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1643 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1644 (long) get_frame_register_unsigned
1645 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1646 (long) get_frame_register_unsigned
1647 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1648 (long) get_frame_register_unsigned
1649 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1650 (long) get_frame_register_unsigned
1651 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1652 (long) get_frame_register_unsigned
1653 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1654 (long) get_frame_register_unsigned
1655 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1656 (long) get_frame_register_unsigned
1657 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1658 (long) get_frame_register_unsigned
1659 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1661 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1662 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1663 (long) get_frame_register_unsigned
1664 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1665 (long) get_frame_register_unsigned
1666 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1667 (long) get_frame_register_unsigned
1668 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1669 (long) get_frame_register_unsigned
1670 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1671 (long) get_frame_register_unsigned
1672 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1673 (long) get_frame_register_unsigned
1674 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1675 (long) get_frame_register_unsigned
1676 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1677 (long) get_frame_register_unsigned
1678 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1680 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1682 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1683 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1684 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1685 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1686 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1687 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1688 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1689 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1690 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1692 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1693 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1694 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1695 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1696 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1697 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1698 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1699 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1701 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1702 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1703 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1704 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1705 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1706 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1710 sh2a_nofpu_show_regs (struct frame_info *frame)
1712 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1715 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1716 phex (get_frame_register_unsigned (frame,
1718 (get_frame_arch (frame))), 4),
1719 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1720 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1721 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1724 (" GBR %08lx VBR %08lx TBR %08lx MACL %08lx\n",
1725 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1726 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1727 (long) get_frame_register_unsigned (frame, TBR_REGNUM),
1728 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1730 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1731 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1732 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1733 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1734 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1737 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1738 (long) get_frame_register_unsigned (frame, 0),
1739 (long) get_frame_register_unsigned (frame, 1),
1740 (long) get_frame_register_unsigned (frame, 2),
1741 (long) get_frame_register_unsigned (frame, 3),
1742 (long) get_frame_register_unsigned (frame, 4),
1743 (long) get_frame_register_unsigned (frame, 5),
1744 (long) get_frame_register_unsigned (frame, 6),
1745 (long) get_frame_register_unsigned (frame, 7));
1747 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1748 (long) get_frame_register_unsigned (frame, 8),
1749 (long) get_frame_register_unsigned (frame, 9),
1750 (long) get_frame_register_unsigned (frame, 10),
1751 (long) get_frame_register_unsigned (frame, 11),
1752 (long) get_frame_register_unsigned (frame, 12),
1753 (long) get_frame_register_unsigned (frame, 13),
1754 (long) get_frame_register_unsigned (frame, 14),
1755 (long) get_frame_register_unsigned (frame, 15));
1758 ("BANK=%-3d\n", (int) get_frame_register_unsigned (frame, BANK_REGNUM));
1760 ("R0b-R7b %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1761 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 0),
1762 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 1),
1763 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 2),
1764 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 3),
1765 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 4),
1766 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 5),
1767 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 6),
1768 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 7));
1770 ("R8b-R14b %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1771 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 8),
1772 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 9),
1773 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 10),
1774 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 11),
1775 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 12),
1776 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 13),
1777 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 14));
1779 ("MACHb=%08lx IVNb=%08lx PRb=%08lx GBRb=%08lx MACLb=%08lx\n",
1780 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 15),
1781 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 16),
1782 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 17),
1783 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 18),
1784 (long) get_frame_register_unsigned (frame, R0_BANK0_REGNUM + 19));
1788 sh3e_show_regs (struct frame_info *frame)
1790 struct gdbarch *gdbarch = get_frame_arch (frame);
1792 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1793 phex (get_frame_register_unsigned (frame,
1794 gdbarch_pc_regnum (gdbarch)), 4),
1795 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1796 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1797 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1800 (" GBR %08lx VBR %08lx MACL %08lx\n",
1801 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1802 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1803 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1805 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1806 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1807 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1808 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1809 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1812 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1813 (long) get_frame_register_unsigned (frame, 0),
1814 (long) get_frame_register_unsigned (frame, 1),
1815 (long) get_frame_register_unsigned (frame, 2),
1816 (long) get_frame_register_unsigned (frame, 3),
1817 (long) get_frame_register_unsigned (frame, 4),
1818 (long) get_frame_register_unsigned (frame, 5),
1819 (long) get_frame_register_unsigned (frame, 6),
1820 (long) get_frame_register_unsigned (frame, 7));
1822 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1823 (long) get_frame_register_unsigned (frame, 8),
1824 (long) get_frame_register_unsigned (frame, 9),
1825 (long) get_frame_register_unsigned (frame, 10),
1826 (long) get_frame_register_unsigned (frame, 11),
1827 (long) get_frame_register_unsigned (frame, 12),
1828 (long) get_frame_register_unsigned (frame, 13),
1829 (long) get_frame_register_unsigned (frame, 14),
1830 (long) get_frame_register_unsigned (frame, 15));
1833 ("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1834 (long) get_frame_register_unsigned
1835 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1836 (long) get_frame_register_unsigned
1837 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1838 (long) get_frame_register_unsigned
1839 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1840 (long) get_frame_register_unsigned
1841 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1842 (long) get_frame_register_unsigned
1843 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1844 (long) get_frame_register_unsigned
1845 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1846 (long) get_frame_register_unsigned
1847 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1848 (long) get_frame_register_unsigned
1849 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
1851 ("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1852 (long) get_frame_register_unsigned
1853 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
1854 (long) get_frame_register_unsigned
1855 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
1856 (long) get_frame_register_unsigned
1857 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
1858 (long) get_frame_register_unsigned
1859 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
1860 (long) get_frame_register_unsigned
1861 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
1862 (long) get_frame_register_unsigned
1863 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
1864 (long) get_frame_register_unsigned
1865 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
1866 (long) get_frame_register_unsigned
1867 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
1871 sh3_dsp_show_regs (struct frame_info *frame)
1874 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1875 phex (get_frame_register_unsigned (frame,
1877 (get_frame_arch (frame))), 4),
1878 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1879 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1880 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1883 (" GBR %08lx VBR %08lx MACL %08lx\n",
1884 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1885 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1886 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1889 (" SSR %08lx SPC %08lx DSR %08lx\n",
1890 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1891 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1892 (long) get_frame_register_unsigned (frame, DSR_REGNUM));
1895 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1896 (long) get_frame_register_unsigned (frame, 0),
1897 (long) get_frame_register_unsigned (frame, 1),
1898 (long) get_frame_register_unsigned (frame, 2),
1899 (long) get_frame_register_unsigned (frame, 3),
1900 (long) get_frame_register_unsigned (frame, 4),
1901 (long) get_frame_register_unsigned (frame, 5),
1902 (long) get_frame_register_unsigned (frame, 6),
1903 (long) get_frame_register_unsigned (frame, 7));
1905 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1906 (long) get_frame_register_unsigned (frame, 8),
1907 (long) get_frame_register_unsigned (frame, 9),
1908 (long) get_frame_register_unsigned (frame, 10),
1909 (long) get_frame_register_unsigned (frame, 11),
1910 (long) get_frame_register_unsigned (frame, 12),
1911 (long) get_frame_register_unsigned (frame, 13),
1912 (long) get_frame_register_unsigned (frame, 14),
1913 (long) get_frame_register_unsigned (frame, 15));
1916 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1917 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
1918 (long) get_frame_register_unsigned (frame, A0_REGNUM),
1919 (long) get_frame_register_unsigned (frame, M0_REGNUM),
1920 (long) get_frame_register_unsigned (frame, X0_REGNUM),
1921 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
1922 (long) get_frame_register_unsigned (frame, RS_REGNUM),
1923 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
1925 ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1926 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
1927 (long) get_frame_register_unsigned (frame, A1_REGNUM),
1928 (long) get_frame_register_unsigned (frame, M1_REGNUM),
1929 (long) get_frame_register_unsigned (frame, X1_REGNUM),
1930 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
1931 (long) get_frame_register_unsigned (frame, RE_REGNUM));
1935 sh4_show_regs (struct frame_info *frame)
1937 struct gdbarch *gdbarch = get_frame_arch (frame);
1938 int pr = get_frame_register_unsigned (frame, FPSCR_REGNUM) & 0x80000;
1941 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
1942 phex (get_frame_register_unsigned (frame,
1943 gdbarch_pc_regnum (gdbarch)), 4),
1944 (long) get_frame_register_unsigned (frame, SR_REGNUM),
1945 (long) get_frame_register_unsigned (frame, PR_REGNUM),
1946 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
1949 (" GBR %08lx VBR %08lx MACL %08lx\n",
1950 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
1951 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
1952 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
1954 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
1955 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
1956 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
1957 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
1958 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
1961 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1962 (long) get_frame_register_unsigned (frame, 0),
1963 (long) get_frame_register_unsigned (frame, 1),
1964 (long) get_frame_register_unsigned (frame, 2),
1965 (long) get_frame_register_unsigned (frame, 3),
1966 (long) get_frame_register_unsigned (frame, 4),
1967 (long) get_frame_register_unsigned (frame, 5),
1968 (long) get_frame_register_unsigned (frame, 6),
1969 (long) get_frame_register_unsigned (frame, 7));
1971 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1972 (long) get_frame_register_unsigned (frame, 8),
1973 (long) get_frame_register_unsigned (frame, 9),
1974 (long) get_frame_register_unsigned (frame, 10),
1975 (long) get_frame_register_unsigned (frame, 11),
1976 (long) get_frame_register_unsigned (frame, 12),
1977 (long) get_frame_register_unsigned (frame, 13),
1978 (long) get_frame_register_unsigned (frame, 14),
1979 (long) get_frame_register_unsigned (frame, 15));
1982 (pr ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1983 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1984 (long) get_frame_register_unsigned
1985 (frame, gdbarch_fp0_regnum (gdbarch) + 0),
1986 (long) get_frame_register_unsigned
1987 (frame, gdbarch_fp0_regnum (gdbarch) + 1),
1988 (long) get_frame_register_unsigned
1989 (frame, gdbarch_fp0_regnum (gdbarch) + 2),
1990 (long) get_frame_register_unsigned
1991 (frame, gdbarch_fp0_regnum (gdbarch) + 3),
1992 (long) get_frame_register_unsigned
1993 (frame, gdbarch_fp0_regnum (gdbarch) + 4),
1994 (long) get_frame_register_unsigned
1995 (frame, gdbarch_fp0_regnum (gdbarch) + 5),
1996 (long) get_frame_register_unsigned
1997 (frame, gdbarch_fp0_regnum (gdbarch) + 6),
1998 (long) get_frame_register_unsigned
1999 (frame, gdbarch_fp0_regnum (gdbarch) + 7));
2001 (pr ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2002 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2003 (long) get_frame_register_unsigned
2004 (frame, gdbarch_fp0_regnum (gdbarch) + 8),
2005 (long) get_frame_register_unsigned
2006 (frame, gdbarch_fp0_regnum (gdbarch) + 9),
2007 (long) get_frame_register_unsigned
2008 (frame, gdbarch_fp0_regnum (gdbarch) + 10),
2009 (long) get_frame_register_unsigned
2010 (frame, gdbarch_fp0_regnum (gdbarch) + 11),
2011 (long) get_frame_register_unsigned
2012 (frame, gdbarch_fp0_regnum (gdbarch) + 12),
2013 (long) get_frame_register_unsigned
2014 (frame, gdbarch_fp0_regnum (gdbarch) + 13),
2015 (long) get_frame_register_unsigned
2016 (frame, gdbarch_fp0_regnum (gdbarch) + 14),
2017 (long) get_frame_register_unsigned
2018 (frame, gdbarch_fp0_regnum (gdbarch) + 15));
2022 sh4_nofpu_show_regs (struct frame_info *frame)
2025 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2026 phex (get_frame_register_unsigned (frame,
2028 (get_frame_arch (frame))), 4),
2029 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2030 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2031 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2034 (" GBR %08lx VBR %08lx MACL %08lx\n",
2035 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2036 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2037 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2039 (" SSR %08lx SPC %08lx FPUL %08lx FPSCR %08lx\n",
2040 (long) get_frame_register_unsigned (frame, SSR_REGNUM),
2041 (long) get_frame_register_unsigned (frame, SPC_REGNUM),
2042 (long) get_frame_register_unsigned (frame, FPUL_REGNUM),
2043 (long) get_frame_register_unsigned (frame, FPSCR_REGNUM));
2046 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2047 (long) get_frame_register_unsigned (frame, 0),
2048 (long) get_frame_register_unsigned (frame, 1),
2049 (long) get_frame_register_unsigned (frame, 2),
2050 (long) get_frame_register_unsigned (frame, 3),
2051 (long) get_frame_register_unsigned (frame, 4),
2052 (long) get_frame_register_unsigned (frame, 5),
2053 (long) get_frame_register_unsigned (frame, 6),
2054 (long) get_frame_register_unsigned (frame, 7));
2056 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2057 (long) get_frame_register_unsigned (frame, 8),
2058 (long) get_frame_register_unsigned (frame, 9),
2059 (long) get_frame_register_unsigned (frame, 10),
2060 (long) get_frame_register_unsigned (frame, 11),
2061 (long) get_frame_register_unsigned (frame, 12),
2062 (long) get_frame_register_unsigned (frame, 13),
2063 (long) get_frame_register_unsigned (frame, 14),
2064 (long) get_frame_register_unsigned (frame, 15));
2068 sh_dsp_show_regs (struct frame_info *frame)
2071 (" PC %s SR %08lx PR %08lx MACH %08lx\n",
2072 phex (get_frame_register_unsigned (frame,
2074 (get_frame_arch (frame))), 4),
2075 (long) get_frame_register_unsigned (frame, SR_REGNUM),
2076 (long) get_frame_register_unsigned (frame, PR_REGNUM),
2077 (long) get_frame_register_unsigned (frame, MACH_REGNUM));
2080 (" GBR %08lx VBR %08lx DSR %08lx MACL %08lx\n",
2081 (long) get_frame_register_unsigned (frame, GBR_REGNUM),
2082 (long) get_frame_register_unsigned (frame, VBR_REGNUM),
2083 (long) get_frame_register_unsigned (frame, DSR_REGNUM),
2084 (long) get_frame_register_unsigned (frame, MACL_REGNUM));
2087 ("R0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2088 (long) get_frame_register_unsigned (frame, 0),
2089 (long) get_frame_register_unsigned (frame, 1),
2090 (long) get_frame_register_unsigned (frame, 2),
2091 (long) get_frame_register_unsigned (frame, 3),
2092 (long) get_frame_register_unsigned (frame, 4),
2093 (long) get_frame_register_unsigned (frame, 5),
2094 (long) get_frame_register_unsigned (frame, 6),
2095 (long) get_frame_register_unsigned (frame, 7));
2097 ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2098 (long) get_frame_register_unsigned (frame, 8),
2099 (long) get_frame_register_unsigned (frame, 9),
2100 (long) get_frame_register_unsigned (frame, 10),
2101 (long) get_frame_register_unsigned (frame, 11),
2102 (long) get_frame_register_unsigned (frame, 12),
2103 (long) get_frame_register_unsigned (frame, 13),
2104 (long) get_frame_register_unsigned (frame, 14),
2105 (long) get_frame_register_unsigned (frame, 15));
2108 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2109 (long) get_frame_register_unsigned (frame, A0G_REGNUM) & 0xff,
2110 (long) get_frame_register_unsigned (frame, A0_REGNUM),
2111 (long) get_frame_register_unsigned (frame, M0_REGNUM),
2112 (long) get_frame_register_unsigned (frame, X0_REGNUM),
2113 (long) get_frame_register_unsigned (frame, Y0_REGNUM),
2114 (long) get_frame_register_unsigned (frame, RS_REGNUM),
2115 (long) get_frame_register_unsigned (frame, MOD_REGNUM));
2116 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2117 (long) get_frame_register_unsigned (frame, A1G_REGNUM) & 0xff,
2118 (long) get_frame_register_unsigned (frame, A1_REGNUM),
2119 (long) get_frame_register_unsigned (frame, M1_REGNUM),
2120 (long) get_frame_register_unsigned (frame, X1_REGNUM),
2121 (long) get_frame_register_unsigned (frame, Y1_REGNUM),
2122 (long) get_frame_register_unsigned (frame, RE_REGNUM));
2126 sh_show_regs_command (char *args, int from_tty)
2129 (*sh_show_regs) (get_current_frame ());
2132 static struct type *
2133 sh_sh2a_register_type (struct gdbarch *gdbarch, int reg_nr)
2135 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2136 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2137 return builtin_type (gdbarch)->builtin_float;
2138 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2139 return builtin_type (gdbarch)->builtin_double;
2141 return builtin_type (gdbarch)->builtin_int;
2144 /* Return the GDB type object for the "standard" data type
2145 of data in register N. */
2146 static struct type *
2147 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
2149 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2150 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2151 return builtin_type (gdbarch)->builtin_float;
2153 return builtin_type (gdbarch)->builtin_int;
2156 static struct type *
2157 sh_sh4_build_float_register_type (struct gdbarch *gdbarch, int high)
2159 return lookup_array_range_type (builtin_type (gdbarch)->builtin_float,
2163 static struct type *
2164 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
2166 if ((reg_nr >= gdbarch_fp0_regnum (gdbarch)
2167 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
2168 return builtin_type (gdbarch)->builtin_float;
2169 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2170 return builtin_type (gdbarch)->builtin_double;
2171 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2172 return sh_sh4_build_float_register_type (gdbarch, 3);
2174 return builtin_type (gdbarch)->builtin_int;
2177 static struct type *
2178 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
2180 return builtin_type (gdbarch)->builtin_int;
2183 /* Is a register in a reggroup?
2184 The default code in reggroup.c doesn't identify system registers, some
2185 float registers or any of the vector registers.
2186 TODO: sh2a and dsp registers. */
2188 sh_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2189 struct reggroup *reggroup)
2191 if (gdbarch_register_name (gdbarch, regnum) == NULL
2192 || *gdbarch_register_name (gdbarch, regnum) == '\0')
2195 if (reggroup == float_reggroup
2196 && (regnum == FPUL_REGNUM
2197 || regnum == FPSCR_REGNUM))
2200 if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
2202 if (reggroup == vector_reggroup || reggroup == float_reggroup)
2204 if (reggroup == general_reggroup)
2208 if (regnum == VBR_REGNUM
2209 || regnum == SR_REGNUM
2210 || regnum == FPSCR_REGNUM
2211 || regnum == SSR_REGNUM
2212 || regnum == SPC_REGNUM)
2214 if (reggroup == system_reggroup)
2216 if (reggroup == general_reggroup)
2220 /* The default code can cope with any other registers. */
2221 return default_register_reggroup_p (gdbarch, regnum, reggroup);
2224 /* On the sh4, the DRi pseudo registers are problematic if the target
2225 is little endian. When the user writes one of those registers, for
2226 instance with 'ser var $dr0=1', we want the double to be stored
2228 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2229 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2231 This corresponds to little endian byte order & big endian word
2232 order. However if we let gdb write the register w/o conversion, it
2233 will write fr0 and fr1 this way:
2234 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2235 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
2236 because it will consider fr0 and fr1 as a single LE stretch of memory.
2238 To achieve what we want we must force gdb to store things in
2239 floatformat_ieee_double_littlebyte_bigword (which is defined in
2240 include/floatformat.h and libiberty/floatformat.c.
2242 In case the target is big endian, there is no problem, the
2243 raw bytes will look like:
2244 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
2245 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
2247 The other pseudo registers (the FVs) also don't pose a problem
2248 because they are stored as 4 individual FP elements. */
2251 sh_register_convert_to_virtual (int regnum, struct type *type,
2252 char *from, char *to)
2254 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2257 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2259 store_typed_floating (to, type, val);
2263 ("sh_register_convert_to_virtual called with non DR register number");
2267 sh_register_convert_to_raw (struct type *type, int regnum,
2268 const void *from, void *to)
2270 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
2272 DOUBLEST val = extract_typed_floating (from, type);
2273 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
2277 error (_("sh_register_convert_to_raw called with non DR register number"));
2280 /* For vectors of 4 floating point registers. */
2282 fv_reg_base_num (struct gdbarch *gdbarch, int fv_regnum)
2286 fp_regnum = gdbarch_fp0_regnum (gdbarch)
2287 + (fv_regnum - FV0_REGNUM) * 4;
2291 /* For double precision floating point registers, i.e 2 fp regs.*/
2293 dr_reg_base_num (struct gdbarch *gdbarch, int dr_regnum)
2297 fp_regnum = gdbarch_fp0_regnum (gdbarch)
2298 + (dr_regnum - DR0_REGNUM) * 2;
2303 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2304 int reg_nr, gdb_byte *buffer)
2306 int base_regnum, portion;
2307 char temp_buffer[MAX_REGISTER_SIZE];
2309 if (reg_nr == PSEUDO_BANK_REGNUM)
2310 regcache_raw_read (regcache, BANK_REGNUM, buffer);
2312 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2314 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2316 /* Build the value in the provided buffer. */
2317 /* Read the real regs for which this one is an alias. */
2318 for (portion = 0; portion < 2; portion++)
2319 regcache_raw_read (regcache, base_regnum + portion,
2321 + register_size (gdbarch,
2322 base_regnum) * portion));
2323 /* We must pay attention to the endiannes. */
2324 sh_register_convert_to_virtual (reg_nr,
2325 register_type (gdbarch, reg_nr),
2326 temp_buffer, buffer);
2328 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2330 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2332 /* Read the real regs for which this one is an alias. */
2333 for (portion = 0; portion < 4; portion++)
2334 regcache_raw_read (regcache, base_regnum + portion,
2336 + register_size (gdbarch,
2337 base_regnum) * portion));
2342 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2343 int reg_nr, const gdb_byte *buffer)
2345 int base_regnum, portion;
2346 char temp_buffer[MAX_REGISTER_SIZE];
2348 if (reg_nr == PSEUDO_BANK_REGNUM)
2350 /* When the bank register is written to, the whole register bank
2351 is switched and all values in the bank registers must be read
2352 from the target/sim again. We're just invalidating the regcache
2353 so that a re-read happens next time it's necessary. */
2356 regcache_raw_write (regcache, BANK_REGNUM, buffer);
2357 for (bregnum = R0_BANK0_REGNUM; bregnum < MACLB_REGNUM; ++bregnum)
2358 regcache_invalidate (regcache, bregnum);
2360 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
2362 base_regnum = dr_reg_base_num (gdbarch, reg_nr);
2364 /* We must pay attention to the endiannes. */
2365 sh_register_convert_to_raw (register_type (gdbarch, reg_nr),
2366 reg_nr, buffer, temp_buffer);
2368 /* Write the real regs for which this one is an alias. */
2369 for (portion = 0; portion < 2; portion++)
2370 regcache_raw_write (regcache, base_regnum + portion,
2372 + register_size (gdbarch,
2373 base_regnum) * portion));
2375 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
2377 base_regnum = fv_reg_base_num (gdbarch, reg_nr);
2379 /* Write the real regs for which this one is an alias. */
2380 for (portion = 0; portion < 4; portion++)
2381 regcache_raw_write (regcache, base_regnum + portion,
2383 + register_size (gdbarch,
2384 base_regnum) * portion));
2389 sh_dsp_register_sim_regno (struct gdbarch *gdbarch, int nr)
2391 if (legacy_register_sim_regno (gdbarch, nr) < 0)
2392 return legacy_register_sim_regno (gdbarch, nr);
2393 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
2394 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
2395 if (nr == MOD_REGNUM)
2396 return SIM_SH_MOD_REGNUM;
2397 if (nr == RS_REGNUM)
2398 return SIM_SH_RS_REGNUM;
2399 if (nr == RE_REGNUM)
2400 return SIM_SH_RE_REGNUM;
2401 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
2402 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
2407 sh_sh2a_register_sim_regno (struct gdbarch *gdbarch, int nr)
2412 return SIM_SH_TBR_REGNUM;
2414 return SIM_SH_IBNR_REGNUM;
2416 return SIM_SH_IBCR_REGNUM;
2418 return SIM_SH_BANK_REGNUM;
2420 return SIM_SH_BANK_MACL_REGNUM;
2422 return SIM_SH_BANK_GBR_REGNUM;
2424 return SIM_SH_BANK_PR_REGNUM;
2426 return SIM_SH_BANK_IVN_REGNUM;
2428 return SIM_SH_BANK_MACH_REGNUM;
2432 return legacy_register_sim_regno (gdbarch, nr);
2435 /* Set up the register unwinding such that call-clobbered registers are
2436 not displayed in frames >0 because the true value is not certain.
2437 The 'undefined' registers will show up as 'not available' unless the
2440 This function is currently set up for SH4 and compatible only. */
2443 sh_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2444 struct dwarf2_frame_state_reg *reg,
2445 struct frame_info *this_frame)
2447 /* Mark the PC as the destination for the return address. */
2448 if (regnum == gdbarch_pc_regnum (gdbarch))
2449 reg->how = DWARF2_FRAME_REG_RA;
2451 /* Mark the stack pointer as the call frame address. */
2452 else if (regnum == gdbarch_sp_regnum (gdbarch))
2453 reg->how = DWARF2_FRAME_REG_CFA;
2455 /* The above was taken from the default init_reg in dwarf2-frame.c
2456 while the below is SH specific. */
2458 /* Caller save registers. */
2459 else if ((regnum >= R0_REGNUM && regnum <= R0_REGNUM+7)
2460 || (regnum >= FR0_REGNUM && regnum <= FR0_REGNUM+11)
2461 || (regnum >= DR0_REGNUM && regnum <= DR0_REGNUM+5)
2462 || (regnum >= FV0_REGNUM && regnum <= FV0_REGNUM+2)
2463 || (regnum == MACH_REGNUM)
2464 || (regnum == MACL_REGNUM)
2465 || (regnum == FPUL_REGNUM)
2466 || (regnum == SR_REGNUM))
2467 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2469 /* Callee save registers. */
2470 else if ((regnum >= R0_REGNUM+8 && regnum <= R0_REGNUM+15)
2471 || (regnum >= FR0_REGNUM+12 && regnum <= FR0_REGNUM+15)
2472 || (regnum >= DR0_REGNUM+6 && regnum <= DR0_REGNUM+8)
2473 || (regnum == FV0_REGNUM+3))
2474 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
2476 /* Other registers. These are not in the ABI and may or may not
2477 mean anything in frames >0 so don't show them. */
2478 else if ((regnum >= R0_BANK0_REGNUM && regnum <= R0_BANK0_REGNUM+15)
2479 || (regnum == GBR_REGNUM)
2480 || (regnum == VBR_REGNUM)
2481 || (regnum == FPSCR_REGNUM)
2482 || (regnum == SSR_REGNUM)
2483 || (regnum == SPC_REGNUM))
2484 reg->how = DWARF2_FRAME_REG_UNDEFINED;
2487 static struct sh_frame_cache *
2488 sh_alloc_frame_cache (void)
2490 struct sh_frame_cache *cache;
2493 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
2497 cache->saved_sp = 0;
2498 cache->sp_offset = 0;
2501 /* Frameless until proven otherwise. */
2504 /* Saved registers. We initialize these to -1 since zero is a valid
2505 offset (that's where fp is supposed to be stored). */
2506 for (i = 0; i < SH_NUM_REGS; i++)
2508 cache->saved_regs[i] = -1;
2514 static struct sh_frame_cache *
2515 sh_frame_cache (struct frame_info *this_frame, void **this_cache)
2517 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2518 struct sh_frame_cache *cache;
2519 CORE_ADDR current_pc;
2525 cache = sh_alloc_frame_cache ();
2526 *this_cache = cache;
2528 /* In principle, for normal frames, fp holds the frame pointer,
2529 which holds the base address for the current stack frame.
2530 However, for functions that don't need it, the frame pointer is
2531 optional. For these "frameless" functions the frame pointer is
2532 actually the frame pointer of the calling frame. */
2533 cache->base = get_frame_register_unsigned (this_frame, FP_REGNUM);
2534 if (cache->base == 0)
2537 cache->pc = get_frame_func (this_frame);
2538 current_pc = get_frame_pc (this_frame);
2542 fpscr = get_frame_register_unsigned (this_frame, FPSCR_REGNUM);
2543 sh_analyze_prologue (gdbarch, cache->pc, current_pc, cache, fpscr);
2546 if (!cache->uses_fp)
2548 /* We didn't find a valid frame, which means that CACHE->base
2549 currently holds the frame pointer for our calling frame. If
2550 we're at the start of a function, or somewhere half-way its
2551 prologue, the function's frame probably hasn't been fully
2552 setup yet. Try to reconstruct the base address for the stack
2553 frame by looking at the stack pointer. For truly "frameless"
2554 functions this might work too. */
2555 cache->base = get_frame_register_unsigned
2556 (this_frame, gdbarch_sp_regnum (gdbarch));
2559 /* Now that we have the base address for the stack frame we can
2560 calculate the value of sp in the calling frame. */
2561 cache->saved_sp = cache->base + cache->sp_offset;
2563 /* Adjust all the saved registers such that they contain addresses
2564 instead of offsets. */
2565 for (i = 0; i < SH_NUM_REGS; i++)
2566 if (cache->saved_regs[i] != -1)
2567 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
2572 static struct value *
2573 sh_frame_prev_register (struct frame_info *this_frame,
2574 void **this_cache, int regnum)
2576 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2577 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2579 gdb_assert (regnum >= 0);
2581 if (regnum == gdbarch_sp_regnum (gdbarch) && cache->saved_sp)
2582 return frame_unwind_got_constant (this_frame, regnum, cache->saved_sp);
2584 /* The PC of the previous frame is stored in the PR register of
2585 the current frame. Frob regnum so that we pull the value from
2586 the correct place. */
2587 if (regnum == gdbarch_pc_regnum (gdbarch))
2590 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2591 return frame_unwind_got_memory (this_frame, regnum,
2592 cache->saved_regs[regnum]);
2594 return frame_unwind_got_register (this_frame, regnum, regnum);
2598 sh_frame_this_id (struct frame_info *this_frame, void **this_cache,
2599 struct frame_id *this_id)
2601 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2603 /* This marks the outermost frame. */
2604 if (cache->base == 0)
2607 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2610 static const struct frame_unwind sh_frame_unwind = {
2613 sh_frame_prev_register,
2615 default_frame_sniffer
2619 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2621 return frame_unwind_register_unsigned (next_frame,
2622 gdbarch_sp_regnum (gdbarch));
2626 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2628 return frame_unwind_register_unsigned (next_frame,
2629 gdbarch_pc_regnum (gdbarch));
2632 static struct frame_id
2633 sh_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2635 CORE_ADDR sp = get_frame_register_unsigned (this_frame,
2636 gdbarch_sp_regnum (gdbarch));
2637 return frame_id_build (sp, get_frame_pc (this_frame));
2641 sh_frame_base_address (struct frame_info *this_frame, void **this_cache)
2643 struct sh_frame_cache *cache = sh_frame_cache (this_frame, this_cache);
2648 static const struct frame_base sh_frame_base = {
2650 sh_frame_base_address,
2651 sh_frame_base_address,
2652 sh_frame_base_address
2655 /* The epilogue is defined here as the area at the end of a function,
2656 either on the `ret' instruction itself or after an instruction which
2657 destroys the function's stack frame. */
2659 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2661 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2662 CORE_ADDR func_addr = 0, func_end = 0;
2664 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2667 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2668 for a nop and some fixed data (e.g. big offsets) which are
2669 unfortunately also treated as part of the function (which
2670 means, they are below func_end. */
2671 CORE_ADDR addr = func_end - 28;
2672 if (addr < func_addr + 4)
2673 addr = func_addr + 4;
2677 /* First search forward until hitting an rts. */
2678 while (addr < func_end
2679 && !IS_RTS (read_memory_unsigned_integer (addr, 2, byte_order)))
2681 if (addr >= func_end)
2684 /* At this point we should find a mov.l @r15+,r14 instruction,
2685 either before or after the rts. If not, then the function has
2686 probably no "normal" epilogue and we bail out here. */
2687 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2688 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2,
2691 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2,
2695 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2697 /* Step over possible lds.l @r15+,macl. */
2698 if (IS_MACL_LDS (inst))
2701 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2704 /* Step over possible lds.l @r15+,pr. */
2708 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2711 /* Step over possible mov r14,r15. */
2712 if (IS_MOV_FP_SP (inst))
2715 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2718 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2720 while (addr > func_addr + 4
2721 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2724 inst = read_memory_unsigned_integer (addr - 2, 2, byte_order);
2727 /* On SH2a check if the previous instruction was perhaps a MOVI20.
2728 That's allowed for the epilogue. */
2729 if ((gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a
2730 || gdbarch_bfd_arch_info (gdbarch)->mach == bfd_mach_sh2a_nofpu)
2731 && addr > func_addr + 6
2732 && IS_MOVI20 (read_memory_unsigned_integer (addr - 4, 2,
2743 static struct gdbarch *
2744 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2746 struct gdbarch *gdbarch;
2748 sh_show_regs = sh_generic_show_regs;
2749 switch (info.bfd_arch_info->mach)
2752 sh_show_regs = sh2e_show_regs;
2755 sh_show_regs = sh2a_show_regs;
2757 case bfd_mach_sh2a_nofpu:
2758 sh_show_regs = sh2a_nofpu_show_regs;
2760 case bfd_mach_sh_dsp:
2761 sh_show_regs = sh_dsp_show_regs;
2765 case bfd_mach_sh3_nommu:
2766 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2767 sh_show_regs = sh3_show_regs;
2771 case bfd_mach_sh2a_or_sh3e:
2772 sh_show_regs = sh3e_show_regs;
2775 case bfd_mach_sh3_dsp:
2776 case bfd_mach_sh4al_dsp:
2777 sh_show_regs = sh3_dsp_show_regs;
2782 case bfd_mach_sh2a_or_sh4:
2783 sh_show_regs = sh4_show_regs;
2786 case bfd_mach_sh4_nofpu:
2787 case bfd_mach_sh4_nommu_nofpu:
2788 case bfd_mach_sh4a_nofpu:
2789 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2790 sh_show_regs = sh4_nofpu_show_regs;
2794 sh_show_regs = sh64_show_regs;
2795 /* SH5 is handled entirely in sh64-tdep.c */
2796 return sh64_gdbarch_init (info, arches);
2799 /* If there is already a candidate, use it. */
2800 arches = gdbarch_list_lookup_by_info (arches, &info);
2802 return arches->gdbarch;
2804 /* None found, create a new architecture from the information
2806 gdbarch = gdbarch_alloc (&info, NULL);
2808 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2809 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2810 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2811 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2812 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2813 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2814 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2815 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2817 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2818 set_gdbarch_sp_regnum (gdbarch, 15);
2819 set_gdbarch_pc_regnum (gdbarch, 16);
2820 set_gdbarch_fp0_regnum (gdbarch, -1);
2821 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2823 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2824 set_gdbarch_register_reggroup_p (gdbarch, sh_register_reggroup_p);
2826 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2828 set_gdbarch_print_insn (gdbarch, print_insn_sh);
2829 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2831 set_gdbarch_return_value (gdbarch, sh_return_value_nofpu);
2833 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2834 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2836 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2838 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2840 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2841 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2842 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2843 set_gdbarch_dummy_id (gdbarch, sh_dummy_id);
2844 frame_base_set_default (gdbarch, &sh_frame_base);
2846 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2848 dwarf2_frame_set_init_reg (gdbarch, sh_dwarf2_frame_init_reg);
2850 switch (info.bfd_arch_info->mach)
2853 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2857 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2861 /* doubles on sh2e and sh3e are actually 4 byte. */
2862 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2864 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2865 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2866 set_gdbarch_fp0_regnum (gdbarch, 25);
2867 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2868 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2872 set_gdbarch_register_name (gdbarch, sh_sh2a_register_name);
2873 set_gdbarch_register_type (gdbarch, sh_sh2a_register_type);
2874 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2876 set_gdbarch_fp0_regnum (gdbarch, 25);
2877 set_gdbarch_num_pseudo_regs (gdbarch, 9);
2878 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2879 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2880 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2881 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2884 case bfd_mach_sh2a_nofpu:
2885 set_gdbarch_register_name (gdbarch, sh_sh2a_nofpu_register_name);
2886 set_gdbarch_register_sim_regno (gdbarch, sh_sh2a_register_sim_regno);
2888 set_gdbarch_num_pseudo_regs (gdbarch, 1);
2889 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2890 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2893 case bfd_mach_sh_dsp:
2894 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2895 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2899 case bfd_mach_sh3_nommu:
2900 case bfd_mach_sh2a_nofpu_or_sh3_nommu:
2901 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2905 case bfd_mach_sh2a_or_sh3e:
2906 /* doubles on sh2e and sh3e are actually 4 byte. */
2907 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2909 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2910 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2911 set_gdbarch_fp0_regnum (gdbarch, 25);
2912 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2913 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2916 case bfd_mach_sh3_dsp:
2917 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2918 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2923 case bfd_mach_sh2a_or_sh4:
2924 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2925 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2926 set_gdbarch_fp0_regnum (gdbarch, 25);
2927 set_gdbarch_num_pseudo_regs (gdbarch, 13);
2928 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2929 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2930 set_gdbarch_return_value (gdbarch, sh_return_value_fpu);
2931 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2934 case bfd_mach_sh4_nofpu:
2935 case bfd_mach_sh4a_nofpu:
2936 case bfd_mach_sh4_nommu_nofpu:
2937 case bfd_mach_sh2a_nofpu_or_sh4_nommu_nofpu:
2938 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2941 case bfd_mach_sh4al_dsp:
2942 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2943 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2947 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2951 /* Hook in ABI-specific overrides, if they have been registered. */
2952 gdbarch_init_osabi (info, gdbarch);
2954 dwarf2_append_unwinders (gdbarch);
2955 frame_unwind_append_unwinder (gdbarch, &sh_frame_unwind);
2961 show_sh_command (char *args, int from_tty)
2963 help_list (showshcmdlist, "show sh ", all_commands, gdb_stdout);
2967 set_sh_command (char *args, int from_tty)
2970 ("\"set sh\" must be followed by an appropriate subcommand.\n");
2971 help_list (setshcmdlist, "set sh ", all_commands, gdb_stdout);
2974 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2977 _initialize_sh_tdep (void)
2979 struct cmd_list_element *c;
2981 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2983 add_com ("regs", class_vars, sh_show_regs_command, _("Print all registers"));
2985 add_prefix_cmd ("sh", no_class, set_sh_command, "SH specific commands.",
2986 &setshcmdlist, "set sh ", 0, &setlist);
2987 add_prefix_cmd ("sh", no_class, show_sh_command, "SH specific commands.",
2988 &showshcmdlist, "show sh ", 0, &showlist);
2990 add_setshow_enum_cmd ("calling-convention", class_vars, sh_cc_enum,
2991 &sh_active_calling_convention,
2992 _("Set calling convention used when calling target "
2993 "functions from GDB."),
2994 _("Show calling convention used when calling target "
2995 "functions from GDB."),
2996 _("gcc - Use GCC calling convention (default).\n"
2997 "renesas - Enforce Renesas calling convention."),
2999 &setshcmdlist, &showshcmdlist);