1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
39 #include "gdb_string.h"
40 #include "gdb_assert.h"
41 #include "arch-utils.h"
42 #include "floatformat.h"
50 #include "solib-svr4.h"
54 /* registers numbers shared with the simulator */
55 #include "gdb/sim-sh.h"
57 static void (*sh_show_regs) (void);
59 #define SH_NUM_REGS 59
68 /* Flag showing that a frame has been created in the prologue code. */
71 /* Saved registers. */
72 CORE_ADDR saved_regs[SH_NUM_REGS];
77 sh_sh_register_name (int reg_nr)
79 static char *register_names[] = {
80 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
81 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
82 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
84 "", "", "", "", "", "", "", "",
85 "", "", "", "", "", "", "", "",
87 "", "", "", "", "", "", "", "",
88 "", "", "", "", "", "", "", "",
92 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return register_names[reg_nr];
98 sh_sh3_register_name (int reg_nr)
100 static char *register_names[] = {
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
108 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
109 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
113 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
115 return register_names[reg_nr];
119 sh_sh3e_register_name (int reg_nr)
121 static char *register_names[] = {
122 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
123 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
124 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
126 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
127 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
129 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
130 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
134 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
136 return register_names[reg_nr];
140 sh_sh2e_register_name (int reg_nr)
142 static char *register_names[] = {
143 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
144 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
145 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
147 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
148 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
155 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
157 return register_names[reg_nr];
161 sh_sh_dsp_register_name (int reg_nr)
163 static char *register_names[] = {
164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
169 "y0", "y1", "", "", "", "", "", "mod",
171 "rs", "re", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
176 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
178 return register_names[reg_nr];
182 sh_sh3_dsp_register_name (int reg_nr)
184 static char *register_names[] = {
185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
192 "rs", "re", "", "", "", "", "", "",
193 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
194 "", "", "", "", "", "", "", "",
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return register_names[reg_nr];
204 sh_sh4_register_name (int reg_nr)
206 static char *register_names[] = {
207 /* general registers 0-15 */
208 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
209 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
211 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
214 /* floating point registers 25 - 40 */
215 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
216 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
220 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
222 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
223 /* double precision (pseudo) 59 - 66 */
224 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
225 /* vectors (pseudo) 67 - 70 */
226 "fv0", "fv4", "fv8", "fv12",
227 /* FIXME: missing XF 71 - 86 */
228 /* FIXME: missing XD 87 - 94 */
232 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
234 return register_names[reg_nr];
238 sh_sh4_nofpu_register_name (int reg_nr)
240 static char *register_names[] = {
241 /* general registers 0-15 */
242 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
243 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
245 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
248 /* floating point registers 25 - 40 -- not for nofpu target */
249 "", "", "", "", "", "", "", "",
250 "", "", "", "", "", "", "", "",
254 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
256 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
257 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
258 "", "", "", "", "", "", "", "",
259 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
264 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
266 return register_names[reg_nr];
270 sh_sh4al_dsp_register_name (int reg_nr)
272 static char *register_names[] = {
273 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
274 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
275 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
277 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
278 "y0", "y1", "", "", "", "", "", "mod",
280 "rs", "re", "", "", "", "", "", "",
281 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
282 "", "", "", "", "", "", "", "",
286 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
288 return register_names[reg_nr];
291 static const unsigned char *
292 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
294 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
295 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
297 *lenptr = sizeof (breakpoint);
301 /* Prologue looks like
305 sub <room_for_loca_vars>,r15
308 Actually it can be more complicated than this but that's it, basically.
311 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
312 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
314 /* STS.L PR,@-r15 0100111100100010
315 r15-4-->r15, PR-->(r15) */
316 #define IS_STS(x) ((x) == 0x4f22)
318 /* MOV.L Rm,@-r15 00101111mmmm0110
319 r15-4-->r15, Rm-->(R15) */
320 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
322 /* MOV r15,r14 0110111011110011
324 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
326 /* ADD #imm,r15 01111111iiiiiiii
328 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
330 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
331 #define IS_SHLL_R3(x) ((x) == 0x4300)
333 /* ADD r3,r15 0011111100111100
335 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
337 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
338 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
339 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
340 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
341 make this entirely clear. */
342 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
343 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
345 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
346 #define IS_MOV_ARG_TO_REG(x) \
347 (((x) & 0xf00f) == 0x6003 && \
348 ((x) & 0x00f0) >= 0x0040 && \
349 ((x) & 0x00f0) <= 0x0070)
350 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
351 #define IS_MOV_ARG_TO_IND_R14(x) \
352 (((x) & 0xff0f) == 0x2e02 && \
353 ((x) & 0x00f0) >= 0x0040 && \
354 ((x) & 0x00f0) <= 0x0070)
355 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
356 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
357 (((x) & 0xff00) == 0x1e00 && \
358 ((x) & 0x00f0) >= 0x0040 && \
359 ((x) & 0x00f0) <= 0x0070)
361 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
362 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
363 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
364 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
365 /* SUB Rn,R15 00111111nnnn1000 */
366 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
368 #define FPSCR_SZ (1 << 20)
370 /* The following instructions are used for epilogue testing. */
371 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
372 #define IS_RTS(x) ((x) == 0x000b)
373 #define IS_LDS(x) ((x) == 0x4f26)
374 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
375 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
376 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
378 /* Disassemble an instruction. */
380 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
382 info->endian = TARGET_BYTE_ORDER;
383 return print_insn_sh (memaddr, info);
387 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
388 struct sh_frame_cache *cache)
395 int reg, sav_reg = -1;
397 if (pc >= current_pc)
401 for (opc = pc + (2 * 28); pc < opc; pc += 2)
403 inst = read_memory_unsigned_integer (pc, 2);
404 /* See where the registers will be saved to */
407 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
408 cache->sp_offset += 4;
410 else if (IS_STS (inst))
412 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
413 cache->sp_offset += 4;
415 else if (IS_MOV_R3 (inst))
417 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
419 else if (IS_SHLL_R3 (inst))
423 else if (IS_ADD_R3SP (inst))
425 cache->sp_offset += -r3_val;
427 else if (IS_ADD_IMM_SP (inst))
429 offset = ((inst & 0xff) ^ 0x80) - 0x80;
430 cache->sp_offset -= offset;
432 else if (IS_MOVW_PCREL_TO_REG (inst))
436 reg = GET_TARGET_REG (inst);
440 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
442 read_memory_integer (((pc + 4) & ~3) + offset, 2);
446 else if (IS_MOVL_PCREL_TO_REG (inst))
450 reg = (inst & 0x0f00) >> 8;
454 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
456 read_memory_integer (((pc + 4) & ~3) + offset, 4);
460 else if (IS_SUB_REG_FROM_SP (inst))
462 reg = GET_SOURCE_REG (inst);
463 if (sav_reg > 0 && reg == sav_reg)
467 cache->sp_offset += sav_offset;
469 else if (IS_FPUSH (inst))
471 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
473 cache->sp_offset += 8;
477 cache->sp_offset += 4;
480 else if (IS_MOV_SP_FP (inst))
484 /* At this point, only allow argument register moves to other
485 registers or argument register moves to @(X,fp) which are
486 moving the register arguments onto the stack area allocated
487 by a former add somenumber to SP call. Don't allow moving
488 to an fp indirect address above fp + cache->sp_offset. */
490 for (opc = pc + 12; pc < opc; pc += 2)
492 inst = read_memory_integer (pc, 2);
493 if (IS_MOV_ARG_TO_IND_R14 (inst))
495 reg = GET_SOURCE_REG (inst);
496 if (cache->sp_offset > 0)
497 cache->saved_regs[reg] = cache->sp_offset;
499 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
501 reg = GET_SOURCE_REG (inst);
502 offset = (inst & 0xf) * 4;
503 if (cache->sp_offset > offset)
504 cache->saved_regs[reg] = cache->sp_offset - offset;
506 else if (IS_MOV_ARG_TO_REG (inst))
513 #if 0 /* This used to just stop when it found an instruction that
514 was not considered part of the prologue. Now, we just
515 keep going looking for likely instructions. */
524 /* Skip any prologue before the guts of a function */
526 /* Skip the prologue using the debug information. If this fails we'll
527 fall back on the 'guess' method below. */
529 after_prologue (CORE_ADDR pc)
531 struct symtab_and_line sal;
532 CORE_ADDR func_addr, func_end;
534 /* If we can not find the symbol in the partial symbol table, then
535 there is no hope we can determine the function's start address
537 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
540 /* Get the line associated with FUNC_ADDR. */
541 sal = find_pc_line (func_addr, 0);
543 /* There are only two cases to consider. First, the end of the source line
544 is within the function bounds. In that case we return the end of the
545 source line. Second is the end of the source line extends beyond the
546 bounds of the current function. We need to use the slow code to
547 examine instructions in that case. */
548 if (sal.end < func_end)
555 sh_skip_prologue (CORE_ADDR start_pc)
558 struct sh_frame_cache cache;
560 /* See if we can determine the end of the prologue via the symbol table.
561 If so, then return either PC, or the PC after the prologue, whichever
563 pc = after_prologue (start_pc);
565 /* If after_prologue returned a useful address, then use it. Else
566 fall back on the instruction skipping code. */
568 return max (pc, start_pc);
570 cache.sp_offset = -4;
571 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
580 Aggregate types not bigger than 8 bytes that have the same size and
581 alignment as one of the integer scalar types are returned in the
582 same registers as the integer type they match.
584 For example, a 2-byte aligned structure with size 2 bytes has the
585 same size and alignment as a short int, and will be returned in R0.
586 A 4-byte aligned structure with size 8 bytes has the same size and
587 alignment as a long long int, and will be returned in R0 and R1.
589 When an aggregate type is returned in R0 and R1, R0 contains the
590 first four bytes of the aggregate, and R1 contains the
591 remainder. If the size of the aggregate type is not a multiple of 4
592 bytes, the aggregate is tail-padded up to a multiple of 4
593 bytes. The value of the padding is undefined. For little-endian
594 targets the padding will appear at the most significant end of the
595 last element, for big-endian targets the padding appears at the
596 least significant end of the last element.
598 All other aggregate types are returned by address. The caller
599 function passes the address of an area large enough to hold the
600 aggregate value in R2. The called function stores the result in
603 To reiterate, structs smaller than 8 bytes could also be returned
604 in memory, if they don't pass the "same size and alignment as an
609 struct s { char c[3]; } wibble;
610 struct s foo(void) { return wibble; }
612 the return value from foo() will be in memory, not
613 in R0, because there is no 3-byte integer type.
617 struct s { char c[2]; } wibble;
618 struct s foo(void) { return wibble; }
620 because a struct containing two chars has alignment 1, that matches
621 type char, but size 2, that matches type short. There's no integer
622 type that has alignment 1 and size 2, so the struct is returned in
628 sh_use_struct_convention (int gcc_p, struct type *type)
630 int len = TYPE_LENGTH (type);
631 int nelem = TYPE_NFIELDS (type);
633 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
634 fit in two registers anyway) use struct convention. */
635 if (len != 1 && len != 2 && len != 4 && len != 8)
638 /* Scalar types and aggregate types with exactly one field are aligned
639 by definition. They are returned in registers. */
643 /* If the first field in the aggregate has the same length as the entire
644 aggregate type, the type is returned in registers. */
645 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
648 /* If the size of the aggregate is 8 bytes and the first field is
649 of size 4 bytes its alignment is equal to long long's alignment,
650 so it's returned in registers. */
651 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
654 /* Otherwise use struct convention. */
658 /* Extract from an array REGBUF containing the (raw) register state
659 the address in which a function should return its structure value,
660 as a CORE_ADDR (or an expression that can be used as one). */
662 sh_extract_struct_value_address (struct regcache *regcache)
666 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
671 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
676 /* Function: push_dummy_call (formerly push_arguments)
677 Setup the function arguments for calling a function in the inferior.
679 On the Renesas SH architecture, there are four registers (R4 to R7)
680 which are dedicated for passing function arguments. Up to the first
681 four arguments (depending on size) may go into these registers.
682 The rest go on the stack.
684 MVS: Except on SH variants that have floating point registers.
685 In that case, float and double arguments are passed in the same
686 manner, but using FP registers instead of GP registers.
688 Arguments that are smaller than 4 bytes will still take up a whole
689 register or a whole 32-bit word on the stack, and will be
690 right-justified in the register or the stack word. This includes
691 chars, shorts, and small aggregate types.
693 Arguments that are larger than 4 bytes may be split between two or
694 more registers. If there are not enough registers free, an argument
695 may be passed partly in a register (or registers), and partly on the
696 stack. This includes doubles, long longs, and larger aggregates.
697 As far as I know, there is no upper limit to the size of aggregates
698 that will be passed in this way; in other words, the convention of
699 passing a pointer to a large aggregate instead of a copy is not used.
701 MVS: The above appears to be true for the SH variants that do not
702 have an FPU, however those that have an FPU appear to copy the
703 aggregate argument onto the stack (and not place it in registers)
704 if it is larger than 16 bytes (four GP registers).
706 An exceptional case exists for struct arguments (and possibly other
707 aggregates such as arrays) if the size is larger than 4 bytes but
708 not a multiple of 4 bytes. In this case the argument is never split
709 between the registers and the stack, but instead is copied in its
710 entirety onto the stack, AND also copied into as many registers as
711 there is room for. In other words, space in registers permitting,
712 two copies of the same argument are passed in. As far as I can tell,
713 only the one on the stack is used, although that may be a function
714 of the level of compiler optimization. I suspect this is a compiler
715 bug. Arguments of these odd sizes are left-justified within the
716 word (as opposed to arguments smaller than 4 bytes, which are
719 If the function is to return an aggregate type such as a struct, it
720 is either returned in the normal return value register R0 (if its
721 size is no greater than one byte), or else the caller must allocate
722 space into which the callee will copy the return value (if the size
723 is greater than one byte). In this case, a pointer to the return
724 value location is passed into the callee in register R2, which does
725 not displace any of the other arguments passed in via registers R4
728 /* Helper function to justify value in register according to endianess. */
730 sh_justify_value_in_reg (struct value *val, int len)
732 static char valbuf[4];
734 memset (valbuf, 0, sizeof (valbuf));
737 /* value gets right-justified in the register or stack word */
738 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
739 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
741 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
744 return (char *) VALUE_CONTENTS (val);
747 /* Helper function to eval number of bytes to allocate on stack. */
749 sh_stack_allocsize (int nargs, struct value **args)
753 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
757 /* Helper functions for getting the float arguments right. Registers usage
758 depends on the ABI and the endianess. The comments should enlighten how
759 it's intended to work. */
761 /* This array stores which of the float arg registers are already in use. */
762 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
764 /* This function just resets the above array to "no reg used so far". */
766 sh_init_flt_argreg (void)
768 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
771 /* This function returns the next register to use for float arg passing.
772 It returns either a valid value between FLOAT_ARG0_REGNUM and
773 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
774 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
776 Note that register number 0 in flt_argreg_array corresponds with the
777 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
778 29) the parity of the register number is preserved, which is important
779 for the double register passing test (see the "argreg & 1" test below). */
781 sh_next_flt_argreg (int len)
785 /* First search for the next free register. */
786 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
788 if (!flt_argreg_array[argreg])
791 /* No register left? */
792 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
793 return FLOAT_ARGLAST_REGNUM + 1;
797 /* Doubles are always starting in a even register number. */
800 flt_argreg_array[argreg] = 1;
804 /* No register left? */
805 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
806 return FLOAT_ARGLAST_REGNUM + 1;
808 /* Also mark the next register as used. */
809 flt_argreg_array[argreg + 1] = 1;
811 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
813 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
814 if (!flt_argreg_array[argreg + 1])
817 flt_argreg_array[argreg] = 1;
818 return FLOAT_ARG0_REGNUM + argreg;
821 /* Helper function which figures out, if a type is treated like a float type.
823 The FPU ABIs have a special way how to treat types as float types.
824 Structures with exactly one member, which is of type float or double, are
825 treated exactly as the base types float or double:
835 are handled the same way as just
841 As a result, arguments of these struct types are pushed into floating point
842 registers exactly as floats or doubles, using the same decision algorithm.
844 The same is valid if these types are used as function return types. The
845 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
846 or even using struct convention as it is for other structs. */
849 sh_treat_as_flt_p (struct type *type)
851 int len = TYPE_LENGTH (type);
853 /* Ordinary float types are obviously treated as float. */
854 if (TYPE_CODE (type) == TYPE_CODE_FLT)
856 /* Otherwise non-struct types are not treated as float. */
857 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
859 /* Otherwise structs with more than one memeber are not treated as float. */
860 if (TYPE_NFIELDS (type) != 1)
862 /* Otherwise if the type of that member is float, the whole type is
864 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
866 /* Otherwise it's not treated as float. */
871 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
873 struct regcache *regcache,
874 CORE_ADDR bp_addr, int nargs,
876 CORE_ADDR sp, int struct_return,
877 CORE_ADDR struct_addr)
879 int stack_offset = 0;
880 int argreg = ARG0_REGNUM;
886 int len, reg_size = 0;
887 int pass_on_stack = 0;
890 /* first force sp to a 4-byte alignment */
891 sp = sh_frame_align (gdbarch, sp);
894 regcache_cooked_write_unsigned (regcache,
895 STRUCT_RETURN_REGNUM, struct_addr);
897 /* make room on stack for args */
898 sp -= sh_stack_allocsize (nargs, args);
900 /* Initialize float argument mechanism. */
901 sh_init_flt_argreg ();
903 /* Now load as many as possible of the first arguments into
904 registers, and push the rest onto the stack. There are 16 bytes
905 in four registers available. Loop thru args from first to last. */
906 for (argnum = 0; argnum < nargs; argnum++)
908 type = VALUE_TYPE (args[argnum]);
909 len = TYPE_LENGTH (type);
910 val = sh_justify_value_in_reg (args[argnum], len);
912 /* Some decisions have to be made how various types are handled.
913 This also differs in different ABIs. */
916 /* Find out the next register to use for a floating point value. */
917 treat_as_flt = sh_treat_as_flt_p (type);
919 flt_argreg = sh_next_flt_argreg (len);
920 /* In contrast to non-FPU CPUs, arguments are never split between
921 registers and stack. If an argument doesn't fit in the remaining
922 registers it's always pushed entirely on the stack. */
923 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
928 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
929 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
932 /* The data goes entirely on the stack, 4-byte aligned. */
933 reg_size = (len + 3) & ~3;
934 write_memory (sp + stack_offset, val, reg_size);
935 stack_offset += reg_size;
937 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
939 /* Argument goes in a float argument register. */
940 reg_size = register_size (gdbarch, flt_argreg);
941 regval = extract_unsigned_integer (val, reg_size);
942 /* In little endian mode, float types taking two registers
943 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
944 be stored swapped in the argument registers. The below
945 code first writes the first 32 bits in the next but one
946 register, increments the val and len values accordingly
947 and then proceeds as normal by writing the second 32 bits
948 into the next register. */
949 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
950 && TYPE_LENGTH (type) == 2 * reg_size)
952 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
956 regval = extract_unsigned_integer (val, reg_size);
958 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
960 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
962 /* there's room in a register */
963 reg_size = register_size (gdbarch, argreg);
964 regval = extract_unsigned_integer (val, reg_size);
965 regcache_cooked_write_unsigned (regcache, argreg++, regval);
967 /* Store the value one register at a time or in one step on stack. */
973 /* Store return address. */
974 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
976 /* Update stack pointer. */
977 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
983 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
985 struct regcache *regcache,
987 int nargs, struct value **args,
988 CORE_ADDR sp, int struct_return,
989 CORE_ADDR struct_addr)
991 int stack_offset = 0;
992 int argreg = ARG0_REGNUM;
999 /* first force sp to a 4-byte alignment */
1000 sp = sh_frame_align (gdbarch, sp);
1003 regcache_cooked_write_unsigned (regcache,
1004 STRUCT_RETURN_REGNUM, struct_addr);
1006 /* make room on stack for args */
1007 sp -= sh_stack_allocsize (nargs, args);
1009 /* Now load as many as possible of the first arguments into
1010 registers, and push the rest onto the stack. There are 16 bytes
1011 in four registers available. Loop thru args from first to last. */
1012 for (argnum = 0; argnum < nargs; argnum++)
1014 type = VALUE_TYPE (args[argnum]);
1015 len = TYPE_LENGTH (type);
1016 val = sh_justify_value_in_reg (args[argnum], len);
1020 if (argreg > ARGLAST_REGNUM)
1022 /* The remainder of the data goes entirely on the stack,
1024 reg_size = (len + 3) & ~3;
1025 write_memory (sp + stack_offset, val, reg_size);
1026 stack_offset += reg_size;
1028 else if (argreg <= ARGLAST_REGNUM)
1030 /* there's room in a register */
1031 reg_size = register_size (gdbarch, argreg);
1032 regval = extract_unsigned_integer (val, reg_size);
1033 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1035 /* Store the value reg_size bytes at a time. This means that things
1036 larger than reg_size bytes may go partly in registers and partly
1043 /* Store return address. */
1044 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1046 /* Update stack pointer. */
1047 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1052 /* Find a function's return value in the appropriate registers (in
1053 regbuf), and copy it into valbuf. Extract from an array REGBUF
1054 containing the (raw) register state a function return value of type
1055 TYPE, and copy that, in virtual format, into VALBUF. */
1057 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1060 int len = TYPE_LENGTH (type);
1061 int return_register = R0_REGNUM;
1068 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1069 store_unsigned_integer (valbuf, len, c);
1073 int i, regnum = R0_REGNUM;
1074 for (i = 0; i < len; i += 4)
1075 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1078 error ("bad size for return value");
1082 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1085 if (sh_treat_as_flt_p (type))
1087 int len = TYPE_LENGTH (type);
1088 int i, regnum = FP0_REGNUM;
1089 for (i = 0; i < len; i += 4)
1090 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1091 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1093 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1096 sh_default_extract_return_value (type, regcache, valbuf);
1099 /* Write into appropriate registers a function return value
1100 of type TYPE, given in virtual format.
1101 If the architecture is sh4 or sh3e, store a function's return value
1102 in the R0 general register or in the FP0 floating point register,
1103 depending on the type of the return value. In all the other cases
1104 the result is stored in r0, left-justified. */
1106 sh_default_store_return_value (struct type *type, struct regcache *regcache,
1110 int len = TYPE_LENGTH (type);
1114 val = extract_unsigned_integer (valbuf, len);
1115 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1119 int i, regnum = R0_REGNUM;
1120 for (i = 0; i < len; i += 4)
1121 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1126 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1129 if (sh_treat_as_flt_p (type))
1131 int len = TYPE_LENGTH (type);
1132 int i, regnum = FP0_REGNUM;
1133 for (i = 0; i < len; i += 4)
1134 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1137 sh_default_store_return_value (type, regcache, valbuf);
1140 /* Print the registers in a form similar to the E7000 */
1143 sh_generic_show_regs (void)
1145 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1146 paddr (read_register (PC_REGNUM)),
1147 (long) read_register (SR_REGNUM),
1148 (long) read_register (PR_REGNUM),
1149 (long) read_register (MACH_REGNUM),
1150 (long) read_register (MACL_REGNUM));
1152 printf_filtered ("GBR=%08lx VBR=%08lx",
1153 (long) read_register (GBR_REGNUM),
1154 (long) read_register (VBR_REGNUM));
1157 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1158 (long) read_register (0), (long) read_register (1),
1159 (long) read_register (2), (long) read_register (3),
1160 (long) read_register (4), (long) read_register (5),
1161 (long) read_register (6), (long) read_register (7));
1162 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1163 (long) read_register (8), (long) read_register (9),
1164 (long) read_register (10), (long) read_register (11),
1165 (long) read_register (12), (long) read_register (13),
1166 (long) read_register (14), (long) read_register (15));
1170 sh3_show_regs (void)
1172 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1173 paddr (read_register (PC_REGNUM)),
1174 (long) read_register (SR_REGNUM),
1175 (long) read_register (PR_REGNUM),
1176 (long) read_register (MACH_REGNUM),
1177 (long) read_register (MACL_REGNUM));
1179 printf_filtered ("GBR=%08lx VBR=%08lx",
1180 (long) read_register (GBR_REGNUM),
1181 (long) read_register (VBR_REGNUM));
1182 printf_filtered (" SSR=%08lx SPC=%08lx",
1183 (long) read_register (SSR_REGNUM),
1184 (long) read_register (SPC_REGNUM));
1187 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1188 (long) read_register (0), (long) read_register (1),
1189 (long) read_register (2), (long) read_register (3),
1190 (long) read_register (4), (long) read_register (5),
1191 (long) read_register (6), (long) read_register (7));
1192 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1193 (long) read_register (8), (long) read_register (9),
1194 (long) read_register (10), (long) read_register (11),
1195 (long) read_register (12), (long) read_register (13),
1196 (long) read_register (14), (long) read_register (15));
1201 sh2e_show_regs (void)
1203 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1204 paddr (read_register (PC_REGNUM)),
1205 (long) read_register (SR_REGNUM),
1206 (long) read_register (PR_REGNUM),
1207 (long) read_register (MACH_REGNUM),
1208 (long) read_register (MACL_REGNUM));
1210 printf_filtered ("GBR=%08lx VBR=%08lx",
1211 (long) read_register (GBR_REGNUM),
1212 (long) read_register (VBR_REGNUM));
1213 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1214 (long) read_register (FPUL_REGNUM),
1215 (long) read_register (FPSCR_REGNUM));
1218 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1219 (long) read_register (0), (long) read_register (1),
1220 (long) read_register (2), (long) read_register (3),
1221 (long) read_register (4), (long) read_register (5),
1222 (long) read_register (6), (long) read_register (7));
1223 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1224 (long) read_register (8), (long) read_register (9),
1225 (long) read_register (10), (long) read_register (11),
1226 (long) read_register (12), (long) read_register (13),
1227 (long) read_register (14), (long) read_register (15));
1229 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1230 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1234 sh3e_show_regs (void)
1236 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1237 paddr (read_register (PC_REGNUM)),
1238 (long) read_register (SR_REGNUM),
1239 (long) read_register (PR_REGNUM),
1240 (long) read_register (MACH_REGNUM),
1241 (long) read_register (MACL_REGNUM));
1243 printf_filtered ("GBR=%08lx VBR=%08lx",
1244 (long) read_register (GBR_REGNUM),
1245 (long) read_register (VBR_REGNUM));
1246 printf_filtered (" SSR=%08lx SPC=%08lx",
1247 (long) read_register (SSR_REGNUM),
1248 (long) read_register (SPC_REGNUM));
1249 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1250 (long) read_register (FPUL_REGNUM),
1251 (long) read_register (FPSCR_REGNUM));
1254 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1255 (long) read_register (0), (long) read_register (1),
1256 (long) read_register (2), (long) read_register (3),
1257 (long) read_register (4), (long) read_register (5),
1258 (long) read_register (6), (long) read_register (7));
1259 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1260 (long) read_register (8), (long) read_register (9),
1261 (long) read_register (10), (long) read_register (11),
1262 (long) read_register (12), (long) read_register (13),
1263 (long) read_register (14), (long) read_register (15));
1265 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1266 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1270 sh3_dsp_show_regs (void)
1272 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1273 paddr (read_register (PC_REGNUM)),
1274 (long) read_register (SR_REGNUM),
1275 (long) read_register (PR_REGNUM),
1276 (long) read_register (MACH_REGNUM),
1277 (long) read_register (MACL_REGNUM));
1279 printf_filtered ("GBR=%08lx VBR=%08lx",
1280 (long) read_register (GBR_REGNUM),
1281 (long) read_register (VBR_REGNUM));
1283 printf_filtered (" SSR=%08lx SPC=%08lx",
1284 (long) read_register (SSR_REGNUM),
1285 (long) read_register (SPC_REGNUM));
1287 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1290 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1291 (long) read_register (0), (long) read_register (1),
1292 (long) read_register (2), (long) read_register (3),
1293 (long) read_register (4), (long) read_register (5),
1294 (long) read_register (6), (long) read_register (7));
1295 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1296 (long) read_register (8), (long) read_register (9),
1297 (long) read_register (10), (long) read_register (11),
1298 (long) read_register (12), (long) read_register (13),
1299 (long) read_register (14), (long) read_register (15));
1302 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1303 (long) read_register (A0G_REGNUM) & 0xff,
1304 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1305 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1306 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1307 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1308 (long) read_register (A1G_REGNUM) & 0xff,
1309 (long) read_register (A1_REGNUM),
1310 (long) read_register (M1_REGNUM),
1311 (long) read_register (X1_REGNUM),
1312 (long) read_register (Y1_REGNUM),
1313 (long) read_register (RE_REGNUM));
1317 sh4_show_regs (void)
1319 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1320 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1321 paddr (read_register (PC_REGNUM)),
1322 (long) read_register (SR_REGNUM),
1323 (long) read_register (PR_REGNUM),
1324 (long) read_register (MACH_REGNUM),
1325 (long) read_register (MACL_REGNUM));
1327 printf_filtered ("GBR=%08lx VBR=%08lx",
1328 (long) read_register (GBR_REGNUM),
1329 (long) read_register (VBR_REGNUM));
1330 printf_filtered (" SSR=%08lx SPC=%08lx",
1331 (long) read_register (SSR_REGNUM),
1332 (long) read_register (SPC_REGNUM));
1333 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1334 (long) read_register (FPUL_REGNUM),
1335 (long) read_register (FPSCR_REGNUM));
1338 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1339 (long) read_register (0), (long) read_register (1),
1340 (long) read_register (2), (long) read_register (3),
1341 (long) read_register (4), (long) read_register (5),
1342 (long) read_register (6), (long) read_register (7));
1343 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1344 (long) read_register (8), (long) read_register (9),
1345 (long) read_register (10), (long) read_register (11),
1346 (long) read_register (12), (long) read_register (13),
1347 (long) read_register (14), (long) read_register (15));
1349 printf_filtered ((pr
1350 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1352 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1353 (long) read_register (FP0_REGNUM + 0),
1354 (long) read_register (FP0_REGNUM + 1),
1355 (long) read_register (FP0_REGNUM + 2),
1356 (long) read_register (FP0_REGNUM + 3),
1357 (long) read_register (FP0_REGNUM + 4),
1358 (long) read_register (FP0_REGNUM + 5),
1359 (long) read_register (FP0_REGNUM + 6),
1360 (long) read_register (FP0_REGNUM + 7));
1361 printf_filtered ((pr ?
1362 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1363 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1364 (long) read_register (FP0_REGNUM + 8),
1365 (long) read_register (FP0_REGNUM + 9),
1366 (long) read_register (FP0_REGNUM + 10),
1367 (long) read_register (FP0_REGNUM + 11),
1368 (long) read_register (FP0_REGNUM + 12),
1369 (long) read_register (FP0_REGNUM + 13),
1370 (long) read_register (FP0_REGNUM + 14),
1371 (long) read_register (FP0_REGNUM + 15));
1375 sh4_nofpu_show_regs (void)
1377 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1378 paddr (read_register (PC_REGNUM)),
1379 (long) read_register (SR_REGNUM),
1380 (long) read_register (PR_REGNUM),
1381 (long) read_register (MACH_REGNUM),
1382 (long) read_register (MACL_REGNUM));
1384 printf_filtered ("GBR=%08lx VBR=%08lx",
1385 (long) read_register (GBR_REGNUM),
1386 (long) read_register (VBR_REGNUM));
1387 printf_filtered (" SSR=%08lx SPC=%08lx",
1388 (long) read_register (SSR_REGNUM),
1389 (long) read_register (SPC_REGNUM));
1392 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1393 (long) read_register (0), (long) read_register (1),
1394 (long) read_register (2), (long) read_register (3),
1395 (long) read_register (4), (long) read_register (5),
1396 (long) read_register (6), (long) read_register (7));
1397 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1398 (long) read_register (8), (long) read_register (9),
1399 (long) read_register (10), (long) read_register (11),
1400 (long) read_register (12), (long) read_register (13),
1401 (long) read_register (14), (long) read_register (15));
1405 sh_dsp_show_regs (void)
1407 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1408 paddr (read_register (PC_REGNUM)),
1409 (long) read_register (SR_REGNUM),
1410 (long) read_register (PR_REGNUM),
1411 (long) read_register (MACH_REGNUM),
1412 (long) read_register (MACL_REGNUM));
1414 printf_filtered ("GBR=%08lx VBR=%08lx",
1415 (long) read_register (GBR_REGNUM),
1416 (long) read_register (VBR_REGNUM));
1418 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1421 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1422 (long) read_register (0), (long) read_register (1),
1423 (long) read_register (2), (long) read_register (3),
1424 (long) read_register (4), (long) read_register (5),
1425 (long) read_register (6), (long) read_register (7));
1426 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1427 (long) read_register (8), (long) read_register (9),
1428 (long) read_register (10), (long) read_register (11),
1429 (long) read_register (12), (long) read_register (13),
1430 (long) read_register (14), (long) read_register (15));
1433 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1434 (long) read_register (A0G_REGNUM) & 0xff,
1435 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1436 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1437 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1438 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1439 (long) read_register (A1G_REGNUM) & 0xff,
1440 (long) read_register (A1_REGNUM),
1441 (long) read_register (M1_REGNUM),
1442 (long) read_register (X1_REGNUM),
1443 (long) read_register (Y1_REGNUM),
1444 (long) read_register (RE_REGNUM));
1448 sh_show_regs_command (char *args, int from_tty)
1454 /* Return the GDB type object for the "standard" data type
1455 of data in register N. */
1456 static struct type *
1457 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1459 if ((reg_nr >= FP0_REGNUM
1460 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1461 return builtin_type_float;
1463 return builtin_type_int;
1466 static struct type *
1467 sh_sh4_build_float_register_type (int high)
1471 temp = create_range_type (NULL, builtin_type_int, 0, high);
1472 return create_array_type (NULL, builtin_type_float, temp);
1475 static struct type *
1476 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1478 if ((reg_nr >= FP0_REGNUM
1479 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1480 return builtin_type_float;
1481 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1482 return builtin_type_double;
1483 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1484 return sh_sh4_build_float_register_type (3);
1486 return builtin_type_int;
1489 static struct type *
1490 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1492 return builtin_type_int;
1495 /* On the sh4, the DRi pseudo registers are problematic if the target
1496 is little endian. When the user writes one of those registers, for
1497 instance with 'ser var $dr0=1', we want the double to be stored
1499 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1500 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1502 This corresponds to little endian byte order & big endian word
1503 order. However if we let gdb write the register w/o conversion, it
1504 will write fr0 and fr1 this way:
1505 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1506 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1507 because it will consider fr0 and fr1 as a single LE stretch of memory.
1509 To achieve what we want we must force gdb to store things in
1510 floatformat_ieee_double_littlebyte_bigword (which is defined in
1511 include/floatformat.h and libiberty/floatformat.c.
1513 In case the target is big endian, there is no problem, the
1514 raw bytes will look like:
1515 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1516 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1518 The other pseudo registers (the FVs) also don't pose a problem
1519 because they are stored as 4 individual FP elements. */
1522 sh_register_convert_to_virtual (int regnum, struct type *type,
1523 char *from, char *to)
1525 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1528 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1530 store_typed_floating (to, type, val);
1534 ("sh_register_convert_to_virtual called with non DR register number");
1538 sh_register_convert_to_raw (struct type *type, int regnum,
1539 const void *from, void *to)
1541 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1543 DOUBLEST val = extract_typed_floating (from, type);
1544 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1548 error ("sh_register_convert_to_raw called with non DR register number");
1551 /* For vectors of 4 floating point registers. */
1553 fv_reg_base_num (int fv_regnum)
1557 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1561 /* For double precision floating point registers, i.e 2 fp regs.*/
1563 dr_reg_base_num (int dr_regnum)
1567 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1572 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1573 int reg_nr, void *buffer)
1575 int base_regnum, portion;
1576 char temp_buffer[MAX_REGISTER_SIZE];
1578 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1580 base_regnum = dr_reg_base_num (reg_nr);
1582 /* Build the value in the provided buffer. */
1583 /* Read the real regs for which this one is an alias. */
1584 for (portion = 0; portion < 2; portion++)
1585 regcache_raw_read (regcache, base_regnum + portion,
1587 + register_size (gdbarch,
1588 base_regnum) * portion));
1589 /* We must pay attention to the endiannes. */
1590 sh_register_convert_to_virtual (reg_nr,
1591 gdbarch_register_type (gdbarch, reg_nr),
1592 temp_buffer, buffer);
1594 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1596 base_regnum = fv_reg_base_num (reg_nr);
1598 /* Read the real regs for which this one is an alias. */
1599 for (portion = 0; portion < 4; portion++)
1600 regcache_raw_read (regcache, base_regnum + portion,
1602 + register_size (gdbarch,
1603 base_regnum) * portion));
1608 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1609 int reg_nr, const void *buffer)
1611 int base_regnum, portion;
1612 char temp_buffer[MAX_REGISTER_SIZE];
1614 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1616 base_regnum = dr_reg_base_num (reg_nr);
1618 /* We must pay attention to the endiannes. */
1619 sh_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1620 reg_nr, buffer, temp_buffer);
1622 /* Write the real regs for which this one is an alias. */
1623 for (portion = 0; portion < 2; portion++)
1624 regcache_raw_write (regcache, base_regnum + portion,
1626 + register_size (gdbarch,
1627 base_regnum) * portion));
1629 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1631 base_regnum = fv_reg_base_num (reg_nr);
1633 /* Write the real regs for which this one is an alias. */
1634 for (portion = 0; portion < 4; portion++)
1635 regcache_raw_write (regcache, base_regnum + portion,
1637 + register_size (gdbarch,
1638 base_regnum) * portion));
1642 /* Floating point vector of 4 float registers. */
1644 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1647 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1648 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1649 fv_regnum - FV0_REGNUM,
1650 (int) read_register (first_fp_reg_num),
1651 (int) read_register (first_fp_reg_num + 1),
1652 (int) read_register (first_fp_reg_num + 2),
1653 (int) read_register (first_fp_reg_num + 3));
1656 /* Double precision registers. */
1658 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1661 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1663 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1664 dr_regnum - DR0_REGNUM,
1665 (int) read_register (first_fp_reg_num),
1666 (int) read_register (first_fp_reg_num + 1));
1670 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1673 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1674 internal_error (__FILE__, __LINE__,
1675 "Invalid pseudo register number %d\n", regnum);
1676 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1677 do_dr_register_info (gdbarch, file, regnum);
1678 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1679 do_fv_register_info (gdbarch, file, regnum);
1683 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1684 { /* do values for FP (float) regs */
1686 double flt; /* double extracted from raw hex data */
1690 /* Allocate space for the float. */
1691 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1693 /* Get the data in raw format. */
1694 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1695 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1697 /* Get the register as a number */
1698 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1700 /* Print the name and some spaces. */
1701 fputs_filtered (REGISTER_NAME (regnum), file);
1702 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1704 /* Print the value. */
1706 fprintf_filtered (file, "<invalid float>");
1708 fprintf_filtered (file, "%-10.9g", flt);
1710 /* Print the fp register as hex. */
1711 fprintf_filtered (file, "\t(raw 0x");
1712 for (j = 0; j < register_size (gdbarch, regnum); j++)
1714 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1716 : register_size (gdbarch, regnum) - 1 - j);
1717 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1719 fprintf_filtered (file, ")");
1720 fprintf_filtered (file, "\n");
1724 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1726 char raw_buffer[MAX_REGISTER_SIZE];
1728 fputs_filtered (REGISTER_NAME (regnum), file);
1729 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1731 /* Get the data in raw format. */
1732 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1733 fprintf_filtered (file, "*value not available*\n");
1735 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1736 file, 'x', 1, 0, Val_pretty_default);
1737 fprintf_filtered (file, "\t");
1738 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1739 file, 0, 1, 0, Val_pretty_default);
1740 fprintf_filtered (file, "\n");
1744 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1746 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1747 internal_error (__FILE__, __LINE__,
1748 "Invalid register number %d\n", regnum);
1750 else if (regnum >= 0 && regnum < NUM_REGS)
1752 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1754 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1756 sh_do_register (gdbarch, file, regnum); /* All other regs */
1759 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1761 sh_print_pseudo_register (gdbarch, file, regnum);
1766 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1767 struct frame_info *frame, int regnum, int fpregs)
1769 if (regnum != -1) /* do one specified register */
1771 if (*(REGISTER_NAME (regnum)) == '\0')
1772 error ("Not a valid register for the current processor type");
1774 sh_print_register (gdbarch, file, regnum);
1777 /* do all (or most) registers */
1780 while (regnum < NUM_REGS)
1782 /* If the register name is empty, it is undefined for this
1783 processor, so don't display anything. */
1784 if (REGISTER_NAME (regnum) == NULL
1785 || *(REGISTER_NAME (regnum)) == '\0')
1791 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1796 /* true for "INFO ALL-REGISTERS" command */
1797 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1801 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
1805 sh_do_register (gdbarch, file, regnum); /* All other regs */
1811 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1813 sh_print_pseudo_register (gdbarch, file, regnum);
1819 #ifdef SVR4_SHARED_LIBS
1821 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1822 for native i386 linux targets using the struct offsets defined in
1823 link.h (but without actual reference to that file).
1825 This makes it possible to access i386-linux shared libraries from
1826 a gdb that was not built on an i386-linux host (for cross debugging).
1829 struct link_map_offsets *
1830 sh_linux_svr4_fetch_link_map_offsets (void)
1832 static struct link_map_offsets lmo;
1833 static struct link_map_offsets *lmp = 0;
1839 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1841 lmo.r_map_offset = 4;
1844 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1846 lmo.l_addr_offset = 0;
1847 lmo.l_addr_size = 4;
1849 lmo.l_name_offset = 4;
1850 lmo.l_name_size = 4;
1852 lmo.l_next_offset = 12;
1853 lmo.l_next_size = 4;
1855 lmo.l_prev_offset = 16;
1856 lmo.l_prev_size = 4;
1861 #endif /* SVR4_SHARED_LIBS */
1864 sh_dsp_register_sim_regno (int nr)
1866 if (legacy_register_sim_regno (nr) < 0)
1867 return legacy_register_sim_regno (nr);
1868 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1869 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1870 if (nr == MOD_REGNUM)
1871 return SIM_SH_MOD_REGNUM;
1872 if (nr == RS_REGNUM)
1873 return SIM_SH_RS_REGNUM;
1874 if (nr == RE_REGNUM)
1875 return SIM_SH_RE_REGNUM;
1876 if (nr >= R0_BANK_REGNUM && nr <= R7_BANK_REGNUM)
1877 return nr - R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1881 static struct sh_frame_cache *
1882 sh_alloc_frame_cache (void)
1884 struct sh_frame_cache *cache;
1887 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1891 cache->saved_sp = 0;
1892 cache->sp_offset = 0;
1895 /* Frameless until proven otherwise. */
1898 /* Saved registers. We initialize these to -1 since zero is a valid
1899 offset (that's where fp is supposed to be stored). */
1900 for (i = 0; i < SH_NUM_REGS; i++)
1902 cache->saved_regs[i] = -1;
1908 static struct sh_frame_cache *
1909 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1911 struct sh_frame_cache *cache;
1912 CORE_ADDR current_pc;
1918 cache = sh_alloc_frame_cache ();
1919 *this_cache = cache;
1921 /* In principle, for normal frames, fp holds the frame pointer,
1922 which holds the base address for the current stack frame.
1923 However, for functions that don't need it, the frame pointer is
1924 optional. For these "frameless" functions the frame pointer is
1925 actually the frame pointer of the calling frame. */
1926 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1927 if (cache->base == 0)
1930 cache->pc = frame_func_unwind (next_frame);
1931 current_pc = frame_pc_unwind (next_frame);
1933 sh_analyze_prologue (cache->pc, current_pc, cache);
1935 if (!cache->uses_fp)
1937 /* We didn't find a valid frame, which means that CACHE->base
1938 currently holds the frame pointer for our calling frame. If
1939 we're at the start of a function, or somewhere half-way its
1940 prologue, the function's frame probably hasn't been fully
1941 setup yet. Try to reconstruct the base address for the stack
1942 frame by looking at the stack pointer. For truly "frameless"
1943 functions this might work too. */
1944 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1947 /* Now that we have the base address for the stack frame we can
1948 calculate the value of sp in the calling frame. */
1949 cache->saved_sp = cache->base + cache->sp_offset;
1951 /* Adjust all the saved registers such that they contain addresses
1952 instead of offsets. */
1953 for (i = 0; i < SH_NUM_REGS; i++)
1954 if (cache->saved_regs[i] != -1)
1955 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1961 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1962 int regnum, int *optimizedp,
1963 enum lval_type *lvalp, CORE_ADDR *addrp,
1964 int *realnump, void *valuep)
1966 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1968 gdb_assert (regnum >= 0);
1970 if (regnum == SP_REGNUM && cache->saved_sp)
1978 /* Store the value. */
1979 store_unsigned_integer (valuep, 4, cache->saved_sp);
1984 /* The PC of the previous frame is stored in the PR register of
1985 the current frame. Frob regnum so that we pull the value from
1986 the correct place. */
1987 if (regnum == PC_REGNUM)
1990 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
1993 *lvalp = lval_memory;
1994 *addrp = cache->saved_regs[regnum];
1998 /* Read the value in from memory. */
1999 read_memory (*addrp, valuep,
2000 register_size (current_gdbarch, regnum));
2005 frame_register_unwind (next_frame, regnum,
2006 optimizedp, lvalp, addrp, realnump, valuep);
2010 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2011 struct frame_id *this_id)
2013 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2015 /* This marks the outermost frame. */
2016 if (cache->base == 0)
2019 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2022 static const struct frame_unwind sh_frame_unwind = {
2025 sh_frame_prev_register
2028 static const struct frame_unwind *
2029 sh_frame_sniffer (struct frame_info *next_frame)
2031 return &sh_frame_unwind;
2035 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2037 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2041 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2043 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2046 static struct frame_id
2047 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2049 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2050 frame_pc_unwind (next_frame));
2054 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2056 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2061 static const struct frame_base sh_frame_base = {
2063 sh_frame_base_address,
2064 sh_frame_base_address,
2065 sh_frame_base_address
2068 /* The epilogue is defined here as the area at the end of a function,
2069 either on the `ret' instruction itself or after an instruction which
2070 destroys the function's stack frame. */
2072 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2074 CORE_ADDR func_addr = 0, func_end = 0;
2076 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2079 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2080 for a nop and some fixed data (e.g. big offsets) which are
2081 unfortunately also treated as part of the function (which
2082 means, they are below func_end. */
2083 CORE_ADDR addr = func_end - 28;
2084 if (addr < func_addr + 4)
2085 addr = func_addr + 4;
2089 /* First search forward until hitting an rts. */
2090 while (addr < func_end
2091 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2093 if (addr >= func_end)
2096 /* At this point we should find a mov.l @r15+,r14 instruction,
2097 either before or after the rts. If not, then the function has
2098 probably no "normal" epilogue and we bail out here. */
2099 inst = read_memory_unsigned_integer (addr - 2, 2);
2100 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2102 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2105 /* Step over possible lds.l @r15+,pr. */
2106 inst = read_memory_unsigned_integer (addr - 2, 2);
2110 inst = read_memory_unsigned_integer (addr - 2, 2);
2113 /* Step over possible mov r14,r15. */
2114 if (IS_MOV_FP_SP (inst))
2117 inst = read_memory_unsigned_integer (addr - 2, 2);
2120 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2122 while (addr > func_addr + 4
2123 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2126 inst = read_memory_unsigned_integer (addr - 2, 2);
2135 static gdbarch_init_ftype sh_gdbarch_init;
2137 static struct gdbarch *
2138 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2140 struct gdbarch *gdbarch;
2142 sh_show_regs = sh_generic_show_regs;
2143 switch (info.bfd_arch_info->mach)
2146 sh_show_regs = sh2e_show_regs;
2148 case bfd_mach_sh_dsp:
2149 sh_show_regs = sh_dsp_show_regs;
2153 sh_show_regs = sh3_show_regs;
2157 sh_show_regs = sh3e_show_regs;
2160 case bfd_mach_sh3_dsp:
2161 case bfd_mach_sh4al_dsp:
2162 sh_show_regs = sh3_dsp_show_regs;
2167 sh_show_regs = sh4_show_regs;
2170 case bfd_mach_sh4_nofpu:
2171 case bfd_mach_sh4a_nofpu:
2172 sh_show_regs = sh4_nofpu_show_regs;
2176 sh_show_regs = sh64_show_regs;
2177 /* SH5 is handled entirely in sh64-tdep.c */
2178 return sh64_gdbarch_init (info, arches);
2181 /* If there is already a candidate, use it. */
2182 arches = gdbarch_list_lookup_by_info (arches, &info);
2184 return arches->gdbarch;
2186 /* None found, create a new architecture from the information
2188 gdbarch = gdbarch_alloc (&info, NULL);
2190 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2191 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2192 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2193 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2194 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2195 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2196 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2197 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2199 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2200 set_gdbarch_sp_regnum (gdbarch, 15);
2201 set_gdbarch_pc_regnum (gdbarch, 16);
2202 set_gdbarch_fp0_regnum (gdbarch, -1);
2203 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2205 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2207 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2209 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2210 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2212 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2213 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2215 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2217 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2218 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2219 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2221 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2222 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2224 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2226 set_gdbarch_deprecated_frameless_function_invocation (gdbarch, legacy_frameless_look_for_prologue);
2227 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2229 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2230 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2231 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2232 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2233 frame_base_set_default (gdbarch, &sh_frame_base);
2235 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2237 switch (info.bfd_arch_info->mach)
2240 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2244 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2248 /* doubles on sh2e and sh3e are actually 4 byte. */
2249 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2251 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2252 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2253 set_gdbarch_fp0_regnum (gdbarch, 25);
2254 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2255 set_gdbarch_extract_return_value (gdbarch,
2256 sh3e_sh4_extract_return_value);
2257 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2260 case bfd_mach_sh_dsp:
2261 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2262 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2266 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2270 /* doubles on sh2e and sh3e are actually 4 byte. */
2271 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2273 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2274 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2275 set_gdbarch_fp0_regnum (gdbarch, 25);
2276 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2277 set_gdbarch_extract_return_value (gdbarch,
2278 sh3e_sh4_extract_return_value);
2279 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2282 case bfd_mach_sh3_dsp:
2283 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2284 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2289 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2290 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2291 set_gdbarch_fp0_regnum (gdbarch, 25);
2292 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2293 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2294 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2295 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2296 set_gdbarch_extract_return_value (gdbarch,
2297 sh3e_sh4_extract_return_value);
2298 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2301 case bfd_mach_sh4_nofpu:
2302 case bfd_mach_sh4a_nofpu:
2303 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2306 case bfd_mach_sh4al_dsp:
2307 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2308 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2312 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2316 /* Hook in ABI-specific overrides, if they have been registered. */
2317 gdbarch_init_osabi (info, gdbarch);
2319 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2320 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2325 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2328 _initialize_sh_tdep (void)
2330 struct cmd_list_element *c;
2332 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2334 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");