1 /* Target-dependent code for Hitachi Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
36 #include "inferior.h" /* for BEFORE_TEXT_END etc. */
37 #include "gdb_string.h"
38 #include "arch-utils.h"
39 #include "floatformat.h"
47 #include "solib-svr4.h"
51 /* registers numbers shared with the simulator */
52 #include "gdb/sim-sh.h"
54 void (*sh_show_regs) (void);
55 CORE_ADDR (*skip_prologue_hard_way) (CORE_ADDR);
56 void (*do_pseudo_register) (int);
58 #define SH_DEFAULT_NUM_REGS 59
60 /* Define other aspects of the stack frame.
61 we keep a copy of the worked out return pc lying around, since it
62 is a useful bit of info */
64 struct frame_extra_info
72 sh_generic_register_name (int reg_nr)
74 static char *register_names[] =
76 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
77 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
78 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
80 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
81 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
83 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
84 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
88 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
90 return register_names[reg_nr];
94 sh_sh_register_name (int reg_nr)
96 static char *register_names[] =
98 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
99 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
100 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
102 "", "", "", "", "", "", "", "",
103 "", "", "", "", "", "", "", "",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
110 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
112 return register_names[reg_nr];
116 sh_sh3_register_name (int reg_nr)
118 static char *register_names[] =
120 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
121 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
122 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
124 "", "", "", "", "", "", "", "",
125 "", "", "", "", "", "", "", "",
127 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
128 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
132 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
134 return register_names[reg_nr];
138 sh_sh3e_register_name (int reg_nr)
140 static char *register_names[] =
142 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
143 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
144 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
146 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
147 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
149 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
150 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
154 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
156 return register_names[reg_nr];
160 sh_sh_dsp_register_name (int reg_nr)
162 static char *register_names[] =
164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
169 "y0", "y1", "", "", "", "", "", "mod",
171 "rs", "re", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
176 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
178 return register_names[reg_nr];
182 sh_sh3_dsp_register_name (int reg_nr)
184 static char *register_names[] =
186 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
187 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
188 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
190 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
191 "y0", "y1", "", "", "", "", "", "mod",
193 "rs", "re", "", "", "", "", "", "",
194 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b"
195 "", "", "", "", "", "", "", "",
199 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
201 return register_names[reg_nr];
205 sh_sh4_register_name (int reg_nr)
207 static char *register_names[] =
209 /* general registers 0-15 */
210 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
211 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
213 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
216 /* floating point registers 25 - 40 */
217 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
218 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
222 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
224 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
225 /* double precision (pseudo) 59 - 66 */
226 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
227 /* vectors (pseudo) 67 - 70 */
228 "fv0", "fv4", "fv8", "fv12",
229 /* FIXME: missing XF 71 - 86 */
230 /* FIXME: missing XD 87 - 94 */
234 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
236 return register_names[reg_nr];
240 sh_sh64_register_name (int reg_nr)
242 static char *register_names[] =
244 /* SH MEDIA MODE (ISA 32) */
245 /* general registers (64-bit) 0-63 */
246 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
247 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
248 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
249 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
250 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
251 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
252 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55",
253 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63",
258 /* status reg., saved status reg., saved pc reg. (64-bit) 65-67 */
261 /* target registers (64-bit) 68-75*/
262 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7",
264 /* floating point state control register (32-bit) 76 */
267 /* single precision floating point registers (32-bit) 77-140*/
268 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
269 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
270 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23",
271 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31",
272 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39",
273 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47",
274 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55",
275 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63",
277 /* double precision registers (pseudo) 141-172 */
278 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
279 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30",
280 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46",
281 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62",
283 /* floating point pairs (pseudo) 173-204*/
284 "fp0", "fp2", "fp4", "fp6", "fp8", "fp10", "fp12", "fp14",
285 "fp16", "fp18", "fp20", "fp22", "fp24", "fp26", "fp28", "fp30",
286 "fp32", "fp34", "fp36", "fp38", "fp40", "fp42", "fp44", "fp46",
287 "fp48", "fp50", "fp52", "fp54", "fp56", "fp58", "fp60", "fp62",
289 /* floating point vectors (4 floating point regs) (pseudo) 205-220*/
290 "fv0", "fv4", "fv8", "fv12", "fv16", "fv20", "fv24", "fv28",
291 "fv32", "fv36", "fv40", "fv44", "fv48", "fv52", "fv56", "fv60",
293 /* SH COMPACT MODE (ISA 16) (all pseudo) 221-272*/
294 "r0_c", "r1_c", "r2_c", "r3_c", "r4_c", "r5_c", "r6_c", "r7_c",
295 "r8_c", "r9_c", "r10_c", "r11_c", "r12_c", "r13_c", "r14_c", "r15_c",
297 "gbr_c", "mach_c", "macl_c", "pr_c", "t_c",
299 "fr0_c", "fr1_c", "fr2_c", "fr3_c", "fr4_c", "fr5_c", "fr6_c", "fr7_c",
300 "fr8_c", "fr9_c", "fr10_c", "fr11_c", "fr12_c", "fr13_c", "fr14_c", "fr15_c",
301 "dr0_c", "dr2_c", "dr4_c", "dr6_c", "dr8_c", "dr10_c", "dr12_c", "dr14_c",
302 "fv0_c", "fv4_c", "fv8_c", "fv12_c",
303 /* FIXME!!!! XF0 XF15, XD0 XD14 ?????*/
308 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
310 return register_names[reg_nr];
313 #define NUM_PSEUDO_REGS_SH_MEDIA 80
314 #define NUM_PSEUDO_REGS_SH_COMPACT 51
316 static const unsigned char *
317 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
319 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
320 static unsigned char breakpoint[] = {0xc3, 0xc3};
322 *lenptr = sizeof (breakpoint);
326 /* Macros and functions for setting and testing a bit in a minimal
327 symbol that marks it as 32-bit function. The MSB of the minimal
328 symbol's "info" field is used for this purpose. This field is
329 already being used to store the symbol size, so the assumption is
330 that the symbol size cannot exceed 2^31.
332 ELF_MAKE_MSYMBOL_SPECIAL
333 tests whether an ELF symbol is "special", i.e. refers
334 to a 32-bit function, and sets a "special" bit in a
335 minimal symbol to mark it as a 32-bit function
336 MSYMBOL_IS_SPECIAL tests the "special" bit in a minimal symbol
337 MSYMBOL_SIZE returns the size of the minimal symbol, i.e.
338 the "info" field with the "special" bit masked out */
340 #define MSYMBOL_IS_SPECIAL(msym) \
341 (((long) MSYMBOL_INFO (msym) & 0x80000000) != 0)
344 sh64_elf_make_msymbol_special (asymbol *sym, struct minimal_symbol *msym)
349 if (((elf_symbol_type *)(sym))->internal_elf_sym.st_other == STO_SH5_ISA32)
351 MSYMBOL_INFO (msym) = (char *) (((long) MSYMBOL_INFO (msym)) | 0x80000000);
352 SYMBOL_VALUE_ADDRESS (msym) |= 1;
356 /* ISA32 (shmedia) function addresses are odd (bit 0 is set). Here
357 are some macros to test, set, or clear bit 0 of addresses. */
358 #define IS_ISA32_ADDR(addr) ((addr) & 1)
359 #define MAKE_ISA32_ADDR(addr) ((addr) | 1)
360 #define UNMAKE_ISA32_ADDR(addr) ((addr) & ~1)
363 pc_is_isa32 (bfd_vma memaddr)
365 struct minimal_symbol *sym;
367 /* If bit 0 of the address is set, assume this is a
368 ISA32 (shmedia) address. */
369 if (IS_ISA32_ADDR (memaddr))
372 /* A flag indicating that this is a ISA32 function is stored by elfread.c in
373 the high bit of the info field. Use this to decide if the function is
375 sym = lookup_minimal_symbol_by_pc (memaddr);
377 return MSYMBOL_IS_SPECIAL (sym);
382 static const unsigned char *
383 sh_sh64_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
385 /* The BRK instruction for shmedia is
386 01101111 11110101 11111111 11110000
387 which translates in big endian mode to 0x6f, 0xf5, 0xff, 0xf0
388 and in little endian mode to 0xf0, 0xff, 0xf5, 0x6f */
390 /* The BRK instruction for shcompact is
392 which translates in big endian mode to 0x0, 0x3b
393 and in little endian mode to 0x3b, 0x0*/
395 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
397 if (pc_is_isa32 (*pcptr))
399 static unsigned char big_breakpoint_media[] = {0x6f, 0xf5, 0xff, 0xf0};
400 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
401 *lenptr = sizeof (big_breakpoint_media);
402 return big_breakpoint_media;
406 static unsigned char big_breakpoint_compact[] = {0x0, 0x3b};
407 *lenptr = sizeof (big_breakpoint_compact);
408 return big_breakpoint_compact;
413 if (pc_is_isa32 (*pcptr))
415 static unsigned char little_breakpoint_media[] = {0xf0, 0xff, 0xf5, 0x6f};
416 *pcptr = UNMAKE_ISA32_ADDR (*pcptr);
417 *lenptr = sizeof (little_breakpoint_media);
418 return little_breakpoint_media;
422 static unsigned char little_breakpoint_compact[] = {0x3b, 0x0};
423 *lenptr = sizeof (little_breakpoint_compact);
424 return little_breakpoint_compact;
429 /* Prologue looks like
430 [mov.l <regs>,@-r15]...
435 Actually it can be more complicated than this. For instance, with
453 /* PTABS/L Rn, TRa 0110101111110001nnnnnnl00aaa0000
454 with l=1 and n = 18 0110101111110001010010100aaa0000 */
455 #define IS_PTABSL_R18(x) (((x) & 0xffffff8f) == 0x6bf14a00)
457 /* STS.L PR,@-r0 0100000000100010
458 r0-4-->r0, PR-->(r0) */
459 #define IS_STS_R0(x) ((x) == 0x4022)
461 /* STS PR, Rm 0000mmmm00101010
463 #define IS_STS_PR(x) (((x) & 0xf0ff) == 0x2a)
465 /* MOV.L Rm,@(disp,r15) 00011111mmmmdddd
467 #define IS_MOV_TO_R15(x) (((x) & 0xff00) == 0x1f00)
469 /* MOV.L R14,@(disp,r15) 000111111110dddd
470 R14-->(dispx4+r15) */
471 #define IS_MOV_R14(x) (((x) & 0xfff0) == 0x1fe0)
473 /* ST.Q R14, disp, R18 101011001110dddddddddd0100100000
474 R18-->(dispx8+R14) */
475 #define IS_STQ_R18_R14(x) (((x) & 0xfff003ff) == 0xace00120)
477 /* ST.Q R15, disp, R18 101011001111dddddddddd0100100000
478 R18-->(dispx8+R15) */
479 #define IS_STQ_R18_R15(x) (((x) & 0xfff003ff) == 0xacf00120)
481 /* ST.L R15, disp, R18 101010001111dddddddddd0100100000
482 R18-->(dispx4+R15) */
483 #define IS_STL_R18_R15(x) (((x) & 0xfff003ff) == 0xa8f00120)
485 /* ST.Q R15, disp, R14 1010 1100 1111 dddd dddd dd00 1110 0000
486 R14-->(dispx8+R15) */
487 #define IS_STQ_R14_R15(x) (((x) & 0xfff003ff) == 0xacf000e0)
489 /* ST.L R15, disp, R14 1010 1000 1111 dddd dddd dd00 1110 0000
490 R14-->(dispx4+R15) */
491 #define IS_STL_R14_R15(x) (((x) & 0xfff003ff) == 0xa8f000e0)
493 /* ADDI.L R15,imm,R15 1101 0100 1111 ssss ssss ss00 1111 0000
495 #define IS_ADDIL_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd4f000f0)
497 /* ADDI R15,imm,R15 1101 0000 1111 ssss ssss ss00 1111 0000
499 #define IS_ADDI_SP_MEDIA(x) (((x) & 0xfff003ff) == 0xd0f000f0)
501 /* ADD.L R15,R63,R14 0000 0000 1111 1000 1111 1100 1110 0000
503 #define IS_ADDL_SP_FP_MEDIA(x) ((x) == 0x00f8fce0)
505 /* ADD R15,R63,R14 0000 0000 1111 1001 1111 1100 1110 0000
507 #define IS_ADD_SP_FP_MEDIA(x) ((x) == 0x00f9fce0)
509 #define IS_MOV_SP_FP_MEDIA(x) (IS_ADDL_SP_FP_MEDIA(x) || IS_ADD_SP_FP_MEDIA(x))
511 /* MOV #imm, R0 1110 0000 ssss ssss
513 #define IS_MOV_R0(x) (((x) & 0xff00) == 0xe000)
515 /* MOV.L @(disp,PC), R0 1101 0000 iiii iiii */
516 #define IS_MOVL_R0(x) (((x) & 0xff00) == 0xd000)
518 /* ADD r15,r0 0011 0000 1111 1100
520 #define IS_ADD_SP_R0(x) ((x) == 0x30fc)
522 /* MOV.L R14 @-R0 0010 0000 1110 0110
523 R14-->(R0-4), R0-4-->R0 */
524 #define IS_MOV_R14_R0(x) ((x) == 0x20e6)
526 /* ADD Rm,R63,Rn Rm+R63-->Rn 0000 00mm mmmm 1001 1111 11nn nnnn 0000
527 where Rm is one of r2-r9 which are the argument registers. */
528 /* FIXME: Recognize the float and double register moves too! */
529 #define IS_MEDIA_IND_ARG_MOV(x) \
530 ((((x) & 0xfc0ffc0f) == 0x0009fc00) && (((x) & 0x03f00000) >= 0x00200000 && ((x) & 0x03f00000) <= 0x00900000))
532 /* ST.Q Rn,0,Rm Rm-->Rn+0 1010 11nn nnnn 0000 0000 00mm mmmm 0000
533 or ST.L Rn,0,Rm Rm-->Rn+0 1010 10nn nnnn 0000 0000 00mm mmmm 0000
534 where Rm is one of r2-r9 which are the argument registers. */
535 #define IS_MEDIA_ARG_MOV(x) \
536 (((((x) & 0xfc0ffc0f) == 0xac000000) || (((x) & 0xfc0ffc0f) == 0xa8000000)) \
537 && (((x) & 0x000003f0) >= 0x00000020 && ((x) & 0x000003f0) <= 0x00000090))
539 /* ST.B R14,0,Rn Rn-->(R14+0) 1010 0000 1110 0000 0000 00nn nnnn 0000*/
540 /* ST.W R14,0,Rn Rn-->(R14+0) 1010 0100 1110 0000 0000 00nn nnnn 0000*/
541 /* ST.L R14,0,Rn Rn-->(R14+0) 1010 1000 1110 0000 0000 00nn nnnn 0000*/
542 /* FST.S R14,0,FRn Rn-->(R14+0) 1011 0100 1110 0000 0000 00nn nnnn 0000*/
543 /* FST.D R14,0,DRn Rn-->(R14+0) 1011 1100 1110 0000 0000 00nn nnnn 0000*/
544 #define IS_MEDIA_MOV_TO_R14(x) \
545 ((((x) & 0xfffffc0f) == 0xa0e00000) \
546 || (((x) & 0xfffffc0f) == 0xa4e00000) \
547 || (((x) & 0xfffffc0f) == 0xa8e00000) \
548 || (((x) & 0xfffffc0f) == 0xb4e00000) \
549 || (((x) & 0xfffffc0f) == 0xbce00000))
551 /* MOV Rm, Rn Rm-->Rn 0110 nnnn mmmm 0011
553 #define IS_COMPACT_IND_ARG_MOV(x) \
554 ((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0020) && (((x) & 0x00f0) <= 0x0090))
556 /* compact direct arg move!
557 MOV.L Rn, @r14 0010 1110 mmmm 0010 */
558 #define IS_COMPACT_ARG_MOV(x) \
559 (((((x) & 0xff0f) == 0x2e02) && (((x) & 0x00f0) >= 0x0020) && ((x) & 0x00f0) <= 0x0090))
561 /* MOV.B Rm, @R14 0010 1110 mmmm 0000
562 MOV.W Rm, @R14 0010 1110 mmmm 0001 */
563 #define IS_COMPACT_MOV_TO_R14(x) \
564 ((((x) & 0xff0f) == 0x2e00) || (((x) & 0xff0f) == 0x2e01))
566 #define IS_JSR_R0(x) ((x) == 0x400b)
567 #define IS_NOP(x) ((x) == 0x0009)
570 /* STS.L PR,@-r15 0100111100100010
571 r15-4-->r15, PR-->(r15) */
572 #define IS_STS(x) ((x) == 0x4f22)
574 /* MOV.L Rm,@-r15 00101111mmmm0110
575 r15-4-->r15, Rm-->(R15) */
576 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
578 #define GET_PUSHED_REG(x) (((x) >> 4) & 0xf)
580 /* MOV r15,r14 0110111011110011
582 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
584 /* ADD #imm,r15 01111111iiiiiiii
586 #define IS_ADD_SP(x) (((x) & 0xff00) == 0x7f00)
588 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
589 #define IS_SHLL_R3(x) ((x) == 0x4300)
591 /* ADD r3,r15 0011111100111100
593 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
595 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
596 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
597 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
598 #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b)
600 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011
601 MOV.L Rm,@(disp,Rn) Rm-->(dispx4+Rn) 0001nnnnmmmmdddd
602 MOV.L Rm,@Rn Rm-->(Rn) 0010nnnnmmmm0010
603 where Rm is one of r4,r5,r6,r7 which are the argument registers. */
604 #define IS_ARG_MOV(x) \
605 (((((x) & 0xf00f) == 0x6003) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
606 || ((((x) & 0xf000) == 0x1000) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)) \
607 || ((((x) & 0xf00f) == 0x2002) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070)))
609 /* MOV.L Rm,@(disp,r14) 00011110mmmmdddd
610 Rm-->(dispx4+r14) where Rm is one of r4,r5,r6,r7 */
611 #define IS_MOV_TO_R14(x) \
612 ((((x) & 0xff00) == 0x1e) && (((x) & 0x00f0) >= 0x0040 && ((x) & 0x00f0) <= 0x0070))
614 #define FPSCR_SZ (1 << 20)
616 /* Skip any prologue before the guts of a function */
618 /* Skip the prologue using the debug information. If this fails we'll
619 fall back on the 'guess' method below. */
621 after_prologue (CORE_ADDR pc)
623 struct symtab_and_line sal;
624 CORE_ADDR func_addr, func_end;
626 /* If we can not find the symbol in the partial symbol table, then
627 there is no hope we can determine the function's start address
629 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
632 /* Get the line associated with FUNC_ADDR. */
633 sal = find_pc_line (func_addr, 0);
635 /* There are only two cases to consider. First, the end of the source line
636 is within the function bounds. In that case we return the end of the
637 source line. Second is the end of the source line extends beyond the
638 bounds of the current function. We need to use the slow code to
639 examine instructions in that case. */
640 if (sal.end < func_end)
646 /* Here we look at each instruction in the function, and try to guess
647 where the prologue ends. Unfortunately this is not always
650 sh_skip_prologue_hard_way (CORE_ADDR start_pc)
658 for (here = start_pc, end = start_pc + (2 * 28); here < end;)
660 int w = read_memory_integer (here, 2);
662 if (IS_FMOV (w) || IS_PUSH (w) || IS_STS (w) || IS_MOV_R3 (w)
663 || IS_ADD_R3SP (w) || IS_ADD_SP (w) || IS_SHLL_R3 (w)
664 || IS_ARG_MOV (w) || IS_MOV_TO_R14 (w))
668 else if (IS_MOV_SP_FP (w))
674 /* Don't bail out yet, if we are before the copy of sp. */
683 look_for_args_moves (CORE_ADDR start_pc, int media_mode)
687 int insn_size = (media_mode ? 4 : 2);
689 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
693 w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
695 if (IS_MEDIA_IND_ARG_MOV (w))
697 /* This must be followed by a store to r14, so the argument
698 is where the debug info says it is. This can happen after
699 the SP has been saved, unfortunately. */
701 int next_insn = read_memory_integer (UNMAKE_ISA32_ADDR (here),
704 if (IS_MEDIA_MOV_TO_R14 (next_insn))
707 else if (IS_MEDIA_ARG_MOV (w))
709 /* These instructions store directly the argument in r14. */
717 w = read_memory_integer (here, insn_size);
720 if (IS_COMPACT_IND_ARG_MOV (w))
722 /* This must be followed by a store to r14, so the argument
723 is where the debug info says it is. This can happen after
724 the SP has been saved, unfortunately. */
726 int next_insn = 0xffff & read_memory_integer (here, insn_size);
728 if (IS_COMPACT_MOV_TO_R14 (next_insn))
731 else if (IS_COMPACT_ARG_MOV (w))
733 /* These instructions store directly the argument in r14. */
736 else if (IS_MOVL_R0 (w))
738 /* There is a function that gcc calls to get the arguments
739 passed correctly to the function. Only after this
740 function call the arguments will be found at the place
741 where they are supposed to be. This happens in case the
742 argument has to be stored into a 64-bit register (for
743 instance doubles, long longs). SHcompact doesn't have
744 access to the full 64-bits, so we store the register in
745 stack slot and store the address of the stack slot in
746 the register, then do a call through a wrapper that
747 loads the memory value into the register. A SHcompact
748 callee calls an argument decoder
749 (GCC_shcompact_incoming_args) that stores the 64-bit
750 value in a stack slot and stores the address of the
751 stack slot in the register. GCC thinks the argument is
752 just passed by transparent reference, but this is only
753 true after the argument decoder is called. Such a call
754 needs to be considered part of the prologue. */
756 /* This must be followed by a JSR @r0 instruction and by
757 a NOP instruction. After these, the prologue is over! */
759 int next_insn = 0xffff & read_memory_integer (here, insn_size);
761 if (IS_JSR_R0 (next_insn))
763 next_insn = 0xffff & read_memory_integer (here, insn_size);
766 if (IS_NOP (next_insn))
779 sh64_skip_prologue_hard_way (CORE_ADDR start_pc)
789 if (pc_is_isa32 (start_pc) == 0)
795 for (here = start_pc, end = start_pc + (insn_size * 28); here < end;)
800 int w = read_memory_integer (UNMAKE_ISA32_ADDR (here), insn_size);
802 if (IS_STQ_R18_R14 (w) || IS_STQ_R18_R15 (w) || IS_STQ_R14_R15 (w)
803 || IS_STL_R14_R15 (w) || IS_STL_R18_R15 (w)
804 || IS_ADDIL_SP_MEDIA (w) || IS_ADDI_SP_MEDIA (w) || IS_PTABSL_R18 (w))
808 else if (IS_MOV_SP_FP (w) || IS_MOV_SP_FP_MEDIA(w))
816 /* Don't bail out yet, we may have arguments stored in
817 registers here, according to the debug info, so that
818 gdb can print the frames correctly. */
819 start_pc = look_for_args_moves (here - insn_size, media_mode);
825 int w = 0xffff & read_memory_integer (here, insn_size);
828 if (IS_STS_R0 (w) || IS_STS_PR (w)
829 || IS_MOV_TO_R15 (w) || IS_MOV_R14 (w)
830 || IS_MOV_R0 (w) || IS_ADD_SP_R0 (w) || IS_MOV_R14_R0 (w))
834 else if (IS_MOV_SP_FP (w))
842 /* Don't bail out yet, we may have arguments stored in
843 registers here, according to the debug info, so that
844 gdb can print the frames correctly. */
845 start_pc = look_for_args_moves (here - insn_size, media_mode);
855 sh_skip_prologue (CORE_ADDR pc)
857 CORE_ADDR post_prologue_pc;
859 /* See if we can determine the end of the prologue via the symbol table.
860 If so, then return either PC, or the PC after the prologue, whichever
862 post_prologue_pc = after_prologue (pc);
864 /* If after_prologue returned a useful address, then use it. Else
865 fall back on the instruction skipping code. */
866 if (post_prologue_pc != 0)
867 return max (pc, post_prologue_pc);
869 return (skip_prologue_hard_way (pc));
872 /* Immediately after a function call, return the saved pc.
873 Can't always go through the frames for this because on some machines
874 the new frame is not set up until the new function executes
877 The return address is the value saved in the PR register + 4 */
879 sh_saved_pc_after_call (struct frame_info *frame)
881 return (ADDR_BITS_REMOVE (read_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM)));
884 /* Should call_function allocate stack space for a struct return? */
886 sh_use_struct_convention (int gcc_p, struct type *type)
889 return (TYPE_LENGTH (type) > 1);
891 int len = TYPE_LENGTH (type);
892 int nelem = TYPE_NFIELDS (type);
893 return ((len != 1 && len != 2 && len != 4 && len != 8) || nelem != 1) &&
894 (len != 8 || TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) != 4);
899 sh64_use_struct_convention (int gcc_p, struct type *type)
901 return (TYPE_LENGTH (type) > 8);
904 /* Store the address of the place in which to copy the structure the
905 subroutine will return. This is called from call_function.
907 We store structs through a pointer passed in R2 */
909 sh_store_struct_return (CORE_ADDR addr, CORE_ADDR sp)
911 write_register (STRUCT_RETURN_REGNUM, (addr));
914 /* Disassemble an instruction. */
916 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info *info)
918 info->endian = TARGET_BYTE_ORDER;
919 return print_insn_sh (memaddr, info);
922 /* Given a GDB frame, determine the address of the calling function's
923 frame. This will be used to create a new GDB frame struct, and
924 then INIT_EXTRA_FRAME_INFO and DEPRECATED_INIT_FRAME_PC will be
925 called for the new frame.
927 For us, the frame address is its stack pointer value, so we look up
928 the function prologue to determine the caller's sp value, and return it. */
930 sh_frame_chain (struct frame_info *frame)
932 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
933 return frame->frame; /* dummy frame same as caller's frame */
934 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
935 return read_memory_integer (get_frame_base (frame) + frame->extra_info->f_offset, 4);
940 /* Given a register number RN as it appears in an assembly
941 instruction, find the corresponding register number in the GDB
944 translate_insn_rn (int rn, int media_mode)
946 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
948 /* FIXME: this assumes that the number rn is for a not pseudo
954 /* These registers don't have a corresponding compact one. */
955 /* FIXME: This is probably not enough. */
957 if ((rn >= 16 && rn <= 63) || (rn >= 93 && rn <= 140))
960 if (rn >= 0 && rn <= tdep->R0_C_REGNUM)
961 return tdep->R0_C_REGNUM + rn;
968 sh64_frame_chain (struct frame_info *frame)
970 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
971 return frame->frame; /* dummy frame same as caller's frame */
972 if (get_frame_pc (frame) && !inside_entry_file (get_frame_pc (frame)))
974 int media_mode = pc_is_isa32 (get_frame_pc (frame));
976 if (gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
979 size = REGISTER_RAW_SIZE (translate_insn_rn (FP_REGNUM, media_mode));
980 return read_memory_integer (get_frame_base (frame) + frame->extra_info->f_offset, size);
986 /* Find REGNUM on the stack. Otherwise, it's in an active register. One thing
987 we might want to do here is to check REGNUM against the clobber mask, and
988 somehow flag it as invalid if it isn't saved on the stack somewhere. This
989 would provide a graceful failure mode when trying to get the value of
990 caller-saves registers for an inner frame. */
992 sh_find_callers_reg (struct frame_info *fi, int regnum)
994 for (; fi; fi = fi->next)
995 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame))
996 /* When the caller requests PR from the dummy frame, we return PC because
997 that's where the previous routine appears to have done a call from. */
998 return deprecated_read_register_dummy (get_frame_pc (fi), fi->frame, regnum);
1001 FRAME_INIT_SAVED_REGS (fi);
1002 if (!get_frame_pc (fi))
1004 if (get_frame_saved_regs (fi)[regnum] != 0)
1005 return read_memory_integer (get_frame_saved_regs (fi)[regnum],
1006 REGISTER_RAW_SIZE (regnum));
1008 return read_register (regnum);
1012 sh64_get_saved_pr (struct frame_info *fi, int pr_regnum)
1016 for (; fi; fi = fi->next)
1017 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame))
1018 /* When the caller requests PR from the dummy frame, we return PC because
1019 that's where the previous routine appears to have done a call from. */
1020 return deprecated_read_register_dummy (get_frame_pc (fi), fi->frame, pr_regnum);
1023 FRAME_INIT_SAVED_REGS (fi);
1024 if (!get_frame_pc (fi))
1027 media_mode = pc_is_isa32 (get_frame_pc (fi));
1029 if (get_frame_saved_regs (fi)[pr_regnum] != 0)
1031 int gdb_reg_num = translate_insn_rn (pr_regnum, media_mode);
1032 int size = ((gdbarch_tdep (current_gdbarch)->sh_abi == SH_ABI_32)
1034 : REGISTER_RAW_SIZE (gdb_reg_num));
1035 return read_memory_integer (get_frame_saved_regs (fi)[pr_regnum], size);
1038 return read_register (pr_regnum);
1041 /* Put here the code to store, into a struct frame_saved_regs, the
1042 addresses of the saved registers of frame described by FRAME_INFO.
1043 This includes special registers such as pc and fp saved in special
1044 ways in the stack frame. sp is even more special: the address we
1045 return for it IS the sp for the next frame. */
1047 sh_nofp_frame_init_saved_regs (struct frame_info *fi)
1049 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof(int));
1057 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), fi->frame);
1059 if (get_frame_saved_regs (fi) == NULL)
1060 frame_saved_regs_zalloc (fi);
1062 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1066 /* DANGER! This is ONLY going to work if the char buffer format of
1067 the saved registers is byte-for-byte identical to the
1068 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1069 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1073 fi->extra_info->leaf_function = 1;
1074 fi->extra_info->f_offset = 0;
1076 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1081 /* Loop around examining the prologue insns until we find something
1082 that does not appear to be part of the prologue. But give up
1083 after 20 of them, since we're getting silly then. */
1085 pc = get_pc_function_start (get_frame_pc (fi));
1088 deprecated_update_frame_pc_hack (fi, 0);
1092 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1094 insn = read_memory_integer (pc, 2);
1095 /* See where the registers will be saved to */
1098 rn = GET_PUSHED_REG (insn);
1102 else if (IS_STS (insn))
1104 where[gdbarch_tdep (current_gdbarch)->PR_REGNUM] = depth;
1105 /* If we're storing the pr then this isn't a leaf */
1106 fi->extra_info->leaf_function = 0;
1109 else if (IS_MOV_R3 (insn))
1111 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1113 else if (IS_SHLL_R3 (insn))
1117 else if (IS_ADD_R3SP (insn))
1121 else if (IS_ADD_SP (insn))
1123 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1125 else if (IS_MOV_SP_FP (insn))
1127 #if 0 /* This used to just stop when it found an instruction that
1128 was not considered part of the prologue. Now, we just
1129 keep going looking for likely instructions. */
1135 /* Now we know how deep things are, we can work out their addresses */
1137 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1141 if (rn == FP_REGNUM)
1144 get_frame_saved_regs (fi)[rn] = fi->frame - where[rn] + depth - 4;
1148 get_frame_saved_regs (fi)[rn] = 0;
1154 get_frame_saved_regs (fi)[SP_REGNUM] = read_memory_integer (get_frame_saved_regs (fi)[FP_REGNUM], 4);
1158 get_frame_saved_regs (fi)[SP_REGNUM] = fi->frame - 4;
1161 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
1162 /* Work out the return pc - either from the saved pr or the pr
1166 /* For vectors of 4 floating point registers. */
1168 fv_reg_base_num (int fv_regnum)
1172 fp_regnum = FP0_REGNUM +
1173 (fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM) * 4;
1177 /* For double precision floating point registers, i.e 2 fp regs.*/
1179 dr_reg_base_num (int dr_regnum)
1183 fp_regnum = FP0_REGNUM +
1184 (dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM) * 2;
1188 /* For pairs of floating point registers */
1190 fpp_reg_base_num (int fpp_regnum)
1194 fp_regnum = FP0_REGNUM +
1195 (fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM) * 2;
1200 is_media_pseudo (int rn)
1202 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1204 return (rn >= tdep->DR0_REGNUM
1205 && rn <= tdep->FV_LAST_REGNUM);
1209 sh64_get_gdb_regnum (int gcc_regnum, CORE_ADDR pc)
1211 return translate_insn_rn (gcc_regnum, pc_is_isa32 (pc));
1215 sh64_media_reg_base_num (int reg_nr)
1217 int base_regnum = -1;
1218 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1220 if (reg_nr >= tdep->DR0_REGNUM
1221 && reg_nr <= tdep->DR_LAST_REGNUM)
1222 base_regnum = dr_reg_base_num (reg_nr);
1224 else if (reg_nr >= tdep->FPP0_REGNUM
1225 && reg_nr <= tdep->FPP_LAST_REGNUM)
1226 base_regnum = fpp_reg_base_num (reg_nr);
1228 else if (reg_nr >= tdep->FV0_REGNUM
1229 && reg_nr <= tdep->FV_LAST_REGNUM)
1230 base_regnum = fv_reg_base_num (reg_nr);
1237 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
1238 GDB_REGNUM BASE_REGNUM
1298 sh64_compact_reg_base_num (int reg_nr)
1300 int base_regnum = -1;
1301 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1303 /* general register N maps to general register N */
1304 if (reg_nr >= tdep->R0_C_REGNUM
1305 && reg_nr <= tdep->R_LAST_C_REGNUM)
1306 base_regnum = reg_nr - tdep->R0_C_REGNUM;
1308 /* floating point register N maps to floating point register N */
1309 else if (reg_nr >= tdep->FP0_C_REGNUM
1310 && reg_nr <= tdep->FP_LAST_C_REGNUM)
1311 base_regnum = reg_nr - tdep->FP0_C_REGNUM + FP0_REGNUM;
1313 /* double prec register N maps to base regnum for double prec register N */
1314 else if (reg_nr >= tdep->DR0_C_REGNUM
1315 && reg_nr <= tdep->DR_LAST_C_REGNUM)
1316 base_regnum = dr_reg_base_num (tdep->DR0_REGNUM
1317 + reg_nr - tdep->DR0_C_REGNUM);
1319 /* vector N maps to base regnum for vector register N */
1320 else if (reg_nr >= tdep->FV0_C_REGNUM
1321 && reg_nr <= tdep->FV_LAST_C_REGNUM)
1322 base_regnum = fv_reg_base_num (tdep->FV0_REGNUM
1323 + reg_nr - tdep->FV0_C_REGNUM);
1325 else if (reg_nr == tdep->PC_C_REGNUM)
1326 base_regnum = PC_REGNUM;
1328 else if (reg_nr == tdep->GBR_C_REGNUM)
1331 else if (reg_nr == tdep->MACH_C_REGNUM
1332 || reg_nr == tdep->MACL_C_REGNUM)
1335 else if (reg_nr == tdep->PR_C_REGNUM)
1338 else if (reg_nr == tdep->T_C_REGNUM)
1341 else if (reg_nr == tdep->FPSCR_C_REGNUM)
1342 base_regnum = tdep->FPSCR_REGNUM; /*???? this register is a mess. */
1344 else if (reg_nr == tdep->FPUL_C_REGNUM)
1345 base_regnum = FP0_REGNUM + 32;
1350 /* Given a register number RN (according to the gdb scheme) , return
1351 its corresponding architectural register. In media mode, only a
1352 subset of the registers is pseudo registers. For compact mode, all
1353 the registers are pseudo. */
1355 translate_rn_to_arch_reg_num (int rn, int media_mode)
1360 if (!is_media_pseudo (rn))
1363 return sh64_media_reg_base_num (rn);
1366 /* All compact registers are pseudo. */
1367 return sh64_compact_reg_base_num (rn);
1371 sign_extend (int value, int bits)
1373 value = value & ((1 << bits) - 1);
1374 return (value & (1 << (bits - 1))
1375 ? value | (~((1 << bits) - 1))
1380 sh64_nofp_frame_init_saved_regs (struct frame_info *fi)
1382 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1394 int gdb_register_number;
1395 int register_number;
1396 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), fi->frame);
1397 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1399 if (get_frame_saved_regs (fi) == NULL)
1400 frame_saved_regs_zalloc (fi);
1402 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1406 /* DANGER! This is ONLY going to work if the char buffer format of
1407 the saved registers is byte-for-byte identical to the
1408 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1409 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1413 fi->extra_info->leaf_function = 1;
1414 fi->extra_info->f_offset = 0;
1416 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1421 /* Loop around examining the prologue insns until we find something
1422 that does not appear to be part of the prologue. But give up
1423 after 20 of them, since we're getting silly then. */
1425 pc = get_pc_function_start (get_frame_pc (fi));
1428 deprecated_update_frame_pc_hack (fi, 0);
1432 if (pc_is_isa32 (pc))
1443 /* The frame pointer register is general register 14 in shmedia and
1444 shcompact modes. In sh compact it is a pseudo register. Same goes
1445 for the stack pointer register, which is register 15. */
1446 fp_regnum = translate_insn_rn (FP_REGNUM, media_mode);
1447 sp_regnum = translate_insn_rn (SP_REGNUM, media_mode);
1449 for (opc = pc + (insn_size * 28); pc < opc; pc += insn_size)
1451 insn = read_memory_integer (media_mode ? UNMAKE_ISA32_ADDR (pc) : pc,
1454 if (media_mode == 0)
1456 if (IS_STS_PR (insn))
1458 int next_insn = read_memory_integer (pc + insn_size, insn_size);
1459 if (IS_MOV_TO_R15 (next_insn))
1461 int reg_nr = tdep->PR_C_REGNUM;
1463 where[reg_nr] = depth - ((((next_insn & 0xf) ^ 0x8) - 0x8) << 2);
1464 fi->extra_info->leaf_function = 0;
1468 else if (IS_MOV_R14 (insn))
1470 where[fp_regnum] = depth - ((((insn & 0xf) ^ 0x8) - 0x8) << 2);
1473 else if (IS_MOV_R0 (insn))
1475 /* Put in R0 the offset from SP at which to store some
1476 registers. We are interested in this value, because it
1477 will tell us where the given registers are stored within
1479 r0_val = ((insn & 0xff) ^ 0x80) - 0x80;
1481 else if (IS_ADD_SP_R0 (insn))
1483 /* This instruction still prepares r0, but we don't care.
1484 We already have the offset in r0_val. */
1486 else if (IS_STS_R0 (insn))
1488 /* Store PR at r0_val-4 from SP. Decrement r0 by 4*/
1489 int reg_nr = tdep->PR_C_REGNUM;
1490 where[reg_nr] = depth - (r0_val - 4);
1492 fi->extra_info->leaf_function = 0;
1494 else if (IS_MOV_R14_R0 (insn))
1496 /* Store R14 at r0_val-4 from SP. Decrement r0 by 4 */
1497 where[fp_regnum] = depth - (r0_val - 4);
1501 else if (IS_ADD_SP (insn))
1503 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1505 else if (IS_MOV_SP_FP (insn))
1510 if (IS_ADDIL_SP_MEDIA (insn)
1511 || IS_ADDI_SP_MEDIA (insn))
1513 depth -= sign_extend ((((insn & 0xffc00) ^ 0x80000) - 0x80000) >> 10, 9);
1516 else if (IS_STQ_R18_R15 (insn))
1518 where[tdep->PR_REGNUM] =
1519 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1520 fi->extra_info->leaf_function = 0;
1523 else if (IS_STL_R18_R15 (insn))
1525 where[tdep->PR_REGNUM] =
1526 depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1527 fi->extra_info->leaf_function = 0;
1530 else if (IS_STQ_R14_R15 (insn))
1532 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 3);
1535 else if (IS_STL_R14_R15 (insn))
1537 where[fp_regnum] = depth - (sign_extend ((insn & 0xffc00) >> 10, 9) << 2);
1540 else if (IS_MOV_SP_FP_MEDIA (insn))
1545 /* Now we know how deep things are, we can work out their addresses. */
1546 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1548 register_number = translate_rn_to_arch_reg_num (rn, media_mode);
1552 if (rn == fp_regnum)
1555 /* Watch out! saved_regs is only for the real registers, and
1556 doesn't include space for the pseudo registers. */
1557 get_frame_saved_regs (fi)[register_number]= fi->frame - where[rn] + depth;
1561 get_frame_saved_regs (fi)[register_number] = 0;
1566 /* SP_REGNUM is 15. For shmedia 15 is the real register. For
1567 shcompact 15 is the arch register corresponding to the pseudo
1568 register r15 which still is the SP register. */
1569 /* The place on the stack where fp is stored contains the sp of
1571 /* Again, saved_registers contains only space for the real registers,
1572 so we store in FP_REGNUM position. */
1574 if (tdep->sh_abi == SH_ABI_32)
1577 size = REGISTER_RAW_SIZE (fp_regnum);
1578 get_frame_saved_regs (fi)[sp_regnum] = read_memory_integer (get_frame_saved_regs (fi)[fp_regnum], size);
1581 get_frame_saved_regs (fi)[sp_regnum] = fi->frame;
1583 fi->extra_info->f_offset = depth - where[fp_regnum];
1587 sh_fp_frame_init_saved_regs (struct frame_info *fi)
1589 int *where = (int *) alloca ((NUM_REGS + NUM_PSEUDO_REGS) * sizeof (int));
1597 char *dummy_regs = deprecated_generic_find_dummy_frame (get_frame_pc (fi), fi->frame);
1598 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1600 if (get_frame_saved_regs (fi) == NULL)
1601 frame_saved_regs_zalloc (fi);
1603 memset (get_frame_saved_regs (fi), 0, SIZEOF_FRAME_SAVED_REGS);
1607 /* DANGER! This is ONLY going to work if the char buffer format of
1608 the saved registers is byte-for-byte identical to the
1609 CORE_ADDR regs[NUM_REGS] format used by struct frame_saved_regs! */
1610 memcpy (fi->saved_regs, dummy_regs, sizeof (fi->saved_regs));
1614 fi->extra_info->leaf_function = 1;
1615 fi->extra_info->f_offset = 0;
1617 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1622 /* Loop around examining the prologue insns until we find something
1623 that does not appear to be part of the prologue. But give up
1624 after 20 of them, since we're getting silly then. */
1626 pc = get_pc_function_start (get_frame_pc (fi));
1629 deprecated_update_frame_pc_hack (fi, 0);
1633 for (opc = pc + (2 * 28); pc < opc; pc += 2)
1635 insn = read_memory_integer (pc, 2);
1636 /* See where the registers will be saved to */
1639 rn = GET_PUSHED_REG (insn);
1643 else if (IS_STS (insn))
1645 where[tdep->PR_REGNUM] = depth;
1646 /* If we're storing the pr then this isn't a leaf */
1647 fi->extra_info->leaf_function = 0;
1650 else if (IS_MOV_R3 (insn))
1652 r3_val = ((insn & 0xff) ^ 0x80) - 0x80;
1654 else if (IS_SHLL_R3 (insn))
1658 else if (IS_ADD_R3SP (insn))
1662 else if (IS_ADD_SP (insn))
1664 depth -= ((insn & 0xff) ^ 0x80) - 0x80;
1666 else if (IS_FMOV (insn))
1668 if (read_register (tdep->FPSCR_REGNUM) & FPSCR_SZ)
1677 else if (IS_MOV_SP_FP (insn))
1679 #if 0 /* This used to just stop when it found an instruction that
1680 was not considered part of the prologue. Now, we just
1681 keep going looking for likely instructions. */
1687 /* Now we know how deep things are, we can work out their addresses */
1689 for (rn = 0; rn < NUM_REGS + NUM_PSEUDO_REGS; rn++)
1693 if (rn == FP_REGNUM)
1696 get_frame_saved_regs (fi)[rn] = fi->frame - where[rn] + depth - 4;
1700 get_frame_saved_regs (fi)[rn] = 0;
1706 get_frame_saved_regs (fi)[SP_REGNUM] =
1707 read_memory_integer (get_frame_saved_regs (fi)[FP_REGNUM], 4);
1711 get_frame_saved_regs (fi)[SP_REGNUM] = fi->frame - 4;
1714 fi->extra_info->f_offset = depth - where[FP_REGNUM] - 4;
1715 /* Work out the return pc - either from the saved pr or the pr
1719 /* Initialize the extra info saved in a FRAME */
1721 sh_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1724 fi->extra_info = (struct frame_extra_info *)
1725 frame_obstack_alloc (sizeof (struct frame_extra_info));
1728 deprecated_update_frame_pc_hack (fi, FRAME_SAVED_PC (fi->next));
1730 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame))
1732 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1733 by assuming it's always FP. */
1734 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), fi->frame,
1736 fi->extra_info->return_pc = deprecated_read_register_dummy (get_frame_pc (fi),
1739 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1740 fi->extra_info->leaf_function = 0;
1745 FRAME_INIT_SAVED_REGS (fi);
1746 fi->extra_info->return_pc =
1747 sh_find_callers_reg (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1752 sh64_init_extra_frame_info (int fromleaf, struct frame_info *fi)
1754 int media_mode = pc_is_isa32 (get_frame_pc (fi));
1756 fi->extra_info = (struct frame_extra_info *)
1757 frame_obstack_alloc (sizeof (struct frame_extra_info));
1760 deprecated_update_frame_pc_hack (fi, FRAME_SAVED_PC (fi->next));
1762 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (fi), fi->frame, fi->frame))
1764 /* We need to setup fi->frame here because run_stack_dummy gets it wrong
1765 by assuming it's always FP. */
1766 deprecated_update_frame_base_hack (fi, deprecated_read_register_dummy (get_frame_pc (fi), fi->frame,
1768 fi->extra_info->return_pc =
1769 deprecated_read_register_dummy (get_frame_pc (fi), fi->frame, PC_REGNUM);
1770 fi->extra_info->f_offset = -(CALL_DUMMY_LENGTH + 4);
1771 fi->extra_info->leaf_function = 0;
1776 FRAME_INIT_SAVED_REGS (fi);
1777 fi->extra_info->return_pc =
1778 sh64_get_saved_pr (fi, gdbarch_tdep (current_gdbarch)->PR_REGNUM);
1783 sh64_get_saved_register (char *raw_buffer, int *optimized, CORE_ADDR *addrp,
1784 struct frame_info *frame, int regnum,
1785 enum lval_type *lval)
1788 int live_regnum = regnum;
1789 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1791 if (!target_has_registers)
1792 error ("No registers.");
1794 /* Normal systems don't optimize out things with register numbers. */
1795 if (optimized != NULL)
1798 if (addrp) /* default assumption: not found in memory */
1802 memset (raw_buffer, 0, sizeof (raw_buffer));
1804 /* We must do this here, before the following while loop changes
1805 frame, and makes it NULL. If this is a media register number,
1806 but we are in compact mode, it will become the corresponding
1807 compact pseudo register. If there is no corresponding compact
1808 pseudo-register what do we do?*/
1809 media_mode = pc_is_isa32 (get_frame_pc (frame));
1810 live_regnum = translate_insn_rn (regnum, media_mode);
1812 /* Note: since the current frame's registers could only have been
1813 saved by frames INTERIOR TO the current frame, we skip examining
1814 the current frame itself: otherwise, we would be getting the
1815 previous frame's registers which were saved by the current frame. */
1817 while (frame && ((frame = frame->next) != NULL))
1819 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
1821 if (lval) /* found it in a CALL_DUMMY frame */
1825 (deprecated_generic_find_dummy_frame (get_frame_pc (frame), frame->frame)
1826 + REGISTER_BYTE (regnum)),
1827 REGISTER_RAW_SIZE (regnum));
1831 FRAME_INIT_SAVED_REGS (frame);
1832 if (get_frame_saved_regs (frame) != NULL
1833 && get_frame_saved_regs (frame)[regnum] != 0)
1835 if (lval) /* found it saved on the stack */
1836 *lval = lval_memory;
1837 if (regnum == SP_REGNUM)
1839 if (raw_buffer) /* SP register treated specially */
1840 store_address (raw_buffer, REGISTER_RAW_SIZE (regnum),
1841 get_frame_saved_regs (frame)[regnum]);
1844 { /* any other register */
1847 *addrp = get_frame_saved_regs (frame)[regnum];
1851 if (tdep->sh_abi == SH_ABI_32
1852 && (live_regnum == FP_REGNUM
1853 || live_regnum == tdep->PR_REGNUM))
1856 size = REGISTER_RAW_SIZE (live_regnum);
1857 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1858 read_memory (get_frame_saved_regs (frame)[regnum], raw_buffer, size);
1860 read_memory (get_frame_saved_regs (frame)[regnum],
1862 + REGISTER_RAW_SIZE (live_regnum)
1871 /* If we get thru the loop to this point, it means the register was
1872 not saved in any frame. Return the actual live-register value. */
1874 if (lval) /* found it in a live register */
1875 *lval = lval_register;
1877 *addrp = REGISTER_BYTE (live_regnum);
1879 deprecated_read_register_gen (live_regnum, raw_buffer);
1882 /* Extract from an array REGBUF containing the (raw) register state
1883 the address in which a function should return its structure value,
1884 as a CORE_ADDR (or an expression that can be used as one). */
1886 sh_extract_struct_value_address (char *regbuf)
1888 return (extract_address ((regbuf), REGISTER_RAW_SIZE (0)));
1892 sh64_extract_struct_value_address (char *regbuf)
1894 return (extract_address ((regbuf + REGISTER_BYTE (STRUCT_RETURN_REGNUM)),
1895 REGISTER_RAW_SIZE (STRUCT_RETURN_REGNUM)));
1899 sh_frame_saved_pc (struct frame_info *frame)
1901 return ((frame)->extra_info->return_pc);
1904 /* Discard from the stack the innermost frame,
1905 restoring all saved registers. */
1909 register struct frame_info *frame = get_current_frame ();
1910 register CORE_ADDR fp;
1911 register int regnum;
1913 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
1914 generic_pop_dummy_frame ();
1917 fp = get_frame_base (frame);
1918 FRAME_INIT_SAVED_REGS (frame);
1920 /* Copy regs from where they were saved in the frame */
1921 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1922 if (get_frame_saved_regs (frame)[regnum])
1923 write_register (regnum,
1924 read_memory_integer (get_frame_saved_regs (frame)[regnum], 4));
1926 write_register (PC_REGNUM, frame->extra_info->return_pc);
1927 write_register (SP_REGNUM, fp + 4);
1929 flush_cached_frames ();
1932 /* Used in the 'return' command. */
1934 sh64_pop_frame (void)
1936 register struct frame_info *frame = get_current_frame ();
1937 register CORE_ADDR fp;
1938 register int regnum;
1939 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1941 int media_mode = pc_is_isa32 (get_frame_pc (frame));
1943 if (DEPRECATED_PC_IN_CALL_DUMMY (get_frame_pc (frame), frame->frame, frame->frame))
1944 generic_pop_dummy_frame ();
1947 fp = get_frame_base (frame);
1948 FRAME_INIT_SAVED_REGS (frame);
1950 /* Copy regs from where they were saved in the frame */
1951 for (regnum = 0; regnum < NUM_REGS + NUM_PSEUDO_REGS; regnum++)
1952 if (get_frame_saved_regs (frame)[regnum])
1955 if (tdep->sh_abi == SH_ABI_32
1956 && (regnum == FP_REGNUM
1957 || regnum == tdep->PR_REGNUM))
1960 size = REGISTER_RAW_SIZE (translate_insn_rn (regnum,
1962 write_register (regnum,
1963 read_memory_integer (get_frame_saved_regs (frame)[regnum],
1967 write_register (PC_REGNUM, frame->extra_info->return_pc);
1968 write_register (SP_REGNUM, fp + 8);
1970 flush_cached_frames ();
1973 /* Function: push_arguments
1974 Setup the function arguments for calling a function in the inferior.
1976 On the Hitachi SH architecture, there are four registers (R4 to R7)
1977 which are dedicated for passing function arguments. Up to the first
1978 four arguments (depending on size) may go into these registers.
1979 The rest go on the stack.
1981 Arguments that are smaller than 4 bytes will still take up a whole
1982 register or a whole 32-bit word on the stack, and will be
1983 right-justified in the register or the stack word. This includes
1984 chars, shorts, and small aggregate types.
1986 Arguments that are larger than 4 bytes may be split between two or
1987 more registers. If there are not enough registers free, an argument
1988 may be passed partly in a register (or registers), and partly on the
1989 stack. This includes doubles, long longs, and larger aggregates.
1990 As far as I know, there is no upper limit to the size of aggregates
1991 that will be passed in this way; in other words, the convention of
1992 passing a pointer to a large aggregate instead of a copy is not used.
1994 An exceptional case exists for struct arguments (and possibly other
1995 aggregates such as arrays) if the size is larger than 4 bytes but
1996 not a multiple of 4 bytes. In this case the argument is never split
1997 between the registers and the stack, but instead is copied in its
1998 entirety onto the stack, AND also copied into as many registers as
1999 there is room for. In other words, space in registers permitting,
2000 two copies of the same argument are passed in. As far as I can tell,
2001 only the one on the stack is used, although that may be a function
2002 of the level of compiler optimization. I suspect this is a compiler
2003 bug. Arguments of these odd sizes are left-justified within the
2004 word (as opposed to arguments smaller than 4 bytes, which are
2007 If the function is to return an aggregate type such as a struct, it
2008 is either returned in the normal return value register R0 (if its
2009 size is no greater than one byte), or else the caller must allocate
2010 space into which the callee will copy the return value (if the size
2011 is greater than one byte). In this case, a pointer to the return
2012 value location is passed into the callee in register R2, which does
2013 not displace any of the other arguments passed in via registers R4
2017 sh_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2018 int struct_return, CORE_ADDR struct_addr)
2020 int stack_offset, stack_alloc;
2028 int odd_sized_struct;
2029 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2031 /* first force sp to a 4-byte alignment */
2034 /* The "struct return pointer" pseudo-argument has its own dedicated
2037 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2039 /* Now make sure there's space on the stack */
2040 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2041 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 3) & ~3);
2042 sp -= stack_alloc; /* make room on stack for args */
2044 /* Now load as many as possible of the first arguments into
2045 registers, and push the rest onto the stack. There are 16 bytes
2046 in four registers available. Loop thru args from first to last. */
2048 argreg = tdep->ARG0_REGNUM;
2049 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2051 type = VALUE_TYPE (args[argnum]);
2052 len = TYPE_LENGTH (type);
2053 memset (valbuf, 0, sizeof (valbuf));
2056 /* value gets right-justified in the register or stack word */
2057 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2058 memcpy (valbuf + (4 - len),
2059 (char *) VALUE_CONTENTS (args[argnum]), len);
2061 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2065 val = (char *) VALUE_CONTENTS (args[argnum]);
2067 if (len > 4 && (len & 3) != 0)
2068 odd_sized_struct = 1; /* such structs go entirely on stack */
2070 odd_sized_struct = 0;
2073 if (argreg > tdep->ARGLAST_REGNUM
2074 || odd_sized_struct)
2076 /* must go on the stack */
2077 write_memory (sp + stack_offset, val, 4);
2080 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2081 That's because some *&^%$ things get passed on the stack
2082 AND in the registers! */
2083 if (argreg <= tdep->ARGLAST_REGNUM)
2085 /* there's room in a register */
2086 regval = extract_address (val, REGISTER_RAW_SIZE (argreg));
2087 write_register (argreg++, regval);
2089 /* Store the value 4 bytes at a time. This means that things
2090 larger than 4 bytes may go partly in registers and partly
2092 len -= REGISTER_RAW_SIZE (argreg);
2093 val += REGISTER_RAW_SIZE (argreg);
2099 /* R2-R9 for integer types and integer equivalent (char, pointers) and
2100 non-scalar (struct, union) elements (even if the elements are
2102 FR0-FR11 for single precision floating point (float)
2103 DR0-DR10 for double precision floating point (double)
2105 If a float is argument number 3 (for instance) and arguments number
2106 1,2, and 4 are integer, the mapping will be:
2107 arg1 -->R2, arg2 --> R3, arg3 -->FR0, arg4 --> R5. I.e. R4 is not used.
2109 If a float is argument number 10 (for instance) and arguments number
2110 1 through 10 are integer, the mapping will be:
2111 arg1->R2, arg2->R3, arg3->R4, arg4->R5, arg5->R6, arg6->R7, arg7->R8,
2112 arg8->R9, arg9->(0,SP)stack(8-byte aligned), arg10->FR0, arg11->stack(16,SP).
2113 I.e. there is hole in the stack.
2115 Different rules apply for variable arguments functions, and for functions
2116 for which the prototype is not known. */
2119 sh64_push_arguments (int nargs, struct value **args, CORE_ADDR sp,
2120 int struct_return, CORE_ADDR struct_addr)
2122 int stack_offset, stack_alloc;
2126 int float_arg_index = 0;
2127 int double_arg_index = 0;
2137 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2139 memset (fp_args, 0, sizeof (fp_args));
2141 /* first force sp to a 8-byte alignment */
2144 /* The "struct return pointer" pseudo-argument has its own dedicated
2148 write_register (STRUCT_RETURN_REGNUM, struct_addr);
2150 /* Now make sure there's space on the stack */
2151 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++)
2152 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[argnum])) + 7) & ~7);
2153 sp -= stack_alloc; /* make room on stack for args */
2155 /* Now load as many as possible of the first arguments into
2156 registers, and push the rest onto the stack. There are 64 bytes
2157 in eight registers available. Loop thru args from first to last. */
2159 int_argreg = tdep->ARG0_REGNUM;
2160 float_argreg = FP0_REGNUM;
2161 double_argreg = tdep->DR0_REGNUM;
2163 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++)
2165 type = VALUE_TYPE (args[argnum]);
2166 len = TYPE_LENGTH (type);
2167 memset (valbuf, 0, sizeof (valbuf));
2169 if (TYPE_CODE (type) != TYPE_CODE_FLT)
2171 argreg_size = REGISTER_RAW_SIZE (int_argreg);
2173 if (len < argreg_size)
2175 /* value gets right-justified in the register or stack word */
2176 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2177 memcpy (valbuf + argreg_size - len,
2178 (char *) VALUE_CONTENTS (args[argnum]), len);
2180 memcpy (valbuf, (char *) VALUE_CONTENTS (args[argnum]), len);
2185 val = (char *) VALUE_CONTENTS (args[argnum]);
2189 if (int_argreg > tdep->ARGLAST_REGNUM)
2191 /* must go on the stack */
2192 write_memory (sp + stack_offset, val, argreg_size);
2193 stack_offset += 8;/*argreg_size;*/
2195 /* NOTE WELL!!!!! This is not an "else if" clause!!!
2196 That's because some *&^%$ things get passed on the stack
2197 AND in the registers! */
2198 if (int_argreg <= tdep->ARGLAST_REGNUM)
2200 /* there's room in a register */
2201 regval = extract_address (val, argreg_size);
2202 write_register (int_argreg, regval);
2204 /* Store the value 8 bytes at a time. This means that
2205 things larger than 8 bytes may go partly in registers
2206 and partly on the stack. FIXME: argreg is incremented
2207 before we use its size. */
2215 val = (char *) VALUE_CONTENTS (args[argnum]);
2218 /* Where is it going to be stored? */
2219 while (fp_args[float_arg_index])
2222 /* Now float_argreg points to the register where it
2223 should be stored. Are we still within the allowed
2225 if (float_arg_index <= tdep->FLOAT_ARGLAST_REGNUM)
2227 /* Goes in FR0...FR11 */
2228 deprecated_write_register_gen (FP0_REGNUM + float_arg_index,
2230 fp_args[float_arg_index] = 1;
2231 /* Skip the corresponding general argument register. */
2236 /* Store it as the integers, 8 bytes at the time, if
2237 necessary spilling on the stack. */
2242 /* Where is it going to be stored? */
2243 while (fp_args[double_arg_index])
2244 double_arg_index += 2;
2245 /* Now double_argreg points to the register
2246 where it should be stored.
2247 Are we still within the allowed register set? */
2248 if (double_arg_index < tdep->FLOAT_ARGLAST_REGNUM)
2250 /* Goes in DR0...DR10 */
2251 /* The numbering of the DRi registers is consecutive,
2252 i.e. includes odd numbers. */
2253 int double_register_offset = double_arg_index / 2;
2254 int regnum = tdep->DR0_REGNUM +
2255 double_register_offset;
2257 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2259 memset (valbuf_tmp, 0, sizeof (valbuf_tmp));
2260 REGISTER_CONVERT_TO_VIRTUAL (regnum,
2261 type, val, valbuf_tmp);
2265 /* Note: must use write_register_gen here instead
2266 of regcache_raw_write, because
2267 regcache_raw_write works only for real
2268 registers, not pseudo. write_register_gen will
2269 call the gdbarch function to do register
2270 writes, and that will properly know how to deal
2272 deprecated_write_register_gen (regnum, val);
2273 fp_args[double_arg_index] = 1;
2274 fp_args[double_arg_index + 1] = 1;
2275 /* Skip the corresponding general argument register. */
2280 /* Store it as the integers, 8 bytes at the time, if
2281 necessary spilling on the stack. */
2288 /* Function: push_return_address (pc)
2289 Set up the return address for the inferior function call.
2290 Needed for targets where we don't actually execute a JSR/BSR instruction */
2293 sh_push_return_address (CORE_ADDR pc, CORE_ADDR sp)
2295 write_register (gdbarch_tdep (current_gdbarch)->PR_REGNUM,
2296 CALL_DUMMY_ADDRESS ());
2300 /* Function: fix_call_dummy
2301 Poke the callee function's address into the destination part of
2302 the CALL_DUMMY. The address is actually stored in a data word
2303 following the actualy CALL_DUMMY instructions, which will load
2304 it into a register using PC-relative addressing. This function
2305 expects the CALL_DUMMY to look like this:
2316 sh_fix_call_dummy (char *dummy, CORE_ADDR pc, CORE_ADDR fun, int nargs,
2317 struct value **args, struct type *type, int gcc_p)
2319 *(unsigned long *) (dummy + 8) = fun;
2323 /* Find a function's return value in the appropriate registers (in
2324 regbuf), and copy it into valbuf. Extract from an array REGBUF
2325 containing the (raw) register state a function return value of type
2326 TYPE, and copy that, in virtual format, into VALBUF. */
2328 sh_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2330 int len = TYPE_LENGTH (type);
2331 int return_register = R0_REGNUM;
2336 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2337 offset = REGISTER_BYTE (return_register) + 4 - len;
2339 offset = REGISTER_BYTE (return_register);
2340 memcpy (valbuf, regbuf + offset, len);
2344 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2345 offset = REGISTER_BYTE (return_register) + 8 - len;
2347 offset = REGISTER_BYTE (return_register);
2348 memcpy (valbuf, regbuf + offset, len);
2351 error ("bad size for return value");
2355 sh3e_sh4_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2357 int return_register;
2359 int len = TYPE_LENGTH (type);
2361 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2362 return_register = FP0_REGNUM;
2364 return_register = R0_REGNUM;
2366 if (len == 8 && TYPE_CODE (type) == TYPE_CODE_FLT)
2369 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2370 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2371 (char *) regbuf + REGISTER_BYTE (return_register),
2374 floatformat_to_doublest (&floatformat_ieee_double_big,
2375 (char *) regbuf + REGISTER_BYTE (return_register),
2377 store_floating (valbuf, len, val);
2381 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2382 offset = REGISTER_BYTE (return_register) + 4 - len;
2384 offset = REGISTER_BYTE (return_register);
2385 memcpy (valbuf, regbuf + offset, len);
2389 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2390 offset = REGISTER_BYTE (return_register) + 8 - len;
2392 offset = REGISTER_BYTE (return_register);
2393 memcpy (valbuf, regbuf + offset, len);
2396 error ("bad size for return value");
2400 sh64_extract_return_value (struct type *type, char *regbuf, char *valbuf)
2403 int return_register;
2404 int len = TYPE_LENGTH (type);
2405 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2407 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2411 /* Return value stored in FP0_REGNUM */
2412 return_register = FP0_REGNUM;
2413 offset = REGISTER_BYTE (return_register);
2414 memcpy (valbuf, (char *) regbuf + offset, len);
2418 /* return value stored in DR0_REGNUM */
2421 return_register = tdep->DR0_REGNUM;
2422 offset = REGISTER_BYTE (return_register);
2424 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2425 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
2426 (char *) regbuf + offset, &val);
2428 floatformat_to_doublest (&floatformat_ieee_double_big,
2429 (char *) regbuf + offset, &val);
2430 store_floating (valbuf, len, val);
2437 /* Result is in register 2. If smaller than 8 bytes, it is padded
2438 at the most significant end. */
2439 return_register = tdep->RETURN_REGNUM;
2440 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2441 offset = REGISTER_BYTE (return_register) +
2442 REGISTER_RAW_SIZE (return_register) - len;
2444 offset = REGISTER_BYTE (return_register);
2445 memcpy (valbuf, (char *) regbuf + offset, len);
2448 error ("bad size for return value");
2452 /* Write into appropriate registers a function return value
2453 of type TYPE, given in virtual format.
2454 If the architecture is sh4 or sh3e, store a function's return value
2455 in the R0 general register or in the FP0 floating point register,
2456 depending on the type of the return value. In all the other cases
2457 the result is stored in r0, left-justified. */
2459 sh_default_store_return_value (struct type *type, char *valbuf)
2461 char buf[32]; /* more than enough... */
2463 if (TYPE_LENGTH (type) < REGISTER_RAW_SIZE (R0_REGNUM))
2465 /* Add leading zeros to the value. */
2466 memset (buf, 0, REGISTER_RAW_SIZE (R0_REGNUM));
2467 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2468 memcpy (buf + REGISTER_RAW_SIZE (R0_REGNUM) - TYPE_LENGTH (type),
2469 valbuf, TYPE_LENGTH (type));
2471 memcpy (buf, valbuf, TYPE_LENGTH (type));
2472 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), buf,
2473 REGISTER_RAW_SIZE (R0_REGNUM));
2476 deprecated_write_register_bytes (REGISTER_BYTE (R0_REGNUM), valbuf,
2477 TYPE_LENGTH (type));
2481 sh3e_sh4_store_return_value (struct type *type, char *valbuf)
2483 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2484 deprecated_write_register_bytes (REGISTER_BYTE (FP0_REGNUM),
2485 valbuf, TYPE_LENGTH (type));
2487 sh_default_store_return_value (type, valbuf);
2491 sh64_store_return_value (struct type *type, char *valbuf)
2493 char buf[64]; /* more than enough... */
2494 int len = TYPE_LENGTH (type);
2496 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2500 /* Return value stored in FP0_REGNUM */
2501 deprecated_write_register_gen (FP0_REGNUM, valbuf);
2505 /* return value stored in DR0_REGNUM */
2506 /* FIXME: Implement */
2511 int return_register = gdbarch_tdep (current_gdbarch)->RETURN_REGNUM;
2514 if (len <= REGISTER_RAW_SIZE (return_register))
2516 /* Pad with zeros. */
2517 memset (buf, 0, REGISTER_RAW_SIZE (return_register));
2518 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
2519 offset = 0; /*REGISTER_RAW_SIZE (return_register) - len;*/
2521 offset = REGISTER_RAW_SIZE (return_register) - len;
2523 memcpy (buf + offset, valbuf, len);
2524 deprecated_write_register_gen (return_register, buf);
2527 deprecated_write_register_gen (return_register, valbuf);
2531 /* Print the registers in a form similar to the E7000 */
2534 sh_generic_show_regs (void)
2536 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2538 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2539 paddr (read_register (PC_REGNUM)),
2540 (long) read_register (tdep->SR_REGNUM),
2541 (long) read_register (tdep->PR_REGNUM),
2542 (long) read_register (MACH_REGNUM),
2543 (long) read_register (MACL_REGNUM));
2545 printf_filtered ("GBR=%08lx VBR=%08lx",
2546 (long) read_register (GBR_REGNUM),
2547 (long) read_register (VBR_REGNUM));
2549 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2550 (long) read_register (0),
2551 (long) read_register (1),
2552 (long) read_register (2),
2553 (long) read_register (3),
2554 (long) read_register (4),
2555 (long) read_register (5),
2556 (long) read_register (6),
2557 (long) read_register (7));
2558 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2559 (long) read_register (8),
2560 (long) read_register (9),
2561 (long) read_register (10),
2562 (long) read_register (11),
2563 (long) read_register (12),
2564 (long) read_register (13),
2565 (long) read_register (14),
2566 (long) read_register (15));
2570 sh3_show_regs (void)
2572 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2574 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2575 paddr (read_register (PC_REGNUM)),
2576 (long) read_register (tdep->SR_REGNUM),
2577 (long) read_register (tdep->PR_REGNUM),
2578 (long) read_register (MACH_REGNUM),
2579 (long) read_register (MACL_REGNUM));
2581 printf_filtered ("GBR=%08lx VBR=%08lx",
2582 (long) read_register (GBR_REGNUM),
2583 (long) read_register (VBR_REGNUM));
2584 printf_filtered (" SSR=%08lx SPC=%08lx",
2585 (long) read_register (tdep->SSR_REGNUM),
2586 (long) read_register (tdep->SPC_REGNUM));
2588 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2589 (long) read_register (0),
2590 (long) read_register (1),
2591 (long) read_register (2),
2592 (long) read_register (3),
2593 (long) read_register (4),
2594 (long) read_register (5),
2595 (long) read_register (6),
2596 (long) read_register (7));
2597 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2598 (long) read_register (8),
2599 (long) read_register (9),
2600 (long) read_register (10),
2601 (long) read_register (11),
2602 (long) read_register (12),
2603 (long) read_register (13),
2604 (long) read_register (14),
2605 (long) read_register (15));
2610 sh3e_show_regs (void)
2612 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2614 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2615 paddr (read_register (PC_REGNUM)),
2616 (long) read_register (tdep->SR_REGNUM),
2617 (long) read_register (tdep->PR_REGNUM),
2618 (long) read_register (MACH_REGNUM),
2619 (long) read_register (MACL_REGNUM));
2621 printf_filtered ("GBR=%08lx VBR=%08lx",
2622 (long) read_register (GBR_REGNUM),
2623 (long) read_register (VBR_REGNUM));
2624 printf_filtered (" SSR=%08lx SPC=%08lx",
2625 (long) read_register (tdep->SSR_REGNUM),
2626 (long) read_register (tdep->SPC_REGNUM));
2627 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2628 (long) read_register (tdep->FPUL_REGNUM),
2629 (long) read_register (tdep->FPSCR_REGNUM));
2631 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2632 (long) read_register (0),
2633 (long) read_register (1),
2634 (long) read_register (2),
2635 (long) read_register (3),
2636 (long) read_register (4),
2637 (long) read_register (5),
2638 (long) read_register (6),
2639 (long) read_register (7));
2640 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2641 (long) read_register (8),
2642 (long) read_register (9),
2643 (long) read_register (10),
2644 (long) read_register (11),
2645 (long) read_register (12),
2646 (long) read_register (13),
2647 (long) read_register (14),
2648 (long) read_register (15));
2650 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2651 (long) read_register (FP0_REGNUM + 0),
2652 (long) read_register (FP0_REGNUM + 1),
2653 (long) read_register (FP0_REGNUM + 2),
2654 (long) read_register (FP0_REGNUM + 3),
2655 (long) read_register (FP0_REGNUM + 4),
2656 (long) read_register (FP0_REGNUM + 5),
2657 (long) read_register (FP0_REGNUM + 6),
2658 (long) read_register (FP0_REGNUM + 7));
2659 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2660 (long) read_register (FP0_REGNUM + 8),
2661 (long) read_register (FP0_REGNUM + 9),
2662 (long) read_register (FP0_REGNUM + 10),
2663 (long) read_register (FP0_REGNUM + 11),
2664 (long) read_register (FP0_REGNUM + 12),
2665 (long) read_register (FP0_REGNUM + 13),
2666 (long) read_register (FP0_REGNUM + 14),
2667 (long) read_register (FP0_REGNUM + 15));
2671 sh3_dsp_show_regs (void)
2673 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2675 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2676 paddr (read_register (PC_REGNUM)),
2677 (long) read_register (tdep->SR_REGNUM),
2678 (long) read_register (tdep->PR_REGNUM),
2679 (long) read_register (MACH_REGNUM),
2680 (long) read_register (MACL_REGNUM));
2682 printf_filtered ("GBR=%08lx VBR=%08lx",
2683 (long) read_register (GBR_REGNUM),
2684 (long) read_register (VBR_REGNUM));
2686 printf_filtered (" SSR=%08lx SPC=%08lx",
2687 (long) read_register (tdep->SSR_REGNUM),
2688 (long) read_register (tdep->SPC_REGNUM));
2690 printf_filtered (" DSR=%08lx",
2691 (long) read_register (tdep->DSR_REGNUM));
2693 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2694 (long) read_register (0),
2695 (long) read_register (1),
2696 (long) read_register (2),
2697 (long) read_register (3),
2698 (long) read_register (4),
2699 (long) read_register (5),
2700 (long) read_register (6),
2701 (long) read_register (7));
2702 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2703 (long) read_register (8),
2704 (long) read_register (9),
2705 (long) read_register (10),
2706 (long) read_register (11),
2707 (long) read_register (12),
2708 (long) read_register (13),
2709 (long) read_register (14),
2710 (long) read_register (15));
2712 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2713 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2714 (long) read_register (tdep->A0_REGNUM),
2715 (long) read_register (tdep->M0_REGNUM),
2716 (long) read_register (tdep->X0_REGNUM),
2717 (long) read_register (tdep->Y0_REGNUM),
2718 (long) read_register (tdep->RS_REGNUM),
2719 (long) read_register (tdep->MOD_REGNUM));
2720 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2721 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2722 (long) read_register (tdep->A1_REGNUM),
2723 (long) read_register (tdep->M1_REGNUM),
2724 (long) read_register (tdep->X1_REGNUM),
2725 (long) read_register (tdep->Y1_REGNUM),
2726 (long) read_register (tdep->RE_REGNUM));
2730 sh4_show_regs (void)
2732 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2734 int pr = read_register (tdep->FPSCR_REGNUM) & 0x80000;
2735 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2736 paddr (read_register (PC_REGNUM)),
2737 (long) read_register (tdep->SR_REGNUM),
2738 (long) read_register (tdep->PR_REGNUM),
2739 (long) read_register (MACH_REGNUM),
2740 (long) read_register (MACL_REGNUM));
2742 printf_filtered ("GBR=%08lx VBR=%08lx",
2743 (long) read_register (GBR_REGNUM),
2744 (long) read_register (VBR_REGNUM));
2745 printf_filtered (" SSR=%08lx SPC=%08lx",
2746 (long) read_register (tdep->SSR_REGNUM),
2747 (long) read_register (tdep->SPC_REGNUM));
2748 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
2749 (long) read_register (tdep->FPUL_REGNUM),
2750 (long) read_register (tdep->FPSCR_REGNUM));
2752 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2753 (long) read_register (0),
2754 (long) read_register (1),
2755 (long) read_register (2),
2756 (long) read_register (3),
2757 (long) read_register (4),
2758 (long) read_register (5),
2759 (long) read_register (6),
2760 (long) read_register (7));
2761 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2762 (long) read_register (8),
2763 (long) read_register (9),
2764 (long) read_register (10),
2765 (long) read_register (11),
2766 (long) read_register (12),
2767 (long) read_register (13),
2768 (long) read_register (14),
2769 (long) read_register (15));
2771 printf_filtered ((pr
2772 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2773 : "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2774 (long) read_register (FP0_REGNUM + 0),
2775 (long) read_register (FP0_REGNUM + 1),
2776 (long) read_register (FP0_REGNUM + 2),
2777 (long) read_register (FP0_REGNUM + 3),
2778 (long) read_register (FP0_REGNUM + 4),
2779 (long) read_register (FP0_REGNUM + 5),
2780 (long) read_register (FP0_REGNUM + 6),
2781 (long) read_register (FP0_REGNUM + 7));
2782 printf_filtered ((pr
2783 ? "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
2784 : "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
2785 (long) read_register (FP0_REGNUM + 8),
2786 (long) read_register (FP0_REGNUM + 9),
2787 (long) read_register (FP0_REGNUM + 10),
2788 (long) read_register (FP0_REGNUM + 11),
2789 (long) read_register (FP0_REGNUM + 12),
2790 (long) read_register (FP0_REGNUM + 13),
2791 (long) read_register (FP0_REGNUM + 14),
2792 (long) read_register (FP0_REGNUM + 15));
2796 sh_dsp_show_regs (void)
2798 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2800 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
2801 paddr (read_register (PC_REGNUM)),
2802 (long) read_register (tdep->SR_REGNUM),
2803 (long) read_register (tdep->PR_REGNUM),
2804 (long) read_register (MACH_REGNUM),
2805 (long) read_register (MACL_REGNUM));
2807 printf_filtered ("GBR=%08lx VBR=%08lx",
2808 (long) read_register (GBR_REGNUM),
2809 (long) read_register (VBR_REGNUM));
2811 printf_filtered (" DSR=%08lx",
2812 (long) read_register (tdep->DSR_REGNUM));
2814 printf_filtered ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2815 (long) read_register (0),
2816 (long) read_register (1),
2817 (long) read_register (2),
2818 (long) read_register (3),
2819 (long) read_register (4),
2820 (long) read_register (5),
2821 (long) read_register (6),
2822 (long) read_register (7));
2823 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2824 (long) read_register (8),
2825 (long) read_register (9),
2826 (long) read_register (10),
2827 (long) read_register (11),
2828 (long) read_register (12),
2829 (long) read_register (13),
2830 (long) read_register (14),
2831 (long) read_register (15));
2833 printf_filtered ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
2834 (long) read_register (tdep->A0G_REGNUM) & 0xff,
2835 (long) read_register (tdep->A0_REGNUM),
2836 (long) read_register (tdep->M0_REGNUM),
2837 (long) read_register (tdep->X0_REGNUM),
2838 (long) read_register (tdep->Y0_REGNUM),
2839 (long) read_register (tdep->RS_REGNUM),
2840 (long) read_register (tdep->MOD_REGNUM));
2841 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
2842 (long) read_register (tdep->A1G_REGNUM) & 0xff,
2843 (long) read_register (tdep->A1_REGNUM),
2844 (long) read_register (tdep->M1_REGNUM),
2845 (long) read_register (tdep->X1_REGNUM),
2846 (long) read_register (tdep->Y1_REGNUM),
2847 (long) read_register (tdep->RE_REGNUM));
2851 sh64_show_media_regs (void)
2854 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2856 printf_filtered ("PC=%s SR=%016llx \n",
2857 paddr (read_register (PC_REGNUM)),
2858 (long long) read_register (tdep->SR_REGNUM));
2860 printf_filtered ("SSR=%016llx SPC=%016llx \n",
2861 (long long) read_register (tdep->SSR_REGNUM),
2862 (long long) read_register (tdep->SPC_REGNUM));
2863 printf_filtered ("FPSCR=%016lx\n ",
2864 (long) read_register (tdep->FPSCR_REGNUM));
2866 for (i = 0; i < 64; i = i + 4)
2867 printf_filtered ("\nR%d-R%d %016llx %016llx %016llx %016llx\n",
2869 (long long) read_register (i + 0),
2870 (long long) read_register (i + 1),
2871 (long long) read_register (i + 2),
2872 (long long) read_register (i + 3));
2874 printf_filtered ("\n");
2876 for (i = 0; i < 64; i = i + 8)
2877 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2879 (long) read_register (FP0_REGNUM + i + 0),
2880 (long) read_register (FP0_REGNUM + i + 1),
2881 (long) read_register (FP0_REGNUM + i + 2),
2882 (long) read_register (FP0_REGNUM + i + 3),
2883 (long) read_register (FP0_REGNUM + i + 4),
2884 (long) read_register (FP0_REGNUM + i + 5),
2885 (long) read_register (FP0_REGNUM + i + 6),
2886 (long) read_register (FP0_REGNUM + i + 7));
2890 sh64_show_compact_regs (void)
2893 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2895 printf_filtered ("PC=%s \n",
2896 paddr (read_register (tdep->PC_C_REGNUM)));
2898 printf_filtered ("GBR=%08lx MACH=%08lx MACL=%08lx PR=%08lx T=%08lx\n",
2899 (long) read_register (tdep->GBR_C_REGNUM),
2900 (long) read_register (tdep->MACH_C_REGNUM),
2901 (long) read_register (tdep->MACL_C_REGNUM),
2902 (long) read_register (tdep->PR_C_REGNUM),
2903 (long) read_register (tdep->T_C_REGNUM));
2904 printf_filtered ("FPSCR=%08lx FPUL=%08lx\n",
2905 (long) read_register (tdep->FPSCR_REGNUM),
2906 (long) read_register (tdep->FPUL_REGNUM));
2908 for (i = 0; i < 16; i = i + 4)
2909 printf_filtered ("\nR%d-R%d %08lx %08lx %08lx %08lx\n",
2911 (long) read_register (i + 0),
2912 (long) read_register (i + 1),
2913 (long) read_register (i + 2),
2914 (long) read_register (i + 3));
2916 printf_filtered ("\n");
2918 for (i = 0; i < 16; i = i + 8)
2919 printf_filtered ("FR%d-FR%d %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
2921 (long) read_register (FP0_REGNUM + i + 0),
2922 (long) read_register (FP0_REGNUM + i + 1),
2923 (long) read_register (FP0_REGNUM + i + 2),
2924 (long) read_register (FP0_REGNUM + i + 3),
2925 (long) read_register (FP0_REGNUM + i + 4),
2926 (long) read_register (FP0_REGNUM + i + 5),
2927 (long) read_register (FP0_REGNUM + i + 6),
2928 (long) read_register (FP0_REGNUM + i + 7));
2931 /*FIXME!!! This only shows the registers for shmedia, excluding the
2932 pseudo registers. */
2934 sh64_show_regs (void)
2936 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
2937 sh64_show_media_regs ();
2939 sh64_show_compact_regs ();
2942 void sh_show_regs_command (char *args, int from_tty)
2948 /* Index within `registers' of the first byte of the space for
2951 sh_default_register_byte (int reg_nr)
2953 return (reg_nr * 4);
2957 sh_sh4_register_byte (int reg_nr)
2959 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2961 if (reg_nr >= tdep->DR0_REGNUM
2962 && reg_nr <= tdep->DR_LAST_REGNUM)
2963 return (dr_reg_base_num (reg_nr) * 4);
2964 else if (reg_nr >= tdep->FV0_REGNUM
2965 && reg_nr <= tdep->FV_LAST_REGNUM)
2966 return (fv_reg_base_num (reg_nr) * 4);
2968 return (reg_nr * 4);
2973 SH MEDIA MODE (ISA 32)
2974 general registers (64-bit) 0-63
2975 0 r0, r1, r2, r3, r4, r5, r6, r7,
2976 64 r8, r9, r10, r11, r12, r13, r14, r15,
2977 128 r16, r17, r18, r19, r20, r21, r22, r23,
2978 192 r24, r25, r26, r27, r28, r29, r30, r31,
2979 256 r32, r33, r34, r35, r36, r37, r38, r39,
2980 320 r40, r41, r42, r43, r44, r45, r46, r47,
2981 384 r48, r49, r50, r51, r52, r53, r54, r55,
2982 448 r56, r57, r58, r59, r60, r61, r62, r63,
2987 status reg., saved status reg., saved pc reg. (64-bit) 65-67
2990 target registers (64-bit) 68-75
2991 544 tr0, tr1, tr2, tr3, tr4, tr5, tr6, tr7,
2993 floating point state control register (32-bit) 76
2996 single precision floating point registers (32-bit) 77-140
2997 612 fr0, fr1, fr2, fr3, fr4, fr5, fr6, fr7,
2998 644 fr8, fr9, fr10, fr11, fr12, fr13, fr14, fr15,
2999 676 fr16, fr17, fr18, fr19, fr20, fr21, fr22, fr23,
3000 708 fr24, fr25, fr26, fr27, fr28, fr29, fr30, fr31,
3001 740 fr32, fr33, fr34, fr35, fr36, fr37, fr38, fr39,
3002 772 fr40, fr41, fr42, fr43, fr44, fr45, fr46, fr47,
3003 804 fr48, fr49, fr50, fr51, fr52, fr53, fr54, fr55,
3004 836 fr56, fr57, fr58, fr59, fr60, fr61, fr62, fr63,
3006 TOTAL SPACE FOR REGISTERS: 868 bytes
3008 From here on they are all pseudo registers: no memory allocated.
3009 REGISTER_BYTE returns the register byte for the base register.
3011 double precision registers (pseudo) 141-172
3012 dr0, dr2, dr4, dr6, dr8, dr10, dr12, dr14,
3013 dr16, dr18, dr20, dr22, dr24, dr26, dr28, dr30,
3014 dr32, dr34, dr36, dr38, dr40, dr42, dr44, dr46,
3015 dr48, dr50, dr52, dr54, dr56, dr58, dr60, dr62,
3017 floating point pairs (pseudo) 173-204
3018 fp0, fp2, fp4, fp6, fp8, fp10, fp12, fp14,
3019 fp16, fp18, fp20, fp22, fp24, fp26, fp28, fp30,
3020 fp32, fp34, fp36, fp38, fp40, fp42, fp44, fp46,
3021 fp48, fp50, fp52, fp54, fp56, fp58, fp60, fp62,
3023 floating point vectors (4 floating point regs) (pseudo) 205-220
3024 fv0, fv4, fv8, fv12, fv16, fv20, fv24, fv28,
3025 fv32, fv36, fv40, fv44, fv48, fv52, fv56, fv60,
3027 SH COMPACT MODE (ISA 16) (all pseudo) 221-272
3028 r0_c, r1_c, r2_c, r3_c, r4_c, r5_c, r6_c, r7_c,
3029 r8_c, r9_c, r10_c, r11_c, r12_c, r13_c, r14_c, r15_c,
3031 gbr_c, mach_c, macl_c, pr_c, t_c,
3033 fr0_c, fr1_c, fr2_c, fr3_c, fr4_c, fr5_c, fr6_c, fr7_c,
3034 fr8_c, fr9_c, fr10_c, fr11_c, fr12_c, fr13_c, fr14_c, fr15_c
3035 dr0_c, dr2_c, dr4_c, dr6_c, dr8_c, dr10_c, dr12_c, dr14_c
3036 fv0_c, fv4_c, fv8_c, fv12_c
3040 sh_sh64_register_byte (int reg_nr)
3042 int base_regnum = -1;
3043 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3045 /* If it is a pseudo register, get the number of the first floating
3046 point register that is part of it. */
3047 if (reg_nr >= tdep->DR0_REGNUM
3048 && reg_nr <= tdep->DR_LAST_REGNUM)
3049 base_regnum = dr_reg_base_num (reg_nr);
3051 else if (reg_nr >= tdep->FPP0_REGNUM
3052 && reg_nr <= tdep->FPP_LAST_REGNUM)
3053 base_regnum = fpp_reg_base_num (reg_nr);
3055 else if (reg_nr >= tdep->FV0_REGNUM
3056 && reg_nr <= tdep->FV_LAST_REGNUM)
3057 base_regnum = fv_reg_base_num (reg_nr);
3059 /* sh compact pseudo register. FPSCR is a pathological case, need to
3060 treat it as special. */
3061 else if ((reg_nr >= tdep->R0_C_REGNUM
3062 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3063 && reg_nr != tdep->FPSCR_C_REGNUM)
3064 base_regnum = sh64_compact_reg_base_num (reg_nr);
3066 /* Now return the offset in bytes within the register cache. */
3067 /* sh media pseudo register, i.e. any of DR, FFP, FV registers. */
3068 if (reg_nr >= tdep->DR0_REGNUM
3069 && reg_nr <= tdep->FV_LAST_REGNUM)
3070 return (base_regnum - FP0_REGNUM + 1) * 4
3071 + (tdep->TR7_REGNUM + 1) * 8;
3073 /* sh compact pseudo register: general register */
3074 if ((reg_nr >= tdep->R0_C_REGNUM
3075 && reg_nr <= tdep->R_LAST_C_REGNUM))
3076 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3077 ? base_regnum * 8 + 4
3080 /* sh compact pseudo register: */
3081 if (reg_nr == tdep->PC_C_REGNUM
3082 || reg_nr == tdep->GBR_C_REGNUM
3083 || reg_nr == tdep->MACL_C_REGNUM
3084 || reg_nr == tdep->PR_C_REGNUM)
3085 return (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
3086 ? base_regnum * 8 + 4
3089 if (reg_nr == tdep->MACH_C_REGNUM)
3090 return base_regnum * 8;
3092 if (reg_nr == tdep->T_C_REGNUM)
3093 return base_regnum * 8; /* FIXME??? how do we get bit 0? Do we have to? */
3095 /* sh compact pseudo register: floating point register */
3096 else if (reg_nr >=tdep->FP0_C_REGNUM
3097 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3098 return (base_regnum - FP0_REGNUM) * 4
3099 + (tdep->TR7_REGNUM + 1) * 8 + 4;
3101 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3102 /* This is complicated, for now return the beginning of the
3103 architectural FPSCR register. */
3104 return (tdep->TR7_REGNUM + 1) * 8;
3106 else if (reg_nr == tdep->FPUL_C_REGNUM)
3107 return ((base_regnum - FP0_REGNUM) * 4 +
3108 (tdep->TR7_REGNUM + 1) * 8 + 4);
3110 /* It is not a pseudo register. */
3111 /* It is a 64 bit register. */
3112 else if (reg_nr <= tdep->TR7_REGNUM)
3115 /* It is a 32 bit register. */
3117 if (reg_nr == tdep->FPSCR_REGNUM)
3118 return (tdep->FPSCR_REGNUM * 8);
3120 /* It is floating point 32-bit register */
3122 return ((tdep->TR7_REGNUM + 1) * 8
3123 + (reg_nr - FP0_REGNUM + 1) * 4);
3126 /* Number of bytes of storage in the actual machine representation for
3129 sh_default_register_raw_size (int reg_nr)
3135 sh_sh4_register_raw_size (int reg_nr)
3137 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3139 if (reg_nr >= tdep->DR0_REGNUM
3140 && reg_nr <= tdep->DR_LAST_REGNUM)
3142 else if (reg_nr >= tdep->FV0_REGNUM
3143 && reg_nr <= tdep->FV_LAST_REGNUM)
3150 sh_sh64_register_raw_size (int reg_nr)
3152 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3154 if ((reg_nr >= tdep->DR0_REGNUM
3155 && reg_nr <= tdep->DR_LAST_REGNUM)
3156 || (reg_nr >= tdep->FPP0_REGNUM
3157 && reg_nr <= tdep->FPP_LAST_REGNUM)
3158 || (reg_nr >= tdep->DR0_C_REGNUM
3159 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3160 || (reg_nr <= tdep->TR7_REGNUM))
3163 else if ((reg_nr >= tdep->FV0_REGNUM
3164 && reg_nr <= tdep->FV_LAST_REGNUM)
3165 || (reg_nr >= tdep->FV0_C_REGNUM
3166 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3169 else /* this covers also the 32-bit SH compact registers. */
3173 /* Number of bytes of storage in the program's representation
3176 sh_register_virtual_size (int reg_nr)
3183 sh_sh64_register_virtual_size (int reg_nr)
3185 if (reg_nr >= FP0_REGNUM
3186 && reg_nr <= gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM)
3192 /* Return the GDB type object for the "standard" data type
3193 of data in register N. */
3194 static struct type *
3195 sh_sh3e_register_virtual_type (int reg_nr)
3197 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3199 if ((reg_nr >= FP0_REGNUM
3200 && (reg_nr <= tdep->FP_LAST_REGNUM))
3201 || (reg_nr == tdep->FPUL_REGNUM))
3202 return builtin_type_float;
3204 return builtin_type_int;
3207 static struct type *
3208 sh_sh4_build_float_register_type (int high)
3212 temp = create_range_type (NULL, builtin_type_int, 0, high);
3213 return create_array_type (NULL, builtin_type_float, temp);
3216 static struct type *
3217 sh_sh4_register_virtual_type (int reg_nr)
3219 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3221 if ((reg_nr >= FP0_REGNUM
3222 && (reg_nr <= tdep->FP_LAST_REGNUM))
3223 || (reg_nr == tdep->FPUL_REGNUM))
3224 return builtin_type_float;
3225 else if (reg_nr >= tdep->DR0_REGNUM
3226 && reg_nr <= tdep->DR_LAST_REGNUM)
3227 return builtin_type_double;
3228 else if (reg_nr >= tdep->FV0_REGNUM
3229 && reg_nr <= tdep->FV_LAST_REGNUM)
3230 return sh_sh4_build_float_register_type (3);
3232 return builtin_type_int;
3235 static struct type *
3236 sh_sh64_register_virtual_type (int reg_nr)
3238 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3240 if ((reg_nr >= FP0_REGNUM
3241 && reg_nr <= tdep->FP_LAST_REGNUM)
3242 || (reg_nr >= tdep->FP0_C_REGNUM
3243 && reg_nr <= tdep->FP_LAST_C_REGNUM))
3244 return builtin_type_float;
3245 else if ((reg_nr >= tdep->DR0_REGNUM
3246 && reg_nr <= tdep->DR_LAST_REGNUM)
3247 || (reg_nr >= tdep->DR0_C_REGNUM
3248 && reg_nr <= tdep->DR_LAST_C_REGNUM))
3249 return builtin_type_double;
3250 else if (reg_nr >= tdep->FPP0_REGNUM
3251 && reg_nr <= tdep->FPP_LAST_REGNUM)
3252 return sh_sh4_build_float_register_type (1);
3253 else if ((reg_nr >= tdep->FV0_REGNUM
3254 && reg_nr <= tdep->FV_LAST_REGNUM)
3255 ||(reg_nr >= tdep->FV0_C_REGNUM
3256 && reg_nr <= tdep->FV_LAST_C_REGNUM))
3257 return sh_sh4_build_float_register_type (3);
3258 else if (reg_nr == tdep->FPSCR_REGNUM)
3259 return builtin_type_int;
3260 else if (reg_nr >= tdep->R0_C_REGNUM
3261 && reg_nr < tdep->FP0_C_REGNUM)
3262 return builtin_type_int;
3264 return builtin_type_long_long;
3267 static struct type *
3268 sh_default_register_virtual_type (int reg_nr)
3270 return builtin_type_int;
3273 /* On the sh4, the DRi pseudo registers are problematic if the target
3274 is little endian. When the user writes one of those registers, for
3275 instance with 'ser var $dr0=1', we want the double to be stored
3277 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3278 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3280 This corresponds to little endian byte order & big endian word
3281 order. However if we let gdb write the register w/o conversion, it
3282 will write fr0 and fr1 this way:
3283 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3284 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
3285 because it will consider fr0 and fr1 as a single LE stretch of memory.
3287 To achieve what we want we must force gdb to store things in
3288 floatformat_ieee_double_littlebyte_bigword (which is defined in
3289 include/floatformat.h and libiberty/floatformat.c.
3291 In case the target is big endian, there is no problem, the
3292 raw bytes will look like:
3293 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
3294 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
3296 The other pseudo registers (the FVs) also don't pose a problem
3297 because they are stored as 4 individual FP elements. */
3300 sh_sh4_register_convert_to_virtual (int regnum, struct type *type,
3301 char *from, char *to)
3303 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3305 if (regnum >= tdep->DR0_REGNUM
3306 && regnum <= tdep->DR_LAST_REGNUM)
3309 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3310 store_floating (to, TYPE_LENGTH (type), val);
3313 error ("sh_register_convert_to_virtual called with non DR register number");
3317 sh_sh64_register_convert_to_virtual (int regnum, struct type *type,
3318 char *from, char *to)
3320 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3322 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3324 /* It is a no-op. */
3325 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3329 if ((regnum >= tdep->DR0_REGNUM
3330 && regnum <= tdep->DR_LAST_REGNUM)
3331 || (regnum >= tdep->DR0_C_REGNUM
3332 && regnum <= tdep->DR_LAST_C_REGNUM))
3335 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword, from, &val);
3336 store_floating(to, TYPE_LENGTH(type), val);
3339 error("sh_register_convert_to_virtual called with non DR register number");
3343 sh_sh4_register_convert_to_raw (struct type *type, int regnum,
3344 const void *from, void *to)
3346 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3348 if (regnum >= tdep->DR0_REGNUM
3349 && regnum <= tdep->DR_LAST_REGNUM)
3351 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3352 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3355 error("sh_register_convert_to_raw called with non DR register number");
3359 sh_sh64_register_convert_to_raw (struct type *type, int regnum,
3360 const void *from, void *to)
3362 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3364 if (TARGET_BYTE_ORDER != BFD_ENDIAN_LITTLE)
3366 /* It is a no-op. */
3367 memcpy (to, from, REGISTER_RAW_SIZE (regnum));
3371 if ((regnum >= tdep->DR0_REGNUM
3372 && regnum <= tdep->DR_LAST_REGNUM)
3373 || (regnum >= tdep->DR0_C_REGNUM
3374 && regnum <= tdep->DR_LAST_C_REGNUM))
3376 DOUBLEST val = extract_floating (from, TYPE_LENGTH(type));
3377 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword, &val, to);
3380 error("sh_register_convert_to_raw called with non DR register number");
3384 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3385 int reg_nr, void *buffer)
3387 int base_regnum, portion;
3388 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3389 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3391 if (reg_nr >= tdep->DR0_REGNUM
3392 && reg_nr <= tdep->DR_LAST_REGNUM)
3394 base_regnum = dr_reg_base_num (reg_nr);
3396 /* Build the value in the provided buffer. */
3397 /* Read the real regs for which this one is an alias. */
3398 for (portion = 0; portion < 2; portion++)
3399 regcache_raw_read (regcache, base_regnum + portion,
3401 + REGISTER_RAW_SIZE (base_regnum) * portion));
3402 /* We must pay attention to the endiannes. */
3403 sh_sh4_register_convert_to_virtual (reg_nr,
3404 REGISTER_VIRTUAL_TYPE (reg_nr),
3405 temp_buffer, buffer);
3407 else if (reg_nr >= tdep->FV0_REGNUM
3408 && reg_nr <= tdep->FV_LAST_REGNUM)
3410 base_regnum = fv_reg_base_num (reg_nr);
3412 /* Read the real regs for which this one is an alias. */
3413 for (portion = 0; portion < 4; portion++)
3414 regcache_raw_read (regcache, base_regnum + portion,
3416 + REGISTER_RAW_SIZE (base_regnum) * portion));
3421 sh64_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
3422 int reg_nr, void *buffer)
3427 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3428 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3430 if (reg_nr >= tdep->DR0_REGNUM
3431 && reg_nr <= tdep->DR_LAST_REGNUM)
3433 base_regnum = dr_reg_base_num (reg_nr);
3435 /* Build the value in the provided buffer. */
3436 /* DR regs are double precision registers obtained by
3437 concatenating 2 single precision floating point registers. */
3438 for (portion = 0; portion < 2; portion++)
3439 regcache_raw_read (regcache, base_regnum + portion,
3441 + REGISTER_RAW_SIZE (base_regnum) * portion));
3443 /* We must pay attention to the endiannes. */
3444 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3445 temp_buffer, buffer);
3449 else if (reg_nr >= tdep->FPP0_REGNUM
3450 && reg_nr <= tdep->FPP_LAST_REGNUM)
3452 base_regnum = fpp_reg_base_num (reg_nr);
3454 /* Build the value in the provided buffer. */
3455 /* FPP regs are pairs of single precision registers obtained by
3456 concatenating 2 single precision floating point registers. */
3457 for (portion = 0; portion < 2; portion++)
3458 regcache_raw_read (regcache, base_regnum + portion,
3460 + REGISTER_RAW_SIZE (base_regnum) * portion));
3463 else if (reg_nr >= tdep->FV0_REGNUM
3464 && reg_nr <= tdep->FV_LAST_REGNUM)
3466 base_regnum = fv_reg_base_num (reg_nr);
3468 /* Build the value in the provided buffer. */
3469 /* FV regs are vectors of single precision registers obtained by
3470 concatenating 4 single precision floating point registers. */
3471 for (portion = 0; portion < 4; portion++)
3472 regcache_raw_read (regcache, base_regnum + portion,
3474 + REGISTER_RAW_SIZE (base_regnum) * portion));
3477 /* sh compact pseudo registers. 1-to-1 with a shmedia register */
3478 else if (reg_nr >= tdep->R0_C_REGNUM
3479 && reg_nr <= tdep->T_C_REGNUM)
3481 base_regnum = sh64_compact_reg_base_num (reg_nr);
3483 /* Build the value in the provided buffer. */
3484 regcache_raw_read (regcache, base_regnum, temp_buffer);
3485 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3487 memcpy (buffer, temp_buffer + offset, 4); /* get LOWER 32 bits only????*/
3490 else if (reg_nr >= tdep->FP0_C_REGNUM
3491 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3493 base_regnum = sh64_compact_reg_base_num (reg_nr);
3495 /* Build the value in the provided buffer. */
3496 /* Floating point registers map 1-1 to the media fp regs,
3497 they have the same size and endienness. */
3498 regcache_raw_read (regcache, base_regnum, buffer);
3501 else if (reg_nr >= tdep->DR0_C_REGNUM
3502 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3504 base_regnum = sh64_compact_reg_base_num (reg_nr);
3506 /* DR_C regs are double precision registers obtained by
3507 concatenating 2 single precision floating point registers. */
3508 for (portion = 0; portion < 2; portion++)
3509 regcache_raw_read (regcache, base_regnum + portion,
3511 + REGISTER_RAW_SIZE (base_regnum) * portion));
3513 /* We must pay attention to the endiannes. */
3514 sh_sh64_register_convert_to_virtual (reg_nr, REGISTER_VIRTUAL_TYPE (reg_nr),
3515 temp_buffer, buffer);
3518 else if (reg_nr >= tdep->FV0_C_REGNUM
3519 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3521 base_regnum = sh64_compact_reg_base_num (reg_nr);
3523 /* Build the value in the provided buffer. */
3524 /* FV_C regs are vectors of single precision registers obtained by
3525 concatenating 4 single precision floating point registers. */
3526 for (portion = 0; portion < 4; portion++)
3527 regcache_raw_read (regcache, base_regnum + portion,
3529 + REGISTER_RAW_SIZE (base_regnum) * portion));
3532 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3534 int fpscr_base_regnum;
3536 unsigned int fpscr_value;
3537 unsigned int sr_value;
3538 unsigned int fpscr_c_value;
3539 unsigned int fpscr_c_part1_value;
3540 unsigned int fpscr_c_part2_value;
3542 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3543 sr_base_regnum = tdep->SR_REGNUM;
3545 /* Build the value in the provided buffer. */
3546 /* FPSCR_C is a very weird register that contains sparse bits
3547 from the FPSCR and the SR architectural registers.
3554 2-17 Bit 2-18 of FPSCR
3555 18-20 Bits 12,13,14 of SR
3559 /* Get FPSCR into a local buffer */
3560 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3561 /* Get value as an int. */
3562 fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3563 /* Get SR into a local buffer */
3564 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3565 /* Get value as an int. */
3566 sr_value = extract_unsigned_integer (temp_buffer, 4);
3567 /* Build the new value. */
3568 fpscr_c_part1_value = fpscr_value & 0x3fffd;
3569 fpscr_c_part2_value = (sr_value & 0x7000) << 6;
3570 fpscr_c_value = fpscr_c_part1_value | fpscr_c_part2_value;
3571 /* Store that in out buffer!!! */
3572 store_unsigned_integer (buffer, 4, fpscr_c_value);
3573 /* FIXME There is surely an endianness gotcha here. */
3576 else if (reg_nr == tdep->FPUL_C_REGNUM)
3578 base_regnum = sh64_compact_reg_base_num (reg_nr);
3580 /* FPUL_C register is floating point register 32,
3581 same size, same endianness. */
3582 regcache_raw_read (regcache, base_regnum, buffer);
3587 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3588 int reg_nr, const void *buffer)
3590 int base_regnum, portion;
3591 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3592 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3594 if (reg_nr >= tdep->DR0_REGNUM
3595 && reg_nr <= tdep->DR_LAST_REGNUM)
3597 base_regnum = dr_reg_base_num (reg_nr);
3599 /* We must pay attention to the endiannes. */
3600 sh_sh4_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3601 buffer, temp_buffer);
3603 /* Write the real regs for which this one is an alias. */
3604 for (portion = 0; portion < 2; portion++)
3605 regcache_raw_write (regcache, base_regnum + portion,
3607 + REGISTER_RAW_SIZE (base_regnum) * portion));
3609 else if (reg_nr >= tdep->FV0_REGNUM
3610 && reg_nr <= tdep->FV_LAST_REGNUM)
3612 base_regnum = fv_reg_base_num (reg_nr);
3614 /* Write the real regs for which this one is an alias. */
3615 for (portion = 0; portion < 4; portion++)
3616 regcache_raw_write (regcache, base_regnum + portion,
3618 + REGISTER_RAW_SIZE (base_regnum) * portion));
3623 sh64_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
3624 int reg_nr, const void *buffer)
3626 int base_regnum, portion;
3628 char *temp_buffer = (char*) alloca (MAX_REGISTER_RAW_SIZE);
3629 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3631 if (reg_nr >= tdep->DR0_REGNUM
3632 && reg_nr <= tdep->DR_LAST_REGNUM)
3634 base_regnum = dr_reg_base_num (reg_nr);
3635 /* We must pay attention to the endiannes. */
3636 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3637 buffer, temp_buffer);
3640 /* Write the real regs for which this one is an alias. */
3641 for (portion = 0; portion < 2; portion++)
3642 regcache_raw_write (regcache, base_regnum + portion,
3644 + REGISTER_RAW_SIZE (base_regnum) * portion));
3647 else if (reg_nr >= tdep->FPP0_REGNUM
3648 && reg_nr <= tdep->FPP_LAST_REGNUM)
3650 base_regnum = fpp_reg_base_num (reg_nr);
3652 /* Write the real regs for which this one is an alias. */
3653 for (portion = 0; portion < 2; portion++)
3654 regcache_raw_write (regcache, base_regnum + portion,
3656 + REGISTER_RAW_SIZE (base_regnum) * portion));
3659 else if (reg_nr >= tdep->FV0_REGNUM
3660 && reg_nr <= tdep->FV_LAST_REGNUM)
3662 base_regnum = fv_reg_base_num (reg_nr);
3664 /* Write the real regs for which this one is an alias. */
3665 for (portion = 0; portion < 4; portion++)
3666 regcache_raw_write (regcache, base_regnum + portion,
3668 + REGISTER_RAW_SIZE (base_regnum) * portion));
3671 /* sh compact general pseudo registers. 1-to-1 with a shmedia
3672 register but only 4 bytes of it. */
3673 else if (reg_nr >= tdep->R0_C_REGNUM
3674 && reg_nr <= tdep->T_C_REGNUM)
3676 base_regnum = sh64_compact_reg_base_num (reg_nr);
3677 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
3678 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
3682 /* Let's read the value of the base register into a temporary
3683 buffer, so that overwriting the last four bytes with the new
3684 value of the pseudo will leave the upper 4 bytes unchanged. */
3685 regcache_raw_read (regcache, base_regnum, temp_buffer);
3686 /* Write as an 8 byte quantity */
3687 memcpy (temp_buffer + offset, buffer, 4);
3688 regcache_raw_write (regcache, base_regnum, temp_buffer);
3691 /* sh floating point compact pseudo registers. 1-to-1 with a shmedia
3692 registers. Both are 4 bytes. */
3693 else if (reg_nr >= tdep->FP0_C_REGNUM
3694 && reg_nr <= tdep->FP_LAST_C_REGNUM)
3696 base_regnum = sh64_compact_reg_base_num (reg_nr);
3697 regcache_raw_write (regcache, base_regnum, buffer);
3700 else if (reg_nr >= tdep->DR0_C_REGNUM
3701 && reg_nr <= tdep->DR_LAST_C_REGNUM)
3703 base_regnum = sh64_compact_reg_base_num (reg_nr);
3704 for (portion = 0; portion < 2; portion++)
3706 /* We must pay attention to the endiannes. */
3707 sh_sh64_register_convert_to_raw (REGISTER_VIRTUAL_TYPE (reg_nr), reg_nr,
3708 buffer, temp_buffer);
3710 regcache_raw_write (regcache, base_regnum + portion,
3712 + REGISTER_RAW_SIZE (base_regnum) * portion));
3716 else if (reg_nr >= tdep->FV0_C_REGNUM
3717 && reg_nr <= tdep->FV_LAST_C_REGNUM)
3719 base_regnum = sh64_compact_reg_base_num (reg_nr);
3721 for (portion = 0; portion < 4; portion++)
3723 regcache_raw_write (regcache, base_regnum + portion,
3725 + REGISTER_RAW_SIZE (base_regnum) * portion));
3729 else if (reg_nr == tdep->FPSCR_C_REGNUM)
3731 int fpscr_base_regnum;
3733 unsigned int fpscr_value;
3734 unsigned int sr_value;
3735 unsigned int old_fpscr_value;
3736 unsigned int old_sr_value;
3737 unsigned int fpscr_c_value;
3738 unsigned int fpscr_mask;
3739 unsigned int sr_mask;
3741 fpscr_base_regnum = tdep->FPSCR_REGNUM;
3742 sr_base_regnum = tdep->SR_REGNUM;
3744 /* FPSCR_C is a very weird register that contains sparse bits
3745 from the FPSCR and the SR architectural registers.
3752 2-17 Bit 2-18 of FPSCR
3753 18-20 Bits 12,13,14 of SR
3757 /* Get value as an int. */
3758 fpscr_c_value = extract_unsigned_integer (buffer, 4);
3760 /* Build the new values. */
3761 fpscr_mask = 0x0003fffd;
3762 sr_mask = 0x001c0000;
3764 fpscr_value = fpscr_c_value & fpscr_mask;
3765 sr_value = (fpscr_value & sr_mask) >> 6;
3767 regcache_raw_read (regcache, fpscr_base_regnum, temp_buffer);
3768 old_fpscr_value = extract_unsigned_integer (temp_buffer, 4);
3769 old_fpscr_value &= 0xfffc0002;
3770 fpscr_value |= old_fpscr_value;
3771 store_unsigned_integer (temp_buffer, 4, fpscr_value);
3772 regcache_raw_write (regcache, fpscr_base_regnum, temp_buffer);
3774 regcache_raw_read (regcache, sr_base_regnum, temp_buffer);
3775 old_sr_value = extract_unsigned_integer (temp_buffer, 4);
3776 old_sr_value &= 0xffff8fff;
3777 sr_value |= old_sr_value;
3778 store_unsigned_integer (temp_buffer, 4, sr_value);
3779 regcache_raw_write (regcache, sr_base_regnum, temp_buffer);
3782 else if (reg_nr == tdep->FPUL_C_REGNUM)
3784 base_regnum = sh64_compact_reg_base_num (reg_nr);
3785 regcache_raw_write (regcache, base_regnum, buffer);
3789 /* Floating point vector of 4 float registers. */
3791 do_fv_register_info (int fv_regnum)
3793 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
3794 printf_filtered ("fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3795 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_REGNUM,
3796 (int) read_register (first_fp_reg_num),
3797 (int) read_register (first_fp_reg_num + 1),
3798 (int) read_register (first_fp_reg_num + 2),
3799 (int) read_register (first_fp_reg_num + 3));
3802 /* Floating point vector of 4 float registers, compact mode. */
3804 do_fv_c_register_info (int fv_regnum)
3806 int first_fp_reg_num = sh64_compact_reg_base_num (fv_regnum);
3807 printf_filtered ("fv%d_c\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
3808 fv_regnum - gdbarch_tdep (current_gdbarch)->FV0_C_REGNUM,
3809 (int) read_register (first_fp_reg_num),
3810 (int) read_register (first_fp_reg_num + 1),
3811 (int) read_register (first_fp_reg_num + 2),
3812 (int) read_register (first_fp_reg_num + 3));
3815 /* Pairs of single regs. The DR are instead double precision
3818 do_fpp_register_info (int fpp_regnum)
3820 int first_fp_reg_num = fpp_reg_base_num (fpp_regnum);
3822 printf_filtered ("fpp%d\t0x%08x\t0x%08x\n",
3823 fpp_regnum - gdbarch_tdep (current_gdbarch)->FPP0_REGNUM,
3824 (int) read_register (first_fp_reg_num),
3825 (int) read_register (first_fp_reg_num + 1));
3828 /* Double precision registers. */
3830 do_dr_register_info (int dr_regnum)
3832 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
3834 printf_filtered ("dr%d\t0x%08x%08x\n",
3835 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_REGNUM,
3836 (int) read_register (first_fp_reg_num),
3837 (int) read_register (first_fp_reg_num + 1));
3840 /* Double precision registers, compact mode. */
3842 do_dr_c_register_info (int dr_regnum)
3844 int first_fp_reg_num = sh64_compact_reg_base_num (dr_regnum);
3846 printf_filtered ("dr%d_c\t0x%08x%08x\n",
3847 dr_regnum - gdbarch_tdep (current_gdbarch)->DR0_C_REGNUM,
3848 (int) read_register (first_fp_reg_num),
3849 (int) read_register (first_fp_reg_num +1));
3852 /* General register in compact mode. */
3854 do_r_c_register_info (int r_c_regnum)
3856 int regnum = sh64_compact_reg_base_num (r_c_regnum);
3858 printf_filtered ("r%d_c\t0x%08x\n",
3859 r_c_regnum - gdbarch_tdep (current_gdbarch)->R0_C_REGNUM,
3860 /*FIXME!!!*/ (int) read_register (regnum));
3863 /* FIXME:!! THIS SHOULD TAKE CARE OF GETTING THE RIGHT PORTION OF THE
3864 shmedia REGISTERS. */
3865 /* Control registers, compact mode. */
3867 do_cr_c_register_info (int cr_c_regnum)
3869 switch (cr_c_regnum)
3871 case 237: printf_filtered ("pc_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3873 case 238: printf_filtered ("gbr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3875 case 239: printf_filtered ("mach_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3877 case 240: printf_filtered ("macl_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3879 case 241: printf_filtered ("pr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3881 case 242: printf_filtered ("t_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3883 case 243: printf_filtered ("fpscr_c\t0x%08x\n", (int) read_register (cr_c_regnum));
3885 case 244: printf_filtered ("fpul_c\t0x%08x\n", (int)read_register (cr_c_regnum));
3891 sh_do_pseudo_register (int regnum)
3893 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3895 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
3896 internal_error (__FILE__, __LINE__,
3897 "Invalid pseudo register number %d\n", regnum);
3898 else if (regnum >= tdep->DR0_REGNUM
3899 && regnum < tdep->DR_LAST_REGNUM)
3900 do_dr_register_info (regnum);
3901 else if (regnum >= tdep->FV0_REGNUM
3902 && regnum <= tdep->FV_LAST_REGNUM)
3903 do_fv_register_info (regnum);
3907 sh_do_fp_register (int regnum)
3908 { /* do values for FP (float) regs */
3910 double flt; /* double extracted from raw hex data */
3914 /* Allocate space for the float. */
3915 raw_buffer = (char *) alloca (REGISTER_RAW_SIZE (FP0_REGNUM));
3917 /* Get the data in raw format. */
3918 if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
3919 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
3921 /* Get the register as a number */
3922 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
3924 /* Print the name and some spaces. */
3925 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3926 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
3928 /* Print the value. */
3930 printf_filtered ("<invalid float>");
3932 printf_filtered ("%-10.9g", flt);
3934 /* Print the fp register as hex. */
3935 printf_filtered ("\t(raw 0x");
3936 for (j = 0; j < REGISTER_RAW_SIZE (regnum); j++)
3938 register int idx = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? j
3939 : REGISTER_RAW_SIZE (regnum) - 1 - j;
3940 printf_filtered ("%02x", (unsigned char) raw_buffer[idx]);
3942 printf_filtered (")");
3943 printf_filtered ("\n");
3947 sh64_do_pseudo_register (int regnum)
3949 /* All the sh64-compact mode registers are pseudo registers. */
3950 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3952 if (regnum < NUM_REGS
3953 || regnum >= NUM_REGS + NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT)
3954 internal_error (__FILE__, __LINE__,
3955 "Invalid pseudo register number %d\n", regnum);
3957 else if ((regnum >= tdep->DR0_REGNUM
3958 && regnum <= tdep->DR_LAST_REGNUM))
3959 do_dr_register_info (regnum);
3961 else if ((regnum >= tdep->DR0_C_REGNUM
3962 && regnum <= tdep->DR_LAST_C_REGNUM))
3963 do_dr_c_register_info (regnum);
3965 else if ((regnum >= tdep->FV0_REGNUM
3966 && regnum <= tdep->FV_LAST_REGNUM))
3967 do_fv_register_info (regnum);
3969 else if ((regnum >= tdep->FV0_C_REGNUM
3970 && regnum <= tdep->FV_LAST_C_REGNUM))
3971 do_fv_c_register_info (regnum);
3973 else if (regnum >= tdep->FPP0_REGNUM
3974 && regnum <= tdep->FPP_LAST_REGNUM)
3975 do_fpp_register_info (regnum);
3977 else if (regnum >= tdep->R0_C_REGNUM
3978 && regnum <= tdep->R_LAST_C_REGNUM)
3979 do_r_c_register_info (regnum); /* FIXME, this function will not print the right format */
3981 else if (regnum >= tdep->FP0_C_REGNUM
3982 && regnum <= tdep->FP_LAST_C_REGNUM)
3983 sh_do_fp_register (regnum); /* this should work also for pseudoregs */
3985 else if (regnum >= tdep->PC_C_REGNUM
3986 && regnum <= tdep->FPUL_C_REGNUM)
3987 do_cr_c_register_info (regnum);
3992 sh_do_register (int regnum)
3994 char raw_buffer[MAX_REGISTER_RAW_SIZE];
3996 fputs_filtered (REGISTER_NAME (regnum), gdb_stdout);
3997 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), gdb_stdout);
3999 /* Get the data in raw format. */
4000 if (!frame_register_read (deprecated_selected_frame, regnum, raw_buffer))
4001 printf_filtered ("*value not available*\n");
4003 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4004 gdb_stdout, 'x', 1, 0, Val_pretty_default);
4005 printf_filtered ("\t");
4006 val_print (REGISTER_VIRTUAL_TYPE (regnum), raw_buffer, 0, 0,
4007 gdb_stdout, 0, 1, 0, Val_pretty_default);
4008 printf_filtered ("\n");
4012 sh_print_register (int regnum)
4014 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
4015 internal_error (__FILE__, __LINE__,
4016 "Invalid register number %d\n", regnum);
4018 else if (regnum >= 0 && regnum < NUM_REGS)
4020 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4021 sh_do_fp_register (regnum); /* FP regs */
4023 sh_do_register (regnum); /* All other regs */
4026 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4027 do_pseudo_register (regnum);
4031 sh_do_registers_info (int regnum, int fpregs)
4033 if (regnum != -1) /* do one specified register */
4035 if (*(REGISTER_NAME (regnum)) == '\0')
4036 error ("Not a valid register for the current processor type");
4038 sh_print_register (regnum);
4041 /* do all (or most) registers */
4044 while (regnum < NUM_REGS)
4046 /* If the register name is empty, it is undefined for this
4047 processor, so don't display anything. */
4048 if (REGISTER_NAME (regnum) == NULL
4049 || *(REGISTER_NAME (regnum)) == '\0')
4055 if (TYPE_CODE (REGISTER_VIRTUAL_TYPE (regnum)) == TYPE_CODE_FLT)
4059 /* true for "INFO ALL-REGISTERS" command */
4060 sh_do_fp_register (regnum); /* FP regs */
4064 regnum += (gdbarch_tdep (current_gdbarch)->FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
4068 sh_do_register (regnum); /* All other regs */
4074 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4076 do_pseudo_register (regnum);
4083 sh_compact_do_registers_info (int regnum, int fpregs)
4085 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4086 if (regnum != -1) /* do one specified register */
4088 if (*(REGISTER_NAME (regnum)) == '\0')
4089 error ("Not a valid register for the current processor type");
4091 if (regnum >= 0 && regnum < tdep->R0_C_REGNUM)
4092 error ("Not a valid register for the current processor mode.");
4094 sh_print_register (regnum);
4097 /* do all compact registers */
4099 regnum = tdep->R0_C_REGNUM;
4100 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
4102 do_pseudo_register (regnum);
4109 sh64_do_registers_info (int regnum, int fpregs)
4111 if (pc_is_isa32 (get_frame_pc (deprecated_selected_frame)))
4112 sh_do_registers_info (regnum, fpregs);
4114 sh_compact_do_registers_info (regnum, fpregs);
4117 #ifdef SVR4_SHARED_LIBS
4119 /* Fetch (and possibly build) an appropriate link_map_offsets structure
4120 for native i386 linux targets using the struct offsets defined in
4121 link.h (but without actual reference to that file).
4123 This makes it possible to access i386-linux shared libraries from
4124 a gdb that was not built on an i386-linux host (for cross debugging).
4127 struct link_map_offsets *
4128 sh_linux_svr4_fetch_link_map_offsets (void)
4130 static struct link_map_offsets lmo;
4131 static struct link_map_offsets *lmp = 0;
4137 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
4139 lmo.r_map_offset = 4;
4142 lmo.link_map_size = 20; /* 552 not actual size but all we need */
4144 lmo.l_addr_offset = 0;
4145 lmo.l_addr_size = 4;
4147 lmo.l_name_offset = 4;
4148 lmo.l_name_size = 4;
4150 lmo.l_next_offset = 12;
4151 lmo.l_next_size = 4;
4153 lmo.l_prev_offset = 16;
4154 lmo.l_prev_size = 4;
4159 #endif /* SVR4_SHARED_LIBS */
4164 DSP_DSR_REGNUM = 24,
4176 DSP_MOD_REGNUM = 40,
4181 DSP_R0_BANK_REGNUM = 51,
4182 DSP_R7_BANK_REGNUM = DSP_R0_BANK_REGNUM + 7
4186 sh_dsp_register_sim_regno (int nr)
4188 if (legacy_register_sim_regno (nr) < 0)
4189 return legacy_register_sim_regno (nr);
4190 if (nr >= DSP_DSR_REGNUM && nr < DSP_Y1_REGNUM)
4191 return nr - DSP_DSR_REGNUM + SIM_SH_DSR_REGNUM;
4192 if (nr == DSP_MOD_REGNUM)
4193 return SIM_SH_MOD_REGNUM;
4194 if (nr == DSP_RS_REGNUM)
4195 return SIM_SH_RS_REGNUM;
4196 if (nr == DSP_RE_REGNUM)
4197 return SIM_SH_RE_REGNUM;
4198 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
4199 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
4203 static gdbarch_init_ftype sh_gdbarch_init;
4205 static struct gdbarch *
4206 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
4208 static LONGEST sh_call_dummy_words[] = {0};
4209 struct gdbarch *gdbarch;
4210 struct gdbarch_tdep *tdep;
4211 gdbarch_register_name_ftype *sh_register_name;
4212 gdbarch_deprecated_store_return_value_ftype *sh_store_return_value;
4213 gdbarch_register_virtual_type_ftype *sh_register_virtual_type;
4215 /* If there is already a candidate, use it. */
4216 arches = gdbarch_list_lookup_by_info (arches, &info);
4218 return arches->gdbarch;
4220 /* None found, create a new architecture from the information
4222 tdep = XMALLOC (struct gdbarch_tdep);
4223 gdbarch = gdbarch_alloc (&info, tdep);
4225 /* NOTE: cagney/2002-12-06: This can be deleted when this arch is
4226 ready to unwind the PC first (see frame.c:get_prev_frame()). */
4227 set_gdbarch_deprecated_init_frame_pc (gdbarch, init_frame_pc_default);
4229 /* Initialize the register numbers that are not common to all the
4230 variants to -1, if necessary thse will be overwritten in the case
4232 tdep->FPUL_REGNUM = -1;
4233 tdep->FPSCR_REGNUM = -1;
4234 tdep->PR_REGNUM = 17;
4235 tdep->SR_REGNUM = 22;
4236 tdep->DSR_REGNUM = -1;
4237 tdep->FP_LAST_REGNUM = -1;
4238 tdep->A0G_REGNUM = -1;
4239 tdep->A0_REGNUM = -1;
4240 tdep->A1G_REGNUM = -1;
4241 tdep->A1_REGNUM = -1;
4242 tdep->M0_REGNUM = -1;
4243 tdep->M1_REGNUM = -1;
4244 tdep->X0_REGNUM = -1;
4245 tdep->X1_REGNUM = -1;
4246 tdep->Y0_REGNUM = -1;
4247 tdep->Y1_REGNUM = -1;
4248 tdep->MOD_REGNUM = -1;
4249 tdep->RS_REGNUM = -1;
4250 tdep->RE_REGNUM = -1;
4251 tdep->SSR_REGNUM = -1;
4252 tdep->SPC_REGNUM = -1;
4253 tdep->DR0_REGNUM = -1;
4254 tdep->DR_LAST_REGNUM = -1;
4255 tdep->FV0_REGNUM = -1;
4256 tdep->FV_LAST_REGNUM = -1;
4257 tdep->ARG0_REGNUM = 4;
4258 tdep->ARGLAST_REGNUM = 7;
4259 tdep->RETURN_REGNUM = 0;
4260 tdep->FLOAT_ARGLAST_REGNUM = -1;
4262 tdep->sh_abi = SH_ABI_UNKNOWN;
4264 set_gdbarch_fp0_regnum (gdbarch, -1);
4265 set_gdbarch_num_pseudo_regs (gdbarch, 0);
4266 set_gdbarch_max_register_raw_size (gdbarch, 4);
4267 set_gdbarch_max_register_virtual_size (gdbarch, 4);
4268 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4269 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4270 set_gdbarch_num_regs (gdbarch, SH_DEFAULT_NUM_REGS);
4271 set_gdbarch_sp_regnum (gdbarch, 15);
4272 set_gdbarch_fp_regnum (gdbarch, 14);
4273 set_gdbarch_pc_regnum (gdbarch, 16);
4274 set_gdbarch_register_size (gdbarch, 4);
4275 set_gdbarch_register_bytes (gdbarch, SH_DEFAULT_NUM_REGS * 4);
4276 set_gdbarch_deprecated_do_registers_info (gdbarch, sh_do_registers_info);
4277 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
4278 set_gdbarch_frame_chain (gdbarch, sh_frame_chain);
4279 set_gdbarch_get_saved_register (gdbarch, deprecated_generic_get_saved_register);
4280 set_gdbarch_init_extra_frame_info (gdbarch, sh_init_extra_frame_info);
4281 set_gdbarch_deprecated_extract_return_value (gdbarch, sh_extract_return_value);
4282 set_gdbarch_push_arguments (gdbarch, sh_push_arguments);
4283 set_gdbarch_store_struct_return (gdbarch, sh_store_struct_return);
4284 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
4285 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
4286 set_gdbarch_pop_frame (gdbarch, sh_pop_frame);
4287 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
4288 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
4289 skip_prologue_hard_way = sh_skip_prologue_hard_way;
4290 do_pseudo_register = sh_do_pseudo_register;
4292 switch (info.bfd_arch_info->mach)
4295 sh_register_name = sh_sh_register_name;
4296 sh_show_regs = sh_generic_show_regs;
4297 sh_store_return_value = sh_default_store_return_value;
4298 sh_register_virtual_type = sh_default_register_virtual_type;
4299 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4300 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4301 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4302 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4305 sh_register_name = sh_sh_register_name;
4306 sh_show_regs = sh_generic_show_regs;
4307 sh_store_return_value = sh_default_store_return_value;
4308 sh_register_virtual_type = sh_default_register_virtual_type;
4309 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4310 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4311 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4312 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4314 case bfd_mach_sh_dsp:
4315 sh_register_name = sh_sh_dsp_register_name;
4316 sh_show_regs = sh_dsp_show_regs;
4317 sh_store_return_value = sh_default_store_return_value;
4318 sh_register_virtual_type = sh_default_register_virtual_type;
4319 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4320 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4321 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4322 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4323 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
4324 tdep->DSR_REGNUM = 24;
4325 tdep->A0G_REGNUM = 25;
4326 tdep->A0_REGNUM = 26;
4327 tdep->A1G_REGNUM = 27;
4328 tdep->A1_REGNUM = 28;
4329 tdep->M0_REGNUM = 29;
4330 tdep->M1_REGNUM = 30;
4331 tdep->X0_REGNUM = 31;
4332 tdep->X1_REGNUM = 32;
4333 tdep->Y0_REGNUM = 33;
4334 tdep->Y1_REGNUM = 34;
4335 tdep->MOD_REGNUM = 40;
4336 tdep->RS_REGNUM = 43;
4337 tdep->RE_REGNUM = 44;
4340 sh_register_name = sh_sh3_register_name;
4341 sh_show_regs = sh3_show_regs;
4342 sh_store_return_value = sh_default_store_return_value;
4343 sh_register_virtual_type = sh_default_register_virtual_type;
4344 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4345 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4346 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4347 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4348 tdep->SSR_REGNUM = 41;
4349 tdep->SPC_REGNUM = 42;
4352 sh_register_name = sh_sh3e_register_name;
4353 sh_show_regs = sh3e_show_regs;
4354 sh_store_return_value = sh3e_sh4_store_return_value;
4355 sh_register_virtual_type = sh_sh3e_register_virtual_type;
4356 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4357 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4358 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4359 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4360 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4361 set_gdbarch_fp0_regnum (gdbarch, 25);
4362 tdep->FPUL_REGNUM = 23;
4363 tdep->FPSCR_REGNUM = 24;
4364 tdep->FP_LAST_REGNUM = 40;
4365 tdep->SSR_REGNUM = 41;
4366 tdep->SPC_REGNUM = 42;
4368 case bfd_mach_sh3_dsp:
4369 sh_register_name = sh_sh3_dsp_register_name;
4370 sh_show_regs = sh3_dsp_show_regs;
4371 sh_store_return_value = sh_default_store_return_value;
4372 sh_register_virtual_type = sh_default_register_virtual_type;
4373 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4374 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4375 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4376 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4377 tdep->DSR_REGNUM = 24;
4378 tdep->A0G_REGNUM = 25;
4379 tdep->A0_REGNUM = 26;
4380 tdep->A1G_REGNUM = 27;
4381 tdep->A1_REGNUM = 28;
4382 tdep->M0_REGNUM = 29;
4383 tdep->M1_REGNUM = 30;
4384 tdep->X0_REGNUM = 31;
4385 tdep->X1_REGNUM = 32;
4386 tdep->Y0_REGNUM = 33;
4387 tdep->Y1_REGNUM = 34;
4388 tdep->MOD_REGNUM = 40;
4389 tdep->RS_REGNUM = 43;
4390 tdep->RE_REGNUM = 44;
4391 tdep->SSR_REGNUM = 41;
4392 tdep->SPC_REGNUM = 42;
4395 sh_register_name = sh_sh4_register_name;
4396 sh_show_regs = sh4_show_regs;
4397 sh_store_return_value = sh3e_sh4_store_return_value;
4398 sh_register_virtual_type = sh_sh4_register_virtual_type;
4399 set_gdbarch_frame_init_saved_regs (gdbarch, sh_fp_frame_init_saved_regs);
4400 set_gdbarch_deprecated_extract_return_value (gdbarch, sh3e_sh4_extract_return_value);
4401 set_gdbarch_fp0_regnum (gdbarch, 25);
4402 set_gdbarch_register_raw_size (gdbarch, sh_sh4_register_raw_size);
4403 set_gdbarch_register_virtual_size (gdbarch, sh_sh4_register_raw_size);
4404 set_gdbarch_register_byte (gdbarch, sh_sh4_register_byte);
4405 set_gdbarch_num_pseudo_regs (gdbarch, 12);
4406 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4407 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
4408 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
4409 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
4410 tdep->FPUL_REGNUM = 23;
4411 tdep->FPSCR_REGNUM = 24;
4412 tdep->FP_LAST_REGNUM = 40;
4413 tdep->SSR_REGNUM = 41;
4414 tdep->SPC_REGNUM = 42;
4415 tdep->DR0_REGNUM = 59;
4416 tdep->DR_LAST_REGNUM = 66;
4417 tdep->FV0_REGNUM = 67;
4418 tdep->FV_LAST_REGNUM = 70;
4421 tdep->PR_REGNUM = 18;
4422 tdep->SR_REGNUM = 65;
4423 tdep->FPSCR_REGNUM = SIM_SH64_FPCSR_REGNUM;
4424 tdep->FP_LAST_REGNUM = SIM_SH64_FR0_REGNUM + SIM_SH64_NR_FP_REGS - 1;
4425 tdep->SSR_REGNUM = SIM_SH64_SSR_REGNUM;
4426 tdep->SPC_REGNUM = SIM_SH64_SPC_REGNUM;
4427 tdep->TR7_REGNUM = SIM_SH64_TR0_REGNUM + 7;
4428 tdep->FPP0_REGNUM = 173;
4429 tdep->FPP_LAST_REGNUM = 204;
4430 tdep->DR0_REGNUM = 141;
4431 tdep->DR_LAST_REGNUM = 172;
4432 tdep->FV0_REGNUM = 205;
4433 tdep->FV_LAST_REGNUM = 220;
4434 tdep->R0_C_REGNUM = 221;
4435 tdep->R_LAST_C_REGNUM = 236;
4436 tdep->PC_C_REGNUM = 237;
4437 tdep->GBR_C_REGNUM = 238;
4438 tdep->MACH_C_REGNUM = 239;
4439 tdep->MACL_C_REGNUM = 240;
4440 tdep->PR_C_REGNUM = 241;
4441 tdep->T_C_REGNUM = 242;
4442 tdep->FPSCR_C_REGNUM = 243;
4443 tdep->FPUL_C_REGNUM = 244;
4444 tdep->FP0_C_REGNUM = 245;
4445 tdep->FP_LAST_C_REGNUM = 260;
4446 tdep->DR0_C_REGNUM = 261;
4447 tdep->DR_LAST_C_REGNUM = 268;
4448 tdep->FV0_C_REGNUM = 269;
4449 tdep->FV_LAST_C_REGNUM = 272;
4450 tdep->ARG0_REGNUM = 2;
4451 tdep->ARGLAST_REGNUM = 9;
4452 tdep->RETURN_REGNUM = 2;
4453 tdep->FLOAT_ARGLAST_REGNUM = 11;
4455 set_gdbarch_num_pseudo_regs (gdbarch, NUM_PSEUDO_REGS_SH_MEDIA + NUM_PSEUDO_REGS_SH_COMPACT);
4456 set_gdbarch_fp0_regnum (gdbarch, SIM_SH64_FR0_REGNUM);
4457 set_gdbarch_pc_regnum (gdbarch, 64);
4459 /* Determine the ABI */
4460 if (bfd_get_arch_size (info.abfd) == 64)
4462 /* If the ABI is the 64-bit one, it can only be sh-media. */
4463 tdep->sh_abi = SH_ABI_64;
4464 set_gdbarch_ptr_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4465 set_gdbarch_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4469 /* If the ABI is the 32-bit one it could be either media or
4471 tdep->sh_abi = SH_ABI_32;
4472 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4473 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4476 /* the number of real registers is the same whether we are in
4477 ISA16(compact) or ISA32(media). */
4478 set_gdbarch_num_regs (gdbarch, SIM_SH64_NR_REGS);
4479 set_gdbarch_register_size (gdbarch, 8); /*????*/
4480 set_gdbarch_register_bytes (gdbarch,
4481 ((SIM_SH64_NR_FP_REGS + 1) * 4)
4482 + (SIM_SH64_NR_REGS - SIM_SH64_NR_FP_REGS -1) * 8);
4484 sh_register_name = sh_sh64_register_name;
4485 sh_show_regs = sh64_show_regs;
4486 sh_register_virtual_type = sh_sh64_register_virtual_type;
4487 sh_store_return_value = sh64_store_return_value;
4488 skip_prologue_hard_way = sh64_skip_prologue_hard_way;
4489 do_pseudo_register = sh64_do_pseudo_register;
4490 set_gdbarch_register_raw_size (gdbarch, sh_sh64_register_raw_size);
4491 set_gdbarch_register_virtual_size (gdbarch, sh_sh64_register_raw_size);
4492 set_gdbarch_register_byte (gdbarch, sh_sh64_register_byte);
4493 /* This seems awfully wrong!*/
4494 /*set_gdbarch_max_register_raw_size (gdbarch, 8);*/
4495 /* should include the size of the pseudo regs. */
4496 set_gdbarch_max_register_raw_size (gdbarch, 4 * 4);
4497 /* Or should that go in the virtual_size? */
4498 /*set_gdbarch_max_register_virtual_size (gdbarch, 8);*/
4499 set_gdbarch_max_register_virtual_size (gdbarch, 4 * 4);
4500 set_gdbarch_pseudo_register_read (gdbarch, sh64_pseudo_register_read);
4501 set_gdbarch_pseudo_register_write (gdbarch, sh64_pseudo_register_write);
4503 set_gdbarch_deprecated_do_registers_info (gdbarch, sh64_do_registers_info);
4504 set_gdbarch_frame_init_saved_regs (gdbarch, sh64_nofp_frame_init_saved_regs);
4505 set_gdbarch_breakpoint_from_pc (gdbarch, sh_sh64_breakpoint_from_pc);
4506 set_gdbarch_init_extra_frame_info (gdbarch, sh64_init_extra_frame_info);
4507 set_gdbarch_frame_chain (gdbarch, sh64_frame_chain);
4508 set_gdbarch_get_saved_register (gdbarch, sh64_get_saved_register);
4509 set_gdbarch_deprecated_extract_return_value (gdbarch, sh64_extract_return_value);
4510 set_gdbarch_push_arguments (gdbarch, sh64_push_arguments);
4511 /*set_gdbarch_store_struct_return (gdbarch, sh64_store_struct_return);*/
4512 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh64_extract_struct_value_address);
4513 set_gdbarch_use_struct_convention (gdbarch, sh64_use_struct_convention);
4514 set_gdbarch_pop_frame (gdbarch, sh64_pop_frame);
4515 set_gdbarch_elf_make_msymbol_special (gdbarch,
4516 sh64_elf_make_msymbol_special);
4519 sh_register_name = sh_generic_register_name;
4520 sh_show_regs = sh_generic_show_regs;
4521 sh_store_return_value = sh_default_store_return_value;
4522 sh_register_virtual_type = sh_default_register_virtual_type;
4523 set_gdbarch_frame_init_saved_regs (gdbarch, sh_nofp_frame_init_saved_regs);
4524 set_gdbarch_register_raw_size (gdbarch, sh_default_register_raw_size);
4525 set_gdbarch_register_virtual_size (gdbarch, sh_default_register_raw_size);
4526 set_gdbarch_register_byte (gdbarch, sh_default_register_byte);
4530 set_gdbarch_read_pc (gdbarch, generic_target_read_pc);
4531 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
4532 set_gdbarch_read_fp (gdbarch, generic_target_read_fp);
4533 set_gdbarch_read_sp (gdbarch, generic_target_read_sp);
4534 set_gdbarch_write_sp (gdbarch, generic_target_write_sp);
4536 set_gdbarch_register_name (gdbarch, sh_register_name);
4537 set_gdbarch_register_virtual_type (gdbarch, sh_register_virtual_type);
4539 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4540 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4541 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4542 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4543 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4544 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4546 set_gdbarch_call_dummy_length (gdbarch, 0);
4547 set_gdbarch_call_dummy_address (gdbarch, entry_point_address);
4548 set_gdbarch_call_dummy_breakpoint_offset_p (gdbarch, 1); /*???*/
4549 set_gdbarch_call_dummy_breakpoint_offset (gdbarch, 0);
4550 set_gdbarch_call_dummy_start_offset (gdbarch, 0);
4551 set_gdbarch_call_dummy_words (gdbarch, sh_call_dummy_words);
4552 set_gdbarch_sizeof_call_dummy_words (gdbarch, sizeof (sh_call_dummy_words));
4553 set_gdbarch_call_dummy_p (gdbarch, 1);
4554 set_gdbarch_call_dummy_stack_adjust_p (gdbarch, 0);
4555 set_gdbarch_fix_call_dummy (gdbarch, generic_fix_call_dummy);
4557 set_gdbarch_push_dummy_frame (gdbarch, generic_push_dummy_frame);
4558 set_gdbarch_push_return_address (gdbarch, sh_push_return_address);
4560 set_gdbarch_deprecated_store_return_value (gdbarch, sh_store_return_value);
4561 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
4562 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4563 set_gdbarch_decr_pc_after_break (gdbarch, 0);
4564 set_gdbarch_function_start_offset (gdbarch, 0);
4566 set_gdbarch_frame_args_skip (gdbarch, 0);
4567 set_gdbarch_frameless_function_invocation (gdbarch, frameless_look_for_prologue);
4568 set_gdbarch_frame_chain_valid (gdbarch, generic_file_frame_chain_valid);
4569 set_gdbarch_frame_saved_pc (gdbarch, sh_frame_saved_pc);
4570 set_gdbarch_saved_pc_after_call (gdbarch, sh_saved_pc_after_call);
4571 set_gdbarch_frame_num_args (gdbarch, frame_num_args_unknown);
4572 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
4574 /* Hook in ABI-specific overrides, if they have been registered. */
4575 gdbarch_init_osabi (info, gdbarch);
4581 sh_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
4583 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
4588 /* FIXME: dump the rest of gdbarch_tdep. */
4592 _initialize_sh_tdep (void)
4594 struct cmd_list_element *c;
4596 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, sh_dump_tdep);
4598 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");