1 /* Target-dependent code for Renesas Super-H, for GDB.
2 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
3 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
23 Contributed by Steve Chamberlain
29 #include "frame-base.h"
30 #include "frame-unwind.h"
31 #include "dwarf2-frame.h"
39 #include "gdb_string.h"
40 #include "gdb_assert.h"
41 #include "arch-utils.h"
42 #include "floatformat.h"
50 #include "solib-svr4.h"
54 /* registers numbers shared with the simulator */
55 #include "gdb/sim-sh.h"
57 static void (*sh_show_regs) (void);
59 #define SH_NUM_REGS 59
68 /* Flag showing that a frame has been created in the prologue code. */
71 /* Saved registers. */
72 CORE_ADDR saved_regs[SH_NUM_REGS];
77 sh_sh_register_name (int reg_nr)
79 static char *register_names[] = {
80 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
81 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
82 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
84 "", "", "", "", "", "", "", "",
85 "", "", "", "", "", "", "", "",
87 "", "", "", "", "", "", "", "",
88 "", "", "", "", "", "", "", "",
92 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
94 return register_names[reg_nr];
98 sh_sh3_register_name (int reg_nr)
100 static char *register_names[] = {
101 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
102 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
103 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
105 "", "", "", "", "", "", "", "",
106 "", "", "", "", "", "", "", "",
108 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
109 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1"
113 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
115 return register_names[reg_nr];
119 sh_sh3e_register_name (int reg_nr)
121 static char *register_names[] = {
122 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
123 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
124 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
126 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
127 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
129 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
130 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
134 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
136 return register_names[reg_nr];
140 sh_sh2e_register_name (int reg_nr)
142 static char *register_names[] = {
143 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
144 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
145 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
147 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
148 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
150 "", "", "", "", "", "", "", "",
151 "", "", "", "", "", "", "", "",
155 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
157 return register_names[reg_nr];
161 sh_sh_dsp_register_name (int reg_nr)
163 static char *register_names[] = {
164 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
165 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
166 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
168 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
169 "y0", "y1", "", "", "", "", "", "mod",
171 "rs", "re", "", "", "", "", "", "",
172 "", "", "", "", "", "", "", "",
176 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
178 return register_names[reg_nr];
182 sh_sh3_dsp_register_name (int reg_nr)
184 static char *register_names[] = {
185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
187 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
189 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
190 "y0", "y1", "", "", "", "", "", "mod",
192 "rs", "re", "", "", "", "", "", "",
193 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
194 "", "", "", "", "", "", "", "",
198 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
200 return register_names[reg_nr];
204 sh_sh4_register_name (int reg_nr)
206 static char *register_names[] = {
207 /* general registers 0-15 */
208 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
209 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
211 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
214 /* floating point registers 25 - 40 */
215 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
216 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
220 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
222 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
223 /* double precision (pseudo) 59 - 66 */
224 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14",
225 /* vectors (pseudo) 67 - 70 */
226 "fv0", "fv4", "fv8", "fv12",
227 /* FIXME: missing XF 71 - 86 */
228 /* FIXME: missing XD 87 - 94 */
232 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
234 return register_names[reg_nr];
238 sh_sh4_nofpu_register_name (int reg_nr)
240 static char *register_names[] = {
241 /* general registers 0-15 */
242 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
243 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
245 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
248 /* floating point registers 25 - 40 -- not for nofpu target */
249 "", "", "", "", "", "", "", "",
250 "", "", "", "", "", "", "", "",
254 "r0b0", "r1b0", "r2b0", "r3b0", "r4b0", "r5b0", "r6b0", "r7b0",
256 "r0b1", "r1b1", "r2b1", "r3b1", "r4b1", "r5b1", "r6b1", "r7b1",
257 /* double precision (pseudo) 59 - 66 -- not for nofpu target */
258 "", "", "", "", "", "", "", "",
259 /* vectors (pseudo) 67 - 70 -- not for nofpu target */
264 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
266 return register_names[reg_nr];
270 sh_sh4al_dsp_register_name (int reg_nr)
272 static char *register_names[] = {
273 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
274 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
275 "pc", "pr", "gbr", "vbr", "mach", "macl", "sr",
277 "a0g", "a0", "a1g", "a1", "m0", "m1", "x0", "x1",
278 "y0", "y1", "", "", "", "", "", "mod",
280 "rs", "re", "", "", "", "", "", "",
281 "r0b", "r1b", "r2b", "r3b", "r4b", "r5b", "r6b", "r7b",
282 "", "", "", "", "", "", "", "",
286 if (reg_nr >= (sizeof (register_names) / sizeof (*register_names)))
288 return register_names[reg_nr];
291 static const unsigned char *
292 sh_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr)
294 /* 0xc3c3 is trapa #c3, and it works in big and little endian modes */
295 static unsigned char breakpoint[] = { 0xc3, 0xc3 };
297 *lenptr = sizeof (breakpoint);
301 /* Prologue looks like
305 sub <room_for_loca_vars>,r15
308 Actually it can be more complicated than this but that's it, basically.
311 #define GET_SOURCE_REG(x) (((x) >> 4) & 0xf)
312 #define GET_TARGET_REG(x) (((x) >> 8) & 0xf)
314 /* JSR @Rm 0100mmmm00001011 */
315 #define IS_JSR(x) (((x) & 0xf0ff) == 0x400b)
317 /* STS.L PR,@-r15 0100111100100010
318 r15-4-->r15, PR-->(r15) */
319 #define IS_STS(x) ((x) == 0x4f22)
321 /* MOV.L Rm,@-r15 00101111mmmm0110
322 r15-4-->r15, Rm-->(R15) */
323 #define IS_PUSH(x) (((x) & 0xff0f) == 0x2f06)
325 /* MOV r15,r14 0110111011110011
327 #define IS_MOV_SP_FP(x) ((x) == 0x6ef3)
329 /* ADD #imm,r15 01111111iiiiiiii
331 #define IS_ADD_IMM_SP(x) (((x) & 0xff00) == 0x7f00)
333 #define IS_MOV_R3(x) (((x) & 0xff00) == 0x1a00)
334 #define IS_SHLL_R3(x) ((x) == 0x4300)
336 /* ADD r3,r15 0011111100111100
338 #define IS_ADD_R3SP(x) ((x) == 0x3f3c)
340 /* FMOV.S FRm,@-Rn Rn-4-->Rn, FRm-->(Rn) 1111nnnnmmmm1011
341 FMOV DRm,@-Rn Rn-8-->Rn, DRm-->(Rn) 1111nnnnmmm01011
342 FMOV XDm,@-Rn Rn-8-->Rn, XDm-->(Rn) 1111nnnnmmm11011 */
343 /* CV, 2003-08-28: Only suitable with Rn == SP, therefore name changed to
344 make this entirely clear. */
345 /* #define IS_FMOV(x) (((x) & 0xf00f) == 0xf00b) */
346 #define IS_FPUSH(x) (((x) & 0xff0f) == 0xff0b)
348 /* MOV Rm,Rn Rm-->Rn 0110nnnnmmmm0011 4 <= m <= 7 */
349 #define IS_MOV_ARG_TO_REG(x) \
350 (((x) & 0xf00f) == 0x6003 && \
351 ((x) & 0x00f0) >= 0x0040 && \
352 ((x) & 0x00f0) <= 0x0070)
353 /* MOV.L Rm,@Rn 0010nnnnmmmm0010 n = 14, 4 <= m <= 7 */
354 #define IS_MOV_ARG_TO_IND_R14(x) \
355 (((x) & 0xff0f) == 0x2e02 && \
356 ((x) & 0x00f0) >= 0x0040 && \
357 ((x) & 0x00f0) <= 0x0070)
358 /* MOV.L Rm,@(disp*4,Rn) 00011110mmmmdddd n = 14, 4 <= m <= 7 */
359 #define IS_MOV_ARG_TO_IND_R14_WITH_DISP(x) \
360 (((x) & 0xff00) == 0x1e00 && \
361 ((x) & 0x00f0) >= 0x0040 && \
362 ((x) & 0x00f0) <= 0x0070)
364 /* MOV.W @(disp*2,PC),Rn 1001nnnndddddddd */
365 #define IS_MOVW_PCREL_TO_REG(x) (((x) & 0xf000) == 0x9000)
366 /* MOV.L @(disp*4,PC),Rn 1101nnnndddddddd */
367 #define IS_MOVL_PCREL_TO_REG(x) (((x) & 0xf000) == 0xd000)
368 /* SUB Rn,R15 00111111nnnn1000 */
369 #define IS_SUB_REG_FROM_SP(x) (((x) & 0xff0f) == 0x3f08)
371 #define FPSCR_SZ (1 << 20)
373 /* The following instructions are used for epilogue testing. */
374 #define IS_RESTORE_FP(x) ((x) == 0x6ef6)
375 #define IS_RTS(x) ((x) == 0x000b)
376 #define IS_LDS(x) ((x) == 0x4f26)
377 #define IS_MOV_FP_SP(x) ((x) == 0x6fe3)
378 #define IS_ADD_REG_TO_FP(x) (((x) & 0xff0f) == 0x3e0c)
379 #define IS_ADD_IMM_FP(x) (((x) & 0xff00) == 0x7e00)
381 /* Disassemble an instruction. */
383 gdb_print_insn_sh (bfd_vma memaddr, disassemble_info * info)
385 info->endian = TARGET_BYTE_ORDER;
386 return print_insn_sh (memaddr, info);
390 sh_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc,
391 struct sh_frame_cache *cache)
398 int reg, sav_reg = -1;
400 if (pc >= current_pc)
404 for (opc = pc + (2 * 28); pc < opc; pc += 2)
406 inst = read_memory_unsigned_integer (pc, 2);
407 /* See where the registers will be saved to */
410 cache->saved_regs[GET_SOURCE_REG (inst)] = cache->sp_offset;
411 cache->sp_offset += 4;
413 else if (IS_STS (inst))
415 cache->saved_regs[PR_REGNUM] = cache->sp_offset;
416 cache->sp_offset += 4;
418 else if (IS_MOV_R3 (inst))
420 r3_val = ((inst & 0xff) ^ 0x80) - 0x80;
422 else if (IS_SHLL_R3 (inst))
426 else if (IS_ADD_R3SP (inst))
428 cache->sp_offset += -r3_val;
430 else if (IS_ADD_IMM_SP (inst))
432 offset = ((inst & 0xff) ^ 0x80) - 0x80;
433 cache->sp_offset -= offset;
435 else if (IS_MOVW_PCREL_TO_REG (inst))
439 reg = GET_TARGET_REG (inst);
443 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
445 read_memory_integer (((pc + 4) & ~3) + offset, 2);
449 else if (IS_MOVL_PCREL_TO_REG (inst))
453 reg = (inst & 0x0f00) >> 8;
457 offset = (((inst & 0xff) ^ 0x80) - 0x80) << 1;
459 read_memory_integer (((pc + 4) & ~3) + offset, 4);
463 else if (IS_SUB_REG_FROM_SP (inst))
465 reg = GET_SOURCE_REG (inst);
466 if (sav_reg > 0 && reg == sav_reg)
470 cache->sp_offset += sav_offset;
472 else if (IS_FPUSH (inst))
474 if (read_register (FPSCR_REGNUM) & FPSCR_SZ)
476 cache->sp_offset += 8;
480 cache->sp_offset += 4;
483 else if (IS_MOV_SP_FP (inst))
487 /* At this point, only allow argument register moves to other
488 registers or argument register moves to @(X,fp) which are
489 moving the register arguments onto the stack area allocated
490 by a former add somenumber to SP call. Don't allow moving
491 to an fp indirect address above fp + cache->sp_offset. */
493 for (opc = pc + 12; pc < opc; pc += 2)
495 inst = read_memory_integer (pc, 2);
496 if (IS_MOV_ARG_TO_IND_R14 (inst))
498 reg = GET_SOURCE_REG (inst);
499 if (cache->sp_offset > 0)
500 cache->saved_regs[reg] = cache->sp_offset;
502 else if (IS_MOV_ARG_TO_IND_R14_WITH_DISP (inst))
504 reg = GET_SOURCE_REG (inst);
505 offset = (inst & 0xf) * 4;
506 if (cache->sp_offset > offset)
507 cache->saved_regs[reg] = cache->sp_offset - offset;
509 else if (IS_MOV_ARG_TO_REG (inst))
516 else if (IS_JSR (inst))
518 /* We have found a jsr that has been scheduled into the prologue.
519 If we continue the scan and return a pc someplace after this,
520 then setting a breakpoint on this function will cause it to
521 appear to be called after the function it is calling via the
522 jsr, which will be very confusing. Most likely the next
523 instruction is going to be IS_MOV_SP_FP in the delay slot. If
524 so, note that before returning the current pc. */
525 inst = read_memory_integer (pc + 2, 2);
526 if (IS_MOV_SP_FP (inst))
530 #if 0 /* This used to just stop when it found an instruction that
531 was not considered part of the prologue. Now, we just
532 keep going looking for likely instructions. */
541 /* Skip any prologue before the guts of a function */
543 /* Skip the prologue using the debug information. If this fails we'll
544 fall back on the 'guess' method below. */
546 after_prologue (CORE_ADDR pc)
548 struct symtab_and_line sal;
549 CORE_ADDR func_addr, func_end;
551 /* If we can not find the symbol in the partial symbol table, then
552 there is no hope we can determine the function's start address
554 if (!find_pc_partial_function (pc, NULL, &func_addr, &func_end))
557 /* Get the line associated with FUNC_ADDR. */
558 sal = find_pc_line (func_addr, 0);
560 /* There are only two cases to consider. First, the end of the source line
561 is within the function bounds. In that case we return the end of the
562 source line. Second is the end of the source line extends beyond the
563 bounds of the current function. We need to use the slow code to
564 examine instructions in that case. */
565 if (sal.end < func_end)
572 sh_skip_prologue (CORE_ADDR start_pc)
575 struct sh_frame_cache cache;
577 /* See if we can determine the end of the prologue via the symbol table.
578 If so, then return either PC, or the PC after the prologue, whichever
580 pc = after_prologue (start_pc);
582 /* If after_prologue returned a useful address, then use it. Else
583 fall back on the instruction skipping code. */
585 return max (pc, start_pc);
587 cache.sp_offset = -4;
588 pc = sh_analyze_prologue (start_pc, (CORE_ADDR) -1, &cache);
597 Aggregate types not bigger than 8 bytes that have the same size and
598 alignment as one of the integer scalar types are returned in the
599 same registers as the integer type they match.
601 For example, a 2-byte aligned structure with size 2 bytes has the
602 same size and alignment as a short int, and will be returned in R0.
603 A 4-byte aligned structure with size 8 bytes has the same size and
604 alignment as a long long int, and will be returned in R0 and R1.
606 When an aggregate type is returned in R0 and R1, R0 contains the
607 first four bytes of the aggregate, and R1 contains the
608 remainder. If the size of the aggregate type is not a multiple of 4
609 bytes, the aggregate is tail-padded up to a multiple of 4
610 bytes. The value of the padding is undefined. For little-endian
611 targets the padding will appear at the most significant end of the
612 last element, for big-endian targets the padding appears at the
613 least significant end of the last element.
615 All other aggregate types are returned by address. The caller
616 function passes the address of an area large enough to hold the
617 aggregate value in R2. The called function stores the result in
620 To reiterate, structs smaller than 8 bytes could also be returned
621 in memory, if they don't pass the "same size and alignment as an
626 struct s { char c[3]; } wibble;
627 struct s foo(void) { return wibble; }
629 the return value from foo() will be in memory, not
630 in R0, because there is no 3-byte integer type.
634 struct s { char c[2]; } wibble;
635 struct s foo(void) { return wibble; }
637 because a struct containing two chars has alignment 1, that matches
638 type char, but size 2, that matches type short. There's no integer
639 type that has alignment 1 and size 2, so the struct is returned in
645 sh_use_struct_convention (int gcc_p, struct type *type)
647 int len = TYPE_LENGTH (type);
648 int nelem = TYPE_NFIELDS (type);
650 /* Non-power of 2 length types and types bigger than 8 bytes (which don't
651 fit in two registers anyway) use struct convention. */
652 if (len != 1 && len != 2 && len != 4 && len != 8)
655 /* Scalar types and aggregate types with exactly one field are aligned
656 by definition. They are returned in registers. */
660 /* If the first field in the aggregate has the same length as the entire
661 aggregate type, the type is returned in registers. */
662 if (TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == len)
665 /* If the size of the aggregate is 8 bytes and the first field is
666 of size 4 bytes its alignment is equal to long long's alignment,
667 so it's returned in registers. */
668 if (len == 8 && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
671 /* Otherwise use struct convention. */
675 /* Extract from an array REGBUF containing the (raw) register state
676 the address in which a function should return its structure value,
677 as a CORE_ADDR (or an expression that can be used as one). */
679 sh_extract_struct_value_address (struct regcache *regcache)
683 regcache_cooked_read_unsigned (regcache, STRUCT_RETURN_REGNUM, &addr);
688 sh_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
693 /* Function: push_dummy_call (formerly push_arguments)
694 Setup the function arguments for calling a function in the inferior.
696 On the Renesas SH architecture, there are four registers (R4 to R7)
697 which are dedicated for passing function arguments. Up to the first
698 four arguments (depending on size) may go into these registers.
699 The rest go on the stack.
701 MVS: Except on SH variants that have floating point registers.
702 In that case, float and double arguments are passed in the same
703 manner, but using FP registers instead of GP registers.
705 Arguments that are smaller than 4 bytes will still take up a whole
706 register or a whole 32-bit word on the stack, and will be
707 right-justified in the register or the stack word. This includes
708 chars, shorts, and small aggregate types.
710 Arguments that are larger than 4 bytes may be split between two or
711 more registers. If there are not enough registers free, an argument
712 may be passed partly in a register (or registers), and partly on the
713 stack. This includes doubles, long longs, and larger aggregates.
714 As far as I know, there is no upper limit to the size of aggregates
715 that will be passed in this way; in other words, the convention of
716 passing a pointer to a large aggregate instead of a copy is not used.
718 MVS: The above appears to be true for the SH variants that do not
719 have an FPU, however those that have an FPU appear to copy the
720 aggregate argument onto the stack (and not place it in registers)
721 if it is larger than 16 bytes (four GP registers).
723 An exceptional case exists for struct arguments (and possibly other
724 aggregates such as arrays) if the size is larger than 4 bytes but
725 not a multiple of 4 bytes. In this case the argument is never split
726 between the registers and the stack, but instead is copied in its
727 entirety onto the stack, AND also copied into as many registers as
728 there is room for. In other words, space in registers permitting,
729 two copies of the same argument are passed in. As far as I can tell,
730 only the one on the stack is used, although that may be a function
731 of the level of compiler optimization. I suspect this is a compiler
732 bug. Arguments of these odd sizes are left-justified within the
733 word (as opposed to arguments smaller than 4 bytes, which are
736 If the function is to return an aggregate type such as a struct, it
737 is either returned in the normal return value register R0 (if its
738 size is no greater than one byte), or else the caller must allocate
739 space into which the callee will copy the return value (if the size
740 is greater than one byte). In this case, a pointer to the return
741 value location is passed into the callee in register R2, which does
742 not displace any of the other arguments passed in via registers R4
745 /* Helper function to justify value in register according to endianess. */
747 sh_justify_value_in_reg (struct value *val, int len)
749 static char valbuf[4];
751 memset (valbuf, 0, sizeof (valbuf));
754 /* value gets right-justified in the register or stack word */
755 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
756 memcpy (valbuf + (4 - len), (char *) VALUE_CONTENTS (val), len);
758 memcpy (valbuf, (char *) VALUE_CONTENTS (val), len);
761 return (char *) VALUE_CONTENTS (val);
764 /* Helper function to eval number of bytes to allocate on stack. */
766 sh_stack_allocsize (int nargs, struct value **args)
770 stack_alloc += ((TYPE_LENGTH (VALUE_TYPE (args[nargs])) + 3) & ~3);
774 /* Helper functions for getting the float arguments right. Registers usage
775 depends on the ABI and the endianess. The comments should enlighten how
776 it's intended to work. */
778 /* This array stores which of the float arg registers are already in use. */
779 static int flt_argreg_array[FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM + 1];
781 /* This function just resets the above array to "no reg used so far". */
783 sh_init_flt_argreg (void)
785 memset (flt_argreg_array, 0, sizeof flt_argreg_array);
788 /* This function returns the next register to use for float arg passing.
789 It returns either a valid value between FLOAT_ARG0_REGNUM and
790 FLOAT_ARGLAST_REGNUM if a register is available, otherwise it returns
791 FLOAT_ARGLAST_REGNUM + 1 to indicate that no register is available.
793 Note that register number 0 in flt_argreg_array corresponds with the
794 real float register fr4. In contrast to FLOAT_ARG0_REGNUM (value is
795 29) the parity of the register number is preserved, which is important
796 for the double register passing test (see the "argreg & 1" test below). */
798 sh_next_flt_argreg (int len)
802 /* First search for the next free register. */
803 for (argreg = 0; argreg <= FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM;
805 if (!flt_argreg_array[argreg])
808 /* No register left? */
809 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
810 return FLOAT_ARGLAST_REGNUM + 1;
814 /* Doubles are always starting in a even register number. */
817 flt_argreg_array[argreg] = 1;
821 /* No register left? */
822 if (argreg > FLOAT_ARGLAST_REGNUM - FLOAT_ARG0_REGNUM)
823 return FLOAT_ARGLAST_REGNUM + 1;
825 /* Also mark the next register as used. */
826 flt_argreg_array[argreg + 1] = 1;
828 else if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
830 /* In little endian, gcc passes floats like this: f5, f4, f7, f6, ... */
831 if (!flt_argreg_array[argreg + 1])
834 flt_argreg_array[argreg] = 1;
835 return FLOAT_ARG0_REGNUM + argreg;
838 /* Helper function which figures out, if a type is treated like a float type.
840 The FPU ABIs have a special way how to treat types as float types.
841 Structures with exactly one member, which is of type float or double, are
842 treated exactly as the base types float or double:
852 are handled the same way as just
858 As a result, arguments of these struct types are pushed into floating point
859 registers exactly as floats or doubles, using the same decision algorithm.
861 The same is valid if these types are used as function return types. The
862 above structs are returned in fr0 resp. fr0,fr1 instead of in r0, r0,r1
863 or even using struct convention as it is for other structs. */
866 sh_treat_as_flt_p (struct type *type)
868 int len = TYPE_LENGTH (type);
870 /* Ordinary float types are obviously treated as float. */
871 if (TYPE_CODE (type) == TYPE_CODE_FLT)
873 /* Otherwise non-struct types are not treated as float. */
874 if (TYPE_CODE (type) != TYPE_CODE_STRUCT)
876 /* Otherwise structs with more than one memeber are not treated as float. */
877 if (TYPE_NFIELDS (type) != 1)
879 /* Otherwise if the type of that member is float, the whole type is
881 if (TYPE_CODE (TYPE_FIELD_TYPE (type, 0)) == TYPE_CODE_FLT)
883 /* Otherwise it's not treated as float. */
888 sh_push_dummy_call_fpu (struct gdbarch *gdbarch,
890 struct regcache *regcache,
891 CORE_ADDR bp_addr, int nargs,
893 CORE_ADDR sp, int struct_return,
894 CORE_ADDR struct_addr)
896 int stack_offset = 0;
897 int argreg = ARG0_REGNUM;
903 int len, reg_size = 0;
904 int pass_on_stack = 0;
907 /* first force sp to a 4-byte alignment */
908 sp = sh_frame_align (gdbarch, sp);
911 regcache_cooked_write_unsigned (regcache,
912 STRUCT_RETURN_REGNUM, struct_addr);
914 /* make room on stack for args */
915 sp -= sh_stack_allocsize (nargs, args);
917 /* Initialize float argument mechanism. */
918 sh_init_flt_argreg ();
920 /* Now load as many as possible of the first arguments into
921 registers, and push the rest onto the stack. There are 16 bytes
922 in four registers available. Loop thru args from first to last. */
923 for (argnum = 0; argnum < nargs; argnum++)
925 type = VALUE_TYPE (args[argnum]);
926 len = TYPE_LENGTH (type);
927 val = sh_justify_value_in_reg (args[argnum], len);
929 /* Some decisions have to be made how various types are handled.
930 This also differs in different ABIs. */
933 /* Find out the next register to use for a floating point value. */
934 treat_as_flt = sh_treat_as_flt_p (type);
936 flt_argreg = sh_next_flt_argreg (len);
937 /* In contrast to non-FPU CPUs, arguments are never split between
938 registers and stack. If an argument doesn't fit in the remaining
939 registers it's always pushed entirely on the stack. */
940 else if (len > ((ARGLAST_REGNUM - argreg + 1) * 4))
945 if ((treat_as_flt && flt_argreg > FLOAT_ARGLAST_REGNUM)
946 || (!treat_as_flt && (argreg > ARGLAST_REGNUM
949 /* The data goes entirely on the stack, 4-byte aligned. */
950 reg_size = (len + 3) & ~3;
951 write_memory (sp + stack_offset, val, reg_size);
952 stack_offset += reg_size;
954 else if (treat_as_flt && flt_argreg <= FLOAT_ARGLAST_REGNUM)
956 /* Argument goes in a float argument register. */
957 reg_size = register_size (gdbarch, flt_argreg);
958 regval = extract_unsigned_integer (val, reg_size);
959 /* In little endian mode, float types taking two registers
960 (doubles on sh4, long doubles on sh2e, sh3e and sh4) must
961 be stored swapped in the argument registers. The below
962 code first writes the first 32 bits in the next but one
963 register, increments the val and len values accordingly
964 and then proceeds as normal by writing the second 32 bits
965 into the next register. */
966 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE
967 && TYPE_LENGTH (type) == 2 * reg_size)
969 regcache_cooked_write_unsigned (regcache, flt_argreg + 1,
973 regval = extract_unsigned_integer (val, reg_size);
975 regcache_cooked_write_unsigned (regcache, flt_argreg++, regval);
977 else if (!treat_as_flt && argreg <= ARGLAST_REGNUM)
979 /* there's room in a register */
980 reg_size = register_size (gdbarch, argreg);
981 regval = extract_unsigned_integer (val, reg_size);
982 regcache_cooked_write_unsigned (regcache, argreg++, regval);
984 /* Store the value one register at a time or in one step on stack. */
990 /* Store return address. */
991 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
993 /* Update stack pointer. */
994 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1000 sh_push_dummy_call_nofpu (struct gdbarch *gdbarch,
1001 CORE_ADDR func_addr,
1002 struct regcache *regcache,
1004 int nargs, struct value **args,
1005 CORE_ADDR sp, int struct_return,
1006 CORE_ADDR struct_addr)
1008 int stack_offset = 0;
1009 int argreg = ARG0_REGNUM;
1016 /* first force sp to a 4-byte alignment */
1017 sp = sh_frame_align (gdbarch, sp);
1020 regcache_cooked_write_unsigned (regcache,
1021 STRUCT_RETURN_REGNUM, struct_addr);
1023 /* make room on stack for args */
1024 sp -= sh_stack_allocsize (nargs, args);
1026 /* Now load as many as possible of the first arguments into
1027 registers, and push the rest onto the stack. There are 16 bytes
1028 in four registers available. Loop thru args from first to last. */
1029 for (argnum = 0; argnum < nargs; argnum++)
1031 type = VALUE_TYPE (args[argnum]);
1032 len = TYPE_LENGTH (type);
1033 val = sh_justify_value_in_reg (args[argnum], len);
1037 if (argreg > ARGLAST_REGNUM)
1039 /* The remainder of the data goes entirely on the stack,
1041 reg_size = (len + 3) & ~3;
1042 write_memory (sp + stack_offset, val, reg_size);
1043 stack_offset += reg_size;
1045 else if (argreg <= ARGLAST_REGNUM)
1047 /* there's room in a register */
1048 reg_size = register_size (gdbarch, argreg);
1049 regval = extract_unsigned_integer (val, reg_size);
1050 regcache_cooked_write_unsigned (regcache, argreg++, regval);
1052 /* Store the value reg_size bytes at a time. This means that things
1053 larger than reg_size bytes may go partly in registers and partly
1060 /* Store return address. */
1061 regcache_cooked_write_unsigned (regcache, PR_REGNUM, bp_addr);
1063 /* Update stack pointer. */
1064 regcache_cooked_write_unsigned (regcache, SP_REGNUM, sp);
1069 /* Find a function's return value in the appropriate registers (in
1070 regbuf), and copy it into valbuf. Extract from an array REGBUF
1071 containing the (raw) register state a function return value of type
1072 TYPE, and copy that, in virtual format, into VALBUF. */
1074 sh_default_extract_return_value (struct type *type, struct regcache *regcache,
1077 int len = TYPE_LENGTH (type);
1078 int return_register = R0_REGNUM;
1085 regcache_cooked_read_unsigned (regcache, R0_REGNUM, &c);
1086 store_unsigned_integer (valbuf, len, c);
1090 int i, regnum = R0_REGNUM;
1091 for (i = 0; i < len; i += 4)
1092 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1095 error ("bad size for return value");
1099 sh3e_sh4_extract_return_value (struct type *type, struct regcache *regcache,
1102 if (sh_treat_as_flt_p (type))
1104 int len = TYPE_LENGTH (type);
1105 int i, regnum = FP0_REGNUM;
1106 for (i = 0; i < len; i += 4)
1107 if (TARGET_BYTE_ORDER == BFD_ENDIAN_LITTLE)
1108 regcache_raw_read (regcache, regnum++, (char *) valbuf + len - 4 - i);
1110 regcache_raw_read (regcache, regnum++, (char *) valbuf + i);
1113 sh_default_extract_return_value (type, regcache, valbuf);
1116 /* Write into appropriate registers a function return value
1117 of type TYPE, given in virtual format.
1118 If the architecture is sh4 or sh3e, store a function's return value
1119 in the R0 general register or in the FP0 floating point register,
1120 depending on the type of the return value. In all the other cases
1121 the result is stored in r0, left-justified. */
1123 sh_default_store_return_value (struct type *type, struct regcache *regcache,
1127 int len = TYPE_LENGTH (type);
1131 val = extract_unsigned_integer (valbuf, len);
1132 regcache_cooked_write_unsigned (regcache, R0_REGNUM, val);
1136 int i, regnum = R0_REGNUM;
1137 for (i = 0; i < len; i += 4)
1138 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1143 sh3e_sh4_store_return_value (struct type *type, struct regcache *regcache,
1146 if (sh_treat_as_flt_p (type))
1148 int len = TYPE_LENGTH (type);
1149 int i, regnum = FP0_REGNUM;
1150 for (i = 0; i < len; i += 4)
1151 regcache_raw_write (regcache, regnum++, (char *) valbuf + i);
1154 sh_default_store_return_value (type, regcache, valbuf);
1157 /* Print the registers in a form similar to the E7000 */
1160 sh_generic_show_regs (void)
1162 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1163 paddr (read_register (PC_REGNUM)),
1164 (long) read_register (SR_REGNUM),
1165 (long) read_register (PR_REGNUM),
1166 (long) read_register (MACH_REGNUM),
1167 (long) read_register (MACL_REGNUM));
1169 printf_filtered ("GBR=%08lx VBR=%08lx",
1170 (long) read_register (GBR_REGNUM),
1171 (long) read_register (VBR_REGNUM));
1174 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1175 (long) read_register (0), (long) read_register (1),
1176 (long) read_register (2), (long) read_register (3),
1177 (long) read_register (4), (long) read_register (5),
1178 (long) read_register (6), (long) read_register (7));
1179 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1180 (long) read_register (8), (long) read_register (9),
1181 (long) read_register (10), (long) read_register (11),
1182 (long) read_register (12), (long) read_register (13),
1183 (long) read_register (14), (long) read_register (15));
1187 sh3_show_regs (void)
1189 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1190 paddr (read_register (PC_REGNUM)),
1191 (long) read_register (SR_REGNUM),
1192 (long) read_register (PR_REGNUM),
1193 (long) read_register (MACH_REGNUM),
1194 (long) read_register (MACL_REGNUM));
1196 printf_filtered ("GBR=%08lx VBR=%08lx",
1197 (long) read_register (GBR_REGNUM),
1198 (long) read_register (VBR_REGNUM));
1199 printf_filtered (" SSR=%08lx SPC=%08lx",
1200 (long) read_register (SSR_REGNUM),
1201 (long) read_register (SPC_REGNUM));
1204 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1205 (long) read_register (0), (long) read_register (1),
1206 (long) read_register (2), (long) read_register (3),
1207 (long) read_register (4), (long) read_register (5),
1208 (long) read_register (6), (long) read_register (7));
1209 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1210 (long) read_register (8), (long) read_register (9),
1211 (long) read_register (10), (long) read_register (11),
1212 (long) read_register (12), (long) read_register (13),
1213 (long) read_register (14), (long) read_register (15));
1218 sh2e_show_regs (void)
1220 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1221 paddr (read_register (PC_REGNUM)),
1222 (long) read_register (SR_REGNUM),
1223 (long) read_register (PR_REGNUM),
1224 (long) read_register (MACH_REGNUM),
1225 (long) read_register (MACL_REGNUM));
1227 printf_filtered ("GBR=%08lx VBR=%08lx",
1228 (long) read_register (GBR_REGNUM),
1229 (long) read_register (VBR_REGNUM));
1230 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1231 (long) read_register (FPUL_REGNUM),
1232 (long) read_register (FPSCR_REGNUM));
1235 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1236 (long) read_register (0), (long) read_register (1),
1237 (long) read_register (2), (long) read_register (3),
1238 (long) read_register (4), (long) read_register (5),
1239 (long) read_register (6), (long) read_register (7));
1240 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1241 (long) read_register (8), (long) read_register (9),
1242 (long) read_register (10), (long) read_register (11),
1243 (long) read_register (12), (long) read_register (13),
1244 (long) read_register (14), (long) read_register (15));
1246 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1247 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1251 sh3e_show_regs (void)
1253 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1254 paddr (read_register (PC_REGNUM)),
1255 (long) read_register (SR_REGNUM),
1256 (long) read_register (PR_REGNUM),
1257 (long) read_register (MACH_REGNUM),
1258 (long) read_register (MACL_REGNUM));
1260 printf_filtered ("GBR=%08lx VBR=%08lx",
1261 (long) read_register (GBR_REGNUM),
1262 (long) read_register (VBR_REGNUM));
1263 printf_filtered (" SSR=%08lx SPC=%08lx",
1264 (long) read_register (SSR_REGNUM),
1265 (long) read_register (SPC_REGNUM));
1266 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1267 (long) read_register (FPUL_REGNUM),
1268 (long) read_register (FPSCR_REGNUM));
1271 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1272 (long) read_register (0), (long) read_register (1),
1273 (long) read_register (2), (long) read_register (3),
1274 (long) read_register (4), (long) read_register (5),
1275 (long) read_register (6), (long) read_register (7));
1276 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1277 (long) read_register (8), (long) read_register (9),
1278 (long) read_register (10), (long) read_register (11),
1279 (long) read_register (12), (long) read_register (13),
1280 (long) read_register (14), (long) read_register (15));
1282 printf_filtered (("FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 0), (long) read_register (FP0_REGNUM + 1), (long) read_register (FP0_REGNUM + 2), (long) read_register (FP0_REGNUM + 3), (long) read_register (FP0_REGNUM + 4), (long) read_register (FP0_REGNUM + 5), (long) read_register (FP0_REGNUM + 6), (long) read_register (FP0_REGNUM + 7));
1283 printf_filtered (("FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"), (long) read_register (FP0_REGNUM + 8), (long) read_register (FP0_REGNUM + 9), (long) read_register (FP0_REGNUM + 10), (long) read_register (FP0_REGNUM + 11), (long) read_register (FP0_REGNUM + 12), (long) read_register (FP0_REGNUM + 13), (long) read_register (FP0_REGNUM + 14), (long) read_register (FP0_REGNUM + 15));
1287 sh3_dsp_show_regs (void)
1289 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1290 paddr (read_register (PC_REGNUM)),
1291 (long) read_register (SR_REGNUM),
1292 (long) read_register (PR_REGNUM),
1293 (long) read_register (MACH_REGNUM),
1294 (long) read_register (MACL_REGNUM));
1296 printf_filtered ("GBR=%08lx VBR=%08lx",
1297 (long) read_register (GBR_REGNUM),
1298 (long) read_register (VBR_REGNUM));
1300 printf_filtered (" SSR=%08lx SPC=%08lx",
1301 (long) read_register (SSR_REGNUM),
1302 (long) read_register (SPC_REGNUM));
1304 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1307 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1308 (long) read_register (0), (long) read_register (1),
1309 (long) read_register (2), (long) read_register (3),
1310 (long) read_register (4), (long) read_register (5),
1311 (long) read_register (6), (long) read_register (7));
1312 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1313 (long) read_register (8), (long) read_register (9),
1314 (long) read_register (10), (long) read_register (11),
1315 (long) read_register (12), (long) read_register (13),
1316 (long) read_register (14), (long) read_register (15));
1319 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1320 (long) read_register (A0G_REGNUM) & 0xff,
1321 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1322 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1323 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1324 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1325 (long) read_register (A1G_REGNUM) & 0xff,
1326 (long) read_register (A1_REGNUM),
1327 (long) read_register (M1_REGNUM),
1328 (long) read_register (X1_REGNUM),
1329 (long) read_register (Y1_REGNUM),
1330 (long) read_register (RE_REGNUM));
1334 sh4_show_regs (void)
1336 int pr = read_register (FPSCR_REGNUM) & 0x80000;
1337 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1338 paddr (read_register (PC_REGNUM)),
1339 (long) read_register (SR_REGNUM),
1340 (long) read_register (PR_REGNUM),
1341 (long) read_register (MACH_REGNUM),
1342 (long) read_register (MACL_REGNUM));
1344 printf_filtered ("GBR=%08lx VBR=%08lx",
1345 (long) read_register (GBR_REGNUM),
1346 (long) read_register (VBR_REGNUM));
1347 printf_filtered (" SSR=%08lx SPC=%08lx",
1348 (long) read_register (SSR_REGNUM),
1349 (long) read_register (SPC_REGNUM));
1350 printf_filtered (" FPUL=%08lx FPSCR=%08lx",
1351 (long) read_register (FPUL_REGNUM),
1352 (long) read_register (FPSCR_REGNUM));
1355 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1356 (long) read_register (0), (long) read_register (1),
1357 (long) read_register (2), (long) read_register (3),
1358 (long) read_register (4), (long) read_register (5),
1359 (long) read_register (6), (long) read_register (7));
1360 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1361 (long) read_register (8), (long) read_register (9),
1362 (long) read_register (10), (long) read_register (11),
1363 (long) read_register (12), (long) read_register (13),
1364 (long) read_register (14), (long) read_register (15));
1366 printf_filtered ((pr
1367 ? "DR0-DR6 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n"
1369 "FP0-FP7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1370 (long) read_register (FP0_REGNUM + 0),
1371 (long) read_register (FP0_REGNUM + 1),
1372 (long) read_register (FP0_REGNUM + 2),
1373 (long) read_register (FP0_REGNUM + 3),
1374 (long) read_register (FP0_REGNUM + 4),
1375 (long) read_register (FP0_REGNUM + 5),
1376 (long) read_register (FP0_REGNUM + 6),
1377 (long) read_register (FP0_REGNUM + 7));
1378 printf_filtered ((pr ?
1379 "DR8-DR14 %08lx%08lx %08lx%08lx %08lx%08lx %08lx%08lx\n" :
1380 "FP8-FP15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n"),
1381 (long) read_register (FP0_REGNUM + 8),
1382 (long) read_register (FP0_REGNUM + 9),
1383 (long) read_register (FP0_REGNUM + 10),
1384 (long) read_register (FP0_REGNUM + 11),
1385 (long) read_register (FP0_REGNUM + 12),
1386 (long) read_register (FP0_REGNUM + 13),
1387 (long) read_register (FP0_REGNUM + 14),
1388 (long) read_register (FP0_REGNUM + 15));
1392 sh4_nofpu_show_regs (void)
1394 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1395 paddr (read_register (PC_REGNUM)),
1396 (long) read_register (SR_REGNUM),
1397 (long) read_register (PR_REGNUM),
1398 (long) read_register (MACH_REGNUM),
1399 (long) read_register (MACL_REGNUM));
1401 printf_filtered ("GBR=%08lx VBR=%08lx",
1402 (long) read_register (GBR_REGNUM),
1403 (long) read_register (VBR_REGNUM));
1404 printf_filtered (" SSR=%08lx SPC=%08lx",
1405 (long) read_register (SSR_REGNUM),
1406 (long) read_register (SPC_REGNUM));
1409 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1410 (long) read_register (0), (long) read_register (1),
1411 (long) read_register (2), (long) read_register (3),
1412 (long) read_register (4), (long) read_register (5),
1413 (long) read_register (6), (long) read_register (7));
1414 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1415 (long) read_register (8), (long) read_register (9),
1416 (long) read_register (10), (long) read_register (11),
1417 (long) read_register (12), (long) read_register (13),
1418 (long) read_register (14), (long) read_register (15));
1422 sh_dsp_show_regs (void)
1424 printf_filtered ("PC=%s SR=%08lx PR=%08lx MACH=%08lx MACHL=%08lx\n",
1425 paddr (read_register (PC_REGNUM)),
1426 (long) read_register (SR_REGNUM),
1427 (long) read_register (PR_REGNUM),
1428 (long) read_register (MACH_REGNUM),
1429 (long) read_register (MACL_REGNUM));
1431 printf_filtered ("GBR=%08lx VBR=%08lx",
1432 (long) read_register (GBR_REGNUM),
1433 (long) read_register (VBR_REGNUM));
1435 printf_filtered (" DSR=%08lx", (long) read_register (DSR_REGNUM));
1438 ("\nR0-R7 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1439 (long) read_register (0), (long) read_register (1),
1440 (long) read_register (2), (long) read_register (3),
1441 (long) read_register (4), (long) read_register (5),
1442 (long) read_register (6), (long) read_register (7));
1443 printf_filtered ("R8-R15 %08lx %08lx %08lx %08lx %08lx %08lx %08lx %08lx\n",
1444 (long) read_register (8), (long) read_register (9),
1445 (long) read_register (10), (long) read_register (11),
1446 (long) read_register (12), (long) read_register (13),
1447 (long) read_register (14), (long) read_register (15));
1450 ("A0G=%02lx A0=%08lx M0=%08lx X0=%08lx Y0=%08lx RS=%08lx MOD=%08lx\n",
1451 (long) read_register (A0G_REGNUM) & 0xff,
1452 (long) read_register (A0_REGNUM), (long) read_register (M0_REGNUM),
1453 (long) read_register (X0_REGNUM), (long) read_register (Y0_REGNUM),
1454 (long) read_register (RS_REGNUM), (long) read_register (MOD_REGNUM));
1455 printf_filtered ("A1G=%02lx A1=%08lx M1=%08lx X1=%08lx Y1=%08lx RE=%08lx\n",
1456 (long) read_register (A1G_REGNUM) & 0xff,
1457 (long) read_register (A1_REGNUM),
1458 (long) read_register (M1_REGNUM),
1459 (long) read_register (X1_REGNUM),
1460 (long) read_register (Y1_REGNUM),
1461 (long) read_register (RE_REGNUM));
1465 sh_show_regs_command (char *args, int from_tty)
1471 /* Return the GDB type object for the "standard" data type
1472 of data in register N. */
1473 static struct type *
1474 sh_sh3e_register_type (struct gdbarch *gdbarch, int reg_nr)
1476 if ((reg_nr >= FP0_REGNUM
1477 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1478 return builtin_type_float;
1480 return builtin_type_int;
1483 static struct type *
1484 sh_sh4_build_float_register_type (int high)
1488 temp = create_range_type (NULL, builtin_type_int, 0, high);
1489 return create_array_type (NULL, builtin_type_float, temp);
1492 static struct type *
1493 sh_sh4_register_type (struct gdbarch *gdbarch, int reg_nr)
1495 if ((reg_nr >= FP0_REGNUM
1496 && (reg_nr <= FP_LAST_REGNUM)) || (reg_nr == FPUL_REGNUM))
1497 return builtin_type_float;
1498 else if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1499 return builtin_type_double;
1500 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1501 return sh_sh4_build_float_register_type (3);
1503 return builtin_type_int;
1506 static struct type *
1507 sh_default_register_type (struct gdbarch *gdbarch, int reg_nr)
1509 return builtin_type_int;
1512 /* On the sh4, the DRi pseudo registers are problematic if the target
1513 is little endian. When the user writes one of those registers, for
1514 instance with 'ser var $dr0=1', we want the double to be stored
1516 fr0 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1517 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1519 This corresponds to little endian byte order & big endian word
1520 order. However if we let gdb write the register w/o conversion, it
1521 will write fr0 and fr1 this way:
1522 fr0 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1523 fr1 = 0x00 0x00 0x00 0x00 0x00 0xf0 0x3f
1524 because it will consider fr0 and fr1 as a single LE stretch of memory.
1526 To achieve what we want we must force gdb to store things in
1527 floatformat_ieee_double_littlebyte_bigword (which is defined in
1528 include/floatformat.h and libiberty/floatformat.c.
1530 In case the target is big endian, there is no problem, the
1531 raw bytes will look like:
1532 fr0 = 0x3f 0xf0 0x00 0x00 0x00 0x00 0x00
1533 fr1 = 0x00 0x00 0x00 0x00 0x00 0x00 0x00
1535 The other pseudo registers (the FVs) also don't pose a problem
1536 because they are stored as 4 individual FP elements. */
1539 sh_register_convert_to_virtual (int regnum, struct type *type,
1540 char *from, char *to)
1542 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1545 floatformat_to_doublest (&floatformat_ieee_double_littlebyte_bigword,
1547 store_typed_floating (to, type, val);
1551 ("sh_register_convert_to_virtual called with non DR register number");
1555 sh_register_convert_to_raw (struct type *type, int regnum,
1556 const void *from, void *to)
1558 if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1560 DOUBLEST val = extract_typed_floating (from, type);
1561 floatformat_from_doublest (&floatformat_ieee_double_littlebyte_bigword,
1565 error ("sh_register_convert_to_raw called with non DR register number");
1568 /* For vectors of 4 floating point registers. */
1570 fv_reg_base_num (int fv_regnum)
1574 fp_regnum = FP0_REGNUM + (fv_regnum - FV0_REGNUM) * 4;
1578 /* For double precision floating point registers, i.e 2 fp regs.*/
1580 dr_reg_base_num (int dr_regnum)
1584 fp_regnum = FP0_REGNUM + (dr_regnum - DR0_REGNUM) * 2;
1589 sh_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1590 int reg_nr, void *buffer)
1592 int base_regnum, portion;
1593 char temp_buffer[MAX_REGISTER_SIZE];
1595 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1597 base_regnum = dr_reg_base_num (reg_nr);
1599 /* Build the value in the provided buffer. */
1600 /* Read the real regs for which this one is an alias. */
1601 for (portion = 0; portion < 2; portion++)
1602 regcache_raw_read (regcache, base_regnum + portion,
1604 + register_size (gdbarch,
1605 base_regnum) * portion));
1606 /* We must pay attention to the endiannes. */
1607 sh_register_convert_to_virtual (reg_nr,
1608 gdbarch_register_type (gdbarch, reg_nr),
1609 temp_buffer, buffer);
1611 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1613 base_regnum = fv_reg_base_num (reg_nr);
1615 /* Read the real regs for which this one is an alias. */
1616 for (portion = 0; portion < 4; portion++)
1617 regcache_raw_read (regcache, base_regnum + portion,
1619 + register_size (gdbarch,
1620 base_regnum) * portion));
1625 sh_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1626 int reg_nr, const void *buffer)
1628 int base_regnum, portion;
1629 char temp_buffer[MAX_REGISTER_SIZE];
1631 if (reg_nr >= DR0_REGNUM && reg_nr <= DR_LAST_REGNUM)
1633 base_regnum = dr_reg_base_num (reg_nr);
1635 /* We must pay attention to the endiannes. */
1636 sh_register_convert_to_raw (gdbarch_register_type (gdbarch, reg_nr),
1637 reg_nr, buffer, temp_buffer);
1639 /* Write the real regs for which this one is an alias. */
1640 for (portion = 0; portion < 2; portion++)
1641 regcache_raw_write (regcache, base_regnum + portion,
1643 + register_size (gdbarch,
1644 base_regnum) * portion));
1646 else if (reg_nr >= FV0_REGNUM && reg_nr <= FV_LAST_REGNUM)
1648 base_regnum = fv_reg_base_num (reg_nr);
1650 /* Write the real regs for which this one is an alias. */
1651 for (portion = 0; portion < 4; portion++)
1652 regcache_raw_write (regcache, base_regnum + portion,
1654 + register_size (gdbarch,
1655 base_regnum) * portion));
1659 /* Floating point vector of 4 float registers. */
1661 do_fv_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1664 int first_fp_reg_num = fv_reg_base_num (fv_regnum);
1665 fprintf_filtered (file, "fv%d\t0x%08x\t0x%08x\t0x%08x\t0x%08x\n",
1666 fv_regnum - FV0_REGNUM,
1667 (int) read_register (first_fp_reg_num),
1668 (int) read_register (first_fp_reg_num + 1),
1669 (int) read_register (first_fp_reg_num + 2),
1670 (int) read_register (first_fp_reg_num + 3));
1673 /* Double precision registers. */
1675 do_dr_register_info (struct gdbarch *gdbarch, struct ui_file *file,
1678 int first_fp_reg_num = dr_reg_base_num (dr_regnum);
1680 fprintf_filtered (file, "dr%d\t0x%08x%08x\n",
1681 dr_regnum - DR0_REGNUM,
1682 (int) read_register (first_fp_reg_num),
1683 (int) read_register (first_fp_reg_num + 1));
1687 sh_print_pseudo_register (struct gdbarch *gdbarch, struct ui_file *file,
1690 if (regnum < NUM_REGS || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1691 internal_error (__FILE__, __LINE__,
1692 "Invalid pseudo register number %d\n", regnum);
1693 else if (regnum >= DR0_REGNUM && regnum <= DR_LAST_REGNUM)
1694 do_dr_register_info (gdbarch, file, regnum);
1695 else if (regnum >= FV0_REGNUM && regnum <= FV_LAST_REGNUM)
1696 do_fv_register_info (gdbarch, file, regnum);
1700 sh_do_fp_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1701 { /* do values for FP (float) regs */
1703 double flt; /* double extracted from raw hex data */
1707 /* Allocate space for the float. */
1708 raw_buffer = (char *) alloca (register_size (gdbarch, FP0_REGNUM));
1710 /* Get the data in raw format. */
1711 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1712 error ("can't read register %d (%s)", regnum, REGISTER_NAME (regnum));
1714 /* Get the register as a number */
1715 flt = unpack_double (builtin_type_float, raw_buffer, &inv);
1717 /* Print the name and some spaces. */
1718 fputs_filtered (REGISTER_NAME (regnum), file);
1719 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1721 /* Print the value. */
1723 fprintf_filtered (file, "<invalid float>");
1725 fprintf_filtered (file, "%-10.9g", flt);
1727 /* Print the fp register as hex. */
1728 fprintf_filtered (file, "\t(raw 0x");
1729 for (j = 0; j < register_size (gdbarch, regnum); j++)
1731 int idx = (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1733 : register_size (gdbarch, regnum) - 1 - j);
1734 fprintf_filtered (file, "%02x", (unsigned char) raw_buffer[idx]);
1736 fprintf_filtered (file, ")");
1737 fprintf_filtered (file, "\n");
1741 sh_do_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1743 char raw_buffer[MAX_REGISTER_SIZE];
1745 fputs_filtered (REGISTER_NAME (regnum), file);
1746 print_spaces_filtered (15 - strlen (REGISTER_NAME (regnum)), file);
1748 /* Get the data in raw format. */
1749 if (!frame_register_read (get_selected_frame (), regnum, raw_buffer))
1750 fprintf_filtered (file, "*value not available*\n");
1752 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1753 file, 'x', 1, 0, Val_pretty_default);
1754 fprintf_filtered (file, "\t");
1755 val_print (gdbarch_register_type (gdbarch, regnum), raw_buffer, 0, 0,
1756 file, 0, 1, 0, Val_pretty_default);
1757 fprintf_filtered (file, "\n");
1761 sh_print_register (struct gdbarch *gdbarch, struct ui_file *file, int regnum)
1763 if (regnum < 0 || regnum >= NUM_REGS + NUM_PSEUDO_REGS)
1764 internal_error (__FILE__, __LINE__,
1765 "Invalid register number %d\n", regnum);
1767 else if (regnum >= 0 && regnum < NUM_REGS)
1769 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1771 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1773 sh_do_register (gdbarch, file, regnum); /* All other regs */
1776 else if (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1778 sh_print_pseudo_register (gdbarch, file, regnum);
1783 sh_print_registers_info (struct gdbarch *gdbarch, struct ui_file *file,
1784 struct frame_info *frame, int regnum, int fpregs)
1786 if (regnum != -1) /* do one specified register */
1788 if (*(REGISTER_NAME (regnum)) == '\0')
1789 error ("Not a valid register for the current processor type");
1791 sh_print_register (gdbarch, file, regnum);
1794 /* do all (or most) registers */
1797 while (regnum < NUM_REGS)
1799 /* If the register name is empty, it is undefined for this
1800 processor, so don't display anything. */
1801 if (REGISTER_NAME (regnum) == NULL
1802 || *(REGISTER_NAME (regnum)) == '\0')
1808 if (TYPE_CODE (gdbarch_register_type (gdbarch, regnum)) ==
1813 /* true for "INFO ALL-REGISTERS" command */
1814 sh_do_fp_register (gdbarch, file, regnum); /* FP regs */
1818 regnum += (FP_LAST_REGNUM - FP0_REGNUM); /* skip FP regs */
1822 sh_do_register (gdbarch, file, regnum); /* All other regs */
1828 while (regnum < NUM_REGS + NUM_PSEUDO_REGS)
1830 sh_print_pseudo_register (gdbarch, file, regnum);
1836 #ifdef SVR4_SHARED_LIBS
1838 /* Fetch (and possibly build) an appropriate link_map_offsets structure
1839 for native i386 linux targets using the struct offsets defined in
1840 link.h (but without actual reference to that file).
1842 This makes it possible to access i386-linux shared libraries from
1843 a gdb that was not built on an i386-linux host (for cross debugging).
1846 struct link_map_offsets *
1847 sh_linux_svr4_fetch_link_map_offsets (void)
1849 static struct link_map_offsets lmo;
1850 static struct link_map_offsets *lmp = 0;
1856 lmo.r_debug_size = 8; /* 20 not actual size but all we need */
1858 lmo.r_map_offset = 4;
1861 lmo.link_map_size = 20; /* 552 not actual size but all we need */
1863 lmo.l_addr_offset = 0;
1864 lmo.l_addr_size = 4;
1866 lmo.l_name_offset = 4;
1867 lmo.l_name_size = 4;
1869 lmo.l_next_offset = 12;
1870 lmo.l_next_size = 4;
1872 lmo.l_prev_offset = 16;
1873 lmo.l_prev_size = 4;
1878 #endif /* SVR4_SHARED_LIBS */
1881 sh_dsp_register_sim_regno (int nr)
1883 if (legacy_register_sim_regno (nr) < 0)
1884 return legacy_register_sim_regno (nr);
1885 if (nr >= DSR_REGNUM && nr <= Y1_REGNUM)
1886 return nr - DSR_REGNUM + SIM_SH_DSR_REGNUM;
1887 if (nr == MOD_REGNUM)
1888 return SIM_SH_MOD_REGNUM;
1889 if (nr == RS_REGNUM)
1890 return SIM_SH_RS_REGNUM;
1891 if (nr == RE_REGNUM)
1892 return SIM_SH_RE_REGNUM;
1893 if (nr >= DSP_R0_BANK_REGNUM && nr <= DSP_R7_BANK_REGNUM)
1894 return nr - DSP_R0_BANK_REGNUM + SIM_SH_R0_BANK_REGNUM;
1898 static struct sh_frame_cache *
1899 sh_alloc_frame_cache (void)
1901 struct sh_frame_cache *cache;
1904 cache = FRAME_OBSTACK_ZALLOC (struct sh_frame_cache);
1908 cache->saved_sp = 0;
1909 cache->sp_offset = 0;
1912 /* Frameless until proven otherwise. */
1915 /* Saved registers. We initialize these to -1 since zero is a valid
1916 offset (that's where fp is supposed to be stored). */
1917 for (i = 0; i < SH_NUM_REGS; i++)
1919 cache->saved_regs[i] = -1;
1925 static struct sh_frame_cache *
1926 sh_frame_cache (struct frame_info *next_frame, void **this_cache)
1928 struct sh_frame_cache *cache;
1929 CORE_ADDR current_pc;
1935 cache = sh_alloc_frame_cache ();
1936 *this_cache = cache;
1938 /* In principle, for normal frames, fp holds the frame pointer,
1939 which holds the base address for the current stack frame.
1940 However, for functions that don't need it, the frame pointer is
1941 optional. For these "frameless" functions the frame pointer is
1942 actually the frame pointer of the calling frame. */
1943 cache->base = frame_unwind_register_unsigned (next_frame, FP_REGNUM);
1944 if (cache->base == 0)
1947 cache->pc = frame_func_unwind (next_frame);
1948 current_pc = frame_pc_unwind (next_frame);
1950 sh_analyze_prologue (cache->pc, current_pc, cache);
1952 if (!cache->uses_fp)
1954 /* We didn't find a valid frame, which means that CACHE->base
1955 currently holds the frame pointer for our calling frame. If
1956 we're at the start of a function, or somewhere half-way its
1957 prologue, the function's frame probably hasn't been fully
1958 setup yet. Try to reconstruct the base address for the stack
1959 frame by looking at the stack pointer. For truly "frameless"
1960 functions this might work too. */
1961 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
1964 /* Now that we have the base address for the stack frame we can
1965 calculate the value of sp in the calling frame. */
1966 cache->saved_sp = cache->base + cache->sp_offset;
1968 /* Adjust all the saved registers such that they contain addresses
1969 instead of offsets. */
1970 for (i = 0; i < SH_NUM_REGS; i++)
1971 if (cache->saved_regs[i] != -1)
1972 cache->saved_regs[i] = cache->saved_sp - cache->saved_regs[i] - 4;
1978 sh_frame_prev_register (struct frame_info *next_frame, void **this_cache,
1979 int regnum, int *optimizedp,
1980 enum lval_type *lvalp, CORE_ADDR *addrp,
1981 int *realnump, void *valuep)
1983 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
1985 gdb_assert (regnum >= 0);
1987 if (regnum == SP_REGNUM && cache->saved_sp)
1995 /* Store the value. */
1996 store_unsigned_integer (valuep, 4, cache->saved_sp);
2001 /* The PC of the previous frame is stored in the PR register of
2002 the current frame. Frob regnum so that we pull the value from
2003 the correct place. */
2004 if (regnum == PC_REGNUM)
2007 if (regnum < SH_NUM_REGS && cache->saved_regs[regnum] != -1)
2010 *lvalp = lval_memory;
2011 *addrp = cache->saved_regs[regnum];
2015 /* Read the value in from memory. */
2016 read_memory (*addrp, valuep,
2017 register_size (current_gdbarch, regnum));
2022 frame_register_unwind (next_frame, regnum,
2023 optimizedp, lvalp, addrp, realnump, valuep);
2027 sh_frame_this_id (struct frame_info *next_frame, void **this_cache,
2028 struct frame_id *this_id)
2030 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2032 /* This marks the outermost frame. */
2033 if (cache->base == 0)
2036 *this_id = frame_id_build (cache->saved_sp, cache->pc);
2039 static const struct frame_unwind sh_frame_unwind = {
2042 sh_frame_prev_register
2045 static const struct frame_unwind *
2046 sh_frame_sniffer (struct frame_info *next_frame)
2048 return &sh_frame_unwind;
2052 sh_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2054 return frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2058 sh_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2060 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2063 static struct frame_id
2064 sh_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2066 return frame_id_build (sh_unwind_sp (gdbarch, next_frame),
2067 frame_pc_unwind (next_frame));
2071 sh_frame_base_address (struct frame_info *next_frame, void **this_cache)
2073 struct sh_frame_cache *cache = sh_frame_cache (next_frame, this_cache);
2078 static const struct frame_base sh_frame_base = {
2080 sh_frame_base_address,
2081 sh_frame_base_address,
2082 sh_frame_base_address
2085 /* The epilogue is defined here as the area at the end of a function,
2086 either on the `ret' instruction itself or after an instruction which
2087 destroys the function's stack frame. */
2089 sh_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
2091 CORE_ADDR func_addr = 0, func_end = 0;
2093 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
2096 /* The sh epilogue is max. 14 bytes long. Give another 14 bytes
2097 for a nop and some fixed data (e.g. big offsets) which are
2098 unfortunately also treated as part of the function (which
2099 means, they are below func_end. */
2100 CORE_ADDR addr = func_end - 28;
2101 if (addr < func_addr + 4)
2102 addr = func_addr + 4;
2106 /* First search forward until hitting an rts. */
2107 while (addr < func_end
2108 && !IS_RTS (read_memory_unsigned_integer (addr, 2)))
2110 if (addr >= func_end)
2113 /* At this point we should find a mov.l @r15+,r14 instruction,
2114 either before or after the rts. If not, then the function has
2115 probably no "normal" epilogue and we bail out here. */
2116 inst = read_memory_unsigned_integer (addr - 2, 2);
2117 if (IS_RESTORE_FP (read_memory_unsigned_integer (addr - 2, 2)))
2119 else if (!IS_RESTORE_FP (read_memory_unsigned_integer (addr + 2, 2)))
2122 /* Step over possible lds.l @r15+,pr. */
2123 inst = read_memory_unsigned_integer (addr - 2, 2);
2127 inst = read_memory_unsigned_integer (addr - 2, 2);
2130 /* Step over possible mov r14,r15. */
2131 if (IS_MOV_FP_SP (inst))
2134 inst = read_memory_unsigned_integer (addr - 2, 2);
2137 /* Now check for FP adjustments, using add #imm,r14 or add rX, r14
2139 while (addr > func_addr + 4
2140 && (IS_ADD_REG_TO_FP (inst) || IS_ADD_IMM_FP (inst)))
2143 inst = read_memory_unsigned_integer (addr - 2, 2);
2152 static gdbarch_init_ftype sh_gdbarch_init;
2154 static struct gdbarch *
2155 sh_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2157 struct gdbarch *gdbarch;
2159 sh_show_regs = sh_generic_show_regs;
2160 switch (info.bfd_arch_info->mach)
2163 sh_show_regs = sh2e_show_regs;
2165 case bfd_mach_sh_dsp:
2166 sh_show_regs = sh_dsp_show_regs;
2170 sh_show_regs = sh3_show_regs;
2174 sh_show_regs = sh3e_show_regs;
2177 case bfd_mach_sh3_dsp:
2178 case bfd_mach_sh4al_dsp:
2179 sh_show_regs = sh3_dsp_show_regs;
2184 sh_show_regs = sh4_show_regs;
2187 case bfd_mach_sh4_nofpu:
2188 case bfd_mach_sh4a_nofpu:
2189 sh_show_regs = sh4_nofpu_show_regs;
2193 sh_show_regs = sh64_show_regs;
2194 /* SH5 is handled entirely in sh64-tdep.c */
2195 return sh64_gdbarch_init (info, arches);
2198 /* If there is already a candidate, use it. */
2199 arches = gdbarch_list_lookup_by_info (arches, &info);
2201 return arches->gdbarch;
2203 /* None found, create a new architecture from the information
2205 gdbarch = gdbarch_alloc (&info, NULL);
2207 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2208 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2209 set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2210 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2211 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2212 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2213 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2214 set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2216 set_gdbarch_num_regs (gdbarch, SH_NUM_REGS);
2217 set_gdbarch_sp_regnum (gdbarch, 15);
2218 set_gdbarch_pc_regnum (gdbarch, 16);
2219 set_gdbarch_fp0_regnum (gdbarch, -1);
2220 set_gdbarch_num_pseudo_regs (gdbarch, 0);
2222 set_gdbarch_register_type (gdbarch, sh_default_register_type);
2224 set_gdbarch_print_registers_info (gdbarch, sh_print_registers_info);
2226 set_gdbarch_breakpoint_from_pc (gdbarch, sh_breakpoint_from_pc);
2227 set_gdbarch_use_struct_convention (gdbarch, sh_use_struct_convention);
2229 set_gdbarch_print_insn (gdbarch, gdb_print_insn_sh);
2230 set_gdbarch_register_sim_regno (gdbarch, legacy_register_sim_regno);
2232 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2234 set_gdbarch_store_return_value (gdbarch, sh_default_store_return_value);
2235 set_gdbarch_extract_return_value (gdbarch, sh_default_extract_return_value);
2236 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, sh_extract_struct_value_address);
2238 set_gdbarch_skip_prologue (gdbarch, sh_skip_prologue);
2239 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2241 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_nofpu);
2243 set_gdbarch_deprecated_frameless_function_invocation (gdbarch, legacy_frameless_look_for_prologue);
2244 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2246 set_gdbarch_frame_align (gdbarch, sh_frame_align);
2247 set_gdbarch_unwind_sp (gdbarch, sh_unwind_sp);
2248 set_gdbarch_unwind_pc (gdbarch, sh_unwind_pc);
2249 set_gdbarch_unwind_dummy_id (gdbarch, sh_unwind_dummy_id);
2250 frame_base_set_default (gdbarch, &sh_frame_base);
2252 set_gdbarch_in_function_epilogue_p (gdbarch, sh_in_function_epilogue_p);
2254 switch (info.bfd_arch_info->mach)
2257 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2261 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2265 /* doubles on sh2e and sh3e are actually 4 byte. */
2266 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2268 set_gdbarch_register_name (gdbarch, sh_sh2e_register_name);
2269 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2270 set_gdbarch_fp0_regnum (gdbarch, 25);
2271 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2272 set_gdbarch_extract_return_value (gdbarch,
2273 sh3e_sh4_extract_return_value);
2274 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2277 case bfd_mach_sh_dsp:
2278 set_gdbarch_register_name (gdbarch, sh_sh_dsp_register_name);
2279 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2283 set_gdbarch_register_name (gdbarch, sh_sh3_register_name);
2287 /* doubles on sh2e and sh3e are actually 4 byte. */
2288 set_gdbarch_double_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2290 set_gdbarch_register_name (gdbarch, sh_sh3e_register_name);
2291 set_gdbarch_register_type (gdbarch, sh_sh3e_register_type);
2292 set_gdbarch_fp0_regnum (gdbarch, 25);
2293 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2294 set_gdbarch_extract_return_value (gdbarch,
2295 sh3e_sh4_extract_return_value);
2296 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2299 case bfd_mach_sh3_dsp:
2300 set_gdbarch_register_name (gdbarch, sh_sh3_dsp_register_name);
2301 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2306 set_gdbarch_register_name (gdbarch, sh_sh4_register_name);
2307 set_gdbarch_register_type (gdbarch, sh_sh4_register_type);
2308 set_gdbarch_fp0_regnum (gdbarch, 25);
2309 set_gdbarch_num_pseudo_regs (gdbarch, 12);
2310 set_gdbarch_pseudo_register_read (gdbarch, sh_pseudo_register_read);
2311 set_gdbarch_pseudo_register_write (gdbarch, sh_pseudo_register_write);
2312 set_gdbarch_store_return_value (gdbarch, sh3e_sh4_store_return_value);
2313 set_gdbarch_extract_return_value (gdbarch,
2314 sh3e_sh4_extract_return_value);
2315 set_gdbarch_push_dummy_call (gdbarch, sh_push_dummy_call_fpu);
2318 case bfd_mach_sh4_nofpu:
2319 case bfd_mach_sh4a_nofpu:
2320 set_gdbarch_register_name (gdbarch, sh_sh4_nofpu_register_name);
2323 case bfd_mach_sh4al_dsp:
2324 set_gdbarch_register_name (gdbarch, sh_sh4al_dsp_register_name);
2325 set_gdbarch_register_sim_regno (gdbarch, sh_dsp_register_sim_regno);
2329 set_gdbarch_register_name (gdbarch, sh_sh_register_name);
2333 /* Hook in ABI-specific overrides, if they have been registered. */
2334 gdbarch_init_osabi (info, gdbarch);
2336 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
2337 frame_unwind_append_sniffer (gdbarch, sh_frame_sniffer);
2342 extern initialize_file_ftype _initialize_sh_tdep; /* -Wmissing-prototypes */
2345 _initialize_sh_tdep (void)
2347 struct cmd_list_element *c;
2349 gdbarch_register (bfd_arch_sh, sh_gdbarch_init, NULL);
2351 add_com ("regs", class_vars, sh_show_regs_command, "Print all registers");