1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-1987, 1989, 1991-2012 Free Software Foundation,
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
53 #include "solib-svr4.h"
55 #include "ppc-ravenscar-thread.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "features/rs6000/powerpc-32.c"
65 #include "features/rs6000/powerpc-altivec32.c"
66 #include "features/rs6000/powerpc-vsx32.c"
67 #include "features/rs6000/powerpc-403.c"
68 #include "features/rs6000/powerpc-403gc.c"
69 #include "features/rs6000/powerpc-405.c"
70 #include "features/rs6000/powerpc-505.c"
71 #include "features/rs6000/powerpc-601.c"
72 #include "features/rs6000/powerpc-602.c"
73 #include "features/rs6000/powerpc-603.c"
74 #include "features/rs6000/powerpc-604.c"
75 #include "features/rs6000/powerpc-64.c"
76 #include "features/rs6000/powerpc-altivec64.c"
77 #include "features/rs6000/powerpc-vsx64.c"
78 #include "features/rs6000/powerpc-7400.c"
79 #include "features/rs6000/powerpc-750.c"
80 #include "features/rs6000/powerpc-860.c"
81 #include "features/rs6000/powerpc-e500.c"
82 #include "features/rs6000/rs6000.c"
84 /* Determine if regnum is an SPE pseudo-register. */
85 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
86 && (regnum) >= (tdep)->ppc_ev0_regnum \
87 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
89 /* Determine if regnum is a decimal float pseudo-register. */
90 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_dl0_regnum \
92 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
94 /* Determine if regnum is a POWER7 VSX register. */
95 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_vsr0_regnum \
97 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
99 /* Determine if regnum is a POWER7 Extended FP register. */
100 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_efpr0_regnum \
102 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
104 /* The list of available "set powerpc ..." and "show powerpc ..."
106 static struct cmd_list_element *setpowerpccmdlist = NULL;
107 static struct cmd_list_element *showpowerpccmdlist = NULL;
109 static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
111 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
112 static const char *const powerpc_vector_strings[] =
121 /* A variable that can be configured by the user. */
122 static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
123 static const char *powerpc_vector_abi_string = "auto";
125 /* To be used by skip_prologue. */
127 struct rs6000_framedata
129 int offset; /* total size of frame --- the distance
130 by which we decrement sp to allocate
132 int saved_gpr; /* smallest # of saved gpr */
133 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
134 int saved_fpr; /* smallest # of saved fpr */
135 int saved_vr; /* smallest # of saved vr */
136 int saved_ev; /* smallest # of saved ev */
137 int alloca_reg; /* alloca register number (frame ptr) */
138 char frameless; /* true if frameless functions. */
139 char nosavedpc; /* true if pc not saved. */
140 char used_bl; /* true if link register clobbered */
141 int gpr_offset; /* offset of saved gprs from prev sp */
142 int fpr_offset; /* offset of saved fprs from prev sp */
143 int vr_offset; /* offset of saved vrs from prev sp */
144 int ev_offset; /* offset of saved evs from prev sp */
145 int lr_offset; /* offset of saved lr */
146 int lr_register; /* register of saved lr, if trustworthy */
147 int cr_offset; /* offset of saved cr */
148 int vrsave_offset; /* offset of saved vrsave register */
152 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
154 vsx_register_p (struct gdbarch *gdbarch, int regno)
156 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 if (tdep->ppc_vsr0_regnum < 0)
160 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
161 <= tdep->ppc_vsr0_upper_regnum + 31);
164 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
166 altivec_register_p (struct gdbarch *gdbarch, int regno)
168 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
169 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
172 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
176 /* Return true if REGNO is an SPE register, false otherwise. */
178 spe_register_p (struct gdbarch *gdbarch, int regno)
180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
182 /* Is it a reference to EV0 -- EV31, and do we have those? */
183 if (IS_SPE_PSEUDOREG (tdep, regno))
186 /* Is it a reference to one of the raw upper GPR halves? */
187 if (tdep->ppc_ev0_upper_regnum >= 0
188 && tdep->ppc_ev0_upper_regnum <= regno
189 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
192 /* Is it a reference to the 64-bit accumulator, and do we have that? */
193 if (tdep->ppc_acc_regnum >= 0
194 && tdep->ppc_acc_regnum == regno)
197 /* Is it a reference to the SPE floating-point status and control register,
198 and do we have that? */
199 if (tdep->ppc_spefscr_regnum >= 0
200 && tdep->ppc_spefscr_regnum == regno)
207 /* Return non-zero if the architecture described by GDBARCH has
208 floating-point registers (f0 --- f31 and fpscr). */
210 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
212 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
214 return (tdep->ppc_fp0_regnum >= 0
215 && tdep->ppc_fpscr_regnum >= 0);
218 /* Return non-zero if the architecture described by GDBARCH has
219 VSX registers (vsr0 --- vsr63). */
221 ppc_vsx_support_p (struct gdbarch *gdbarch)
223 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
225 return tdep->ppc_vsr0_regnum >= 0;
228 /* Return non-zero if the architecture described by GDBARCH has
229 Altivec registers (vr0 --- vr31, vrsave and vscr). */
231 ppc_altivec_support_p (struct gdbarch *gdbarch)
233 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
235 return (tdep->ppc_vr0_regnum >= 0
236 && tdep->ppc_vrsave_regnum >= 0);
239 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
242 This is a helper function for init_sim_regno_table, constructing
243 the table mapping GDB register numbers to sim register numbers; we
244 initialize every element in that table to -1 before we start
247 set_sim_regno (int *table, int gdb_regno, int sim_regno)
249 /* Make sure we don't try to assign any given GDB register a sim
250 register number more than once. */
251 gdb_assert (table[gdb_regno] == -1);
252 table[gdb_regno] = sim_regno;
256 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
257 numbers to simulator register numbers, based on the values placed
258 in the ARCH->tdep->ppc_foo_regnum members. */
260 init_sim_regno_table (struct gdbarch *arch)
262 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
263 int total_regs = gdbarch_num_regs (arch);
264 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
266 static const char *const segment_regs[] = {
267 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
268 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
271 /* Presume that all registers not explicitly mentioned below are
272 unavailable from the sim. */
273 for (i = 0; i < total_regs; i++)
276 /* General-purpose registers. */
277 for (i = 0; i < ppc_num_gprs; i++)
278 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
280 /* Floating-point registers. */
281 if (tdep->ppc_fp0_regnum >= 0)
282 for (i = 0; i < ppc_num_fprs; i++)
283 set_sim_regno (sim_regno,
284 tdep->ppc_fp0_regnum + i,
285 sim_ppc_f0_regnum + i);
286 if (tdep->ppc_fpscr_regnum >= 0)
287 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
289 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
291 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
293 /* Segment registers. */
294 for (i = 0; i < ppc_num_srs; i++)
298 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
300 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
303 /* Altivec registers. */
304 if (tdep->ppc_vr0_regnum >= 0)
306 for (i = 0; i < ppc_num_vrs; i++)
307 set_sim_regno (sim_regno,
308 tdep->ppc_vr0_regnum + i,
309 sim_ppc_vr0_regnum + i);
311 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
312 we can treat this more like the other cases. */
313 set_sim_regno (sim_regno,
314 tdep->ppc_vr0_regnum + ppc_num_vrs,
315 sim_ppc_vscr_regnum);
317 /* vsave is a special-purpose register, so the code below handles it. */
319 /* SPE APU (E500) registers. */
320 if (tdep->ppc_ev0_upper_regnum >= 0)
321 for (i = 0; i < ppc_num_gprs; i++)
322 set_sim_regno (sim_regno,
323 tdep->ppc_ev0_upper_regnum + i,
324 sim_ppc_rh0_regnum + i);
325 if (tdep->ppc_acc_regnum >= 0)
326 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
327 /* spefscr is a special-purpose register, so the code below handles it. */
330 /* Now handle all special-purpose registers. Verify that they
331 haven't mistakenly been assigned numbers by any of the above
333 for (i = 0; i < sim_ppc_num_sprs; i++)
335 const char *spr_name = sim_spr_register_name (i);
338 if (spr_name != NULL)
339 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
342 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
346 /* Drop the initialized array into place. */
347 tdep->sim_regno = sim_regno;
351 /* Given a GDB register number REG, return the corresponding SIM
354 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
356 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
359 if (tdep->sim_regno == NULL)
360 init_sim_regno_table (gdbarch);
363 && reg <= gdbarch_num_regs (gdbarch)
364 + gdbarch_num_pseudo_regs (gdbarch));
365 sim_regno = tdep->sim_regno[reg];
370 return LEGACY_SIM_REGNO_IGNORE;
375 /* Register set support functions. */
377 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
378 Write the register to REGCACHE. */
381 ppc_supply_reg (struct regcache *regcache, int regnum,
382 const gdb_byte *regs, size_t offset, int regsize)
384 if (regnum != -1 && offset != -1)
388 struct gdbarch *gdbarch = get_regcache_arch (regcache);
389 int gdb_regsize = register_size (gdbarch, regnum);
390 if (gdb_regsize < regsize
391 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
392 offset += regsize - gdb_regsize;
394 regcache_raw_supply (regcache, regnum, regs + offset);
398 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
399 in a field REGSIZE wide. Zero pad as necessary. */
402 ppc_collect_reg (const struct regcache *regcache, int regnum,
403 gdb_byte *regs, size_t offset, int regsize)
405 if (regnum != -1 && offset != -1)
409 struct gdbarch *gdbarch = get_regcache_arch (regcache);
410 int gdb_regsize = register_size (gdbarch, regnum);
411 if (gdb_regsize < regsize)
413 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
415 memset (regs + offset, 0, regsize - gdb_regsize);
416 offset += regsize - gdb_regsize;
419 memset (regs + offset + regsize - gdb_regsize, 0,
420 regsize - gdb_regsize);
423 regcache_raw_collect (regcache, regnum, regs + offset);
428 ppc_greg_offset (struct gdbarch *gdbarch,
429 struct gdbarch_tdep *tdep,
430 const struct ppc_reg_offsets *offsets,
434 *regsize = offsets->gpr_size;
435 if (regnum >= tdep->ppc_gp0_regnum
436 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
437 return (offsets->r0_offset
438 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
440 if (regnum == gdbarch_pc_regnum (gdbarch))
441 return offsets->pc_offset;
443 if (regnum == tdep->ppc_ps_regnum)
444 return offsets->ps_offset;
446 if (regnum == tdep->ppc_lr_regnum)
447 return offsets->lr_offset;
449 if (regnum == tdep->ppc_ctr_regnum)
450 return offsets->ctr_offset;
452 *regsize = offsets->xr_size;
453 if (regnum == tdep->ppc_cr_regnum)
454 return offsets->cr_offset;
456 if (regnum == tdep->ppc_xer_regnum)
457 return offsets->xer_offset;
459 if (regnum == tdep->ppc_mq_regnum)
460 return offsets->mq_offset;
466 ppc_fpreg_offset (struct gdbarch_tdep *tdep,
467 const struct ppc_reg_offsets *offsets,
470 if (regnum >= tdep->ppc_fp0_regnum
471 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
472 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
474 if (regnum == tdep->ppc_fpscr_regnum)
475 return offsets->fpscr_offset;
481 ppc_vrreg_offset (struct gdbarch_tdep *tdep,
482 const struct ppc_reg_offsets *offsets,
485 if (regnum >= tdep->ppc_vr0_regnum
486 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
487 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
489 if (regnum == tdep->ppc_vrsave_regnum - 1)
490 return offsets->vscr_offset;
492 if (regnum == tdep->ppc_vrsave_regnum)
493 return offsets->vrsave_offset;
498 /* Supply register REGNUM in the general-purpose register set REGSET
499 from the buffer specified by GREGS and LEN to register cache
500 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
503 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
504 int regnum, const void *gregs, size_t len)
506 struct gdbarch *gdbarch = get_regcache_arch (regcache);
507 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
508 const struct ppc_reg_offsets *offsets = regset->descr;
515 int gpr_size = offsets->gpr_size;
517 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
518 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
519 i++, offset += gpr_size)
520 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
522 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
523 gregs, offsets->pc_offset, gpr_size);
524 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
525 gregs, offsets->ps_offset, gpr_size);
526 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
527 gregs, offsets->lr_offset, gpr_size);
528 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
529 gregs, offsets->ctr_offset, gpr_size);
530 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
531 gregs, offsets->cr_offset, offsets->xr_size);
532 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
533 gregs, offsets->xer_offset, offsets->xr_size);
534 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
535 gregs, offsets->mq_offset, offsets->xr_size);
539 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
540 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
543 /* Supply register REGNUM in the floating-point register set REGSET
544 from the buffer specified by FPREGS and LEN to register cache
545 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
548 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
549 int regnum, const void *fpregs, size_t len)
551 struct gdbarch *gdbarch = get_regcache_arch (regcache);
552 struct gdbarch_tdep *tdep;
553 const struct ppc_reg_offsets *offsets;
556 if (!ppc_floating_point_unit_p (gdbarch))
559 tdep = gdbarch_tdep (gdbarch);
560 offsets = regset->descr;
565 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
566 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
568 ppc_supply_reg (regcache, i, fpregs, offset, 8);
570 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
571 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
575 offset = ppc_fpreg_offset (tdep, offsets, regnum);
576 ppc_supply_reg (regcache, regnum, fpregs, offset,
577 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
580 /* Supply register REGNUM in the VSX register set REGSET
581 from the buffer specified by VSXREGS and LEN to register cache
582 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
585 ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
586 int regnum, const void *vsxregs, size_t len)
588 struct gdbarch *gdbarch = get_regcache_arch (regcache);
589 struct gdbarch_tdep *tdep;
591 if (!ppc_vsx_support_p (gdbarch))
594 tdep = gdbarch_tdep (gdbarch);
600 for (i = tdep->ppc_vsr0_upper_regnum;
601 i < tdep->ppc_vsr0_upper_regnum + 32;
603 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
608 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
611 /* Supply register REGNUM in the Altivec register set REGSET
612 from the buffer specified by VRREGS and LEN to register cache
613 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
616 ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
617 int regnum, const void *vrregs, size_t len)
619 struct gdbarch *gdbarch = get_regcache_arch (regcache);
620 struct gdbarch_tdep *tdep;
621 const struct ppc_reg_offsets *offsets;
624 if (!ppc_altivec_support_p (gdbarch))
627 tdep = gdbarch_tdep (gdbarch);
628 offsets = regset->descr;
633 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
634 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
636 ppc_supply_reg (regcache, i, vrregs, offset, 16);
638 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
639 vrregs, offsets->vscr_offset, 4);
641 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
642 vrregs, offsets->vrsave_offset, 4);
646 offset = ppc_vrreg_offset (tdep, offsets, regnum);
647 if (regnum != tdep->ppc_vrsave_regnum
648 && regnum != tdep->ppc_vrsave_regnum - 1)
649 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
651 ppc_supply_reg (regcache, regnum,
655 /* Collect register REGNUM in the general-purpose register set
656 REGSET from register cache REGCACHE into the buffer specified by
657 GREGS and LEN. If REGNUM is -1, do this for all registers in
661 ppc_collect_gregset (const struct regset *regset,
662 const struct regcache *regcache,
663 int regnum, void *gregs, size_t len)
665 struct gdbarch *gdbarch = get_regcache_arch (regcache);
666 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
667 const struct ppc_reg_offsets *offsets = regset->descr;
674 int gpr_size = offsets->gpr_size;
676 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
677 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
678 i++, offset += gpr_size)
679 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
681 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
682 gregs, offsets->pc_offset, gpr_size);
683 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
684 gregs, offsets->ps_offset, gpr_size);
685 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
686 gregs, offsets->lr_offset, gpr_size);
687 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
688 gregs, offsets->ctr_offset, gpr_size);
689 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
690 gregs, offsets->cr_offset, offsets->xr_size);
691 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
692 gregs, offsets->xer_offset, offsets->xr_size);
693 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
694 gregs, offsets->mq_offset, offsets->xr_size);
698 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
699 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
702 /* Collect register REGNUM in the floating-point register set
703 REGSET from register cache REGCACHE into the buffer specified by
704 FPREGS and LEN. If REGNUM is -1, do this for all registers in
708 ppc_collect_fpregset (const struct regset *regset,
709 const struct regcache *regcache,
710 int regnum, void *fpregs, size_t len)
712 struct gdbarch *gdbarch = get_regcache_arch (regcache);
713 struct gdbarch_tdep *tdep;
714 const struct ppc_reg_offsets *offsets;
717 if (!ppc_floating_point_unit_p (gdbarch))
720 tdep = gdbarch_tdep (gdbarch);
721 offsets = regset->descr;
726 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
727 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
729 ppc_collect_reg (regcache, i, fpregs, offset, 8);
731 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
732 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
736 offset = ppc_fpreg_offset (tdep, offsets, regnum);
737 ppc_collect_reg (regcache, regnum, fpregs, offset,
738 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
741 /* Collect register REGNUM in the VSX register set
742 REGSET from register cache REGCACHE into the buffer specified by
743 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
747 ppc_collect_vsxregset (const struct regset *regset,
748 const struct regcache *regcache,
749 int regnum, void *vsxregs, size_t len)
751 struct gdbarch *gdbarch = get_regcache_arch (regcache);
752 struct gdbarch_tdep *tdep;
754 if (!ppc_vsx_support_p (gdbarch))
757 tdep = gdbarch_tdep (gdbarch);
763 for (i = tdep->ppc_vsr0_upper_regnum;
764 i < tdep->ppc_vsr0_upper_regnum + 32;
766 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
771 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
775 /* Collect register REGNUM in the Altivec register set
776 REGSET from register cache REGCACHE into the buffer specified by
777 VRREGS and LEN. If REGNUM is -1, do this for all registers in
781 ppc_collect_vrregset (const struct regset *regset,
782 const struct regcache *regcache,
783 int regnum, void *vrregs, size_t len)
785 struct gdbarch *gdbarch = get_regcache_arch (regcache);
786 struct gdbarch_tdep *tdep;
787 const struct ppc_reg_offsets *offsets;
790 if (!ppc_altivec_support_p (gdbarch))
793 tdep = gdbarch_tdep (gdbarch);
794 offsets = regset->descr;
799 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
800 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
802 ppc_collect_reg (regcache, i, vrregs, offset, 16);
804 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
805 vrregs, offsets->vscr_offset, 4);
807 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
808 vrregs, offsets->vrsave_offset, 4);
812 offset = ppc_vrreg_offset (tdep, offsets, regnum);
813 if (regnum != tdep->ppc_vrsave_regnum
814 && regnum != tdep->ppc_vrsave_regnum - 1)
815 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
817 ppc_collect_reg (regcache, regnum,
823 insn_changes_sp_or_jumps (unsigned long insn)
825 int opcode = (insn >> 26) & 0x03f;
826 int sd = (insn >> 21) & 0x01f;
827 int a = (insn >> 16) & 0x01f;
828 int subcode = (insn >> 1) & 0x3ff;
830 /* Changes the stack pointer. */
832 /* NOTE: There are many ways to change the value of a given register.
833 The ways below are those used when the register is R1, the SP,
834 in a funtion's epilogue. */
836 if (opcode == 31 && subcode == 444 && a == 1)
837 return 1; /* mr R1,Rn */
838 if (opcode == 14 && sd == 1)
839 return 1; /* addi R1,Rn,simm */
840 if (opcode == 58 && sd == 1)
841 return 1; /* ld R1,ds(Rn) */
843 /* Transfers control. */
849 if (opcode == 19 && subcode == 16)
851 if (opcode == 19 && subcode == 528)
852 return 1; /* bcctr */
857 /* Return true if we are in the function's epilogue, i.e. after the
858 instruction that destroyed the function's stack frame.
860 1) scan forward from the point of execution:
861 a) If you find an instruction that modifies the stack pointer
862 or transfers control (except a return), execution is not in
864 b) Stop scanning if you find a return instruction or reach the
865 end of the function or reach the hard limit for the size of
867 2) scan backward from the point of execution:
868 a) If you find an instruction that modifies the stack pointer,
869 execution *is* in an epilogue, return.
870 b) Stop scanning if you reach an instruction that transfers
871 control or the beginning of the function or reach the hard
872 limit for the size of an epilogue. */
875 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
877 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
878 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
879 bfd_byte insn_buf[PPC_INSN_SIZE];
880 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
882 struct frame_info *curfrm;
884 /* Find the search limits based on function boundaries and hard limit. */
886 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
889 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
890 if (epilogue_start < func_start) epilogue_start = func_start;
892 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
893 if (epilogue_end > func_end) epilogue_end = func_end;
895 curfrm = get_current_frame ();
897 /* Scan forward until next 'blr'. */
899 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
901 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
903 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
904 if (insn == 0x4e800020)
906 /* Assume a bctr is a tail call unless it points strictly within
908 if (insn == 0x4e800420)
910 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
911 tdep->ppc_ctr_regnum);
912 if (ctr > func_start && ctr < func_end)
917 if (insn_changes_sp_or_jumps (insn))
921 /* Scan backward until adjustment to stack pointer (R1). */
923 for (scan_pc = pc - PPC_INSN_SIZE;
924 scan_pc >= epilogue_start;
925 scan_pc -= PPC_INSN_SIZE)
927 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
929 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
930 if (insn_changes_sp_or_jumps (insn))
937 /* Get the ith function argument for the current function. */
939 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
942 return get_frame_register_unsigned (frame, 3 + argi);
945 /* Sequence of bytes for breakpoint instruction. */
947 const static unsigned char *
948 rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
951 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
952 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
954 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
955 return big_breakpoint;
957 return little_breakpoint;
960 /* Instruction masks for displaced stepping. */
961 #define BRANCH_MASK 0xfc000000
962 #define BP_MASK 0xFC0007FE
963 #define B_INSN 0x48000000
964 #define BC_INSN 0x40000000
965 #define BXL_INSN 0x4c000000
966 #define BP_INSN 0x7C000008
968 /* Fix up the state of registers and memory after having single-stepped
969 a displaced instruction. */
971 ppc_displaced_step_fixup (struct gdbarch *gdbarch,
972 struct displaced_step_closure *closure,
973 CORE_ADDR from, CORE_ADDR to,
974 struct regcache *regs)
976 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
977 /* Since we use simple_displaced_step_copy_insn, our closure is a
978 copy of the instruction. */
979 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
980 PPC_INSN_SIZE, byte_order);
982 /* Offset for non PC-relative instructions. */
983 LONGEST offset = PPC_INSN_SIZE;
985 opcode = insn & BRANCH_MASK;
988 fprintf_unfiltered (gdb_stdlog,
989 "displaced: (ppc) fixup (%s, %s)\n",
990 paddress (gdbarch, from), paddress (gdbarch, to));
993 /* Handle PC-relative branch instructions. */
994 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
998 /* Read the current PC value after the instruction has been executed
999 in a displaced location. Calculate the offset to be applied to the
1000 original PC value before the displaced stepping. */
1001 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1003 offset = current_pc - to;
1005 if (opcode != BXL_INSN)
1007 /* Check for AA bit indicating whether this is an absolute
1008 addressing or PC-relative (1: absolute, 0: relative). */
1011 /* PC-relative addressing is being used in the branch. */
1012 if (debug_displaced)
1015 "displaced: (ppc) branch instruction: %s\n"
1016 "displaced: (ppc) adjusted PC from %s to %s\n",
1017 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1018 paddress (gdbarch, from + offset));
1020 regcache_cooked_write_unsigned (regs,
1021 gdbarch_pc_regnum (gdbarch),
1027 /* If we're here, it means we have a branch to LR or CTR. If the
1028 branch was taken, the offset is probably greater than 4 (the next
1029 instruction), so it's safe to assume that an offset of 4 means we
1030 did not take the branch. */
1031 if (offset == PPC_INSN_SIZE)
1032 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1033 from + PPC_INSN_SIZE);
1036 /* Check for LK bit indicating whether we should set the link
1037 register to point to the next instruction
1038 (1: Set, 0: Don't set). */
1041 /* Link register needs to be set to the next instruction's PC. */
1042 regcache_cooked_write_unsigned (regs,
1043 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1044 from + PPC_INSN_SIZE);
1045 if (debug_displaced)
1046 fprintf_unfiltered (gdb_stdlog,
1047 "displaced: (ppc) adjusted LR to %s\n",
1048 paddress (gdbarch, from + PPC_INSN_SIZE));
1052 /* Check for breakpoints in the inferior. If we've found one, place the PC
1053 right at the breakpoint instruction. */
1054 else if ((insn & BP_MASK) == BP_INSN)
1055 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1057 /* Handle any other instructions that do not fit in the categories above. */
1058 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1062 /* Always use hardware single-stepping to execute the
1063 displaced instruction. */
1065 ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1066 struct displaced_step_closure *closure)
1071 /* Instruction masks used during single-stepping of atomic sequences. */
1072 #define LWARX_MASK 0xfc0007fe
1073 #define LWARX_INSTRUCTION 0x7c000028
1074 #define LDARX_INSTRUCTION 0x7c0000A8
1075 #define STWCX_MASK 0xfc0007ff
1076 #define STWCX_INSTRUCTION 0x7c00012d
1077 #define STDCX_INSTRUCTION 0x7c0001ad
1079 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1080 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1081 is found, attempt to step through it. A breakpoint is placed at the end of
1085 ppc_deal_with_atomic_sequence (struct frame_info *frame)
1087 struct gdbarch *gdbarch = get_frame_arch (frame);
1088 struct address_space *aspace = get_frame_address_space (frame);
1089 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1090 CORE_ADDR pc = get_frame_pc (frame);
1091 CORE_ADDR breaks[2] = {-1, -1};
1093 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
1094 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1097 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1098 const int atomic_sequence_length = 16; /* Instruction sequence length. */
1099 int opcode; /* Branch instruction's OPcode. */
1100 int bc_insn_count = 0; /* Conditional branch instruction count. */
1102 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1103 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1104 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1107 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1109 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1111 loc += PPC_INSN_SIZE;
1112 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1114 /* Assume that there is at most one conditional branch in the atomic
1115 sequence. If a conditional branch is found, put a breakpoint in
1116 its destination address. */
1117 if ((insn & BRANCH_MASK) == BC_INSN)
1119 int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1120 int absolute = insn & 2;
1122 if (bc_insn_count >= 1)
1123 return 0; /* More than one conditional branch found, fallback
1124 to the standard single-step code. */
1127 breaks[1] = immediate;
1129 breaks[1] = loc + immediate;
1135 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1136 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1140 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1141 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1142 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1146 loc += PPC_INSN_SIZE;
1147 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1149 /* Insert a breakpoint right after the end of the atomic sequence. */
1152 /* Check for duplicated breakpoints. Check also for a breakpoint
1153 placed (branch instruction's destination) anywhere in sequence. */
1155 && (breaks[1] == breaks[0]
1156 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
1157 last_breakpoint = 0;
1159 /* Effectively inserts the breakpoints. */
1160 for (index = 0; index <= last_breakpoint; index++)
1161 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
1167 #define SIGNED_SHORT(x) \
1168 ((sizeof (short) == 2) \
1169 ? ((int)(short)(x)) \
1170 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1172 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1174 /* Limit the number of skipped non-prologue instructions, as the examining
1175 of the prologue is expensive. */
1176 static int max_skip_non_prologue_insns = 10;
1178 /* Return nonzero if the given instruction OP can be part of the prologue
1179 of a function and saves a parameter on the stack. FRAMEP should be
1180 set if one of the previous instructions in the function has set the
1184 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1186 /* Move parameters from argument registers to temporary register. */
1187 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1189 /* Rx must be scratch register r0. */
1190 const int rx_regno = (op >> 16) & 31;
1191 /* Ry: Only r3 - r10 are used for parameter passing. */
1192 const int ry_regno = GET_SRC_REG (op);
1194 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1196 *r0_contains_arg = 1;
1203 /* Save a General Purpose Register on stack. */
1205 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1206 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1208 /* Rx: Only r3 - r10 are used for parameter passing. */
1209 const int rx_regno = GET_SRC_REG (op);
1211 return (rx_regno >= 3 && rx_regno <= 10);
1214 /* Save a General Purpose Register on stack via the Frame Pointer. */
1217 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1218 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1219 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1221 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1222 However, the compiler sometimes uses r0 to hold an argument. */
1223 const int rx_regno = GET_SRC_REG (op);
1225 return ((rx_regno >= 3 && rx_regno <= 10)
1226 || (rx_regno == 0 && *r0_contains_arg));
1229 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1231 /* Only f2 - f8 are used for parameter passing. */
1232 const int src_regno = GET_SRC_REG (op);
1234 return (src_regno >= 2 && src_regno <= 8);
1237 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1239 /* Only f2 - f8 are used for parameter passing. */
1240 const int src_regno = GET_SRC_REG (op);
1242 return (src_regno >= 2 && src_regno <= 8);
1245 /* Not an insn that saves a parameter on stack. */
1249 /* Assuming that INSN is a "bl" instruction located at PC, return
1250 nonzero if the destination of the branch is a "blrl" instruction.
1252 This sequence is sometimes found in certain function prologues.
1253 It allows the function to load the LR register with a value that
1254 they can use to access PIC data using PC-relative offsets. */
1257 bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
1264 absolute = (int) ((insn >> 1) & 1);
1265 immediate = ((insn & ~3) << 6) >> 6;
1269 dest = pc + immediate;
1271 dest_insn = read_memory_integer (dest, 4, byte_order);
1272 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1278 /* Masks for decoding a branch-and-link (bl) instruction.
1280 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1281 The former is anded with the opcode in question; if the result of
1282 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1283 question is a ``bl'' instruction.
1285 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1286 the branch displacement. */
1288 #define BL_MASK 0xfc000001
1289 #define BL_INSTRUCTION 0x48000001
1290 #define BL_DISPLACEMENT_MASK 0x03fffffc
1292 static unsigned long
1293 rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
1295 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1299 /* Fetch the instruction and convert it to an integer. */
1300 if (target_read_memory (pc, buf, 4))
1302 op = extract_unsigned_integer (buf, 4, byte_order);
1307 /* GCC generates several well-known sequences of instructions at the begining
1308 of each function prologue when compiling with -fstack-check. If one of
1309 such sequences starts at START_PC, then return the address of the
1310 instruction immediately past this sequence. Otherwise, return START_PC. */
1313 rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
1315 CORE_ADDR pc = start_pc;
1316 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
1318 /* First possible sequence: A small number of probes.
1319 stw 0, -<some immediate>(1)
1320 [repeat this instruction any (small) number of times]. */
1322 if ((op & 0xffff0000) == 0x90010000)
1324 while ((op & 0xffff0000) == 0x90010000)
1327 op = rs6000_fetch_instruction (gdbarch, pc);
1332 /* Second sequence: A probing loop.
1333 addi 12,1,-<some immediate>
1334 lis 0,-<some immediate>
1335 [possibly ori 0,0,<some immediate>]
1339 addi 12,12,-<some immediate>
1342 [possibly one last probe: stw 0,<some immediate>(12)]. */
1346 /* addi 12,1,-<some immediate> */
1347 if ((op & 0xffff0000) != 0x39810000)
1350 /* lis 0,-<some immediate> */
1352 op = rs6000_fetch_instruction (gdbarch, pc);
1353 if ((op & 0xffff0000) != 0x3c000000)
1357 op = rs6000_fetch_instruction (gdbarch, pc);
1358 /* [possibly ori 0,0,<some immediate>] */
1359 if ((op & 0xffff0000) == 0x60000000)
1362 op = rs6000_fetch_instruction (gdbarch, pc);
1365 if (op != 0x7c0c0214)
1370 op = rs6000_fetch_instruction (gdbarch, pc);
1371 if (op != 0x7c0c0000)
1376 op = rs6000_fetch_instruction (gdbarch, pc);
1377 if ((op & 0xff9f0001) != 0x41820000)
1380 /* addi 12,12,-<some immediate> */
1382 op = rs6000_fetch_instruction (gdbarch, pc);
1383 if ((op & 0xffff0000) != 0x398c0000)
1388 op = rs6000_fetch_instruction (gdbarch, pc);
1389 if (op != 0x900c0000)
1394 op = rs6000_fetch_instruction (gdbarch, pc);
1395 if ((op & 0xfc000001) != 0x48000000)
1398 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1400 op = rs6000_fetch_instruction (gdbarch, pc);
1401 if ((op & 0xffff0000) == 0x900c0000)
1404 op = rs6000_fetch_instruction (gdbarch, pc);
1407 /* We found a valid stack-check sequence, return the new PC. */
1411 /* Third sequence: No probe; instead, a comparizon between the stack size
1412 limit (saved in a run-time global variable) and the current stack
1415 addi 0,1,-<some immediate>
1416 lis 12,__gnat_stack_limit@ha
1417 lwz 12,__gnat_stack_limit@l(12)
1420 or, with a small variant in the case of a bigger stack frame:
1421 addis 0,1,<some immediate>
1422 addic 0,0,-<some immediate>
1423 lis 12,__gnat_stack_limit@ha
1424 lwz 12,__gnat_stack_limit@l(12)
1429 /* addi 0,1,-<some immediate> */
1430 if ((op & 0xffff0000) != 0x38010000)
1432 /* small stack frame variant not recognized; try the
1433 big stack frame variant: */
1435 /* addis 0,1,<some immediate> */
1436 if ((op & 0xffff0000) != 0x3c010000)
1439 /* addic 0,0,-<some immediate> */
1441 op = rs6000_fetch_instruction (gdbarch, pc);
1442 if ((op & 0xffff0000) != 0x30000000)
1446 /* lis 12,<some immediate> */
1448 op = rs6000_fetch_instruction (gdbarch, pc);
1449 if ((op & 0xffff0000) != 0x3d800000)
1452 /* lwz 12,<some immediate>(12) */
1454 op = rs6000_fetch_instruction (gdbarch, pc);
1455 if ((op & 0xffff0000) != 0x818c0000)
1460 op = rs6000_fetch_instruction (gdbarch, pc);
1461 if ((op & 0xfffffffe) != 0x7c406008)
1464 /* We found a valid stack-check sequence, return the new PC. */
1468 /* No stack check code in our prologue, return the start_pc. */
1472 /* return pc value after skipping a function prologue and also return
1473 information about a function frame.
1475 in struct rs6000_framedata fdata:
1476 - frameless is TRUE, if function does not have a frame.
1477 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1478 - offset is the initial size of this stack frame --- the amount by
1479 which we decrement the sp to allocate the frame.
1480 - saved_gpr is the number of the first saved gpr.
1481 - saved_fpr is the number of the first saved fpr.
1482 - saved_vr is the number of the first saved vr.
1483 - saved_ev is the number of the first saved ev.
1484 - alloca_reg is the number of the register used for alloca() handling.
1486 - gpr_offset is the offset of the first saved gpr from the previous frame.
1487 - fpr_offset is the offset of the first saved fpr from the previous frame.
1488 - vr_offset is the offset of the first saved vr from the previous frame.
1489 - ev_offset is the offset of the first saved ev from the previous frame.
1490 - lr_offset is the offset of the saved lr
1491 - cr_offset is the offset of the saved cr
1492 - vrsave_offset is the offset of the saved vrsave register. */
1495 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1496 struct rs6000_framedata *fdata)
1498 CORE_ADDR orig_pc = pc;
1499 CORE_ADDR last_prologue_pc = pc;
1500 CORE_ADDR li_found_pc = 0;
1504 long vr_saved_offset = 0;
1510 int vrsave_reg = -1;
1513 int minimal_toc_loaded = 0;
1514 int prev_insn_was_prologue_insn = 1;
1515 int num_skip_non_prologue_insns = 0;
1516 int r0_contains_arg = 0;
1517 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1518 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1519 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1521 memset (fdata, 0, sizeof (struct rs6000_framedata));
1522 fdata->saved_gpr = -1;
1523 fdata->saved_fpr = -1;
1524 fdata->saved_vr = -1;
1525 fdata->saved_ev = -1;
1526 fdata->alloca_reg = -1;
1527 fdata->frameless = 1;
1528 fdata->nosavedpc = 1;
1529 fdata->lr_register = -1;
1531 pc = rs6000_skip_stack_check (gdbarch, pc);
1537 /* Sometimes it isn't clear if an instruction is a prologue
1538 instruction or not. When we encounter one of these ambiguous
1539 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1540 Otherwise, we'll assume that it really is a prologue instruction. */
1541 if (prev_insn_was_prologue_insn)
1542 last_prologue_pc = pc;
1544 /* Stop scanning if we've hit the limit. */
1548 prev_insn_was_prologue_insn = 1;
1550 /* Fetch the instruction and convert it to an integer. */
1551 if (target_read_memory (pc, buf, 4))
1553 op = extract_unsigned_integer (buf, 4, byte_order);
1555 if ((op & 0xfc1fffff) == 0x7c0802a6)
1557 /* Since shared library / PIC code, which needs to get its
1558 address at runtime, can appear to save more than one link
1572 remember just the first one, but skip over additional
1575 lr_reg = (op & 0x03e00000) >> 21;
1577 r0_contains_arg = 0;
1580 else if ((op & 0xfc1fffff) == 0x7c000026)
1582 cr_reg = (op & 0x03e00000);
1584 r0_contains_arg = 0;
1588 else if ((op & 0xfc1f0000) == 0xd8010000)
1589 { /* stfd Rx,NUM(r1) */
1590 reg = GET_SRC_REG (op);
1591 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1593 fdata->saved_fpr = reg;
1594 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1599 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1600 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1601 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1602 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1605 reg = GET_SRC_REG (op);
1606 if ((op & 0xfc1f0000) == 0xbc010000)
1607 fdata->gpr_mask |= ~((1U << reg) - 1);
1609 fdata->gpr_mask |= 1U << reg;
1610 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1612 fdata->saved_gpr = reg;
1613 if ((op & 0xfc1f0003) == 0xf8010000)
1615 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1620 else if ((op & 0xffff0000) == 0x60000000)
1623 /* Allow nops in the prologue, but do not consider them to
1624 be part of the prologue unless followed by other prologue
1626 prev_insn_was_prologue_insn = 0;
1630 else if ((op & 0xffff0000) == 0x3c000000)
1631 { /* addis 0,0,NUM, used
1632 for >= 32k frames */
1633 fdata->offset = (op & 0x0000ffff) << 16;
1634 fdata->frameless = 0;
1635 r0_contains_arg = 0;
1639 else if ((op & 0xffff0000) == 0x60000000)
1640 { /* ori 0,0,NUM, 2nd ha
1641 lf of >= 32k frames */
1642 fdata->offset |= (op & 0x0000ffff);
1643 fdata->frameless = 0;
1644 r0_contains_arg = 0;
1648 else if (lr_reg >= 0 &&
1649 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1650 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1651 /* stw Rx, NUM(r1) */
1652 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1653 /* stwu Rx, NUM(r1) */
1654 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1655 { /* where Rx == lr */
1656 fdata->lr_offset = offset;
1657 fdata->nosavedpc = 0;
1658 /* Invalidate lr_reg, but don't set it to -1.
1659 That would mean that it had never been set. */
1661 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1662 (op & 0xfc000000) == 0x90000000) /* stw */
1664 /* Does not update r1, so add displacement to lr_offset. */
1665 fdata->lr_offset += SIGNED_SHORT (op);
1670 else if (cr_reg >= 0 &&
1671 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1672 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1673 /* stw Rx, NUM(r1) */
1674 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1675 /* stwu Rx, NUM(r1) */
1676 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1677 { /* where Rx == cr */
1678 fdata->cr_offset = offset;
1679 /* Invalidate cr_reg, but don't set it to -1.
1680 That would mean that it had never been set. */
1682 if ((op & 0xfc000003) == 0xf8000000 ||
1683 (op & 0xfc000000) == 0x90000000)
1685 /* Does not update r1, so add displacement to cr_offset. */
1686 fdata->cr_offset += SIGNED_SHORT (op);
1691 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1693 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1694 prediction bits. If the LR has already been saved, we can
1698 else if (op == 0x48000005)
1705 else if (op == 0x48000004)
1710 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1711 in V.4 -mminimal-toc */
1712 (op & 0xffff0000) == 0x3bde0000)
1713 { /* addi 30,30,foo@l */
1717 else if ((op & 0xfc000001) == 0x48000001)
1721 fdata->frameless = 0;
1723 /* If the return address has already been saved, we can skip
1724 calls to blrl (for PIC). */
1725 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
1731 /* Don't skip over the subroutine call if it is not within
1732 the first three instructions of the prologue and either
1733 we have no line table information or the line info tells
1734 us that the subroutine call is not part of the line
1735 associated with the prologue. */
1736 if ((pc - orig_pc) > 8)
1738 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1739 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1741 if ((prologue_sal.line == 0)
1742 || (prologue_sal.line != this_sal.line))
1746 op = read_memory_integer (pc + 4, 4, byte_order);
1748 /* At this point, make sure this is not a trampoline
1749 function (a function that simply calls another functions,
1750 and nothing else). If the next is not a nop, this branch
1751 was part of the function prologue. */
1753 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1754 break; /* Don't skip over
1760 /* update stack pointer */
1761 else if ((op & 0xfc1f0000) == 0x94010000)
1762 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1763 fdata->frameless = 0;
1764 fdata->offset = SIGNED_SHORT (op);
1765 offset = fdata->offset;
1768 else if ((op & 0xfc1f016a) == 0x7c01016e)
1769 { /* stwux rX,r1,rY */
1770 /* No way to figure out what r1 is going to be. */
1771 fdata->frameless = 0;
1772 offset = fdata->offset;
1775 else if ((op & 0xfc1f0003) == 0xf8010001)
1776 { /* stdu rX,NUM(r1) */
1777 fdata->frameless = 0;
1778 fdata->offset = SIGNED_SHORT (op & ~3UL);
1779 offset = fdata->offset;
1782 else if ((op & 0xfc1f016a) == 0x7c01016a)
1783 { /* stdux rX,r1,rY */
1784 /* No way to figure out what r1 is going to be. */
1785 fdata->frameless = 0;
1786 offset = fdata->offset;
1789 else if ((op & 0xffff0000) == 0x38210000)
1790 { /* addi r1,r1,SIMM */
1791 fdata->frameless = 0;
1792 fdata->offset += SIGNED_SHORT (op);
1793 offset = fdata->offset;
1796 /* Load up minimal toc pointer. Do not treat an epilogue restore
1797 of r31 as a minimal TOC load. */
1798 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1799 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1801 && !minimal_toc_loaded)
1803 minimal_toc_loaded = 1;
1806 /* move parameters from argument registers to local variable
1809 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1810 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1811 (((op >> 21) & 31) <= 10) &&
1812 ((long) ((op >> 16) & 31)
1813 >= fdata->saved_gpr)) /* Rx: local var reg */
1817 /* store parameters in stack */
1819 /* Move parameters from argument registers to temporary register. */
1820 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1824 /* Set up frame pointer */
1826 else if (op == 0x603d0000) /* oril r29, r1, 0x0 */
1828 fdata->frameless = 0;
1830 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29);
1833 /* Another way to set up the frame pointer. */
1835 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1836 || op == 0x7c3f0b78)
1838 fdata->frameless = 0;
1840 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1843 /* Another way to set up the frame pointer. */
1845 else if ((op & 0xfc1fffff) == 0x38010000)
1846 { /* addi rX, r1, 0x0 */
1847 fdata->frameless = 0;
1849 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1850 + ((op & ~0x38010000) >> 21));
1853 /* AltiVec related instructions. */
1854 /* Store the vrsave register (spr 256) in another register for
1855 later manipulation, or load a register into the vrsave
1856 register. 2 instructions are used: mfvrsave and
1857 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1858 and mtspr SPR256, Rn. */
1859 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1860 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1861 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1863 vrsave_reg = GET_SRC_REG (op);
1866 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1870 /* Store the register where vrsave was saved to onto the stack:
1871 rS is the register where vrsave was stored in a previous
1873 /* 100100 sssss 00001 dddddddd dddddddd */
1874 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1876 if (vrsave_reg == GET_SRC_REG (op))
1878 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1883 /* Compute the new value of vrsave, by modifying the register
1884 where vrsave was saved to. */
1885 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1886 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1890 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1891 in a pair of insns to save the vector registers on the
1893 /* 001110 00000 00000 iiii iiii iiii iiii */
1894 /* 001110 01110 00000 iiii iiii iiii iiii */
1895 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1896 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1898 if ((op & 0xffff0000) == 0x38000000)
1899 r0_contains_arg = 0;
1901 vr_saved_offset = SIGNED_SHORT (op);
1903 /* This insn by itself is not part of the prologue, unless
1904 if part of the pair of insns mentioned above. So do not
1905 record this insn as part of the prologue yet. */
1906 prev_insn_was_prologue_insn = 0;
1908 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1909 /* 011111 sssss 11111 00000 00111001110 */
1910 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1912 if (pc == (li_found_pc + 4))
1914 vr_reg = GET_SRC_REG (op);
1915 /* If this is the first vector reg to be saved, or if
1916 it has a lower number than others previously seen,
1917 reupdate the frame info. */
1918 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1920 fdata->saved_vr = vr_reg;
1921 fdata->vr_offset = vr_saved_offset + offset;
1923 vr_saved_offset = -1;
1928 /* End AltiVec related instructions. */
1930 /* Start BookE related instructions. */
1931 /* Store gen register S at (r31+uimm).
1932 Any register less than r13 is volatile, so we don't care. */
1933 /* 000100 sssss 11111 iiiii 01100100001 */
1934 else if (arch_info->mach == bfd_mach_ppc_e500
1935 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1937 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1940 ev_reg = GET_SRC_REG (op);
1941 imm = (op >> 11) & 0x1f;
1942 ev_offset = imm * 8;
1943 /* If this is the first vector reg to be saved, or if
1944 it has a lower number than others previously seen,
1945 reupdate the frame info. */
1946 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1948 fdata->saved_ev = ev_reg;
1949 fdata->ev_offset = ev_offset + offset;
1954 /* Store gen register rS at (r1+rB). */
1955 /* 000100 sssss 00001 bbbbb 01100100000 */
1956 else if (arch_info->mach == bfd_mach_ppc_e500
1957 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1959 if (pc == (li_found_pc + 4))
1961 ev_reg = GET_SRC_REG (op);
1962 /* If this is the first vector reg to be saved, or if
1963 it has a lower number than others previously seen,
1964 reupdate the frame info. */
1965 /* We know the contents of rB from the previous instruction. */
1966 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1968 fdata->saved_ev = ev_reg;
1969 fdata->ev_offset = vr_saved_offset + offset;
1971 vr_saved_offset = -1;
1977 /* Store gen register r31 at (rA+uimm). */
1978 /* 000100 11111 aaaaa iiiii 01100100001 */
1979 else if (arch_info->mach == bfd_mach_ppc_e500
1980 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1982 /* Wwe know that the source register is 31 already, but
1983 it can't hurt to compute it. */
1984 ev_reg = GET_SRC_REG (op);
1985 ev_offset = ((op >> 11) & 0x1f) * 8;
1986 /* If this is the first vector reg to be saved, or if
1987 it has a lower number than others previously seen,
1988 reupdate the frame info. */
1989 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1991 fdata->saved_ev = ev_reg;
1992 fdata->ev_offset = ev_offset + offset;
1997 /* Store gen register S at (r31+r0).
1998 Store param on stack when offset from SP bigger than 4 bytes. */
1999 /* 000100 sssss 11111 00000 01100100000 */
2000 else if (arch_info->mach == bfd_mach_ppc_e500
2001 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2003 if (pc == (li_found_pc + 4))
2005 if ((op & 0x03e00000) >= 0x01a00000)
2007 ev_reg = GET_SRC_REG (op);
2008 /* If this is the first vector reg to be saved, or if
2009 it has a lower number than others previously seen,
2010 reupdate the frame info. */
2011 /* We know the contents of r0 from the previous
2013 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2015 fdata->saved_ev = ev_reg;
2016 fdata->ev_offset = vr_saved_offset + offset;
2020 vr_saved_offset = -1;
2025 /* End BookE related instructions. */
2029 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2031 /* Not a recognized prologue instruction.
2032 Handle optimizer code motions into the prologue by continuing
2033 the search if we have no valid frame yet or if the return
2034 address is not yet saved in the frame. Also skip instructions
2035 if some of the GPRs expected to be saved are not yet saved. */
2036 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2037 && (fdata->gpr_mask & all_mask) == all_mask)
2040 if (op == 0x4e800020 /* blr */
2041 || op == 0x4e800420) /* bctr */
2042 /* Do not scan past epilogue in frameless functions or
2045 if ((op & 0xf4000000) == 0x40000000) /* bxx */
2046 /* Never skip branches. */
2049 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2050 /* Do not scan too many insns, scanning insns is expensive with
2054 /* Continue scanning. */
2055 prev_insn_was_prologue_insn = 0;
2061 /* I have problems with skipping over __main() that I need to address
2062 * sometime. Previously, I used to use misc_function_vector which
2063 * didn't work as well as I wanted to be. -MGO */
2065 /* If the first thing after skipping a prolog is a branch to a function,
2066 this might be a call to an initializer in main(), introduced by gcc2.
2067 We'd like to skip over it as well. Fortunately, xlc does some extra
2068 work before calling a function right after a prologue, thus we can
2069 single out such gcc2 behaviour. */
2072 if ((op & 0xfc000001) == 0x48000001)
2073 { /* bl foo, an initializer function? */
2074 op = read_memory_integer (pc + 4, 4, byte_order);
2076 if (op == 0x4def7b82)
2077 { /* cror 0xf, 0xf, 0xf (nop) */
2079 /* Check and see if we are in main. If so, skip over this
2080 initializer function as well. */
2082 tmp = find_pc_misc_function (pc);
2084 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
2090 if (pc == lim_pc && lr_reg >= 0)
2091 fdata->lr_register = lr_reg;
2093 fdata->offset = -fdata->offset;
2094 return last_prologue_pc;
2098 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2100 struct rs6000_framedata frame;
2101 CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
2103 /* See if we can determine the end of the prologue via the symbol table.
2104 If so, then return either PC, or the PC after the prologue, whichever
2106 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
2108 CORE_ADDR post_prologue_pc
2109 = skip_prologue_using_sal (gdbarch, func_addr);
2110 if (post_prologue_pc != 0)
2111 return max (pc, post_prologue_pc);
2114 /* Can't determine prologue from the symbol table, need to examine
2117 /* Find an upper limit on the function prologue using the debug
2118 information. If the debug information could not be used to provide
2119 that bound, then use an arbitrary large number as the upper bound. */
2120 limit_pc = skip_prologue_using_sal (gdbarch, pc);
2122 limit_pc = pc + 100; /* Magic. */
2124 /* Do not allow limit_pc to be past the function end, if we know
2125 where that end is... */
2126 if (func_end_addr && limit_pc > func_end_addr)
2127 limit_pc = func_end_addr;
2129 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2133 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2134 in the prologue of main().
2136 The function below examines the code pointed at by PC and checks to
2137 see if it corresponds to a call to __eabi. If so, it returns the
2138 address of the instruction following that call. Otherwise, it simply
2142 rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2144 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2148 if (target_read_memory (pc, buf, 4))
2150 op = extract_unsigned_integer (buf, 4, byte_order);
2152 if ((op & BL_MASK) == BL_INSTRUCTION)
2154 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2155 CORE_ADDR call_dest = pc + 4 + displ;
2156 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2158 /* We check for ___eabi (three leading underscores) in addition
2159 to __eabi in case the GCC option "-fleading-underscore" was
2160 used to compile the program. */
2162 && SYMBOL_LINKAGE_NAME (s) != NULL
2163 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2164 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2170 /* All the ABI's require 16 byte alignment. */
2172 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2174 return (addr & -16);
2177 /* Return whether handle_inferior_event() should proceed through code
2178 starting at PC in function NAME when stepping.
2180 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2181 handle memory references that are too distant to fit in instructions
2182 generated by the compiler. For example, if 'foo' in the following
2187 is greater than 32767, the linker might replace the lwz with a branch to
2188 somewhere in @FIX1 that does the load in 2 instructions and then branches
2189 back to where execution should continue.
2191 GDB should silently step over @FIX code, just like AIX dbx does.
2192 Unfortunately, the linker uses the "b" instruction for the
2193 branches, meaning that the link register doesn't get set.
2194 Therefore, GDB's usual step_over_function () mechanism won't work.
2196 Instead, use the gdbarch_skip_trampoline_code and
2197 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2201 rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2202 CORE_ADDR pc, const char *name)
2204 return name && !strncmp (name, "@FIX", 4);
2207 /* Skip code that the user doesn't want to see when stepping:
2209 1. Indirect function calls use a piece of trampoline code to do context
2210 switching, i.e. to set the new TOC table. Skip such code if we are on
2211 its first instruction (as when we have single-stepped to here).
2213 2. Skip shared library trampoline code (which is different from
2214 indirect function call trampolines).
2216 3. Skip bigtoc fixup code.
2218 Result is desired PC to step until, or NULL if we are not in
2219 code that should be skipped. */
2222 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
2224 struct gdbarch *gdbarch = get_frame_arch (frame);
2225 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2226 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2227 unsigned int ii, op;
2229 CORE_ADDR solib_target_pc;
2230 struct minimal_symbol *msymbol;
2232 static unsigned trampoline_code[] =
2234 0x800b0000, /* l r0,0x0(r11) */
2235 0x90410014, /* st r2,0x14(r1) */
2236 0x7c0903a6, /* mtctr r0 */
2237 0x804b0004, /* l r2,0x4(r11) */
2238 0x816b0008, /* l r11,0x8(r11) */
2239 0x4e800420, /* bctr */
2240 0x4e800020, /* br */
2244 /* Check for bigtoc fixup code. */
2245 msymbol = lookup_minimal_symbol_by_pc (pc);
2247 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2248 SYMBOL_LINKAGE_NAME (msymbol)))
2250 /* Double-check that the third instruction from PC is relative "b". */
2251 op = read_memory_integer (pc + 8, 4, byte_order);
2252 if ((op & 0xfc000003) == 0x48000000)
2254 /* Extract bits 6-29 as a signed 24-bit relative word address and
2255 add it to the containing PC. */
2256 rel = ((int)(op << 6) >> 6);
2257 return pc + 8 + rel;
2261 /* If pc is in a shared library trampoline, return its target. */
2262 solib_target_pc = find_solib_trampoline_target (frame, pc);
2263 if (solib_target_pc)
2264 return solib_target_pc;
2266 for (ii = 0; trampoline_code[ii]; ++ii)
2268 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
2269 if (op != trampoline_code[ii])
2272 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
2274 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
2278 /* ISA-specific vector types. */
2280 static struct type *
2281 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2283 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2285 if (!tdep->ppc_builtin_type_vec64)
2287 const struct builtin_type *bt = builtin_type (gdbarch);
2289 /* The type we're building is this: */
2291 union __gdb_builtin_type_vec64
2295 int32_t v2_int32[2];
2296 int16_t v4_int16[4];
2303 t = arch_composite_type (gdbarch,
2304 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2305 append_composite_type_field (t, "uint64", bt->builtin_int64);
2306 append_composite_type_field (t, "v2_float",
2307 init_vector_type (bt->builtin_float, 2));
2308 append_composite_type_field (t, "v2_int32",
2309 init_vector_type (bt->builtin_int32, 2));
2310 append_composite_type_field (t, "v4_int16",
2311 init_vector_type (bt->builtin_int16, 4));
2312 append_composite_type_field (t, "v8_int8",
2313 init_vector_type (bt->builtin_int8, 8));
2315 TYPE_VECTOR (t) = 1;
2316 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2317 tdep->ppc_builtin_type_vec64 = t;
2320 return tdep->ppc_builtin_type_vec64;
2323 /* Vector 128 type. */
2325 static struct type *
2326 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2328 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2330 if (!tdep->ppc_builtin_type_vec128)
2332 const struct builtin_type *bt = builtin_type (gdbarch);
2334 /* The type we're building is this
2336 type = union __ppc_builtin_type_vec128 {
2338 double v2_double[2];
2340 int32_t v4_int32[4];
2341 int16_t v8_int16[8];
2342 int8_t v16_int8[16];
2348 t = arch_composite_type (gdbarch,
2349 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
2350 append_composite_type_field (t, "uint128", bt->builtin_uint128);
2351 append_composite_type_field (t, "v2_double",
2352 init_vector_type (bt->builtin_double, 2));
2353 append_composite_type_field (t, "v4_float",
2354 init_vector_type (bt->builtin_float, 4));
2355 append_composite_type_field (t, "v4_int32",
2356 init_vector_type (bt->builtin_int32, 4));
2357 append_composite_type_field (t, "v8_int16",
2358 init_vector_type (bt->builtin_int16, 8));
2359 append_composite_type_field (t, "v16_int8",
2360 init_vector_type (bt->builtin_int8, 16));
2362 TYPE_VECTOR (t) = 1;
2363 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2364 tdep->ppc_builtin_type_vec128 = t;
2367 return tdep->ppc_builtin_type_vec128;
2370 /* Return the name of register number REGNO, or the empty string if it
2371 is an anonymous register. */
2374 rs6000_register_name (struct gdbarch *gdbarch, int regno)
2376 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2378 /* The upper half "registers" have names in the XML description,
2379 but we present only the low GPRs and the full 64-bit registers
2381 if (tdep->ppc_ev0_upper_regnum >= 0
2382 && tdep->ppc_ev0_upper_regnum <= regno
2383 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2386 /* Hide the upper halves of the vs0~vs31 registers. */
2387 if (tdep->ppc_vsr0_regnum >= 0
2388 && tdep->ppc_vsr0_upper_regnum <= regno
2389 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2392 /* Check if the SPE pseudo registers are available. */
2393 if (IS_SPE_PSEUDOREG (tdep, regno))
2395 static const char *const spe_regnames[] = {
2396 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2397 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2398 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2399 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2401 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2404 /* Check if the decimal128 pseudo-registers are available. */
2405 if (IS_DFP_PSEUDOREG (tdep, regno))
2407 static const char *const dfp128_regnames[] = {
2408 "dl0", "dl1", "dl2", "dl3",
2409 "dl4", "dl5", "dl6", "dl7",
2410 "dl8", "dl9", "dl10", "dl11",
2411 "dl12", "dl13", "dl14", "dl15"
2413 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2416 /* Check if this is a VSX pseudo-register. */
2417 if (IS_VSX_PSEUDOREG (tdep, regno))
2419 static const char *const vsx_regnames[] = {
2420 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2421 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2422 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2423 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2424 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2425 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2426 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2427 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2428 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2430 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2433 /* Check if the this is a Extended FP pseudo-register. */
2434 if (IS_EFP_PSEUDOREG (tdep, regno))
2436 static const char *const efpr_regnames[] = {
2437 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2438 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2439 "f46", "f47", "f48", "f49", "f50", "f51",
2440 "f52", "f53", "f54", "f55", "f56", "f57",
2441 "f58", "f59", "f60", "f61", "f62", "f63"
2443 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2446 return tdesc_register_name (gdbarch, regno);
2449 /* Return the GDB type object for the "standard" data type of data in
2452 static struct type *
2453 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2455 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2457 /* These are the only pseudo-registers we support. */
2458 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2459 || IS_DFP_PSEUDOREG (tdep, regnum)
2460 || IS_VSX_PSEUDOREG (tdep, regnum)
2461 || IS_EFP_PSEUDOREG (tdep, regnum));
2463 /* These are the e500 pseudo-registers. */
2464 if (IS_SPE_PSEUDOREG (tdep, regnum))
2465 return rs6000_builtin_type_vec64 (gdbarch);
2466 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2467 /* PPC decimal128 pseudo-registers. */
2468 return builtin_type (gdbarch)->builtin_declong;
2469 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2470 /* POWER7 VSX pseudo-registers. */
2471 return rs6000_builtin_type_vec128 (gdbarch);
2473 /* POWER7 Extended FP pseudo-registers. */
2474 return builtin_type (gdbarch)->builtin_double;
2477 /* Is REGNUM a member of REGGROUP? */
2479 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2480 struct reggroup *group)
2482 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2484 /* These are the only pseudo-registers we support. */
2485 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2486 || IS_DFP_PSEUDOREG (tdep, regnum)
2487 || IS_VSX_PSEUDOREG (tdep, regnum)
2488 || IS_EFP_PSEUDOREG (tdep, regnum));
2490 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2491 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
2492 return group == all_reggroup || group == vector_reggroup;
2494 /* PPC decimal128 or Extended FP pseudo-registers. */
2495 return group == all_reggroup || group == float_reggroup;
2498 /* The register format for RS/6000 floating point registers is always
2499 double, we need a conversion if the memory format is float. */
2502 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2505 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2507 return (tdep->ppc_fp0_regnum >= 0
2508 && regnum >= tdep->ppc_fp0_regnum
2509 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2510 && TYPE_CODE (type) == TYPE_CODE_FLT
2511 && TYPE_LENGTH (type)
2512 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
2516 rs6000_register_to_value (struct frame_info *frame,
2520 int *optimizedp, int *unavailablep)
2522 struct gdbarch *gdbarch = get_frame_arch (frame);
2523 gdb_byte from[MAX_REGISTER_SIZE];
2525 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2527 if (!get_frame_register_bytes (frame, regnum, 0,
2528 register_size (gdbarch, regnum),
2529 from, optimizedp, unavailablep))
2532 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2534 *optimizedp = *unavailablep = 0;
2539 rs6000_value_to_register (struct frame_info *frame,
2542 const gdb_byte *from)
2544 struct gdbarch *gdbarch = get_frame_arch (frame);
2545 gdb_byte to[MAX_REGISTER_SIZE];
2547 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2549 convert_typed_floating (from, type,
2550 to, builtin_type (gdbarch)->builtin_double);
2551 put_frame_register (frame, regnum, to);
2554 /* The type of a function that moves the value of REG between CACHE
2555 or BUF --- in either direction. */
2556 typedef enum register_status (*move_ev_register_func) (struct regcache *,
2559 /* Move SPE vector register values between a 64-bit buffer and the two
2560 32-bit raw register halves in a regcache. This function handles
2561 both splitting a 64-bit value into two 32-bit halves, and joining
2562 two halves into a whole 64-bit value, depending on the function
2563 passed as the MOVE argument.
2565 EV_REG must be the number of an SPE evN vector register --- a
2566 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2569 Call MOVE once for each 32-bit half of that register, passing
2570 REGCACHE, the number of the raw register corresponding to that
2571 half, and the address of the appropriate half of BUFFER.
2573 For example, passing 'regcache_raw_read' as the MOVE function will
2574 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2575 'regcache_raw_supply' will supply the contents of BUFFER to the
2576 appropriate pair of raw registers in REGCACHE.
2578 You may need to cast away some 'const' qualifiers when passing
2579 MOVE, since this function can't tell at compile-time which of
2580 REGCACHE or BUFFER is acting as the source of the data. If C had
2581 co-variant type qualifiers, ... */
2583 static enum register_status
2584 e500_move_ev_register (move_ev_register_func move,
2585 struct regcache *regcache, int ev_reg, void *buffer)
2587 struct gdbarch *arch = get_regcache_arch (regcache);
2588 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2590 gdb_byte *byte_buffer = buffer;
2591 enum register_status status;
2593 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
2595 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2597 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2599 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2601 if (status == REG_VALID)
2602 status = move (regcache, tdep->ppc_gp0_regnum + reg_index,
2607 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2608 if (status == REG_VALID)
2609 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2616 static enum register_status
2617 do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer)
2619 return regcache_raw_read (regcache, regnum, buffer);
2622 static enum register_status
2623 do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer)
2625 regcache_raw_write (regcache, regnum, buffer);
2630 static enum register_status
2631 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2632 int reg_nr, gdb_byte *buffer)
2634 return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer);
2638 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2639 int reg_nr, const gdb_byte *buffer)
2641 e500_move_ev_register (do_regcache_raw_write, regcache,
2642 reg_nr, (void *) buffer);
2645 /* Read method for DFP pseudo-registers. */
2646 static enum register_status
2647 dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2648 int reg_nr, gdb_byte *buffer)
2650 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2651 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2652 enum register_status status;
2654 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2656 /* Read two FP registers to form a whole dl register. */
2657 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2658 2 * reg_index, buffer);
2659 if (status == REG_VALID)
2660 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2661 2 * reg_index + 1, buffer + 8);
2665 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2666 2 * reg_index + 1, buffer + 8);
2667 if (status == REG_VALID)
2668 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2669 2 * reg_index, buffer);
2675 /* Write method for DFP pseudo-registers. */
2677 dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2678 int reg_nr, const gdb_byte *buffer)
2680 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2681 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2683 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2685 /* Write each half of the dl register into a separate
2687 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2688 2 * reg_index, buffer);
2689 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2690 2 * reg_index + 1, buffer + 8);
2694 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2695 2 * reg_index + 1, buffer + 8);
2696 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2697 2 * reg_index, buffer);
2701 /* Read method for POWER7 VSX pseudo-registers. */
2702 static enum register_status
2703 vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2704 int reg_nr, gdb_byte *buffer)
2706 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2707 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2708 enum register_status status;
2710 /* Read the portion that overlaps the VMX registers. */
2712 status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2713 reg_index - 32, buffer);
2715 /* Read the portion that overlaps the FPR registers. */
2716 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2718 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2720 if (status == REG_VALID)
2721 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2722 reg_index, buffer + 8);
2726 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2727 reg_index, buffer + 8);
2728 if (status == REG_VALID)
2729 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2736 /* Write method for POWER7 VSX pseudo-registers. */
2738 vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2739 int reg_nr, const gdb_byte *buffer)
2741 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2742 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2744 /* Write the portion that overlaps the VMX registers. */
2746 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2747 reg_index - 32, buffer);
2749 /* Write the portion that overlaps the FPR registers. */
2750 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2752 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2754 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2755 reg_index, buffer + 8);
2759 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2760 reg_index, buffer + 8);
2761 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2766 /* Read method for POWER7 Extended FP pseudo-registers. */
2767 static enum register_status
2768 efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2769 int reg_nr, gdb_byte *buffer)
2771 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2772 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2774 /* Read the portion that overlaps the VMX register. */
2775 return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2776 register_size (gdbarch, reg_nr), buffer);
2779 /* Write method for POWER7 Extended FP pseudo-registers. */
2781 efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2782 int reg_nr, const gdb_byte *buffer)
2784 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2785 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2787 /* Write the portion that overlaps the VMX register. */
2788 regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2789 register_size (gdbarch, reg_nr), buffer);
2792 static enum register_status
2793 rs6000_pseudo_register_read (struct gdbarch *gdbarch,
2794 struct regcache *regcache,
2795 int reg_nr, gdb_byte *buffer)
2797 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2798 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2800 gdb_assert (regcache_arch == gdbarch);
2802 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2803 return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2804 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2805 return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2806 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2807 return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2808 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2809 return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2811 internal_error (__FILE__, __LINE__,
2812 _("rs6000_pseudo_register_read: "
2813 "called on unexpected register '%s' (%d)"),
2814 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2818 rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2819 struct regcache *regcache,
2820 int reg_nr, const gdb_byte *buffer)
2822 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2823 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2825 gdb_assert (regcache_arch == gdbarch);
2827 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2828 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2829 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2830 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2831 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2832 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2833 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2834 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2836 internal_error (__FILE__, __LINE__,
2837 _("rs6000_pseudo_register_write: "
2838 "called on unexpected register '%s' (%d)"),
2839 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2842 /* Convert a DBX STABS register number to a GDB register number. */
2844 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
2846 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2848 if (0 <= num && num <= 31)
2849 return tdep->ppc_gp0_regnum + num;
2850 else if (32 <= num && num <= 63)
2851 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2852 specifies registers the architecture doesn't have? Our
2853 callers don't check the value we return. */
2854 return tdep->ppc_fp0_regnum + (num - 32);
2855 else if (77 <= num && num <= 108)
2856 return tdep->ppc_vr0_regnum + (num - 77);
2857 else if (1200 <= num && num < 1200 + 32)
2858 return tdep->ppc_ev0_regnum + (num - 1200);
2863 return tdep->ppc_mq_regnum;
2865 return tdep->ppc_lr_regnum;
2867 return tdep->ppc_ctr_regnum;
2869 return tdep->ppc_xer_regnum;
2871 return tdep->ppc_vrsave_regnum;
2873 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2875 return tdep->ppc_acc_regnum;
2877 return tdep->ppc_spefscr_regnum;
2884 /* Convert a Dwarf 2 register number to a GDB register number. */
2886 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
2888 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2890 if (0 <= num && num <= 31)
2891 return tdep->ppc_gp0_regnum + num;
2892 else if (32 <= num && num <= 63)
2893 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2894 specifies registers the architecture doesn't have? Our
2895 callers don't check the value we return. */
2896 return tdep->ppc_fp0_regnum + (num - 32);
2897 else if (1124 <= num && num < 1124 + 32)
2898 return tdep->ppc_vr0_regnum + (num - 1124);
2899 else if (1200 <= num && num < 1200 + 32)
2900 return tdep->ppc_ev0_regnum + (num - 1200);
2905 return tdep->ppc_cr_regnum;
2907 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2909 return tdep->ppc_acc_regnum;
2911 return tdep->ppc_mq_regnum;
2913 return tdep->ppc_xer_regnum;
2915 return tdep->ppc_lr_regnum;
2917 return tdep->ppc_ctr_regnum;
2919 return tdep->ppc_vrsave_regnum;
2921 return tdep->ppc_spefscr_regnum;
2927 /* Translate a .eh_frame register to DWARF register, or adjust a
2928 .debug_frame register. */
2931 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2933 /* GCC releases before 3.4 use GCC internal register numbering in
2934 .debug_frame (and .debug_info, et cetera). The numbering is
2935 different from the standard SysV numbering for everything except
2936 for GPRs and FPRs. We can not detect this problem in most cases
2937 - to get accurate debug info for variables living in lr, ctr, v0,
2938 et cetera, use a newer version of GCC. But we must detect
2939 one important case - lr is in column 65 in .debug_frame output,
2942 GCC 3.4, and the "hammer" branch, have a related problem. They
2943 record lr register saves in .debug_frame as 108, but still record
2944 the return column as 65. We fix that up too.
2946 We can do this because 65 is assigned to fpsr, and GCC never
2947 generates debug info referring to it. To add support for
2948 handwritten debug info that restores fpsr, we would need to add a
2949 producer version check to this. */
2958 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2959 internal register numbering; translate that to the standard DWARF2
2960 register numbering. */
2961 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2963 else if (68 <= num && num <= 75) /* cr0-cr8 */
2964 return num - 68 + 86;
2965 else if (77 <= num && num <= 108) /* vr0-vr31 */
2966 return num - 77 + 1124;
2978 case 109: /* vrsave */
2980 case 110: /* vscr */
2982 case 111: /* spe_acc */
2984 case 112: /* spefscr */
2992 /* Handling the various POWER/PowerPC variants. */
2994 /* Information about a particular processor variant. */
2998 /* Name of this variant. */
3001 /* English description of the variant. */
3004 /* bfd_arch_info.arch corresponding to variant. */
3005 enum bfd_architecture arch;
3007 /* bfd_arch_info.mach corresponding to variant. */
3010 /* Target description for this variant. */
3011 struct target_desc **tdesc;
3014 static struct variant variants[] =
3016 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
3017 bfd_mach_ppc, &tdesc_powerpc_altivec32},
3018 {"power", "POWER user-level", bfd_arch_rs6000,
3019 bfd_mach_rs6k, &tdesc_rs6000},
3020 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
3021 bfd_mach_ppc_403, &tdesc_powerpc_403},
3022 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
3023 bfd_mach_ppc_405, &tdesc_powerpc_405},
3024 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
3025 bfd_mach_ppc_601, &tdesc_powerpc_601},
3026 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
3027 bfd_mach_ppc_602, &tdesc_powerpc_602},
3028 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
3029 bfd_mach_ppc_603, &tdesc_powerpc_603},
3030 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
3031 604, &tdesc_powerpc_604},
3032 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
3033 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
3034 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
3035 bfd_mach_ppc_505, &tdesc_powerpc_505},
3036 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
3037 bfd_mach_ppc_860, &tdesc_powerpc_860},
3038 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
3039 bfd_mach_ppc_750, &tdesc_powerpc_750},
3040 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
3041 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
3042 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
3043 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
3046 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
3047 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
3048 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
3049 bfd_mach_ppc_620, &tdesc_powerpc_64},
3050 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
3051 bfd_mach_ppc_630, &tdesc_powerpc_64},
3052 {"a35", "PowerPC A35", bfd_arch_powerpc,
3053 bfd_mach_ppc_a35, &tdesc_powerpc_64},
3054 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
3055 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
3056 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
3057 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
3059 /* FIXME: I haven't checked the register sets of the following. */
3060 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
3061 bfd_mach_rs6k_rs1, &tdesc_rs6000},
3062 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
3063 bfd_mach_rs6k_rsc, &tdesc_rs6000},
3064 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
3065 bfd_mach_rs6k_rs2, &tdesc_rs6000},
3070 /* Return the variant corresponding to architecture ARCH and machine number
3071 MACH. If no such variant exists, return null. */
3073 static const struct variant *
3074 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
3076 const struct variant *v;
3078 for (v = variants; v->name; v++)
3079 if (arch == v->arch && mach == v->mach)
3086 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3088 if (info->endian == BFD_ENDIAN_BIG)
3089 return print_insn_big_powerpc (memaddr, info);
3091 return print_insn_little_powerpc (memaddr, info);
3095 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3097 return frame_unwind_register_unsigned (next_frame,
3098 gdbarch_pc_regnum (gdbarch));
3101 static struct frame_id
3102 rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3104 return frame_id_build (get_frame_register_unsigned
3105 (this_frame, gdbarch_sp_regnum (gdbarch)),
3106 get_frame_pc (this_frame));
3109 struct rs6000_frame_cache
3112 CORE_ADDR initial_sp;
3113 struct trad_frame_saved_reg *saved_regs;
3116 static struct rs6000_frame_cache *
3117 rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
3119 struct rs6000_frame_cache *cache;
3120 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3121 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3122 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3123 struct rs6000_framedata fdata;
3124 int wordsize = tdep->wordsize;
3127 if ((*this_cache) != NULL)
3128 return (*this_cache);
3129 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3130 (*this_cache) = cache;
3131 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3133 func = get_frame_func (this_frame);
3134 pc = get_frame_pc (this_frame);
3135 skip_prologue (gdbarch, func, pc, &fdata);
3137 /* Figure out the parent's stack pointer. */
3139 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3140 address of the current frame. Things might be easier if the
3141 ->frame pointed to the outer-most address of the frame. In
3142 the mean time, the address of the prev frame is used as the
3143 base address of this frame. */
3144 cache->base = get_frame_register_unsigned
3145 (this_frame, gdbarch_sp_regnum (gdbarch));
3147 /* If the function appears to be frameless, check a couple of likely
3148 indicators that we have simply failed to find the frame setup.
3149 Two common cases of this are missing symbols (i.e.
3150 get_frame_func returns the wrong address or 0), and assembly
3151 stubs which have a fast exit path but set up a frame on the slow
3154 If the LR appears to return to this function, then presume that
3155 we have an ABI compliant frame that we failed to find. */
3156 if (fdata.frameless && fdata.lr_offset == 0)
3161 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
3162 if (func == 0 && saved_lr == pc)
3166 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3167 if (func == saved_func)
3173 fdata.frameless = 0;
3174 fdata.lr_offset = tdep->lr_frame_offset;
3178 if (!fdata.frameless)
3179 /* Frameless really means stackless. */
3181 = read_memory_unsigned_integer (cache->base, wordsize, byte_order);
3183 trad_frame_set_value (cache->saved_regs,
3184 gdbarch_sp_regnum (gdbarch), cache->base);
3186 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3187 All fpr's from saved_fpr to fp31 are saved. */
3189 if (fdata.saved_fpr >= 0)
3192 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3194 /* If skip_prologue says floating-point registers were saved,
3195 but the current architecture has no floating-point registers,
3196 then that's strange. But we have no indices to even record
3197 the addresses under, so we just ignore it. */
3198 if (ppc_floating_point_unit_p (gdbarch))
3199 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3201 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3206 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3207 All gpr's from saved_gpr to gpr31 are saved (except during the
3210 if (fdata.saved_gpr >= 0)
3213 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3214 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3216 if (fdata.gpr_mask & (1U << i))
3217 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3218 gpr_addr += wordsize;
3222 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3223 All vr's from saved_vr to vr31 are saved. */
3224 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3226 if (fdata.saved_vr >= 0)
3229 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3230 for (i = fdata.saved_vr; i < 32; i++)
3232 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3233 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3238 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3239 All vr's from saved_ev to ev31 are saved. ????? */
3240 if (tdep->ppc_ev0_regnum != -1)
3242 if (fdata.saved_ev >= 0)
3245 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3246 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3248 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3249 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3250 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3255 /* If != 0, fdata.cr_offset is the offset from the frame that
3257 if (fdata.cr_offset != 0)
3258 cache->saved_regs[tdep->ppc_cr_regnum].addr
3259 = cache->base + fdata.cr_offset;
3261 /* If != 0, fdata.lr_offset is the offset from the frame that
3263 if (fdata.lr_offset != 0)
3264 cache->saved_regs[tdep->ppc_lr_regnum].addr
3265 = cache->base + fdata.lr_offset;
3266 else if (fdata.lr_register != -1)
3267 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
3268 /* The PC is found in the link register. */
3269 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3270 cache->saved_regs[tdep->ppc_lr_regnum];
3272 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3273 holds the VRSAVE. */
3274 if (fdata.vrsave_offset != 0)
3275 cache->saved_regs[tdep->ppc_vrsave_regnum].addr
3276 = cache->base + fdata.vrsave_offset;
3278 if (fdata.alloca_reg < 0)
3279 /* If no alloca register used, then fi->frame is the value of the
3280 %sp for this frame, and it is good enough. */
3282 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
3285 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
3291 rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
3292 struct frame_id *this_id)
3294 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3296 /* This marks the outermost frame. */
3297 if (info->base == 0)
3300 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3303 static struct value *
3304 rs6000_frame_prev_register (struct frame_info *this_frame,
3305 void **this_cache, int regnum)
3307 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3309 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3312 static const struct frame_unwind rs6000_frame_unwind =
3315 default_frame_unwind_stop_reason,
3316 rs6000_frame_this_id,
3317 rs6000_frame_prev_register,
3319 default_frame_sniffer
3324 rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
3326 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3328 return info->initial_sp;
3331 static const struct frame_base rs6000_frame_base = {
3332 &rs6000_frame_unwind,
3333 rs6000_frame_base_address,
3334 rs6000_frame_base_address,
3335 rs6000_frame_base_address
3338 static const struct frame_base *
3339 rs6000_frame_base_sniffer (struct frame_info *this_frame)
3341 return &rs6000_frame_base;
3344 /* DWARF-2 frame support. Used to handle the detection of
3345 clobbered registers during function calls. */
3348 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3349 struct dwarf2_frame_state_reg *reg,
3350 struct frame_info *this_frame)
3352 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3354 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3355 non-volatile registers. We will use the same code for both. */
3357 /* Call-saved GP registers. */
3358 if ((regnum >= tdep->ppc_gp0_regnum + 14
3359 && regnum <= tdep->ppc_gp0_regnum + 31)
3360 || (regnum == tdep->ppc_gp0_regnum + 1))
3361 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3363 /* Call-clobbered GP registers. */
3364 if ((regnum >= tdep->ppc_gp0_regnum + 3
3365 && regnum <= tdep->ppc_gp0_regnum + 12)
3366 || (regnum == tdep->ppc_gp0_regnum))
3367 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3369 /* Deal with FP registers, if supported. */
3370 if (tdep->ppc_fp0_regnum >= 0)
3372 /* Call-saved FP registers. */
3373 if ((regnum >= tdep->ppc_fp0_regnum + 14
3374 && regnum <= tdep->ppc_fp0_regnum + 31))
3375 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3377 /* Call-clobbered FP registers. */
3378 if ((regnum >= tdep->ppc_fp0_regnum
3379 && regnum <= tdep->ppc_fp0_regnum + 13))
3380 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3383 /* Deal with ALTIVEC registers, if supported. */
3384 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3386 /* Call-saved Altivec registers. */
3387 if ((regnum >= tdep->ppc_vr0_regnum + 20
3388 && regnum <= tdep->ppc_vr0_regnum + 31)
3389 || regnum == tdep->ppc_vrsave_regnum)
3390 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3392 /* Call-clobbered Altivec registers. */
3393 if ((regnum >= tdep->ppc_vr0_regnum
3394 && regnum <= tdep->ppc_vr0_regnum + 19))
3395 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3398 /* Handle PC register and Stack Pointer correctly. */
3399 if (regnum == gdbarch_pc_regnum (gdbarch))
3400 reg->how = DWARF2_FRAME_REG_RA;
3401 else if (regnum == gdbarch_sp_regnum (gdbarch))
3402 reg->how = DWARF2_FRAME_REG_CFA;
3406 /* Return true if a .gnu_attributes section exists in BFD and it
3407 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3408 section exists in BFD and it indicates that SPE extensions are in
3409 use. Check the .gnu.attributes section first, as the binary might be
3410 compiled for SPE, but not actually using SPE instructions. */
3413 bfd_uses_spe_extensions (bfd *abfd)
3416 gdb_byte *contents = NULL;
3426 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3427 could be using the SPE vector abi without actually using any spe
3428 bits whatsoever. But it's close enough for now. */
3429 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3430 Tag_GNU_Power_ABI_Vector);
3431 if (vector_abi == 3)
3435 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3439 size = bfd_get_section_size (sect);
3440 contents = xmalloc (size);
3441 if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3447 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3453 char name[name_len rounded up to 4-byte alignment];
3454 char data[data_len];
3457 Technically, there's only supposed to be one such structure in a
3458 given apuinfo section, but the linker is not always vigilant about
3459 merging apuinfo sections from input files. Just go ahead and parse
3460 them all, exiting early when we discover the binary uses SPE
3463 It's not specified in what endianness the information in this
3464 section is stored. Assume that it's the endianness of the BFD. */
3468 unsigned int name_len;
3469 unsigned int data_len;
3472 /* If we can't read the first three fields, we're done. */
3476 name_len = bfd_get_32 (abfd, ptr);
3477 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3478 data_len = bfd_get_32 (abfd, ptr + 4);
3479 type = bfd_get_32 (abfd, ptr + 8);
3482 /* The name must be "APUinfo\0". */
3484 && strcmp ((const char *) ptr, "APUinfo") != 0)
3488 /* The type must be 2. */
3492 /* The data is stored as a series of uint32. The upper half of
3493 each uint32 indicates the particular APU used and the lower
3494 half indicates the revision of that APU. We just care about
3497 /* Not 4-byte quantities. */
3503 unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3504 unsigned int apu = apuinfo >> 16;
3508 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3510 if (apu == 0x100 || apu == 0x101)
3525 /* Initialize the current architecture based on INFO. If possible, re-use an
3526 architecture from ARCHES, which is a list of architectures already created
3527 during this debugging session.
3529 Called e.g. at program startup, when reading a core file, and when reading
3532 static struct gdbarch *
3533 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3535 struct gdbarch *gdbarch;
3536 struct gdbarch_tdep *tdep;
3537 int wordsize, from_xcoff_exec, from_elf_exec;
3538 enum bfd_architecture arch;
3541 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3543 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
3544 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3546 int tdesc_wordsize = -1;
3547 const struct target_desc *tdesc = info.target_desc;
3548 struct tdesc_arch_data *tdesc_data = NULL;
3549 int num_pseudoregs = 0;
3552 /* INFO may refer to a binary that is not of the PowerPC architecture,
3553 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3554 In this case, we must not attempt to infer properties of the (PowerPC
3555 side) of the target system from properties of that executable. Trust
3556 the target description instead. */
3558 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
3559 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
3562 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3563 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3565 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3566 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3568 /* Check word size. If INFO is from a binary file, infer it from
3569 that, else choose a likely default. */
3570 if (from_xcoff_exec)
3572 if (bfd_xcoff_is_xcoff64 (info.abfd))
3577 else if (from_elf_exec)
3579 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3584 else if (tdesc_has_registers (tdesc))
3588 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3589 wordsize = info.bfd_arch_info->bits_per_word /
3590 info.bfd_arch_info->bits_per_byte;
3595 /* Get the architecture and machine from the BFD. */
3596 arch = info.bfd_arch_info->arch;
3597 mach = info.bfd_arch_info->mach;
3599 /* For e500 executables, the apuinfo section is of help here. Such
3600 section contains the identifier and revision number of each
3601 Application-specific Processing Unit that is present on the
3602 chip. The content of the section is determined by the assembler
3603 which looks at each instruction and determines which unit (and
3604 which version of it) can execute it. Grovel through the section
3605 looking for relevant e500 APUs. */
3607 if (bfd_uses_spe_extensions (info.abfd))
3609 arch = info.bfd_arch_info->arch;
3610 mach = bfd_mach_ppc_e500;
3611 bfd_default_set_arch_mach (&abfd, arch, mach);
3612 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3615 /* Find a default target description which describes our register
3616 layout, if we do not already have one. */
3617 if (! tdesc_has_registers (tdesc))
3619 const struct variant *v;
3621 /* Choose variant. */
3622 v = find_variant_by_arch (arch, mach);
3629 gdb_assert (tdesc_has_registers (tdesc));
3631 /* Check any target description for validity. */
3632 if (tdesc_has_registers (tdesc))
3634 static const char *const gprs[] = {
3635 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3636 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3637 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3638 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3640 static const char *const segment_regs[] = {
3641 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3642 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3644 const struct tdesc_feature *feature;
3646 static const char *const msr_names[] = { "msr", "ps" };
3647 static const char *const cr_names[] = { "cr", "cnd" };
3648 static const char *const ctr_names[] = { "ctr", "cnt" };
3650 feature = tdesc_find_feature (tdesc,
3651 "org.gnu.gdb.power.core");
3652 if (feature == NULL)
3655 tdesc_data = tdesc_data_alloc ();
3658 for (i = 0; i < ppc_num_gprs; i++)
3659 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3660 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3662 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3664 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3667 /* Allow alternate names for these registers, to accomodate GDB's
3669 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3670 PPC_MSR_REGNUM, msr_names);
3671 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3672 PPC_CR_REGNUM, cr_names);
3673 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3674 PPC_CTR_REGNUM, ctr_names);
3678 tdesc_data_cleanup (tdesc_data);
3682 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3685 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3687 wordsize = tdesc_wordsize;
3689 feature = tdesc_find_feature (tdesc,
3690 "org.gnu.gdb.power.fpu");
3691 if (feature != NULL)
3693 static const char *const fprs[] = {
3694 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3695 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3696 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3697 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3700 for (i = 0; i < ppc_num_fprs; i++)
3701 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3702 PPC_F0_REGNUM + i, fprs[i]);
3703 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3704 PPC_FPSCR_REGNUM, "fpscr");
3708 tdesc_data_cleanup (tdesc_data);
3716 /* The DFP pseudo-registers will be available when there are floating
3718 have_dfp = have_fpu;
3720 feature = tdesc_find_feature (tdesc,
3721 "org.gnu.gdb.power.altivec");
3722 if (feature != NULL)
3724 static const char *const vector_regs[] = {
3725 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3726 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3727 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3728 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3732 for (i = 0; i < ppc_num_gprs; i++)
3733 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3736 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3737 PPC_VSCR_REGNUM, "vscr");
3738 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3739 PPC_VRSAVE_REGNUM, "vrsave");
3741 if (have_spe || !valid_p)
3743 tdesc_data_cleanup (tdesc_data);
3751 /* Check for POWER7 VSX registers support. */
3752 feature = tdesc_find_feature (tdesc,
3753 "org.gnu.gdb.power.vsx");
3755 if (feature != NULL)
3757 static const char *const vsx_regs[] = {
3758 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3759 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3760 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3761 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3762 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3768 for (i = 0; i < ppc_num_vshrs; i++)
3769 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3770 PPC_VSR0_UPPER_REGNUM + i,
3774 tdesc_data_cleanup (tdesc_data);
3783 /* On machines supporting the SPE APU, the general-purpose registers
3784 are 64 bits long. There are SIMD vector instructions to treat them
3785 as pairs of floats, but the rest of the instruction set treats them
3786 as 32-bit registers, and only operates on their lower halves.
3788 In the GDB regcache, we treat their high and low halves as separate
3789 registers. The low halves we present as the general-purpose
3790 registers, and then we have pseudo-registers that stitch together
3791 the upper and lower halves and present them as pseudo-registers.
3793 Thus, the target description is expected to supply the upper
3794 halves separately. */
3796 feature = tdesc_find_feature (tdesc,
3797 "org.gnu.gdb.power.spe");
3798 if (feature != NULL)
3800 static const char *const upper_spe[] = {
3801 "ev0h", "ev1h", "ev2h", "ev3h",
3802 "ev4h", "ev5h", "ev6h", "ev7h",
3803 "ev8h", "ev9h", "ev10h", "ev11h",
3804 "ev12h", "ev13h", "ev14h", "ev15h",
3805 "ev16h", "ev17h", "ev18h", "ev19h",
3806 "ev20h", "ev21h", "ev22h", "ev23h",
3807 "ev24h", "ev25h", "ev26h", "ev27h",
3808 "ev28h", "ev29h", "ev30h", "ev31h"
3812 for (i = 0; i < ppc_num_gprs; i++)
3813 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3814 PPC_SPE_UPPER_GP0_REGNUM + i,
3816 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3817 PPC_SPE_ACC_REGNUM, "acc");
3818 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3819 PPC_SPE_FSCR_REGNUM, "spefscr");
3821 if (have_mq || have_fpu || !valid_p)
3823 tdesc_data_cleanup (tdesc_data);
3832 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3833 complain for a 32-bit binary on a 64-bit target; we do not yet
3834 support that. For instance, the 32-bit ABI routines expect
3837 As long as there isn't an explicit target description, we'll
3838 choose one based on the BFD architecture and get a word size
3839 matching the binary (probably powerpc:common or
3840 powerpc:common64). So there is only trouble if a 64-bit target
3841 supplies a 64-bit description while debugging a 32-bit
3843 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3845 tdesc_data_cleanup (tdesc_data);
3850 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3852 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3853 Tag_GNU_Power_ABI_FP))
3856 soft_float_flag = AUTO_BOOLEAN_FALSE;
3859 soft_float_flag = AUTO_BOOLEAN_TRUE;
3866 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3868 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3869 Tag_GNU_Power_ABI_Vector))
3872 vector_abi = POWERPC_VEC_GENERIC;
3875 vector_abi = POWERPC_VEC_ALTIVEC;
3878 vector_abi = POWERPC_VEC_SPE;
3886 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3888 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3891 soft_float = !have_fpu;
3893 /* If we have a hard float binary or setting but no floating point
3894 registers, downgrade to soft float anyway. We're still somewhat
3895 useful in this scenario. */
3896 if (!soft_float && !have_fpu)
3899 /* Similarly for vector registers. */
3900 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3901 vector_abi = POWERPC_VEC_GENERIC;
3903 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3904 vector_abi = POWERPC_VEC_GENERIC;
3906 if (vector_abi == POWERPC_VEC_AUTO)
3909 vector_abi = POWERPC_VEC_ALTIVEC;
3911 vector_abi = POWERPC_VEC_SPE;
3913 vector_abi = POWERPC_VEC_GENERIC;
3916 /* Do not limit the vector ABI based on available hardware, since we
3917 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3919 /* Find a candidate among extant architectures. */
3920 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3922 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3924 /* Word size in the various PowerPC bfd_arch_info structs isn't
3925 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3926 separate word size check. */
3927 tdep = gdbarch_tdep (arches->gdbarch);
3928 if (tdep && tdep->soft_float != soft_float)
3930 if (tdep && tdep->vector_abi != vector_abi)
3932 if (tdep && tdep->wordsize == wordsize)
3934 if (tdesc_data != NULL)
3935 tdesc_data_cleanup (tdesc_data);
3936 return arches->gdbarch;
3940 /* None found, create a new architecture from INFO, whose bfd_arch_info
3941 validity depends on the source:
3942 - executable useless
3943 - rs6000_host_arch() good
3945 - "set arch" trust blindly
3946 - GDB startup useless but harmless */
3948 tdep = XCALLOC (1, struct gdbarch_tdep);
3949 tdep->wordsize = wordsize;
3950 tdep->soft_float = soft_float;
3951 tdep->vector_abi = vector_abi;
3953 gdbarch = gdbarch_alloc (&info, tdep);
3955 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3956 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3957 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3958 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3959 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3960 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3961 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3962 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3964 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3965 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
3966 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
3967 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3968 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3969 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3970 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3971 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3973 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3974 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3975 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3976 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
3977 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3979 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3980 GDB traditionally called it "ps", though, so let GDB add an
3982 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3985 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3987 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3989 /* Set lr_frame_offset. */
3991 tdep->lr_frame_offset = 16;
3993 tdep->lr_frame_offset = 4;
3995 if (have_spe || have_dfp || have_vsx)
3997 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
3998 set_gdbarch_pseudo_register_write (gdbarch,
3999 rs6000_pseudo_register_write);
4002 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4004 /* Select instruction printer. */
4005 if (arch == bfd_arch_rs6000)
4006 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
4008 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
4010 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
4013 num_pseudoregs += 32;
4015 num_pseudoregs += 16;
4017 /* Include both VSX and Extended FP registers. */
4018 num_pseudoregs += 96;
4020 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
4022 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4023 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4024 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4025 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4026 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4027 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4028 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4029 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4030 set_gdbarch_char_signed (gdbarch, 0);
4032 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4035 set_gdbarch_frame_red_zone_size (gdbarch, 288);
4037 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
4038 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
4039 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
4041 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
4042 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
4045 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4046 else if (wordsize == 8)
4047 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
4049 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
4050 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
4051 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
4053 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4054 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
4056 /* The value of symbols of type N_SO and N_FUN maybe null when
4058 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
4060 /* Handles single stepping of atomic sequences. */
4061 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
4063 /* Not sure on this. FIXMEmgo */
4064 set_gdbarch_frame_args_skip (gdbarch, 8);
4066 /* Helpers for function argument information. */
4067 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
4070 set_gdbarch_in_solib_return_trampoline
4071 (gdbarch, rs6000_in_solib_return_trampoline);
4072 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
4074 /* Hook in the DWARF CFI frame unwinder. */
4075 dwarf2_append_unwinders (gdbarch);
4076 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
4078 /* Frame handling. */
4079 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
4081 /* Setup displaced stepping. */
4082 set_gdbarch_displaced_step_copy_insn (gdbarch,
4083 simple_displaced_step_copy_insn);
4084 set_gdbarch_displaced_step_hw_singlestep (gdbarch,
4085 ppc_displaced_step_hw_singlestep);
4086 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
4087 set_gdbarch_displaced_step_free_closure (gdbarch,
4088 simple_displaced_step_free_closure);
4089 set_gdbarch_displaced_step_location (gdbarch,
4090 displaced_step_at_entry_point);
4092 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
4094 /* Hook in ABI-specific overrides, if they have been registered. */
4095 info.target_desc = tdesc;
4096 info.tdep_info = (void *) tdesc_data;
4097 gdbarch_init_osabi (info, gdbarch);
4101 case GDB_OSABI_LINUX:
4102 case GDB_OSABI_NETBSD_AOUT:
4103 case GDB_OSABI_NETBSD_ELF:
4104 case GDB_OSABI_UNKNOWN:
4105 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
4106 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4107 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
4108 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
4111 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
4113 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
4114 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4115 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
4116 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
4119 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
4120 set_tdesc_pseudo_register_reggroup_p (gdbarch,
4121 rs6000_pseudo_register_reggroup_p);
4122 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
4124 /* Override the normal target description method to make the SPE upper
4125 halves anonymous. */
4126 set_gdbarch_register_name (gdbarch, rs6000_register_name);
4128 /* Choose register numbers for all supported pseudo-registers. */
4129 tdep->ppc_ev0_regnum = -1;
4130 tdep->ppc_dl0_regnum = -1;
4131 tdep->ppc_vsr0_regnum = -1;
4132 tdep->ppc_efpr0_regnum = -1;
4134 cur_reg = gdbarch_num_regs (gdbarch);
4138 tdep->ppc_ev0_regnum = cur_reg;
4143 tdep->ppc_dl0_regnum = cur_reg;
4148 tdep->ppc_vsr0_regnum = cur_reg;
4150 tdep->ppc_efpr0_regnum = cur_reg;
4154 gdb_assert (gdbarch_num_regs (gdbarch)
4155 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
4157 /* Register the ravenscar_arch_ops. */
4158 if (mach == bfd_mach_ppc_e500)
4159 register_e500_ravenscar_ops (gdbarch);
4161 register_ppc_ravenscar_ops (gdbarch);
4167 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
4169 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4174 /* FIXME: Dump gdbarch_tdep. */
4177 /* PowerPC-specific commands. */
4180 set_powerpc_command (char *args, int from_tty)
4182 printf_unfiltered (_("\
4183 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
4184 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
4188 show_powerpc_command (char *args, int from_tty)
4190 cmd_show_list (showpowerpccmdlist, from_tty, "");
4194 powerpc_set_soft_float (char *args, int from_tty,
4195 struct cmd_list_element *c)
4197 struct gdbarch_info info;
4199 /* Update the architecture. */
4200 gdbarch_info_init (&info);
4201 if (!gdbarch_update_p (info))
4202 internal_error (__FILE__, __LINE__, _("could not update architecture"));
4206 powerpc_set_vector_abi (char *args, int from_tty,
4207 struct cmd_list_element *c)
4209 struct gdbarch_info info;
4210 enum powerpc_vector_abi vector_abi;
4212 for (vector_abi = POWERPC_VEC_AUTO;
4213 vector_abi != POWERPC_VEC_LAST;
4215 if (strcmp (powerpc_vector_abi_string,
4216 powerpc_vector_strings[vector_abi]) == 0)
4218 powerpc_vector_abi_global = vector_abi;
4222 if (vector_abi == POWERPC_VEC_LAST)
4223 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4224 powerpc_vector_abi_string);
4226 /* Update the architecture. */
4227 gdbarch_info_init (&info);
4228 if (!gdbarch_update_p (info))
4229 internal_error (__FILE__, __LINE__, _("could not update architecture"));
4232 /* Show the current setting of the exact watchpoints flag. */
4235 show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty,
4236 struct cmd_list_element *c,
4239 fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value);
4242 /* Initialization code. */
4244 /* -Wmissing-prototypes */
4245 extern initialize_file_ftype _initialize_rs6000_tdep;
4248 _initialize_rs6000_tdep (void)
4250 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4251 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
4253 /* Initialize the standard target descriptions. */
4254 initialize_tdesc_powerpc_32 ();
4255 initialize_tdesc_powerpc_altivec32 ();
4256 initialize_tdesc_powerpc_vsx32 ();
4257 initialize_tdesc_powerpc_403 ();
4258 initialize_tdesc_powerpc_403gc ();
4259 initialize_tdesc_powerpc_405 ();
4260 initialize_tdesc_powerpc_505 ();
4261 initialize_tdesc_powerpc_601 ();
4262 initialize_tdesc_powerpc_602 ();
4263 initialize_tdesc_powerpc_603 ();
4264 initialize_tdesc_powerpc_604 ();
4265 initialize_tdesc_powerpc_64 ();
4266 initialize_tdesc_powerpc_altivec64 ();
4267 initialize_tdesc_powerpc_vsx64 ();
4268 initialize_tdesc_powerpc_7400 ();
4269 initialize_tdesc_powerpc_750 ();
4270 initialize_tdesc_powerpc_860 ();
4271 initialize_tdesc_powerpc_e500 ();
4272 initialize_tdesc_rs6000 ();
4274 /* Add root prefix command for all "set powerpc"/"show powerpc"
4276 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4277 _("Various PowerPC-specific commands."),
4278 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4280 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4281 _("Various PowerPC-specific commands."),
4282 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4284 /* Add a command to allow the user to force the ABI. */
4285 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4286 &powerpc_soft_float_global,
4287 _("Set whether to use a soft-float ABI."),
4288 _("Show whether to use a soft-float ABI."),
4290 powerpc_set_soft_float, NULL,
4291 &setpowerpccmdlist, &showpowerpccmdlist);
4293 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4294 &powerpc_vector_abi_string,
4295 _("Set the vector ABI."),
4296 _("Show the vector ABI."),
4297 NULL, powerpc_set_vector_abi, NULL,
4298 &setpowerpccmdlist, &showpowerpccmdlist);
4300 add_setshow_boolean_cmd ("exact-watchpoints", class_support,
4301 &target_exact_watchpoints,
4303 Set whether to use just one debug register for watchpoints on scalars."),
4305 Show whether to use just one debug register for watchpoints on scalars."),
4307 If true, GDB will use only one debug register when watching a variable of\n\
4308 scalar type, thus assuming that the variable is accessed through the address\n\
4309 of its first byte."),
4310 NULL, show_powerpc_exact_watchpoints,
4311 &setpowerpccmdlist, &showpowerpccmdlist);