1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
43 #include "dwarf2-frame.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "solib-svr4.h"
56 #include "gdb_assert.h"
59 #include "trad-frame.h"
60 #include "frame-unwind.h"
61 #include "frame-base.h"
63 #include "rs6000-tdep.h"
65 /* If the kernel has to deliver a signal, it pushes a sigcontext
66 structure on the stack and then calls the signal handler, passing
67 the address of the sigcontext in an argument register. Usually
68 the signal handler doesn't save this register, so we have to
69 access the sigcontext structure via an offset from the signal handler
71 The following constants were determined by experimentation on AIX 3.2. */
72 #define SIG_FRAME_PC_OFFSET 96
73 #define SIG_FRAME_LR_OFFSET 108
74 #define SIG_FRAME_FP_OFFSET 284
76 /* To be used by skip_prologue. */
78 struct rs6000_framedata
80 int offset; /* total size of frame --- the distance
81 by which we decrement sp to allocate
83 int saved_gpr; /* smallest # of saved gpr */
84 int saved_fpr; /* smallest # of saved fpr */
85 int saved_vr; /* smallest # of saved vr */
86 int saved_ev; /* smallest # of saved ev */
87 int alloca_reg; /* alloca register number (frame ptr) */
88 char frameless; /* true if frameless functions. */
89 char nosavedpc; /* true if pc not saved. */
90 int gpr_offset; /* offset of saved gprs from prev sp */
91 int fpr_offset; /* offset of saved fprs from prev sp */
92 int vr_offset; /* offset of saved vrs from prev sp */
93 int ev_offset; /* offset of saved evs from prev sp */
94 int lr_offset; /* offset of saved lr */
95 int cr_offset; /* offset of saved cr */
96 int vrsave_offset; /* offset of saved vrsave register */
99 /* Description of a single register. */
103 char *name; /* name of register */
104 unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */
105 unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */
106 unsigned char fpr; /* whether register is floating-point */
107 unsigned char pseudo; /* whether register is pseudo */
108 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
109 This is an ISA SPR number, not a GDB
113 /* Hook for determining the TOC address when calling functions in the
114 inferior under AIX. The initialization code in rs6000-nat.c sets
115 this hook to point to find_toc_address. */
117 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
119 /* Static function prototypes */
121 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
123 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
124 struct rs6000_framedata *);
126 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
128 altivec_register_p (int regno)
130 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
131 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
134 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
138 /* Return true if REGNO is an SPE register, false otherwise. */
140 spe_register_p (int regno)
142 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
144 /* Is it a reference to EV0 -- EV31, and do we have those? */
145 if (tdep->ppc_ev0_regnum >= 0
146 && tdep->ppc_ev31_regnum >= 0
147 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
150 /* Is it a reference to one of the raw upper GPR halves? */
151 if (tdep->ppc_ev0_upper_regnum >= 0
152 && tdep->ppc_ev0_upper_regnum <= regno
153 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
156 /* Is it a reference to the 64-bit accumulator, and do we have that? */
157 if (tdep->ppc_acc_regnum >= 0
158 && tdep->ppc_acc_regnum == regno)
161 /* Is it a reference to the SPE floating-point status and control register,
162 and do we have that? */
163 if (tdep->ppc_spefscr_regnum >= 0
164 && tdep->ppc_spefscr_regnum == regno)
171 /* Return non-zero if the architecture described by GDBARCH has
172 floating-point registers (f0 --- f31 and fpscr). */
174 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
176 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
178 return (tdep->ppc_fp0_regnum >= 0
179 && tdep->ppc_fpscr_regnum >= 0);
183 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
186 This is a helper function for init_sim_regno_table, constructing
187 the table mapping GDB register numbers to sim register numbers; we
188 initialize every element in that table to -1 before we start
191 set_sim_regno (int *table, int gdb_regno, int sim_regno)
193 /* Make sure we don't try to assign any given GDB register a sim
194 register number more than once. */
195 gdb_assert (table[gdb_regno] == -1);
196 table[gdb_regno] = sim_regno;
200 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
201 numbers to simulator register numbers, based on the values placed
202 in the ARCH->tdep->ppc_foo_regnum members. */
204 init_sim_regno_table (struct gdbarch *arch)
206 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
207 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
208 const struct reg *regs = tdep->regs;
209 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
212 /* Presume that all registers not explicitly mentioned below are
213 unavailable from the sim. */
214 for (i = 0; i < total_regs; i++)
217 /* General-purpose registers. */
218 for (i = 0; i < ppc_num_gprs; i++)
219 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
221 /* Floating-point registers. */
222 if (tdep->ppc_fp0_regnum >= 0)
223 for (i = 0; i < ppc_num_fprs; i++)
224 set_sim_regno (sim_regno,
225 tdep->ppc_fp0_regnum + i,
226 sim_ppc_f0_regnum + i);
227 if (tdep->ppc_fpscr_regnum >= 0)
228 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
230 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
231 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
232 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
234 /* Segment registers. */
235 if (tdep->ppc_sr0_regnum >= 0)
236 for (i = 0; i < ppc_num_srs; i++)
237 set_sim_regno (sim_regno,
238 tdep->ppc_sr0_regnum + i,
239 sim_ppc_sr0_regnum + i);
241 /* Altivec registers. */
242 if (tdep->ppc_vr0_regnum >= 0)
244 for (i = 0; i < ppc_num_vrs; i++)
245 set_sim_regno (sim_regno,
246 tdep->ppc_vr0_regnum + i,
247 sim_ppc_vr0_regnum + i);
249 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
250 we can treat this more like the other cases. */
251 set_sim_regno (sim_regno,
252 tdep->ppc_vr0_regnum + ppc_num_vrs,
253 sim_ppc_vscr_regnum);
255 /* vsave is a special-purpose register, so the code below handles it. */
257 /* SPE APU (E500) registers. */
258 if (tdep->ppc_ev0_regnum >= 0)
259 for (i = 0; i < ppc_num_gprs; i++)
260 set_sim_regno (sim_regno,
261 tdep->ppc_ev0_regnum + i,
262 sim_ppc_ev0_regnum + i);
263 if (tdep->ppc_ev0_upper_regnum >= 0)
264 for (i = 0; i < ppc_num_gprs; i++)
265 set_sim_regno (sim_regno,
266 tdep->ppc_ev0_upper_regnum + i,
267 sim_ppc_rh0_regnum + i);
268 if (tdep->ppc_acc_regnum >= 0)
269 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
270 /* spefscr is a special-purpose register, so the code below handles it. */
272 /* Now handle all special-purpose registers. Verify that they
273 haven't mistakenly been assigned numbers by any of the above
275 for (i = 0; i < total_regs; i++)
276 if (regs[i].spr_num >= 0)
277 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
279 /* Drop the initialized array into place. */
280 tdep->sim_regno = sim_regno;
284 /* Given a GDB register number REG, return the corresponding SIM
287 rs6000_register_sim_regno (int reg)
289 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
292 gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
293 sim_regno = tdep->sim_regno[reg];
298 return LEGACY_SIM_REGNO_IGNORE;
303 /* Register set support functions. */
306 ppc_supply_reg (struct regcache *regcache, int regnum,
307 const gdb_byte *regs, size_t offset)
309 if (regnum != -1 && offset != -1)
310 regcache_raw_supply (regcache, regnum, regs + offset);
314 ppc_collect_reg (const struct regcache *regcache, int regnum,
315 gdb_byte *regs, size_t offset)
317 if (regnum != -1 && offset != -1)
318 regcache_raw_collect (regcache, regnum, regs + offset);
321 /* Supply register REGNUM in the general-purpose register set REGSET
322 from the buffer specified by GREGS and LEN to register cache
323 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
326 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
327 int regnum, const void *gregs, size_t len)
329 struct gdbarch *gdbarch = get_regcache_arch (regcache);
330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
331 const struct ppc_reg_offsets *offsets = regset->descr;
335 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
336 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
339 if (regnum == -1 || regnum == i)
340 ppc_supply_reg (regcache, i, gregs, offset);
343 if (regnum == -1 || regnum == PC_REGNUM)
344 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
345 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
346 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
347 gregs, offsets->ps_offset);
348 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
349 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
350 gregs, offsets->cr_offset);
351 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
352 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
353 gregs, offsets->lr_offset);
354 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
355 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
356 gregs, offsets->ctr_offset);
357 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
358 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
359 gregs, offsets->cr_offset);
360 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
361 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
364 /* Supply register REGNUM in the floating-point register set REGSET
365 from the buffer specified by FPREGS and LEN to register cache
366 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
369 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
370 int regnum, const void *fpregs, size_t len)
372 struct gdbarch *gdbarch = get_regcache_arch (regcache);
373 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
374 const struct ppc_reg_offsets *offsets = regset->descr;
378 gdb_assert (ppc_floating_point_unit_p (gdbarch));
380 offset = offsets->f0_offset;
381 for (i = tdep->ppc_fp0_regnum;
382 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
385 if (regnum == -1 || regnum == i)
386 ppc_supply_reg (regcache, i, fpregs, offset);
389 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
390 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
391 fpregs, offsets->fpscr_offset);
394 /* Collect register REGNUM in the general-purpose register set
395 REGSET. from register cache REGCACHE into the buffer specified by
396 GREGS and LEN. If REGNUM is -1, do this for all registers in
400 ppc_collect_gregset (const struct regset *regset,
401 const struct regcache *regcache,
402 int regnum, void *gregs, size_t len)
404 struct gdbarch *gdbarch = get_regcache_arch (regcache);
405 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
406 const struct ppc_reg_offsets *offsets = regset->descr;
410 offset = offsets->r0_offset;
411 for (i = tdep->ppc_gp0_regnum;
412 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
415 if (regnum == -1 || regnum == i)
416 ppc_collect_reg (regcache, i, gregs, offset);
419 if (regnum == -1 || regnum == PC_REGNUM)
420 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
421 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
422 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
423 gregs, offsets->ps_offset);
424 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
425 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
426 gregs, offsets->cr_offset);
427 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
428 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
429 gregs, offsets->lr_offset);
430 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
431 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
432 gregs, offsets->ctr_offset);
433 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
434 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
435 gregs, offsets->xer_offset);
436 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
437 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
438 gregs, offsets->mq_offset);
441 /* Collect register REGNUM in the floating-point register set
442 REGSET. from register cache REGCACHE into the buffer specified by
443 FPREGS and LEN. If REGNUM is -1, do this for all registers in
447 ppc_collect_fpregset (const struct regset *regset,
448 const struct regcache *regcache,
449 int regnum, void *fpregs, size_t len)
451 struct gdbarch *gdbarch = get_regcache_arch (regcache);
452 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
453 const struct ppc_reg_offsets *offsets = regset->descr;
457 gdb_assert (ppc_floating_point_unit_p (gdbarch));
459 offset = offsets->f0_offset;
460 for (i = tdep->ppc_fp0_regnum;
461 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
464 if (regnum == -1 || regnum == i)
465 ppc_collect_reg (regcache, i, fpregs, offset);
468 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
469 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
470 fpregs, offsets->fpscr_offset);
474 /* Read a LEN-byte address from debugged memory address MEMADDR. */
477 read_memory_addr (CORE_ADDR memaddr, int len)
479 return read_memory_unsigned_integer (memaddr, len);
483 rs6000_skip_prologue (CORE_ADDR pc)
485 struct rs6000_framedata frame;
486 CORE_ADDR limit_pc, func_addr;
488 /* See if we can determine the end of the prologue via the symbol table.
489 If so, then return either PC, or the PC after the prologue, whichever
491 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
493 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
494 if (post_prologue_pc != 0)
495 return max (pc, post_prologue_pc);
498 /* Can't determine prologue from the symbol table, need to examine
501 /* Find an upper limit on the function prologue using the debug
502 information. If the debug information could not be used to provide
503 that bound, then use an arbitrary large number as the upper bound. */
504 limit_pc = skip_prologue_using_sal (pc);
506 limit_pc = pc + 100; /* Magic. */
508 pc = skip_prologue (pc, limit_pc, &frame);
513 insn_changes_sp_or_jumps (unsigned long insn)
515 int opcode = (insn >> 26) & 0x03f;
516 int sd = (insn >> 21) & 0x01f;
517 int a = (insn >> 16) & 0x01f;
518 int subcode = (insn >> 1) & 0x3ff;
520 /* Changes the stack pointer. */
522 /* NOTE: There are many ways to change the value of a given register.
523 The ways below are those used when the register is R1, the SP,
524 in a funtion's epilogue. */
526 if (opcode == 31 && subcode == 444 && a == 1)
527 return 1; /* mr R1,Rn */
528 if (opcode == 14 && sd == 1)
529 return 1; /* addi R1,Rn,simm */
530 if (opcode == 58 && sd == 1)
531 return 1; /* ld R1,ds(Rn) */
533 /* Transfers control. */
539 if (opcode == 19 && subcode == 16)
541 if (opcode == 19 && subcode == 528)
542 return 1; /* bcctr */
547 /* Return true if we are in the function's epilogue, i.e. after the
548 instruction that destroyed the function's stack frame.
550 1) scan forward from the point of execution:
551 a) If you find an instruction that modifies the stack pointer
552 or transfers control (except a return), execution is not in
554 b) Stop scanning if you find a return instruction or reach the
555 end of the function or reach the hard limit for the size of
557 2) scan backward from the point of execution:
558 a) If you find an instruction that modifies the stack pointer,
559 execution *is* in an epilogue, return.
560 b) Stop scanning if you reach an instruction that transfers
561 control or the beginning of the function or reach the hard
562 limit for the size of an epilogue. */
565 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
567 bfd_byte insn_buf[PPC_INSN_SIZE];
568 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
570 struct frame_info *curfrm;
572 /* Find the search limits based on function boundaries and hard limit. */
574 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
577 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
578 if (epilogue_start < func_start) epilogue_start = func_start;
580 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
581 if (epilogue_end > func_end) epilogue_end = func_end;
583 curfrm = get_current_frame ();
585 /* Scan forward until next 'blr'. */
587 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
589 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
591 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
592 if (insn == 0x4e800020)
594 if (insn_changes_sp_or_jumps (insn))
598 /* Scan backward until adjustment to stack pointer (R1). */
600 for (scan_pc = pc - PPC_INSN_SIZE;
601 scan_pc >= epilogue_start;
602 scan_pc -= PPC_INSN_SIZE)
604 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
606 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
607 if (insn_changes_sp_or_jumps (insn))
614 /* Get the ith function argument for the current function. */
616 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
619 return get_frame_register_unsigned (frame, 3 + argi);
622 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
625 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
632 absolute = (int) ((instr >> 1) & 1);
637 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
641 dest = pc + immediate;
645 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
649 dest = pc + immediate;
653 ext_op = (instr >> 1) & 0x3ff;
655 if (ext_op == 16) /* br conditional register */
657 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
659 /* If we are about to return from a signal handler, dest is
660 something like 0x3c90. The current frame is a signal handler
661 caller frame, upon completion of the sigreturn system call
662 execution will return to the saved PC in the frame. */
663 if (dest < gdbarch_tdep (current_gdbarch)->text_segment_base)
665 struct frame_info *fi;
667 fi = get_current_frame ();
669 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
670 gdbarch_tdep (current_gdbarch)->wordsize);
674 else if (ext_op == 528) /* br cond to count reg */
676 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
678 /* If we are about to execute a system call, dest is something
679 like 0x22fc or 0x3b00. Upon completion the system call
680 will return to the address in the link register. */
681 if (dest < gdbarch_tdep (current_gdbarch)->text_segment_base)
682 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
691 return (dest < gdbarch_tdep (current_gdbarch)->text_segment_base) ? safety : dest;
695 /* Sequence of bytes for breakpoint instruction. */
697 const static unsigned char *
698 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
700 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
701 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
703 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
704 return big_breakpoint;
706 return little_breakpoint;
710 /* AIX does not support PT_STEP. Simulate it. */
713 rs6000_software_single_step (struct regcache *regcache)
717 const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
725 insn = read_memory_integer (loc, 4);
727 breaks[0] = loc + breakp_sz;
729 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
731 /* Don't put two breakpoints on the same address. */
732 if (breaks[1] == breaks[0])
735 for (ii = 0; ii < 2; ++ii)
737 /* ignore invalid breakpoint. */
738 if (breaks[ii] == -1)
740 insert_single_step_breakpoint (breaks[ii]);
743 errno = 0; /* FIXME, don't ignore errors! */
744 /* What errors? {read,write}_memory call error(). */
749 /* return pc value after skipping a function prologue and also return
750 information about a function frame.
752 in struct rs6000_framedata fdata:
753 - frameless is TRUE, if function does not have a frame.
754 - nosavedpc is TRUE, if function does not save %pc value in its frame.
755 - offset is the initial size of this stack frame --- the amount by
756 which we decrement the sp to allocate the frame.
757 - saved_gpr is the number of the first saved gpr.
758 - saved_fpr is the number of the first saved fpr.
759 - saved_vr is the number of the first saved vr.
760 - saved_ev is the number of the first saved ev.
761 - alloca_reg is the number of the register used for alloca() handling.
763 - gpr_offset is the offset of the first saved gpr from the previous frame.
764 - fpr_offset is the offset of the first saved fpr from the previous frame.
765 - vr_offset is the offset of the first saved vr from the previous frame.
766 - ev_offset is the offset of the first saved ev from the previous frame.
767 - lr_offset is the offset of the saved lr
768 - cr_offset is the offset of the saved cr
769 - vrsave_offset is the offset of the saved vrsave register
772 #define SIGNED_SHORT(x) \
773 ((sizeof (short) == 2) \
774 ? ((int)(short)(x)) \
775 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
777 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
779 /* Limit the number of skipped non-prologue instructions, as the examining
780 of the prologue is expensive. */
781 static int max_skip_non_prologue_insns = 10;
783 /* Return nonzero if the given instruction OP can be part of the prologue
784 of a function and saves a parameter on the stack. FRAMEP should be
785 set if one of the previous instructions in the function has set the
789 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
791 /* Move parameters from argument registers to temporary register. */
792 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
794 /* Rx must be scratch register r0. */
795 const int rx_regno = (op >> 16) & 31;
796 /* Ry: Only r3 - r10 are used for parameter passing. */
797 const int ry_regno = GET_SRC_REG (op);
799 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
801 *r0_contains_arg = 1;
808 /* Save a General Purpose Register on stack. */
810 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
811 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
813 /* Rx: Only r3 - r10 are used for parameter passing. */
814 const int rx_regno = GET_SRC_REG (op);
816 return (rx_regno >= 3 && rx_regno <= 10);
819 /* Save a General Purpose Register on stack via the Frame Pointer. */
822 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
823 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
824 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
826 /* Rx: Usually, only r3 - r10 are used for parameter passing.
827 However, the compiler sometimes uses r0 to hold an argument. */
828 const int rx_regno = GET_SRC_REG (op);
830 return ((rx_regno >= 3 && rx_regno <= 10)
831 || (rx_regno == 0 && *r0_contains_arg));
834 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
836 /* Only f2 - f8 are used for parameter passing. */
837 const int src_regno = GET_SRC_REG (op);
839 return (src_regno >= 2 && src_regno <= 8);
842 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
844 /* Only f2 - f8 are used for parameter passing. */
845 const int src_regno = GET_SRC_REG (op);
847 return (src_regno >= 2 && src_regno <= 8);
850 /* Not an insn that saves a parameter on stack. */
854 /* Assuming that INSN is a "bl" instruction located at PC, return
855 nonzero if the destination of the branch is a "blrl" instruction.
857 This sequence is sometimes found in certain function prologues.
858 It allows the function to load the LR register with a value that
859 they can use to access PIC data using PC-relative offsets. */
862 bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
864 const int opcode = 18;
865 const CORE_ADDR dest = branch_dest (opcode, insn, pc, -1);
869 return 0; /* Should never happen, but just return zero to be safe. */
871 dest_insn = read_memory_integer (dest, 4);
872 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
879 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
881 CORE_ADDR orig_pc = pc;
882 CORE_ADDR last_prologue_pc = pc;
883 CORE_ADDR li_found_pc = 0;
887 long vr_saved_offset = 0;
896 int minimal_toc_loaded = 0;
897 int prev_insn_was_prologue_insn = 1;
898 int num_skip_non_prologue_insns = 0;
899 int r0_contains_arg = 0;
900 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
901 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
903 memset (fdata, 0, sizeof (struct rs6000_framedata));
904 fdata->saved_gpr = -1;
905 fdata->saved_fpr = -1;
906 fdata->saved_vr = -1;
907 fdata->saved_ev = -1;
908 fdata->alloca_reg = -1;
909 fdata->frameless = 1;
910 fdata->nosavedpc = 1;
914 /* Sometimes it isn't clear if an instruction is a prologue
915 instruction or not. When we encounter one of these ambiguous
916 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
917 Otherwise, we'll assume that it really is a prologue instruction. */
918 if (prev_insn_was_prologue_insn)
919 last_prologue_pc = pc;
921 /* Stop scanning if we've hit the limit. */
925 prev_insn_was_prologue_insn = 1;
927 /* Fetch the instruction and convert it to an integer. */
928 if (target_read_memory (pc, buf, 4))
930 op = extract_unsigned_integer (buf, 4);
932 if ((op & 0xfc1fffff) == 0x7c0802a6)
934 /* Since shared library / PIC code, which needs to get its
935 address at runtime, can appear to save more than one link
949 remember just the first one, but skip over additional
952 lr_reg = (op & 0x03e00000);
957 else if ((op & 0xfc1fffff) == 0x7c000026)
959 cr_reg = (op & 0x03e00000);
965 else if ((op & 0xfc1f0000) == 0xd8010000)
966 { /* stfd Rx,NUM(r1) */
967 reg = GET_SRC_REG (op);
968 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
970 fdata->saved_fpr = reg;
971 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
976 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
977 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
978 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
979 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
982 reg = GET_SRC_REG (op);
983 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
985 fdata->saved_gpr = reg;
986 if ((op & 0xfc1f0003) == 0xf8010000)
988 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
993 else if ((op & 0xffff0000) == 0x60000000)
996 /* Allow nops in the prologue, but do not consider them to
997 be part of the prologue unless followed by other prologue
999 prev_insn_was_prologue_insn = 0;
1003 else if ((op & 0xffff0000) == 0x3c000000)
1004 { /* addis 0,0,NUM, used
1005 for >= 32k frames */
1006 fdata->offset = (op & 0x0000ffff) << 16;
1007 fdata->frameless = 0;
1008 r0_contains_arg = 0;
1012 else if ((op & 0xffff0000) == 0x60000000)
1013 { /* ori 0,0,NUM, 2nd ha
1014 lf of >= 32k frames */
1015 fdata->offset |= (op & 0x0000ffff);
1016 fdata->frameless = 0;
1017 r0_contains_arg = 0;
1021 else if (lr_reg >= 0 &&
1022 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1023 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1024 /* stw Rx, NUM(r1) */
1025 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1026 /* stwu Rx, NUM(r1) */
1027 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1028 { /* where Rx == lr */
1029 fdata->lr_offset = offset;
1030 fdata->nosavedpc = 0;
1031 /* Invalidate lr_reg, but don't set it to -1.
1032 That would mean that it had never been set. */
1034 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1035 (op & 0xfc000000) == 0x90000000) /* stw */
1037 /* Does not update r1, so add displacement to lr_offset. */
1038 fdata->lr_offset += SIGNED_SHORT (op);
1043 else if (cr_reg >= 0 &&
1044 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1045 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1046 /* stw Rx, NUM(r1) */
1047 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1048 /* stwu Rx, NUM(r1) */
1049 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1050 { /* where Rx == cr */
1051 fdata->cr_offset = offset;
1052 /* Invalidate cr_reg, but don't set it to -1.
1053 That would mean that it had never been set. */
1055 if ((op & 0xfc000003) == 0xf8000000 ||
1056 (op & 0xfc000000) == 0x90000000)
1058 /* Does not update r1, so add displacement to cr_offset. */
1059 fdata->cr_offset += SIGNED_SHORT (op);
1064 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1066 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1067 prediction bits. If the LR has already been saved, we can
1071 else if (op == 0x48000005)
1077 else if (op == 0x48000004)
1082 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1083 in V.4 -mminimal-toc */
1084 (op & 0xffff0000) == 0x3bde0000)
1085 { /* addi 30,30,foo@l */
1089 else if ((op & 0xfc000001) == 0x48000001)
1093 fdata->frameless = 0;
1095 /* If the return address has already been saved, we can skip
1096 calls to blrl (for PIC). */
1097 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
1100 /* Don't skip over the subroutine call if it is not within
1101 the first three instructions of the prologue and either
1102 we have no line table information or the line info tells
1103 us that the subroutine call is not part of the line
1104 associated with the prologue. */
1105 if ((pc - orig_pc) > 8)
1107 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1108 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1110 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1114 op = read_memory_integer (pc + 4, 4);
1116 /* At this point, make sure this is not a trampoline
1117 function (a function that simply calls another functions,
1118 and nothing else). If the next is not a nop, this branch
1119 was part of the function prologue. */
1121 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1122 break; /* don't skip over
1127 /* update stack pointer */
1128 else if ((op & 0xfc1f0000) == 0x94010000)
1129 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1130 fdata->frameless = 0;
1131 fdata->offset = SIGNED_SHORT (op);
1132 offset = fdata->offset;
1135 else if ((op & 0xfc1f016a) == 0x7c01016e)
1136 { /* stwux rX,r1,rY */
1137 /* no way to figure out what r1 is going to be */
1138 fdata->frameless = 0;
1139 offset = fdata->offset;
1142 else if ((op & 0xfc1f0003) == 0xf8010001)
1143 { /* stdu rX,NUM(r1) */
1144 fdata->frameless = 0;
1145 fdata->offset = SIGNED_SHORT (op & ~3UL);
1146 offset = fdata->offset;
1149 else if ((op & 0xfc1f016a) == 0x7c01016a)
1150 { /* stdux rX,r1,rY */
1151 /* no way to figure out what r1 is going to be */
1152 fdata->frameless = 0;
1153 offset = fdata->offset;
1156 else if ((op & 0xffff0000) == 0x38210000)
1157 { /* addi r1,r1,SIMM */
1158 fdata->frameless = 0;
1159 fdata->offset += SIGNED_SHORT (op);
1160 offset = fdata->offset;
1163 /* Load up minimal toc pointer. Do not treat an epilogue restore
1164 of r31 as a minimal TOC load. */
1165 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1166 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1168 && !minimal_toc_loaded)
1170 minimal_toc_loaded = 1;
1173 /* move parameters from argument registers to local variable
1176 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1177 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1178 (((op >> 21) & 31) <= 10) &&
1179 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1183 /* store parameters in stack */
1185 /* Move parameters from argument registers to temporary register. */
1186 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1190 /* Set up frame pointer */
1192 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1193 || op == 0x7c3f0b78)
1195 fdata->frameless = 0;
1197 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1200 /* Another way to set up the frame pointer. */
1202 else if ((op & 0xfc1fffff) == 0x38010000)
1203 { /* addi rX, r1, 0x0 */
1204 fdata->frameless = 0;
1206 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1207 + ((op & ~0x38010000) >> 21));
1210 /* AltiVec related instructions. */
1211 /* Store the vrsave register (spr 256) in another register for
1212 later manipulation, or load a register into the vrsave
1213 register. 2 instructions are used: mfvrsave and
1214 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1215 and mtspr SPR256, Rn. */
1216 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1217 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1218 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1220 vrsave_reg = GET_SRC_REG (op);
1223 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1227 /* Store the register where vrsave was saved to onto the stack:
1228 rS is the register where vrsave was stored in a previous
1230 /* 100100 sssss 00001 dddddddd dddddddd */
1231 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1233 if (vrsave_reg == GET_SRC_REG (op))
1235 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1240 /* Compute the new value of vrsave, by modifying the register
1241 where vrsave was saved to. */
1242 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1243 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1247 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1248 in a pair of insns to save the vector registers on the
1250 /* 001110 00000 00000 iiii iiii iiii iiii */
1251 /* 001110 01110 00000 iiii iiii iiii iiii */
1252 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1253 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1255 if ((op & 0xffff0000) == 0x38000000)
1256 r0_contains_arg = 0;
1258 vr_saved_offset = SIGNED_SHORT (op);
1260 /* This insn by itself is not part of the prologue, unless
1261 if part of the pair of insns mentioned above. So do not
1262 record this insn as part of the prologue yet. */
1263 prev_insn_was_prologue_insn = 0;
1265 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1266 /* 011111 sssss 11111 00000 00111001110 */
1267 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1269 if (pc == (li_found_pc + 4))
1271 vr_reg = GET_SRC_REG (op);
1272 /* If this is the first vector reg to be saved, or if
1273 it has a lower number than others previously seen,
1274 reupdate the frame info. */
1275 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1277 fdata->saved_vr = vr_reg;
1278 fdata->vr_offset = vr_saved_offset + offset;
1280 vr_saved_offset = -1;
1285 /* End AltiVec related instructions. */
1287 /* Start BookE related instructions. */
1288 /* Store gen register S at (r31+uimm).
1289 Any register less than r13 is volatile, so we don't care. */
1290 /* 000100 sssss 11111 iiiii 01100100001 */
1291 else if (arch_info->mach == bfd_mach_ppc_e500
1292 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1294 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1297 ev_reg = GET_SRC_REG (op);
1298 imm = (op >> 11) & 0x1f;
1299 ev_offset = imm * 8;
1300 /* If this is the first vector reg to be saved, or if
1301 it has a lower number than others previously seen,
1302 reupdate the frame info. */
1303 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1305 fdata->saved_ev = ev_reg;
1306 fdata->ev_offset = ev_offset + offset;
1311 /* Store gen register rS at (r1+rB). */
1312 /* 000100 sssss 00001 bbbbb 01100100000 */
1313 else if (arch_info->mach == bfd_mach_ppc_e500
1314 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1316 if (pc == (li_found_pc + 4))
1318 ev_reg = GET_SRC_REG (op);
1319 /* If this is the first vector reg to be saved, or if
1320 it has a lower number than others previously seen,
1321 reupdate the frame info. */
1322 /* We know the contents of rB from the previous instruction. */
1323 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1325 fdata->saved_ev = ev_reg;
1326 fdata->ev_offset = vr_saved_offset + offset;
1328 vr_saved_offset = -1;
1334 /* Store gen register r31 at (rA+uimm). */
1335 /* 000100 11111 aaaaa iiiii 01100100001 */
1336 else if (arch_info->mach == bfd_mach_ppc_e500
1337 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1339 /* Wwe know that the source register is 31 already, but
1340 it can't hurt to compute it. */
1341 ev_reg = GET_SRC_REG (op);
1342 ev_offset = ((op >> 11) & 0x1f) * 8;
1343 /* If this is the first vector reg to be saved, or if
1344 it has a lower number than others previously seen,
1345 reupdate the frame info. */
1346 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1348 fdata->saved_ev = ev_reg;
1349 fdata->ev_offset = ev_offset + offset;
1354 /* Store gen register S at (r31+r0).
1355 Store param on stack when offset from SP bigger than 4 bytes. */
1356 /* 000100 sssss 11111 00000 01100100000 */
1357 else if (arch_info->mach == bfd_mach_ppc_e500
1358 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1360 if (pc == (li_found_pc + 4))
1362 if ((op & 0x03e00000) >= 0x01a00000)
1364 ev_reg = GET_SRC_REG (op);
1365 /* If this is the first vector reg to be saved, or if
1366 it has a lower number than others previously seen,
1367 reupdate the frame info. */
1368 /* We know the contents of r0 from the previous
1370 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1372 fdata->saved_ev = ev_reg;
1373 fdata->ev_offset = vr_saved_offset + offset;
1377 vr_saved_offset = -1;
1382 /* End BookE related instructions. */
1386 /* Not a recognized prologue instruction.
1387 Handle optimizer code motions into the prologue by continuing
1388 the search if we have no valid frame yet or if the return
1389 address is not yet saved in the frame. */
1390 if (fdata->frameless == 0 && fdata->nosavedpc == 0)
1393 if (op == 0x4e800020 /* blr */
1394 || op == 0x4e800420) /* bctr */
1395 /* Do not scan past epilogue in frameless functions or
1398 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1399 /* Never skip branches. */
1402 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1403 /* Do not scan too many insns, scanning insns is expensive with
1407 /* Continue scanning. */
1408 prev_insn_was_prologue_insn = 0;
1414 /* I have problems with skipping over __main() that I need to address
1415 * sometime. Previously, I used to use misc_function_vector which
1416 * didn't work as well as I wanted to be. -MGO */
1418 /* If the first thing after skipping a prolog is a branch to a function,
1419 this might be a call to an initializer in main(), introduced by gcc2.
1420 We'd like to skip over it as well. Fortunately, xlc does some extra
1421 work before calling a function right after a prologue, thus we can
1422 single out such gcc2 behaviour. */
1425 if ((op & 0xfc000001) == 0x48000001)
1426 { /* bl foo, an initializer function? */
1427 op = read_memory_integer (pc + 4, 4);
1429 if (op == 0x4def7b82)
1430 { /* cror 0xf, 0xf, 0xf (nop) */
1432 /* Check and see if we are in main. If so, skip over this
1433 initializer function as well. */
1435 tmp = find_pc_misc_function (pc);
1437 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1443 fdata->offset = -fdata->offset;
1444 return last_prologue_pc;
1448 /*************************************************************************
1449 Support for creating pushing a dummy frame into the stack, and popping
1451 *************************************************************************/
1454 /* All the ABI's require 16 byte alignment. */
1456 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1458 return (addr & -16);
1461 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1462 the first eight words of the argument list (that might be less than
1463 eight parameters if some parameters occupy more than one word) are
1464 passed in r3..r10 registers. float and double parameters are
1465 passed in fpr's, in addition to that. Rest of the parameters if any
1466 are passed in user stack. There might be cases in which half of the
1467 parameter is copied into registers, the other half is pushed into
1470 Stack must be aligned on 64-bit boundaries when synthesizing
1473 If the function is returning a structure, then the return address is passed
1474 in r3, then the first 7 words of the parameters can be passed in registers,
1475 starting from r4. */
1478 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1479 struct regcache *regcache, CORE_ADDR bp_addr,
1480 int nargs, struct value **args, CORE_ADDR sp,
1481 int struct_return, CORE_ADDR struct_addr)
1483 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1486 int argno; /* current argument number */
1487 int argbytes; /* current argument byte */
1488 gdb_byte tmp_buffer[50];
1489 int f_argno = 0; /* current floating point argno */
1490 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1491 CORE_ADDR func_addr = find_function_addr (function, NULL);
1493 struct value *arg = 0;
1498 /* The calling convention this function implements assumes the
1499 processor has floating-point registers. We shouldn't be using it
1500 on PPC variants that lack them. */
1501 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1503 /* The first eight words of ther arguments are passed in registers.
1504 Copy them appropriately. */
1507 /* If the function is returning a `struct', then the first word
1508 (which will be passed in r3) is used for struct return address.
1509 In that case we should advance one word and start from r4
1510 register to copy parameters. */
1513 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1519 effectively indirect call... gcc does...
1521 return_val example( float, int);
1524 float in fp0, int in r3
1525 offset of stack on overflow 8/16
1526 for varargs, must go by type.
1528 float in r3&r4, int in r5
1529 offset of stack on overflow different
1531 return in r3 or f0. If no float, must study how gcc emulates floats;
1532 pay attention to arg promotion.
1533 User may have to cast\args to handle promotion correctly
1534 since gdb won't know if prototype supplied or not.
1537 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1539 int reg_size = register_size (current_gdbarch, ii + 3);
1542 type = check_typedef (value_type (arg));
1543 len = TYPE_LENGTH (type);
1545 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1548 /* Floating point arguments are passed in fpr's, as well as gpr's.
1549 There are 13 fpr's reserved for passing parameters. At this point
1550 there is no way we would run out of them. */
1552 gdb_assert (len <= 8);
1554 regcache_cooked_write (regcache,
1555 tdep->ppc_fp0_regnum + 1 + f_argno,
1556 value_contents (arg));
1563 /* Argument takes more than one register. */
1564 while (argbytes < len)
1566 gdb_byte word[MAX_REGISTER_SIZE];
1567 memset (word, 0, reg_size);
1569 ((char *) value_contents (arg)) + argbytes,
1570 (len - argbytes) > reg_size
1571 ? reg_size : len - argbytes);
1572 regcache_cooked_write (regcache,
1573 tdep->ppc_gp0_regnum + 3 + ii,
1575 ++ii, argbytes += reg_size;
1578 goto ran_out_of_registers_for_arguments;
1585 /* Argument can fit in one register. No problem. */
1586 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1587 gdb_byte word[MAX_REGISTER_SIZE];
1589 memset (word, 0, reg_size);
1590 memcpy (word, value_contents (arg), len);
1591 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1596 ran_out_of_registers_for_arguments:
1598 saved_sp = read_sp ();
1600 /* Location for 8 parameters are always reserved. */
1603 /* Another six words for back chain, TOC register, link register, etc. */
1606 /* Stack pointer must be quadword aligned. */
1609 /* If there are more arguments, allocate space for them in
1610 the stack, then push them starting from the ninth one. */
1612 if ((argno < nargs) || argbytes)
1618 space += ((len - argbytes + 3) & -4);
1624 for (; jj < nargs; ++jj)
1626 struct value *val = args[jj];
1627 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
1630 /* Add location required for the rest of the parameters. */
1631 space = (space + 15) & -16;
1634 /* This is another instance we need to be concerned about
1635 securing our stack space. If we write anything underneath %sp
1636 (r1), we might conflict with the kernel who thinks he is free
1637 to use this area. So, update %sp first before doing anything
1640 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1642 /* If the last argument copied into the registers didn't fit there
1643 completely, push the rest of it into stack. */
1647 write_memory (sp + 24 + (ii * 4),
1648 value_contents (arg) + argbytes,
1651 ii += ((len - argbytes + 3) & -4) / 4;
1654 /* Push the rest of the arguments into stack. */
1655 for (; argno < nargs; ++argno)
1659 type = check_typedef (value_type (arg));
1660 len = TYPE_LENGTH (type);
1663 /* Float types should be passed in fpr's, as well as in the
1665 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1668 gdb_assert (len <= 8);
1670 regcache_cooked_write (regcache,
1671 tdep->ppc_fp0_regnum + 1 + f_argno,
1672 value_contents (arg));
1676 write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
1677 ii += ((len + 3) & -4) / 4;
1681 /* Set the stack pointer. According to the ABI, the SP is meant to
1682 be set _before_ the corresponding stack space is used. On AIX,
1683 this even applies when the target has been completely stopped!
1684 Not doing this can lead to conflicts with the kernel which thinks
1685 that it still has control over this not-yet-allocated stack
1687 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1689 /* Set back chain properly. */
1690 store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
1691 write_memory (sp, tmp_buffer, wordsize);
1693 /* Point the inferior function call's return address at the dummy's
1695 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1697 /* Set the TOC register, get the value from the objfile reader
1698 which, in turn, gets it from the VMAP table. */
1699 if (rs6000_find_toc_address_hook != NULL)
1701 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1702 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1705 target_store_registers (regcache, -1);
1709 static enum return_value_convention
1710 rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype,
1711 struct regcache *regcache, gdb_byte *readbuf,
1712 const gdb_byte *writebuf)
1714 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1717 /* The calling convention this function implements assumes the
1718 processor has floating-point registers. We shouldn't be using it
1719 on PowerPC variants that lack them. */
1720 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1722 /* AltiVec extension: Functions that declare a vector data type as a
1723 return value place that return value in VR2. */
1724 if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype)
1725 && TYPE_LENGTH (valtype) == 16)
1728 regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
1730 regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
1732 return RETURN_VALUE_REGISTER_CONVENTION;
1735 /* If the called subprogram returns an aggregate, there exists an
1736 implicit first argument, whose value is the address of a caller-
1737 allocated buffer into which the callee is assumed to store its
1738 return value. All explicit parameters are appropriately
1740 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1741 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1742 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1743 return RETURN_VALUE_STRUCT_CONVENTION;
1745 /* Scalar floating-point values are returned in FPR1 for float or
1746 double, and in FPR1:FPR2 for quadword precision. Fortran
1747 complex*8 and complex*16 are returned in FPR1:FPR2, and
1748 complex*32 is returned in FPR1:FPR4. */
1749 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
1750 && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8))
1752 struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
1755 /* FIXME: kettenis/2007-01-01: Add support for quadword
1756 precision and complex. */
1760 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
1761 convert_typed_floating (regval, regtype, readbuf, valtype);
1765 convert_typed_floating (writebuf, valtype, regval, regtype);
1766 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
1769 return RETURN_VALUE_REGISTER_CONVENTION;
1772 /* Values of the types int, long, short, pointer, and char (length
1773 is less than or equal to four bytes), as well as bit values of
1774 lengths less than or equal to 32 bits, must be returned right
1775 justified in GPR3 with signed values sign extended and unsigned
1776 values zero extended, as necessary. */
1777 if (TYPE_LENGTH (valtype) <= tdep->wordsize)
1783 /* For reading we don't have to worry about sign extension. */
1784 regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1786 store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval);
1790 /* For writing, use unpack_long since that should handle any
1791 required sign extension. */
1792 regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1793 unpack_long (valtype, writebuf));
1796 return RETURN_VALUE_REGISTER_CONVENTION;
1799 /* Eight-byte non-floating-point scalar values must be returned in
1802 if (TYPE_LENGTH (valtype) == 8)
1804 gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT);
1805 gdb_assert (tdep->wordsize == 4);
1811 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval);
1812 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
1814 memcpy (readbuf, regval, 8);
1818 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
1819 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
1823 return RETURN_VALUE_REGISTER_CONVENTION;
1826 return RETURN_VALUE_STRUCT_CONVENTION;
1829 /* Return whether handle_inferior_event() should proceed through code
1830 starting at PC in function NAME when stepping.
1832 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1833 handle memory references that are too distant to fit in instructions
1834 generated by the compiler. For example, if 'foo' in the following
1839 is greater than 32767, the linker might replace the lwz with a branch to
1840 somewhere in @FIX1 that does the load in 2 instructions and then branches
1841 back to where execution should continue.
1843 GDB should silently step over @FIX code, just like AIX dbx does.
1844 Unfortunately, the linker uses the "b" instruction for the
1845 branches, meaning that the link register doesn't get set.
1846 Therefore, GDB's usual step_over_function () mechanism won't work.
1848 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1849 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1853 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1855 return name && !strncmp (name, "@FIX", 4);
1858 /* Skip code that the user doesn't want to see when stepping:
1860 1. Indirect function calls use a piece of trampoline code to do context
1861 switching, i.e. to set the new TOC table. Skip such code if we are on
1862 its first instruction (as when we have single-stepped to here).
1864 2. Skip shared library trampoline code (which is different from
1865 indirect function call trampolines).
1867 3. Skip bigtoc fixup code.
1869 Result is desired PC to step until, or NULL if we are not in
1870 code that should be skipped. */
1873 rs6000_skip_trampoline_code (CORE_ADDR pc)
1875 unsigned int ii, op;
1877 CORE_ADDR solib_target_pc;
1878 struct minimal_symbol *msymbol;
1880 static unsigned trampoline_code[] =
1882 0x800b0000, /* l r0,0x0(r11) */
1883 0x90410014, /* st r2,0x14(r1) */
1884 0x7c0903a6, /* mtctr r0 */
1885 0x804b0004, /* l r2,0x4(r11) */
1886 0x816b0008, /* l r11,0x8(r11) */
1887 0x4e800420, /* bctr */
1888 0x4e800020, /* br */
1892 /* Check for bigtoc fixup code. */
1893 msymbol = lookup_minimal_symbol_by_pc (pc);
1895 && rs6000_in_solib_return_trampoline (pc,
1896 DEPRECATED_SYMBOL_NAME (msymbol)))
1898 /* Double-check that the third instruction from PC is relative "b". */
1899 op = read_memory_integer (pc + 8, 4);
1900 if ((op & 0xfc000003) == 0x48000000)
1902 /* Extract bits 6-29 as a signed 24-bit relative word address and
1903 add it to the containing PC. */
1904 rel = ((int)(op << 6) >> 6);
1905 return pc + 8 + rel;
1909 /* If pc is in a shared library trampoline, return its target. */
1910 solib_target_pc = find_solib_trampoline_target (pc);
1911 if (solib_target_pc)
1912 return solib_target_pc;
1914 for (ii = 0; trampoline_code[ii]; ++ii)
1916 op = read_memory_integer (pc + (ii * 4), 4);
1917 if (op != trampoline_code[ii])
1920 ii = read_register (11); /* r11 holds destination addr */
1921 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1925 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1926 isn't available with that word size, return 0. */
1929 regsize (const struct reg *reg, int wordsize)
1931 return wordsize == 8 ? reg->sz64 : reg->sz32;
1934 /* Return the name of register number N, or null if no such register exists
1935 in the current architecture. */
1938 rs6000_register_name (int n)
1940 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1941 const struct reg *reg = tdep->regs + n;
1943 if (!regsize (reg, tdep->wordsize))
1948 /* Return the GDB type object for the "standard" data type
1949 of data in register N. */
1951 static struct type *
1952 rs6000_register_type (struct gdbarch *gdbarch, int n)
1954 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1955 const struct reg *reg = tdep->regs + n;
1958 return builtin_type_double;
1961 int size = regsize (reg, tdep->wordsize);
1965 return builtin_type_int0;
1967 return builtin_type_uint32;
1969 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1970 return builtin_type_vec64;
1972 return builtin_type_uint64;
1975 return builtin_type_vec128;
1978 internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"),
1984 /* Is REGNUM a member of REGGROUP? */
1986 rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1987 struct reggroup *group)
1989 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1994 if (REGISTER_NAME (regnum) == NULL
1995 || *REGISTER_NAME (regnum) == '\0')
1997 if (group == all_reggroup)
2000 float_p = (regnum == tdep->ppc_fpscr_regnum
2001 || (regnum >= tdep->ppc_fp0_regnum
2002 && regnum < tdep->ppc_fp0_regnum + 32));
2003 if (group == float_reggroup)
2006 vector_p = ((tdep->ppc_vr0_regnum >= 0
2007 && regnum >= tdep->ppc_vr0_regnum
2008 && regnum < tdep->ppc_vr0_regnum + 32)
2009 || (tdep->ppc_ev0_regnum >= 0
2010 && regnum >= tdep->ppc_ev0_regnum
2011 && regnum < tdep->ppc_ev0_regnum + 32)
2012 || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */
2013 || regnum == tdep->ppc_vrsave_regnum
2014 || regnum == tdep->ppc_acc_regnum
2015 || regnum == tdep->ppc_spefscr_regnum);
2016 if (group == vector_reggroup)
2019 /* Note that PS aka MSR isn't included - it's a system register (and
2020 besides, due to GCC's CFI foobar you do not want to restore
2022 general_p = ((regnum >= tdep->ppc_gp0_regnum
2023 && regnum < tdep->ppc_gp0_regnum + 32)
2024 || regnum == tdep->ppc_toc_regnum
2025 || regnum == tdep->ppc_cr_regnum
2026 || regnum == tdep->ppc_lr_regnum
2027 || regnum == tdep->ppc_ctr_regnum
2028 || regnum == tdep->ppc_xer_regnum
2029 || regnum == PC_REGNUM);
2030 if (group == general_reggroup)
2033 if (group == save_reggroup || group == restore_reggroup)
2034 return general_p || vector_p || float_p;
2039 /* The register format for RS/6000 floating point registers is always
2040 double, we need a conversion if the memory format is float. */
2043 rs6000_convert_register_p (int regnum, struct type *type)
2045 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2048 && TYPE_CODE (type) == TYPE_CODE_FLT
2049 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2053 rs6000_register_to_value (struct frame_info *frame,
2058 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2059 gdb_byte from[MAX_REGISTER_SIZE];
2061 gdb_assert (reg->fpr);
2062 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2064 get_frame_register (frame, regnum, from);
2065 convert_typed_floating (from, builtin_type_double, to, type);
2069 rs6000_value_to_register (struct frame_info *frame,
2072 const gdb_byte *from)
2074 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2075 gdb_byte to[MAX_REGISTER_SIZE];
2077 gdb_assert (reg->fpr);
2078 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2080 convert_typed_floating (from, type, to, builtin_type_double);
2081 put_frame_register (frame, regnum, to);
2084 /* Move SPE vector register values between a 64-bit buffer and the two
2085 32-bit raw register halves in a regcache. This function handles
2086 both splitting a 64-bit value into two 32-bit halves, and joining
2087 two halves into a whole 64-bit value, depending on the function
2088 passed as the MOVE argument.
2090 EV_REG must be the number of an SPE evN vector register --- a
2091 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2094 Call MOVE once for each 32-bit half of that register, passing
2095 REGCACHE, the number of the raw register corresponding to that
2096 half, and the address of the appropriate half of BUFFER.
2098 For example, passing 'regcache_raw_read' as the MOVE function will
2099 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2100 'regcache_raw_supply' will supply the contents of BUFFER to the
2101 appropriate pair of raw registers in REGCACHE.
2103 You may need to cast away some 'const' qualifiers when passing
2104 MOVE, since this function can't tell at compile-time which of
2105 REGCACHE or BUFFER is acting as the source of the data. If C had
2106 co-variant type qualifiers, ... */
2108 e500_move_ev_register (void (*move) (struct regcache *regcache,
2109 int regnum, gdb_byte *buf),
2110 struct regcache *regcache, int ev_reg,
2113 struct gdbarch *arch = get_regcache_arch (regcache);
2114 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2116 gdb_byte *byte_buffer = buffer;
2118 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
2119 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
2121 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2123 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2125 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2126 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2130 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2131 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2136 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2137 int reg_nr, gdb_byte *buffer)
2139 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2140 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2142 gdb_assert (regcache_arch == gdbarch);
2144 if (tdep->ppc_ev0_regnum <= reg_nr
2145 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2146 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2148 internal_error (__FILE__, __LINE__,
2149 _("e500_pseudo_register_read: "
2150 "called on unexpected register '%s' (%d)"),
2151 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2155 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2156 int reg_nr, const gdb_byte *buffer)
2158 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2159 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2161 gdb_assert (regcache_arch == gdbarch);
2163 if (tdep->ppc_ev0_regnum <= reg_nr
2164 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2165 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2167 regcache, reg_nr, (gdb_byte *) buffer);
2169 internal_error (__FILE__, __LINE__,
2170 _("e500_pseudo_register_read: "
2171 "called on unexpected register '%s' (%d)"),
2172 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2175 /* The E500 needs a custom reggroup function: it has anonymous raw
2176 registers, and default_register_reggroup_p assumes that anonymous
2177 registers are not members of any reggroup. */
2179 e500_register_reggroup_p (struct gdbarch *gdbarch,
2181 struct reggroup *group)
2183 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2185 /* The save and restore register groups need to include the
2186 upper-half registers, even though they're anonymous. */
2187 if ((group == save_reggroup
2188 || group == restore_reggroup)
2189 && (tdep->ppc_ev0_upper_regnum <= regnum
2190 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
2193 /* In all other regards, the default reggroup definition is fine. */
2194 return default_register_reggroup_p (gdbarch, regnum, group);
2197 /* Convert a DBX STABS register number to a GDB register number. */
2199 rs6000_stab_reg_to_regnum (int num)
2201 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2203 if (0 <= num && num <= 31)
2204 return tdep->ppc_gp0_regnum + num;
2205 else if (32 <= num && num <= 63)
2206 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2207 specifies registers the architecture doesn't have? Our
2208 callers don't check the value we return. */
2209 return tdep->ppc_fp0_regnum + (num - 32);
2210 else if (77 <= num && num <= 108)
2211 return tdep->ppc_vr0_regnum + (num - 77);
2212 else if (1200 <= num && num < 1200 + 32)
2213 return tdep->ppc_ev0_regnum + (num - 1200);
2218 return tdep->ppc_mq_regnum;
2220 return tdep->ppc_lr_regnum;
2222 return tdep->ppc_ctr_regnum;
2224 return tdep->ppc_xer_regnum;
2226 return tdep->ppc_vrsave_regnum;
2228 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2230 return tdep->ppc_acc_regnum;
2232 return tdep->ppc_spefscr_regnum;
2239 /* Convert a Dwarf 2 register number to a GDB register number. */
2241 rs6000_dwarf2_reg_to_regnum (int num)
2243 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2245 if (0 <= num && num <= 31)
2246 return tdep->ppc_gp0_regnum + num;
2247 else if (32 <= num && num <= 63)
2248 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2249 specifies registers the architecture doesn't have? Our
2250 callers don't check the value we return. */
2251 return tdep->ppc_fp0_regnum + (num - 32);
2252 else if (1124 <= num && num < 1124 + 32)
2253 return tdep->ppc_vr0_regnum + (num - 1124);
2254 else if (1200 <= num && num < 1200 + 32)
2255 return tdep->ppc_ev0_regnum + (num - 1200);
2260 return tdep->ppc_cr_regnum;
2262 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2264 return tdep->ppc_acc_regnum;
2266 return tdep->ppc_mq_regnum;
2268 return tdep->ppc_xer_regnum;
2270 return tdep->ppc_lr_regnum;
2272 return tdep->ppc_ctr_regnum;
2274 return tdep->ppc_vrsave_regnum;
2276 return tdep->ppc_spefscr_regnum;
2282 /* Translate a .eh_frame register to DWARF register, or adjust a
2283 .debug_frame register. */
2286 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2288 /* GCC releases before 3.4 use GCC internal register numbering in
2289 .debug_frame (and .debug_info, et cetera). The numbering is
2290 different from the standard SysV numbering for everything except
2291 for GPRs and FPRs. We can not detect this problem in most cases
2292 - to get accurate debug info for variables living in lr, ctr, v0,
2293 et cetera, use a newer version of GCC. But we must detect
2294 one important case - lr is in column 65 in .debug_frame output,
2297 GCC 3.4, and the "hammer" branch, have a related problem. They
2298 record lr register saves in .debug_frame as 108, but still record
2299 the return column as 65. We fix that up too.
2301 We can do this because 65 is assigned to fpsr, and GCC never
2302 generates debug info referring to it. To add support for
2303 handwritten debug info that restores fpsr, we would need to add a
2304 producer version check to this. */
2313 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2314 internal register numbering; translate that to the standard DWARF2
2315 register numbering. */
2316 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2318 else if (68 <= num && num <= 75) /* cr0-cr8 */
2319 return num - 68 + 86;
2320 else if (77 <= num && num <= 108) /* vr0-vr31 */
2321 return num - 77 + 1124;
2333 case 109: /* vrsave */
2335 case 110: /* vscr */
2337 case 111: /* spe_acc */
2339 case 112: /* spefscr */
2346 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2348 Usually a function pointer's representation is simply the address
2349 of the function. On the RS/6000 however, a function pointer is
2350 represented by a pointer to an OPD entry. This OPD entry contains
2351 three words, the first word is the address of the function, the
2352 second word is the TOC pointer (r2), and the third word is the
2353 static chain value. Throughout GDB it is currently assumed that a
2354 function pointer contains the address of the function, which is not
2355 easy to fix. In addition, the conversion of a function address to
2356 a function pointer would require allocation of an OPD entry in the
2357 inferior's memory space, with all its drawbacks. To be able to
2358 call C++ virtual methods in the inferior (which are called via
2359 function pointers), find_function_addr uses this function to get the
2360 function address from a function pointer. */
2362 /* Return real function address if ADDR (a function pointer) is in the data
2363 space and is therefore a special function pointer. */
2366 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2368 struct target_ops *targ)
2370 struct obj_section *s;
2372 s = find_pc_section (addr);
2373 if (s && s->the_bfd_section->flags & SEC_CODE)
2376 /* ADDR is in the data space, so it's a special function pointer. */
2377 return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize);
2381 /* Handling the various POWER/PowerPC variants. */
2384 /* The arrays here called registers_MUMBLE hold information about available
2387 For each family of PPC variants, I've tried to isolate out the
2388 common registers and put them up front, so that as long as you get
2389 the general family right, GDB will correctly identify the registers
2390 common to that family. The common register sets are:
2392 For the 60x family: hid0 hid1 iabr dabr pir
2394 For the 505 and 860 family: eie eid nri
2396 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2397 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2400 Most of these register groups aren't anything formal. I arrived at
2401 them by looking at the registers that occurred in more than one
2404 Note: kevinb/2002-04-30: Support for the fpscr register was added
2405 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2406 for Power. For PowerPC, slot 70 was unused and was already in the
2407 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2408 slot 70 was being used for "mq", so the next available slot (71)
2409 was chosen. It would have been nice to be able to make the
2410 register numbers the same across processor cores, but this wasn't
2411 possible without either 1) renumbering some registers for some
2412 processors or 2) assigning fpscr to a really high slot that's
2413 larger than any current register number. Doing (1) is bad because
2414 existing stubs would break. Doing (2) is undesirable because it
2415 would introduce a really large gap between fpscr and the rest of
2416 the registers for most processors. */
2418 /* Convenience macros for populating register arrays. */
2420 /* Within another macro, convert S to a string. */
2424 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2425 and 64 bits on 64-bit systems. */
2426 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2428 /* Return a struct reg defining register NAME that's 32 bits on all
2430 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2432 /* Return a struct reg defining register NAME that's 64 bits on all
2434 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2436 /* Return a struct reg defining register NAME that's 128 bits on all
2438 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2440 /* Return a struct reg defining floating-point register NAME. */
2441 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2443 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2444 long on all systems. */
2445 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2447 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2448 systems and that doesn't exist on 64-bit systems. */
2449 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2451 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2452 systems and that doesn't exist on 32-bit systems. */
2453 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2455 /* Return a struct reg placeholder for a register that doesn't exist. */
2456 #define R0 { 0, 0, 0, 0, 0, -1 }
2458 /* Return a struct reg defining an anonymous raw register that's 32
2459 bits on all systems. */
2460 #define A4 { 0, 4, 4, 0, 0, -1 }
2462 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2463 32-bit systems and 64 bits on 64-bit systems. */
2464 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2466 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2468 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2470 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2471 all systems, and whose SPR number is NUMBER. */
2472 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2474 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2475 64-bit systems and that doesn't exist on 32-bit systems. */
2476 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2478 /* UISA registers common across all architectures, including POWER. */
2480 #define COMMON_UISA_REGS \
2481 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2482 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2483 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2484 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2485 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2486 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2487 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2488 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2489 /* 64 */ R(pc), R(ps)
2491 /* UISA-level SPRs for PowerPC. */
2492 #define PPC_UISA_SPRS \
2493 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2495 /* UISA-level SPRs for PowerPC without floating point support. */
2496 #define PPC_UISA_NOFP_SPRS \
2497 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2499 /* Segment registers, for PowerPC. */
2500 #define PPC_SEGMENT_REGS \
2501 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2502 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2503 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2504 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2506 /* OEA SPRs for PowerPC. */
2507 #define PPC_OEA_SPRS \
2509 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2510 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2511 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2512 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2513 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2514 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2515 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2516 /* 116 */ S4(dec), S(dabr), S4(ear)
2518 /* AltiVec registers. */
2519 #define PPC_ALTIVEC_REGS \
2520 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2521 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2522 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2523 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2524 /*151*/R4(vscr), R4(vrsave)
2527 /* On machines supporting the SPE APU, the general-purpose registers
2528 are 64 bits long. There are SIMD vector instructions to treat them
2529 as pairs of floats, but the rest of the instruction set treats them
2530 as 32-bit registers, and only operates on their lower halves.
2532 In the GDB regcache, we treat their high and low halves as separate
2533 registers. The low halves we present as the general-purpose
2534 registers, and then we have pseudo-registers that stitch together
2535 the upper and lower halves and present them as pseudo-registers. */
2537 /* SPE GPR lower halves --- raw registers. */
2538 #define PPC_SPE_GP_REGS \
2539 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2540 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2541 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2542 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2544 /* SPE GPR upper halves --- anonymous raw registers. */
2545 #define PPC_SPE_UPPER_GP_REGS \
2546 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2547 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2548 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2549 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2551 /* SPE GPR vector registers --- pseudo registers based on underlying
2552 gprs and the anonymous upper half raw registers. */
2553 #define PPC_EV_PSEUDO_REGS \
2554 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2555 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2556 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2557 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2559 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2560 user-level SPR's. */
2561 static const struct reg registers_power[] =
2564 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
2568 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2569 view of the PowerPC. */
2570 static const struct reg registers_powerpc[] =
2579 Some notes about the "tcr" special-purpose register:
2580 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2581 403's programmable interval timer, fixed interval timer, and
2583 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2584 watchdog timer, and nothing else.
2586 Some of the fields are similar between the two, but they're not
2587 compatible with each other. Since the two variants have different
2588 registers, with different numbers, but the same name, we can't
2589 splice the register name to get the SPR number. */
2590 static const struct reg registers_403[] =
2596 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2597 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2598 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2599 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2600 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2601 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
2604 /* IBM PowerPC 403GC.
2605 See the comments about 'tcr' for the 403, above. */
2606 static const struct reg registers_403GC[] =
2612 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2613 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2614 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2615 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2616 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2617 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
2618 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
2619 /* 147 */ S(tbhu), S(tblu)
2622 /* Motorola PowerPC 505. */
2623 static const struct reg registers_505[] =
2629 /* 119 */ S(eie), S(eid), S(nri)
2632 /* Motorola PowerPC 860 or 850. */
2633 static const struct reg registers_860[] =
2639 /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
2640 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
2641 /* 127 */ S(der), S(counta), S(countb), S(cmpe),
2642 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
2643 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
2644 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
2645 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
2646 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
2647 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
2648 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
2649 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
2650 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
2653 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2654 for reading and writing RTCU and RTCL. However, how one reads and writes a
2655 register is the stub's problem. */
2656 static const struct reg registers_601[] =
2662 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2663 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
2666 /* Motorola PowerPC 602.
2667 See the notes under the 403 about 'tcr'. */
2668 static const struct reg registers_602[] =
2674 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2675 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
2676 /* 127 */ S(sebr), S(ser), S(sp), S(lt)
2679 /* Motorola/IBM PowerPC 603 or 603e. */
2680 static const struct reg registers_603[] =
2686 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2687 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
2688 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
2691 /* Motorola PowerPC 604 or 604e. */
2692 static const struct reg registers_604[] =
2698 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2699 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
2700 /* 127 */ S(sia), S(sda)
2703 /* Motorola/IBM PowerPC 750 or 740. */
2704 static const struct reg registers_750[] =
2710 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2711 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
2712 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
2713 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
2714 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
2715 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
2719 /* Motorola PowerPC 7400. */
2720 static const struct reg registers_7400[] =
2722 /* gpr0-gpr31, fpr0-fpr31 */
2724 /* cr, lr, ctr, xer, fpscr */
2729 /* vr0-vr31, vrsave, vscr */
2731 /* FIXME? Add more registers? */
2734 /* Motorola e500. */
2735 static const struct reg registers_e500[] =
2737 /* 0 .. 31 */ PPC_SPE_GP_REGS,
2738 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
2739 /* 64 .. 65 */ R(pc), R(ps),
2740 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
2741 /* 71 .. 72 */ R8(acc), S4(spefscr),
2742 /* NOTE: Add new registers here the end of the raw register
2743 list and just before the first pseudo register. */
2744 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2747 /* Information about a particular processor variant. */
2751 /* Name of this variant. */
2754 /* English description of the variant. */
2757 /* bfd_arch_info.arch corresponding to variant. */
2758 enum bfd_architecture arch;
2760 /* bfd_arch_info.mach corresponding to variant. */
2763 /* Number of real registers. */
2766 /* Number of pseudo registers. */
2769 /* Number of total registers (the sum of nregs and npregs). */
2772 /* Table of register names; registers[R] is the name of the register
2774 const struct reg *regs;
2777 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2780 num_registers (const struct reg *reg_list, int num_tot_regs)
2785 for (i = 0; i < num_tot_regs; i++)
2786 if (!reg_list[i].pseudo)
2793 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2798 for (i = 0; i < num_tot_regs; i++)
2799 if (reg_list[i].pseudo)
2805 /* Information in this table comes from the following web sites:
2806 IBM: http://www.chips.ibm.com:80/products/embedded/
2807 Motorola: http://www.mot.com/SPS/PowerPC/
2809 I'm sure I've got some of the variant descriptions not quite right.
2810 Please report any inaccuracies you find to GDB's maintainer.
2812 If you add entries to this table, please be sure to allow the new
2813 value as an argument to the --with-cpu flag, in configure.in. */
2815 static struct variant variants[] =
2818 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2819 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2821 {"power", "POWER user-level", bfd_arch_rs6000,
2822 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2824 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2825 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2827 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2828 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2830 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2831 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2833 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2834 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2836 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2837 604, -1, -1, tot_num_registers (registers_604),
2839 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2840 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2842 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2843 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2845 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2846 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2848 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2849 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2851 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2852 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2854 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2855 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2859 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2860 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2862 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2863 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2865 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2866 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2868 {"a35", "PowerPC A35", bfd_arch_powerpc,
2869 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2871 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2872 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2874 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2875 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2878 /* FIXME: I haven't checked the register sets of the following. */
2879 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2880 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2882 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2883 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2885 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2886 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2889 {0, 0, 0, 0, 0, 0, 0, 0}
2892 /* Initialize the number of registers and pseudo registers in each variant. */
2895 init_variants (void)
2899 for (v = variants; v->name; v++)
2902 v->nregs = num_registers (v->regs, v->num_tot_regs);
2903 if (v->npregs == -1)
2904 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2908 /* Return the variant corresponding to architecture ARCH and machine number
2909 MACH. If no such variant exists, return null. */
2911 static const struct variant *
2912 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2914 const struct variant *v;
2916 for (v = variants; v->name; v++)
2917 if (arch == v->arch && mach == v->mach)
2924 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2926 if (!info->disassembler_options)
2927 info->disassembler_options = "any";
2929 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2930 return print_insn_big_powerpc (memaddr, info);
2932 return print_insn_little_powerpc (memaddr, info);
2936 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2938 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2941 static struct frame_id
2942 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2944 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2946 frame_pc_unwind (next_frame));
2949 struct rs6000_frame_cache
2952 CORE_ADDR initial_sp;
2953 struct trad_frame_saved_reg *saved_regs;
2956 static struct rs6000_frame_cache *
2957 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2959 struct rs6000_frame_cache *cache;
2960 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2961 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2962 struct rs6000_framedata fdata;
2963 int wordsize = tdep->wordsize;
2966 if ((*this_cache) != NULL)
2967 return (*this_cache);
2968 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2969 (*this_cache) = cache;
2970 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2972 func = frame_func_unwind (next_frame, NORMAL_FRAME);
2973 pc = frame_pc_unwind (next_frame);
2974 skip_prologue (func, pc, &fdata);
2976 /* Figure out the parent's stack pointer. */
2978 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2979 address of the current frame. Things might be easier if the
2980 ->frame pointed to the outer-most address of the frame. In
2981 the mean time, the address of the prev frame is used as the
2982 base address of this frame. */
2983 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2985 /* If the function appears to be frameless, check a couple of likely
2986 indicators that we have simply failed to find the frame setup.
2987 Two common cases of this are missing symbols (i.e.
2988 frame_func_unwind returns the wrong address or 0), and assembly
2989 stubs which have a fast exit path but set up a frame on the slow
2992 If the LR appears to return to this function, then presume that
2993 we have an ABI compliant frame that we failed to find. */
2994 if (fdata.frameless && fdata.lr_offset == 0)
2999 saved_lr = frame_unwind_register_unsigned (next_frame,
3000 tdep->ppc_lr_regnum);
3001 if (func == 0 && saved_lr == pc)
3005 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3006 if (func == saved_func)
3012 fdata.frameless = 0;
3013 fdata.lr_offset = tdep->lr_frame_offset;
3017 if (!fdata.frameless)
3018 /* Frameless really means stackless. */
3019 cache->base = read_memory_addr (cache->base, wordsize);
3021 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
3023 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3024 All fpr's from saved_fpr to fp31 are saved. */
3026 if (fdata.saved_fpr >= 0)
3029 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3031 /* If skip_prologue says floating-point registers were saved,
3032 but the current architecture has no floating-point registers,
3033 then that's strange. But we have no indices to even record
3034 the addresses under, so we just ignore it. */
3035 if (ppc_floating_point_unit_p (gdbarch))
3036 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3038 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3043 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3044 All gpr's from saved_gpr to gpr31 are saved. */
3046 if (fdata.saved_gpr >= 0)
3049 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3050 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3052 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3053 gpr_addr += wordsize;
3057 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3058 All vr's from saved_vr to vr31 are saved. */
3059 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3061 if (fdata.saved_vr >= 0)
3064 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3065 for (i = fdata.saved_vr; i < 32; i++)
3067 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3068 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3073 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3074 All vr's from saved_ev to ev31 are saved. ????? */
3075 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
3077 if (fdata.saved_ev >= 0)
3080 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3081 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3083 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3084 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3085 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3090 /* If != 0, fdata.cr_offset is the offset from the frame that
3092 if (fdata.cr_offset != 0)
3093 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3095 /* If != 0, fdata.lr_offset is the offset from the frame that
3097 if (fdata.lr_offset != 0)
3098 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
3099 /* The PC is found in the link register. */
3100 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
3102 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3103 holds the VRSAVE. */
3104 if (fdata.vrsave_offset != 0)
3105 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3107 if (fdata.alloca_reg < 0)
3108 /* If no alloca register used, then fi->frame is the value of the
3109 %sp for this frame, and it is good enough. */
3110 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
3112 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3119 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3120 struct frame_id *this_id)
3122 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3124 (*this_id) = frame_id_build (info->base,
3125 frame_func_unwind (next_frame, NORMAL_FRAME));
3129 rs6000_frame_prev_register (struct frame_info *next_frame,
3131 int regnum, int *optimizedp,
3132 enum lval_type *lvalp, CORE_ADDR *addrp,
3133 int *realnump, gdb_byte *valuep)
3135 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3137 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3138 optimizedp, lvalp, addrp, realnump, valuep);
3141 static const struct frame_unwind rs6000_frame_unwind =
3144 rs6000_frame_this_id,
3145 rs6000_frame_prev_register
3148 static const struct frame_unwind *
3149 rs6000_frame_sniffer (struct frame_info *next_frame)
3151 return &rs6000_frame_unwind;
3157 rs6000_frame_base_address (struct frame_info *next_frame,
3160 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3162 return info->initial_sp;
3165 static const struct frame_base rs6000_frame_base = {
3166 &rs6000_frame_unwind,
3167 rs6000_frame_base_address,
3168 rs6000_frame_base_address,
3169 rs6000_frame_base_address
3172 static const struct frame_base *
3173 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3175 return &rs6000_frame_base;
3178 /* Initialize the current architecture based on INFO. If possible, re-use an
3179 architecture from ARCHES, which is a list of architectures already created
3180 during this debugging session.
3182 Called e.g. at program startup, when reading a core file, and when reading
3185 static struct gdbarch *
3186 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3188 struct gdbarch *gdbarch;
3189 struct gdbarch_tdep *tdep;
3190 int wordsize, from_xcoff_exec, from_elf_exec, i, off;
3192 const struct variant *v;
3193 enum bfd_architecture arch;
3199 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3200 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3202 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3203 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3205 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3207 /* Check word size. If INFO is from a binary file, infer it from
3208 that, else choose a likely default. */
3209 if (from_xcoff_exec)
3211 if (bfd_xcoff_is_xcoff64 (info.abfd))
3216 else if (from_elf_exec)
3218 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3225 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3226 wordsize = info.bfd_arch_info->bits_per_word /
3227 info.bfd_arch_info->bits_per_byte;
3232 /* Find a candidate among extant architectures. */
3233 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3235 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3237 /* Word size in the various PowerPC bfd_arch_info structs isn't
3238 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3239 separate word size check. */
3240 tdep = gdbarch_tdep (arches->gdbarch);
3241 if (tdep && tdep->wordsize == wordsize)
3242 return arches->gdbarch;
3245 /* None found, create a new architecture from INFO, whose bfd_arch_info
3246 validity depends on the source:
3247 - executable useless
3248 - rs6000_host_arch() good
3250 - "set arch" trust blindly
3251 - GDB startup useless but harmless */
3253 if (!from_xcoff_exec)
3255 arch = info.bfd_arch_info->arch;
3256 mach = info.bfd_arch_info->mach;
3260 arch = bfd_arch_powerpc;
3261 bfd_default_set_arch_mach (&abfd, arch, 0);
3262 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3263 mach = info.bfd_arch_info->mach;
3265 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3266 tdep->wordsize = wordsize;
3268 /* For e500 executables, the apuinfo section is of help here. Such
3269 section contains the identifier and revision number of each
3270 Application-specific Processing Unit that is present on the
3271 chip. The content of the section is determined by the assembler
3272 which looks at each instruction and determines which unit (and
3273 which version of it) can execute it. In our case we just look for
3274 the existance of the section. */
3278 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3281 arch = info.bfd_arch_info->arch;
3282 mach = bfd_mach_ppc_e500;
3283 bfd_default_set_arch_mach (&abfd, arch, mach);
3284 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3288 gdbarch = gdbarch_alloc (&info, tdep);
3290 /* Initialize the number of real and pseudo registers in each variant. */
3293 /* Choose variant. */
3294 v = find_variant_by_arch (arch, mach);
3298 tdep->regs = v->regs;
3300 tdep->ppc_gp0_regnum = 0;
3301 tdep->ppc_toc_regnum = 2;
3302 tdep->ppc_ps_regnum = 65;
3303 tdep->ppc_cr_regnum = 66;
3304 tdep->ppc_lr_regnum = 67;
3305 tdep->ppc_ctr_regnum = 68;
3306 tdep->ppc_xer_regnum = 69;
3307 if (v->mach == bfd_mach_ppc_601)
3308 tdep->ppc_mq_regnum = 124;
3309 else if (arch == bfd_arch_rs6000)
3310 tdep->ppc_mq_regnum = 70;
3312 tdep->ppc_mq_regnum = -1;
3313 tdep->ppc_fp0_regnum = 32;
3314 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
3315 tdep->ppc_sr0_regnum = 71;
3316 tdep->ppc_vr0_regnum = -1;
3317 tdep->ppc_vrsave_regnum = -1;
3318 tdep->ppc_ev0_upper_regnum = -1;
3319 tdep->ppc_ev0_regnum = -1;
3320 tdep->ppc_ev31_regnum = -1;
3321 tdep->ppc_acc_regnum = -1;
3322 tdep->ppc_spefscr_regnum = -1;
3324 set_gdbarch_pc_regnum (gdbarch, 64);
3325 set_gdbarch_sp_regnum (gdbarch, 1);
3326 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
3327 set_gdbarch_fp0_regnum (gdbarch, 32);
3328 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3329 if (sysv_abi && wordsize == 8)
3330 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3331 else if (sysv_abi && wordsize == 4)
3332 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3334 set_gdbarch_return_value (gdbarch, rs6000_return_value);
3336 /* Set lr_frame_offset. */
3338 tdep->lr_frame_offset = 16;
3340 tdep->lr_frame_offset = 4;
3342 tdep->lr_frame_offset = 8;
3344 if (v->arch == bfd_arch_rs6000)
3345 tdep->ppc_sr0_regnum = -1;
3346 else if (v->arch == bfd_arch_powerpc)
3350 tdep->ppc_sr0_regnum = -1;
3351 tdep->ppc_vr0_regnum = 71;
3352 tdep->ppc_vrsave_regnum = 104;
3354 case bfd_mach_ppc_7400:
3355 tdep->ppc_vr0_regnum = 119;
3356 tdep->ppc_vrsave_regnum = 152;
3358 case bfd_mach_ppc_e500:
3359 tdep->ppc_toc_regnum = -1;
3360 tdep->ppc_ev0_upper_regnum = 32;
3361 tdep->ppc_ev0_regnum = 73;
3362 tdep->ppc_ev31_regnum = 104;
3363 tdep->ppc_acc_regnum = 71;
3364 tdep->ppc_spefscr_regnum = 72;
3365 tdep->ppc_fp0_regnum = -1;
3366 tdep->ppc_fpscr_regnum = -1;
3367 tdep->ppc_sr0_regnum = -1;
3368 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3369 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3370 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
3373 case bfd_mach_ppc64:
3374 case bfd_mach_ppc_620:
3375 case bfd_mach_ppc_630:
3376 case bfd_mach_ppc_a35:
3377 case bfd_mach_ppc_rs64ii:
3378 case bfd_mach_ppc_rs64iii:
3379 /* These processor's register sets don't have segment registers. */
3380 tdep->ppc_sr0_regnum = -1;
3384 internal_error (__FILE__, __LINE__,
3385 _("rs6000_gdbarch_init: "
3386 "received unexpected BFD 'arch' value"));
3388 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3390 /* Sanity check on registers. */
3391 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
3393 /* Select instruction printer. */
3394 if (arch == bfd_arch_rs6000)
3395 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3397 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3399 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
3401 set_gdbarch_num_regs (gdbarch, v->nregs);
3402 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
3403 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3404 set_gdbarch_register_type (gdbarch, rs6000_register_type);
3405 set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p);
3407 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3408 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3409 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3410 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3411 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3412 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3413 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3415 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3417 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3418 set_gdbarch_char_signed (gdbarch, 0);
3420 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3421 if (sysv_abi && wordsize == 8)
3423 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3424 else if (!sysv_abi && wordsize == 4)
3425 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3426 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3427 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3429 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3431 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3432 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3433 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3435 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3436 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3438 if (sysv_abi && wordsize == 4)
3439 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3440 else if (sysv_abi && wordsize == 8)
3441 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3443 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3445 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3446 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3448 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3449 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3451 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3452 for the descriptor and ".FN" for the entry-point -- a user
3453 specifying "break FN" will unexpectedly end up with a breakpoint
3454 on the descriptor and not the function. This architecture method
3455 transforms any breakpoints on descriptors into breakpoints on the
3456 corresponding entry point. */
3457 if (sysv_abi && wordsize == 8)
3458 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3460 /* Not sure on this. FIXMEmgo */
3461 set_gdbarch_frame_args_skip (gdbarch, 8);
3465 /* Handle RS/6000 function pointers (which are really function
3467 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3468 rs6000_convert_from_func_ptr_addr);
3471 /* Helpers for function argument information. */
3472 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3475 set_gdbarch_in_solib_return_trampoline
3476 (gdbarch, rs6000_in_solib_return_trampoline);
3477 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3479 /* Hook in the DWARF CFI frame unwinder. */
3480 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3481 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3483 /* Hook in ABI-specific overrides, if they have been registered. */
3484 gdbarch_init_osabi (info, gdbarch);
3488 case GDB_OSABI_LINUX:
3489 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3490 have altivec registers. If not, ptrace will fail the first time it's
3491 called to access one and will not be called again. This wart will
3492 be removed when Daniel Jacobowitz's proposal for autodetecting target
3493 registers is implemented. */
3494 if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64))
3496 tdep->ppc_vr0_regnum = 71;
3497 tdep->ppc_vrsave_regnum = 104;
3500 case GDB_OSABI_NETBSD_AOUT:
3501 case GDB_OSABI_NETBSD_ELF:
3502 case GDB_OSABI_UNKNOWN:
3503 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3504 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3505 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3506 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3509 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3511 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3512 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3513 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3514 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3517 init_sim_regno_table (gdbarch);
3523 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3525 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3530 /* FIXME: Dump gdbarch_tdep. */
3533 /* Initialization code. */
3535 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3538 _initialize_rs6000_tdep (void)
3540 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3541 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);