1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "libbfd.h" /* for bfd_default_set_arch_mach */
41 #include "coff/internal.h" /* for libcoff.h */
42 #include "libcoff.h" /* for xcoff_data */
43 #include "coff/xcoff.h"
48 #include "solib-svr4.h"
51 #include "gdb_assert.h"
54 #include "trad-frame.h"
55 #include "frame-unwind.h"
56 #include "frame-base.h"
58 /* If the kernel has to deliver a signal, it pushes a sigcontext
59 structure on the stack and then calls the signal handler, passing
60 the address of the sigcontext in an argument register. Usually
61 the signal handler doesn't save this register, so we have to
62 access the sigcontext structure via an offset from the signal handler
64 The following constants were determined by experimentation on AIX 3.2. */
65 #define SIG_FRAME_PC_OFFSET 96
66 #define SIG_FRAME_LR_OFFSET 108
67 #define SIG_FRAME_FP_OFFSET 284
69 /* To be used by skip_prologue. */
71 struct rs6000_framedata
73 int offset; /* total size of frame --- the distance
74 by which we decrement sp to allocate
76 int saved_gpr; /* smallest # of saved gpr */
77 int saved_fpr; /* smallest # of saved fpr */
78 int saved_vr; /* smallest # of saved vr */
79 int saved_ev; /* smallest # of saved ev */
80 int alloca_reg; /* alloca register number (frame ptr) */
81 char frameless; /* true if frameless functions. */
82 char nosavedpc; /* true if pc not saved. */
83 int gpr_offset; /* offset of saved gprs from prev sp */
84 int fpr_offset; /* offset of saved fprs from prev sp */
85 int vr_offset; /* offset of saved vrs from prev sp */
86 int ev_offset; /* offset of saved evs from prev sp */
87 int lr_offset; /* offset of saved lr */
88 int cr_offset; /* offset of saved cr */
89 int vrsave_offset; /* offset of saved vrsave register */
92 /* Description of a single register. */
96 char *name; /* name of register */
97 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
98 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
99 unsigned char fpr; /* whether register is floating-point */
100 unsigned char pseudo; /* whether register is pseudo */
103 /* Breakpoint shadows for the single step instructions will be kept here. */
105 static struct sstep_breaks
107 /* Address, or 0 if this is not in use. */
109 /* Shadow contents. */
114 /* Hook for determining the TOC address when calling functions in the
115 inferior under AIX. The initialization code in rs6000-nat.c sets
116 this hook to point to find_toc_address. */
118 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
120 /* Hook to set the current architecture when starting a child process.
121 rs6000-nat.c sets this. */
123 void (*rs6000_set_host_arch_hook) (int) = NULL;
125 /* Static function prototypes */
127 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
129 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
130 struct rs6000_framedata *);
132 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
134 altivec_register_p (int regno)
136 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
137 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
140 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
144 /* Return non-zero if the architecture described by GDBARCH has
145 floating-point registers (f0 --- f31 and fpscr). */
147 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
149 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
151 return (tdep->ppc_fp0_regnum >= 0
152 && tdep->ppc_fpscr_regnum >= 0);
156 /* Register set support functions. */
159 ppc_supply_reg (struct regcache *regcache, int regnum,
160 const char *regs, size_t offset)
162 if (regnum != -1 && offset != -1)
163 regcache_raw_supply (regcache, regnum, regs + offset);
167 ppc_collect_reg (const struct regcache *regcache, int regnum,
168 char *regs, size_t offset)
170 if (regnum != -1 && offset != -1)
171 regcache_raw_collect (regcache, regnum, regs + offset);
174 /* Supply register REGNUM in the general-purpose register set REGSET
175 from the buffer specified by GREGS and LEN to register cache
176 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
179 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
180 int regnum, const void *gregs, size_t len)
182 struct gdbarch *gdbarch = get_regcache_arch (regcache);
183 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
184 const struct ppc_reg_offsets *offsets = regset->descr;
188 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
189 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
192 if (regnum == -1 || regnum == i)
193 ppc_supply_reg (regcache, i, gregs, offset);
196 if (regnum == -1 || regnum == PC_REGNUM)
197 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
198 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
199 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
200 gregs, offsets->ps_offset);
201 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
202 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
203 gregs, offsets->cr_offset);
204 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
205 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
206 gregs, offsets->lr_offset);
207 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
208 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
209 gregs, offsets->ctr_offset);
210 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
211 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
212 gregs, offsets->cr_offset);
213 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
214 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
217 /* Supply register REGNUM in the floating-point register set REGSET
218 from the buffer specified by FPREGS and LEN to register cache
219 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
222 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
223 int regnum, const void *fpregs, size_t len)
225 struct gdbarch *gdbarch = get_regcache_arch (regcache);
226 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
227 const struct ppc_reg_offsets *offsets = regset->descr;
231 gdb_assert (ppc_floating_point_unit_p (gdbarch));
233 offset = offsets->f0_offset;
234 for (i = tdep->ppc_fp0_regnum;
235 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
238 if (regnum == -1 || regnum == i)
239 ppc_supply_reg (regcache, i, fpregs, offset);
242 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
243 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
244 fpregs, offsets->fpscr_offset);
247 /* Collect register REGNUM in the general-purpose register set
248 REGSET. from register cache REGCACHE into the buffer specified by
249 GREGS and LEN. If REGNUM is -1, do this for all registers in
253 ppc_collect_gregset (const struct regset *regset,
254 const struct regcache *regcache,
255 int regnum, void *gregs, size_t len)
257 struct gdbarch *gdbarch = get_regcache_arch (regcache);
258 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
259 const struct ppc_reg_offsets *offsets = regset->descr;
263 offset = offsets->r0_offset;
264 for (i = tdep->ppc_gp0_regnum;
265 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
268 if (regnum == -1 || regnum == i)
269 ppc_collect_reg (regcache, i, gregs, offset);
272 if (regnum == -1 || regnum == PC_REGNUM)
273 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
274 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
275 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
276 gregs, offsets->ps_offset);
277 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
278 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
279 gregs, offsets->cr_offset);
280 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
281 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
282 gregs, offsets->lr_offset);
283 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
284 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
285 gregs, offsets->ctr_offset);
286 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
287 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
288 gregs, offsets->xer_offset);
289 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
290 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
291 gregs, offsets->mq_offset);
294 /* Collect register REGNUM in the floating-point register set
295 REGSET. from register cache REGCACHE into the buffer specified by
296 FPREGS and LEN. If REGNUM is -1, do this for all registers in
300 ppc_collect_fpregset (const struct regset *regset,
301 const struct regcache *regcache,
302 int regnum, void *fpregs, size_t len)
304 struct gdbarch *gdbarch = get_regcache_arch (regcache);
305 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
306 const struct ppc_reg_offsets *offsets = regset->descr;
310 gdb_assert (ppc_floating_point_unit_p (gdbarch));
312 offset = offsets->f0_offset;
313 for (i = tdep->ppc_fp0_regnum;
314 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
317 if (regnum == -1 || regnum == i)
318 ppc_collect_reg (regcache, regnum, fpregs, offset);
321 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
322 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
323 fpregs, offsets->fpscr_offset);
327 /* Read a LEN-byte address from debugged memory address MEMADDR. */
330 read_memory_addr (CORE_ADDR memaddr, int len)
332 return read_memory_unsigned_integer (memaddr, len);
336 rs6000_skip_prologue (CORE_ADDR pc)
338 struct rs6000_framedata frame;
339 pc = skip_prologue (pc, 0, &frame);
344 /* Fill in fi->saved_regs */
346 struct frame_extra_info
348 /* Functions calling alloca() change the value of the stack
349 pointer. We need to use initial stack pointer (which is saved in
350 r31 by gcc) in such cases. If a compiler emits traceback table,
351 then we should use the alloca register specified in traceback
353 CORE_ADDR initial_sp; /* initial stack pointer. */
356 /* Get the ith function argument for the current function. */
358 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
362 get_frame_register (frame, 3 + argi, &addr);
366 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
369 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
376 absolute = (int) ((instr >> 1) & 1);
381 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
385 dest = pc + immediate;
389 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
393 dest = pc + immediate;
397 ext_op = (instr >> 1) & 0x3ff;
399 if (ext_op == 16) /* br conditional register */
401 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
403 /* If we are about to return from a signal handler, dest is
404 something like 0x3c90. The current frame is a signal handler
405 caller frame, upon completion of the sigreturn system call
406 execution will return to the saved PC in the frame. */
407 if (dest < TEXT_SEGMENT_BASE)
409 struct frame_info *fi;
411 fi = get_current_frame ();
413 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
414 gdbarch_tdep (current_gdbarch)->wordsize);
418 else if (ext_op == 528) /* br cond to count reg */
420 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
422 /* If we are about to execute a system call, dest is something
423 like 0x22fc or 0x3b00. Upon completion the system call
424 will return to the address in the link register. */
425 if (dest < TEXT_SEGMENT_BASE)
426 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
435 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
439 /* Sequence of bytes for breakpoint instruction. */
441 const static unsigned char *
442 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
444 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
445 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
447 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
448 return big_breakpoint;
450 return little_breakpoint;
454 /* AIX does not support PT_STEP. Simulate it. */
457 rs6000_software_single_step (enum target_signal signal,
458 int insert_breakpoints_p)
462 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
468 if (insert_breakpoints_p)
473 insn = read_memory_integer (loc, 4);
475 breaks[0] = loc + breakp_sz;
477 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
479 /* Don't put two breakpoints on the same address. */
480 if (breaks[1] == breaks[0])
483 stepBreaks[1].address = 0;
485 for (ii = 0; ii < 2; ++ii)
488 /* ignore invalid breakpoint. */
489 if (breaks[ii] == -1)
491 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
492 stepBreaks[ii].address = breaks[ii];
499 /* remove step breakpoints. */
500 for (ii = 0; ii < 2; ++ii)
501 if (stepBreaks[ii].address != 0)
502 target_remove_breakpoint (stepBreaks[ii].address,
503 stepBreaks[ii].data);
505 errno = 0; /* FIXME, don't ignore errors! */
506 /* What errors? {read,write}_memory call error(). */
510 /* return pc value after skipping a function prologue and also return
511 information about a function frame.
513 in struct rs6000_framedata fdata:
514 - frameless is TRUE, if function does not have a frame.
515 - nosavedpc is TRUE, if function does not save %pc value in its frame.
516 - offset is the initial size of this stack frame --- the amount by
517 which we decrement the sp to allocate the frame.
518 - saved_gpr is the number of the first saved gpr.
519 - saved_fpr is the number of the first saved fpr.
520 - saved_vr is the number of the first saved vr.
521 - saved_ev is the number of the first saved ev.
522 - alloca_reg is the number of the register used for alloca() handling.
524 - gpr_offset is the offset of the first saved gpr from the previous frame.
525 - fpr_offset is the offset of the first saved fpr from the previous frame.
526 - vr_offset is the offset of the first saved vr from the previous frame.
527 - ev_offset is the offset of the first saved ev from the previous frame.
528 - lr_offset is the offset of the saved lr
529 - cr_offset is the offset of the saved cr
530 - vrsave_offset is the offset of the saved vrsave register
533 #define SIGNED_SHORT(x) \
534 ((sizeof (short) == 2) \
535 ? ((int)(short)(x)) \
536 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
538 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
540 /* Limit the number of skipped non-prologue instructions, as the examining
541 of the prologue is expensive. */
542 static int max_skip_non_prologue_insns = 10;
544 /* Given PC representing the starting address of a function, and
545 LIM_PC which is the (sloppy) limit to which to scan when looking
546 for a prologue, attempt to further refine this limit by using
547 the line data in the symbol table. If successful, a better guess
548 on where the prologue ends is returned, otherwise the previous
549 value of lim_pc is returned. */
551 /* FIXME: cagney/2004-02-14: This function and logic have largely been
552 superseded by skip_prologue_using_sal. */
555 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
557 struct symtab_and_line prologue_sal;
559 prologue_sal = find_pc_line (pc, 0);
560 if (prologue_sal.line != 0)
563 CORE_ADDR addr = prologue_sal.end;
565 /* Handle the case in which compiler's optimizer/scheduler
566 has moved instructions into the prologue. We scan ahead
567 in the function looking for address ranges whose corresponding
568 line number is less than or equal to the first one that we
569 found for the function. (It can be less than when the
570 scheduler puts a body instruction before the first prologue
572 for (i = 2 * max_skip_non_prologue_insns;
573 i > 0 && (lim_pc == 0 || addr < lim_pc);
576 struct symtab_and_line sal;
578 sal = find_pc_line (addr, 0);
581 if (sal.line <= prologue_sal.line
582 && sal.symtab == prologue_sal.symtab)
589 if (lim_pc == 0 || prologue_sal.end < lim_pc)
590 lim_pc = prologue_sal.end;
595 /* Return nonzero if the given instruction OP can be part of the prologue
596 of a function and saves a parameter on the stack. FRAMEP should be
597 set if one of the previous instructions in the function has set the
601 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
603 /* Move parameters from argument registers to temporary register. */
604 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
606 /* Rx must be scratch register r0. */
607 const int rx_regno = (op >> 16) & 31;
608 /* Ry: Only r3 - r10 are used for parameter passing. */
609 const int ry_regno = GET_SRC_REG (op);
611 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
613 *r0_contains_arg = 1;
620 /* Save a General Purpose Register on stack. */
622 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
623 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
625 /* Rx: Only r3 - r10 are used for parameter passing. */
626 const int rx_regno = GET_SRC_REG (op);
628 return (rx_regno >= 3 && rx_regno <= 10);
631 /* Save a General Purpose Register on stack via the Frame Pointer. */
634 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
635 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
636 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
638 /* Rx: Usually, only r3 - r10 are used for parameter passing.
639 However, the compiler sometimes uses r0 to hold an argument. */
640 const int rx_regno = GET_SRC_REG (op);
642 return ((rx_regno >= 3 && rx_regno <= 10)
643 || (rx_regno == 0 && *r0_contains_arg));
646 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
648 /* Only f2 - f8 are used for parameter passing. */
649 const int src_regno = GET_SRC_REG (op);
651 return (src_regno >= 2 && src_regno <= 8);
654 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
656 /* Only f2 - f8 are used for parameter passing. */
657 const int src_regno = GET_SRC_REG (op);
659 return (src_regno >= 2 && src_regno <= 8);
662 /* Not an insn that saves a parameter on stack. */
667 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
669 CORE_ADDR orig_pc = pc;
670 CORE_ADDR last_prologue_pc = pc;
671 CORE_ADDR li_found_pc = 0;
675 long vr_saved_offset = 0;
684 int minimal_toc_loaded = 0;
685 int prev_insn_was_prologue_insn = 1;
686 int num_skip_non_prologue_insns = 0;
687 int r0_contains_arg = 0;
688 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
689 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
691 /* Attempt to find the end of the prologue when no limit is specified.
692 Note that refine_prologue_limit() has been written so that it may
693 be used to "refine" the limits of non-zero PC values too, but this
694 is only safe if we 1) trust the line information provided by the
695 compiler and 2) iterate enough to actually find the end of the
698 It may become a good idea at some point (for both performance and
699 accuracy) to unconditionally call refine_prologue_limit(). But,
700 until we can make a clear determination that this is beneficial,
701 we'll play it safe and only use it to obtain a limit when none
702 has been specified. */
704 lim_pc = refine_prologue_limit (pc, lim_pc);
706 memset (fdata, 0, sizeof (struct rs6000_framedata));
707 fdata->saved_gpr = -1;
708 fdata->saved_fpr = -1;
709 fdata->saved_vr = -1;
710 fdata->saved_ev = -1;
711 fdata->alloca_reg = -1;
712 fdata->frameless = 1;
713 fdata->nosavedpc = 1;
717 /* Sometimes it isn't clear if an instruction is a prologue
718 instruction or not. When we encounter one of these ambiguous
719 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
720 Otherwise, we'll assume that it really is a prologue instruction. */
721 if (prev_insn_was_prologue_insn)
722 last_prologue_pc = pc;
724 /* Stop scanning if we've hit the limit. */
725 if (lim_pc != 0 && pc >= lim_pc)
728 prev_insn_was_prologue_insn = 1;
730 /* Fetch the instruction and convert it to an integer. */
731 if (target_read_memory (pc, buf, 4))
733 op = extract_signed_integer (buf, 4);
735 if ((op & 0xfc1fffff) == 0x7c0802a6)
737 /* Since shared library / PIC code, which needs to get its
738 address at runtime, can appear to save more than one link
752 remember just the first one, but skip over additional
755 lr_reg = (op & 0x03e00000);
760 else if ((op & 0xfc1fffff) == 0x7c000026)
762 cr_reg = (op & 0x03e00000);
768 else if ((op & 0xfc1f0000) == 0xd8010000)
769 { /* stfd Rx,NUM(r1) */
770 reg = GET_SRC_REG (op);
771 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
773 fdata->saved_fpr = reg;
774 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
779 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
780 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
781 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
782 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
785 reg = GET_SRC_REG (op);
786 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
788 fdata->saved_gpr = reg;
789 if ((op & 0xfc1f0003) == 0xf8010000)
791 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
796 else if ((op & 0xffff0000) == 0x60000000)
799 /* Allow nops in the prologue, but do not consider them to
800 be part of the prologue unless followed by other prologue
802 prev_insn_was_prologue_insn = 0;
806 else if ((op & 0xffff0000) == 0x3c000000)
807 { /* addis 0,0,NUM, used
809 fdata->offset = (op & 0x0000ffff) << 16;
810 fdata->frameless = 0;
815 else if ((op & 0xffff0000) == 0x60000000)
816 { /* ori 0,0,NUM, 2nd ha
817 lf of >= 32k frames */
818 fdata->offset |= (op & 0x0000ffff);
819 fdata->frameless = 0;
824 else if (lr_reg != -1 &&
825 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
826 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
827 /* stw Rx, NUM(r1) */
828 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
829 /* stwu Rx, NUM(r1) */
830 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
831 { /* where Rx == lr */
832 fdata->lr_offset = offset;
833 fdata->nosavedpc = 0;
835 if ((op & 0xfc000003) == 0xf8000000 || /* std */
836 (op & 0xfc000000) == 0x90000000) /* stw */
838 /* Does not update r1, so add displacement to lr_offset. */
839 fdata->lr_offset += SIGNED_SHORT (op);
844 else if (cr_reg != -1 &&
845 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
846 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
847 /* stw Rx, NUM(r1) */
848 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
849 /* stwu Rx, NUM(r1) */
850 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
851 { /* where Rx == cr */
852 fdata->cr_offset = offset;
854 if ((op & 0xfc000003) == 0xf8000000 ||
855 (op & 0xfc000000) == 0x90000000)
857 /* Does not update r1, so add displacement to cr_offset. */
858 fdata->cr_offset += SIGNED_SHORT (op);
863 else if (op == 0x48000005)
869 else if (op == 0x48000004)
874 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
875 in V.4 -mminimal-toc */
876 (op & 0xffff0000) == 0x3bde0000)
877 { /* addi 30,30,foo@l */
881 else if ((op & 0xfc000001) == 0x48000001)
885 fdata->frameless = 0;
886 /* Don't skip over the subroutine call if it is not within
887 the first three instructions of the prologue. */
888 if ((pc - orig_pc) > 8)
891 op = read_memory_integer (pc + 4, 4);
893 /* At this point, make sure this is not a trampoline
894 function (a function that simply calls another functions,
895 and nothing else). If the next is not a nop, this branch
896 was part of the function prologue. */
898 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
899 break; /* don't skip over
904 /* update stack pointer */
905 else if ((op & 0xfc1f0000) == 0x94010000)
906 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
907 fdata->frameless = 0;
908 fdata->offset = SIGNED_SHORT (op);
909 offset = fdata->offset;
912 else if ((op & 0xfc1f016a) == 0x7c01016e)
913 { /* stwux rX,r1,rY */
914 /* no way to figure out what r1 is going to be */
915 fdata->frameless = 0;
916 offset = fdata->offset;
919 else if ((op & 0xfc1f0003) == 0xf8010001)
920 { /* stdu rX,NUM(r1) */
921 fdata->frameless = 0;
922 fdata->offset = SIGNED_SHORT (op & ~3UL);
923 offset = fdata->offset;
926 else if ((op & 0xfc1f016a) == 0x7c01016a)
927 { /* stdux rX,r1,rY */
928 /* no way to figure out what r1 is going to be */
929 fdata->frameless = 0;
930 offset = fdata->offset;
933 /* Load up minimal toc pointer */
934 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
935 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
936 && !minimal_toc_loaded)
938 minimal_toc_loaded = 1;
941 /* move parameters from argument registers to local variable
944 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
945 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
946 (((op >> 21) & 31) <= 10) &&
947 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
951 /* store parameters in stack */
953 /* Move parameters from argument registers to temporary register. */
954 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
958 /* Set up frame pointer */
960 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
963 fdata->frameless = 0;
965 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
968 /* Another way to set up the frame pointer. */
970 else if ((op & 0xfc1fffff) == 0x38010000)
971 { /* addi rX, r1, 0x0 */
972 fdata->frameless = 0;
974 fdata->alloca_reg = (tdep->ppc_gp0_regnum
975 + ((op & ~0x38010000) >> 21));
978 /* AltiVec related instructions. */
979 /* Store the vrsave register (spr 256) in another register for
980 later manipulation, or load a register into the vrsave
981 register. 2 instructions are used: mfvrsave and
982 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
983 and mtspr SPR256, Rn. */
984 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
985 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
986 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
988 vrsave_reg = GET_SRC_REG (op);
991 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
995 /* Store the register where vrsave was saved to onto the stack:
996 rS is the register where vrsave was stored in a previous
998 /* 100100 sssss 00001 dddddddd dddddddd */
999 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1001 if (vrsave_reg == GET_SRC_REG (op))
1003 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1008 /* Compute the new value of vrsave, by modifying the register
1009 where vrsave was saved to. */
1010 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1011 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1015 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1016 in a pair of insns to save the vector registers on the
1018 /* 001110 00000 00000 iiii iiii iiii iiii */
1019 /* 001110 01110 00000 iiii iiii iiii iiii */
1020 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1021 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1023 if ((op & 0xffff0000) == 0x38000000)
1024 r0_contains_arg = 0;
1026 vr_saved_offset = SIGNED_SHORT (op);
1028 /* This insn by itself is not part of the prologue, unless
1029 if part of the pair of insns mentioned above. So do not
1030 record this insn as part of the prologue yet. */
1031 prev_insn_was_prologue_insn = 0;
1033 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1034 /* 011111 sssss 11111 00000 00111001110 */
1035 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1037 if (pc == (li_found_pc + 4))
1039 vr_reg = GET_SRC_REG (op);
1040 /* If this is the first vector reg to be saved, or if
1041 it has a lower number than others previously seen,
1042 reupdate the frame info. */
1043 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1045 fdata->saved_vr = vr_reg;
1046 fdata->vr_offset = vr_saved_offset + offset;
1048 vr_saved_offset = -1;
1053 /* End AltiVec related instructions. */
1055 /* Start BookE related instructions. */
1056 /* Store gen register S at (r31+uimm).
1057 Any register less than r13 is volatile, so we don't care. */
1058 /* 000100 sssss 11111 iiiii 01100100001 */
1059 else if (arch_info->mach == bfd_mach_ppc_e500
1060 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1062 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1065 ev_reg = GET_SRC_REG (op);
1066 imm = (op >> 11) & 0x1f;
1067 ev_offset = imm * 8;
1068 /* If this is the first vector reg to be saved, or if
1069 it has a lower number than others previously seen,
1070 reupdate the frame info. */
1071 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1073 fdata->saved_ev = ev_reg;
1074 fdata->ev_offset = ev_offset + offset;
1079 /* Store gen register rS at (r1+rB). */
1080 /* 000100 sssss 00001 bbbbb 01100100000 */
1081 else if (arch_info->mach == bfd_mach_ppc_e500
1082 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1084 if (pc == (li_found_pc + 4))
1086 ev_reg = GET_SRC_REG (op);
1087 /* If this is the first vector reg to be saved, or if
1088 it has a lower number than others previously seen,
1089 reupdate the frame info. */
1090 /* We know the contents of rB from the previous instruction. */
1091 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1093 fdata->saved_ev = ev_reg;
1094 fdata->ev_offset = vr_saved_offset + offset;
1096 vr_saved_offset = -1;
1102 /* Store gen register r31 at (rA+uimm). */
1103 /* 000100 11111 aaaaa iiiii 01100100001 */
1104 else if (arch_info->mach == bfd_mach_ppc_e500
1105 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1107 /* Wwe know that the source register is 31 already, but
1108 it can't hurt to compute it. */
1109 ev_reg = GET_SRC_REG (op);
1110 ev_offset = ((op >> 11) & 0x1f) * 8;
1111 /* If this is the first vector reg to be saved, or if
1112 it has a lower number than others previously seen,
1113 reupdate the frame info. */
1114 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1116 fdata->saved_ev = ev_reg;
1117 fdata->ev_offset = ev_offset + offset;
1122 /* Store gen register S at (r31+r0).
1123 Store param on stack when offset from SP bigger than 4 bytes. */
1124 /* 000100 sssss 11111 00000 01100100000 */
1125 else if (arch_info->mach == bfd_mach_ppc_e500
1126 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1128 if (pc == (li_found_pc + 4))
1130 if ((op & 0x03e00000) >= 0x01a00000)
1132 ev_reg = GET_SRC_REG (op);
1133 /* If this is the first vector reg to be saved, or if
1134 it has a lower number than others previously seen,
1135 reupdate the frame info. */
1136 /* We know the contents of r0 from the previous
1138 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1140 fdata->saved_ev = ev_reg;
1141 fdata->ev_offset = vr_saved_offset + offset;
1145 vr_saved_offset = -1;
1150 /* End BookE related instructions. */
1154 /* Not a recognized prologue instruction.
1155 Handle optimizer code motions into the prologue by continuing
1156 the search if we have no valid frame yet or if the return
1157 address is not yet saved in the frame. */
1158 if (fdata->frameless == 0
1159 && (lr_reg == -1 || fdata->nosavedpc == 0))
1162 if (op == 0x4e800020 /* blr */
1163 || op == 0x4e800420) /* bctr */
1164 /* Do not scan past epilogue in frameless functions or
1167 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1168 /* Never skip branches. */
1171 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1172 /* Do not scan too many insns, scanning insns is expensive with
1176 /* Continue scanning. */
1177 prev_insn_was_prologue_insn = 0;
1183 /* I have problems with skipping over __main() that I need to address
1184 * sometime. Previously, I used to use misc_function_vector which
1185 * didn't work as well as I wanted to be. -MGO */
1187 /* If the first thing after skipping a prolog is a branch to a function,
1188 this might be a call to an initializer in main(), introduced by gcc2.
1189 We'd like to skip over it as well. Fortunately, xlc does some extra
1190 work before calling a function right after a prologue, thus we can
1191 single out such gcc2 behaviour. */
1194 if ((op & 0xfc000001) == 0x48000001)
1195 { /* bl foo, an initializer function? */
1196 op = read_memory_integer (pc + 4, 4);
1198 if (op == 0x4def7b82)
1199 { /* cror 0xf, 0xf, 0xf (nop) */
1201 /* Check and see if we are in main. If so, skip over this
1202 initializer function as well. */
1204 tmp = find_pc_misc_function (pc);
1206 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1212 fdata->offset = -fdata->offset;
1213 return last_prologue_pc;
1217 /*************************************************************************
1218 Support for creating pushing a dummy frame into the stack, and popping
1220 *************************************************************************/
1223 /* All the ABI's require 16 byte alignment. */
1225 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1227 return (addr & -16);
1230 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1231 the first eight words of the argument list (that might be less than
1232 eight parameters if some parameters occupy more than one word) are
1233 passed in r3..r10 registers. float and double parameters are
1234 passed in fpr's, in addition to that. Rest of the parameters if any
1235 are passed in user stack. There might be cases in which half of the
1236 parameter is copied into registers, the other half is pushed into
1239 Stack must be aligned on 64-bit boundaries when synthesizing
1242 If the function is returning a structure, then the return address is passed
1243 in r3, then the first 7 words of the parameters can be passed in registers,
1244 starting from r4. */
1247 rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1248 struct regcache *regcache, CORE_ADDR bp_addr,
1249 int nargs, struct value **args, CORE_ADDR sp,
1250 int struct_return, CORE_ADDR struct_addr)
1252 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1255 int argno; /* current argument number */
1256 int argbytes; /* current argument byte */
1257 char tmp_buffer[50];
1258 int f_argno = 0; /* current floating point argno */
1259 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1261 struct value *arg = 0;
1266 /* The calling convention this function implements assumes the
1267 processor has floating-point registers. We shouldn't be using it
1268 on PPC variants that lack them. */
1269 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1271 /* The first eight words of ther arguments are passed in registers.
1272 Copy them appropriately. */
1275 /* If the function is returning a `struct', then the first word
1276 (which will be passed in r3) is used for struct return address.
1277 In that case we should advance one word and start from r4
1278 register to copy parameters. */
1281 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1287 effectively indirect call... gcc does...
1289 return_val example( float, int);
1292 float in fp0, int in r3
1293 offset of stack on overflow 8/16
1294 for varargs, must go by type.
1296 float in r3&r4, int in r5
1297 offset of stack on overflow different
1299 return in r3 or f0. If no float, must study how gcc emulates floats;
1300 pay attention to arg promotion.
1301 User may have to cast\args to handle promotion correctly
1302 since gdb won't know if prototype supplied or not.
1305 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1307 int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3);
1310 type = check_typedef (VALUE_TYPE (arg));
1311 len = TYPE_LENGTH (type);
1313 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1316 /* Floating point arguments are passed in fpr's, as well as gpr's.
1317 There are 13 fpr's reserved for passing parameters. At this point
1318 there is no way we would run out of them. */
1321 printf_unfiltered ("Fatal Error: a floating point parameter "
1322 "#%d with a size > 8 is found!\n", argno);
1324 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE
1325 (tdep->ppc_fp0_regnum + 1 + f_argno)],
1326 VALUE_CONTENTS (arg),
1334 /* Argument takes more than one register. */
1335 while (argbytes < len)
1337 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0,
1339 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)],
1340 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1341 (len - argbytes) > reg_size
1342 ? reg_size : len - argbytes);
1343 ++ii, argbytes += reg_size;
1346 goto ran_out_of_registers_for_arguments;
1353 /* Argument can fit in one register. No problem. */
1354 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1355 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size);
1356 memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj,
1357 VALUE_CONTENTS (arg), len);
1362 ran_out_of_registers_for_arguments:
1364 saved_sp = read_sp ();
1366 /* Location for 8 parameters are always reserved. */
1369 /* Another six words for back chain, TOC register, link register, etc. */
1372 /* Stack pointer must be quadword aligned. */
1375 /* If there are more arguments, allocate space for them in
1376 the stack, then push them starting from the ninth one. */
1378 if ((argno < nargs) || argbytes)
1384 space += ((len - argbytes + 3) & -4);
1390 for (; jj < nargs; ++jj)
1392 struct value *val = args[jj];
1393 space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
1396 /* Add location required for the rest of the parameters. */
1397 space = (space + 15) & -16;
1400 /* This is another instance we need to be concerned about
1401 securing our stack space. If we write anything underneath %sp
1402 (r1), we might conflict with the kernel who thinks he is free
1403 to use this area. So, update %sp first before doing anything
1406 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1408 /* If the last argument copied into the registers didn't fit there
1409 completely, push the rest of it into stack. */
1413 write_memory (sp + 24 + (ii * 4),
1414 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1417 ii += ((len - argbytes + 3) & -4) / 4;
1420 /* Push the rest of the arguments into stack. */
1421 for (; argno < nargs; ++argno)
1425 type = check_typedef (VALUE_TYPE (arg));
1426 len = TYPE_LENGTH (type);
1429 /* Float types should be passed in fpr's, as well as in the
1431 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1435 printf_unfiltered ("Fatal Error: a floating point parameter"
1436 " #%d with a size > 8 is found!\n", argno);
1438 memcpy (&(deprecated_registers
1439 [DEPRECATED_REGISTER_BYTE
1440 (tdep->ppc_fp0_regnum + 1 + f_argno)]),
1441 VALUE_CONTENTS (arg),
1446 write_memory (sp + 24 + (ii * 4),
1447 (char *) VALUE_CONTENTS (arg),
1449 ii += ((len + 3) & -4) / 4;
1453 /* Set the stack pointer. According to the ABI, the SP is meant to
1454 be set _before_ the corresponding stack space is used. On AIX,
1455 this even applies when the target has been completely stopped!
1456 Not doing this can lead to conflicts with the kernel which thinks
1457 that it still has control over this not-yet-allocated stack
1459 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1461 /* Set back chain properly. */
1462 store_unsigned_integer (tmp_buffer, 4, saved_sp);
1463 write_memory (sp, tmp_buffer, 4);
1465 /* Point the inferior function call's return address at the dummy's
1467 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1469 /* Set the TOC register, get the value from the objfile reader
1470 which, in turn, gets it from the VMAP table. */
1471 if (rs6000_find_toc_address_hook != NULL)
1473 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1474 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1477 target_store_registers (-1);
1481 /* PowerOpen always puts structures in memory. Vectors, which were
1482 added later, do get returned in a register though. */
1485 rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1487 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1488 && TYPE_VECTOR (value_type))
1494 rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
1497 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1499 /* The calling convention this function implements assumes the
1500 processor has floating-point registers. We shouldn't be using it
1501 on PPC variants that lack them. */
1502 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1504 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1507 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1508 We need to truncate the return value into float size (4 byte) if
1511 convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
1512 (tdep->ppc_fp0_regnum + 1)],
1513 builtin_type_double,
1517 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1518 && TYPE_LENGTH (valtype) == 16
1519 && TYPE_VECTOR (valtype))
1521 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1522 TYPE_LENGTH (valtype));
1526 /* return value is copied starting from r3. */
1527 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1528 && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3))
1529 offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype);
1532 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
1533 TYPE_LENGTH (valtype));
1537 /* Return whether handle_inferior_event() should proceed through code
1538 starting at PC in function NAME when stepping.
1540 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1541 handle memory references that are too distant to fit in instructions
1542 generated by the compiler. For example, if 'foo' in the following
1547 is greater than 32767, the linker might replace the lwz with a branch to
1548 somewhere in @FIX1 that does the load in 2 instructions and then branches
1549 back to where execution should continue.
1551 GDB should silently step over @FIX code, just like AIX dbx does.
1552 Unfortunately, the linker uses the "b" instruction for the branches,
1553 meaning that the link register doesn't get set. Therefore, GDB's usual
1554 step_over_function() mechanism won't work.
1556 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1557 in handle_inferior_event() to skip past @FIX code. */
1560 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1562 return name && !strncmp (name, "@FIX", 4);
1565 /* Skip code that the user doesn't want to see when stepping:
1567 1. Indirect function calls use a piece of trampoline code to do context
1568 switching, i.e. to set the new TOC table. Skip such code if we are on
1569 its first instruction (as when we have single-stepped to here).
1571 2. Skip shared library trampoline code (which is different from
1572 indirect function call trampolines).
1574 3. Skip bigtoc fixup code.
1576 Result is desired PC to step until, or NULL if we are not in
1577 code that should be skipped. */
1580 rs6000_skip_trampoline_code (CORE_ADDR pc)
1582 unsigned int ii, op;
1584 CORE_ADDR solib_target_pc;
1585 struct minimal_symbol *msymbol;
1587 static unsigned trampoline_code[] =
1589 0x800b0000, /* l r0,0x0(r11) */
1590 0x90410014, /* st r2,0x14(r1) */
1591 0x7c0903a6, /* mtctr r0 */
1592 0x804b0004, /* l r2,0x4(r11) */
1593 0x816b0008, /* l r11,0x8(r11) */
1594 0x4e800420, /* bctr */
1595 0x4e800020, /* br */
1599 /* Check for bigtoc fixup code. */
1600 msymbol = lookup_minimal_symbol_by_pc (pc);
1601 if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol)))
1603 /* Double-check that the third instruction from PC is relative "b". */
1604 op = read_memory_integer (pc + 8, 4);
1605 if ((op & 0xfc000003) == 0x48000000)
1607 /* Extract bits 6-29 as a signed 24-bit relative word address and
1608 add it to the containing PC. */
1609 rel = ((int)(op << 6) >> 6);
1610 return pc + 8 + rel;
1614 /* If pc is in a shared library trampoline, return its target. */
1615 solib_target_pc = find_solib_trampoline_target (pc);
1616 if (solib_target_pc)
1617 return solib_target_pc;
1619 for (ii = 0; trampoline_code[ii]; ++ii)
1621 op = read_memory_integer (pc + (ii * 4), 4);
1622 if (op != trampoline_code[ii])
1625 ii = read_register (11); /* r11 holds destination addr */
1626 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1630 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1631 isn't available with that word size, return 0. */
1634 regsize (const struct reg *reg, int wordsize)
1636 return wordsize == 8 ? reg->sz64 : reg->sz32;
1639 /* Return the name of register number N, or null if no such register exists
1640 in the current architecture. */
1643 rs6000_register_name (int n)
1645 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1646 const struct reg *reg = tdep->regs + n;
1648 if (!regsize (reg, tdep->wordsize))
1653 /* Index within `registers' of the first byte of the space for
1657 rs6000_register_byte (int n)
1659 return gdbarch_tdep (current_gdbarch)->regoff[n];
1662 /* Return the number of bytes of storage in the actual machine representation
1663 for register N if that register is available, else return 0. */
1666 rs6000_register_raw_size (int n)
1668 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1669 const struct reg *reg = tdep->regs + n;
1670 return regsize (reg, tdep->wordsize);
1673 /* Return the GDB type object for the "standard" data type
1674 of data in register N. */
1676 static struct type *
1677 rs6000_register_virtual_type (int n)
1679 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1680 const struct reg *reg = tdep->regs + n;
1683 return builtin_type_double;
1686 int size = regsize (reg, tdep->wordsize);
1690 return builtin_type_int0;
1692 return builtin_type_uint32;
1694 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1695 return builtin_type_vec64;
1697 return builtin_type_uint64;
1700 return builtin_type_vec128;
1703 internal_error (__FILE__, __LINE__, "Register %d size %d unknown",
1709 /* Return whether register N requires conversion when moving from raw format
1712 The register format for RS/6000 floating point registers is always
1713 double, we need a conversion if the memory format is float. */
1716 rs6000_register_convertible (int n)
1718 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n;
1722 /* Convert data from raw format for register N in buffer FROM
1723 to virtual format with type TYPE in buffer TO. */
1726 rs6000_register_convert_to_virtual (int n, struct type *type,
1727 char *from, char *to)
1729 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n))
1731 double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n));
1732 deprecated_store_floating (to, TYPE_LENGTH (type), val);
1735 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n));
1738 /* Convert data from virtual format with type TYPE in buffer FROM
1739 to raw format for register N in buffer TO. */
1742 rs6000_register_convert_to_raw (struct type *type, int n,
1743 const char *from, char *to)
1745 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n))
1747 double val = deprecated_extract_floating (from, TYPE_LENGTH (type));
1748 deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val);
1751 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n));
1755 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1756 int reg_nr, void *buffer)
1760 char temp_buffer[MAX_REGISTER_SIZE];
1761 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1763 if (reg_nr >= tdep->ppc_gp0_regnum
1764 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
1766 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1768 /* Build the value in the provided buffer. */
1769 /* Read the raw register of which this one is the lower portion. */
1770 regcache_raw_read (regcache, base_regnum, temp_buffer);
1771 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1773 memcpy ((char *) buffer, temp_buffer + offset, 4);
1778 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1779 int reg_nr, const void *buffer)
1783 char temp_buffer[MAX_REGISTER_SIZE];
1784 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1786 if (reg_nr >= tdep->ppc_gp0_regnum
1787 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
1789 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1790 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1791 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1794 /* Let's read the value of the base register into a temporary
1795 buffer, so that overwriting the last four bytes with the new
1796 value of the pseudo will leave the upper 4 bytes unchanged. */
1797 regcache_raw_read (regcache, base_regnum, temp_buffer);
1799 /* Write as an 8 byte quantity. */
1800 memcpy (temp_buffer + offset, (char *) buffer, 4);
1801 regcache_raw_write (regcache, base_regnum, temp_buffer);
1805 /* Convert a dbx stab or Dwarf 2 register number (from `r'
1806 declaration) to a gdb REGNUM. */
1808 rs6000_dwarf2_stab_reg_to_regnum (int num)
1810 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1812 if (0 <= num && num <= 31)
1813 return tdep->ppc_gp0_regnum + num;
1814 else if (32 <= num && num <= 63)
1815 /* FIXME: jimb/2004-05-05: What should we do when the debug info
1816 specifies registers the architecture doesn't have? Our
1817 callers don't check the value we return. */
1818 return tdep->ppc_fp0_regnum + (num - 32);
1819 else if (1200 <= num && num < 1200 + 32)
1820 return tdep->ppc_ev0_regnum + (num - 1200);
1825 return tdep->ppc_mq_regnum;
1827 return tdep->ppc_lr_regnum;
1829 return tdep->ppc_ctr_regnum;
1831 return tdep->ppc_xer_regnum;
1833 return tdep->ppc_vrsave_regnum;
1838 /* FIXME: jimb/2004-03-28: Doesn't something need to be done here
1839 for the Altivec registers, too?
1841 Looking at GCC, the headers in config/rs6000 never define a
1842 DBX_REGISTER_NUMBER macro, so the debug info uses the same
1843 numbers GCC does internally. Then, looking at the REGISTER_NAMES
1844 macro defined in config/rs6000/rs6000.h, it seems that GCC gives
1845 v0 -- v31 the numbers 77 -- 108. But we number them 119 -- 150.
1847 I don't have a way to test this ready to hand, but I noticed it
1848 and thought I should include a note. */
1852 rs6000_store_return_value (struct type *type, char *valbuf)
1854 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1856 /* The calling convention this function implements assumes the
1857 processor has floating-point registers. We shouldn't be using it
1858 on PPC variants that lack them. */
1859 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1861 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1863 /* Floating point values are returned starting from FPR1 and up.
1864 Say a double_double_double type could be returned in
1865 FPR1/FPR2/FPR3 triple. */
1867 deprecated_write_register_bytes
1868 (DEPRECATED_REGISTER_BYTE (tdep->ppc_fp0_regnum + 1),
1870 TYPE_LENGTH (type));
1871 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1873 if (TYPE_LENGTH (type) == 16
1874 && TYPE_VECTOR (type))
1875 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1876 valbuf, TYPE_LENGTH (type));
1879 /* Everything else is returned in GPR3 and up. */
1880 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3),
1881 valbuf, TYPE_LENGTH (type));
1884 /* Extract from an array REGBUF containing the (raw) register state
1885 the address in which a function should return its structure value,
1886 as a CORE_ADDR (or an expression that can be used as one). */
1889 rs6000_extract_struct_value_address (struct regcache *regcache)
1891 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
1892 function call GDB knows the address of the struct return value
1893 and hence, should not need to call this function. Unfortunately,
1894 the current call_function_by_hand() code only saves the most
1895 recent struct address leading to occasional calls. The code
1896 should instead maintain a stack of such addresses (in the dummy
1898 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
1899 really got no idea where the return value is being stored. While
1900 r3, on function entry, contained the address it will have since
1901 been reused (scratch) and hence wouldn't be valid */
1905 /* Hook called when a new child process is started. */
1908 rs6000_create_inferior (int pid)
1910 if (rs6000_set_host_arch_hook)
1911 rs6000_set_host_arch_hook (pid);
1914 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
1916 Usually a function pointer's representation is simply the address
1917 of the function. On the RS/6000 however, a function pointer is
1918 represented by a pointer to a TOC entry. This TOC entry contains
1919 three words, the first word is the address of the function, the
1920 second word is the TOC pointer (r2), and the third word is the
1921 static chain value. Throughout GDB it is currently assumed that a
1922 function pointer contains the address of the function, which is not
1923 easy to fix. In addition, the conversion of a function address to
1924 a function pointer would require allocation of a TOC entry in the
1925 inferior's memory space, with all its drawbacks. To be able to
1926 call C++ virtual methods in the inferior (which are called via
1927 function pointers), find_function_addr uses this function to get the
1928 function address from a function pointer. */
1930 /* Return real function address if ADDR (a function pointer) is in the data
1931 space and is therefore a special function pointer. */
1934 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
1936 struct target_ops *targ)
1938 struct obj_section *s;
1940 s = find_pc_section (addr);
1941 if (s && s->the_bfd_section->flags & SEC_CODE)
1944 /* ADDR is in the data space, so it's a special function pointer. */
1945 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
1949 /* Handling the various POWER/PowerPC variants. */
1952 /* The arrays here called registers_MUMBLE hold information about available
1955 For each family of PPC variants, I've tried to isolate out the
1956 common registers and put them up front, so that as long as you get
1957 the general family right, GDB will correctly identify the registers
1958 common to that family. The common register sets are:
1960 For the 60x family: hid0 hid1 iabr dabr pir
1962 For the 505 and 860 family: eie eid nri
1964 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
1965 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
1968 Most of these register groups aren't anything formal. I arrived at
1969 them by looking at the registers that occurred in more than one
1972 Note: kevinb/2002-04-30: Support for the fpscr register was added
1973 during April, 2002. Slot 70 is being used for PowerPC and slot 71
1974 for Power. For PowerPC, slot 70 was unused and was already in the
1975 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
1976 slot 70 was being used for "mq", so the next available slot (71)
1977 was chosen. It would have been nice to be able to make the
1978 register numbers the same across processor cores, but this wasn't
1979 possible without either 1) renumbering some registers for some
1980 processors or 2) assigning fpscr to a really high slot that's
1981 larger than any current register number. Doing (1) is bad because
1982 existing stubs would break. Doing (2) is undesirable because it
1983 would introduce a really large gap between fpscr and the rest of
1984 the registers for most processors. */
1986 /* Convenience macros for populating register arrays. */
1988 /* Within another macro, convert S to a string. */
1992 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
1993 and 64 bits on 64-bit systems. */
1994 #define R(name) { STR(name), 4, 8, 0, 0 }
1996 /* Return a struct reg defining register NAME that's 32 bits on all
1998 #define R4(name) { STR(name), 4, 4, 0, 0 }
2000 /* Return a struct reg defining register NAME that's 64 bits on all
2002 #define R8(name) { STR(name), 8, 8, 0, 0 }
2004 /* Return a struct reg defining register NAME that's 128 bits on all
2006 #define R16(name) { STR(name), 16, 16, 0, 0 }
2008 /* Return a struct reg defining floating-point register NAME. */
2009 #define F(name) { STR(name), 8, 8, 1, 0 }
2011 /* Return a struct reg defining a pseudo register NAME. */
2012 #define P(name) { STR(name), 4, 8, 0, 1}
2014 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2015 systems and that doesn't exist on 64-bit systems. */
2016 #define R32(name) { STR(name), 4, 0, 0, 0 }
2018 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2019 systems and that doesn't exist on 32-bit systems. */
2020 #define R64(name) { STR(name), 0, 8, 0, 0 }
2022 /* Return a struct reg placeholder for a register that doesn't exist. */
2023 #define R0 { 0, 0, 0, 0, 0 }
2025 /* UISA registers common across all architectures, including POWER. */
2027 #define COMMON_UISA_REGS \
2028 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2029 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2030 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2031 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2032 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2033 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2034 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2035 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2036 /* 64 */ R(pc), R(ps)
2038 #define COMMON_UISA_NOFP_REGS \
2039 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2040 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2041 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2042 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2043 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2044 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2045 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2046 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
2047 /* 64 */ R(pc), R(ps)
2049 /* UISA-level SPRs for PowerPC. */
2050 #define PPC_UISA_SPRS \
2051 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
2053 /* UISA-level SPRs for PowerPC without floating point support. */
2054 #define PPC_UISA_NOFP_SPRS \
2055 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
2057 /* Segment registers, for PowerPC. */
2058 #define PPC_SEGMENT_REGS \
2059 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2060 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2061 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2062 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2064 /* OEA SPRs for PowerPC. */
2065 #define PPC_OEA_SPRS \
2067 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
2068 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
2069 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
2070 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
2071 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
2072 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
2073 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
2074 /* 116 */ R4(dec), R(dabr), R4(ear)
2076 /* AltiVec registers. */
2077 #define PPC_ALTIVEC_REGS \
2078 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2079 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2080 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2081 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2082 /*151*/R4(vscr), R4(vrsave)
2084 /* Vectors of hi-lo general purpose registers. */
2085 #define PPC_EV_REGS \
2086 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
2087 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
2088 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
2089 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
2091 /* Lower half of the EV registers. */
2092 #define PPC_GPRS_PSEUDO_REGS \
2093 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
2094 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
2095 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
2096 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31)
2098 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2099 user-level SPR's. */
2100 static const struct reg registers_power[] =
2103 /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
2107 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2108 view of the PowerPC. */
2109 static const struct reg registers_powerpc[] =
2116 /* PowerPC UISA - a PPC processor as viewed by user-level
2117 code, but without floating point registers. */
2118 static const struct reg registers_powerpc_nofp[] =
2120 COMMON_UISA_NOFP_REGS,
2124 /* IBM PowerPC 403. */
2125 static const struct reg registers_403[] =
2131 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2132 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2133 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2134 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2135 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2136 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2)
2139 /* IBM PowerPC 403GC. */
2140 static const struct reg registers_403GC[] =
2146 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2147 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2148 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2149 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2150 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2151 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2),
2152 /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr),
2153 /* 147 */ R(tbhu), R(tblu)
2156 /* Motorola PowerPC 505. */
2157 static const struct reg registers_505[] =
2163 /* 119 */ R(eie), R(eid), R(nri)
2166 /* Motorola PowerPC 860 or 850. */
2167 static const struct reg registers_860[] =
2173 /* 119 */ R(eie), R(eid), R(nri), R(cmpa),
2174 /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr),
2175 /* 127 */ R(der), R(counta), R(countb), R(cmpe),
2176 /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1),
2177 /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst),
2178 /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr),
2179 /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr),
2180 /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc),
2181 /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap),
2182 /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn),
2183 /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1),
2184 /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1)
2187 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2188 for reading and writing RTCU and RTCL. However, how one reads and writes a
2189 register is the stub's problem. */
2190 static const struct reg registers_601[] =
2196 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2197 /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl)
2200 /* Motorola PowerPC 602. */
2201 static const struct reg registers_602[] =
2207 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2208 /* 123 */ R0, R(tcr), R(ibr), R(esassr),
2209 /* 127 */ R(sebr), R(ser), R(sp), R(lt)
2212 /* Motorola/IBM PowerPC 603 or 603e. */
2213 static const struct reg registers_603[] =
2219 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2220 /* 123 */ R0, R(dmiss), R(dcmp), R(hash1),
2221 /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa)
2224 /* Motorola PowerPC 604 or 604e. */
2225 static const struct reg registers_604[] =
2231 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2232 /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2),
2233 /* 127 */ R(sia), R(sda)
2236 /* Motorola/IBM PowerPC 750 or 740. */
2237 static const struct reg registers_750[] =
2243 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2244 /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2),
2245 /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4),
2246 /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia),
2247 /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr),
2248 /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3)
2252 /* Motorola PowerPC 7400. */
2253 static const struct reg registers_7400[] =
2255 /* gpr0-gpr31, fpr0-fpr31 */
2257 /* cr, lr, ctr, xer, fpscr */
2262 /* vr0-vr31, vrsave, vscr */
2264 /* FIXME? Add more registers? */
2267 /* Motorola e500. */
2268 static const struct reg registers_e500[] =
2271 /* cr, lr, ctr, xer, "" */
2275 R8(acc), R(spefscr),
2276 /* NOTE: Add new registers here the end of the raw register
2277 list and just before the first pseudo register. */
2279 PPC_GPRS_PSEUDO_REGS
2282 /* Information about a particular processor variant. */
2286 /* Name of this variant. */
2289 /* English description of the variant. */
2292 /* bfd_arch_info.arch corresponding to variant. */
2293 enum bfd_architecture arch;
2295 /* bfd_arch_info.mach corresponding to variant. */
2298 /* Number of real registers. */
2301 /* Number of pseudo registers. */
2304 /* Number of total registers (the sum of nregs and npregs). */
2307 /* Table of register names; registers[R] is the name of the register
2309 const struct reg *regs;
2312 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2315 num_registers (const struct reg *reg_list, int num_tot_regs)
2320 for (i = 0; i < num_tot_regs; i++)
2321 if (!reg_list[i].pseudo)
2328 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2333 for (i = 0; i < num_tot_regs; i++)
2334 if (reg_list[i].pseudo)
2340 /* Information in this table comes from the following web sites:
2341 IBM: http://www.chips.ibm.com:80/products/embedded/
2342 Motorola: http://www.mot.com/SPS/PowerPC/
2344 I'm sure I've got some of the variant descriptions not quite right.
2345 Please report any inaccuracies you find to GDB's maintainer.
2347 If you add entries to this table, please be sure to allow the new
2348 value as an argument to the --with-cpu flag, in configure.in. */
2350 static struct variant variants[] =
2353 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2354 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2356 {"power", "POWER user-level", bfd_arch_rs6000,
2357 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2359 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2360 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2362 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2363 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2365 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2366 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2368 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2369 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2371 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2372 604, -1, -1, tot_num_registers (registers_604),
2374 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2375 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2377 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2378 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2380 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2381 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2383 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2384 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2386 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2387 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2389 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2390 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2394 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2395 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2397 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2398 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2400 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2401 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2403 {"a35", "PowerPC A35", bfd_arch_powerpc,
2404 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2406 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2407 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2409 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2410 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2413 /* FIXME: I haven't checked the register sets of the following. */
2414 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2415 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2417 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2418 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2420 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2421 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2424 {0, 0, 0, 0, 0, 0, 0, 0}
2427 /* Initialize the number of registers and pseudo registers in each variant. */
2430 init_variants (void)
2434 for (v = variants; v->name; v++)
2437 v->nregs = num_registers (v->regs, v->num_tot_regs);
2438 if (v->npregs == -1)
2439 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2443 /* Return the variant corresponding to architecture ARCH and machine number
2444 MACH. If no such variant exists, return null. */
2446 static const struct variant *
2447 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2449 const struct variant *v;
2451 for (v = variants; v->name; v++)
2452 if (arch == v->arch && mach == v->mach)
2459 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2461 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2462 return print_insn_big_powerpc (memaddr, info);
2464 return print_insn_little_powerpc (memaddr, info);
2468 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2470 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2473 static struct frame_id
2474 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2476 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2478 frame_pc_unwind (next_frame));
2481 struct rs6000_frame_cache
2484 CORE_ADDR initial_sp;
2485 struct trad_frame_saved_reg *saved_regs;
2488 static struct rs6000_frame_cache *
2489 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2491 struct rs6000_frame_cache *cache;
2492 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2493 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2494 struct rs6000_framedata fdata;
2495 int wordsize = tdep->wordsize;
2497 if ((*this_cache) != NULL)
2498 return (*this_cache);
2499 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2500 (*this_cache) = cache;
2501 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2503 skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame),
2506 /* If there were any saved registers, figure out parent's stack
2508 /* The following is true only if the frame doesn't have a call to
2511 if (fdata.saved_fpr == 0
2512 && fdata.saved_gpr == 0
2513 && fdata.saved_vr == 0
2514 && fdata.saved_ev == 0
2515 && fdata.lr_offset == 0
2516 && fdata.cr_offset == 0
2517 && fdata.vr_offset == 0
2518 && fdata.ev_offset == 0)
2519 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2522 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2523 address of the current frame. Things might be easier if the
2524 ->frame pointed to the outer-most address of the frame. In
2525 the mean time, the address of the prev frame is used as the
2526 base address of this frame. */
2527 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2528 if (!fdata.frameless)
2529 /* Frameless really means stackless. */
2530 cache->base = read_memory_addr (cache->base, wordsize);
2532 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
2534 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2535 All fpr's from saved_fpr to fp31 are saved. */
2537 if (fdata.saved_fpr >= 0)
2540 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
2542 /* If skip_prologue says floating-point registers were saved,
2543 but the current architecture has no floating-point registers,
2544 then that's strange. But we have no indices to even record
2545 the addresses under, so we just ignore it. */
2546 if (ppc_floating_point_unit_p (gdbarch))
2547 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
2549 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2554 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2555 All gpr's from saved_gpr to gpr31 are saved. */
2557 if (fdata.saved_gpr >= 0)
2560 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
2561 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
2563 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2564 gpr_addr += wordsize;
2568 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2569 All vr's from saved_vr to vr31 are saved. */
2570 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2572 if (fdata.saved_vr >= 0)
2575 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2576 for (i = fdata.saved_vr; i < 32; i++)
2578 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2579 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2584 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2585 All vr's from saved_ev to ev31 are saved. ????? */
2586 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
2588 if (fdata.saved_ev >= 0)
2591 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
2592 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
2594 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2595 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2596 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2601 /* If != 0, fdata.cr_offset is the offset from the frame that
2603 if (fdata.cr_offset != 0)
2604 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2606 /* If != 0, fdata.lr_offset is the offset from the frame that
2608 if (fdata.lr_offset != 0)
2609 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2610 /* The PC is found in the link register. */
2611 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
2613 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2614 holds the VRSAVE. */
2615 if (fdata.vrsave_offset != 0)
2616 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2618 if (fdata.alloca_reg < 0)
2619 /* If no alloca register used, then fi->frame is the value of the
2620 %sp for this frame, and it is good enough. */
2621 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2623 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
2630 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
2631 struct frame_id *this_id)
2633 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2635 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
2639 rs6000_frame_prev_register (struct frame_info *next_frame,
2641 int regnum, int *optimizedp,
2642 enum lval_type *lvalp, CORE_ADDR *addrp,
2643 int *realnump, void *valuep)
2645 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2647 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
2648 optimizedp, lvalp, addrp, realnump, valuep);
2651 static const struct frame_unwind rs6000_frame_unwind =
2654 rs6000_frame_this_id,
2655 rs6000_frame_prev_register
2658 static const struct frame_unwind *
2659 rs6000_frame_sniffer (struct frame_info *next_frame)
2661 return &rs6000_frame_unwind;
2667 rs6000_frame_base_address (struct frame_info *next_frame,
2670 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2672 return info->initial_sp;
2675 static const struct frame_base rs6000_frame_base = {
2676 &rs6000_frame_unwind,
2677 rs6000_frame_base_address,
2678 rs6000_frame_base_address,
2679 rs6000_frame_base_address
2682 static const struct frame_base *
2683 rs6000_frame_base_sniffer (struct frame_info *next_frame)
2685 return &rs6000_frame_base;
2688 /* Initialize the current architecture based on INFO. If possible, re-use an
2689 architecture from ARCHES, which is a list of architectures already created
2690 during this debugging session.
2692 Called e.g. at program startup, when reading a core file, and when reading
2695 static struct gdbarch *
2696 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2698 struct gdbarch *gdbarch;
2699 struct gdbarch_tdep *tdep;
2700 int wordsize, from_xcoff_exec, from_elf_exec, power, i, off;
2702 const struct variant *v;
2703 enum bfd_architecture arch;
2709 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
2710 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
2712 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
2713 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2715 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2717 /* Check word size. If INFO is from a binary file, infer it from
2718 that, else choose a likely default. */
2719 if (from_xcoff_exec)
2721 if (bfd_xcoff_is_xcoff64 (info.abfd))
2726 else if (from_elf_exec)
2728 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
2735 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
2736 wordsize = info.bfd_arch_info->bits_per_word /
2737 info.bfd_arch_info->bits_per_byte;
2742 /* Find a candidate among extant architectures. */
2743 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2745 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2747 /* Word size in the various PowerPC bfd_arch_info structs isn't
2748 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
2749 separate word size check. */
2750 tdep = gdbarch_tdep (arches->gdbarch);
2751 if (tdep && tdep->wordsize == wordsize)
2752 return arches->gdbarch;
2755 /* None found, create a new architecture from INFO, whose bfd_arch_info
2756 validity depends on the source:
2757 - executable useless
2758 - rs6000_host_arch() good
2760 - "set arch" trust blindly
2761 - GDB startup useless but harmless */
2763 if (!from_xcoff_exec)
2765 arch = info.bfd_arch_info->arch;
2766 mach = info.bfd_arch_info->mach;
2770 arch = bfd_arch_powerpc;
2771 bfd_default_set_arch_mach (&abfd, arch, 0);
2772 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2773 mach = info.bfd_arch_info->mach;
2775 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2776 tdep->wordsize = wordsize;
2778 /* For e500 executables, the apuinfo section is of help here. Such
2779 section contains the identifier and revision number of each
2780 Application-specific Processing Unit that is present on the
2781 chip. The content of the section is determined by the assembler
2782 which looks at each instruction and determines which unit (and
2783 which version of it) can execute it. In our case we just look for
2784 the existance of the section. */
2788 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
2791 arch = info.bfd_arch_info->arch;
2792 mach = bfd_mach_ppc_e500;
2793 bfd_default_set_arch_mach (&abfd, arch, mach);
2794 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2798 gdbarch = gdbarch_alloc (&info, tdep);
2799 power = arch == bfd_arch_rs6000;
2801 /* Initialize the number of real and pseudo registers in each variant. */
2804 /* Choose variant. */
2805 v = find_variant_by_arch (arch, mach);
2809 tdep->regs = v->regs;
2811 tdep->ppc_gp0_regnum = 0;
2812 tdep->ppc_toc_regnum = 2;
2813 tdep->ppc_ps_regnum = 65;
2814 tdep->ppc_cr_regnum = 66;
2815 tdep->ppc_lr_regnum = 67;
2816 tdep->ppc_ctr_regnum = 68;
2817 tdep->ppc_xer_regnum = 69;
2818 if (v->mach == bfd_mach_ppc_601)
2819 tdep->ppc_mq_regnum = 124;
2821 tdep->ppc_mq_regnum = 70;
2823 tdep->ppc_mq_regnum = -1;
2824 tdep->ppc_fp0_regnum = 32;
2825 tdep->ppc_fpscr_regnum = power ? 71 : 70;
2826 tdep->ppc_vr0_regnum = -1;
2827 tdep->ppc_vrsave_regnum = -1;
2828 tdep->ppc_ev0_regnum = -1;
2829 tdep->ppc_ev31_regnum = -1;
2831 set_gdbarch_pc_regnum (gdbarch, 64);
2832 set_gdbarch_sp_regnum (gdbarch, 1);
2833 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
2834 if (sysv_abi && wordsize == 8)
2835 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
2836 else if (sysv_abi && wordsize == 4)
2837 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
2840 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
2841 set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value);
2844 /* Set lr_frame_offset. */
2846 tdep->lr_frame_offset = 16;
2848 tdep->lr_frame_offset = 4;
2850 tdep->lr_frame_offset = 8;
2852 /* Calculate byte offsets in raw register array. */
2853 tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int));
2854 for (i = off = 0; i < v->num_tot_regs; i++)
2856 tdep->regoff[i] = off;
2857 off += regsize (v->regs + i, wordsize);
2860 if (v->arch == bfd_arch_powerpc)
2864 tdep->ppc_vr0_regnum = 71;
2865 tdep->ppc_vrsave_regnum = 104;
2867 case bfd_mach_ppc_7400:
2868 tdep->ppc_vr0_regnum = 119;
2869 tdep->ppc_vrsave_regnum = 152;
2871 case bfd_mach_ppc_e500:
2872 tdep->ppc_gp0_regnum = 41;
2873 tdep->ppc_toc_regnum = -1;
2874 tdep->ppc_ps_regnum = 1;
2875 tdep->ppc_cr_regnum = 2;
2876 tdep->ppc_lr_regnum = 3;
2877 tdep->ppc_ctr_regnum = 4;
2878 tdep->ppc_xer_regnum = 5;
2879 tdep->ppc_ev0_regnum = 7;
2880 tdep->ppc_ev31_regnum = 38;
2881 tdep->ppc_fp0_regnum = -1;
2882 tdep->ppc_fpscr_regnum = -1;
2883 set_gdbarch_pc_regnum (gdbarch, 0);
2884 set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
2885 set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
2886 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
2887 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
2891 /* Sanity check on registers. */
2892 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
2894 /* Select instruction printer. */
2896 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
2898 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
2900 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2902 set_gdbarch_num_regs (gdbarch, v->nregs);
2903 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
2904 set_gdbarch_register_name (gdbarch, rs6000_register_name);
2905 set_gdbarch_deprecated_register_size (gdbarch, wordsize);
2906 set_gdbarch_deprecated_register_bytes (gdbarch, off);
2907 set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte);
2908 set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size);
2909 set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type);
2911 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2912 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2913 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2914 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2915 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2916 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2917 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2919 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
2921 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2922 set_gdbarch_char_signed (gdbarch, 0);
2924 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
2925 if (sysv_abi && wordsize == 8)
2927 set_gdbarch_frame_red_zone_size (gdbarch, 288);
2928 else if (!sysv_abi && wordsize == 4)
2929 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
2930 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
2931 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
2933 set_gdbarch_frame_red_zone_size (gdbarch, 224);
2935 set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible);
2936 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual);
2937 set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw);
2938 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
2939 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
2940 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
2941 is correct for the SysV ABI when the wordsize is 8, but I'm also
2942 fairly certain that ppc_sysv_abi_push_arguments() will give even
2943 worse results since it only works for 32-bit code. So, for the moment,
2944 we're better off calling rs6000_push_arguments() since it works for
2945 64-bit code. At some point in the future, this matter needs to be
2947 if (sysv_abi && wordsize == 4)
2948 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
2949 else if (sysv_abi && wordsize == 8)
2950 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
2952 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
2954 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
2956 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
2957 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2958 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
2960 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
2961 for the descriptor and ".FN" for the entry-point -- a user
2962 specifying "break FN" will unexpectedly end up with a breakpoint
2963 on the descriptor and not the function. This architecture method
2964 transforms any breakpoints on descriptors into breakpoints on the
2965 corresponding entry point. */
2966 if (sysv_abi && wordsize == 8)
2967 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
2969 /* Not sure on this. FIXMEmgo */
2970 set_gdbarch_frame_args_skip (gdbarch, 8);
2973 set_gdbarch_use_struct_convention (gdbarch,
2974 rs6000_use_struct_convention);
2978 /* Handle RS/6000 function pointers (which are really function
2980 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
2981 rs6000_convert_from_func_ptr_addr);
2984 /* Helpers for function argument information. */
2985 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
2987 /* Hook in ABI-specific overrides, if they have been registered. */
2988 gdbarch_init_osabi (info, gdbarch);
2992 case GDB_OSABI_NETBSD_AOUT:
2993 case GDB_OSABI_NETBSD_ELF:
2994 case GDB_OSABI_UNKNOWN:
2995 case GDB_OSABI_LINUX:
2996 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
2997 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
2998 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
2999 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3002 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3004 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3005 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3006 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3007 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3010 if (from_xcoff_exec)
3012 /* NOTE: jimix/2003-06-09: This test should really check for
3013 GDB_OSABI_AIX when that is defined and becomes
3014 available. (Actually, once things are properly split apart,
3015 the test goes away.) */
3016 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
3017 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
3024 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3026 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3031 /* FIXME: Dump gdbarch_tdep. */
3034 static struct cmd_list_element *info_powerpc_cmdlist = NULL;
3037 rs6000_info_powerpc_command (char *args, int from_tty)
3039 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
3042 /* Initialization code. */
3044 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3047 _initialize_rs6000_tdep (void)
3049 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3050 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
3052 /* Add root prefix command for "info powerpc" commands */
3053 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
3054 "Various POWERPC info specific commands.",
3055 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);