1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
43 #include "libbfd.h" /* for bfd_default_set_arch_mach */
44 #include "coff/internal.h" /* for libcoff.h */
45 #include "libcoff.h" /* for xcoff_data */
46 #include "coff/xcoff.h"
51 #include "solib-svr4.h"
54 #include "gdb_assert.h"
57 #include "trad-frame.h"
58 #include "frame-unwind.h"
59 #include "frame-base.h"
61 #include "rs6000-tdep.h"
63 /* If the kernel has to deliver a signal, it pushes a sigcontext
64 structure on the stack and then calls the signal handler, passing
65 the address of the sigcontext in an argument register. Usually
66 the signal handler doesn't save this register, so we have to
67 access the sigcontext structure via an offset from the signal handler
69 The following constants were determined by experimentation on AIX 3.2. */
70 #define SIG_FRAME_PC_OFFSET 96
71 #define SIG_FRAME_LR_OFFSET 108
72 #define SIG_FRAME_FP_OFFSET 284
74 /* To be used by skip_prologue. */
76 struct rs6000_framedata
78 int offset; /* total size of frame --- the distance
79 by which we decrement sp to allocate
81 int saved_gpr; /* smallest # of saved gpr */
82 int saved_fpr; /* smallest # of saved fpr */
83 int saved_vr; /* smallest # of saved vr */
84 int saved_ev; /* smallest # of saved ev */
85 int alloca_reg; /* alloca register number (frame ptr) */
86 char frameless; /* true if frameless functions. */
87 char nosavedpc; /* true if pc not saved. */
88 int gpr_offset; /* offset of saved gprs from prev sp */
89 int fpr_offset; /* offset of saved fprs from prev sp */
90 int vr_offset; /* offset of saved vrs from prev sp */
91 int ev_offset; /* offset of saved evs from prev sp */
92 int lr_offset; /* offset of saved lr */
93 int cr_offset; /* offset of saved cr */
94 int vrsave_offset; /* offset of saved vrsave register */
97 /* Description of a single register. */
101 char *name; /* name of register */
102 unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */
103 unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */
104 unsigned char fpr; /* whether register is floating-point */
105 unsigned char pseudo; /* whether register is pseudo */
106 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
107 This is an ISA SPR number, not a GDB
111 /* Hook for determining the TOC address when calling functions in the
112 inferior under AIX. The initialization code in rs6000-nat.c sets
113 this hook to point to find_toc_address. */
115 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
117 /* Static function prototypes */
119 static CORE_ADDR branch_dest (struct frame_info *frame, int opcode,
120 int instr, CORE_ADDR pc, CORE_ADDR safety);
121 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
122 struct rs6000_framedata *);
124 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
126 altivec_register_p (int regno)
128 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
129 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
132 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
136 /* Return true if REGNO is an SPE register, false otherwise. */
138 spe_register_p (int regno)
140 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
142 /* Is it a reference to EV0 -- EV31, and do we have those? */
143 if (tdep->ppc_ev0_regnum >= 0
144 && tdep->ppc_ev31_regnum >= 0
145 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
148 /* Is it a reference to one of the raw upper GPR halves? */
149 if (tdep->ppc_ev0_upper_regnum >= 0
150 && tdep->ppc_ev0_upper_regnum <= regno
151 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
154 /* Is it a reference to the 64-bit accumulator, and do we have that? */
155 if (tdep->ppc_acc_regnum >= 0
156 && tdep->ppc_acc_regnum == regno)
159 /* Is it a reference to the SPE floating-point status and control register,
160 and do we have that? */
161 if (tdep->ppc_spefscr_regnum >= 0
162 && tdep->ppc_spefscr_regnum == regno)
169 /* Return non-zero if the architecture described by GDBARCH has
170 floating-point registers (f0 --- f31 and fpscr). */
172 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
176 return (tdep->ppc_fp0_regnum >= 0
177 && tdep->ppc_fpscr_regnum >= 0);
181 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
184 This is a helper function for init_sim_regno_table, constructing
185 the table mapping GDB register numbers to sim register numbers; we
186 initialize every element in that table to -1 before we start
189 set_sim_regno (int *table, int gdb_regno, int sim_regno)
191 /* Make sure we don't try to assign any given GDB register a sim
192 register number more than once. */
193 gdb_assert (table[gdb_regno] == -1);
194 table[gdb_regno] = sim_regno;
198 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
199 numbers to simulator register numbers, based on the values placed
200 in the ARCH->tdep->ppc_foo_regnum members. */
202 init_sim_regno_table (struct gdbarch *arch)
204 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
205 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
206 const struct reg *regs = tdep->regs;
207 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
210 /* Presume that all registers not explicitly mentioned below are
211 unavailable from the sim. */
212 for (i = 0; i < total_regs; i++)
215 /* General-purpose registers. */
216 for (i = 0; i < ppc_num_gprs; i++)
217 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
219 /* Floating-point registers. */
220 if (tdep->ppc_fp0_regnum >= 0)
221 for (i = 0; i < ppc_num_fprs; i++)
222 set_sim_regno (sim_regno,
223 tdep->ppc_fp0_regnum + i,
224 sim_ppc_f0_regnum + i);
225 if (tdep->ppc_fpscr_regnum >= 0)
226 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
228 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
229 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
230 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
232 /* Segment registers. */
233 if (tdep->ppc_sr0_regnum >= 0)
234 for (i = 0; i < ppc_num_srs; i++)
235 set_sim_regno (sim_regno,
236 tdep->ppc_sr0_regnum + i,
237 sim_ppc_sr0_regnum + i);
239 /* Altivec registers. */
240 if (tdep->ppc_vr0_regnum >= 0)
242 for (i = 0; i < ppc_num_vrs; i++)
243 set_sim_regno (sim_regno,
244 tdep->ppc_vr0_regnum + i,
245 sim_ppc_vr0_regnum + i);
247 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
248 we can treat this more like the other cases. */
249 set_sim_regno (sim_regno,
250 tdep->ppc_vr0_regnum + ppc_num_vrs,
251 sim_ppc_vscr_regnum);
253 /* vsave is a special-purpose register, so the code below handles it. */
255 /* SPE APU (E500) registers. */
256 if (tdep->ppc_ev0_regnum >= 0)
257 for (i = 0; i < ppc_num_gprs; i++)
258 set_sim_regno (sim_regno,
259 tdep->ppc_ev0_regnum + i,
260 sim_ppc_ev0_regnum + i);
261 if (tdep->ppc_ev0_upper_regnum >= 0)
262 for (i = 0; i < ppc_num_gprs; i++)
263 set_sim_regno (sim_regno,
264 tdep->ppc_ev0_upper_regnum + i,
265 sim_ppc_rh0_regnum + i);
266 if (tdep->ppc_acc_regnum >= 0)
267 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
268 /* spefscr is a special-purpose register, so the code below handles it. */
270 /* Now handle all special-purpose registers. Verify that they
271 haven't mistakenly been assigned numbers by any of the above
273 for (i = 0; i < total_regs; i++)
274 if (regs[i].spr_num >= 0)
275 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
277 /* Drop the initialized array into place. */
278 tdep->sim_regno = sim_regno;
282 /* Given a GDB register number REG, return the corresponding SIM
285 rs6000_register_sim_regno (int reg)
287 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
291 && reg <= gdbarch_num_regs (current_gdbarch)
292 + gdbarch_num_pseudo_regs (current_gdbarch));
293 sim_regno = tdep->sim_regno[reg];
298 return LEGACY_SIM_REGNO_IGNORE;
303 /* Register set support functions. */
306 ppc_supply_reg (struct regcache *regcache, int regnum,
307 const gdb_byte *regs, size_t offset)
309 if (regnum != -1 && offset != -1)
310 regcache_raw_supply (regcache, regnum, regs + offset);
314 ppc_collect_reg (const struct regcache *regcache, int regnum,
315 gdb_byte *regs, size_t offset)
317 if (regnum != -1 && offset != -1)
318 regcache_raw_collect (regcache, regnum, regs + offset);
321 /* Supply register REGNUM in the general-purpose register set REGSET
322 from the buffer specified by GREGS and LEN to register cache
323 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
326 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
327 int regnum, const void *gregs, size_t len)
329 struct gdbarch *gdbarch = get_regcache_arch (regcache);
330 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
331 const struct ppc_reg_offsets *offsets = regset->descr;
335 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
336 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
339 if (regnum == -1 || regnum == i)
340 ppc_supply_reg (regcache, i, gregs, offset);
343 if (regnum == -1 || regnum == gdbarch_pc_regnum (current_gdbarch))
344 ppc_supply_reg (regcache, gdbarch_pc_regnum (current_gdbarch),
345 gregs, offsets->pc_offset);
346 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
347 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
348 gregs, offsets->ps_offset);
349 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
350 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
351 gregs, offsets->cr_offset);
352 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
353 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
354 gregs, offsets->lr_offset);
355 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
356 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
357 gregs, offsets->ctr_offset);
358 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
359 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
360 gregs, offsets->cr_offset);
361 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
362 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
365 /* Supply register REGNUM in the floating-point register set REGSET
366 from the buffer specified by FPREGS and LEN to register cache
367 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
370 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
371 int regnum, const void *fpregs, size_t len)
373 struct gdbarch *gdbarch = get_regcache_arch (regcache);
374 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
375 const struct ppc_reg_offsets *offsets = regset->descr;
379 gdb_assert (ppc_floating_point_unit_p (gdbarch));
381 offset = offsets->f0_offset;
382 for (i = tdep->ppc_fp0_regnum;
383 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
386 if (regnum == -1 || regnum == i)
387 ppc_supply_reg (regcache, i, fpregs, offset);
390 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
391 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
392 fpregs, offsets->fpscr_offset);
395 /* Collect register REGNUM in the general-purpose register set
396 REGSET. from register cache REGCACHE into the buffer specified by
397 GREGS and LEN. If REGNUM is -1, do this for all registers in
401 ppc_collect_gregset (const struct regset *regset,
402 const struct regcache *regcache,
403 int regnum, void *gregs, size_t len)
405 struct gdbarch *gdbarch = get_regcache_arch (regcache);
406 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
407 const struct ppc_reg_offsets *offsets = regset->descr;
411 offset = offsets->r0_offset;
412 for (i = tdep->ppc_gp0_regnum;
413 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
416 if (regnum == -1 || regnum == i)
417 ppc_collect_reg (regcache, i, gregs, offset);
420 if (regnum == -1 || regnum == gdbarch_pc_regnum (current_gdbarch))
421 ppc_collect_reg (regcache, gdbarch_pc_regnum (current_gdbarch),
422 gregs, offsets->pc_offset);
423 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
424 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
425 gregs, offsets->ps_offset);
426 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
427 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
428 gregs, offsets->cr_offset);
429 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
430 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
431 gregs, offsets->lr_offset);
432 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
433 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
434 gregs, offsets->ctr_offset);
435 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
436 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
437 gregs, offsets->xer_offset);
438 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
439 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
440 gregs, offsets->mq_offset);
443 /* Collect register REGNUM in the floating-point register set
444 REGSET. from register cache REGCACHE into the buffer specified by
445 FPREGS and LEN. If REGNUM is -1, do this for all registers in
449 ppc_collect_fpregset (const struct regset *regset,
450 const struct regcache *regcache,
451 int regnum, void *fpregs, size_t len)
453 struct gdbarch *gdbarch = get_regcache_arch (regcache);
454 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
455 const struct ppc_reg_offsets *offsets = regset->descr;
459 gdb_assert (ppc_floating_point_unit_p (gdbarch));
461 offset = offsets->f0_offset;
462 for (i = tdep->ppc_fp0_regnum;
463 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
466 if (regnum == -1 || regnum == i)
467 ppc_collect_reg (regcache, i, fpregs, offset);
470 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
471 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
472 fpregs, offsets->fpscr_offset);
476 /* Read a LEN-byte address from debugged memory address MEMADDR. */
479 read_memory_addr (CORE_ADDR memaddr, int len)
481 return read_memory_unsigned_integer (memaddr, len);
485 rs6000_skip_prologue (CORE_ADDR pc)
487 struct rs6000_framedata frame;
488 CORE_ADDR limit_pc, func_addr;
490 /* See if we can determine the end of the prologue via the symbol table.
491 If so, then return either PC, or the PC after the prologue, whichever
493 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
495 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
496 if (post_prologue_pc != 0)
497 return max (pc, post_prologue_pc);
500 /* Can't determine prologue from the symbol table, need to examine
503 /* Find an upper limit on the function prologue using the debug
504 information. If the debug information could not be used to provide
505 that bound, then use an arbitrary large number as the upper bound. */
506 limit_pc = skip_prologue_using_sal (pc);
508 limit_pc = pc + 100; /* Magic. */
510 pc = skip_prologue (pc, limit_pc, &frame);
515 insn_changes_sp_or_jumps (unsigned long insn)
517 int opcode = (insn >> 26) & 0x03f;
518 int sd = (insn >> 21) & 0x01f;
519 int a = (insn >> 16) & 0x01f;
520 int subcode = (insn >> 1) & 0x3ff;
522 /* Changes the stack pointer. */
524 /* NOTE: There are many ways to change the value of a given register.
525 The ways below are those used when the register is R1, the SP,
526 in a funtion's epilogue. */
528 if (opcode == 31 && subcode == 444 && a == 1)
529 return 1; /* mr R1,Rn */
530 if (opcode == 14 && sd == 1)
531 return 1; /* addi R1,Rn,simm */
532 if (opcode == 58 && sd == 1)
533 return 1; /* ld R1,ds(Rn) */
535 /* Transfers control. */
541 if (opcode == 19 && subcode == 16)
543 if (opcode == 19 && subcode == 528)
544 return 1; /* bcctr */
549 /* Return true if we are in the function's epilogue, i.e. after the
550 instruction that destroyed the function's stack frame.
552 1) scan forward from the point of execution:
553 a) If you find an instruction that modifies the stack pointer
554 or transfers control (except a return), execution is not in
556 b) Stop scanning if you find a return instruction or reach the
557 end of the function or reach the hard limit for the size of
559 2) scan backward from the point of execution:
560 a) If you find an instruction that modifies the stack pointer,
561 execution *is* in an epilogue, return.
562 b) Stop scanning if you reach an instruction that transfers
563 control or the beginning of the function or reach the hard
564 limit for the size of an epilogue. */
567 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
569 bfd_byte insn_buf[PPC_INSN_SIZE];
570 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
572 struct frame_info *curfrm;
574 /* Find the search limits based on function boundaries and hard limit. */
576 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
579 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
580 if (epilogue_start < func_start) epilogue_start = func_start;
582 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
583 if (epilogue_end > func_end) epilogue_end = func_end;
585 curfrm = get_current_frame ();
587 /* Scan forward until next 'blr'. */
589 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
591 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
593 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
594 if (insn == 0x4e800020)
596 if (insn_changes_sp_or_jumps (insn))
600 /* Scan backward until adjustment to stack pointer (R1). */
602 for (scan_pc = pc - PPC_INSN_SIZE;
603 scan_pc >= epilogue_start;
604 scan_pc -= PPC_INSN_SIZE)
606 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
608 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
609 if (insn_changes_sp_or_jumps (insn))
616 /* Get the ith function argument for the current function. */
618 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
621 return get_frame_register_unsigned (frame, 3 + argi);
624 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
627 branch_dest (struct frame_info *frame, int opcode, int instr,
628 CORE_ADDR pc, CORE_ADDR safety)
630 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
636 absolute = (int) ((instr >> 1) & 1);
641 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
645 dest = pc + immediate;
649 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
653 dest = pc + immediate;
657 ext_op = (instr >> 1) & 0x3ff;
659 if (ext_op == 16) /* br conditional register */
661 dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3;
663 /* If we are about to return from a signal handler, dest is
664 something like 0x3c90. The current frame is a signal handler
665 caller frame, upon completion of the sigreturn system call
666 execution will return to the saved PC in the frame. */
667 if (dest < tdep->text_segment_base)
668 dest = read_memory_addr (get_frame_base (frame) + SIG_FRAME_PC_OFFSET,
672 else if (ext_op == 528) /* br cond to count reg */
674 dest = get_frame_register_unsigned (frame, tdep->ppc_ctr_regnum) & ~3;
676 /* If we are about to execute a system call, dest is something
677 like 0x22fc or 0x3b00. Upon completion the system call
678 will return to the address in the link register. */
679 if (dest < tdep->text_segment_base)
680 dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3;
689 return (dest < tdep->text_segment_base) ? safety : dest;
693 /* Sequence of bytes for breakpoint instruction. */
695 const static unsigned char *
696 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
698 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
699 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
701 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
702 return big_breakpoint;
704 return little_breakpoint;
708 /* Instruction masks used during single-stepping of atomic sequences. */
709 #define LWARX_MASK 0xfc0007fe
710 #define LWARX_INSTRUCTION 0x7c000028
711 #define LDARX_INSTRUCTION 0x7c0000A8
712 #define STWCX_MASK 0xfc0007ff
713 #define STWCX_INSTRUCTION 0x7c00012d
714 #define STDCX_INSTRUCTION 0x7c0001ad
715 #define BC_MASK 0xfc000000
716 #define BC_INSTRUCTION 0x40000000
718 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
719 instruction and ending with a STWCX/STDCX instruction. If such a sequence
720 is found, attempt to step through it. A breakpoint is placed at the end of
724 deal_with_atomic_sequence (struct frame_info *frame)
726 CORE_ADDR pc = get_frame_pc (frame);
727 CORE_ADDR breaks[2] = {-1, -1};
729 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
730 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
731 int insn = read_memory_integer (loc, PPC_INSN_SIZE);
734 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
735 const int atomic_sequence_length = 16; /* Instruction sequence length. */
736 int opcode; /* Branch instruction's OPcode. */
737 int bc_insn_count = 0; /* Conditional branch instruction count. */
739 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
740 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
741 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
744 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
746 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
748 loc += PPC_INSN_SIZE;
749 insn = read_memory_integer (loc, PPC_INSN_SIZE);
751 /* Assume that there is at most one conditional branch in the atomic
752 sequence. If a conditional branch is found, put a breakpoint in
753 its destination address. */
754 if ((insn & BC_MASK) == BC_INSTRUCTION)
756 if (bc_insn_count >= 1)
757 return 0; /* More than one conditional branch found, fallback
758 to the standard single-step code. */
761 branch_bp = branch_dest (frame, opcode, insn, pc, breaks[0]);
765 breaks[1] = branch_bp;
771 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
772 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
776 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
777 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
778 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
782 loc += PPC_INSN_SIZE;
783 insn = read_memory_integer (loc, PPC_INSN_SIZE);
785 /* Insert a breakpoint right after the end of the atomic sequence. */
788 /* Check for duplicated breakpoints. Check also for a breakpoint
789 placed (branch instruction's destination) at the stwcx/stdcx
790 instruction, this resets the reservation and take us back to the
791 lwarx/ldarx instruction at the beginning of the atomic sequence. */
792 if (last_breakpoint && ((breaks[1] == breaks[0])
793 || (breaks[1] == closing_insn)))
796 /* Effectively inserts the breakpoints. */
797 for (index = 0; index <= last_breakpoint; index++)
798 insert_single_step_breakpoint (breaks[index]);
803 /* AIX does not support PT_STEP. Simulate it. */
806 rs6000_software_single_step (struct frame_info *frame)
810 const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
816 loc = get_frame_pc (frame);
818 insn = read_memory_integer (loc, 4);
820 if (deal_with_atomic_sequence (frame))
823 breaks[0] = loc + breakp_sz;
825 breaks[1] = branch_dest (frame, opcode, insn, loc, breaks[0]);
827 /* Don't put two breakpoints on the same address. */
828 if (breaks[1] == breaks[0])
831 for (ii = 0; ii < 2; ++ii)
833 /* ignore invalid breakpoint. */
834 if (breaks[ii] == -1)
836 insert_single_step_breakpoint (breaks[ii]);
839 errno = 0; /* FIXME, don't ignore errors! */
840 /* What errors? {read,write}_memory call error(). */
845 /* return pc value after skipping a function prologue and also return
846 information about a function frame.
848 in struct rs6000_framedata fdata:
849 - frameless is TRUE, if function does not have a frame.
850 - nosavedpc is TRUE, if function does not save %pc value in its frame.
851 - offset is the initial size of this stack frame --- the amount by
852 which we decrement the sp to allocate the frame.
853 - saved_gpr is the number of the first saved gpr.
854 - saved_fpr is the number of the first saved fpr.
855 - saved_vr is the number of the first saved vr.
856 - saved_ev is the number of the first saved ev.
857 - alloca_reg is the number of the register used for alloca() handling.
859 - gpr_offset is the offset of the first saved gpr from the previous frame.
860 - fpr_offset is the offset of the first saved fpr from the previous frame.
861 - vr_offset is the offset of the first saved vr from the previous frame.
862 - ev_offset is the offset of the first saved ev from the previous frame.
863 - lr_offset is the offset of the saved lr
864 - cr_offset is the offset of the saved cr
865 - vrsave_offset is the offset of the saved vrsave register
868 #define SIGNED_SHORT(x) \
869 ((sizeof (short) == 2) \
870 ? ((int)(short)(x)) \
871 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
873 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
875 /* Limit the number of skipped non-prologue instructions, as the examining
876 of the prologue is expensive. */
877 static int max_skip_non_prologue_insns = 10;
879 /* Return nonzero if the given instruction OP can be part of the prologue
880 of a function and saves a parameter on the stack. FRAMEP should be
881 set if one of the previous instructions in the function has set the
885 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
887 /* Move parameters from argument registers to temporary register. */
888 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
890 /* Rx must be scratch register r0. */
891 const int rx_regno = (op >> 16) & 31;
892 /* Ry: Only r3 - r10 are used for parameter passing. */
893 const int ry_regno = GET_SRC_REG (op);
895 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
897 *r0_contains_arg = 1;
904 /* Save a General Purpose Register on stack. */
906 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
907 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
909 /* Rx: Only r3 - r10 are used for parameter passing. */
910 const int rx_regno = GET_SRC_REG (op);
912 return (rx_regno >= 3 && rx_regno <= 10);
915 /* Save a General Purpose Register on stack via the Frame Pointer. */
918 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
919 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
920 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
922 /* Rx: Usually, only r3 - r10 are used for parameter passing.
923 However, the compiler sometimes uses r0 to hold an argument. */
924 const int rx_regno = GET_SRC_REG (op);
926 return ((rx_regno >= 3 && rx_regno <= 10)
927 || (rx_regno == 0 && *r0_contains_arg));
930 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
932 /* Only f2 - f8 are used for parameter passing. */
933 const int src_regno = GET_SRC_REG (op);
935 return (src_regno >= 2 && src_regno <= 8);
938 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
940 /* Only f2 - f8 are used for parameter passing. */
941 const int src_regno = GET_SRC_REG (op);
943 return (src_regno >= 2 && src_regno <= 8);
946 /* Not an insn that saves a parameter on stack. */
950 /* Assuming that INSN is a "bl" instruction located at PC, return
951 nonzero if the destination of the branch is a "blrl" instruction.
953 This sequence is sometimes found in certain function prologues.
954 It allows the function to load the LR register with a value that
955 they can use to access PIC data using PC-relative offsets. */
958 bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
965 absolute = (int) ((insn >> 1) & 1);
966 immediate = ((insn & ~3) << 6) >> 6;
970 dest = pc + immediate;
972 dest_insn = read_memory_integer (dest, 4);
973 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
980 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
982 CORE_ADDR orig_pc = pc;
983 CORE_ADDR last_prologue_pc = pc;
984 CORE_ADDR li_found_pc = 0;
988 long vr_saved_offset = 0;
997 int minimal_toc_loaded = 0;
998 int prev_insn_was_prologue_insn = 1;
999 int num_skip_non_prologue_insns = 0;
1000 int r0_contains_arg = 0;
1001 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
1002 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1004 memset (fdata, 0, sizeof (struct rs6000_framedata));
1005 fdata->saved_gpr = -1;
1006 fdata->saved_fpr = -1;
1007 fdata->saved_vr = -1;
1008 fdata->saved_ev = -1;
1009 fdata->alloca_reg = -1;
1010 fdata->frameless = 1;
1011 fdata->nosavedpc = 1;
1015 /* Sometimes it isn't clear if an instruction is a prologue
1016 instruction or not. When we encounter one of these ambiguous
1017 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1018 Otherwise, we'll assume that it really is a prologue instruction. */
1019 if (prev_insn_was_prologue_insn)
1020 last_prologue_pc = pc;
1022 /* Stop scanning if we've hit the limit. */
1026 prev_insn_was_prologue_insn = 1;
1028 /* Fetch the instruction and convert it to an integer. */
1029 if (target_read_memory (pc, buf, 4))
1031 op = extract_unsigned_integer (buf, 4);
1033 if ((op & 0xfc1fffff) == 0x7c0802a6)
1035 /* Since shared library / PIC code, which needs to get its
1036 address at runtime, can appear to save more than one link
1050 remember just the first one, but skip over additional
1053 lr_reg = (op & 0x03e00000);
1055 r0_contains_arg = 0;
1058 else if ((op & 0xfc1fffff) == 0x7c000026)
1060 cr_reg = (op & 0x03e00000);
1062 r0_contains_arg = 0;
1066 else if ((op & 0xfc1f0000) == 0xd8010000)
1067 { /* stfd Rx,NUM(r1) */
1068 reg = GET_SRC_REG (op);
1069 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1071 fdata->saved_fpr = reg;
1072 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1077 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1078 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1079 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1080 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1083 reg = GET_SRC_REG (op);
1084 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1086 fdata->saved_gpr = reg;
1087 if ((op & 0xfc1f0003) == 0xf8010000)
1089 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1094 else if ((op & 0xffff0000) == 0x60000000)
1097 /* Allow nops in the prologue, but do not consider them to
1098 be part of the prologue unless followed by other prologue
1100 prev_insn_was_prologue_insn = 0;
1104 else if ((op & 0xffff0000) == 0x3c000000)
1105 { /* addis 0,0,NUM, used
1106 for >= 32k frames */
1107 fdata->offset = (op & 0x0000ffff) << 16;
1108 fdata->frameless = 0;
1109 r0_contains_arg = 0;
1113 else if ((op & 0xffff0000) == 0x60000000)
1114 { /* ori 0,0,NUM, 2nd ha
1115 lf of >= 32k frames */
1116 fdata->offset |= (op & 0x0000ffff);
1117 fdata->frameless = 0;
1118 r0_contains_arg = 0;
1122 else if (lr_reg >= 0 &&
1123 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1124 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1125 /* stw Rx, NUM(r1) */
1126 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1127 /* stwu Rx, NUM(r1) */
1128 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1129 { /* where Rx == lr */
1130 fdata->lr_offset = offset;
1131 fdata->nosavedpc = 0;
1132 /* Invalidate lr_reg, but don't set it to -1.
1133 That would mean that it had never been set. */
1135 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1136 (op & 0xfc000000) == 0x90000000) /* stw */
1138 /* Does not update r1, so add displacement to lr_offset. */
1139 fdata->lr_offset += SIGNED_SHORT (op);
1144 else if (cr_reg >= 0 &&
1145 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1146 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1147 /* stw Rx, NUM(r1) */
1148 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1149 /* stwu Rx, NUM(r1) */
1150 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1151 { /* where Rx == cr */
1152 fdata->cr_offset = offset;
1153 /* Invalidate cr_reg, but don't set it to -1.
1154 That would mean that it had never been set. */
1156 if ((op & 0xfc000003) == 0xf8000000 ||
1157 (op & 0xfc000000) == 0x90000000)
1159 /* Does not update r1, so add displacement to cr_offset. */
1160 fdata->cr_offset += SIGNED_SHORT (op);
1165 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1167 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1168 prediction bits. If the LR has already been saved, we can
1172 else if (op == 0x48000005)
1178 else if (op == 0x48000004)
1183 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1184 in V.4 -mminimal-toc */
1185 (op & 0xffff0000) == 0x3bde0000)
1186 { /* addi 30,30,foo@l */
1190 else if ((op & 0xfc000001) == 0x48000001)
1194 fdata->frameless = 0;
1196 /* If the return address has already been saved, we can skip
1197 calls to blrl (for PIC). */
1198 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
1201 /* Don't skip over the subroutine call if it is not within
1202 the first three instructions of the prologue and either
1203 we have no line table information or the line info tells
1204 us that the subroutine call is not part of the line
1205 associated with the prologue. */
1206 if ((pc - orig_pc) > 8)
1208 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1209 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1211 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1215 op = read_memory_integer (pc + 4, 4);
1217 /* At this point, make sure this is not a trampoline
1218 function (a function that simply calls another functions,
1219 and nothing else). If the next is not a nop, this branch
1220 was part of the function prologue. */
1222 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1223 break; /* don't skip over
1228 /* update stack pointer */
1229 else if ((op & 0xfc1f0000) == 0x94010000)
1230 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1231 fdata->frameless = 0;
1232 fdata->offset = SIGNED_SHORT (op);
1233 offset = fdata->offset;
1236 else if ((op & 0xfc1f016a) == 0x7c01016e)
1237 { /* stwux rX,r1,rY */
1238 /* no way to figure out what r1 is going to be */
1239 fdata->frameless = 0;
1240 offset = fdata->offset;
1243 else if ((op & 0xfc1f0003) == 0xf8010001)
1244 { /* stdu rX,NUM(r1) */
1245 fdata->frameless = 0;
1246 fdata->offset = SIGNED_SHORT (op & ~3UL);
1247 offset = fdata->offset;
1250 else if ((op & 0xfc1f016a) == 0x7c01016a)
1251 { /* stdux rX,r1,rY */
1252 /* no way to figure out what r1 is going to be */
1253 fdata->frameless = 0;
1254 offset = fdata->offset;
1257 else if ((op & 0xffff0000) == 0x38210000)
1258 { /* addi r1,r1,SIMM */
1259 fdata->frameless = 0;
1260 fdata->offset += SIGNED_SHORT (op);
1261 offset = fdata->offset;
1264 /* Load up minimal toc pointer. Do not treat an epilogue restore
1265 of r31 as a minimal TOC load. */
1266 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1267 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1269 && !minimal_toc_loaded)
1271 minimal_toc_loaded = 1;
1274 /* move parameters from argument registers to local variable
1277 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1278 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1279 (((op >> 21) & 31) <= 10) &&
1280 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1284 /* store parameters in stack */
1286 /* Move parameters from argument registers to temporary register. */
1287 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1291 /* Set up frame pointer */
1293 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1294 || op == 0x7c3f0b78)
1296 fdata->frameless = 0;
1298 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1301 /* Another way to set up the frame pointer. */
1303 else if ((op & 0xfc1fffff) == 0x38010000)
1304 { /* addi rX, r1, 0x0 */
1305 fdata->frameless = 0;
1307 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1308 + ((op & ~0x38010000) >> 21));
1311 /* AltiVec related instructions. */
1312 /* Store the vrsave register (spr 256) in another register for
1313 later manipulation, or load a register into the vrsave
1314 register. 2 instructions are used: mfvrsave and
1315 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1316 and mtspr SPR256, Rn. */
1317 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1318 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1319 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1321 vrsave_reg = GET_SRC_REG (op);
1324 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1328 /* Store the register where vrsave was saved to onto the stack:
1329 rS is the register where vrsave was stored in a previous
1331 /* 100100 sssss 00001 dddddddd dddddddd */
1332 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1334 if (vrsave_reg == GET_SRC_REG (op))
1336 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1341 /* Compute the new value of vrsave, by modifying the register
1342 where vrsave was saved to. */
1343 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1344 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1348 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1349 in a pair of insns to save the vector registers on the
1351 /* 001110 00000 00000 iiii iiii iiii iiii */
1352 /* 001110 01110 00000 iiii iiii iiii iiii */
1353 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1354 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1356 if ((op & 0xffff0000) == 0x38000000)
1357 r0_contains_arg = 0;
1359 vr_saved_offset = SIGNED_SHORT (op);
1361 /* This insn by itself is not part of the prologue, unless
1362 if part of the pair of insns mentioned above. So do not
1363 record this insn as part of the prologue yet. */
1364 prev_insn_was_prologue_insn = 0;
1366 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1367 /* 011111 sssss 11111 00000 00111001110 */
1368 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1370 if (pc == (li_found_pc + 4))
1372 vr_reg = GET_SRC_REG (op);
1373 /* If this is the first vector reg to be saved, or if
1374 it has a lower number than others previously seen,
1375 reupdate the frame info. */
1376 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1378 fdata->saved_vr = vr_reg;
1379 fdata->vr_offset = vr_saved_offset + offset;
1381 vr_saved_offset = -1;
1386 /* End AltiVec related instructions. */
1388 /* Start BookE related instructions. */
1389 /* Store gen register S at (r31+uimm).
1390 Any register less than r13 is volatile, so we don't care. */
1391 /* 000100 sssss 11111 iiiii 01100100001 */
1392 else if (arch_info->mach == bfd_mach_ppc_e500
1393 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1395 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1398 ev_reg = GET_SRC_REG (op);
1399 imm = (op >> 11) & 0x1f;
1400 ev_offset = imm * 8;
1401 /* If this is the first vector reg to be saved, or if
1402 it has a lower number than others previously seen,
1403 reupdate the frame info. */
1404 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1406 fdata->saved_ev = ev_reg;
1407 fdata->ev_offset = ev_offset + offset;
1412 /* Store gen register rS at (r1+rB). */
1413 /* 000100 sssss 00001 bbbbb 01100100000 */
1414 else if (arch_info->mach == bfd_mach_ppc_e500
1415 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1417 if (pc == (li_found_pc + 4))
1419 ev_reg = GET_SRC_REG (op);
1420 /* If this is the first vector reg to be saved, or if
1421 it has a lower number than others previously seen,
1422 reupdate the frame info. */
1423 /* We know the contents of rB from the previous instruction. */
1424 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1426 fdata->saved_ev = ev_reg;
1427 fdata->ev_offset = vr_saved_offset + offset;
1429 vr_saved_offset = -1;
1435 /* Store gen register r31 at (rA+uimm). */
1436 /* 000100 11111 aaaaa iiiii 01100100001 */
1437 else if (arch_info->mach == bfd_mach_ppc_e500
1438 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1440 /* Wwe know that the source register is 31 already, but
1441 it can't hurt to compute it. */
1442 ev_reg = GET_SRC_REG (op);
1443 ev_offset = ((op >> 11) & 0x1f) * 8;
1444 /* If this is the first vector reg to be saved, or if
1445 it has a lower number than others previously seen,
1446 reupdate the frame info. */
1447 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1449 fdata->saved_ev = ev_reg;
1450 fdata->ev_offset = ev_offset + offset;
1455 /* Store gen register S at (r31+r0).
1456 Store param on stack when offset from SP bigger than 4 bytes. */
1457 /* 000100 sssss 11111 00000 01100100000 */
1458 else if (arch_info->mach == bfd_mach_ppc_e500
1459 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1461 if (pc == (li_found_pc + 4))
1463 if ((op & 0x03e00000) >= 0x01a00000)
1465 ev_reg = GET_SRC_REG (op);
1466 /* If this is the first vector reg to be saved, or if
1467 it has a lower number than others previously seen,
1468 reupdate the frame info. */
1469 /* We know the contents of r0 from the previous
1471 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1473 fdata->saved_ev = ev_reg;
1474 fdata->ev_offset = vr_saved_offset + offset;
1478 vr_saved_offset = -1;
1483 /* End BookE related instructions. */
1487 /* Not a recognized prologue instruction.
1488 Handle optimizer code motions into the prologue by continuing
1489 the search if we have no valid frame yet or if the return
1490 address is not yet saved in the frame. */
1491 if (fdata->frameless == 0 && fdata->nosavedpc == 0)
1494 if (op == 0x4e800020 /* blr */
1495 || op == 0x4e800420) /* bctr */
1496 /* Do not scan past epilogue in frameless functions or
1499 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1500 /* Never skip branches. */
1503 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1504 /* Do not scan too many insns, scanning insns is expensive with
1508 /* Continue scanning. */
1509 prev_insn_was_prologue_insn = 0;
1515 /* I have problems with skipping over __main() that I need to address
1516 * sometime. Previously, I used to use misc_function_vector which
1517 * didn't work as well as I wanted to be. -MGO */
1519 /* If the first thing after skipping a prolog is a branch to a function,
1520 this might be a call to an initializer in main(), introduced by gcc2.
1521 We'd like to skip over it as well. Fortunately, xlc does some extra
1522 work before calling a function right after a prologue, thus we can
1523 single out such gcc2 behaviour. */
1526 if ((op & 0xfc000001) == 0x48000001)
1527 { /* bl foo, an initializer function? */
1528 op = read_memory_integer (pc + 4, 4);
1530 if (op == 0x4def7b82)
1531 { /* cror 0xf, 0xf, 0xf (nop) */
1533 /* Check and see if we are in main. If so, skip over this
1534 initializer function as well. */
1536 tmp = find_pc_misc_function (pc);
1538 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1544 fdata->offset = -fdata->offset;
1545 return last_prologue_pc;
1549 /*************************************************************************
1550 Support for creating pushing a dummy frame into the stack, and popping
1552 *************************************************************************/
1555 /* All the ABI's require 16 byte alignment. */
1557 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1559 return (addr & -16);
1562 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1563 the first eight words of the argument list (that might be less than
1564 eight parameters if some parameters occupy more than one word) are
1565 passed in r3..r10 registers. float and double parameters are
1566 passed in fpr's, in addition to that. Rest of the parameters if any
1567 are passed in user stack. There might be cases in which half of the
1568 parameter is copied into registers, the other half is pushed into
1571 Stack must be aligned on 64-bit boundaries when synthesizing
1574 If the function is returning a structure, then the return address is passed
1575 in r3, then the first 7 words of the parameters can be passed in registers,
1576 starting from r4. */
1579 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1580 struct regcache *regcache, CORE_ADDR bp_addr,
1581 int nargs, struct value **args, CORE_ADDR sp,
1582 int struct_return, CORE_ADDR struct_addr)
1584 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1587 int argno; /* current argument number */
1588 int argbytes; /* current argument byte */
1589 gdb_byte tmp_buffer[50];
1590 int f_argno = 0; /* current floating point argno */
1591 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1592 CORE_ADDR func_addr = find_function_addr (function, NULL);
1594 struct value *arg = 0;
1599 /* The calling convention this function implements assumes the
1600 processor has floating-point registers. We shouldn't be using it
1601 on PPC variants that lack them. */
1602 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1604 /* The first eight words of ther arguments are passed in registers.
1605 Copy them appropriately. */
1608 /* If the function is returning a `struct', then the first word
1609 (which will be passed in r3) is used for struct return address.
1610 In that case we should advance one word and start from r4
1611 register to copy parameters. */
1614 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1620 effectively indirect call... gcc does...
1622 return_val example( float, int);
1625 float in fp0, int in r3
1626 offset of stack on overflow 8/16
1627 for varargs, must go by type.
1629 float in r3&r4, int in r5
1630 offset of stack on overflow different
1632 return in r3 or f0. If no float, must study how gcc emulates floats;
1633 pay attention to arg promotion.
1634 User may have to cast\args to handle promotion correctly
1635 since gdb won't know if prototype supplied or not.
1638 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1640 int reg_size = register_size (current_gdbarch, ii + 3);
1643 type = check_typedef (value_type (arg));
1644 len = TYPE_LENGTH (type);
1646 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1649 /* Floating point arguments are passed in fpr's, as well as gpr's.
1650 There are 13 fpr's reserved for passing parameters. At this point
1651 there is no way we would run out of them. */
1653 gdb_assert (len <= 8);
1655 regcache_cooked_write (regcache,
1656 tdep->ppc_fp0_regnum + 1 + f_argno,
1657 value_contents (arg));
1664 /* Argument takes more than one register. */
1665 while (argbytes < len)
1667 gdb_byte word[MAX_REGISTER_SIZE];
1668 memset (word, 0, reg_size);
1670 ((char *) value_contents (arg)) + argbytes,
1671 (len - argbytes) > reg_size
1672 ? reg_size : len - argbytes);
1673 regcache_cooked_write (regcache,
1674 tdep->ppc_gp0_regnum + 3 + ii,
1676 ++ii, argbytes += reg_size;
1679 goto ran_out_of_registers_for_arguments;
1686 /* Argument can fit in one register. No problem. */
1687 int adj = gdbarch_byte_order (current_gdbarch)
1688 == BFD_ENDIAN_BIG ? reg_size - len : 0;
1689 gdb_byte word[MAX_REGISTER_SIZE];
1691 memset (word, 0, reg_size);
1692 memcpy (word, value_contents (arg), len);
1693 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1698 ran_out_of_registers_for_arguments:
1700 regcache_cooked_read_unsigned (regcache,
1701 gdbarch_sp_regnum (current_gdbarch),
1704 /* Location for 8 parameters are always reserved. */
1707 /* Another six words for back chain, TOC register, link register, etc. */
1710 /* Stack pointer must be quadword aligned. */
1713 /* If there are more arguments, allocate space for them in
1714 the stack, then push them starting from the ninth one. */
1716 if ((argno < nargs) || argbytes)
1722 space += ((len - argbytes + 3) & -4);
1728 for (; jj < nargs; ++jj)
1730 struct value *val = args[jj];
1731 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
1734 /* Add location required for the rest of the parameters. */
1735 space = (space + 15) & -16;
1738 /* This is another instance we need to be concerned about
1739 securing our stack space. If we write anything underneath %sp
1740 (r1), we might conflict with the kernel who thinks he is free
1741 to use this area. So, update %sp first before doing anything
1744 regcache_raw_write_signed (regcache,
1745 gdbarch_sp_regnum (current_gdbarch), sp);
1747 /* If the last argument copied into the registers didn't fit there
1748 completely, push the rest of it into stack. */
1752 write_memory (sp + 24 + (ii * 4),
1753 value_contents (arg) + argbytes,
1756 ii += ((len - argbytes + 3) & -4) / 4;
1759 /* Push the rest of the arguments into stack. */
1760 for (; argno < nargs; ++argno)
1764 type = check_typedef (value_type (arg));
1765 len = TYPE_LENGTH (type);
1768 /* Float types should be passed in fpr's, as well as in the
1770 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1773 gdb_assert (len <= 8);
1775 regcache_cooked_write (regcache,
1776 tdep->ppc_fp0_regnum + 1 + f_argno,
1777 value_contents (arg));
1781 write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
1782 ii += ((len + 3) & -4) / 4;
1786 /* Set the stack pointer. According to the ABI, the SP is meant to
1787 be set _before_ the corresponding stack space is used. On AIX,
1788 this even applies when the target has been completely stopped!
1789 Not doing this can lead to conflicts with the kernel which thinks
1790 that it still has control over this not-yet-allocated stack
1792 regcache_raw_write_signed (regcache, gdbarch_sp_regnum (current_gdbarch), sp);
1794 /* Set back chain properly. */
1795 store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
1796 write_memory (sp, tmp_buffer, wordsize);
1798 /* Point the inferior function call's return address at the dummy's
1800 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1802 /* Set the TOC register, get the value from the objfile reader
1803 which, in turn, gets it from the VMAP table. */
1804 if (rs6000_find_toc_address_hook != NULL)
1806 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1807 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1810 target_store_registers (regcache, -1);
1814 static enum return_value_convention
1815 rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype,
1816 struct regcache *regcache, gdb_byte *readbuf,
1817 const gdb_byte *writebuf)
1819 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1822 /* The calling convention this function implements assumes the
1823 processor has floating-point registers. We shouldn't be using it
1824 on PowerPC variants that lack them. */
1825 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1827 /* AltiVec extension: Functions that declare a vector data type as a
1828 return value place that return value in VR2. */
1829 if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype)
1830 && TYPE_LENGTH (valtype) == 16)
1833 regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
1835 regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
1837 return RETURN_VALUE_REGISTER_CONVENTION;
1840 /* If the called subprogram returns an aggregate, there exists an
1841 implicit first argument, whose value is the address of a caller-
1842 allocated buffer into which the callee is assumed to store its
1843 return value. All explicit parameters are appropriately
1845 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1846 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1847 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1848 return RETURN_VALUE_STRUCT_CONVENTION;
1850 /* Scalar floating-point values are returned in FPR1 for float or
1851 double, and in FPR1:FPR2 for quadword precision. Fortran
1852 complex*8 and complex*16 are returned in FPR1:FPR2, and
1853 complex*32 is returned in FPR1:FPR4. */
1854 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
1855 && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8))
1857 struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
1860 /* FIXME: kettenis/2007-01-01: Add support for quadword
1861 precision and complex. */
1865 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
1866 convert_typed_floating (regval, regtype, readbuf, valtype);
1870 convert_typed_floating (writebuf, valtype, regval, regtype);
1871 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
1874 return RETURN_VALUE_REGISTER_CONVENTION;
1877 /* Values of the types int, long, short, pointer, and char (length
1878 is less than or equal to four bytes), as well as bit values of
1879 lengths less than or equal to 32 bits, must be returned right
1880 justified in GPR3 with signed values sign extended and unsigned
1881 values zero extended, as necessary. */
1882 if (TYPE_LENGTH (valtype) <= tdep->wordsize)
1888 /* For reading we don't have to worry about sign extension. */
1889 regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1891 store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval);
1895 /* For writing, use unpack_long since that should handle any
1896 required sign extension. */
1897 regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1898 unpack_long (valtype, writebuf));
1901 return RETURN_VALUE_REGISTER_CONVENTION;
1904 /* Eight-byte non-floating-point scalar values must be returned in
1907 if (TYPE_LENGTH (valtype) == 8)
1909 gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT);
1910 gdb_assert (tdep->wordsize == 4);
1916 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval);
1917 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
1919 memcpy (readbuf, regval, 8);
1923 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
1924 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
1928 return RETURN_VALUE_REGISTER_CONVENTION;
1931 return RETURN_VALUE_STRUCT_CONVENTION;
1934 /* Return whether handle_inferior_event() should proceed through code
1935 starting at PC in function NAME when stepping.
1937 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1938 handle memory references that are too distant to fit in instructions
1939 generated by the compiler. For example, if 'foo' in the following
1944 is greater than 32767, the linker might replace the lwz with a branch to
1945 somewhere in @FIX1 that does the load in 2 instructions and then branches
1946 back to where execution should continue.
1948 GDB should silently step over @FIX code, just like AIX dbx does.
1949 Unfortunately, the linker uses the "b" instruction for the
1950 branches, meaning that the link register doesn't get set.
1951 Therefore, GDB's usual step_over_function () mechanism won't work.
1953 Instead, use the gdbarch_skip_trampoline_code and
1954 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
1958 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1960 return name && !strncmp (name, "@FIX", 4);
1963 /* Skip code that the user doesn't want to see when stepping:
1965 1. Indirect function calls use a piece of trampoline code to do context
1966 switching, i.e. to set the new TOC table. Skip such code if we are on
1967 its first instruction (as when we have single-stepped to here).
1969 2. Skip shared library trampoline code (which is different from
1970 indirect function call trampolines).
1972 3. Skip bigtoc fixup code.
1974 Result is desired PC to step until, or NULL if we are not in
1975 code that should be skipped. */
1978 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
1980 unsigned int ii, op;
1982 CORE_ADDR solib_target_pc;
1983 struct minimal_symbol *msymbol;
1985 static unsigned trampoline_code[] =
1987 0x800b0000, /* l r0,0x0(r11) */
1988 0x90410014, /* st r2,0x14(r1) */
1989 0x7c0903a6, /* mtctr r0 */
1990 0x804b0004, /* l r2,0x4(r11) */
1991 0x816b0008, /* l r11,0x8(r11) */
1992 0x4e800420, /* bctr */
1993 0x4e800020, /* br */
1997 /* Check for bigtoc fixup code. */
1998 msymbol = lookup_minimal_symbol_by_pc (pc);
2000 && rs6000_in_solib_return_trampoline (pc,
2001 DEPRECATED_SYMBOL_NAME (msymbol)))
2003 /* Double-check that the third instruction from PC is relative "b". */
2004 op = read_memory_integer (pc + 8, 4);
2005 if ((op & 0xfc000003) == 0x48000000)
2007 /* Extract bits 6-29 as a signed 24-bit relative word address and
2008 add it to the containing PC. */
2009 rel = ((int)(op << 6) >> 6);
2010 return pc + 8 + rel;
2014 /* If pc is in a shared library trampoline, return its target. */
2015 solib_target_pc = find_solib_trampoline_target (frame, pc);
2016 if (solib_target_pc)
2017 return solib_target_pc;
2019 for (ii = 0; trampoline_code[ii]; ++ii)
2021 op = read_memory_integer (pc + (ii * 4), 4);
2022 if (op != trampoline_code[ii])
2025 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
2026 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
2030 /* ISA-specific vector types. */
2032 static struct type *
2033 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2035 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2037 if (!tdep->ppc_builtin_type_vec64)
2039 /* The type we're building is this: */
2041 union __gdb_builtin_type_vec64
2045 int32_t v2_int32[2];
2046 int16_t v4_int16[4];
2053 t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2054 append_composite_type_field (t, "uint64", builtin_type_int64);
2055 append_composite_type_field (t, "v2_float",
2056 init_vector_type (builtin_type_float, 2));
2057 append_composite_type_field (t, "v2_int32",
2058 init_vector_type (builtin_type_int32, 2));
2059 append_composite_type_field (t, "v4_int16",
2060 init_vector_type (builtin_type_int16, 4));
2061 append_composite_type_field (t, "v8_int8",
2062 init_vector_type (builtin_type_int8, 8));
2064 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR;
2065 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2066 tdep->ppc_builtin_type_vec64 = t;
2069 return tdep->ppc_builtin_type_vec64;
2072 static struct type *
2073 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2075 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2077 if (!tdep->ppc_builtin_type_vec128)
2079 /* The type we're building is this: */
2081 union __gdb_builtin_type_vec128
2085 int32_t v4_int32[4];
2086 int16_t v8_int16[8];
2087 int8_t v16_int8[16];
2093 t = init_composite_type ("__ppc_builtin_type_vec128", TYPE_CODE_UNION);
2094 append_composite_type_field (t, "uint128", builtin_type_int128);
2095 append_composite_type_field (t, "v4_float",
2096 init_vector_type (builtin_type_float, 4));
2097 append_composite_type_field (t, "v4_int32",
2098 init_vector_type (builtin_type_int32, 4));
2099 append_composite_type_field (t, "v8_int16",
2100 init_vector_type (builtin_type_int16, 8));
2101 append_composite_type_field (t, "v16_int8",
2102 init_vector_type (builtin_type_int8, 16));
2104 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR;
2105 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2106 tdep->ppc_builtin_type_vec128 = t;
2109 return tdep->ppc_builtin_type_vec128;
2112 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
2113 isn't available with that word size, return 0. */
2116 regsize (const struct reg *reg, int wordsize)
2118 return wordsize == 8 ? reg->sz64 : reg->sz32;
2121 /* Return the name of register number N, or null if no such register exists
2122 in the current architecture. */
2125 rs6000_register_name (int n)
2127 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2128 const struct reg *reg = tdep->regs + n;
2130 if (!regsize (reg, tdep->wordsize))
2135 /* Return the GDB type object for the "standard" data type
2136 of data in register N. */
2138 static struct type *
2139 rs6000_register_type (struct gdbarch *gdbarch, int n)
2141 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2142 const struct reg *reg = tdep->regs + n;
2145 return builtin_type_double;
2148 int size = regsize (reg, tdep->wordsize);
2152 return builtin_type_int0;
2154 return builtin_type_uint32;
2156 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
2157 return rs6000_builtin_type_vec64 (gdbarch);
2159 return builtin_type_uint64;
2162 return rs6000_builtin_type_vec128 (gdbarch);
2165 internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"),
2171 /* Is REGNUM a member of REGGROUP? */
2173 rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2174 struct reggroup *group)
2176 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2181 if (gdbarch_register_name (current_gdbarch, regnum) == NULL
2182 || *gdbarch_register_name (current_gdbarch, regnum) == '\0')
2184 if (group == all_reggroup)
2187 float_p = (regnum == tdep->ppc_fpscr_regnum
2188 || (regnum >= tdep->ppc_fp0_regnum
2189 && regnum < tdep->ppc_fp0_regnum + 32));
2190 if (group == float_reggroup)
2193 vector_p = ((tdep->ppc_vr0_regnum >= 0
2194 && regnum >= tdep->ppc_vr0_regnum
2195 && regnum < tdep->ppc_vr0_regnum + 32)
2196 || (tdep->ppc_ev0_regnum >= 0
2197 && regnum >= tdep->ppc_ev0_regnum
2198 && regnum < tdep->ppc_ev0_regnum + 32)
2199 || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */
2200 || regnum == tdep->ppc_vrsave_regnum
2201 || regnum == tdep->ppc_acc_regnum
2202 || regnum == tdep->ppc_spefscr_regnum);
2203 if (group == vector_reggroup)
2206 /* Note that PS aka MSR isn't included - it's a system register (and
2207 besides, due to GCC's CFI foobar you do not want to restore
2209 general_p = ((regnum >= tdep->ppc_gp0_regnum
2210 && regnum < tdep->ppc_gp0_regnum + 32)
2211 || regnum == tdep->ppc_toc_regnum
2212 || regnum == tdep->ppc_cr_regnum
2213 || regnum == tdep->ppc_lr_regnum
2214 || regnum == tdep->ppc_ctr_regnum
2215 || regnum == tdep->ppc_xer_regnum
2216 || regnum == gdbarch_pc_regnum (current_gdbarch));
2217 if (group == general_reggroup)
2220 if (group == save_reggroup || group == restore_reggroup)
2221 return general_p || vector_p || float_p;
2226 /* The register format for RS/6000 floating point registers is always
2227 double, we need a conversion if the memory format is float. */
2230 rs6000_convert_register_p (int regnum, struct type *type)
2232 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2235 && TYPE_CODE (type) == TYPE_CODE_FLT
2236 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2240 rs6000_register_to_value (struct frame_info *frame,
2245 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2246 gdb_byte from[MAX_REGISTER_SIZE];
2248 gdb_assert (reg->fpr);
2249 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2251 get_frame_register (frame, regnum, from);
2252 convert_typed_floating (from, builtin_type_double, to, type);
2256 rs6000_value_to_register (struct frame_info *frame,
2259 const gdb_byte *from)
2261 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2262 gdb_byte to[MAX_REGISTER_SIZE];
2264 gdb_assert (reg->fpr);
2265 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2267 convert_typed_floating (from, type, to, builtin_type_double);
2268 put_frame_register (frame, regnum, to);
2271 /* Move SPE vector register values between a 64-bit buffer and the two
2272 32-bit raw register halves in a regcache. This function handles
2273 both splitting a 64-bit value into two 32-bit halves, and joining
2274 two halves into a whole 64-bit value, depending on the function
2275 passed as the MOVE argument.
2277 EV_REG must be the number of an SPE evN vector register --- a
2278 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2281 Call MOVE once for each 32-bit half of that register, passing
2282 REGCACHE, the number of the raw register corresponding to that
2283 half, and the address of the appropriate half of BUFFER.
2285 For example, passing 'regcache_raw_read' as the MOVE function will
2286 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2287 'regcache_raw_supply' will supply the contents of BUFFER to the
2288 appropriate pair of raw registers in REGCACHE.
2290 You may need to cast away some 'const' qualifiers when passing
2291 MOVE, since this function can't tell at compile-time which of
2292 REGCACHE or BUFFER is acting as the source of the data. If C had
2293 co-variant type qualifiers, ... */
2295 e500_move_ev_register (void (*move) (struct regcache *regcache,
2296 int regnum, gdb_byte *buf),
2297 struct regcache *regcache, int ev_reg,
2300 struct gdbarch *arch = get_regcache_arch (regcache);
2301 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2303 gdb_byte *byte_buffer = buffer;
2305 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
2306 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
2308 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2310 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
2312 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2313 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2317 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2318 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2323 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2324 int reg_nr, gdb_byte *buffer)
2326 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2327 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2329 gdb_assert (regcache_arch == gdbarch);
2331 if (tdep->ppc_ev0_regnum <= reg_nr
2332 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2333 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2335 internal_error (__FILE__, __LINE__,
2336 _("e500_pseudo_register_read: "
2337 "called on unexpected register '%s' (%d)"),
2338 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2342 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2343 int reg_nr, const gdb_byte *buffer)
2345 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2346 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2348 gdb_assert (regcache_arch == gdbarch);
2350 if (tdep->ppc_ev0_regnum <= reg_nr
2351 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2352 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2354 regcache, reg_nr, (gdb_byte *) buffer);
2356 internal_error (__FILE__, __LINE__,
2357 _("e500_pseudo_register_read: "
2358 "called on unexpected register '%s' (%d)"),
2359 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2362 /* The E500 needs a custom reggroup function: it has anonymous raw
2363 registers, and default_register_reggroup_p assumes that anonymous
2364 registers are not members of any reggroup. */
2366 e500_register_reggroup_p (struct gdbarch *gdbarch,
2368 struct reggroup *group)
2370 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2372 /* The save and restore register groups need to include the
2373 upper-half registers, even though they're anonymous. */
2374 if ((group == save_reggroup
2375 || group == restore_reggroup)
2376 && (tdep->ppc_ev0_upper_regnum <= regnum
2377 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
2380 /* In all other regards, the default reggroup definition is fine. */
2381 return default_register_reggroup_p (gdbarch, regnum, group);
2384 /* Convert a DBX STABS register number to a GDB register number. */
2386 rs6000_stab_reg_to_regnum (int num)
2388 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2390 if (0 <= num && num <= 31)
2391 return tdep->ppc_gp0_regnum + num;
2392 else if (32 <= num && num <= 63)
2393 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2394 specifies registers the architecture doesn't have? Our
2395 callers don't check the value we return. */
2396 return tdep->ppc_fp0_regnum + (num - 32);
2397 else if (77 <= num && num <= 108)
2398 return tdep->ppc_vr0_regnum + (num - 77);
2399 else if (1200 <= num && num < 1200 + 32)
2400 return tdep->ppc_ev0_regnum + (num - 1200);
2405 return tdep->ppc_mq_regnum;
2407 return tdep->ppc_lr_regnum;
2409 return tdep->ppc_ctr_regnum;
2411 return tdep->ppc_xer_regnum;
2413 return tdep->ppc_vrsave_regnum;
2415 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2417 return tdep->ppc_acc_regnum;
2419 return tdep->ppc_spefscr_regnum;
2426 /* Convert a Dwarf 2 register number to a GDB register number. */
2428 rs6000_dwarf2_reg_to_regnum (int num)
2430 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2432 if (0 <= num && num <= 31)
2433 return tdep->ppc_gp0_regnum + num;
2434 else if (32 <= num && num <= 63)
2435 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2436 specifies registers the architecture doesn't have? Our
2437 callers don't check the value we return. */
2438 return tdep->ppc_fp0_regnum + (num - 32);
2439 else if (1124 <= num && num < 1124 + 32)
2440 return tdep->ppc_vr0_regnum + (num - 1124);
2441 else if (1200 <= num && num < 1200 + 32)
2442 return tdep->ppc_ev0_regnum + (num - 1200);
2447 return tdep->ppc_cr_regnum;
2449 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2451 return tdep->ppc_acc_regnum;
2453 return tdep->ppc_mq_regnum;
2455 return tdep->ppc_xer_regnum;
2457 return tdep->ppc_lr_regnum;
2459 return tdep->ppc_ctr_regnum;
2461 return tdep->ppc_vrsave_regnum;
2463 return tdep->ppc_spefscr_regnum;
2469 /* Translate a .eh_frame register to DWARF register, or adjust a
2470 .debug_frame register. */
2473 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2475 /* GCC releases before 3.4 use GCC internal register numbering in
2476 .debug_frame (and .debug_info, et cetera). The numbering is
2477 different from the standard SysV numbering for everything except
2478 for GPRs and FPRs. We can not detect this problem in most cases
2479 - to get accurate debug info for variables living in lr, ctr, v0,
2480 et cetera, use a newer version of GCC. But we must detect
2481 one important case - lr is in column 65 in .debug_frame output,
2484 GCC 3.4, and the "hammer" branch, have a related problem. They
2485 record lr register saves in .debug_frame as 108, but still record
2486 the return column as 65. We fix that up too.
2488 We can do this because 65 is assigned to fpsr, and GCC never
2489 generates debug info referring to it. To add support for
2490 handwritten debug info that restores fpsr, we would need to add a
2491 producer version check to this. */
2500 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2501 internal register numbering; translate that to the standard DWARF2
2502 register numbering. */
2503 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2505 else if (68 <= num && num <= 75) /* cr0-cr8 */
2506 return num - 68 + 86;
2507 else if (77 <= num && num <= 108) /* vr0-vr31 */
2508 return num - 77 + 1124;
2520 case 109: /* vrsave */
2522 case 110: /* vscr */
2524 case 111: /* spe_acc */
2526 case 112: /* spefscr */
2533 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2535 Usually a function pointer's representation is simply the address
2536 of the function. On the RS/6000 however, a function pointer is
2537 represented by a pointer to an OPD entry. This OPD entry contains
2538 three words, the first word is the address of the function, the
2539 second word is the TOC pointer (r2), and the third word is the
2540 static chain value. Throughout GDB it is currently assumed that a
2541 function pointer contains the address of the function, which is not
2542 easy to fix. In addition, the conversion of a function address to
2543 a function pointer would require allocation of an OPD entry in the
2544 inferior's memory space, with all its drawbacks. To be able to
2545 call C++ virtual methods in the inferior (which are called via
2546 function pointers), find_function_addr uses this function to get the
2547 function address from a function pointer. */
2549 /* Return real function address if ADDR (a function pointer) is in the data
2550 space and is therefore a special function pointer. */
2553 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2555 struct target_ops *targ)
2557 struct obj_section *s;
2559 s = find_pc_section (addr);
2560 if (s && s->the_bfd_section->flags & SEC_CODE)
2563 /* ADDR is in the data space, so it's a special function pointer. */
2564 return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize);
2568 /* Handling the various POWER/PowerPC variants. */
2571 /* The arrays here called registers_MUMBLE hold information about available
2574 For each family of PPC variants, I've tried to isolate out the
2575 common registers and put them up front, so that as long as you get
2576 the general family right, GDB will correctly identify the registers
2577 common to that family. The common register sets are:
2579 For the 60x family: hid0 hid1 iabr dabr pir
2581 For the 505 and 860 family: eie eid nri
2583 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2584 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2587 Most of these register groups aren't anything formal. I arrived at
2588 them by looking at the registers that occurred in more than one
2591 Note: kevinb/2002-04-30: Support for the fpscr register was added
2592 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2593 for Power. For PowerPC, slot 70 was unused and was already in the
2594 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2595 slot 70 was being used for "mq", so the next available slot (71)
2596 was chosen. It would have been nice to be able to make the
2597 register numbers the same across processor cores, but this wasn't
2598 possible without either 1) renumbering some registers for some
2599 processors or 2) assigning fpscr to a really high slot that's
2600 larger than any current register number. Doing (1) is bad because
2601 existing stubs would break. Doing (2) is undesirable because it
2602 would introduce a really large gap between fpscr and the rest of
2603 the registers for most processors. */
2605 /* Convenience macros for populating register arrays. */
2607 /* Within another macro, convert S to a string. */
2611 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2612 and 64 bits on 64-bit systems. */
2613 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2615 /* Return a struct reg defining register NAME that's 32 bits on all
2617 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2619 /* Return a struct reg defining register NAME that's 64 bits on all
2621 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2623 /* Return a struct reg defining register NAME that's 128 bits on all
2625 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2627 /* Return a struct reg defining floating-point register NAME. */
2628 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2630 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2631 long on all systems. */
2632 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2634 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2635 systems and that doesn't exist on 64-bit systems. */
2636 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2638 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2639 systems and that doesn't exist on 32-bit systems. */
2640 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2642 /* Return a struct reg placeholder for a register that doesn't exist. */
2643 #define R0 { 0, 0, 0, 0, 0, -1 }
2645 /* Return a struct reg defining an anonymous raw register that's 32
2646 bits on all systems. */
2647 #define A4 { 0, 4, 4, 0, 0, -1 }
2649 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2650 32-bit systems and 64 bits on 64-bit systems. */
2651 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2653 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2655 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2657 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2658 all systems, and whose SPR number is NUMBER. */
2659 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2661 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2662 64-bit systems and that doesn't exist on 32-bit systems. */
2663 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2665 /* UISA registers common across all architectures, including POWER. */
2667 #define COMMON_UISA_REGS \
2668 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2669 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2670 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2671 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2672 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2673 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2674 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2675 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2676 /* 64 */ R(pc), R(ps)
2678 /* UISA-level SPRs for PowerPC. */
2679 #define PPC_UISA_SPRS \
2680 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2682 /* UISA-level SPRs for PowerPC without floating point support. */
2683 #define PPC_UISA_NOFP_SPRS \
2684 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2686 /* Segment registers, for PowerPC. */
2687 #define PPC_SEGMENT_REGS \
2688 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2689 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2690 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2691 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2693 /* OEA SPRs for PowerPC. */
2694 #define PPC_OEA_SPRS \
2696 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2697 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2698 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2699 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2700 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2701 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2702 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2703 /* 116 */ S4(dec), S(dabr), S4(ear)
2705 /* AltiVec registers. */
2706 #define PPC_ALTIVEC_REGS \
2707 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2708 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2709 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2710 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2711 /*151*/R4(vscr), R4(vrsave)
2714 /* On machines supporting the SPE APU, the general-purpose registers
2715 are 64 bits long. There are SIMD vector instructions to treat them
2716 as pairs of floats, but the rest of the instruction set treats them
2717 as 32-bit registers, and only operates on their lower halves.
2719 In the GDB regcache, we treat their high and low halves as separate
2720 registers. The low halves we present as the general-purpose
2721 registers, and then we have pseudo-registers that stitch together
2722 the upper and lower halves and present them as pseudo-registers. */
2724 /* SPE GPR lower halves --- raw registers. */
2725 #define PPC_SPE_GP_REGS \
2726 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2727 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2728 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2729 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2731 /* SPE GPR upper halves --- anonymous raw registers. */
2732 #define PPC_SPE_UPPER_GP_REGS \
2733 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2734 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2735 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2736 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2738 /* SPE GPR vector registers --- pseudo registers based on underlying
2739 gprs and the anonymous upper half raw registers. */
2740 #define PPC_EV_PSEUDO_REGS \
2741 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2742 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2743 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2744 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2746 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2747 user-level SPR's. */
2748 static const struct reg registers_power[] =
2751 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
2755 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2756 view of the PowerPC. */
2757 static const struct reg registers_powerpc[] =
2766 Some notes about the "tcr" special-purpose register:
2767 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2768 403's programmable interval timer, fixed interval timer, and
2770 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2771 watchdog timer, and nothing else.
2773 Some of the fields are similar between the two, but they're not
2774 compatible with each other. Since the two variants have different
2775 registers, with different numbers, but the same name, we can't
2776 splice the register name to get the SPR number. */
2777 static const struct reg registers_403[] =
2783 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2784 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2785 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2786 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2787 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2788 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
2791 /* IBM PowerPC 403GC.
2792 See the comments about 'tcr' for the 403, above. */
2793 static const struct reg registers_403GC[] =
2799 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2800 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2801 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2802 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2803 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2804 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
2805 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
2806 /* 147 */ S(tbhu), S(tblu)
2809 /* Motorola PowerPC 505. */
2810 static const struct reg registers_505[] =
2816 /* 119 */ S(eie), S(eid), S(nri)
2819 /* Motorola PowerPC 860 or 850. */
2820 static const struct reg registers_860[] =
2826 /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
2827 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
2828 /* 127 */ S(der), S(counta), S(countb), S(cmpe),
2829 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
2830 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
2831 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
2832 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
2833 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
2834 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
2835 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
2836 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
2837 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
2840 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2841 for reading and writing RTCU and RTCL. However, how one reads and writes a
2842 register is the stub's problem. */
2843 static const struct reg registers_601[] =
2849 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2850 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
2853 /* Motorola PowerPC 602.
2854 See the notes under the 403 about 'tcr'. */
2855 static const struct reg registers_602[] =
2861 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2862 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
2863 /* 127 */ S(sebr), S(ser), S(sp), S(lt)
2866 /* Motorola/IBM PowerPC 603 or 603e. */
2867 static const struct reg registers_603[] =
2873 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2874 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
2875 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
2878 /* Motorola PowerPC 604 or 604e. */
2879 static const struct reg registers_604[] =
2885 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2886 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
2887 /* 127 */ S(sia), S(sda)
2890 /* Motorola/IBM PowerPC 750 or 740. */
2891 static const struct reg registers_750[] =
2897 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2898 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
2899 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
2900 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
2901 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
2902 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
2906 /* Motorola PowerPC 7400. */
2907 static const struct reg registers_7400[] =
2909 /* gpr0-gpr31, fpr0-fpr31 */
2911 /* cr, lr, ctr, xer, fpscr */
2916 /* vr0-vr31, vrsave, vscr */
2918 /* FIXME? Add more registers? */
2921 /* Motorola e500. */
2922 static const struct reg registers_e500[] =
2924 /* 0 .. 31 */ PPC_SPE_GP_REGS,
2925 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
2926 /* 64 .. 65 */ R(pc), R(ps),
2927 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
2928 /* 71 .. 72 */ R8(acc), S4(spefscr),
2929 /* NOTE: Add new registers here the end of the raw register
2930 list and just before the first pseudo register. */
2931 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2934 /* Information about a particular processor variant. */
2938 /* Name of this variant. */
2941 /* English description of the variant. */
2944 /* bfd_arch_info.arch corresponding to variant. */
2945 enum bfd_architecture arch;
2947 /* bfd_arch_info.mach corresponding to variant. */
2950 /* Number of real registers. */
2953 /* Number of pseudo registers. */
2956 /* Number of total registers (the sum of nregs and npregs). */
2959 /* Table of register names; registers[R] is the name of the register
2961 const struct reg *regs;
2964 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2967 num_registers (const struct reg *reg_list, int num_tot_regs)
2972 for (i = 0; i < num_tot_regs; i++)
2973 if (!reg_list[i].pseudo)
2980 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2985 for (i = 0; i < num_tot_regs; i++)
2986 if (reg_list[i].pseudo)
2992 /* Information in this table comes from the following web sites:
2993 IBM: http://www.chips.ibm.com:80/products/embedded/
2994 Motorola: http://www.mot.com/SPS/PowerPC/
2996 I'm sure I've got some of the variant descriptions not quite right.
2997 Please report any inaccuracies you find to GDB's maintainer.
2999 If you add entries to this table, please be sure to allow the new
3000 value as an argument to the --with-cpu flag, in configure.in. */
3002 static struct variant variants[] =
3005 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
3006 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
3008 {"power", "POWER user-level", bfd_arch_rs6000,
3009 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
3011 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
3012 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
3014 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
3015 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
3017 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
3018 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
3020 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
3021 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
3023 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
3024 604, -1, -1, tot_num_registers (registers_604),
3026 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
3027 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
3029 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
3030 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
3032 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
3033 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
3035 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
3036 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
3038 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
3039 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
3041 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
3042 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
3046 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
3047 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
3049 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
3050 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
3052 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
3053 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
3055 {"a35", "PowerPC A35", bfd_arch_powerpc,
3056 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
3058 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
3059 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
3061 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
3062 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
3065 /* FIXME: I haven't checked the register sets of the following. */
3066 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
3067 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
3069 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
3070 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
3072 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
3073 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
3076 {0, 0, 0, 0, 0, 0, 0, 0}
3079 /* Initialize the number of registers and pseudo registers in each variant. */
3082 init_variants (void)
3086 for (v = variants; v->name; v++)
3089 v->nregs = num_registers (v->regs, v->num_tot_regs);
3090 if (v->npregs == -1)
3091 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
3095 /* Return the variant corresponding to architecture ARCH and machine number
3096 MACH. If no such variant exists, return null. */
3098 static const struct variant *
3099 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
3101 const struct variant *v;
3103 for (v = variants; v->name; v++)
3104 if (arch == v->arch && mach == v->mach)
3111 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3113 if (!info->disassembler_options)
3114 info->disassembler_options = "any";
3116 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
3117 return print_insn_big_powerpc (memaddr, info);
3119 return print_insn_little_powerpc (memaddr, info);
3123 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3125 return frame_unwind_register_unsigned (next_frame,
3126 gdbarch_pc_regnum (current_gdbarch));
3129 static struct frame_id
3130 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
3132 return frame_id_build (frame_unwind_register_unsigned
3133 (next_frame, gdbarch_sp_regnum (current_gdbarch)),
3134 frame_pc_unwind (next_frame));
3137 struct rs6000_frame_cache
3140 CORE_ADDR initial_sp;
3141 struct trad_frame_saved_reg *saved_regs;
3144 static struct rs6000_frame_cache *
3145 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
3147 struct rs6000_frame_cache *cache;
3148 struct gdbarch *gdbarch = get_frame_arch (next_frame);
3149 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3150 struct rs6000_framedata fdata;
3151 int wordsize = tdep->wordsize;
3154 if ((*this_cache) != NULL)
3155 return (*this_cache);
3156 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3157 (*this_cache) = cache;
3158 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
3160 func = frame_func_unwind (next_frame, NORMAL_FRAME);
3161 pc = frame_pc_unwind (next_frame);
3162 skip_prologue (func, pc, &fdata);
3164 /* Figure out the parent's stack pointer. */
3166 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3167 address of the current frame. Things might be easier if the
3168 ->frame pointed to the outer-most address of the frame. In
3169 the mean time, the address of the prev frame is used as the
3170 base address of this frame. */
3171 cache->base = frame_unwind_register_unsigned
3172 (next_frame, gdbarch_sp_regnum (current_gdbarch));
3174 /* If the function appears to be frameless, check a couple of likely
3175 indicators that we have simply failed to find the frame setup.
3176 Two common cases of this are missing symbols (i.e.
3177 frame_func_unwind returns the wrong address or 0), and assembly
3178 stubs which have a fast exit path but set up a frame on the slow
3181 If the LR appears to return to this function, then presume that
3182 we have an ABI compliant frame that we failed to find. */
3183 if (fdata.frameless && fdata.lr_offset == 0)
3188 saved_lr = frame_unwind_register_unsigned (next_frame,
3189 tdep->ppc_lr_regnum);
3190 if (func == 0 && saved_lr == pc)
3194 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3195 if (func == saved_func)
3201 fdata.frameless = 0;
3202 fdata.lr_offset = tdep->lr_frame_offset;
3206 if (!fdata.frameless)
3207 /* Frameless really means stackless. */
3208 cache->base = read_memory_addr (cache->base, wordsize);
3210 trad_frame_set_value (cache->saved_regs,
3211 gdbarch_sp_regnum (current_gdbarch), cache->base);
3213 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3214 All fpr's from saved_fpr to fp31 are saved. */
3216 if (fdata.saved_fpr >= 0)
3219 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3221 /* If skip_prologue says floating-point registers were saved,
3222 but the current architecture has no floating-point registers,
3223 then that's strange. But we have no indices to even record
3224 the addresses under, so we just ignore it. */
3225 if (ppc_floating_point_unit_p (gdbarch))
3226 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3228 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3233 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3234 All gpr's from saved_gpr to gpr31 are saved. */
3236 if (fdata.saved_gpr >= 0)
3239 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3240 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3242 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3243 gpr_addr += wordsize;
3247 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3248 All vr's from saved_vr to vr31 are saved. */
3249 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3251 if (fdata.saved_vr >= 0)
3254 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3255 for (i = fdata.saved_vr; i < 32; i++)
3257 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3258 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3263 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3264 All vr's from saved_ev to ev31 are saved. ????? */
3265 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
3267 if (fdata.saved_ev >= 0)
3270 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3271 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3273 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3274 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3275 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3280 /* If != 0, fdata.cr_offset is the offset from the frame that
3282 if (fdata.cr_offset != 0)
3283 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3285 /* If != 0, fdata.lr_offset is the offset from the frame that
3287 if (fdata.lr_offset != 0)
3288 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
3289 /* The PC is found in the link register. */
3290 cache->saved_regs[gdbarch_pc_regnum (current_gdbarch)] =
3291 cache->saved_regs[tdep->ppc_lr_regnum];
3293 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3294 holds the VRSAVE. */
3295 if (fdata.vrsave_offset != 0)
3296 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3298 if (fdata.alloca_reg < 0)
3299 /* If no alloca register used, then fi->frame is the value of the
3300 %sp for this frame, and it is good enough. */
3301 cache->initial_sp = frame_unwind_register_unsigned
3302 (next_frame, gdbarch_sp_regnum (current_gdbarch));
3304 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3311 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3312 struct frame_id *this_id)
3314 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3316 (*this_id) = frame_id_build (info->base,
3317 frame_func_unwind (next_frame, NORMAL_FRAME));
3321 rs6000_frame_prev_register (struct frame_info *next_frame,
3323 int regnum, int *optimizedp,
3324 enum lval_type *lvalp, CORE_ADDR *addrp,
3325 int *realnump, gdb_byte *valuep)
3327 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3329 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3330 optimizedp, lvalp, addrp, realnump, valuep);
3333 static const struct frame_unwind rs6000_frame_unwind =
3336 rs6000_frame_this_id,
3337 rs6000_frame_prev_register
3340 static const struct frame_unwind *
3341 rs6000_frame_sniffer (struct frame_info *next_frame)
3343 return &rs6000_frame_unwind;
3349 rs6000_frame_base_address (struct frame_info *next_frame,
3352 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3354 return info->initial_sp;
3357 static const struct frame_base rs6000_frame_base = {
3358 &rs6000_frame_unwind,
3359 rs6000_frame_base_address,
3360 rs6000_frame_base_address,
3361 rs6000_frame_base_address
3364 static const struct frame_base *
3365 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3367 return &rs6000_frame_base;
3370 /* Initialize the current architecture based on INFO. If possible, re-use an
3371 architecture from ARCHES, which is a list of architectures already created
3372 during this debugging session.
3374 Called e.g. at program startup, when reading a core file, and when reading
3377 static struct gdbarch *
3378 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3380 struct gdbarch *gdbarch;
3381 struct gdbarch_tdep *tdep;
3382 int wordsize, from_xcoff_exec, from_elf_exec, i, off;
3384 const struct variant *v;
3385 enum bfd_architecture arch;
3391 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3392 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3394 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3395 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3397 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3399 /* Check word size. If INFO is from a binary file, infer it from
3400 that, else choose a likely default. */
3401 if (from_xcoff_exec)
3403 if (bfd_xcoff_is_xcoff64 (info.abfd))
3408 else if (from_elf_exec)
3410 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3417 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3418 wordsize = info.bfd_arch_info->bits_per_word /
3419 info.bfd_arch_info->bits_per_byte;
3424 /* Find a candidate among extant architectures. */
3425 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3427 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3429 /* Word size in the various PowerPC bfd_arch_info structs isn't
3430 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3431 separate word size check. */
3432 tdep = gdbarch_tdep (arches->gdbarch);
3433 if (tdep && tdep->wordsize == wordsize)
3434 return arches->gdbarch;
3437 /* None found, create a new architecture from INFO, whose bfd_arch_info
3438 validity depends on the source:
3439 - executable useless
3440 - rs6000_host_arch() good
3442 - "set arch" trust blindly
3443 - GDB startup useless but harmless */
3445 if (!from_xcoff_exec)
3447 arch = info.bfd_arch_info->arch;
3448 mach = info.bfd_arch_info->mach;
3452 arch = bfd_arch_powerpc;
3453 bfd_default_set_arch_mach (&abfd, arch, 0);
3454 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3455 mach = info.bfd_arch_info->mach;
3457 tdep = XCALLOC (1, struct gdbarch_tdep);
3458 tdep->wordsize = wordsize;
3460 /* For e500 executables, the apuinfo section is of help here. Such
3461 section contains the identifier and revision number of each
3462 Application-specific Processing Unit that is present on the
3463 chip. The content of the section is determined by the assembler
3464 which looks at each instruction and determines which unit (and
3465 which version of it) can execute it. In our case we just look for
3466 the existance of the section. */
3470 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3473 arch = info.bfd_arch_info->arch;
3474 mach = bfd_mach_ppc_e500;
3475 bfd_default_set_arch_mach (&abfd, arch, mach);
3476 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3480 gdbarch = gdbarch_alloc (&info, tdep);
3482 /* Initialize the number of real and pseudo registers in each variant. */
3485 /* Choose variant. */
3486 v = find_variant_by_arch (arch, mach);
3490 tdep->regs = v->regs;
3492 tdep->ppc_gp0_regnum = 0;
3493 tdep->ppc_toc_regnum = 2;
3494 tdep->ppc_ps_regnum = 65;
3495 tdep->ppc_cr_regnum = 66;
3496 tdep->ppc_lr_regnum = 67;
3497 tdep->ppc_ctr_regnum = 68;
3498 tdep->ppc_xer_regnum = 69;
3499 if (v->mach == bfd_mach_ppc_601)
3500 tdep->ppc_mq_regnum = 124;
3501 else if (arch == bfd_arch_rs6000)
3502 tdep->ppc_mq_regnum = 70;
3504 tdep->ppc_mq_regnum = -1;
3505 tdep->ppc_fp0_regnum = 32;
3506 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
3507 tdep->ppc_sr0_regnum = 71;
3508 tdep->ppc_vr0_regnum = -1;
3509 tdep->ppc_vrsave_regnum = -1;
3510 tdep->ppc_ev0_upper_regnum = -1;
3511 tdep->ppc_ev0_regnum = -1;
3512 tdep->ppc_ev31_regnum = -1;
3513 tdep->ppc_acc_regnum = -1;
3514 tdep->ppc_spefscr_regnum = -1;
3516 set_gdbarch_pc_regnum (gdbarch, 64);
3517 set_gdbarch_sp_regnum (gdbarch, 1);
3518 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
3519 set_gdbarch_fp0_regnum (gdbarch, 32);
3520 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3521 if (sysv_abi && wordsize == 8)
3522 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3523 else if (sysv_abi && wordsize == 4)
3524 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3526 set_gdbarch_return_value (gdbarch, rs6000_return_value);
3528 /* Set lr_frame_offset. */
3530 tdep->lr_frame_offset = 16;
3532 tdep->lr_frame_offset = 4;
3534 tdep->lr_frame_offset = 8;
3536 if (v->arch == bfd_arch_rs6000)
3537 tdep->ppc_sr0_regnum = -1;
3538 else if (v->arch == bfd_arch_powerpc)
3542 tdep->ppc_sr0_regnum = -1;
3543 tdep->ppc_vr0_regnum = 71;
3544 tdep->ppc_vrsave_regnum = 104;
3546 case bfd_mach_ppc_7400:
3547 tdep->ppc_vr0_regnum = 119;
3548 tdep->ppc_vrsave_regnum = 152;
3550 case bfd_mach_ppc_e500:
3551 tdep->ppc_toc_regnum = -1;
3552 tdep->ppc_ev0_upper_regnum = 32;
3553 tdep->ppc_ev0_regnum = 73;
3554 tdep->ppc_ev31_regnum = 104;
3555 tdep->ppc_acc_regnum = 71;
3556 tdep->ppc_spefscr_regnum = 72;
3557 tdep->ppc_fp0_regnum = -1;
3558 tdep->ppc_fpscr_regnum = -1;
3559 tdep->ppc_sr0_regnum = -1;
3560 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3561 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3562 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
3565 case bfd_mach_ppc64:
3566 case bfd_mach_ppc_620:
3567 case bfd_mach_ppc_630:
3568 case bfd_mach_ppc_a35:
3569 case bfd_mach_ppc_rs64ii:
3570 case bfd_mach_ppc_rs64iii:
3571 /* These processor's register sets don't have segment registers. */
3572 tdep->ppc_sr0_regnum = -1;
3576 internal_error (__FILE__, __LINE__,
3577 _("rs6000_gdbarch_init: "
3578 "received unexpected BFD 'arch' value"));
3580 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3582 /* Sanity check on registers. */
3583 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
3585 /* Select instruction printer. */
3586 if (arch == bfd_arch_rs6000)
3587 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3589 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3591 set_gdbarch_num_regs (gdbarch, v->nregs);
3592 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
3593 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3594 set_gdbarch_register_type (gdbarch, rs6000_register_type);
3595 set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p);
3597 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3598 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3599 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3600 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3601 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3602 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3603 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3605 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3607 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3608 set_gdbarch_char_signed (gdbarch, 0);
3610 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3611 if (sysv_abi && wordsize == 8)
3613 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3614 else if (!sysv_abi && wordsize == 4)
3615 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3616 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3617 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3619 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3621 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3622 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3623 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3625 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3626 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3628 if (sysv_abi && wordsize == 4)
3629 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3630 else if (sysv_abi && wordsize == 8)
3631 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3633 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3635 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3636 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3638 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3639 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3641 /* Handles single stepping of atomic sequences. */
3642 set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence);
3644 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3645 for the descriptor and ".FN" for the entry-point -- a user
3646 specifying "break FN" will unexpectedly end up with a breakpoint
3647 on the descriptor and not the function. This architecture method
3648 transforms any breakpoints on descriptors into breakpoints on the
3649 corresponding entry point. */
3650 if (sysv_abi && wordsize == 8)
3651 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3653 /* Not sure on this. FIXMEmgo */
3654 set_gdbarch_frame_args_skip (gdbarch, 8);
3658 /* Handle RS/6000 function pointers (which are really function
3660 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3661 rs6000_convert_from_func_ptr_addr);
3664 /* Helpers for function argument information. */
3665 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3668 set_gdbarch_in_solib_return_trampoline
3669 (gdbarch, rs6000_in_solib_return_trampoline);
3670 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3672 /* Hook in the DWARF CFI frame unwinder. */
3673 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3674 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3676 /* Hook in ABI-specific overrides, if they have been registered. */
3677 gdbarch_init_osabi (info, gdbarch);
3681 case GDB_OSABI_LINUX:
3682 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3683 have altivec registers. If not, ptrace will fail the first time it's
3684 called to access one and will not be called again. This wart will
3685 be removed when Daniel Jacobowitz's proposal for autodetecting target
3686 registers is implemented. */
3687 if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64))
3689 tdep->ppc_vr0_regnum = 71;
3690 tdep->ppc_vrsave_regnum = 104;
3693 case GDB_OSABI_NETBSD_AOUT:
3694 case GDB_OSABI_NETBSD_ELF:
3695 case GDB_OSABI_UNKNOWN:
3696 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3697 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3698 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3699 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3702 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3704 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3705 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3706 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3707 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3710 init_sim_regno_table (gdbarch);
3716 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3718 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3723 /* FIXME: Dump gdbarch_tdep. */
3726 /* Initialization code. */
3728 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3731 _initialize_rs6000_tdep (void)
3733 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3734 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);