1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
52 #include "solib-svr4.h"
55 #include "gdb_assert.h"
58 #include "trad-frame.h"
59 #include "frame-unwind.h"
60 #include "frame-base.h"
62 #include "rs6000-tdep.h"
64 /* If the kernel has to deliver a signal, it pushes a sigcontext
65 structure on the stack and then calls the signal handler, passing
66 the address of the sigcontext in an argument register. Usually
67 the signal handler doesn't save this register, so we have to
68 access the sigcontext structure via an offset from the signal handler
70 The following constants were determined by experimentation on AIX 3.2. */
71 #define SIG_FRAME_PC_OFFSET 96
72 #define SIG_FRAME_LR_OFFSET 108
73 #define SIG_FRAME_FP_OFFSET 284
75 /* To be used by skip_prologue. */
77 struct rs6000_framedata
79 int offset; /* total size of frame --- the distance
80 by which we decrement sp to allocate
82 int saved_gpr; /* smallest # of saved gpr */
83 int saved_fpr; /* smallest # of saved fpr */
84 int saved_vr; /* smallest # of saved vr */
85 int saved_ev; /* smallest # of saved ev */
86 int alloca_reg; /* alloca register number (frame ptr) */
87 char frameless; /* true if frameless functions. */
88 char nosavedpc; /* true if pc not saved. */
89 int gpr_offset; /* offset of saved gprs from prev sp */
90 int fpr_offset; /* offset of saved fprs from prev sp */
91 int vr_offset; /* offset of saved vrs from prev sp */
92 int ev_offset; /* offset of saved evs from prev sp */
93 int lr_offset; /* offset of saved lr */
94 int cr_offset; /* offset of saved cr */
95 int vrsave_offset; /* offset of saved vrsave register */
98 /* Description of a single register. */
102 char *name; /* name of register */
103 unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */
104 unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */
105 unsigned char fpr; /* whether register is floating-point */
106 unsigned char pseudo; /* whether register is pseudo */
107 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
108 This is an ISA SPR number, not a GDB
112 /* Hook for determining the TOC address when calling functions in the
113 inferior under AIX. The initialization code in rs6000-nat.c sets
114 this hook to point to find_toc_address. */
116 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
118 /* Hook to set the current architecture when starting a child process.
119 rs6000-nat.c sets this. */
121 void (*rs6000_set_host_arch_hook) (int) = NULL;
123 /* Static function prototypes */
125 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
127 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
128 struct rs6000_framedata *);
130 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
132 altivec_register_p (int regno)
134 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
135 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
138 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
142 /* Return true if REGNO is an SPE register, false otherwise. */
144 spe_register_p (int regno)
146 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
148 /* Is it a reference to EV0 -- EV31, and do we have those? */
149 if (tdep->ppc_ev0_regnum >= 0
150 && tdep->ppc_ev31_regnum >= 0
151 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
154 /* Is it a reference to one of the raw upper GPR halves? */
155 if (tdep->ppc_ev0_upper_regnum >= 0
156 && tdep->ppc_ev0_upper_regnum <= regno
157 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
160 /* Is it a reference to the 64-bit accumulator, and do we have that? */
161 if (tdep->ppc_acc_regnum >= 0
162 && tdep->ppc_acc_regnum == regno)
165 /* Is it a reference to the SPE floating-point status and control register,
166 and do we have that? */
167 if (tdep->ppc_spefscr_regnum >= 0
168 && tdep->ppc_spefscr_regnum == regno)
175 /* Return non-zero if the architecture described by GDBARCH has
176 floating-point registers (f0 --- f31 and fpscr). */
178 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
180 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
182 return (tdep->ppc_fp0_regnum >= 0
183 && tdep->ppc_fpscr_regnum >= 0);
187 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
190 This is a helper function for init_sim_regno_table, constructing
191 the table mapping GDB register numbers to sim register numbers; we
192 initialize every element in that table to -1 before we start
195 set_sim_regno (int *table, int gdb_regno, int sim_regno)
197 /* Make sure we don't try to assign any given GDB register a sim
198 register number more than once. */
199 gdb_assert (table[gdb_regno] == -1);
200 table[gdb_regno] = sim_regno;
204 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
205 numbers to simulator register numbers, based on the values placed
206 in the ARCH->tdep->ppc_foo_regnum members. */
208 init_sim_regno_table (struct gdbarch *arch)
210 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
211 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
212 const struct reg *regs = tdep->regs;
213 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
216 /* Presume that all registers not explicitly mentioned below are
217 unavailable from the sim. */
218 for (i = 0; i < total_regs; i++)
221 /* General-purpose registers. */
222 for (i = 0; i < ppc_num_gprs; i++)
223 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
225 /* Floating-point registers. */
226 if (tdep->ppc_fp0_regnum >= 0)
227 for (i = 0; i < ppc_num_fprs; i++)
228 set_sim_regno (sim_regno,
229 tdep->ppc_fp0_regnum + i,
230 sim_ppc_f0_regnum + i);
231 if (tdep->ppc_fpscr_regnum >= 0)
232 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
234 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
235 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
236 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
238 /* Segment registers. */
239 if (tdep->ppc_sr0_regnum >= 0)
240 for (i = 0; i < ppc_num_srs; i++)
241 set_sim_regno (sim_regno,
242 tdep->ppc_sr0_regnum + i,
243 sim_ppc_sr0_regnum + i);
245 /* Altivec registers. */
246 if (tdep->ppc_vr0_regnum >= 0)
248 for (i = 0; i < ppc_num_vrs; i++)
249 set_sim_regno (sim_regno,
250 tdep->ppc_vr0_regnum + i,
251 sim_ppc_vr0_regnum + i);
253 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
254 we can treat this more like the other cases. */
255 set_sim_regno (sim_regno,
256 tdep->ppc_vr0_regnum + ppc_num_vrs,
257 sim_ppc_vscr_regnum);
259 /* vsave is a special-purpose register, so the code below handles it. */
261 /* SPE APU (E500) registers. */
262 if (tdep->ppc_ev0_regnum >= 0)
263 for (i = 0; i < ppc_num_gprs; i++)
264 set_sim_regno (sim_regno,
265 tdep->ppc_ev0_regnum + i,
266 sim_ppc_ev0_regnum + i);
267 if (tdep->ppc_ev0_upper_regnum >= 0)
268 for (i = 0; i < ppc_num_gprs; i++)
269 set_sim_regno (sim_regno,
270 tdep->ppc_ev0_upper_regnum + i,
271 sim_ppc_rh0_regnum + i);
272 if (tdep->ppc_acc_regnum >= 0)
273 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
274 /* spefscr is a special-purpose register, so the code below handles it. */
276 /* Now handle all special-purpose registers. Verify that they
277 haven't mistakenly been assigned numbers by any of the above
279 for (i = 0; i < total_regs; i++)
280 if (regs[i].spr_num >= 0)
281 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
283 /* Drop the initialized array into place. */
284 tdep->sim_regno = sim_regno;
288 /* Given a GDB register number REG, return the corresponding SIM
291 rs6000_register_sim_regno (int reg)
293 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
296 gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
297 sim_regno = tdep->sim_regno[reg];
302 return LEGACY_SIM_REGNO_IGNORE;
307 /* Register set support functions. */
310 ppc_supply_reg (struct regcache *regcache, int regnum,
311 const gdb_byte *regs, size_t offset)
313 if (regnum != -1 && offset != -1)
314 regcache_raw_supply (regcache, regnum, regs + offset);
318 ppc_collect_reg (const struct regcache *regcache, int regnum,
319 gdb_byte *regs, size_t offset)
321 if (regnum != -1 && offset != -1)
322 regcache_raw_collect (regcache, regnum, regs + offset);
325 /* Supply register REGNUM in the general-purpose register set REGSET
326 from the buffer specified by GREGS and LEN to register cache
327 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
330 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
331 int regnum, const void *gregs, size_t len)
333 struct gdbarch *gdbarch = get_regcache_arch (regcache);
334 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
335 const struct ppc_reg_offsets *offsets = regset->descr;
339 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
340 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
343 if (regnum == -1 || regnum == i)
344 ppc_supply_reg (regcache, i, gregs, offset);
347 if (regnum == -1 || regnum == PC_REGNUM)
348 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
349 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
350 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
351 gregs, offsets->ps_offset);
352 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
353 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
354 gregs, offsets->cr_offset);
355 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
356 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
357 gregs, offsets->lr_offset);
358 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
359 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
360 gregs, offsets->ctr_offset);
361 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
362 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
363 gregs, offsets->cr_offset);
364 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
365 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
368 /* Supply register REGNUM in the floating-point register set REGSET
369 from the buffer specified by FPREGS and LEN to register cache
370 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
373 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
374 int regnum, const void *fpregs, size_t len)
376 struct gdbarch *gdbarch = get_regcache_arch (regcache);
377 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
378 const struct ppc_reg_offsets *offsets = regset->descr;
382 gdb_assert (ppc_floating_point_unit_p (gdbarch));
384 offset = offsets->f0_offset;
385 for (i = tdep->ppc_fp0_regnum;
386 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
389 if (regnum == -1 || regnum == i)
390 ppc_supply_reg (regcache, i, fpregs, offset);
393 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
394 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
395 fpregs, offsets->fpscr_offset);
398 /* Collect register REGNUM in the general-purpose register set
399 REGSET. from register cache REGCACHE into the buffer specified by
400 GREGS and LEN. If REGNUM is -1, do this for all registers in
404 ppc_collect_gregset (const struct regset *regset,
405 const struct regcache *regcache,
406 int regnum, void *gregs, size_t len)
408 struct gdbarch *gdbarch = get_regcache_arch (regcache);
409 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
410 const struct ppc_reg_offsets *offsets = regset->descr;
414 offset = offsets->r0_offset;
415 for (i = tdep->ppc_gp0_regnum;
416 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
419 if (regnum == -1 || regnum == i)
420 ppc_collect_reg (regcache, i, gregs, offset);
423 if (regnum == -1 || regnum == PC_REGNUM)
424 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
425 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
426 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
427 gregs, offsets->ps_offset);
428 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
429 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
430 gregs, offsets->cr_offset);
431 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
432 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
433 gregs, offsets->lr_offset);
434 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
435 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
436 gregs, offsets->ctr_offset);
437 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
438 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
439 gregs, offsets->xer_offset);
440 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
441 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
442 gregs, offsets->mq_offset);
445 /* Collect register REGNUM in the floating-point register set
446 REGSET. from register cache REGCACHE into the buffer specified by
447 FPREGS and LEN. If REGNUM is -1, do this for all registers in
451 ppc_collect_fpregset (const struct regset *regset,
452 const struct regcache *regcache,
453 int regnum, void *fpregs, size_t len)
455 struct gdbarch *gdbarch = get_regcache_arch (regcache);
456 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
457 const struct ppc_reg_offsets *offsets = regset->descr;
461 gdb_assert (ppc_floating_point_unit_p (gdbarch));
463 offset = offsets->f0_offset;
464 for (i = tdep->ppc_fp0_regnum;
465 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
468 if (regnum == -1 || regnum == i)
469 ppc_collect_reg (regcache, i, fpregs, offset);
472 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
473 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
474 fpregs, offsets->fpscr_offset);
478 /* Read a LEN-byte address from debugged memory address MEMADDR. */
481 read_memory_addr (CORE_ADDR memaddr, int len)
483 return read_memory_unsigned_integer (memaddr, len);
487 rs6000_skip_prologue (CORE_ADDR pc)
489 struct rs6000_framedata frame;
490 pc = skip_prologue (pc, 0, &frame);
495 insn_changes_sp_or_jumps (unsigned long insn)
497 int opcode = (insn >> 26) & 0x03f;
498 int sd = (insn >> 21) & 0x01f;
499 int a = (insn >> 16) & 0x01f;
500 int subcode = (insn >> 1) & 0x3ff;
502 /* Changes the stack pointer. */
504 /* NOTE: There are many ways to change the value of a given register.
505 The ways below are those used when the register is R1, the SP,
506 in a funtion's epilogue. */
508 if (opcode == 31 && subcode == 444 && a == 1)
509 return 1; /* mr R1,Rn */
510 if (opcode == 14 && sd == 1)
511 return 1; /* addi R1,Rn,simm */
512 if (opcode == 58 && sd == 1)
513 return 1; /* ld R1,ds(Rn) */
515 /* Transfers control. */
521 if (opcode == 19 && subcode == 16)
523 if (opcode == 19 && subcode == 528)
524 return 1; /* bcctr */
529 /* Return true if we are in the function's epilogue, i.e. after the
530 instruction that destroyed the function's stack frame.
532 1) scan forward from the point of execution:
533 a) If you find an instruction that modifies the stack pointer
534 or transfers control (except a return), execution is not in
536 b) Stop scanning if you find a return instruction or reach the
537 end of the function or reach the hard limit for the size of
539 2) scan backward from the point of execution:
540 a) If you find an instruction that modifies the stack pointer,
541 execution *is* in an epilogue, return.
542 b) Stop scanning if you reach an instruction that transfers
543 control or the beginning of the function or reach the hard
544 limit for the size of an epilogue. */
547 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
549 bfd_byte insn_buf[PPC_INSN_SIZE];
550 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
552 struct frame_info *curfrm;
554 /* Find the search limits based on function boundaries and hard limit. */
556 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
559 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
560 if (epilogue_start < func_start) epilogue_start = func_start;
562 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
563 if (epilogue_end > func_end) epilogue_end = func_end;
565 curfrm = get_current_frame ();
567 /* Scan forward until next 'blr'. */
569 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
571 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
573 insn = extract_signed_integer (insn_buf, PPC_INSN_SIZE);
574 if (insn == 0x4e800020)
576 if (insn_changes_sp_or_jumps (insn))
580 /* Scan backward until adjustment to stack pointer (R1). */
582 for (scan_pc = pc - PPC_INSN_SIZE;
583 scan_pc >= epilogue_start;
584 scan_pc -= PPC_INSN_SIZE)
586 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
588 insn = extract_signed_integer (insn_buf, PPC_INSN_SIZE);
589 if (insn_changes_sp_or_jumps (insn))
597 /* Fill in fi->saved_regs */
599 struct frame_extra_info
601 /* Functions calling alloca() change the value of the stack
602 pointer. We need to use initial stack pointer (which is saved in
603 r31 by gcc) in such cases. If a compiler emits traceback table,
604 then we should use the alloca register specified in traceback
606 CORE_ADDR initial_sp; /* initial stack pointer. */
609 /* Get the ith function argument for the current function. */
611 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
614 return get_frame_register_unsigned (frame, 3 + argi);
617 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
620 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
627 absolute = (int) ((instr >> 1) & 1);
632 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
636 dest = pc + immediate;
640 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
644 dest = pc + immediate;
648 ext_op = (instr >> 1) & 0x3ff;
650 if (ext_op == 16) /* br conditional register */
652 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
654 /* If we are about to return from a signal handler, dest is
655 something like 0x3c90. The current frame is a signal handler
656 caller frame, upon completion of the sigreturn system call
657 execution will return to the saved PC in the frame. */
658 if (dest < TEXT_SEGMENT_BASE)
660 struct frame_info *fi;
662 fi = get_current_frame ();
664 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
665 gdbarch_tdep (current_gdbarch)->wordsize);
669 else if (ext_op == 528) /* br cond to count reg */
671 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
673 /* If we are about to execute a system call, dest is something
674 like 0x22fc or 0x3b00. Upon completion the system call
675 will return to the address in the link register. */
676 if (dest < TEXT_SEGMENT_BASE)
677 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
686 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
690 /* Sequence of bytes for breakpoint instruction. */
692 const static unsigned char *
693 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
695 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
696 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
698 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
699 return big_breakpoint;
701 return little_breakpoint;
705 /* AIX does not support PT_STEP. Simulate it. */
708 rs6000_software_single_step (enum target_signal signal,
709 int insert_breakpoints_p)
713 const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
719 if (insert_breakpoints_p)
723 insn = read_memory_integer (loc, 4);
725 breaks[0] = loc + breakp_sz;
727 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
729 /* Don't put two breakpoints on the same address. */
730 if (breaks[1] == breaks[0])
733 for (ii = 0; ii < 2; ++ii)
735 /* ignore invalid breakpoint. */
736 if (breaks[ii] == -1)
738 insert_single_step_breakpoint (breaks[ii]);
742 remove_single_step_breakpoints ();
744 errno = 0; /* FIXME, don't ignore errors! */
745 /* What errors? {read,write}_memory call error(). */
749 /* return pc value after skipping a function prologue and also return
750 information about a function frame.
752 in struct rs6000_framedata fdata:
753 - frameless is TRUE, if function does not have a frame.
754 - nosavedpc is TRUE, if function does not save %pc value in its frame.
755 - offset is the initial size of this stack frame --- the amount by
756 which we decrement the sp to allocate the frame.
757 - saved_gpr is the number of the first saved gpr.
758 - saved_fpr is the number of the first saved fpr.
759 - saved_vr is the number of the first saved vr.
760 - saved_ev is the number of the first saved ev.
761 - alloca_reg is the number of the register used for alloca() handling.
763 - gpr_offset is the offset of the first saved gpr from the previous frame.
764 - fpr_offset is the offset of the first saved fpr from the previous frame.
765 - vr_offset is the offset of the first saved vr from the previous frame.
766 - ev_offset is the offset of the first saved ev from the previous frame.
767 - lr_offset is the offset of the saved lr
768 - cr_offset is the offset of the saved cr
769 - vrsave_offset is the offset of the saved vrsave register
772 #define SIGNED_SHORT(x) \
773 ((sizeof (short) == 2) \
774 ? ((int)(short)(x)) \
775 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
777 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
779 /* Limit the number of skipped non-prologue instructions, as the examining
780 of the prologue is expensive. */
781 static int max_skip_non_prologue_insns = 10;
783 /* Given PC representing the starting address of a function, and
784 LIM_PC which is the (sloppy) limit to which to scan when looking
785 for a prologue, attempt to further refine this limit by using
786 the line data in the symbol table. If successful, a better guess
787 on where the prologue ends is returned, otherwise the previous
788 value of lim_pc is returned. */
790 /* FIXME: cagney/2004-02-14: This function and logic have largely been
791 superseded by skip_prologue_using_sal. */
794 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
796 struct symtab_and_line prologue_sal;
798 prologue_sal = find_pc_line (pc, 0);
799 if (prologue_sal.line != 0)
802 CORE_ADDR addr = prologue_sal.end;
804 /* Handle the case in which compiler's optimizer/scheduler
805 has moved instructions into the prologue. We scan ahead
806 in the function looking for address ranges whose corresponding
807 line number is less than or equal to the first one that we
808 found for the function. (It can be less than when the
809 scheduler puts a body instruction before the first prologue
811 for (i = 2 * max_skip_non_prologue_insns;
812 i > 0 && (lim_pc == 0 || addr < lim_pc);
815 struct symtab_and_line sal;
817 sal = find_pc_line (addr, 0);
820 if (sal.line <= prologue_sal.line
821 && sal.symtab == prologue_sal.symtab)
828 if (lim_pc == 0 || prologue_sal.end < lim_pc)
829 lim_pc = prologue_sal.end;
834 /* Return nonzero if the given instruction OP can be part of the prologue
835 of a function and saves a parameter on the stack. FRAMEP should be
836 set if one of the previous instructions in the function has set the
840 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
842 /* Move parameters from argument registers to temporary register. */
843 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
845 /* Rx must be scratch register r0. */
846 const int rx_regno = (op >> 16) & 31;
847 /* Ry: Only r3 - r10 are used for parameter passing. */
848 const int ry_regno = GET_SRC_REG (op);
850 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
852 *r0_contains_arg = 1;
859 /* Save a General Purpose Register on stack. */
861 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
862 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
864 /* Rx: Only r3 - r10 are used for parameter passing. */
865 const int rx_regno = GET_SRC_REG (op);
867 return (rx_regno >= 3 && rx_regno <= 10);
870 /* Save a General Purpose Register on stack via the Frame Pointer. */
873 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
874 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
875 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
877 /* Rx: Usually, only r3 - r10 are used for parameter passing.
878 However, the compiler sometimes uses r0 to hold an argument. */
879 const int rx_regno = GET_SRC_REG (op);
881 return ((rx_regno >= 3 && rx_regno <= 10)
882 || (rx_regno == 0 && *r0_contains_arg));
885 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
887 /* Only f2 - f8 are used for parameter passing. */
888 const int src_regno = GET_SRC_REG (op);
890 return (src_regno >= 2 && src_regno <= 8);
893 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
895 /* Only f2 - f8 are used for parameter passing. */
896 const int src_regno = GET_SRC_REG (op);
898 return (src_regno >= 2 && src_regno <= 8);
901 /* Not an insn that saves a parameter on stack. */
905 /* Assuming that INSN is a "bl" instruction located at PC, return
906 nonzero if the destination of the branch is a "blrl" instruction.
908 This sequence is sometimes found in certain function prologues.
909 It allows the function to load the LR register with a value that
910 they can use to access PIC data using PC-relative offsets. */
913 bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
915 const int opcode = 18;
916 const CORE_ADDR dest = branch_dest (opcode, insn, pc, -1);
920 return 0; /* Should never happen, but just return zero to be safe. */
922 dest_insn = read_memory_integer (dest, 4);
923 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
930 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
932 CORE_ADDR orig_pc = pc;
933 CORE_ADDR last_prologue_pc = pc;
934 CORE_ADDR li_found_pc = 0;
938 long vr_saved_offset = 0;
947 int minimal_toc_loaded = 0;
948 int prev_insn_was_prologue_insn = 1;
949 int num_skip_non_prologue_insns = 0;
950 int r0_contains_arg = 0;
951 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
952 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
954 /* Attempt to find the end of the prologue when no limit is specified.
955 Note that refine_prologue_limit() has been written so that it may
956 be used to "refine" the limits of non-zero PC values too, but this
957 is only safe if we 1) trust the line information provided by the
958 compiler and 2) iterate enough to actually find the end of the
961 It may become a good idea at some point (for both performance and
962 accuracy) to unconditionally call refine_prologue_limit(). But,
963 until we can make a clear determination that this is beneficial,
964 we'll play it safe and only use it to obtain a limit when none
965 has been specified. */
967 lim_pc = refine_prologue_limit (pc, lim_pc);
969 memset (fdata, 0, sizeof (struct rs6000_framedata));
970 fdata->saved_gpr = -1;
971 fdata->saved_fpr = -1;
972 fdata->saved_vr = -1;
973 fdata->saved_ev = -1;
974 fdata->alloca_reg = -1;
975 fdata->frameless = 1;
976 fdata->nosavedpc = 1;
980 /* Sometimes it isn't clear if an instruction is a prologue
981 instruction or not. When we encounter one of these ambiguous
982 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
983 Otherwise, we'll assume that it really is a prologue instruction. */
984 if (prev_insn_was_prologue_insn)
985 last_prologue_pc = pc;
987 /* Stop scanning if we've hit the limit. */
988 if (lim_pc != 0 && pc >= lim_pc)
991 prev_insn_was_prologue_insn = 1;
993 /* Fetch the instruction and convert it to an integer. */
994 if (target_read_memory (pc, buf, 4))
996 op = extract_signed_integer (buf, 4);
998 if ((op & 0xfc1fffff) == 0x7c0802a6)
1000 /* Since shared library / PIC code, which needs to get its
1001 address at runtime, can appear to save more than one link
1015 remember just the first one, but skip over additional
1018 lr_reg = (op & 0x03e00000);
1020 r0_contains_arg = 0;
1023 else if ((op & 0xfc1fffff) == 0x7c000026)
1025 cr_reg = (op & 0x03e00000);
1027 r0_contains_arg = 0;
1031 else if ((op & 0xfc1f0000) == 0xd8010000)
1032 { /* stfd Rx,NUM(r1) */
1033 reg = GET_SRC_REG (op);
1034 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1036 fdata->saved_fpr = reg;
1037 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1042 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1043 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1044 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1045 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1048 reg = GET_SRC_REG (op);
1049 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1051 fdata->saved_gpr = reg;
1052 if ((op & 0xfc1f0003) == 0xf8010000)
1054 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1059 else if ((op & 0xffff0000) == 0x60000000)
1062 /* Allow nops in the prologue, but do not consider them to
1063 be part of the prologue unless followed by other prologue
1065 prev_insn_was_prologue_insn = 0;
1069 else if ((op & 0xffff0000) == 0x3c000000)
1070 { /* addis 0,0,NUM, used
1071 for >= 32k frames */
1072 fdata->offset = (op & 0x0000ffff) << 16;
1073 fdata->frameless = 0;
1074 r0_contains_arg = 0;
1078 else if ((op & 0xffff0000) == 0x60000000)
1079 { /* ori 0,0,NUM, 2nd ha
1080 lf of >= 32k frames */
1081 fdata->offset |= (op & 0x0000ffff);
1082 fdata->frameless = 0;
1083 r0_contains_arg = 0;
1087 else if (lr_reg >= 0 &&
1088 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1089 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1090 /* stw Rx, NUM(r1) */
1091 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1092 /* stwu Rx, NUM(r1) */
1093 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1094 { /* where Rx == lr */
1095 fdata->lr_offset = offset;
1096 fdata->nosavedpc = 0;
1097 /* Invalidate lr_reg, but don't set it to -1.
1098 That would mean that it had never been set. */
1100 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1101 (op & 0xfc000000) == 0x90000000) /* stw */
1103 /* Does not update r1, so add displacement to lr_offset. */
1104 fdata->lr_offset += SIGNED_SHORT (op);
1109 else if (cr_reg >= 0 &&
1110 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1111 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1112 /* stw Rx, NUM(r1) */
1113 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1114 /* stwu Rx, NUM(r1) */
1115 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1116 { /* where Rx == cr */
1117 fdata->cr_offset = offset;
1118 /* Invalidate cr_reg, but don't set it to -1.
1119 That would mean that it had never been set. */
1121 if ((op & 0xfc000003) == 0xf8000000 ||
1122 (op & 0xfc000000) == 0x90000000)
1124 /* Does not update r1, so add displacement to cr_offset. */
1125 fdata->cr_offset += SIGNED_SHORT (op);
1130 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1132 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1133 prediction bits. If the LR has already been saved, we can
1137 else if (op == 0x48000005)
1143 else if (op == 0x48000004)
1148 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1149 in V.4 -mminimal-toc */
1150 (op & 0xffff0000) == 0x3bde0000)
1151 { /* addi 30,30,foo@l */
1155 else if ((op & 0xfc000001) == 0x48000001)
1159 fdata->frameless = 0;
1161 /* If the return address has already been saved, we can skip
1162 calls to blrl (for PIC). */
1163 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
1166 /* Don't skip over the subroutine call if it is not within
1167 the first three instructions of the prologue and either
1168 we have no line table information or the line info tells
1169 us that the subroutine call is not part of the line
1170 associated with the prologue. */
1171 if ((pc - orig_pc) > 8)
1173 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1174 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1176 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1180 op = read_memory_integer (pc + 4, 4);
1182 /* At this point, make sure this is not a trampoline
1183 function (a function that simply calls another functions,
1184 and nothing else). If the next is not a nop, this branch
1185 was part of the function prologue. */
1187 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1188 break; /* don't skip over
1193 /* update stack pointer */
1194 else if ((op & 0xfc1f0000) == 0x94010000)
1195 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1196 fdata->frameless = 0;
1197 fdata->offset = SIGNED_SHORT (op);
1198 offset = fdata->offset;
1201 else if ((op & 0xfc1f016a) == 0x7c01016e)
1202 { /* stwux rX,r1,rY */
1203 /* no way to figure out what r1 is going to be */
1204 fdata->frameless = 0;
1205 offset = fdata->offset;
1208 else if ((op & 0xfc1f0003) == 0xf8010001)
1209 { /* stdu rX,NUM(r1) */
1210 fdata->frameless = 0;
1211 fdata->offset = SIGNED_SHORT (op & ~3UL);
1212 offset = fdata->offset;
1215 else if ((op & 0xfc1f016a) == 0x7c01016a)
1216 { /* stdux rX,r1,rY */
1217 /* no way to figure out what r1 is going to be */
1218 fdata->frameless = 0;
1219 offset = fdata->offset;
1222 else if ((op & 0xffff0000) == 0x38210000)
1223 { /* addi r1,r1,SIMM */
1224 fdata->frameless = 0;
1225 fdata->offset += SIGNED_SHORT (op);
1226 offset = fdata->offset;
1229 /* Load up minimal toc pointer */
1230 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1231 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1232 && !minimal_toc_loaded)
1234 minimal_toc_loaded = 1;
1237 /* move parameters from argument registers to local variable
1240 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1241 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1242 (((op >> 21) & 31) <= 10) &&
1243 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1247 /* store parameters in stack */
1249 /* Move parameters from argument registers to temporary register. */
1250 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1254 /* Set up frame pointer */
1256 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1257 || op == 0x7c3f0b78)
1259 fdata->frameless = 0;
1261 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1264 /* Another way to set up the frame pointer. */
1266 else if ((op & 0xfc1fffff) == 0x38010000)
1267 { /* addi rX, r1, 0x0 */
1268 fdata->frameless = 0;
1270 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1271 + ((op & ~0x38010000) >> 21));
1274 /* AltiVec related instructions. */
1275 /* Store the vrsave register (spr 256) in another register for
1276 later manipulation, or load a register into the vrsave
1277 register. 2 instructions are used: mfvrsave and
1278 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1279 and mtspr SPR256, Rn. */
1280 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1281 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1282 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1284 vrsave_reg = GET_SRC_REG (op);
1287 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1291 /* Store the register where vrsave was saved to onto the stack:
1292 rS is the register where vrsave was stored in a previous
1294 /* 100100 sssss 00001 dddddddd dddddddd */
1295 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1297 if (vrsave_reg == GET_SRC_REG (op))
1299 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1304 /* Compute the new value of vrsave, by modifying the register
1305 where vrsave was saved to. */
1306 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1307 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1311 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1312 in a pair of insns to save the vector registers on the
1314 /* 001110 00000 00000 iiii iiii iiii iiii */
1315 /* 001110 01110 00000 iiii iiii iiii iiii */
1316 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1317 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1319 if ((op & 0xffff0000) == 0x38000000)
1320 r0_contains_arg = 0;
1322 vr_saved_offset = SIGNED_SHORT (op);
1324 /* This insn by itself is not part of the prologue, unless
1325 if part of the pair of insns mentioned above. So do not
1326 record this insn as part of the prologue yet. */
1327 prev_insn_was_prologue_insn = 0;
1329 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1330 /* 011111 sssss 11111 00000 00111001110 */
1331 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1333 if (pc == (li_found_pc + 4))
1335 vr_reg = GET_SRC_REG (op);
1336 /* If this is the first vector reg to be saved, or if
1337 it has a lower number than others previously seen,
1338 reupdate the frame info. */
1339 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1341 fdata->saved_vr = vr_reg;
1342 fdata->vr_offset = vr_saved_offset + offset;
1344 vr_saved_offset = -1;
1349 /* End AltiVec related instructions. */
1351 /* Start BookE related instructions. */
1352 /* Store gen register S at (r31+uimm).
1353 Any register less than r13 is volatile, so we don't care. */
1354 /* 000100 sssss 11111 iiiii 01100100001 */
1355 else if (arch_info->mach == bfd_mach_ppc_e500
1356 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1358 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1361 ev_reg = GET_SRC_REG (op);
1362 imm = (op >> 11) & 0x1f;
1363 ev_offset = imm * 8;
1364 /* If this is the first vector reg to be saved, or if
1365 it has a lower number than others previously seen,
1366 reupdate the frame info. */
1367 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1369 fdata->saved_ev = ev_reg;
1370 fdata->ev_offset = ev_offset + offset;
1375 /* Store gen register rS at (r1+rB). */
1376 /* 000100 sssss 00001 bbbbb 01100100000 */
1377 else if (arch_info->mach == bfd_mach_ppc_e500
1378 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1380 if (pc == (li_found_pc + 4))
1382 ev_reg = GET_SRC_REG (op);
1383 /* If this is the first vector reg to be saved, or if
1384 it has a lower number than others previously seen,
1385 reupdate the frame info. */
1386 /* We know the contents of rB from the previous instruction. */
1387 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1389 fdata->saved_ev = ev_reg;
1390 fdata->ev_offset = vr_saved_offset + offset;
1392 vr_saved_offset = -1;
1398 /* Store gen register r31 at (rA+uimm). */
1399 /* 000100 11111 aaaaa iiiii 01100100001 */
1400 else if (arch_info->mach == bfd_mach_ppc_e500
1401 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1403 /* Wwe know that the source register is 31 already, but
1404 it can't hurt to compute it. */
1405 ev_reg = GET_SRC_REG (op);
1406 ev_offset = ((op >> 11) & 0x1f) * 8;
1407 /* If this is the first vector reg to be saved, or if
1408 it has a lower number than others previously seen,
1409 reupdate the frame info. */
1410 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1412 fdata->saved_ev = ev_reg;
1413 fdata->ev_offset = ev_offset + offset;
1418 /* Store gen register S at (r31+r0).
1419 Store param on stack when offset from SP bigger than 4 bytes. */
1420 /* 000100 sssss 11111 00000 01100100000 */
1421 else if (arch_info->mach == bfd_mach_ppc_e500
1422 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1424 if (pc == (li_found_pc + 4))
1426 if ((op & 0x03e00000) >= 0x01a00000)
1428 ev_reg = GET_SRC_REG (op);
1429 /* If this is the first vector reg to be saved, or if
1430 it has a lower number than others previously seen,
1431 reupdate the frame info. */
1432 /* We know the contents of r0 from the previous
1434 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1436 fdata->saved_ev = ev_reg;
1437 fdata->ev_offset = vr_saved_offset + offset;
1441 vr_saved_offset = -1;
1446 /* End BookE related instructions. */
1450 /* Not a recognized prologue instruction.
1451 Handle optimizer code motions into the prologue by continuing
1452 the search if we have no valid frame yet or if the return
1453 address is not yet saved in the frame. */
1454 if (fdata->frameless == 0
1455 && (lr_reg == -1 || fdata->nosavedpc == 0))
1458 if (op == 0x4e800020 /* blr */
1459 || op == 0x4e800420) /* bctr */
1460 /* Do not scan past epilogue in frameless functions or
1463 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1464 /* Never skip branches. */
1467 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1468 /* Do not scan too many insns, scanning insns is expensive with
1472 /* Continue scanning. */
1473 prev_insn_was_prologue_insn = 0;
1479 /* I have problems with skipping over __main() that I need to address
1480 * sometime. Previously, I used to use misc_function_vector which
1481 * didn't work as well as I wanted to be. -MGO */
1483 /* If the first thing after skipping a prolog is a branch to a function,
1484 this might be a call to an initializer in main(), introduced by gcc2.
1485 We'd like to skip over it as well. Fortunately, xlc does some extra
1486 work before calling a function right after a prologue, thus we can
1487 single out such gcc2 behaviour. */
1490 if ((op & 0xfc000001) == 0x48000001)
1491 { /* bl foo, an initializer function? */
1492 op = read_memory_integer (pc + 4, 4);
1494 if (op == 0x4def7b82)
1495 { /* cror 0xf, 0xf, 0xf (nop) */
1497 /* Check and see if we are in main. If so, skip over this
1498 initializer function as well. */
1500 tmp = find_pc_misc_function (pc);
1502 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1508 fdata->offset = -fdata->offset;
1509 return last_prologue_pc;
1513 /*************************************************************************
1514 Support for creating pushing a dummy frame into the stack, and popping
1516 *************************************************************************/
1519 /* All the ABI's require 16 byte alignment. */
1521 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1523 return (addr & -16);
1526 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1527 the first eight words of the argument list (that might be less than
1528 eight parameters if some parameters occupy more than one word) are
1529 passed in r3..r10 registers. float and double parameters are
1530 passed in fpr's, in addition to that. Rest of the parameters if any
1531 are passed in user stack. There might be cases in which half of the
1532 parameter is copied into registers, the other half is pushed into
1535 Stack must be aligned on 64-bit boundaries when synthesizing
1538 If the function is returning a structure, then the return address is passed
1539 in r3, then the first 7 words of the parameters can be passed in registers,
1540 starting from r4. */
1543 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1544 struct regcache *regcache, CORE_ADDR bp_addr,
1545 int nargs, struct value **args, CORE_ADDR sp,
1546 int struct_return, CORE_ADDR struct_addr)
1548 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1551 int argno; /* current argument number */
1552 int argbytes; /* current argument byte */
1553 gdb_byte tmp_buffer[50];
1554 int f_argno = 0; /* current floating point argno */
1555 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1556 CORE_ADDR func_addr = find_function_addr (function, NULL);
1558 struct value *arg = 0;
1563 /* The calling convention this function implements assumes the
1564 processor has floating-point registers. We shouldn't be using it
1565 on PPC variants that lack them. */
1566 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1568 /* The first eight words of ther arguments are passed in registers.
1569 Copy them appropriately. */
1572 /* If the function is returning a `struct', then the first word
1573 (which will be passed in r3) is used for struct return address.
1574 In that case we should advance one word and start from r4
1575 register to copy parameters. */
1578 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1584 effectively indirect call... gcc does...
1586 return_val example( float, int);
1589 float in fp0, int in r3
1590 offset of stack on overflow 8/16
1591 for varargs, must go by type.
1593 float in r3&r4, int in r5
1594 offset of stack on overflow different
1596 return in r3 or f0. If no float, must study how gcc emulates floats;
1597 pay attention to arg promotion.
1598 User may have to cast\args to handle promotion correctly
1599 since gdb won't know if prototype supplied or not.
1602 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1604 int reg_size = register_size (current_gdbarch, ii + 3);
1607 type = check_typedef (value_type (arg));
1608 len = TYPE_LENGTH (type);
1610 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1613 /* Floating point arguments are passed in fpr's, as well as gpr's.
1614 There are 13 fpr's reserved for passing parameters. At this point
1615 there is no way we would run out of them. */
1617 gdb_assert (len <= 8);
1619 regcache_cooked_write (regcache,
1620 tdep->ppc_fp0_regnum + 1 + f_argno,
1621 value_contents (arg));
1628 /* Argument takes more than one register. */
1629 while (argbytes < len)
1631 gdb_byte word[MAX_REGISTER_SIZE];
1632 memset (word, 0, reg_size);
1634 ((char *) value_contents (arg)) + argbytes,
1635 (len - argbytes) > reg_size
1636 ? reg_size : len - argbytes);
1637 regcache_cooked_write (regcache,
1638 tdep->ppc_gp0_regnum + 3 + ii,
1640 ++ii, argbytes += reg_size;
1643 goto ran_out_of_registers_for_arguments;
1650 /* Argument can fit in one register. No problem. */
1651 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1652 gdb_byte word[MAX_REGISTER_SIZE];
1654 memset (word, 0, reg_size);
1655 memcpy (word, value_contents (arg), len);
1656 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1661 ran_out_of_registers_for_arguments:
1663 saved_sp = read_sp ();
1665 /* Location for 8 parameters are always reserved. */
1668 /* Another six words for back chain, TOC register, link register, etc. */
1671 /* Stack pointer must be quadword aligned. */
1674 /* If there are more arguments, allocate space for them in
1675 the stack, then push them starting from the ninth one. */
1677 if ((argno < nargs) || argbytes)
1683 space += ((len - argbytes + 3) & -4);
1689 for (; jj < nargs; ++jj)
1691 struct value *val = args[jj];
1692 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
1695 /* Add location required for the rest of the parameters. */
1696 space = (space + 15) & -16;
1699 /* This is another instance we need to be concerned about
1700 securing our stack space. If we write anything underneath %sp
1701 (r1), we might conflict with the kernel who thinks he is free
1702 to use this area. So, update %sp first before doing anything
1705 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1707 /* If the last argument copied into the registers didn't fit there
1708 completely, push the rest of it into stack. */
1712 write_memory (sp + 24 + (ii * 4),
1713 value_contents (arg) + argbytes,
1716 ii += ((len - argbytes + 3) & -4) / 4;
1719 /* Push the rest of the arguments into stack. */
1720 for (; argno < nargs; ++argno)
1724 type = check_typedef (value_type (arg));
1725 len = TYPE_LENGTH (type);
1728 /* Float types should be passed in fpr's, as well as in the
1730 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1733 gdb_assert (len <= 8);
1735 regcache_cooked_write (regcache,
1736 tdep->ppc_fp0_regnum + 1 + f_argno,
1737 value_contents (arg));
1741 write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
1742 ii += ((len + 3) & -4) / 4;
1746 /* Set the stack pointer. According to the ABI, the SP is meant to
1747 be set _before_ the corresponding stack space is used. On AIX,
1748 this even applies when the target has been completely stopped!
1749 Not doing this can lead to conflicts with the kernel which thinks
1750 that it still has control over this not-yet-allocated stack
1752 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1754 /* Set back chain properly. */
1755 store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
1756 write_memory (sp, tmp_buffer, wordsize);
1758 /* Point the inferior function call's return address at the dummy's
1760 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1762 /* Set the TOC register, get the value from the objfile reader
1763 which, in turn, gets it from the VMAP table. */
1764 if (rs6000_find_toc_address_hook != NULL)
1766 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1767 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1770 target_store_registers (-1);
1774 static enum return_value_convention
1775 rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype,
1776 struct regcache *regcache, gdb_byte *readbuf,
1777 const gdb_byte *writebuf)
1779 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1782 /* The calling convention this function implements assumes the
1783 processor has floating-point registers. We shouldn't be using it
1784 on PowerPC variants that lack them. */
1785 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1787 /* AltiVec extension: Functions that declare a vector data type as a
1788 return value place that return value in VR2. */
1789 if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype)
1790 && TYPE_LENGTH (valtype) == 16)
1793 regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
1795 regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
1797 return RETURN_VALUE_REGISTER_CONVENTION;
1800 /* If the called subprogram returns an aggregate, there exists an
1801 implicit first argument, whose value is the address of a caller-
1802 allocated buffer into which the callee is assumed to store its
1803 return value. All explicit parameters are appropriately
1805 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1806 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1807 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1808 return RETURN_VALUE_STRUCT_CONVENTION;
1810 /* Scalar floating-point values are returned in FPR1 for float or
1811 double, and in FPR1:FPR2 for quadword precision. Fortran
1812 complex*8 and complex*16 are returned in FPR1:FPR2, and
1813 complex*32 is returned in FPR1:FPR4. */
1814 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
1815 && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8))
1817 struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
1820 /* FIXME: kettenis/2007-01-01: Add support for quadword
1821 precision and complex. */
1825 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
1826 convert_typed_floating (regval, regtype, readbuf, valtype);
1830 convert_typed_floating (writebuf, valtype, regval, regtype);
1831 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
1834 return RETURN_VALUE_REGISTER_CONVENTION;
1837 /* Values of the types int, long, short, pointer, and char (length
1838 is less than or equal to four bytes), as well as bit values of
1839 lengths less than or equal to 32 bits, must be returned right
1840 justified in GPR3 with signed values sign extended and unsigned
1841 values zero extended, as necessary. */
1842 if (TYPE_LENGTH (valtype) <= tdep->wordsize)
1848 /* For reading we don't have to worry about sign extension. */
1849 regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1851 store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval);
1855 /* For writing, use unpack_long since that should handle any
1856 required sign extension. */
1857 regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1858 unpack_long (valtype, writebuf));
1861 return RETURN_VALUE_REGISTER_CONVENTION;
1864 /* Eight-byte non-floating-point scalar values must be returned in
1867 if (TYPE_LENGTH (valtype) == 8)
1869 gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT);
1870 gdb_assert (tdep->wordsize == 4);
1876 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval);
1877 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
1879 memcpy (readbuf, regval, 8);
1883 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
1884 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
1888 return RETURN_VALUE_REGISTER_CONVENTION;
1891 return RETURN_VALUE_STRUCT_CONVENTION;
1894 /* Return whether handle_inferior_event() should proceed through code
1895 starting at PC in function NAME when stepping.
1897 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1898 handle memory references that are too distant to fit in instructions
1899 generated by the compiler. For example, if 'foo' in the following
1904 is greater than 32767, the linker might replace the lwz with a branch to
1905 somewhere in @FIX1 that does the load in 2 instructions and then branches
1906 back to where execution should continue.
1908 GDB should silently step over @FIX code, just like AIX dbx does.
1909 Unfortunately, the linker uses the "b" instruction for the
1910 branches, meaning that the link register doesn't get set.
1911 Therefore, GDB's usual step_over_function () mechanism won't work.
1913 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1914 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1918 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1920 return name && !strncmp (name, "@FIX", 4);
1923 /* Skip code that the user doesn't want to see when stepping:
1925 1. Indirect function calls use a piece of trampoline code to do context
1926 switching, i.e. to set the new TOC table. Skip such code if we are on
1927 its first instruction (as when we have single-stepped to here).
1929 2. Skip shared library trampoline code (which is different from
1930 indirect function call trampolines).
1932 3. Skip bigtoc fixup code.
1934 Result is desired PC to step until, or NULL if we are not in
1935 code that should be skipped. */
1938 rs6000_skip_trampoline_code (CORE_ADDR pc)
1940 unsigned int ii, op;
1942 CORE_ADDR solib_target_pc;
1943 struct minimal_symbol *msymbol;
1945 static unsigned trampoline_code[] =
1947 0x800b0000, /* l r0,0x0(r11) */
1948 0x90410014, /* st r2,0x14(r1) */
1949 0x7c0903a6, /* mtctr r0 */
1950 0x804b0004, /* l r2,0x4(r11) */
1951 0x816b0008, /* l r11,0x8(r11) */
1952 0x4e800420, /* bctr */
1953 0x4e800020, /* br */
1957 /* Check for bigtoc fixup code. */
1958 msymbol = lookup_minimal_symbol_by_pc (pc);
1960 && rs6000_in_solib_return_trampoline (pc,
1961 DEPRECATED_SYMBOL_NAME (msymbol)))
1963 /* Double-check that the third instruction from PC is relative "b". */
1964 op = read_memory_integer (pc + 8, 4);
1965 if ((op & 0xfc000003) == 0x48000000)
1967 /* Extract bits 6-29 as a signed 24-bit relative word address and
1968 add it to the containing PC. */
1969 rel = ((int)(op << 6) >> 6);
1970 return pc + 8 + rel;
1974 /* If pc is in a shared library trampoline, return its target. */
1975 solib_target_pc = find_solib_trampoline_target (pc);
1976 if (solib_target_pc)
1977 return solib_target_pc;
1979 for (ii = 0; trampoline_code[ii]; ++ii)
1981 op = read_memory_integer (pc + (ii * 4), 4);
1982 if (op != trampoline_code[ii])
1985 ii = read_register (11); /* r11 holds destination addr */
1986 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1990 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1991 isn't available with that word size, return 0. */
1994 regsize (const struct reg *reg, int wordsize)
1996 return wordsize == 8 ? reg->sz64 : reg->sz32;
1999 /* Return the name of register number N, or null if no such register exists
2000 in the current architecture. */
2003 rs6000_register_name (int n)
2005 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2006 const struct reg *reg = tdep->regs + n;
2008 if (!regsize (reg, tdep->wordsize))
2013 /* Return the GDB type object for the "standard" data type
2014 of data in register N. */
2016 static struct type *
2017 rs6000_register_type (struct gdbarch *gdbarch, int n)
2019 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2020 const struct reg *reg = tdep->regs + n;
2023 return builtin_type_double;
2026 int size = regsize (reg, tdep->wordsize);
2030 return builtin_type_int0;
2032 return builtin_type_uint32;
2034 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
2035 return builtin_type_vec64;
2037 return builtin_type_uint64;
2040 return builtin_type_vec128;
2043 internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"),
2049 /* Is REGNUM a member of REGGROUP? */
2051 rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2052 struct reggroup *group)
2054 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2059 if (REGISTER_NAME (regnum) == NULL
2060 || *REGISTER_NAME (regnum) == '\0')
2062 if (group == all_reggroup)
2065 float_p = (regnum == tdep->ppc_fpscr_regnum
2066 || (regnum >= tdep->ppc_fp0_regnum
2067 && regnum < tdep->ppc_fp0_regnum + 32));
2068 if (group == float_reggroup)
2071 vector_p = ((tdep->ppc_vr0_regnum >= 0
2072 && regnum >= tdep->ppc_vr0_regnum
2073 && regnum < tdep->ppc_vr0_regnum + 32)
2074 || (tdep->ppc_ev0_regnum >= 0
2075 && regnum >= tdep->ppc_ev0_regnum
2076 && regnum < tdep->ppc_ev0_regnum + 32)
2077 || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */
2078 || regnum == tdep->ppc_vrsave_regnum
2079 || regnum == tdep->ppc_acc_regnum
2080 || regnum == tdep->ppc_spefscr_regnum);
2081 if (group == vector_reggroup)
2084 /* Note that PS aka MSR isn't included - it's a system register (and
2085 besides, due to GCC's CFI foobar you do not want to restore
2087 general_p = ((regnum >= tdep->ppc_gp0_regnum
2088 && regnum < tdep->ppc_gp0_regnum + 32)
2089 || regnum == tdep->ppc_toc_regnum
2090 || regnum == tdep->ppc_cr_regnum
2091 || regnum == tdep->ppc_lr_regnum
2092 || regnum == tdep->ppc_ctr_regnum
2093 || regnum == tdep->ppc_xer_regnum
2094 || regnum == PC_REGNUM);
2095 if (group == general_reggroup)
2098 if (group == save_reggroup || group == restore_reggroup)
2099 return general_p || vector_p || float_p;
2104 /* The register format for RS/6000 floating point registers is always
2105 double, we need a conversion if the memory format is float. */
2108 rs6000_convert_register_p (int regnum, struct type *type)
2110 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2113 && TYPE_CODE (type) == TYPE_CODE_FLT
2114 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2118 rs6000_register_to_value (struct frame_info *frame,
2123 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2124 gdb_byte from[MAX_REGISTER_SIZE];
2126 gdb_assert (reg->fpr);
2127 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2129 get_frame_register (frame, regnum, from);
2130 convert_typed_floating (from, builtin_type_double, to, type);
2134 rs6000_value_to_register (struct frame_info *frame,
2137 const gdb_byte *from)
2139 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2140 gdb_byte to[MAX_REGISTER_SIZE];
2142 gdb_assert (reg->fpr);
2143 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2145 convert_typed_floating (from, type, to, builtin_type_double);
2146 put_frame_register (frame, regnum, to);
2149 /* Move SPE vector register values between a 64-bit buffer and the two
2150 32-bit raw register halves in a regcache. This function handles
2151 both splitting a 64-bit value into two 32-bit halves, and joining
2152 two halves into a whole 64-bit value, depending on the function
2153 passed as the MOVE argument.
2155 EV_REG must be the number of an SPE evN vector register --- a
2156 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2159 Call MOVE once for each 32-bit half of that register, passing
2160 REGCACHE, the number of the raw register corresponding to that
2161 half, and the address of the appropriate half of BUFFER.
2163 For example, passing 'regcache_raw_read' as the MOVE function will
2164 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2165 'regcache_raw_supply' will supply the contents of BUFFER to the
2166 appropriate pair of raw registers in REGCACHE.
2168 You may need to cast away some 'const' qualifiers when passing
2169 MOVE, since this function can't tell at compile-time which of
2170 REGCACHE or BUFFER is acting as the source of the data. If C had
2171 co-variant type qualifiers, ... */
2173 e500_move_ev_register (void (*move) (struct regcache *regcache,
2174 int regnum, gdb_byte *buf),
2175 struct regcache *regcache, int ev_reg,
2178 struct gdbarch *arch = get_regcache_arch (regcache);
2179 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2181 gdb_byte *byte_buffer = buffer;
2183 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
2184 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
2186 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2188 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2190 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2191 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2195 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2196 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2201 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2202 int reg_nr, gdb_byte *buffer)
2204 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2205 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2207 gdb_assert (regcache_arch == gdbarch);
2209 if (tdep->ppc_ev0_regnum <= reg_nr
2210 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2211 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2213 internal_error (__FILE__, __LINE__,
2214 _("e500_pseudo_register_read: "
2215 "called on unexpected register '%s' (%d)"),
2216 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2220 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2221 int reg_nr, const gdb_byte *buffer)
2223 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2224 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2226 gdb_assert (regcache_arch == gdbarch);
2228 if (tdep->ppc_ev0_regnum <= reg_nr
2229 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2230 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2232 regcache, reg_nr, (gdb_byte *) buffer);
2234 internal_error (__FILE__, __LINE__,
2235 _("e500_pseudo_register_read: "
2236 "called on unexpected register '%s' (%d)"),
2237 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2240 /* The E500 needs a custom reggroup function: it has anonymous raw
2241 registers, and default_register_reggroup_p assumes that anonymous
2242 registers are not members of any reggroup. */
2244 e500_register_reggroup_p (struct gdbarch *gdbarch,
2246 struct reggroup *group)
2248 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2250 /* The save and restore register groups need to include the
2251 upper-half registers, even though they're anonymous. */
2252 if ((group == save_reggroup
2253 || group == restore_reggroup)
2254 && (tdep->ppc_ev0_upper_regnum <= regnum
2255 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
2258 /* In all other regards, the default reggroup definition is fine. */
2259 return default_register_reggroup_p (gdbarch, regnum, group);
2262 /* Convert a DBX STABS register number to a GDB register number. */
2264 rs6000_stab_reg_to_regnum (int num)
2266 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2268 if (0 <= num && num <= 31)
2269 return tdep->ppc_gp0_regnum + num;
2270 else if (32 <= num && num <= 63)
2271 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2272 specifies registers the architecture doesn't have? Our
2273 callers don't check the value we return. */
2274 return tdep->ppc_fp0_regnum + (num - 32);
2275 else if (77 <= num && num <= 108)
2276 return tdep->ppc_vr0_regnum + (num - 77);
2277 else if (1200 <= num && num < 1200 + 32)
2278 return tdep->ppc_ev0_regnum + (num - 1200);
2283 return tdep->ppc_mq_regnum;
2285 return tdep->ppc_lr_regnum;
2287 return tdep->ppc_ctr_regnum;
2289 return tdep->ppc_xer_regnum;
2291 return tdep->ppc_vrsave_regnum;
2293 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2295 return tdep->ppc_acc_regnum;
2297 return tdep->ppc_spefscr_regnum;
2304 /* Convert a Dwarf 2 register number to a GDB register number. */
2306 rs6000_dwarf2_reg_to_regnum (int num)
2308 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2310 if (0 <= num && num <= 31)
2311 return tdep->ppc_gp0_regnum + num;
2312 else if (32 <= num && num <= 63)
2313 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2314 specifies registers the architecture doesn't have? Our
2315 callers don't check the value we return. */
2316 return tdep->ppc_fp0_regnum + (num - 32);
2317 else if (1124 <= num && num < 1124 + 32)
2318 return tdep->ppc_vr0_regnum + (num - 1124);
2319 else if (1200 <= num && num < 1200 + 32)
2320 return tdep->ppc_ev0_regnum + (num - 1200);
2325 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2327 return tdep->ppc_acc_regnum;
2329 return tdep->ppc_mq_regnum;
2331 return tdep->ppc_xer_regnum;
2333 return tdep->ppc_lr_regnum;
2335 return tdep->ppc_ctr_regnum;
2337 return tdep->ppc_vrsave_regnum;
2339 return tdep->ppc_spefscr_regnum;
2345 /* Hook called when a new child process is started. */
2348 rs6000_create_inferior (int pid)
2350 if (rs6000_set_host_arch_hook)
2351 rs6000_set_host_arch_hook (pid);
2354 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2356 Usually a function pointer's representation is simply the address
2357 of the function. On the RS/6000 however, a function pointer is
2358 represented by a pointer to an OPD entry. This OPD entry contains
2359 three words, the first word is the address of the function, the
2360 second word is the TOC pointer (r2), and the third word is the
2361 static chain value. Throughout GDB it is currently assumed that a
2362 function pointer contains the address of the function, which is not
2363 easy to fix. In addition, the conversion of a function address to
2364 a function pointer would require allocation of an OPD entry in the
2365 inferior's memory space, with all its drawbacks. To be able to
2366 call C++ virtual methods in the inferior (which are called via
2367 function pointers), find_function_addr uses this function to get the
2368 function address from a function pointer. */
2370 /* Return real function address if ADDR (a function pointer) is in the data
2371 space and is therefore a special function pointer. */
2374 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2376 struct target_ops *targ)
2378 struct obj_section *s;
2380 s = find_pc_section (addr);
2381 if (s && s->the_bfd_section->flags & SEC_CODE)
2384 /* ADDR is in the data space, so it's a special function pointer. */
2385 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
2389 /* Handling the various POWER/PowerPC variants. */
2392 /* The arrays here called registers_MUMBLE hold information about available
2395 For each family of PPC variants, I've tried to isolate out the
2396 common registers and put them up front, so that as long as you get
2397 the general family right, GDB will correctly identify the registers
2398 common to that family. The common register sets are:
2400 For the 60x family: hid0 hid1 iabr dabr pir
2402 For the 505 and 860 family: eie eid nri
2404 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2405 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2408 Most of these register groups aren't anything formal. I arrived at
2409 them by looking at the registers that occurred in more than one
2412 Note: kevinb/2002-04-30: Support for the fpscr register was added
2413 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2414 for Power. For PowerPC, slot 70 was unused and was already in the
2415 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2416 slot 70 was being used for "mq", so the next available slot (71)
2417 was chosen. It would have been nice to be able to make the
2418 register numbers the same across processor cores, but this wasn't
2419 possible without either 1) renumbering some registers for some
2420 processors or 2) assigning fpscr to a really high slot that's
2421 larger than any current register number. Doing (1) is bad because
2422 existing stubs would break. Doing (2) is undesirable because it
2423 would introduce a really large gap between fpscr and the rest of
2424 the registers for most processors. */
2426 /* Convenience macros for populating register arrays. */
2428 /* Within another macro, convert S to a string. */
2432 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2433 and 64 bits on 64-bit systems. */
2434 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2436 /* Return a struct reg defining register NAME that's 32 bits on all
2438 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2440 /* Return a struct reg defining register NAME that's 64 bits on all
2442 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2444 /* Return a struct reg defining register NAME that's 128 bits on all
2446 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2448 /* Return a struct reg defining floating-point register NAME. */
2449 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2451 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2452 long on all systems. */
2453 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2455 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2456 systems and that doesn't exist on 64-bit systems. */
2457 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2459 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2460 systems and that doesn't exist on 32-bit systems. */
2461 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2463 /* Return a struct reg placeholder for a register that doesn't exist. */
2464 #define R0 { 0, 0, 0, 0, 0, -1 }
2466 /* Return a struct reg defining an anonymous raw register that's 32
2467 bits on all systems. */
2468 #define A4 { 0, 4, 4, 0, 0, -1 }
2470 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2471 32-bit systems and 64 bits on 64-bit systems. */
2472 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2474 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2476 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2478 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2479 all systems, and whose SPR number is NUMBER. */
2480 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2482 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2483 64-bit systems and that doesn't exist on 32-bit systems. */
2484 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2486 /* UISA registers common across all architectures, including POWER. */
2488 #define COMMON_UISA_REGS \
2489 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2490 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2491 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2492 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2493 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2494 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2495 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2496 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2497 /* 64 */ R(pc), R(ps)
2499 /* UISA-level SPRs for PowerPC. */
2500 #define PPC_UISA_SPRS \
2501 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2503 /* UISA-level SPRs for PowerPC without floating point support. */
2504 #define PPC_UISA_NOFP_SPRS \
2505 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2507 /* Segment registers, for PowerPC. */
2508 #define PPC_SEGMENT_REGS \
2509 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2510 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2511 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2512 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2514 /* OEA SPRs for PowerPC. */
2515 #define PPC_OEA_SPRS \
2517 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2518 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2519 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2520 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2521 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2522 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2523 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2524 /* 116 */ S4(dec), S(dabr), S4(ear)
2526 /* AltiVec registers. */
2527 #define PPC_ALTIVEC_REGS \
2528 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2529 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2530 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2531 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2532 /*151*/R4(vscr), R4(vrsave)
2535 /* On machines supporting the SPE APU, the general-purpose registers
2536 are 64 bits long. There are SIMD vector instructions to treat them
2537 as pairs of floats, but the rest of the instruction set treats them
2538 as 32-bit registers, and only operates on their lower halves.
2540 In the GDB regcache, we treat their high and low halves as separate
2541 registers. The low halves we present as the general-purpose
2542 registers, and then we have pseudo-registers that stitch together
2543 the upper and lower halves and present them as pseudo-registers. */
2545 /* SPE GPR lower halves --- raw registers. */
2546 #define PPC_SPE_GP_REGS \
2547 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2548 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2549 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2550 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2552 /* SPE GPR upper halves --- anonymous raw registers. */
2553 #define PPC_SPE_UPPER_GP_REGS \
2554 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2555 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2556 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2557 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2559 /* SPE GPR vector registers --- pseudo registers based on underlying
2560 gprs and the anonymous upper half raw registers. */
2561 #define PPC_EV_PSEUDO_REGS \
2562 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2563 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2564 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2565 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2567 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2568 user-level SPR's. */
2569 static const struct reg registers_power[] =
2572 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
2576 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2577 view of the PowerPC. */
2578 static const struct reg registers_powerpc[] =
2587 Some notes about the "tcr" special-purpose register:
2588 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2589 403's programmable interval timer, fixed interval timer, and
2591 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2592 watchdog timer, and nothing else.
2594 Some of the fields are similar between the two, but they're not
2595 compatible with each other. Since the two variants have different
2596 registers, with different numbers, but the same name, we can't
2597 splice the register name to get the SPR number. */
2598 static const struct reg registers_403[] =
2604 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2605 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2606 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2607 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2608 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2609 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
2612 /* IBM PowerPC 403GC.
2613 See the comments about 'tcr' for the 403, above. */
2614 static const struct reg registers_403GC[] =
2620 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2621 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2622 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2623 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2624 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2625 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
2626 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
2627 /* 147 */ S(tbhu), S(tblu)
2630 /* Motorola PowerPC 505. */
2631 static const struct reg registers_505[] =
2637 /* 119 */ S(eie), S(eid), S(nri)
2640 /* Motorola PowerPC 860 or 850. */
2641 static const struct reg registers_860[] =
2647 /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
2648 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
2649 /* 127 */ S(der), S(counta), S(countb), S(cmpe),
2650 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
2651 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
2652 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
2653 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
2654 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
2655 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
2656 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
2657 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
2658 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
2661 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2662 for reading and writing RTCU and RTCL. However, how one reads and writes a
2663 register is the stub's problem. */
2664 static const struct reg registers_601[] =
2670 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2671 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
2674 /* Motorola PowerPC 602.
2675 See the notes under the 403 about 'tcr'. */
2676 static const struct reg registers_602[] =
2682 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2683 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
2684 /* 127 */ S(sebr), S(ser), S(sp), S(lt)
2687 /* Motorola/IBM PowerPC 603 or 603e. */
2688 static const struct reg registers_603[] =
2694 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2695 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
2696 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
2699 /* Motorola PowerPC 604 or 604e. */
2700 static const struct reg registers_604[] =
2706 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2707 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
2708 /* 127 */ S(sia), S(sda)
2711 /* Motorola/IBM PowerPC 750 or 740. */
2712 static const struct reg registers_750[] =
2718 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2719 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
2720 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
2721 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
2722 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
2723 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
2727 /* Motorola PowerPC 7400. */
2728 static const struct reg registers_7400[] =
2730 /* gpr0-gpr31, fpr0-fpr31 */
2732 /* cr, lr, ctr, xer, fpscr */
2737 /* vr0-vr31, vrsave, vscr */
2739 /* FIXME? Add more registers? */
2742 /* Motorola e500. */
2743 static const struct reg registers_e500[] =
2745 /* 0 .. 31 */ PPC_SPE_GP_REGS,
2746 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
2747 /* 64 .. 65 */ R(pc), R(ps),
2748 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
2749 /* 71 .. 72 */ R8(acc), S4(spefscr),
2750 /* NOTE: Add new registers here the end of the raw register
2751 list and just before the first pseudo register. */
2752 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2755 /* Information about a particular processor variant. */
2759 /* Name of this variant. */
2762 /* English description of the variant. */
2765 /* bfd_arch_info.arch corresponding to variant. */
2766 enum bfd_architecture arch;
2768 /* bfd_arch_info.mach corresponding to variant. */
2771 /* Number of real registers. */
2774 /* Number of pseudo registers. */
2777 /* Number of total registers (the sum of nregs and npregs). */
2780 /* Table of register names; registers[R] is the name of the register
2782 const struct reg *regs;
2785 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2788 num_registers (const struct reg *reg_list, int num_tot_regs)
2793 for (i = 0; i < num_tot_regs; i++)
2794 if (!reg_list[i].pseudo)
2801 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2806 for (i = 0; i < num_tot_regs; i++)
2807 if (reg_list[i].pseudo)
2813 /* Information in this table comes from the following web sites:
2814 IBM: http://www.chips.ibm.com:80/products/embedded/
2815 Motorola: http://www.mot.com/SPS/PowerPC/
2817 I'm sure I've got some of the variant descriptions not quite right.
2818 Please report any inaccuracies you find to GDB's maintainer.
2820 If you add entries to this table, please be sure to allow the new
2821 value as an argument to the --with-cpu flag, in configure.in. */
2823 static struct variant variants[] =
2826 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2827 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2829 {"power", "POWER user-level", bfd_arch_rs6000,
2830 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2832 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2833 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2835 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2836 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2838 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2839 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2841 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2842 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2844 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2845 604, -1, -1, tot_num_registers (registers_604),
2847 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2848 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2850 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2851 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2853 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2854 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2856 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2857 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2859 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2860 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2862 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2863 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2867 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2868 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2870 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2871 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2873 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2874 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2876 {"a35", "PowerPC A35", bfd_arch_powerpc,
2877 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2879 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2880 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2882 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2883 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2886 /* FIXME: I haven't checked the register sets of the following. */
2887 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2888 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2890 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2891 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2893 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2894 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2897 {0, 0, 0, 0, 0, 0, 0, 0}
2900 /* Initialize the number of registers and pseudo registers in each variant. */
2903 init_variants (void)
2907 for (v = variants; v->name; v++)
2910 v->nregs = num_registers (v->regs, v->num_tot_regs);
2911 if (v->npregs == -1)
2912 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2916 /* Return the variant corresponding to architecture ARCH and machine number
2917 MACH. If no such variant exists, return null. */
2919 static const struct variant *
2920 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2922 const struct variant *v;
2924 for (v = variants; v->name; v++)
2925 if (arch == v->arch && mach == v->mach)
2932 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2934 if (!info->disassembler_options)
2935 info->disassembler_options = "any";
2937 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2938 return print_insn_big_powerpc (memaddr, info);
2940 return print_insn_little_powerpc (memaddr, info);
2944 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2946 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2949 static struct frame_id
2950 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2952 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2954 frame_pc_unwind (next_frame));
2957 struct rs6000_frame_cache
2960 CORE_ADDR initial_sp;
2961 struct trad_frame_saved_reg *saved_regs;
2964 static struct rs6000_frame_cache *
2965 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2967 struct rs6000_frame_cache *cache;
2968 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2969 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2970 struct rs6000_framedata fdata;
2971 int wordsize = tdep->wordsize;
2974 if ((*this_cache) != NULL)
2975 return (*this_cache);
2976 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2977 (*this_cache) = cache;
2978 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2980 func = frame_func_unwind (next_frame, NORMAL_FRAME);
2981 pc = frame_pc_unwind (next_frame);
2982 skip_prologue (func, pc, &fdata);
2984 /* Figure out the parent's stack pointer. */
2986 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2987 address of the current frame. Things might be easier if the
2988 ->frame pointed to the outer-most address of the frame. In
2989 the mean time, the address of the prev frame is used as the
2990 base address of this frame. */
2991 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2993 /* If the function appears to be frameless, check a couple of likely
2994 indicators that we have simply failed to find the frame setup.
2995 Two common cases of this are missing symbols (i.e.
2996 frame_func_unwind returns the wrong address or 0), and assembly
2997 stubs which have a fast exit path but set up a frame on the slow
3000 If the LR appears to return to this function, then presume that
3001 we have an ABI compliant frame that we failed to find. */
3002 if (fdata.frameless && fdata.lr_offset == 0)
3007 saved_lr = frame_unwind_register_unsigned (next_frame,
3008 tdep->ppc_lr_regnum);
3009 if (func == 0 && saved_lr == pc)
3013 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3014 if (func == saved_func)
3020 fdata.frameless = 0;
3021 fdata.lr_offset = wordsize;
3025 if (!fdata.frameless)
3026 /* Frameless really means stackless. */
3027 cache->base = read_memory_addr (cache->base, wordsize);
3029 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
3031 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3032 All fpr's from saved_fpr to fp31 are saved. */
3034 if (fdata.saved_fpr >= 0)
3037 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3039 /* If skip_prologue says floating-point registers were saved,
3040 but the current architecture has no floating-point registers,
3041 then that's strange. But we have no indices to even record
3042 the addresses under, so we just ignore it. */
3043 if (ppc_floating_point_unit_p (gdbarch))
3044 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3046 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3051 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3052 All gpr's from saved_gpr to gpr31 are saved. */
3054 if (fdata.saved_gpr >= 0)
3057 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3058 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3060 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3061 gpr_addr += wordsize;
3065 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3066 All vr's from saved_vr to vr31 are saved. */
3067 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3069 if (fdata.saved_vr >= 0)
3072 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3073 for (i = fdata.saved_vr; i < 32; i++)
3075 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3076 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3081 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3082 All vr's from saved_ev to ev31 are saved. ????? */
3083 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
3085 if (fdata.saved_ev >= 0)
3088 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3089 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3091 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3092 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3093 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3098 /* If != 0, fdata.cr_offset is the offset from the frame that
3100 if (fdata.cr_offset != 0)
3101 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3103 /* If != 0, fdata.lr_offset is the offset from the frame that
3105 if (fdata.lr_offset != 0)
3106 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
3107 /* The PC is found in the link register. */
3108 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
3110 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3111 holds the VRSAVE. */
3112 if (fdata.vrsave_offset != 0)
3113 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3115 if (fdata.alloca_reg < 0)
3116 /* If no alloca register used, then fi->frame is the value of the
3117 %sp for this frame, and it is good enough. */
3118 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
3120 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3127 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3128 struct frame_id *this_id)
3130 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3132 (*this_id) = frame_id_build (info->base,
3133 frame_func_unwind (next_frame, NORMAL_FRAME));
3137 rs6000_frame_prev_register (struct frame_info *next_frame,
3139 int regnum, int *optimizedp,
3140 enum lval_type *lvalp, CORE_ADDR *addrp,
3141 int *realnump, gdb_byte *valuep)
3143 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3145 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3146 optimizedp, lvalp, addrp, realnump, valuep);
3149 static const struct frame_unwind rs6000_frame_unwind =
3152 rs6000_frame_this_id,
3153 rs6000_frame_prev_register
3156 static const struct frame_unwind *
3157 rs6000_frame_sniffer (struct frame_info *next_frame)
3159 return &rs6000_frame_unwind;
3165 rs6000_frame_base_address (struct frame_info *next_frame,
3168 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3170 return info->initial_sp;
3173 static const struct frame_base rs6000_frame_base = {
3174 &rs6000_frame_unwind,
3175 rs6000_frame_base_address,
3176 rs6000_frame_base_address,
3177 rs6000_frame_base_address
3180 static const struct frame_base *
3181 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3183 return &rs6000_frame_base;
3186 /* Initialize the current architecture based on INFO. If possible, re-use an
3187 architecture from ARCHES, which is a list of architectures already created
3188 during this debugging session.
3190 Called e.g. at program startup, when reading a core file, and when reading
3193 static struct gdbarch *
3194 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3196 struct gdbarch *gdbarch;
3197 struct gdbarch_tdep *tdep;
3198 int wordsize, from_xcoff_exec, from_elf_exec, i, off;
3200 const struct variant *v;
3201 enum bfd_architecture arch;
3207 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3208 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3210 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3211 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3213 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3215 /* Check word size. If INFO is from a binary file, infer it from
3216 that, else choose a likely default. */
3217 if (from_xcoff_exec)
3219 if (bfd_xcoff_is_xcoff64 (info.abfd))
3224 else if (from_elf_exec)
3226 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3233 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3234 wordsize = info.bfd_arch_info->bits_per_word /
3235 info.bfd_arch_info->bits_per_byte;
3240 /* Find a candidate among extant architectures. */
3241 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3243 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3245 /* Word size in the various PowerPC bfd_arch_info structs isn't
3246 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3247 separate word size check. */
3248 tdep = gdbarch_tdep (arches->gdbarch);
3249 if (tdep && tdep->wordsize == wordsize)
3250 return arches->gdbarch;
3253 /* None found, create a new architecture from INFO, whose bfd_arch_info
3254 validity depends on the source:
3255 - executable useless
3256 - rs6000_host_arch() good
3258 - "set arch" trust blindly
3259 - GDB startup useless but harmless */
3261 if (!from_xcoff_exec)
3263 arch = info.bfd_arch_info->arch;
3264 mach = info.bfd_arch_info->mach;
3268 arch = bfd_arch_powerpc;
3269 bfd_default_set_arch_mach (&abfd, arch, 0);
3270 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3271 mach = info.bfd_arch_info->mach;
3273 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3274 tdep->wordsize = wordsize;
3276 /* For e500 executables, the apuinfo section is of help here. Such
3277 section contains the identifier and revision number of each
3278 Application-specific Processing Unit that is present on the
3279 chip. The content of the section is determined by the assembler
3280 which looks at each instruction and determines which unit (and
3281 which version of it) can execute it. In our case we just look for
3282 the existance of the section. */
3286 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3289 arch = info.bfd_arch_info->arch;
3290 mach = bfd_mach_ppc_e500;
3291 bfd_default_set_arch_mach (&abfd, arch, mach);
3292 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3296 gdbarch = gdbarch_alloc (&info, tdep);
3298 /* Initialize the number of real and pseudo registers in each variant. */
3301 /* Choose variant. */
3302 v = find_variant_by_arch (arch, mach);
3306 tdep->regs = v->regs;
3308 tdep->ppc_gp0_regnum = 0;
3309 tdep->ppc_toc_regnum = 2;
3310 tdep->ppc_ps_regnum = 65;
3311 tdep->ppc_cr_regnum = 66;
3312 tdep->ppc_lr_regnum = 67;
3313 tdep->ppc_ctr_regnum = 68;
3314 tdep->ppc_xer_regnum = 69;
3315 if (v->mach == bfd_mach_ppc_601)
3316 tdep->ppc_mq_regnum = 124;
3317 else if (arch == bfd_arch_rs6000)
3318 tdep->ppc_mq_regnum = 70;
3320 tdep->ppc_mq_regnum = -1;
3321 tdep->ppc_fp0_regnum = 32;
3322 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
3323 tdep->ppc_sr0_regnum = 71;
3324 tdep->ppc_vr0_regnum = -1;
3325 tdep->ppc_vrsave_regnum = -1;
3326 tdep->ppc_ev0_upper_regnum = -1;
3327 tdep->ppc_ev0_regnum = -1;
3328 tdep->ppc_ev31_regnum = -1;
3329 tdep->ppc_acc_regnum = -1;
3330 tdep->ppc_spefscr_regnum = -1;
3332 set_gdbarch_pc_regnum (gdbarch, 64);
3333 set_gdbarch_sp_regnum (gdbarch, 1);
3334 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
3335 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3336 if (sysv_abi && wordsize == 8)
3337 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3338 else if (sysv_abi && wordsize == 4)
3339 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3341 set_gdbarch_return_value (gdbarch, rs6000_return_value);
3343 /* Set lr_frame_offset. */
3345 tdep->lr_frame_offset = 16;
3347 tdep->lr_frame_offset = 4;
3349 tdep->lr_frame_offset = 8;
3351 if (v->arch == bfd_arch_rs6000)
3352 tdep->ppc_sr0_regnum = -1;
3353 else if (v->arch == bfd_arch_powerpc)
3357 tdep->ppc_sr0_regnum = -1;
3358 tdep->ppc_vr0_regnum = 71;
3359 tdep->ppc_vrsave_regnum = 104;
3361 case bfd_mach_ppc_7400:
3362 tdep->ppc_vr0_regnum = 119;
3363 tdep->ppc_vrsave_regnum = 152;
3365 case bfd_mach_ppc_e500:
3366 tdep->ppc_toc_regnum = -1;
3367 tdep->ppc_ev0_upper_regnum = 32;
3368 tdep->ppc_ev0_regnum = 73;
3369 tdep->ppc_ev31_regnum = 104;
3370 tdep->ppc_acc_regnum = 71;
3371 tdep->ppc_spefscr_regnum = 72;
3372 tdep->ppc_fp0_regnum = -1;
3373 tdep->ppc_fpscr_regnum = -1;
3374 tdep->ppc_sr0_regnum = -1;
3375 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3376 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3377 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
3380 case bfd_mach_ppc64:
3381 case bfd_mach_ppc_620:
3382 case bfd_mach_ppc_630:
3383 case bfd_mach_ppc_a35:
3384 case bfd_mach_ppc_rs64ii:
3385 case bfd_mach_ppc_rs64iii:
3386 /* These processor's register sets don't have segment registers. */
3387 tdep->ppc_sr0_regnum = -1;
3391 internal_error (__FILE__, __LINE__,
3392 _("rs6000_gdbarch_init: "
3393 "received unexpected BFD 'arch' value"));
3395 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3397 /* Sanity check on registers. */
3398 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
3400 /* Select instruction printer. */
3401 if (arch == bfd_arch_rs6000)
3402 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3404 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3406 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
3408 set_gdbarch_num_regs (gdbarch, v->nregs);
3409 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
3410 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3411 set_gdbarch_register_type (gdbarch, rs6000_register_type);
3412 set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p);
3414 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3415 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3416 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3417 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3418 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3419 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3420 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3422 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3424 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3425 set_gdbarch_char_signed (gdbarch, 0);
3427 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3428 if (sysv_abi && wordsize == 8)
3430 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3431 else if (!sysv_abi && wordsize == 4)
3432 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3433 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3434 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3436 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3438 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3439 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3440 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3442 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3443 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3445 if (sysv_abi && wordsize == 4)
3446 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3447 else if (sysv_abi && wordsize == 8)
3448 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3450 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3452 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3453 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3455 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3456 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3458 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3459 for the descriptor and ".FN" for the entry-point -- a user
3460 specifying "break FN" will unexpectedly end up with a breakpoint
3461 on the descriptor and not the function. This architecture method
3462 transforms any breakpoints on descriptors into breakpoints on the
3463 corresponding entry point. */
3464 if (sysv_abi && wordsize == 8)
3465 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3467 /* Not sure on this. FIXMEmgo */
3468 set_gdbarch_frame_args_skip (gdbarch, 8);
3472 /* Handle RS/6000 function pointers (which are really function
3474 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3475 rs6000_convert_from_func_ptr_addr);
3478 /* Helpers for function argument information. */
3479 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3481 /* Hook in ABI-specific overrides, if they have been registered. */
3482 gdbarch_init_osabi (info, gdbarch);
3486 case GDB_OSABI_LINUX:
3487 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3488 have altivec registers. If not, ptrace will fail the first time it's
3489 called to access one and will not be called again. This wart will
3490 be removed when Daniel Jacobowitz's proposal for autodetecting target
3491 registers is implemented. */
3492 if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64))
3494 tdep->ppc_vr0_regnum = 71;
3495 tdep->ppc_vrsave_regnum = 104;
3498 case GDB_OSABI_NETBSD_AOUT:
3499 case GDB_OSABI_NETBSD_ELF:
3500 case GDB_OSABI_UNKNOWN:
3501 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3502 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3503 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3504 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3507 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3509 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3510 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3511 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3512 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3515 init_sim_regno_table (gdbarch);
3521 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3523 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3528 /* FIXME: Dump gdbarch_tdep. */
3531 /* Initialization code. */
3533 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3536 _initialize_rs6000_tdep (void)
3538 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3539 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);