1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "libbfd.h" /* for bfd_default_set_arch_mach */
41 #include "coff/internal.h" /* for libcoff.h */
42 #include "libcoff.h" /* for xcoff_data */
43 #include "coff/xcoff.h"
48 #include "solib-svr4.h"
51 #include "gdb_assert.h"
54 #include "trad-frame.h"
55 #include "frame-unwind.h"
56 #include "frame-base.h"
58 /* If the kernel has to deliver a signal, it pushes a sigcontext
59 structure on the stack and then calls the signal handler, passing
60 the address of the sigcontext in an argument register. Usually
61 the signal handler doesn't save this register, so we have to
62 access the sigcontext structure via an offset from the signal handler
64 The following constants were determined by experimentation on AIX 3.2. */
65 #define SIG_FRAME_PC_OFFSET 96
66 #define SIG_FRAME_LR_OFFSET 108
67 #define SIG_FRAME_FP_OFFSET 284
69 /* To be used by skip_prologue. */
71 struct rs6000_framedata
73 int offset; /* total size of frame --- the distance
74 by which we decrement sp to allocate
76 int saved_gpr; /* smallest # of saved gpr */
77 int saved_fpr; /* smallest # of saved fpr */
78 int saved_vr; /* smallest # of saved vr */
79 int saved_ev; /* smallest # of saved ev */
80 int alloca_reg; /* alloca register number (frame ptr) */
81 char frameless; /* true if frameless functions. */
82 char nosavedpc; /* true if pc not saved. */
83 int gpr_offset; /* offset of saved gprs from prev sp */
84 int fpr_offset; /* offset of saved fprs from prev sp */
85 int vr_offset; /* offset of saved vrs from prev sp */
86 int ev_offset; /* offset of saved evs from prev sp */
87 int lr_offset; /* offset of saved lr */
88 int cr_offset; /* offset of saved cr */
89 int vrsave_offset; /* offset of saved vrsave register */
92 /* Description of a single register. */
96 char *name; /* name of register */
97 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
98 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
99 unsigned char fpr; /* whether register is floating-point */
100 unsigned char pseudo; /* whether register is pseudo */
103 /* Breakpoint shadows for the single step instructions will be kept here. */
105 static struct sstep_breaks
107 /* Address, or 0 if this is not in use. */
109 /* Shadow contents. */
114 /* Hook for determining the TOC address when calling functions in the
115 inferior under AIX. The initialization code in rs6000-nat.c sets
116 this hook to point to find_toc_address. */
118 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
120 /* Hook to set the current architecture when starting a child process.
121 rs6000-nat.c sets this. */
123 void (*rs6000_set_host_arch_hook) (int) = NULL;
125 /* Static function prototypes */
127 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
129 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
130 struct rs6000_framedata *);
132 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
134 altivec_register_p (int regno)
136 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
137 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
140 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
143 /* Use the architectures FP registers? */
145 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
147 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
148 if (info->arch == bfd_arch_powerpc)
149 return (info->mach != bfd_mach_ppc_e500);
150 if (info->arch == bfd_arch_rs6000)
156 /* Register set support functions. */
159 ppc_supply_reg (struct regcache *regcache, int regnum,
160 const char *regs, size_t offset)
162 if (regnum != -1 && offset != -1)
163 regcache_raw_supply (regcache, regnum, regs + offset);
167 ppc_collect_reg (const struct regcache *regcache, int regnum,
168 char *regs, size_t offset)
170 if (regnum != -1 && offset != -1)
171 regcache_raw_collect (regcache, regnum, regs + offset);
174 /* Supply register REGNUM in the general-purpose register set REGSET
175 from the buffer specified by GREGS and LEN to register cache
176 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
179 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
180 int regnum, const void *gregs, size_t len)
182 struct gdbarch *gdbarch = get_regcache_arch (regcache);
183 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
184 const struct ppc_reg_offsets *offsets = regset->descr;
188 for (i = 0, offset = offsets->r0_offset; i < 32; i++, offset += 4)
190 if (regnum == -1 || regnum == i)
191 ppc_supply_reg (regcache, i, gregs, offset);
194 if (regnum == -1 || regnum == PC_REGNUM)
195 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
196 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
197 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
198 gregs, offsets->ps_offset);
199 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
200 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
201 gregs, offsets->cr_offset);
202 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
203 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
204 gregs, offsets->lr_offset);
205 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
206 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
207 gregs, offsets->ctr_offset);
208 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
209 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
210 gregs, offsets->cr_offset);
211 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
212 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
215 /* Supply register REGNUM in the floating-point register set REGSET
216 from the buffer specified by FPREGS and LEN to register cache
217 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
220 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
221 int regnum, const void *fpregs, size_t len)
223 struct gdbarch *gdbarch = get_regcache_arch (regcache);
224 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
225 const struct ppc_reg_offsets *offsets = regset->descr;
229 offset = offsets->f0_offset;
230 for (i = FP0_REGNUM; i < FP0_REGNUM + 32; i++, offset += 4)
232 if (regnum == -1 || regnum == i)
233 ppc_supply_reg (regcache, i, fpregs, offset);
236 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
237 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
238 fpregs, offsets->fpscr_offset);
241 /* Collect register REGNUM in the general-purpose register set
242 REGSET. from register cache REGCACHE into the buffer specified by
243 GREGS and LEN. If REGNUM is -1, do this for all registers in
247 ppc_collect_gregset (const struct regset *regset,
248 const struct regcache *regcache,
249 int regnum, void *gregs, size_t len)
251 struct gdbarch *gdbarch = get_regcache_arch (regcache);
252 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
253 const struct ppc_reg_offsets *offsets = regset->descr;
257 offset = offsets->r0_offset;
258 for (i = 0; i <= 32; i++, offset += 4)
260 if (regnum == -1 || regnum == i)
261 ppc_collect_reg (regcache, regnum, gregs, offset);
264 if (regnum == -1 || regnum == PC_REGNUM)
265 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
266 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
267 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
268 gregs, offsets->ps_offset);
269 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
270 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
271 gregs, offsets->cr_offset);
272 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
273 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
274 gregs, offsets->lr_offset);
275 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
276 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
277 gregs, offsets->ctr_offset);
278 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
279 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
280 gregs, offsets->xer_offset);
281 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
282 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
283 gregs, offsets->mq_offset);
286 /* Collect register REGNUM in the floating-point register set
287 REGSET. from register cache REGCACHE into the buffer specified by
288 FPREGS and LEN. If REGNUM is -1, do this for all registers in
292 ppc_collect_fpregset (const struct regset *regset,
293 const struct regcache *regcache,
294 int regnum, void *fpregs, size_t len)
296 struct gdbarch *gdbarch = get_regcache_arch (regcache);
297 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
298 const struct ppc_reg_offsets *offsets = regset->descr;
302 offset = offsets->f0_offset;
303 for (i = FP0_REGNUM; i <= FP0_REGNUM + 32; i++, offset += 4)
305 if (regnum == -1 || regnum == i)
306 ppc_collect_reg (regcache, regnum, fpregs, offset);
309 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
310 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
311 fpregs, offsets->fpscr_offset);
315 /* Read a LEN-byte address from debugged memory address MEMADDR. */
318 read_memory_addr (CORE_ADDR memaddr, int len)
320 return read_memory_unsigned_integer (memaddr, len);
324 rs6000_skip_prologue (CORE_ADDR pc)
326 struct rs6000_framedata frame;
327 pc = skip_prologue (pc, 0, &frame);
332 /* Fill in fi->saved_regs */
334 struct frame_extra_info
336 /* Functions calling alloca() change the value of the stack
337 pointer. We need to use initial stack pointer (which is saved in
338 r31 by gcc) in such cases. If a compiler emits traceback table,
339 then we should use the alloca register specified in traceback
341 CORE_ADDR initial_sp; /* initial stack pointer. */
344 /* Get the ith function argument for the current function. */
346 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
350 get_frame_register (frame, 3 + argi, &addr);
354 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
357 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
364 absolute = (int) ((instr >> 1) & 1);
369 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
373 dest = pc + immediate;
377 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
381 dest = pc + immediate;
385 ext_op = (instr >> 1) & 0x3ff;
387 if (ext_op == 16) /* br conditional register */
389 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
391 /* If we are about to return from a signal handler, dest is
392 something like 0x3c90. The current frame is a signal handler
393 caller frame, upon completion of the sigreturn system call
394 execution will return to the saved PC in the frame. */
395 if (dest < TEXT_SEGMENT_BASE)
397 struct frame_info *fi;
399 fi = get_current_frame ();
401 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
402 gdbarch_tdep (current_gdbarch)->wordsize);
406 else if (ext_op == 528) /* br cond to count reg */
408 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
410 /* If we are about to execute a system call, dest is something
411 like 0x22fc or 0x3b00. Upon completion the system call
412 will return to the address in the link register. */
413 if (dest < TEXT_SEGMENT_BASE)
414 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
423 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
427 /* Sequence of bytes for breakpoint instruction. */
429 const static unsigned char *
430 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
432 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
433 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
435 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
436 return big_breakpoint;
438 return little_breakpoint;
442 /* AIX does not support PT_STEP. Simulate it. */
445 rs6000_software_single_step (enum target_signal signal,
446 int insert_breakpoints_p)
450 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
456 if (insert_breakpoints_p)
461 insn = read_memory_integer (loc, 4);
463 breaks[0] = loc + breakp_sz;
465 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
467 /* Don't put two breakpoints on the same address. */
468 if (breaks[1] == breaks[0])
471 stepBreaks[1].address = 0;
473 for (ii = 0; ii < 2; ++ii)
476 /* ignore invalid breakpoint. */
477 if (breaks[ii] == -1)
479 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
480 stepBreaks[ii].address = breaks[ii];
487 /* remove step breakpoints. */
488 for (ii = 0; ii < 2; ++ii)
489 if (stepBreaks[ii].address != 0)
490 target_remove_breakpoint (stepBreaks[ii].address,
491 stepBreaks[ii].data);
493 errno = 0; /* FIXME, don't ignore errors! */
494 /* What errors? {read,write}_memory call error(). */
498 /* return pc value after skipping a function prologue and also return
499 information about a function frame.
501 in struct rs6000_framedata fdata:
502 - frameless is TRUE, if function does not have a frame.
503 - nosavedpc is TRUE, if function does not save %pc value in its frame.
504 - offset is the initial size of this stack frame --- the amount by
505 which we decrement the sp to allocate the frame.
506 - saved_gpr is the number of the first saved gpr.
507 - saved_fpr is the number of the first saved fpr.
508 - saved_vr is the number of the first saved vr.
509 - saved_ev is the number of the first saved ev.
510 - alloca_reg is the number of the register used for alloca() handling.
512 - gpr_offset is the offset of the first saved gpr from the previous frame.
513 - fpr_offset is the offset of the first saved fpr from the previous frame.
514 - vr_offset is the offset of the first saved vr from the previous frame.
515 - ev_offset is the offset of the first saved ev from the previous frame.
516 - lr_offset is the offset of the saved lr
517 - cr_offset is the offset of the saved cr
518 - vrsave_offset is the offset of the saved vrsave register
521 #define SIGNED_SHORT(x) \
522 ((sizeof (short) == 2) \
523 ? ((int)(short)(x)) \
524 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
526 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
528 /* Limit the number of skipped non-prologue instructions, as the examining
529 of the prologue is expensive. */
530 static int max_skip_non_prologue_insns = 10;
532 /* Given PC representing the starting address of a function, and
533 LIM_PC which is the (sloppy) limit to which to scan when looking
534 for a prologue, attempt to further refine this limit by using
535 the line data in the symbol table. If successful, a better guess
536 on where the prologue ends is returned, otherwise the previous
537 value of lim_pc is returned. */
539 /* FIXME: cagney/2004-02-14: This function and logic have largely been
540 superseded by skip_prologue_using_sal. */
543 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
545 struct symtab_and_line prologue_sal;
547 prologue_sal = find_pc_line (pc, 0);
548 if (prologue_sal.line != 0)
551 CORE_ADDR addr = prologue_sal.end;
553 /* Handle the case in which compiler's optimizer/scheduler
554 has moved instructions into the prologue. We scan ahead
555 in the function looking for address ranges whose corresponding
556 line number is less than or equal to the first one that we
557 found for the function. (It can be less than when the
558 scheduler puts a body instruction before the first prologue
560 for (i = 2 * max_skip_non_prologue_insns;
561 i > 0 && (lim_pc == 0 || addr < lim_pc);
564 struct symtab_and_line sal;
566 sal = find_pc_line (addr, 0);
569 if (sal.line <= prologue_sal.line
570 && sal.symtab == prologue_sal.symtab)
577 if (lim_pc == 0 || prologue_sal.end < lim_pc)
578 lim_pc = prologue_sal.end;
585 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
587 CORE_ADDR orig_pc = pc;
588 CORE_ADDR last_prologue_pc = pc;
589 CORE_ADDR li_found_pc = 0;
593 long vr_saved_offset = 0;
602 int minimal_toc_loaded = 0;
603 int prev_insn_was_prologue_insn = 1;
604 int num_skip_non_prologue_insns = 0;
605 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
606 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
608 /* Attempt to find the end of the prologue when no limit is specified.
609 Note that refine_prologue_limit() has been written so that it may
610 be used to "refine" the limits of non-zero PC values too, but this
611 is only safe if we 1) trust the line information provided by the
612 compiler and 2) iterate enough to actually find the end of the
615 It may become a good idea at some point (for both performance and
616 accuracy) to unconditionally call refine_prologue_limit(). But,
617 until we can make a clear determination that this is beneficial,
618 we'll play it safe and only use it to obtain a limit when none
619 has been specified. */
621 lim_pc = refine_prologue_limit (pc, lim_pc);
623 memset (fdata, 0, sizeof (struct rs6000_framedata));
624 fdata->saved_gpr = -1;
625 fdata->saved_fpr = -1;
626 fdata->saved_vr = -1;
627 fdata->saved_ev = -1;
628 fdata->alloca_reg = -1;
629 fdata->frameless = 1;
630 fdata->nosavedpc = 1;
634 /* Sometimes it isn't clear if an instruction is a prologue
635 instruction or not. When we encounter one of these ambiguous
636 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
637 Otherwise, we'll assume that it really is a prologue instruction. */
638 if (prev_insn_was_prologue_insn)
639 last_prologue_pc = pc;
641 /* Stop scanning if we've hit the limit. */
642 if (lim_pc != 0 && pc >= lim_pc)
645 prev_insn_was_prologue_insn = 1;
647 /* Fetch the instruction and convert it to an integer. */
648 if (target_read_memory (pc, buf, 4))
650 op = extract_signed_integer (buf, 4);
652 if ((op & 0xfc1fffff) == 0x7c0802a6)
654 /* Since shared library / PIC code, which needs to get its
655 address at runtime, can appear to save more than one link
669 remember just the first one, but skip over additional
672 lr_reg = (op & 0x03e00000);
675 else if ((op & 0xfc1fffff) == 0x7c000026)
677 cr_reg = (op & 0x03e00000);
681 else if ((op & 0xfc1f0000) == 0xd8010000)
682 { /* stfd Rx,NUM(r1) */
683 reg = GET_SRC_REG (op);
684 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
686 fdata->saved_fpr = reg;
687 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
692 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
693 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
694 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
695 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
698 reg = GET_SRC_REG (op);
699 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
701 fdata->saved_gpr = reg;
702 if ((op & 0xfc1f0003) == 0xf8010000)
704 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
709 else if ((op & 0xffff0000) == 0x60000000)
712 /* Allow nops in the prologue, but do not consider them to
713 be part of the prologue unless followed by other prologue
715 prev_insn_was_prologue_insn = 0;
719 else if ((op & 0xffff0000) == 0x3c000000)
720 { /* addis 0,0,NUM, used
722 fdata->offset = (op & 0x0000ffff) << 16;
723 fdata->frameless = 0;
727 else if ((op & 0xffff0000) == 0x60000000)
728 { /* ori 0,0,NUM, 2nd ha
729 lf of >= 32k frames */
730 fdata->offset |= (op & 0x0000ffff);
731 fdata->frameless = 0;
735 else if (lr_reg != -1 &&
736 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
737 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
738 /* stw Rx, NUM(r1) */
739 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
740 /* stwu Rx, NUM(r1) */
741 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
742 { /* where Rx == lr */
743 fdata->lr_offset = offset;
744 fdata->nosavedpc = 0;
746 if ((op & 0xfc000003) == 0xf8000000 || /* std */
747 (op & 0xfc000000) == 0x90000000) /* stw */
749 /* Does not update r1, so add displacement to lr_offset. */
750 fdata->lr_offset += SIGNED_SHORT (op);
755 else if (cr_reg != -1 &&
756 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
757 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
758 /* stw Rx, NUM(r1) */
759 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
760 /* stwu Rx, NUM(r1) */
761 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
762 { /* where Rx == cr */
763 fdata->cr_offset = offset;
765 if ((op & 0xfc000003) == 0xf8000000 ||
766 (op & 0xfc000000) == 0x90000000)
768 /* Does not update r1, so add displacement to cr_offset. */
769 fdata->cr_offset += SIGNED_SHORT (op);
774 else if (op == 0x48000005)
780 else if (op == 0x48000004)
785 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
786 in V.4 -mminimal-toc */
787 (op & 0xffff0000) == 0x3bde0000)
788 { /* addi 30,30,foo@l */
792 else if ((op & 0xfc000001) == 0x48000001)
796 fdata->frameless = 0;
797 /* Don't skip over the subroutine call if it is not within
798 the first three instructions of the prologue. */
799 if ((pc - orig_pc) > 8)
802 op = read_memory_integer (pc + 4, 4);
804 /* At this point, make sure this is not a trampoline
805 function (a function that simply calls another functions,
806 and nothing else). If the next is not a nop, this branch
807 was part of the function prologue. */
809 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
810 break; /* don't skip over
815 /* update stack pointer */
816 else if ((op & 0xfc1f0000) == 0x94010000)
817 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
818 fdata->frameless = 0;
819 fdata->offset = SIGNED_SHORT (op);
820 offset = fdata->offset;
823 else if ((op & 0xfc1f016a) == 0x7c01016e)
824 { /* stwux rX,r1,rY */
825 /* no way to figure out what r1 is going to be */
826 fdata->frameless = 0;
827 offset = fdata->offset;
830 else if ((op & 0xfc1f0003) == 0xf8010001)
831 { /* stdu rX,NUM(r1) */
832 fdata->frameless = 0;
833 fdata->offset = SIGNED_SHORT (op & ~3UL);
834 offset = fdata->offset;
837 else if ((op & 0xfc1f016a) == 0x7c01016a)
838 { /* stdux rX,r1,rY */
839 /* no way to figure out what r1 is going to be */
840 fdata->frameless = 0;
841 offset = fdata->offset;
844 /* Load up minimal toc pointer */
845 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
846 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
847 && !minimal_toc_loaded)
849 minimal_toc_loaded = 1;
852 /* move parameters from argument registers to local variable
855 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
856 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
857 (((op >> 21) & 31) <= 10) &&
858 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
862 /* store parameters in stack */
864 /* Move parameters from argument registers to temporary register. */
865 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
866 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
867 (((op >> 21) & 31) <= 10) &&
868 (((op >> 16) & 31) == 0)) /* Rx: scratch register r0 */
872 else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
873 (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
874 (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
878 /* store parameters in stack via frame pointer */
881 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
882 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
883 (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r31) */
884 (op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
888 /* Set up frame pointer */
890 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
893 fdata->frameless = 0;
895 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
898 /* Another way to set up the frame pointer. */
900 else if ((op & 0xfc1fffff) == 0x38010000)
901 { /* addi rX, r1, 0x0 */
902 fdata->frameless = 0;
904 fdata->alloca_reg = (tdep->ppc_gp0_regnum
905 + ((op & ~0x38010000) >> 21));
908 /* AltiVec related instructions. */
909 /* Store the vrsave register (spr 256) in another register for
910 later manipulation, or load a register into the vrsave
911 register. 2 instructions are used: mfvrsave and
912 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
913 and mtspr SPR256, Rn. */
914 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
915 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
916 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
918 vrsave_reg = GET_SRC_REG (op);
921 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
925 /* Store the register where vrsave was saved to onto the stack:
926 rS is the register where vrsave was stored in a previous
928 /* 100100 sssss 00001 dddddddd dddddddd */
929 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
931 if (vrsave_reg == GET_SRC_REG (op))
933 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
938 /* Compute the new value of vrsave, by modifying the register
939 where vrsave was saved to. */
940 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
941 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
945 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
946 in a pair of insns to save the vector registers on the
948 /* 001110 00000 00000 iiii iiii iiii iiii */
949 /* 001110 01110 00000 iiii iiii iiii iiii */
950 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
951 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
954 vr_saved_offset = SIGNED_SHORT (op);
956 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
957 /* 011111 sssss 11111 00000 00111001110 */
958 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
960 if (pc == (li_found_pc + 4))
962 vr_reg = GET_SRC_REG (op);
963 /* If this is the first vector reg to be saved, or if
964 it has a lower number than others previously seen,
965 reupdate the frame info. */
966 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
968 fdata->saved_vr = vr_reg;
969 fdata->vr_offset = vr_saved_offset + offset;
971 vr_saved_offset = -1;
976 /* End AltiVec related instructions. */
978 /* Start BookE related instructions. */
979 /* Store gen register S at (r31+uimm).
980 Any register less than r13 is volatile, so we don't care. */
981 /* 000100 sssss 11111 iiiii 01100100001 */
982 else if (arch_info->mach == bfd_mach_ppc_e500
983 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
985 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
988 ev_reg = GET_SRC_REG (op);
989 imm = (op >> 11) & 0x1f;
991 /* If this is the first vector reg to be saved, or if
992 it has a lower number than others previously seen,
993 reupdate the frame info. */
994 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
996 fdata->saved_ev = ev_reg;
997 fdata->ev_offset = ev_offset + offset;
1002 /* Store gen register rS at (r1+rB). */
1003 /* 000100 sssss 00001 bbbbb 01100100000 */
1004 else if (arch_info->mach == bfd_mach_ppc_e500
1005 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1007 if (pc == (li_found_pc + 4))
1009 ev_reg = GET_SRC_REG (op);
1010 /* If this is the first vector reg to be saved, or if
1011 it has a lower number than others previously seen,
1012 reupdate the frame info. */
1013 /* We know the contents of rB from the previous instruction. */
1014 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1016 fdata->saved_ev = ev_reg;
1017 fdata->ev_offset = vr_saved_offset + offset;
1019 vr_saved_offset = -1;
1025 /* Store gen register r31 at (rA+uimm). */
1026 /* 000100 11111 aaaaa iiiii 01100100001 */
1027 else if (arch_info->mach == bfd_mach_ppc_e500
1028 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1030 /* Wwe know that the source register is 31 already, but
1031 it can't hurt to compute it. */
1032 ev_reg = GET_SRC_REG (op);
1033 ev_offset = ((op >> 11) & 0x1f) * 8;
1034 /* If this is the first vector reg to be saved, or if
1035 it has a lower number than others previously seen,
1036 reupdate the frame info. */
1037 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1039 fdata->saved_ev = ev_reg;
1040 fdata->ev_offset = ev_offset + offset;
1045 /* Store gen register S at (r31+r0).
1046 Store param on stack when offset from SP bigger than 4 bytes. */
1047 /* 000100 sssss 11111 00000 01100100000 */
1048 else if (arch_info->mach == bfd_mach_ppc_e500
1049 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1051 if (pc == (li_found_pc + 4))
1053 if ((op & 0x03e00000) >= 0x01a00000)
1055 ev_reg = GET_SRC_REG (op);
1056 /* If this is the first vector reg to be saved, or if
1057 it has a lower number than others previously seen,
1058 reupdate the frame info. */
1059 /* We know the contents of r0 from the previous
1061 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1063 fdata->saved_ev = ev_reg;
1064 fdata->ev_offset = vr_saved_offset + offset;
1068 vr_saved_offset = -1;
1073 /* End BookE related instructions. */
1077 /* Not a recognized prologue instruction.
1078 Handle optimizer code motions into the prologue by continuing
1079 the search if we have no valid frame yet or if the return
1080 address is not yet saved in the frame. */
1081 if (fdata->frameless == 0
1082 && (lr_reg == -1 || fdata->nosavedpc == 0))
1085 if (op == 0x4e800020 /* blr */
1086 || op == 0x4e800420) /* bctr */
1087 /* Do not scan past epilogue in frameless functions or
1090 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1091 /* Never skip branches. */
1094 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1095 /* Do not scan too many insns, scanning insns is expensive with
1099 /* Continue scanning. */
1100 prev_insn_was_prologue_insn = 0;
1106 /* I have problems with skipping over __main() that I need to address
1107 * sometime. Previously, I used to use misc_function_vector which
1108 * didn't work as well as I wanted to be. -MGO */
1110 /* If the first thing after skipping a prolog is a branch to a function,
1111 this might be a call to an initializer in main(), introduced by gcc2.
1112 We'd like to skip over it as well. Fortunately, xlc does some extra
1113 work before calling a function right after a prologue, thus we can
1114 single out such gcc2 behaviour. */
1117 if ((op & 0xfc000001) == 0x48000001)
1118 { /* bl foo, an initializer function? */
1119 op = read_memory_integer (pc + 4, 4);
1121 if (op == 0x4def7b82)
1122 { /* cror 0xf, 0xf, 0xf (nop) */
1124 /* Check and see if we are in main. If so, skip over this
1125 initializer function as well. */
1127 tmp = find_pc_misc_function (pc);
1129 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1135 fdata->offset = -fdata->offset;
1136 return last_prologue_pc;
1140 /*************************************************************************
1141 Support for creating pushing a dummy frame into the stack, and popping
1143 *************************************************************************/
1146 /* All the ABI's require 16 byte alignment. */
1148 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1150 return (addr & -16);
1153 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1154 the first eight words of the argument list (that might be less than
1155 eight parameters if some parameters occupy more than one word) are
1156 passed in r3..r10 registers. float and double parameters are
1157 passed in fpr's, in addition to that. Rest of the parameters if any
1158 are passed in user stack. There might be cases in which half of the
1159 parameter is copied into registers, the other half is pushed into
1162 Stack must be aligned on 64-bit boundaries when synthesizing
1165 If the function is returning a structure, then the return address is passed
1166 in r3, then the first 7 words of the parameters can be passed in registers,
1167 starting from r4. */
1170 rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1171 struct regcache *regcache, CORE_ADDR bp_addr,
1172 int nargs, struct value **args, CORE_ADDR sp,
1173 int struct_return, CORE_ADDR struct_addr)
1175 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1178 int argno; /* current argument number */
1179 int argbytes; /* current argument byte */
1180 char tmp_buffer[50];
1181 int f_argno = 0; /* current floating point argno */
1182 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1184 struct value *arg = 0;
1189 /* The first eight words of ther arguments are passed in registers.
1190 Copy them appropriately. */
1193 /* If the function is returning a `struct', then the first word
1194 (which will be passed in r3) is used for struct return address.
1195 In that case we should advance one word and start from r4
1196 register to copy parameters. */
1199 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1205 effectively indirect call... gcc does...
1207 return_val example( float, int);
1210 float in fp0, int in r3
1211 offset of stack on overflow 8/16
1212 for varargs, must go by type.
1214 float in r3&r4, int in r5
1215 offset of stack on overflow different
1217 return in r3 or f0. If no float, must study how gcc emulates floats;
1218 pay attention to arg promotion.
1219 User may have to cast\args to handle promotion correctly
1220 since gdb won't know if prototype supplied or not.
1223 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1225 int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3);
1228 type = check_typedef (VALUE_TYPE (arg));
1229 len = TYPE_LENGTH (type);
1231 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1234 /* Floating point arguments are passed in fpr's, as well as gpr's.
1235 There are 13 fpr's reserved for passing parameters. At this point
1236 there is no way we would run out of them. */
1240 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
1242 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
1243 VALUE_CONTENTS (arg),
1251 /* Argument takes more than one register. */
1252 while (argbytes < len)
1254 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0,
1256 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)],
1257 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1258 (len - argbytes) > reg_size
1259 ? reg_size : len - argbytes);
1260 ++ii, argbytes += reg_size;
1263 goto ran_out_of_registers_for_arguments;
1270 /* Argument can fit in one register. No problem. */
1271 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1272 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size);
1273 memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj,
1274 VALUE_CONTENTS (arg), len);
1279 ran_out_of_registers_for_arguments:
1281 saved_sp = read_sp ();
1283 /* Location for 8 parameters are always reserved. */
1286 /* Another six words for back chain, TOC register, link register, etc. */
1289 /* Stack pointer must be quadword aligned. */
1292 /* If there are more arguments, allocate space for them in
1293 the stack, then push them starting from the ninth one. */
1295 if ((argno < nargs) || argbytes)
1301 space += ((len - argbytes + 3) & -4);
1307 for (; jj < nargs; ++jj)
1309 struct value *val = args[jj];
1310 space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
1313 /* Add location required for the rest of the parameters. */
1314 space = (space + 15) & -16;
1317 /* This is another instance we need to be concerned about
1318 securing our stack space. If we write anything underneath %sp
1319 (r1), we might conflict with the kernel who thinks he is free
1320 to use this area. So, update %sp first before doing anything
1323 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1325 /* If the last argument copied into the registers didn't fit there
1326 completely, push the rest of it into stack. */
1330 write_memory (sp + 24 + (ii * 4),
1331 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1334 ii += ((len - argbytes + 3) & -4) / 4;
1337 /* Push the rest of the arguments into stack. */
1338 for (; argno < nargs; ++argno)
1342 type = check_typedef (VALUE_TYPE (arg));
1343 len = TYPE_LENGTH (type);
1346 /* Float types should be passed in fpr's, as well as in the
1348 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1353 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
1355 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1 + f_argno)],
1356 VALUE_CONTENTS (arg),
1361 write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len);
1362 ii += ((len + 3) & -4) / 4;
1366 /* Set the stack pointer. According to the ABI, the SP is meant to
1367 be set _before_ the corresponding stack space is used. On AIX,
1368 this even applies when the target has been completely stopped!
1369 Not doing this can lead to conflicts with the kernel which thinks
1370 that it still has control over this not-yet-allocated stack
1372 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1374 /* Set back chain properly. */
1375 store_unsigned_integer (tmp_buffer, 4, saved_sp);
1376 write_memory (sp, tmp_buffer, 4);
1378 /* Point the inferior function call's return address at the dummy's
1380 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1382 /* Set the TOC register, get the value from the objfile reader
1383 which, in turn, gets it from the VMAP table. */
1384 if (rs6000_find_toc_address_hook != NULL)
1386 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1387 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1390 target_store_registers (-1);
1394 /* PowerOpen always puts structures in memory. Vectors, which were
1395 added later, do get returned in a register though. */
1398 rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1400 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1401 && TYPE_VECTOR (value_type))
1407 rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
1410 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1412 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1415 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1416 We need to truncate the return value into float size (4 byte) if
1419 convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
1421 builtin_type_double,
1425 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1426 && TYPE_LENGTH (valtype) == 16
1427 && TYPE_VECTOR (valtype))
1429 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1430 TYPE_LENGTH (valtype));
1434 /* return value is copied starting from r3. */
1435 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1436 && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3))
1437 offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype);
1440 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
1441 TYPE_LENGTH (valtype));
1445 /* Return whether handle_inferior_event() should proceed through code
1446 starting at PC in function NAME when stepping.
1448 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1449 handle memory references that are too distant to fit in instructions
1450 generated by the compiler. For example, if 'foo' in the following
1455 is greater than 32767, the linker might replace the lwz with a branch to
1456 somewhere in @FIX1 that does the load in 2 instructions and then branches
1457 back to where execution should continue.
1459 GDB should silently step over @FIX code, just like AIX dbx does.
1460 Unfortunately, the linker uses the "b" instruction for the branches,
1461 meaning that the link register doesn't get set. Therefore, GDB's usual
1462 step_over_function() mechanism won't work.
1464 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1465 in handle_inferior_event() to skip past @FIX code. */
1468 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1470 return name && !strncmp (name, "@FIX", 4);
1473 /* Skip code that the user doesn't want to see when stepping:
1475 1. Indirect function calls use a piece of trampoline code to do context
1476 switching, i.e. to set the new TOC table. Skip such code if we are on
1477 its first instruction (as when we have single-stepped to here).
1479 2. Skip shared library trampoline code (which is different from
1480 indirect function call trampolines).
1482 3. Skip bigtoc fixup code.
1484 Result is desired PC to step until, or NULL if we are not in
1485 code that should be skipped. */
1488 rs6000_skip_trampoline_code (CORE_ADDR pc)
1490 unsigned int ii, op;
1492 CORE_ADDR solib_target_pc;
1493 struct minimal_symbol *msymbol;
1495 static unsigned trampoline_code[] =
1497 0x800b0000, /* l r0,0x0(r11) */
1498 0x90410014, /* st r2,0x14(r1) */
1499 0x7c0903a6, /* mtctr r0 */
1500 0x804b0004, /* l r2,0x4(r11) */
1501 0x816b0008, /* l r11,0x8(r11) */
1502 0x4e800420, /* bctr */
1503 0x4e800020, /* br */
1507 /* Check for bigtoc fixup code. */
1508 msymbol = lookup_minimal_symbol_by_pc (pc);
1509 if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol)))
1511 /* Double-check that the third instruction from PC is relative "b". */
1512 op = read_memory_integer (pc + 8, 4);
1513 if ((op & 0xfc000003) == 0x48000000)
1515 /* Extract bits 6-29 as a signed 24-bit relative word address and
1516 add it to the containing PC. */
1517 rel = ((int)(op << 6) >> 6);
1518 return pc + 8 + rel;
1522 /* If pc is in a shared library trampoline, return its target. */
1523 solib_target_pc = find_solib_trampoline_target (pc);
1524 if (solib_target_pc)
1525 return solib_target_pc;
1527 for (ii = 0; trampoline_code[ii]; ++ii)
1529 op = read_memory_integer (pc + (ii * 4), 4);
1530 if (op != trampoline_code[ii])
1533 ii = read_register (11); /* r11 holds destination addr */
1534 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1538 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1539 isn't available with that word size, return 0. */
1542 regsize (const struct reg *reg, int wordsize)
1544 return wordsize == 8 ? reg->sz64 : reg->sz32;
1547 /* Return the name of register number N, or null if no such register exists
1548 in the current architecture. */
1551 rs6000_register_name (int n)
1553 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1554 const struct reg *reg = tdep->regs + n;
1556 if (!regsize (reg, tdep->wordsize))
1561 /* Index within `registers' of the first byte of the space for
1565 rs6000_register_byte (int n)
1567 return gdbarch_tdep (current_gdbarch)->regoff[n];
1570 /* Return the number of bytes of storage in the actual machine representation
1571 for register N if that register is available, else return 0. */
1574 rs6000_register_raw_size (int n)
1576 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1577 const struct reg *reg = tdep->regs + n;
1578 return regsize (reg, tdep->wordsize);
1581 /* Return the GDB type object for the "standard" data type
1582 of data in register N. */
1584 static struct type *
1585 rs6000_register_virtual_type (int n)
1587 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1588 const struct reg *reg = tdep->regs + n;
1591 return builtin_type_double;
1594 int size = regsize (reg, tdep->wordsize);
1598 return builtin_type_int0;
1600 return builtin_type_uint32;
1602 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1603 return builtin_type_vec64;
1605 return builtin_type_uint64;
1608 return builtin_type_vec128;
1611 internal_error (__FILE__, __LINE__, "Register %d size %d unknown",
1617 /* Return whether register N requires conversion when moving from raw format
1620 The register format for RS/6000 floating point registers is always
1621 double, we need a conversion if the memory format is float. */
1624 rs6000_register_convertible (int n)
1626 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n;
1630 /* Convert data from raw format for register N in buffer FROM
1631 to virtual format with type TYPE in buffer TO. */
1634 rs6000_register_convert_to_virtual (int n, struct type *type,
1635 char *from, char *to)
1637 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n))
1639 double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n));
1640 deprecated_store_floating (to, TYPE_LENGTH (type), val);
1643 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n));
1646 /* Convert data from virtual format with type TYPE in buffer FROM
1647 to raw format for register N in buffer TO. */
1650 rs6000_register_convert_to_raw (struct type *type, int n,
1651 const char *from, char *to)
1653 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n))
1655 double val = deprecated_extract_floating (from, TYPE_LENGTH (type));
1656 deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val);
1659 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n));
1663 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1664 int reg_nr, void *buffer)
1668 char temp_buffer[MAX_REGISTER_SIZE];
1669 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1671 if (reg_nr >= tdep->ppc_gp0_regnum
1672 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
1674 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1676 /* Build the value in the provided buffer. */
1677 /* Read the raw register of which this one is the lower portion. */
1678 regcache_raw_read (regcache, base_regnum, temp_buffer);
1679 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1681 memcpy ((char *) buffer, temp_buffer + offset, 4);
1686 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1687 int reg_nr, const void *buffer)
1691 char temp_buffer[MAX_REGISTER_SIZE];
1692 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1694 if (reg_nr >= tdep->ppc_gp0_regnum
1695 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
1697 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1698 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1699 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1702 /* Let's read the value of the base register into a temporary
1703 buffer, so that overwriting the last four bytes with the new
1704 value of the pseudo will leave the upper 4 bytes unchanged. */
1705 regcache_raw_read (regcache, base_regnum, temp_buffer);
1707 /* Write as an 8 byte quantity. */
1708 memcpy (temp_buffer + offset, (char *) buffer, 4);
1709 regcache_raw_write (regcache, base_regnum, temp_buffer);
1713 /* Convert a dbx stab or Dwarf 2 register number (from `r'
1714 declaration) to a gdb REGNUM. */
1716 rs6000_dwarf2_stab_reg_to_regnum (int num)
1718 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1720 if (0 <= num && num <= 31)
1721 return tdep->ppc_gp0_regnum + num;
1722 else if (32 <= num && num <= 63)
1723 return FP0_REGNUM + (num - 32);
1724 else if (1200 <= num && num < 1200 + 32)
1725 return tdep->ppc_ev0_regnum + (num - 1200);
1730 return tdep->ppc_mq_regnum;
1732 return tdep->ppc_lr_regnum;
1734 return tdep->ppc_ctr_regnum;
1736 return tdep->ppc_xer_regnum;
1738 return tdep->ppc_vrsave_regnum;
1743 /* FIXME: jimb/2004-03-28: Doesn't something need to be done here
1744 for the Altivec registers, too?
1746 Looking at GCC, the headers in config/rs6000 never define a
1747 DBX_REGISTER_NUMBER macro, so the debug info uses the same
1748 numbers GCC does internally. Then, looking at the REGISTER_NAMES
1749 macro defined in config/rs6000/rs6000.h, it seems that GCC gives
1750 v0 -- v31 the numbers 77 -- 108. But we number them 119 -- 150.
1752 I don't have a way to test this ready to hand, but I noticed it
1753 and thought I should include a note. */
1757 rs6000_store_return_value (struct type *type, char *valbuf)
1759 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1761 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1763 /* Floating point values are returned starting from FPR1 and up.
1764 Say a double_double_double type could be returned in
1765 FPR1/FPR2/FPR3 triple. */
1767 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (FP0_REGNUM + 1), valbuf,
1768 TYPE_LENGTH (type));
1769 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1771 if (TYPE_LENGTH (type) == 16
1772 && TYPE_VECTOR (type))
1773 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1774 valbuf, TYPE_LENGTH (type));
1777 /* Everything else is returned in GPR3 and up. */
1778 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3),
1779 valbuf, TYPE_LENGTH (type));
1782 /* Extract from an array REGBUF containing the (raw) register state
1783 the address in which a function should return its structure value,
1784 as a CORE_ADDR (or an expression that can be used as one). */
1787 rs6000_extract_struct_value_address (struct regcache *regcache)
1789 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
1790 function call GDB knows the address of the struct return value
1791 and hence, should not need to call this function. Unfortunately,
1792 the current call_function_by_hand() code only saves the most
1793 recent struct address leading to occasional calls. The code
1794 should instead maintain a stack of such addresses (in the dummy
1796 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
1797 really got no idea where the return value is being stored. While
1798 r3, on function entry, contained the address it will have since
1799 been reused (scratch) and hence wouldn't be valid */
1803 /* Hook called when a new child process is started. */
1806 rs6000_create_inferior (int pid)
1808 if (rs6000_set_host_arch_hook)
1809 rs6000_set_host_arch_hook (pid);
1812 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
1814 Usually a function pointer's representation is simply the address
1815 of the function. On the RS/6000 however, a function pointer is
1816 represented by a pointer to a TOC entry. This TOC entry contains
1817 three words, the first word is the address of the function, the
1818 second word is the TOC pointer (r2), and the third word is the
1819 static chain value. Throughout GDB it is currently assumed that a
1820 function pointer contains the address of the function, which is not
1821 easy to fix. In addition, the conversion of a function address to
1822 a function pointer would require allocation of a TOC entry in the
1823 inferior's memory space, with all its drawbacks. To be able to
1824 call C++ virtual methods in the inferior (which are called via
1825 function pointers), find_function_addr uses this function to get the
1826 function address from a function pointer. */
1828 /* Return real function address if ADDR (a function pointer) is in the data
1829 space and is therefore a special function pointer. */
1832 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
1834 struct target_ops *targ)
1836 struct obj_section *s;
1838 s = find_pc_section (addr);
1839 if (s && s->the_bfd_section->flags & SEC_CODE)
1842 /* ADDR is in the data space, so it's a special function pointer. */
1843 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
1847 /* Handling the various POWER/PowerPC variants. */
1850 /* The arrays here called registers_MUMBLE hold information about available
1853 For each family of PPC variants, I've tried to isolate out the
1854 common registers and put them up front, so that as long as you get
1855 the general family right, GDB will correctly identify the registers
1856 common to that family. The common register sets are:
1858 For the 60x family: hid0 hid1 iabr dabr pir
1860 For the 505 and 860 family: eie eid nri
1862 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
1863 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
1866 Most of these register groups aren't anything formal. I arrived at
1867 them by looking at the registers that occurred in more than one
1870 Note: kevinb/2002-04-30: Support for the fpscr register was added
1871 during April, 2002. Slot 70 is being used for PowerPC and slot 71
1872 for Power. For PowerPC, slot 70 was unused and was already in the
1873 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
1874 slot 70 was being used for "mq", so the next available slot (71)
1875 was chosen. It would have been nice to be able to make the
1876 register numbers the same across processor cores, but this wasn't
1877 possible without either 1) renumbering some registers for some
1878 processors or 2) assigning fpscr to a really high slot that's
1879 larger than any current register number. Doing (1) is bad because
1880 existing stubs would break. Doing (2) is undesirable because it
1881 would introduce a really large gap between fpscr and the rest of
1882 the registers for most processors. */
1884 /* Convenience macros for populating register arrays. */
1886 /* Within another macro, convert S to a string. */
1890 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
1891 and 64 bits on 64-bit systems. */
1892 #define R(name) { STR(name), 4, 8, 0, 0 }
1894 /* Return a struct reg defining register NAME that's 32 bits on all
1896 #define R4(name) { STR(name), 4, 4, 0, 0 }
1898 /* Return a struct reg defining register NAME that's 64 bits on all
1900 #define R8(name) { STR(name), 8, 8, 0, 0 }
1902 /* Return a struct reg defining register NAME that's 128 bits on all
1904 #define R16(name) { STR(name), 16, 16, 0, 0 }
1906 /* Return a struct reg defining floating-point register NAME. */
1907 #define F(name) { STR(name), 8, 8, 1, 0 }
1909 /* Return a struct reg defining a pseudo register NAME. */
1910 #define P(name) { STR(name), 4, 8, 0, 1}
1912 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
1913 systems and that doesn't exist on 64-bit systems. */
1914 #define R32(name) { STR(name), 4, 0, 0, 0 }
1916 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
1917 systems and that doesn't exist on 32-bit systems. */
1918 #define R64(name) { STR(name), 0, 8, 0, 0 }
1920 /* Return a struct reg placeholder for a register that doesn't exist. */
1921 #define R0 { 0, 0, 0, 0, 0 }
1923 /* UISA registers common across all architectures, including POWER. */
1925 #define COMMON_UISA_REGS \
1926 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1927 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1928 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1929 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1930 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
1931 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
1932 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
1933 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
1934 /* 64 */ R(pc), R(ps)
1936 #define COMMON_UISA_NOFP_REGS \
1937 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1938 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1939 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1940 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1941 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1942 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1943 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1944 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1945 /* 64 */ R(pc), R(ps)
1947 /* UISA-level SPRs for PowerPC. */
1948 #define PPC_UISA_SPRS \
1949 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
1951 /* UISA-level SPRs for PowerPC without floating point support. */
1952 #define PPC_UISA_NOFP_SPRS \
1953 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
1955 /* Segment registers, for PowerPC. */
1956 #define PPC_SEGMENT_REGS \
1957 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
1958 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
1959 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
1960 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
1962 /* OEA SPRs for PowerPC. */
1963 #define PPC_OEA_SPRS \
1965 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
1966 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
1967 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
1968 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
1969 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
1970 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
1971 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
1972 /* 116 */ R4(dec), R(dabr), R4(ear)
1974 /* AltiVec registers. */
1975 #define PPC_ALTIVEC_REGS \
1976 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
1977 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
1978 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
1979 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
1980 /*151*/R4(vscr), R4(vrsave)
1982 /* Vectors of hi-lo general purpose registers. */
1983 #define PPC_EV_REGS \
1984 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
1985 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
1986 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
1987 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
1989 /* Lower half of the EV registers. */
1990 #define PPC_GPRS_PSEUDO_REGS \
1991 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
1992 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
1993 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
1994 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31)
1996 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
1997 user-level SPR's. */
1998 static const struct reg registers_power[] =
2001 /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
2005 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2006 view of the PowerPC. */
2007 static const struct reg registers_powerpc[] =
2014 /* PowerPC UISA - a PPC processor as viewed by user-level
2015 code, but without floating point registers. */
2016 static const struct reg registers_powerpc_nofp[] =
2018 COMMON_UISA_NOFP_REGS,
2022 /* IBM PowerPC 403. */
2023 static const struct reg registers_403[] =
2029 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2030 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2031 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2032 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2033 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2034 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2)
2037 /* IBM PowerPC 403GC. */
2038 static const struct reg registers_403GC[] =
2044 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2045 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2046 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2047 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2048 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2049 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2),
2050 /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr),
2051 /* 147 */ R(tbhu), R(tblu)
2054 /* Motorola PowerPC 505. */
2055 static const struct reg registers_505[] =
2061 /* 119 */ R(eie), R(eid), R(nri)
2064 /* Motorola PowerPC 860 or 850. */
2065 static const struct reg registers_860[] =
2071 /* 119 */ R(eie), R(eid), R(nri), R(cmpa),
2072 /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr),
2073 /* 127 */ R(der), R(counta), R(countb), R(cmpe),
2074 /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1),
2075 /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst),
2076 /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr),
2077 /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr),
2078 /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc),
2079 /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap),
2080 /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn),
2081 /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1),
2082 /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1)
2085 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2086 for reading and writing RTCU and RTCL. However, how one reads and writes a
2087 register is the stub's problem. */
2088 static const struct reg registers_601[] =
2094 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2095 /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl)
2098 /* Motorola PowerPC 602. */
2099 static const struct reg registers_602[] =
2105 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2106 /* 123 */ R0, R(tcr), R(ibr), R(esassr),
2107 /* 127 */ R(sebr), R(ser), R(sp), R(lt)
2110 /* Motorola/IBM PowerPC 603 or 603e. */
2111 static const struct reg registers_603[] =
2117 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2118 /* 123 */ R0, R(dmiss), R(dcmp), R(hash1),
2119 /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa)
2122 /* Motorola PowerPC 604 or 604e. */
2123 static const struct reg registers_604[] =
2129 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2130 /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2),
2131 /* 127 */ R(sia), R(sda)
2134 /* Motorola/IBM PowerPC 750 or 740. */
2135 static const struct reg registers_750[] =
2141 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2142 /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2),
2143 /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4),
2144 /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia),
2145 /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr),
2146 /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3)
2150 /* Motorola PowerPC 7400. */
2151 static const struct reg registers_7400[] =
2153 /* gpr0-gpr31, fpr0-fpr31 */
2155 /* cr, lr, ctr, xer, fpscr */
2160 /* vr0-vr31, vrsave, vscr */
2162 /* FIXME? Add more registers? */
2165 /* Motorola e500. */
2166 static const struct reg registers_e500[] =
2169 /* cr, lr, ctr, xer, "" */
2173 R8(acc), R(spefscr),
2174 /* NOTE: Add new registers here the end of the raw register
2175 list and just before the first pseudo register. */
2177 PPC_GPRS_PSEUDO_REGS
2180 /* Information about a particular processor variant. */
2184 /* Name of this variant. */
2187 /* English description of the variant. */
2190 /* bfd_arch_info.arch corresponding to variant. */
2191 enum bfd_architecture arch;
2193 /* bfd_arch_info.mach corresponding to variant. */
2196 /* Number of real registers. */
2199 /* Number of pseudo registers. */
2202 /* Number of total registers (the sum of nregs and npregs). */
2205 /* Table of register names; registers[R] is the name of the register
2207 const struct reg *regs;
2210 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2213 num_registers (const struct reg *reg_list, int num_tot_regs)
2218 for (i = 0; i < num_tot_regs; i++)
2219 if (!reg_list[i].pseudo)
2226 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2231 for (i = 0; i < num_tot_regs; i++)
2232 if (reg_list[i].pseudo)
2238 /* Information in this table comes from the following web sites:
2239 IBM: http://www.chips.ibm.com:80/products/embedded/
2240 Motorola: http://www.mot.com/SPS/PowerPC/
2242 I'm sure I've got some of the variant descriptions not quite right.
2243 Please report any inaccuracies you find to GDB's maintainer.
2245 If you add entries to this table, please be sure to allow the new
2246 value as an argument to the --with-cpu flag, in configure.in. */
2248 static struct variant variants[] =
2251 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2252 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2254 {"power", "POWER user-level", bfd_arch_rs6000,
2255 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2257 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2258 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2260 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2261 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2263 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2264 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2266 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2267 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2269 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2270 604, -1, -1, tot_num_registers (registers_604),
2272 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2273 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2275 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2276 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2278 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2279 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2281 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2282 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2284 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2285 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2287 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2288 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2292 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2293 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2295 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2296 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2298 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2299 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2301 {"a35", "PowerPC A35", bfd_arch_powerpc,
2302 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2304 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2305 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2307 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2308 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2311 /* FIXME: I haven't checked the register sets of the following. */
2312 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2313 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2315 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2316 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2318 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2319 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2322 {0, 0, 0, 0, 0, 0, 0, 0}
2325 /* Initialize the number of registers and pseudo registers in each variant. */
2328 init_variants (void)
2332 for (v = variants; v->name; v++)
2335 v->nregs = num_registers (v->regs, v->num_tot_regs);
2336 if (v->npregs == -1)
2337 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2341 /* Return the variant corresponding to architecture ARCH and machine number
2342 MACH. If no such variant exists, return null. */
2344 static const struct variant *
2345 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2347 const struct variant *v;
2349 for (v = variants; v->name; v++)
2350 if (arch == v->arch && mach == v->mach)
2357 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2359 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2360 return print_insn_big_powerpc (memaddr, info);
2362 return print_insn_little_powerpc (memaddr, info);
2366 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2368 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2371 static struct frame_id
2372 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2374 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2376 frame_pc_unwind (next_frame));
2379 struct rs6000_frame_cache
2382 CORE_ADDR initial_sp;
2383 struct trad_frame_saved_reg *saved_regs;
2386 static struct rs6000_frame_cache *
2387 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2389 struct rs6000_frame_cache *cache;
2390 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2391 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2392 struct rs6000_framedata fdata;
2393 int wordsize = tdep->wordsize;
2395 if ((*this_cache) != NULL)
2396 return (*this_cache);
2397 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2398 (*this_cache) = cache;
2399 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2401 skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame),
2404 /* If there were any saved registers, figure out parent's stack
2406 /* The following is true only if the frame doesn't have a call to
2409 if (fdata.saved_fpr == 0
2410 && fdata.saved_gpr == 0
2411 && fdata.saved_vr == 0
2412 && fdata.saved_ev == 0
2413 && fdata.lr_offset == 0
2414 && fdata.cr_offset == 0
2415 && fdata.vr_offset == 0
2416 && fdata.ev_offset == 0)
2417 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2420 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2421 address of the current frame. Things might be easier if the
2422 ->frame pointed to the outer-most address of the frame. In
2423 the mean time, the address of the prev frame is used as the
2424 base address of this frame. */
2425 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2426 if (!fdata.frameless)
2427 /* Frameless really means stackless. */
2428 cache->base = read_memory_addr (cache->base, wordsize);
2430 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
2432 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2433 All fpr's from saved_fpr to fp31 are saved. */
2435 if (fdata.saved_fpr >= 0)
2438 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
2439 for (i = fdata.saved_fpr; i < 32; i++)
2441 cache->saved_regs[FP0_REGNUM + i].addr = fpr_addr;
2446 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2447 All gpr's from saved_gpr to gpr31 are saved. */
2449 if (fdata.saved_gpr >= 0)
2452 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
2453 for (i = fdata.saved_gpr; i < 32; i++)
2455 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2456 gpr_addr += wordsize;
2460 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2461 All vr's from saved_vr to vr31 are saved. */
2462 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2464 if (fdata.saved_vr >= 0)
2467 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2468 for (i = fdata.saved_vr; i < 32; i++)
2470 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2471 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2476 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2477 All vr's from saved_ev to ev31 are saved. ????? */
2478 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
2480 if (fdata.saved_ev >= 0)
2483 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
2484 for (i = fdata.saved_ev; i < 32; i++)
2486 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2487 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2488 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2493 /* If != 0, fdata.cr_offset is the offset from the frame that
2495 if (fdata.cr_offset != 0)
2496 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2498 /* If != 0, fdata.lr_offset is the offset from the frame that
2500 if (fdata.lr_offset != 0)
2501 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2502 /* The PC is found in the link register. */
2503 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
2505 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2506 holds the VRSAVE. */
2507 if (fdata.vrsave_offset != 0)
2508 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2510 if (fdata.alloca_reg < 0)
2511 /* If no alloca register used, then fi->frame is the value of the
2512 %sp for this frame, and it is good enough. */
2513 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2515 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
2522 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
2523 struct frame_id *this_id)
2525 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2527 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
2531 rs6000_frame_prev_register (struct frame_info *next_frame,
2533 int regnum, int *optimizedp,
2534 enum lval_type *lvalp, CORE_ADDR *addrp,
2535 int *realnump, void *valuep)
2537 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2539 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
2540 optimizedp, lvalp, addrp, realnump, valuep);
2543 static const struct frame_unwind rs6000_frame_unwind =
2546 rs6000_frame_this_id,
2547 rs6000_frame_prev_register
2550 static const struct frame_unwind *
2551 rs6000_frame_sniffer (struct frame_info *next_frame)
2553 return &rs6000_frame_unwind;
2559 rs6000_frame_base_address (struct frame_info *next_frame,
2562 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2564 return info->initial_sp;
2567 static const struct frame_base rs6000_frame_base = {
2568 &rs6000_frame_unwind,
2569 rs6000_frame_base_address,
2570 rs6000_frame_base_address,
2571 rs6000_frame_base_address
2574 static const struct frame_base *
2575 rs6000_frame_base_sniffer (struct frame_info *next_frame)
2577 return &rs6000_frame_base;
2580 /* Initialize the current architecture based on INFO. If possible, re-use an
2581 architecture from ARCHES, which is a list of architectures already created
2582 during this debugging session.
2584 Called e.g. at program startup, when reading a core file, and when reading
2587 static struct gdbarch *
2588 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2590 struct gdbarch *gdbarch;
2591 struct gdbarch_tdep *tdep;
2592 int wordsize, from_xcoff_exec, from_elf_exec, power, i, off;
2594 const struct variant *v;
2595 enum bfd_architecture arch;
2601 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
2602 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
2604 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
2605 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2607 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2609 /* Check word size. If INFO is from a binary file, infer it from
2610 that, else choose a likely default. */
2611 if (from_xcoff_exec)
2613 if (bfd_xcoff_is_xcoff64 (info.abfd))
2618 else if (from_elf_exec)
2620 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
2627 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
2628 wordsize = info.bfd_arch_info->bits_per_word /
2629 info.bfd_arch_info->bits_per_byte;
2634 /* Find a candidate among extant architectures. */
2635 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2637 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2639 /* Word size in the various PowerPC bfd_arch_info structs isn't
2640 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
2641 separate word size check. */
2642 tdep = gdbarch_tdep (arches->gdbarch);
2643 if (tdep && tdep->wordsize == wordsize)
2644 return arches->gdbarch;
2647 /* None found, create a new architecture from INFO, whose bfd_arch_info
2648 validity depends on the source:
2649 - executable useless
2650 - rs6000_host_arch() good
2652 - "set arch" trust blindly
2653 - GDB startup useless but harmless */
2655 if (!from_xcoff_exec)
2657 arch = info.bfd_arch_info->arch;
2658 mach = info.bfd_arch_info->mach;
2662 arch = bfd_arch_powerpc;
2663 bfd_default_set_arch_mach (&abfd, arch, 0);
2664 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2665 mach = info.bfd_arch_info->mach;
2667 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2668 tdep->wordsize = wordsize;
2670 /* For e500 executables, the apuinfo section is of help here. Such
2671 section contains the identifier and revision number of each
2672 Application-specific Processing Unit that is present on the
2673 chip. The content of the section is determined by the assembler
2674 which looks at each instruction and determines which unit (and
2675 which version of it) can execute it. In our case we just look for
2676 the existance of the section. */
2680 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
2683 arch = info.bfd_arch_info->arch;
2684 mach = bfd_mach_ppc_e500;
2685 bfd_default_set_arch_mach (&abfd, arch, mach);
2686 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2690 gdbarch = gdbarch_alloc (&info, tdep);
2691 power = arch == bfd_arch_rs6000;
2693 /* Initialize the number of real and pseudo registers in each variant. */
2696 /* Choose variant. */
2697 v = find_variant_by_arch (arch, mach);
2701 tdep->regs = v->regs;
2703 tdep->ppc_gp0_regnum = 0;
2704 tdep->ppc_toc_regnum = 2;
2705 tdep->ppc_ps_regnum = 65;
2706 tdep->ppc_cr_regnum = 66;
2707 tdep->ppc_lr_regnum = 67;
2708 tdep->ppc_ctr_regnum = 68;
2709 tdep->ppc_xer_regnum = 69;
2710 if (v->mach == bfd_mach_ppc_601)
2711 tdep->ppc_mq_regnum = 124;
2713 tdep->ppc_mq_regnum = 70;
2715 tdep->ppc_mq_regnum = -1;
2716 tdep->ppc_fpscr_regnum = power ? 71 : 70;
2718 set_gdbarch_pc_regnum (gdbarch, 64);
2719 set_gdbarch_sp_regnum (gdbarch, 1);
2720 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
2721 if (sysv_abi && wordsize == 8)
2722 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
2723 else if (sysv_abi && wordsize == 4)
2724 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
2727 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
2728 set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value);
2731 if (v->arch == bfd_arch_powerpc)
2735 tdep->ppc_vr0_regnum = 71;
2736 tdep->ppc_vrsave_regnum = 104;
2737 tdep->ppc_ev0_regnum = -1;
2738 tdep->ppc_ev31_regnum = -1;
2740 case bfd_mach_ppc_7400:
2741 tdep->ppc_vr0_regnum = 119;
2742 tdep->ppc_vrsave_regnum = 152;
2743 tdep->ppc_ev0_regnum = -1;
2744 tdep->ppc_ev31_regnum = -1;
2746 case bfd_mach_ppc_e500:
2747 tdep->ppc_gp0_regnum = 41;
2748 tdep->ppc_toc_regnum = -1;
2749 tdep->ppc_ps_regnum = 1;
2750 tdep->ppc_cr_regnum = 2;
2751 tdep->ppc_lr_regnum = 3;
2752 tdep->ppc_ctr_regnum = 4;
2753 tdep->ppc_xer_regnum = 5;
2754 tdep->ppc_ev0_regnum = 7;
2755 tdep->ppc_ev31_regnum = 38;
2756 set_gdbarch_pc_regnum (gdbarch, 0);
2757 set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
2758 set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
2759 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
2760 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
2763 tdep->ppc_vr0_regnum = -1;
2764 tdep->ppc_vrsave_regnum = -1;
2765 tdep->ppc_ev0_regnum = -1;
2766 tdep->ppc_ev31_regnum = -1;
2770 /* Sanity check on registers. */
2771 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
2773 /* Set lr_frame_offset. */
2775 tdep->lr_frame_offset = 16;
2777 tdep->lr_frame_offset = 4;
2779 tdep->lr_frame_offset = 8;
2781 /* Calculate byte offsets in raw register array. */
2782 tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int));
2783 for (i = off = 0; i < v->num_tot_regs; i++)
2785 tdep->regoff[i] = off;
2786 off += regsize (v->regs + i, wordsize);
2789 /* Select instruction printer. */
2791 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
2793 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
2795 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2797 set_gdbarch_num_regs (gdbarch, v->nregs);
2798 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
2799 set_gdbarch_register_name (gdbarch, rs6000_register_name);
2800 set_gdbarch_deprecated_register_size (gdbarch, wordsize);
2801 set_gdbarch_deprecated_register_bytes (gdbarch, off);
2802 set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte);
2803 set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size);
2804 set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type);
2806 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2807 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2808 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2809 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2810 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2811 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2812 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2814 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
2816 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2817 set_gdbarch_char_signed (gdbarch, 0);
2819 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
2820 if (sysv_abi && wordsize == 8)
2822 set_gdbarch_frame_red_zone_size (gdbarch, 288);
2823 else if (!sysv_abi && wordsize == 4)
2824 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
2825 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
2826 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
2828 set_gdbarch_frame_red_zone_size (gdbarch, 224);
2830 set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible);
2831 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual);
2832 set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw);
2833 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
2834 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
2835 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
2836 is correct for the SysV ABI when the wordsize is 8, but I'm also
2837 fairly certain that ppc_sysv_abi_push_arguments() will give even
2838 worse results since it only works for 32-bit code. So, for the moment,
2839 we're better off calling rs6000_push_arguments() since it works for
2840 64-bit code. At some point in the future, this matter needs to be
2842 if (sysv_abi && wordsize == 4)
2843 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
2844 else if (sysv_abi && wordsize == 8)
2845 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
2847 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
2849 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
2851 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
2852 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2853 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
2855 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
2856 for the descriptor and ".FN" for the entry-point -- a user
2857 specifying "break FN" will unexpectedly end up with a breakpoint
2858 on the descriptor and not the function. This architecture method
2859 transforms any breakpoints on descriptors into breakpoints on the
2860 corresponding entry point. */
2861 if (sysv_abi && wordsize == 8)
2862 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
2864 /* Not sure on this. FIXMEmgo */
2865 set_gdbarch_frame_args_skip (gdbarch, 8);
2868 set_gdbarch_use_struct_convention (gdbarch,
2869 rs6000_use_struct_convention);
2873 /* Handle RS/6000 function pointers (which are really function
2875 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
2876 rs6000_convert_from_func_ptr_addr);
2879 /* Helpers for function argument information. */
2880 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
2882 /* Hook in ABI-specific overrides, if they have been registered. */
2883 gdbarch_init_osabi (info, gdbarch);
2887 case GDB_OSABI_NETBSD_AOUT:
2888 case GDB_OSABI_NETBSD_ELF:
2889 case GDB_OSABI_UNKNOWN:
2890 case GDB_OSABI_LINUX:
2891 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
2892 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
2893 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
2894 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
2897 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
2898 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2900 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
2901 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
2902 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
2903 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
2906 if (from_xcoff_exec)
2908 /* NOTE: jimix/2003-06-09: This test should really check for
2909 GDB_OSABI_AIX when that is defined and becomes
2910 available. (Actually, once things are properly split apart,
2911 the test goes away.) */
2912 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
2913 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
2920 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2922 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2927 /* FIXME: Dump gdbarch_tdep. */
2930 static struct cmd_list_element *info_powerpc_cmdlist = NULL;
2933 rs6000_info_powerpc_command (char *args, int from_tty)
2935 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
2938 /* Initialization code. */
2940 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
2943 _initialize_rs6000_tdep (void)
2945 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
2946 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
2948 /* Add root prefix command for "info powerpc" commands */
2949 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
2950 "Various POWERPC info specific commands.",
2951 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);