1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
52 #include "solib-svr4.h"
55 #include "gdb_assert.h"
58 #include "trad-frame.h"
59 #include "frame-unwind.h"
60 #include "frame-base.h"
62 #include "reggroups.h"
63 #include "rs6000-tdep.h"
65 /* If the kernel has to deliver a signal, it pushes a sigcontext
66 structure on the stack and then calls the signal handler, passing
67 the address of the sigcontext in an argument register. Usually
68 the signal handler doesn't save this register, so we have to
69 access the sigcontext structure via an offset from the signal handler
71 The following constants were determined by experimentation on AIX 3.2. */
72 #define SIG_FRAME_PC_OFFSET 96
73 #define SIG_FRAME_LR_OFFSET 108
74 #define SIG_FRAME_FP_OFFSET 284
76 /* To be used by skip_prologue. */
78 struct rs6000_framedata
80 int offset; /* total size of frame --- the distance
81 by which we decrement sp to allocate
83 int saved_gpr; /* smallest # of saved gpr */
84 int saved_fpr; /* smallest # of saved fpr */
85 int saved_vr; /* smallest # of saved vr */
86 int saved_ev; /* smallest # of saved ev */
87 int alloca_reg; /* alloca register number (frame ptr) */
88 char frameless; /* true if frameless functions. */
89 char nosavedpc; /* true if pc not saved. */
90 int gpr_offset; /* offset of saved gprs from prev sp */
91 int fpr_offset; /* offset of saved fprs from prev sp */
92 int vr_offset; /* offset of saved vrs from prev sp */
93 int ev_offset; /* offset of saved evs from prev sp */
94 int lr_offset; /* offset of saved lr */
95 int cr_offset; /* offset of saved cr */
96 int vrsave_offset; /* offset of saved vrsave register */
99 /* Description of a single register. */
103 char *name; /* name of register */
104 unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */
105 unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */
106 unsigned char fpr; /* whether register is floating-point */
107 unsigned char pseudo; /* whether register is pseudo */
108 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
109 This is an ISA SPR number, not a GDB
113 /* Hook for determining the TOC address when calling functions in the
114 inferior under AIX. The initialization code in rs6000-nat.c sets
115 this hook to point to find_toc_address. */
117 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
119 /* Hook to set the current architecture when starting a child process.
120 rs6000-nat.c sets this. */
122 void (*rs6000_set_host_arch_hook) (int) = NULL;
124 /* Static function prototypes */
126 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
128 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
129 struct rs6000_framedata *);
131 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
133 altivec_register_p (int regno)
135 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
136 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
139 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
143 /* Return true if REGNO is an SPE register, false otherwise. */
145 spe_register_p (int regno)
147 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
149 /* Is it a reference to EV0 -- EV31, and do we have those? */
150 if (tdep->ppc_ev0_regnum >= 0
151 && tdep->ppc_ev31_regnum >= 0
152 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
155 /* Is it a reference to one of the raw upper GPR halves? */
156 if (tdep->ppc_ev0_upper_regnum >= 0
157 && tdep->ppc_ev0_upper_regnum <= regno
158 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
161 /* Is it a reference to the 64-bit accumulator, and do we have that? */
162 if (tdep->ppc_acc_regnum >= 0
163 && tdep->ppc_acc_regnum == regno)
166 /* Is it a reference to the SPE floating-point status and control register,
167 and do we have that? */
168 if (tdep->ppc_spefscr_regnum >= 0
169 && tdep->ppc_spefscr_regnum == regno)
176 /* Return non-zero if the architecture described by GDBARCH has
177 floating-point registers (f0 --- f31 and fpscr). */
179 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
181 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
183 return (tdep->ppc_fp0_regnum >= 0
184 && tdep->ppc_fpscr_regnum >= 0);
188 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
191 This is a helper function for init_sim_regno_table, constructing
192 the table mapping GDB register numbers to sim register numbers; we
193 initialize every element in that table to -1 before we start
196 set_sim_regno (int *table, int gdb_regno, int sim_regno)
198 /* Make sure we don't try to assign any given GDB register a sim
199 register number more than once. */
200 gdb_assert (table[gdb_regno] == -1);
201 table[gdb_regno] = sim_regno;
205 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
206 numbers to simulator register numbers, based on the values placed
207 in the ARCH->tdep->ppc_foo_regnum members. */
209 init_sim_regno_table (struct gdbarch *arch)
211 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
212 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
213 const struct reg *regs = tdep->regs;
214 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
217 /* Presume that all registers not explicitly mentioned below are
218 unavailable from the sim. */
219 for (i = 0; i < total_regs; i++)
222 /* General-purpose registers. */
223 for (i = 0; i < ppc_num_gprs; i++)
224 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
226 /* Floating-point registers. */
227 if (tdep->ppc_fp0_regnum >= 0)
228 for (i = 0; i < ppc_num_fprs; i++)
229 set_sim_regno (sim_regno,
230 tdep->ppc_fp0_regnum + i,
231 sim_ppc_f0_regnum + i);
232 if (tdep->ppc_fpscr_regnum >= 0)
233 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
235 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
236 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
237 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
239 /* Segment registers. */
240 if (tdep->ppc_sr0_regnum >= 0)
241 for (i = 0; i < ppc_num_srs; i++)
242 set_sim_regno (sim_regno,
243 tdep->ppc_sr0_regnum + i,
244 sim_ppc_sr0_regnum + i);
246 /* Altivec registers. */
247 if (tdep->ppc_vr0_regnum >= 0)
249 for (i = 0; i < ppc_num_vrs; i++)
250 set_sim_regno (sim_regno,
251 tdep->ppc_vr0_regnum + i,
252 sim_ppc_vr0_regnum + i);
254 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
255 we can treat this more like the other cases. */
256 set_sim_regno (sim_regno,
257 tdep->ppc_vr0_regnum + ppc_num_vrs,
258 sim_ppc_vscr_regnum);
260 /* vsave is a special-purpose register, so the code below handles it. */
262 /* SPE APU (E500) registers. */
263 if (tdep->ppc_ev0_regnum >= 0)
264 for (i = 0; i < ppc_num_gprs; i++)
265 set_sim_regno (sim_regno,
266 tdep->ppc_ev0_regnum + i,
267 sim_ppc_ev0_regnum + i);
268 if (tdep->ppc_ev0_upper_regnum >= 0)
269 for (i = 0; i < ppc_num_gprs; i++)
270 set_sim_regno (sim_regno,
271 tdep->ppc_ev0_upper_regnum + i,
272 sim_ppc_rh0_regnum + i);
273 if (tdep->ppc_acc_regnum >= 0)
274 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
275 /* spefscr is a special-purpose register, so the code below handles it. */
277 /* Now handle all special-purpose registers. Verify that they
278 haven't mistakenly been assigned numbers by any of the above
280 for (i = 0; i < total_regs; i++)
281 if (regs[i].spr_num >= 0)
282 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
284 /* Drop the initialized array into place. */
285 tdep->sim_regno = sim_regno;
289 /* Given a GDB register number REG, return the corresponding SIM
292 rs6000_register_sim_regno (int reg)
294 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
297 gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
298 sim_regno = tdep->sim_regno[reg];
303 return LEGACY_SIM_REGNO_IGNORE;
308 /* Register set support functions. */
311 ppc_supply_reg (struct regcache *regcache, int regnum,
312 const gdb_byte *regs, size_t offset)
314 if (regnum != -1 && offset != -1)
315 regcache_raw_supply (regcache, regnum, regs + offset);
319 ppc_collect_reg (const struct regcache *regcache, int regnum,
320 gdb_byte *regs, size_t offset)
322 if (regnum != -1 && offset != -1)
323 regcache_raw_collect (regcache, regnum, regs + offset);
326 /* Supply register REGNUM in the general-purpose register set REGSET
327 from the buffer specified by GREGS and LEN to register cache
328 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
331 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
332 int regnum, const void *gregs, size_t len)
334 struct gdbarch *gdbarch = get_regcache_arch (regcache);
335 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
336 const struct ppc_reg_offsets *offsets = regset->descr;
340 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
341 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
344 if (regnum == -1 || regnum == i)
345 ppc_supply_reg (regcache, i, gregs, offset);
348 if (regnum == -1 || regnum == PC_REGNUM)
349 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
350 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
351 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
352 gregs, offsets->ps_offset);
353 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
354 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
355 gregs, offsets->cr_offset);
356 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
357 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
358 gregs, offsets->lr_offset);
359 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
360 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
361 gregs, offsets->ctr_offset);
362 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
363 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
364 gregs, offsets->cr_offset);
365 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
366 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
369 /* Supply register REGNUM in the floating-point register set REGSET
370 from the buffer specified by FPREGS and LEN to register cache
371 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
374 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
375 int regnum, const void *fpregs, size_t len)
377 struct gdbarch *gdbarch = get_regcache_arch (regcache);
378 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
379 const struct ppc_reg_offsets *offsets = regset->descr;
383 gdb_assert (ppc_floating_point_unit_p (gdbarch));
385 offset = offsets->f0_offset;
386 for (i = tdep->ppc_fp0_regnum;
387 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
390 if (regnum == -1 || regnum == i)
391 ppc_supply_reg (regcache, i, fpregs, offset);
394 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
395 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
396 fpregs, offsets->fpscr_offset);
399 /* Collect register REGNUM in the general-purpose register set
400 REGSET. from register cache REGCACHE into the buffer specified by
401 GREGS and LEN. If REGNUM is -1, do this for all registers in
405 ppc_collect_gregset (const struct regset *regset,
406 const struct regcache *regcache,
407 int regnum, void *gregs, size_t len)
409 struct gdbarch *gdbarch = get_regcache_arch (regcache);
410 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
411 const struct ppc_reg_offsets *offsets = regset->descr;
415 offset = offsets->r0_offset;
416 for (i = tdep->ppc_gp0_regnum;
417 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
420 if (regnum == -1 || regnum == i)
421 ppc_collect_reg (regcache, i, gregs, offset);
424 if (regnum == -1 || regnum == PC_REGNUM)
425 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
426 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
427 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
428 gregs, offsets->ps_offset);
429 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
430 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
431 gregs, offsets->cr_offset);
432 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
433 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
434 gregs, offsets->lr_offset);
435 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
436 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
437 gregs, offsets->ctr_offset);
438 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
439 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
440 gregs, offsets->xer_offset);
441 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
442 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
443 gregs, offsets->mq_offset);
446 /* Collect register REGNUM in the floating-point register set
447 REGSET. from register cache REGCACHE into the buffer specified by
448 FPREGS and LEN. If REGNUM is -1, do this for all registers in
452 ppc_collect_fpregset (const struct regset *regset,
453 const struct regcache *regcache,
454 int regnum, void *fpregs, size_t len)
456 struct gdbarch *gdbarch = get_regcache_arch (regcache);
457 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
458 const struct ppc_reg_offsets *offsets = regset->descr;
462 gdb_assert (ppc_floating_point_unit_p (gdbarch));
464 offset = offsets->f0_offset;
465 for (i = tdep->ppc_fp0_regnum;
466 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
469 if (regnum == -1 || regnum == i)
470 ppc_collect_reg (regcache, i, fpregs, offset);
473 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
474 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
475 fpregs, offsets->fpscr_offset);
479 /* Read a LEN-byte address from debugged memory address MEMADDR. */
482 read_memory_addr (CORE_ADDR memaddr, int len)
484 return read_memory_unsigned_integer (memaddr, len);
488 rs6000_skip_prologue (CORE_ADDR pc)
490 struct rs6000_framedata frame;
491 pc = skip_prologue (pc, 0, &frame);
496 insn_changes_sp_or_jumps (unsigned long insn)
498 int opcode = (insn >> 26) & 0x03f;
499 int sd = (insn >> 21) & 0x01f;
500 int a = (insn >> 16) & 0x01f;
501 int subcode = (insn >> 1) & 0x3ff;
503 /* Changes the stack pointer. */
505 /* NOTE: There are many ways to change the value of a given register.
506 The ways below are those used when the register is R1, the SP,
507 in a funtion's epilogue. */
509 if (opcode == 31 && subcode == 444 && a == 1)
510 return 1; /* mr R1,Rn */
511 if (opcode == 14 && sd == 1)
512 return 1; /* addi R1,Rn,simm */
513 if (opcode == 58 && sd == 1)
514 return 1; /* ld R1,ds(Rn) */
516 /* Transfers control. */
522 if (opcode == 19 && subcode == 16)
524 if (opcode == 19 && subcode == 528)
525 return 1; /* bcctr */
530 /* Return true if we are in the function's epilogue, i.e. after the
531 instruction that destroyed the function's stack frame.
533 1) scan forward from the point of execution:
534 a) If you find an instruction that modifies the stack pointer
535 or transfers control (except a return), execution is not in
537 b) Stop scanning if you find a return instruction or reach the
538 end of the function or reach the hard limit for the size of
540 2) scan backward from the point of execution:
541 a) If you find an instruction that modifies the stack pointer,
542 execution *is* in an epilogue, return.
543 b) Stop scanning if you reach an instruction that transfers
544 control or the beginning of the function or reach the hard
545 limit for the size of an epilogue. */
548 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
550 bfd_byte insn_buf[PPC_INSN_SIZE];
551 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
553 struct frame_info *curfrm;
555 /* Find the search limits based on function boundaries and hard limit. */
557 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
560 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
561 if (epilogue_start < func_start) epilogue_start = func_start;
563 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
564 if (epilogue_end > func_end) epilogue_end = func_end;
566 curfrm = get_current_frame ();
568 /* Scan forward until next 'blr'. */
570 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
572 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
574 insn = extract_signed_integer (insn_buf, PPC_INSN_SIZE);
575 if (insn == 0x4e800020)
577 if (insn_changes_sp_or_jumps (insn))
581 /* Scan backward until adjustment to stack pointer (R1). */
583 for (scan_pc = pc - PPC_INSN_SIZE;
584 scan_pc >= epilogue_start;
585 scan_pc -= PPC_INSN_SIZE)
587 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
589 insn = extract_signed_integer (insn_buf, PPC_INSN_SIZE);
590 if (insn_changes_sp_or_jumps (insn))
598 /* Fill in fi->saved_regs */
600 struct frame_extra_info
602 /* Functions calling alloca() change the value of the stack
603 pointer. We need to use initial stack pointer (which is saved in
604 r31 by gcc) in such cases. If a compiler emits traceback table,
605 then we should use the alloca register specified in traceback
607 CORE_ADDR initial_sp; /* initial stack pointer. */
610 /* Get the ith function argument for the current function. */
612 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
615 return get_frame_register_unsigned (frame, 3 + argi);
618 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
621 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
628 absolute = (int) ((instr >> 1) & 1);
633 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
637 dest = pc + immediate;
641 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
645 dest = pc + immediate;
649 ext_op = (instr >> 1) & 0x3ff;
651 if (ext_op == 16) /* br conditional register */
653 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
655 /* If we are about to return from a signal handler, dest is
656 something like 0x3c90. The current frame is a signal handler
657 caller frame, upon completion of the sigreturn system call
658 execution will return to the saved PC in the frame. */
659 if (dest < TEXT_SEGMENT_BASE)
661 struct frame_info *fi;
663 fi = get_current_frame ();
665 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
666 gdbarch_tdep (current_gdbarch)->wordsize);
670 else if (ext_op == 528) /* br cond to count reg */
672 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
674 /* If we are about to execute a system call, dest is something
675 like 0x22fc or 0x3b00. Upon completion the system call
676 will return to the address in the link register. */
677 if (dest < TEXT_SEGMENT_BASE)
678 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
687 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
691 /* Sequence of bytes for breakpoint instruction. */
693 const static unsigned char *
694 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
696 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
697 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
699 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
700 return big_breakpoint;
702 return little_breakpoint;
706 /* AIX does not support PT_STEP. Simulate it. */
709 rs6000_software_single_step (enum target_signal signal,
710 int insert_breakpoints_p)
714 const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
720 if (insert_breakpoints_p)
724 insn = read_memory_integer (loc, 4);
726 breaks[0] = loc + breakp_sz;
728 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
730 /* Don't put two breakpoints on the same address. */
731 if (breaks[1] == breaks[0])
734 for (ii = 0; ii < 2; ++ii)
736 /* ignore invalid breakpoint. */
737 if (breaks[ii] == -1)
739 insert_single_step_breakpoint (breaks[ii]);
743 remove_single_step_breakpoints ();
745 errno = 0; /* FIXME, don't ignore errors! */
746 /* What errors? {read,write}_memory call error(). */
750 /* return pc value after skipping a function prologue and also return
751 information about a function frame.
753 in struct rs6000_framedata fdata:
754 - frameless is TRUE, if function does not have a frame.
755 - nosavedpc is TRUE, if function does not save %pc value in its frame.
756 - offset is the initial size of this stack frame --- the amount by
757 which we decrement the sp to allocate the frame.
758 - saved_gpr is the number of the first saved gpr.
759 - saved_fpr is the number of the first saved fpr.
760 - saved_vr is the number of the first saved vr.
761 - saved_ev is the number of the first saved ev.
762 - alloca_reg is the number of the register used for alloca() handling.
764 - gpr_offset is the offset of the first saved gpr from the previous frame.
765 - fpr_offset is the offset of the first saved fpr from the previous frame.
766 - vr_offset is the offset of the first saved vr from the previous frame.
767 - ev_offset is the offset of the first saved ev from the previous frame.
768 - lr_offset is the offset of the saved lr
769 - cr_offset is the offset of the saved cr
770 - vrsave_offset is the offset of the saved vrsave register
773 #define SIGNED_SHORT(x) \
774 ((sizeof (short) == 2) \
775 ? ((int)(short)(x)) \
776 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
778 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
780 /* Limit the number of skipped non-prologue instructions, as the examining
781 of the prologue is expensive. */
782 static int max_skip_non_prologue_insns = 10;
784 /* Given PC representing the starting address of a function, and
785 LIM_PC which is the (sloppy) limit to which to scan when looking
786 for a prologue, attempt to further refine this limit by using
787 the line data in the symbol table. If successful, a better guess
788 on where the prologue ends is returned, otherwise the previous
789 value of lim_pc is returned. */
791 /* FIXME: cagney/2004-02-14: This function and logic have largely been
792 superseded by skip_prologue_using_sal. */
795 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
797 struct symtab_and_line prologue_sal;
799 prologue_sal = find_pc_line (pc, 0);
800 if (prologue_sal.line != 0)
803 CORE_ADDR addr = prologue_sal.end;
805 /* Handle the case in which compiler's optimizer/scheduler
806 has moved instructions into the prologue. We scan ahead
807 in the function looking for address ranges whose corresponding
808 line number is less than or equal to the first one that we
809 found for the function. (It can be less than when the
810 scheduler puts a body instruction before the first prologue
812 for (i = 2 * max_skip_non_prologue_insns;
813 i > 0 && (lim_pc == 0 || addr < lim_pc);
816 struct symtab_and_line sal;
818 sal = find_pc_line (addr, 0);
821 if (sal.line <= prologue_sal.line
822 && sal.symtab == prologue_sal.symtab)
829 if (lim_pc == 0 || prologue_sal.end < lim_pc)
830 lim_pc = prologue_sal.end;
835 /* Return nonzero if the given instruction OP can be part of the prologue
836 of a function and saves a parameter on the stack. FRAMEP should be
837 set if one of the previous instructions in the function has set the
841 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
843 /* Move parameters from argument registers to temporary register. */
844 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
846 /* Rx must be scratch register r0. */
847 const int rx_regno = (op >> 16) & 31;
848 /* Ry: Only r3 - r10 are used for parameter passing. */
849 const int ry_regno = GET_SRC_REG (op);
851 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
853 *r0_contains_arg = 1;
860 /* Save a General Purpose Register on stack. */
862 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
863 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
865 /* Rx: Only r3 - r10 are used for parameter passing. */
866 const int rx_regno = GET_SRC_REG (op);
868 return (rx_regno >= 3 && rx_regno <= 10);
871 /* Save a General Purpose Register on stack via the Frame Pointer. */
874 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
875 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
876 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
878 /* Rx: Usually, only r3 - r10 are used for parameter passing.
879 However, the compiler sometimes uses r0 to hold an argument. */
880 const int rx_regno = GET_SRC_REG (op);
882 return ((rx_regno >= 3 && rx_regno <= 10)
883 || (rx_regno == 0 && *r0_contains_arg));
886 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
888 /* Only f2 - f8 are used for parameter passing. */
889 const int src_regno = GET_SRC_REG (op);
891 return (src_regno >= 2 && src_regno <= 8);
894 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
896 /* Only f2 - f8 are used for parameter passing. */
897 const int src_regno = GET_SRC_REG (op);
899 return (src_regno >= 2 && src_regno <= 8);
902 /* Not an insn that saves a parameter on stack. */
907 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
909 CORE_ADDR orig_pc = pc;
910 CORE_ADDR last_prologue_pc = pc;
911 CORE_ADDR li_found_pc = 0;
915 long vr_saved_offset = 0;
924 int minimal_toc_loaded = 0;
925 int prev_insn_was_prologue_insn = 1;
926 int num_skip_non_prologue_insns = 0;
927 int r0_contains_arg = 0;
928 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
929 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
931 /* Attempt to find the end of the prologue when no limit is specified.
932 Note that refine_prologue_limit() has been written so that it may
933 be used to "refine" the limits of non-zero PC values too, but this
934 is only safe if we 1) trust the line information provided by the
935 compiler and 2) iterate enough to actually find the end of the
938 It may become a good idea at some point (for both performance and
939 accuracy) to unconditionally call refine_prologue_limit(). But,
940 until we can make a clear determination that this is beneficial,
941 we'll play it safe and only use it to obtain a limit when none
942 has been specified. */
944 lim_pc = refine_prologue_limit (pc, lim_pc);
946 memset (fdata, 0, sizeof (struct rs6000_framedata));
947 fdata->saved_gpr = -1;
948 fdata->saved_fpr = -1;
949 fdata->saved_vr = -1;
950 fdata->saved_ev = -1;
951 fdata->alloca_reg = -1;
952 fdata->frameless = 1;
953 fdata->nosavedpc = 1;
957 /* Sometimes it isn't clear if an instruction is a prologue
958 instruction or not. When we encounter one of these ambiguous
959 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
960 Otherwise, we'll assume that it really is a prologue instruction. */
961 if (prev_insn_was_prologue_insn)
962 last_prologue_pc = pc;
964 /* Stop scanning if we've hit the limit. */
965 if (lim_pc != 0 && pc >= lim_pc)
968 prev_insn_was_prologue_insn = 1;
970 /* Fetch the instruction and convert it to an integer. */
971 if (target_read_memory (pc, buf, 4))
973 op = extract_signed_integer (buf, 4);
975 if ((op & 0xfc1fffff) == 0x7c0802a6)
977 /* Since shared library / PIC code, which needs to get its
978 address at runtime, can appear to save more than one link
992 remember just the first one, but skip over additional
995 lr_reg = (op & 0x03e00000);
1000 else if ((op & 0xfc1fffff) == 0x7c000026)
1002 cr_reg = (op & 0x03e00000);
1004 r0_contains_arg = 0;
1008 else if ((op & 0xfc1f0000) == 0xd8010000)
1009 { /* stfd Rx,NUM(r1) */
1010 reg = GET_SRC_REG (op);
1011 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1013 fdata->saved_fpr = reg;
1014 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1019 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1020 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1021 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1022 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1025 reg = GET_SRC_REG (op);
1026 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1028 fdata->saved_gpr = reg;
1029 if ((op & 0xfc1f0003) == 0xf8010000)
1031 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1036 else if ((op & 0xffff0000) == 0x60000000)
1039 /* Allow nops in the prologue, but do not consider them to
1040 be part of the prologue unless followed by other prologue
1042 prev_insn_was_prologue_insn = 0;
1046 else if ((op & 0xffff0000) == 0x3c000000)
1047 { /* addis 0,0,NUM, used
1048 for >= 32k frames */
1049 fdata->offset = (op & 0x0000ffff) << 16;
1050 fdata->frameless = 0;
1051 r0_contains_arg = 0;
1055 else if ((op & 0xffff0000) == 0x60000000)
1056 { /* ori 0,0,NUM, 2nd ha
1057 lf of >= 32k frames */
1058 fdata->offset |= (op & 0x0000ffff);
1059 fdata->frameless = 0;
1060 r0_contains_arg = 0;
1064 else if (lr_reg >= 0 &&
1065 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1066 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1067 /* stw Rx, NUM(r1) */
1068 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1069 /* stwu Rx, NUM(r1) */
1070 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1071 { /* where Rx == lr */
1072 fdata->lr_offset = offset;
1073 fdata->nosavedpc = 0;
1074 /* Invalidate lr_reg, but don't set it to -1.
1075 That would mean that it had never been set. */
1077 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1078 (op & 0xfc000000) == 0x90000000) /* stw */
1080 /* Does not update r1, so add displacement to lr_offset. */
1081 fdata->lr_offset += SIGNED_SHORT (op);
1086 else if (cr_reg >= 0 &&
1087 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1088 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1089 /* stw Rx, NUM(r1) */
1090 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1091 /* stwu Rx, NUM(r1) */
1092 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1093 { /* where Rx == cr */
1094 fdata->cr_offset = offset;
1095 /* Invalidate cr_reg, but don't set it to -1.
1096 That would mean that it had never been set. */
1098 if ((op & 0xfc000003) == 0xf8000000 ||
1099 (op & 0xfc000000) == 0x90000000)
1101 /* Does not update r1, so add displacement to cr_offset. */
1102 fdata->cr_offset += SIGNED_SHORT (op);
1107 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1109 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1110 prediction bits. If the LR has already been saved, we can
1114 else if (op == 0x48000005)
1120 else if (op == 0x48000004)
1125 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1126 in V.4 -mminimal-toc */
1127 (op & 0xffff0000) == 0x3bde0000)
1128 { /* addi 30,30,foo@l */
1132 else if ((op & 0xfc000001) == 0x48000001)
1136 fdata->frameless = 0;
1137 /* Don't skip over the subroutine call if it is not within
1138 the first three instructions of the prologue and either
1139 we have no line table information or the line info tells
1140 us that the subroutine call is not part of the line
1141 associated with the prologue. */
1142 if ((pc - orig_pc) > 8)
1144 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1145 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1147 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1151 op = read_memory_integer (pc + 4, 4);
1153 /* At this point, make sure this is not a trampoline
1154 function (a function that simply calls another functions,
1155 and nothing else). If the next is not a nop, this branch
1156 was part of the function prologue. */
1158 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1159 break; /* don't skip over
1164 /* update stack pointer */
1165 else if ((op & 0xfc1f0000) == 0x94010000)
1166 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1167 fdata->frameless = 0;
1168 fdata->offset = SIGNED_SHORT (op);
1169 offset = fdata->offset;
1172 else if ((op & 0xfc1f016a) == 0x7c01016e)
1173 { /* stwux rX,r1,rY */
1174 /* no way to figure out what r1 is going to be */
1175 fdata->frameless = 0;
1176 offset = fdata->offset;
1179 else if ((op & 0xfc1f0003) == 0xf8010001)
1180 { /* stdu rX,NUM(r1) */
1181 fdata->frameless = 0;
1182 fdata->offset = SIGNED_SHORT (op & ~3UL);
1183 offset = fdata->offset;
1186 else if ((op & 0xfc1f016a) == 0x7c01016a)
1187 { /* stdux rX,r1,rY */
1188 /* no way to figure out what r1 is going to be */
1189 fdata->frameless = 0;
1190 offset = fdata->offset;
1193 /* Load up minimal toc pointer */
1194 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1195 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1196 && !minimal_toc_loaded)
1198 minimal_toc_loaded = 1;
1201 /* move parameters from argument registers to local variable
1204 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1205 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1206 (((op >> 21) & 31) <= 10) &&
1207 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1211 /* store parameters in stack */
1213 /* Move parameters from argument registers to temporary register. */
1214 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1218 /* Set up frame pointer */
1220 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1221 || op == 0x7c3f0b78)
1223 fdata->frameless = 0;
1225 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1228 /* Another way to set up the frame pointer. */
1230 else if ((op & 0xfc1fffff) == 0x38010000)
1231 { /* addi rX, r1, 0x0 */
1232 fdata->frameless = 0;
1234 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1235 + ((op & ~0x38010000) >> 21));
1238 /* AltiVec related instructions. */
1239 /* Store the vrsave register (spr 256) in another register for
1240 later manipulation, or load a register into the vrsave
1241 register. 2 instructions are used: mfvrsave and
1242 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1243 and mtspr SPR256, Rn. */
1244 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1245 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1246 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1248 vrsave_reg = GET_SRC_REG (op);
1251 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1255 /* Store the register where vrsave was saved to onto the stack:
1256 rS is the register where vrsave was stored in a previous
1258 /* 100100 sssss 00001 dddddddd dddddddd */
1259 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1261 if (vrsave_reg == GET_SRC_REG (op))
1263 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1268 /* Compute the new value of vrsave, by modifying the register
1269 where vrsave was saved to. */
1270 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1271 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1275 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1276 in a pair of insns to save the vector registers on the
1278 /* 001110 00000 00000 iiii iiii iiii iiii */
1279 /* 001110 01110 00000 iiii iiii iiii iiii */
1280 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1281 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1283 if ((op & 0xffff0000) == 0x38000000)
1284 r0_contains_arg = 0;
1286 vr_saved_offset = SIGNED_SHORT (op);
1288 /* This insn by itself is not part of the prologue, unless
1289 if part of the pair of insns mentioned above. So do not
1290 record this insn as part of the prologue yet. */
1291 prev_insn_was_prologue_insn = 0;
1293 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1294 /* 011111 sssss 11111 00000 00111001110 */
1295 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1297 if (pc == (li_found_pc + 4))
1299 vr_reg = GET_SRC_REG (op);
1300 /* If this is the first vector reg to be saved, or if
1301 it has a lower number than others previously seen,
1302 reupdate the frame info. */
1303 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1305 fdata->saved_vr = vr_reg;
1306 fdata->vr_offset = vr_saved_offset + offset;
1308 vr_saved_offset = -1;
1313 /* End AltiVec related instructions. */
1315 /* Start BookE related instructions. */
1316 /* Store gen register S at (r31+uimm).
1317 Any register less than r13 is volatile, so we don't care. */
1318 /* 000100 sssss 11111 iiiii 01100100001 */
1319 else if (arch_info->mach == bfd_mach_ppc_e500
1320 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1322 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1325 ev_reg = GET_SRC_REG (op);
1326 imm = (op >> 11) & 0x1f;
1327 ev_offset = imm * 8;
1328 /* If this is the first vector reg to be saved, or if
1329 it has a lower number than others previously seen,
1330 reupdate the frame info. */
1331 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1333 fdata->saved_ev = ev_reg;
1334 fdata->ev_offset = ev_offset + offset;
1339 /* Store gen register rS at (r1+rB). */
1340 /* 000100 sssss 00001 bbbbb 01100100000 */
1341 else if (arch_info->mach == bfd_mach_ppc_e500
1342 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1344 if (pc == (li_found_pc + 4))
1346 ev_reg = GET_SRC_REG (op);
1347 /* If this is the first vector reg to be saved, or if
1348 it has a lower number than others previously seen,
1349 reupdate the frame info. */
1350 /* We know the contents of rB from the previous instruction. */
1351 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1353 fdata->saved_ev = ev_reg;
1354 fdata->ev_offset = vr_saved_offset + offset;
1356 vr_saved_offset = -1;
1362 /* Store gen register r31 at (rA+uimm). */
1363 /* 000100 11111 aaaaa iiiii 01100100001 */
1364 else if (arch_info->mach == bfd_mach_ppc_e500
1365 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1367 /* Wwe know that the source register is 31 already, but
1368 it can't hurt to compute it. */
1369 ev_reg = GET_SRC_REG (op);
1370 ev_offset = ((op >> 11) & 0x1f) * 8;
1371 /* If this is the first vector reg to be saved, or if
1372 it has a lower number than others previously seen,
1373 reupdate the frame info. */
1374 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1376 fdata->saved_ev = ev_reg;
1377 fdata->ev_offset = ev_offset + offset;
1382 /* Store gen register S at (r31+r0).
1383 Store param on stack when offset from SP bigger than 4 bytes. */
1384 /* 000100 sssss 11111 00000 01100100000 */
1385 else if (arch_info->mach == bfd_mach_ppc_e500
1386 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1388 if (pc == (li_found_pc + 4))
1390 if ((op & 0x03e00000) >= 0x01a00000)
1392 ev_reg = GET_SRC_REG (op);
1393 /* If this is the first vector reg to be saved, or if
1394 it has a lower number than others previously seen,
1395 reupdate the frame info. */
1396 /* We know the contents of r0 from the previous
1398 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1400 fdata->saved_ev = ev_reg;
1401 fdata->ev_offset = vr_saved_offset + offset;
1405 vr_saved_offset = -1;
1410 /* End BookE related instructions. */
1414 /* Not a recognized prologue instruction.
1415 Handle optimizer code motions into the prologue by continuing
1416 the search if we have no valid frame yet or if the return
1417 address is not yet saved in the frame. */
1418 if (fdata->frameless == 0
1419 && (lr_reg == -1 || fdata->nosavedpc == 0))
1422 if (op == 0x4e800020 /* blr */
1423 || op == 0x4e800420) /* bctr */
1424 /* Do not scan past epilogue in frameless functions or
1427 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1428 /* Never skip branches. */
1431 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1432 /* Do not scan too many insns, scanning insns is expensive with
1436 /* Continue scanning. */
1437 prev_insn_was_prologue_insn = 0;
1443 /* I have problems with skipping over __main() that I need to address
1444 * sometime. Previously, I used to use misc_function_vector which
1445 * didn't work as well as I wanted to be. -MGO */
1447 /* If the first thing after skipping a prolog is a branch to a function,
1448 this might be a call to an initializer in main(), introduced by gcc2.
1449 We'd like to skip over it as well. Fortunately, xlc does some extra
1450 work before calling a function right after a prologue, thus we can
1451 single out such gcc2 behaviour. */
1454 if ((op & 0xfc000001) == 0x48000001)
1455 { /* bl foo, an initializer function? */
1456 op = read_memory_integer (pc + 4, 4);
1458 if (op == 0x4def7b82)
1459 { /* cror 0xf, 0xf, 0xf (nop) */
1461 /* Check and see if we are in main. If so, skip over this
1462 initializer function as well. */
1464 tmp = find_pc_misc_function (pc);
1466 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1472 fdata->offset = -fdata->offset;
1473 return last_prologue_pc;
1477 /*************************************************************************
1478 Support for creating pushing a dummy frame into the stack, and popping
1480 *************************************************************************/
1483 /* All the ABI's require 16 byte alignment. */
1485 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1487 return (addr & -16);
1490 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1491 the first eight words of the argument list (that might be less than
1492 eight parameters if some parameters occupy more than one word) are
1493 passed in r3..r10 registers. float and double parameters are
1494 passed in fpr's, in addition to that. Rest of the parameters if any
1495 are passed in user stack. There might be cases in which half of the
1496 parameter is copied into registers, the other half is pushed into
1499 Stack must be aligned on 64-bit boundaries when synthesizing
1502 If the function is returning a structure, then the return address is passed
1503 in r3, then the first 7 words of the parameters can be passed in registers,
1504 starting from r4. */
1507 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1508 struct regcache *regcache, CORE_ADDR bp_addr,
1509 int nargs, struct value **args, CORE_ADDR sp,
1510 int struct_return, CORE_ADDR struct_addr)
1512 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1515 int argno; /* current argument number */
1516 int argbytes; /* current argument byte */
1517 gdb_byte tmp_buffer[50];
1518 int f_argno = 0; /* current floating point argno */
1519 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1520 CORE_ADDR func_addr = find_function_addr (function, NULL);
1522 struct value *arg = 0;
1527 /* The calling convention this function implements assumes the
1528 processor has floating-point registers. We shouldn't be using it
1529 on PPC variants that lack them. */
1530 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1532 /* The first eight words of ther arguments are passed in registers.
1533 Copy them appropriately. */
1536 /* If the function is returning a `struct', then the first word
1537 (which will be passed in r3) is used for struct return address.
1538 In that case we should advance one word and start from r4
1539 register to copy parameters. */
1542 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1548 effectively indirect call... gcc does...
1550 return_val example( float, int);
1553 float in fp0, int in r3
1554 offset of stack on overflow 8/16
1555 for varargs, must go by type.
1557 float in r3&r4, int in r5
1558 offset of stack on overflow different
1560 return in r3 or f0. If no float, must study how gcc emulates floats;
1561 pay attention to arg promotion.
1562 User may have to cast\args to handle promotion correctly
1563 since gdb won't know if prototype supplied or not.
1566 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1568 int reg_size = register_size (current_gdbarch, ii + 3);
1571 type = check_typedef (value_type (arg));
1572 len = TYPE_LENGTH (type);
1574 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1577 /* Floating point arguments are passed in fpr's, as well as gpr's.
1578 There are 13 fpr's reserved for passing parameters. At this point
1579 there is no way we would run out of them. */
1581 gdb_assert (len <= 8);
1583 regcache_cooked_write (regcache,
1584 tdep->ppc_fp0_regnum + 1 + f_argno,
1585 value_contents (arg));
1592 /* Argument takes more than one register. */
1593 while (argbytes < len)
1595 gdb_byte word[MAX_REGISTER_SIZE];
1596 memset (word, 0, reg_size);
1598 ((char *) value_contents (arg)) + argbytes,
1599 (len - argbytes) > reg_size
1600 ? reg_size : len - argbytes);
1601 regcache_cooked_write (regcache,
1602 tdep->ppc_gp0_regnum + 3 + ii,
1604 ++ii, argbytes += reg_size;
1607 goto ran_out_of_registers_for_arguments;
1614 /* Argument can fit in one register. No problem. */
1615 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1616 gdb_byte word[MAX_REGISTER_SIZE];
1618 memset (word, 0, reg_size);
1619 memcpy (word, value_contents (arg), len);
1620 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1625 ran_out_of_registers_for_arguments:
1627 saved_sp = read_sp ();
1629 /* Location for 8 parameters are always reserved. */
1632 /* Another six words for back chain, TOC register, link register, etc. */
1635 /* Stack pointer must be quadword aligned. */
1638 /* If there are more arguments, allocate space for them in
1639 the stack, then push them starting from the ninth one. */
1641 if ((argno < nargs) || argbytes)
1647 space += ((len - argbytes + 3) & -4);
1653 for (; jj < nargs; ++jj)
1655 struct value *val = args[jj];
1656 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
1659 /* Add location required for the rest of the parameters. */
1660 space = (space + 15) & -16;
1663 /* This is another instance we need to be concerned about
1664 securing our stack space. If we write anything underneath %sp
1665 (r1), we might conflict with the kernel who thinks he is free
1666 to use this area. So, update %sp first before doing anything
1669 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1671 /* If the last argument copied into the registers didn't fit there
1672 completely, push the rest of it into stack. */
1676 write_memory (sp + 24 + (ii * 4),
1677 value_contents (arg) + argbytes,
1680 ii += ((len - argbytes + 3) & -4) / 4;
1683 /* Push the rest of the arguments into stack. */
1684 for (; argno < nargs; ++argno)
1688 type = check_typedef (value_type (arg));
1689 len = TYPE_LENGTH (type);
1692 /* Float types should be passed in fpr's, as well as in the
1694 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1697 gdb_assert (len <= 8);
1699 regcache_cooked_write (regcache,
1700 tdep->ppc_fp0_regnum + 1 + f_argno,
1701 value_contents (arg));
1705 write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
1706 ii += ((len + 3) & -4) / 4;
1710 /* Set the stack pointer. According to the ABI, the SP is meant to
1711 be set _before_ the corresponding stack space is used. On AIX,
1712 this even applies when the target has been completely stopped!
1713 Not doing this can lead to conflicts with the kernel which thinks
1714 that it still has control over this not-yet-allocated stack
1716 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1718 /* Set back chain properly. */
1719 store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
1720 write_memory (sp, tmp_buffer, wordsize);
1722 /* Point the inferior function call's return address at the dummy's
1724 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1726 /* Set the TOC register, get the value from the objfile reader
1727 which, in turn, gets it from the VMAP table. */
1728 if (rs6000_find_toc_address_hook != NULL)
1730 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1731 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1734 target_store_registers (-1);
1738 /* PowerOpen always puts structures in memory. Vectors, which were
1739 added later, do get returned in a register though. */
1742 rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1744 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1745 && TYPE_VECTOR (value_type))
1751 rs6000_extract_return_value (struct type *valtype, gdb_byte *regbuf,
1755 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1757 /* The calling convention this function implements assumes the
1758 processor has floating-point registers. We shouldn't be using it
1759 on PPC variants that lack them. */
1760 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1762 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1765 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1766 We need to truncate the return value into float size (4 byte) if
1769 convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
1770 (tdep->ppc_fp0_regnum + 1)],
1771 builtin_type_double,
1775 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1776 && TYPE_LENGTH (valtype) == 16
1777 && TYPE_VECTOR (valtype))
1779 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1780 TYPE_LENGTH (valtype));
1784 /* return value is copied starting from r3. */
1785 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1786 && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3))
1787 offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype);
1790 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
1791 TYPE_LENGTH (valtype));
1795 /* Return whether handle_inferior_event() should proceed through code
1796 starting at PC in function NAME when stepping.
1798 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1799 handle memory references that are too distant to fit in instructions
1800 generated by the compiler. For example, if 'foo' in the following
1805 is greater than 32767, the linker might replace the lwz with a branch to
1806 somewhere in @FIX1 that does the load in 2 instructions and then branches
1807 back to where execution should continue.
1809 GDB should silently step over @FIX code, just like AIX dbx does.
1810 Unfortunately, the linker uses the "b" instruction for the
1811 branches, meaning that the link register doesn't get set.
1812 Therefore, GDB's usual step_over_function () mechanism won't work.
1814 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1815 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1819 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1821 return name && !strncmp (name, "@FIX", 4);
1824 /* Skip code that the user doesn't want to see when stepping:
1826 1. Indirect function calls use a piece of trampoline code to do context
1827 switching, i.e. to set the new TOC table. Skip such code if we are on
1828 its first instruction (as when we have single-stepped to here).
1830 2. Skip shared library trampoline code (which is different from
1831 indirect function call trampolines).
1833 3. Skip bigtoc fixup code.
1835 Result is desired PC to step until, or NULL if we are not in
1836 code that should be skipped. */
1839 rs6000_skip_trampoline_code (CORE_ADDR pc)
1841 unsigned int ii, op;
1843 CORE_ADDR solib_target_pc;
1844 struct minimal_symbol *msymbol;
1846 static unsigned trampoline_code[] =
1848 0x800b0000, /* l r0,0x0(r11) */
1849 0x90410014, /* st r2,0x14(r1) */
1850 0x7c0903a6, /* mtctr r0 */
1851 0x804b0004, /* l r2,0x4(r11) */
1852 0x816b0008, /* l r11,0x8(r11) */
1853 0x4e800420, /* bctr */
1854 0x4e800020, /* br */
1858 /* Check for bigtoc fixup code. */
1859 msymbol = lookup_minimal_symbol_by_pc (pc);
1861 && rs6000_in_solib_return_trampoline (pc,
1862 DEPRECATED_SYMBOL_NAME (msymbol)))
1864 /* Double-check that the third instruction from PC is relative "b". */
1865 op = read_memory_integer (pc + 8, 4);
1866 if ((op & 0xfc000003) == 0x48000000)
1868 /* Extract bits 6-29 as a signed 24-bit relative word address and
1869 add it to the containing PC. */
1870 rel = ((int)(op << 6) >> 6);
1871 return pc + 8 + rel;
1875 /* If pc is in a shared library trampoline, return its target. */
1876 solib_target_pc = find_solib_trampoline_target (pc);
1877 if (solib_target_pc)
1878 return solib_target_pc;
1880 for (ii = 0; trampoline_code[ii]; ++ii)
1882 op = read_memory_integer (pc + (ii * 4), 4);
1883 if (op != trampoline_code[ii])
1886 ii = read_register (11); /* r11 holds destination addr */
1887 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1891 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1892 isn't available with that word size, return 0. */
1895 regsize (const struct reg *reg, int wordsize)
1897 return wordsize == 8 ? reg->sz64 : reg->sz32;
1900 /* Return the name of register number N, or null if no such register exists
1901 in the current architecture. */
1904 rs6000_register_name (int n)
1906 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1907 const struct reg *reg = tdep->regs + n;
1909 if (!regsize (reg, tdep->wordsize))
1914 /* Return the GDB type object for the "standard" data type
1915 of data in register N. */
1917 static struct type *
1918 rs6000_register_type (struct gdbarch *gdbarch, int n)
1920 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1921 const struct reg *reg = tdep->regs + n;
1924 return builtin_type_double;
1927 int size = regsize (reg, tdep->wordsize);
1931 return builtin_type_int0;
1933 return builtin_type_uint32;
1935 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1936 return builtin_type_vec64;
1938 return builtin_type_uint64;
1941 return builtin_type_vec128;
1944 internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"),
1950 /* Is REGNUM a member of REGGROUP? */
1952 rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1953 struct reggroup *group)
1955 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1960 if (REGISTER_NAME (regnum) == NULL
1961 || *REGISTER_NAME (regnum) == '\0')
1963 if (group == all_reggroup)
1966 float_p = (regnum == tdep->ppc_fpscr_regnum
1967 || (regnum >= tdep->ppc_fp0_regnum
1968 && regnum < tdep->ppc_fp0_regnum + 32));
1969 if (group == float_reggroup)
1972 vector_p = ((tdep->ppc_vr0_regnum >= 0
1973 && regnum >= tdep->ppc_vr0_regnum
1974 && regnum < tdep->ppc_vr0_regnum + 32)
1975 || (tdep->ppc_ev0_regnum >= 0
1976 && regnum >= tdep->ppc_ev0_regnum
1977 && regnum < tdep->ppc_ev0_regnum + 32)
1978 || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */
1979 || regnum == tdep->ppc_vrsave_regnum
1980 || regnum == tdep->ppc_acc_regnum
1981 || regnum == tdep->ppc_spefscr_regnum);
1982 if (group == vector_reggroup)
1985 /* Note that PS aka MSR isn't included - it's a system register (and
1986 besides, due to GCC's CFI foobar you do not want to restore
1988 general_p = ((regnum >= tdep->ppc_gp0_regnum
1989 && regnum < tdep->ppc_gp0_regnum + 32)
1990 || regnum == tdep->ppc_toc_regnum
1991 || regnum == tdep->ppc_cr_regnum
1992 || regnum == tdep->ppc_lr_regnum
1993 || regnum == tdep->ppc_ctr_regnum
1994 || regnum == tdep->ppc_xer_regnum
1995 || regnum == PC_REGNUM);
1996 if (group == general_reggroup)
1999 if (group == save_reggroup || group == restore_reggroup)
2000 return general_p || vector_p || float_p;
2005 /* The register format for RS/6000 floating point registers is always
2006 double, we need a conversion if the memory format is float. */
2009 rs6000_convert_register_p (int regnum, struct type *type)
2011 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2014 && TYPE_CODE (type) == TYPE_CODE_FLT
2015 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2019 rs6000_register_to_value (struct frame_info *frame,
2024 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2025 gdb_byte from[MAX_REGISTER_SIZE];
2027 gdb_assert (reg->fpr);
2028 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2030 get_frame_register (frame, regnum, from);
2031 convert_typed_floating (from, builtin_type_double, to, type);
2035 rs6000_value_to_register (struct frame_info *frame,
2038 const gdb_byte *from)
2040 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2041 gdb_byte to[MAX_REGISTER_SIZE];
2043 gdb_assert (reg->fpr);
2044 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2046 convert_typed_floating (from, type, to, builtin_type_double);
2047 put_frame_register (frame, regnum, to);
2050 /* Move SPE vector register values between a 64-bit buffer and the two
2051 32-bit raw register halves in a regcache. This function handles
2052 both splitting a 64-bit value into two 32-bit halves, and joining
2053 two halves into a whole 64-bit value, depending on the function
2054 passed as the MOVE argument.
2056 EV_REG must be the number of an SPE evN vector register --- a
2057 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2060 Call MOVE once for each 32-bit half of that register, passing
2061 REGCACHE, the number of the raw register corresponding to that
2062 half, and the address of the appropriate half of BUFFER.
2064 For example, passing 'regcache_raw_read' as the MOVE function will
2065 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2066 'regcache_raw_supply' will supply the contents of BUFFER to the
2067 appropriate pair of raw registers in REGCACHE.
2069 You may need to cast away some 'const' qualifiers when passing
2070 MOVE, since this function can't tell at compile-time which of
2071 REGCACHE or BUFFER is acting as the source of the data. If C had
2072 co-variant type qualifiers, ... */
2074 e500_move_ev_register (void (*move) (struct regcache *regcache,
2075 int regnum, gdb_byte *buf),
2076 struct regcache *regcache, int ev_reg,
2079 struct gdbarch *arch = get_regcache_arch (regcache);
2080 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2082 gdb_byte *byte_buffer = buffer;
2084 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
2085 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
2087 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2089 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2091 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2092 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2096 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2097 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2102 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2103 int reg_nr, gdb_byte *buffer)
2105 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2106 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2108 gdb_assert (regcache_arch == gdbarch);
2110 if (tdep->ppc_ev0_regnum <= reg_nr
2111 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2112 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2114 internal_error (__FILE__, __LINE__,
2115 _("e500_pseudo_register_read: "
2116 "called on unexpected register '%s' (%d)"),
2117 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2121 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2122 int reg_nr, const gdb_byte *buffer)
2124 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2125 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2127 gdb_assert (regcache_arch == gdbarch);
2129 if (tdep->ppc_ev0_regnum <= reg_nr
2130 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2131 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2133 regcache, reg_nr, (gdb_byte *) buffer);
2135 internal_error (__FILE__, __LINE__,
2136 _("e500_pseudo_register_read: "
2137 "called on unexpected register '%s' (%d)"),
2138 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2141 /* The E500 needs a custom reggroup function: it has anonymous raw
2142 registers, and default_register_reggroup_p assumes that anonymous
2143 registers are not members of any reggroup. */
2145 e500_register_reggroup_p (struct gdbarch *gdbarch,
2147 struct reggroup *group)
2149 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2151 /* The save and restore register groups need to include the
2152 upper-half registers, even though they're anonymous. */
2153 if ((group == save_reggroup
2154 || group == restore_reggroup)
2155 && (tdep->ppc_ev0_upper_regnum <= regnum
2156 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
2159 /* In all other regards, the default reggroup definition is fine. */
2160 return default_register_reggroup_p (gdbarch, regnum, group);
2163 /* Convert a DBX STABS register number to a GDB register number. */
2165 rs6000_stab_reg_to_regnum (int num)
2167 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2169 if (0 <= num && num <= 31)
2170 return tdep->ppc_gp0_regnum + num;
2171 else if (32 <= num && num <= 63)
2172 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2173 specifies registers the architecture doesn't have? Our
2174 callers don't check the value we return. */
2175 return tdep->ppc_fp0_regnum + (num - 32);
2176 else if (77 <= num && num <= 108)
2177 return tdep->ppc_vr0_regnum + (num - 77);
2178 else if (1200 <= num && num < 1200 + 32)
2179 return tdep->ppc_ev0_regnum + (num - 1200);
2184 return tdep->ppc_mq_regnum;
2186 return tdep->ppc_lr_regnum;
2188 return tdep->ppc_ctr_regnum;
2190 return tdep->ppc_xer_regnum;
2192 return tdep->ppc_vrsave_regnum;
2194 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2196 return tdep->ppc_acc_regnum;
2198 return tdep->ppc_spefscr_regnum;
2205 /* Convert a Dwarf 2 register number to a GDB register number. */
2207 rs6000_dwarf2_reg_to_regnum (int num)
2209 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2211 if (0 <= num && num <= 31)
2212 return tdep->ppc_gp0_regnum + num;
2213 else if (32 <= num && num <= 63)
2214 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2215 specifies registers the architecture doesn't have? Our
2216 callers don't check the value we return. */
2217 return tdep->ppc_fp0_regnum + (num - 32);
2218 else if (1124 <= num && num < 1124 + 32)
2219 return tdep->ppc_vr0_regnum + (num - 1124);
2220 else if (1200 <= num && num < 1200 + 32)
2221 return tdep->ppc_ev0_regnum + (num - 1200);
2226 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2228 return tdep->ppc_acc_regnum;
2230 return tdep->ppc_mq_regnum;
2232 return tdep->ppc_xer_regnum;
2234 return tdep->ppc_lr_regnum;
2236 return tdep->ppc_ctr_regnum;
2238 return tdep->ppc_vrsave_regnum;
2240 return tdep->ppc_spefscr_regnum;
2248 rs6000_store_return_value (struct type *type,
2249 struct regcache *regcache,
2250 const gdb_byte *valbuf)
2252 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2253 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2256 /* The calling convention this function implements assumes the
2257 processor has floating-point registers. We shouldn't be using it
2258 on PPC variants that lack them. */
2259 gdb_assert (ppc_floating_point_unit_p (gdbarch));
2261 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2262 /* Floating point values are returned starting from FPR1 and up.
2263 Say a double_double_double type could be returned in
2264 FPR1/FPR2/FPR3 triple. */
2265 regnum = tdep->ppc_fp0_regnum + 1;
2266 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2268 if (TYPE_LENGTH (type) == 16
2269 && TYPE_VECTOR (type))
2270 regnum = tdep->ppc_vr0_regnum + 2;
2272 internal_error (__FILE__, __LINE__,
2273 _("rs6000_store_return_value: "
2274 "unexpected array return type"));
2277 /* Everything else is returned in GPR3 and up. */
2278 regnum = tdep->ppc_gp0_regnum + 3;
2281 size_t bytes_written = 0;
2283 while (bytes_written < TYPE_LENGTH (type))
2285 /* How much of this value can we write to this register? */
2286 size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written,
2287 register_size (gdbarch, regnum));
2288 regcache_cooked_write_part (regcache, regnum,
2290 valbuf + bytes_written);
2292 bytes_written += bytes_to_write;
2298 /* Extract from an array REGBUF containing the (raw) register state
2299 the address in which a function should return its structure value,
2300 as a CORE_ADDR (or an expression that can be used as one). */
2303 rs6000_extract_struct_value_address (struct regcache *regcache)
2305 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
2306 function call GDB knows the address of the struct return value
2307 and hence, should not need to call this function. Unfortunately,
2308 the current call_function_by_hand() code only saves the most
2309 recent struct address leading to occasional calls. The code
2310 should instead maintain a stack of such addresses (in the dummy
2312 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
2313 really got no idea where the return value is being stored. While
2314 r3, on function entry, contained the address it will have since
2315 been reused (scratch) and hence wouldn't be valid */
2319 /* Hook called when a new child process is started. */
2322 rs6000_create_inferior (int pid)
2324 if (rs6000_set_host_arch_hook)
2325 rs6000_set_host_arch_hook (pid);
2328 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2330 Usually a function pointer's representation is simply the address
2331 of the function. On the RS/6000 however, a function pointer is
2332 represented by a pointer to an OPD entry. This OPD entry contains
2333 three words, the first word is the address of the function, the
2334 second word is the TOC pointer (r2), and the third word is the
2335 static chain value. Throughout GDB it is currently assumed that a
2336 function pointer contains the address of the function, which is not
2337 easy to fix. In addition, the conversion of a function address to
2338 a function pointer would require allocation of an OPD entry in the
2339 inferior's memory space, with all its drawbacks. To be able to
2340 call C++ virtual methods in the inferior (which are called via
2341 function pointers), find_function_addr uses this function to get the
2342 function address from a function pointer. */
2344 /* Return real function address if ADDR (a function pointer) is in the data
2345 space and is therefore a special function pointer. */
2348 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2350 struct target_ops *targ)
2352 struct obj_section *s;
2354 s = find_pc_section (addr);
2355 if (s && s->the_bfd_section->flags & SEC_CODE)
2358 /* ADDR is in the data space, so it's a special function pointer. */
2359 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
2363 /* Handling the various POWER/PowerPC variants. */
2366 /* The arrays here called registers_MUMBLE hold information about available
2369 For each family of PPC variants, I've tried to isolate out the
2370 common registers and put them up front, so that as long as you get
2371 the general family right, GDB will correctly identify the registers
2372 common to that family. The common register sets are:
2374 For the 60x family: hid0 hid1 iabr dabr pir
2376 For the 505 and 860 family: eie eid nri
2378 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2379 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2382 Most of these register groups aren't anything formal. I arrived at
2383 them by looking at the registers that occurred in more than one
2386 Note: kevinb/2002-04-30: Support for the fpscr register was added
2387 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2388 for Power. For PowerPC, slot 70 was unused and was already in the
2389 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2390 slot 70 was being used for "mq", so the next available slot (71)
2391 was chosen. It would have been nice to be able to make the
2392 register numbers the same across processor cores, but this wasn't
2393 possible without either 1) renumbering some registers for some
2394 processors or 2) assigning fpscr to a really high slot that's
2395 larger than any current register number. Doing (1) is bad because
2396 existing stubs would break. Doing (2) is undesirable because it
2397 would introduce a really large gap between fpscr and the rest of
2398 the registers for most processors. */
2400 /* Convenience macros for populating register arrays. */
2402 /* Within another macro, convert S to a string. */
2406 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2407 and 64 bits on 64-bit systems. */
2408 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2410 /* Return a struct reg defining register NAME that's 32 bits on all
2412 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2414 /* Return a struct reg defining register NAME that's 64 bits on all
2416 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2418 /* Return a struct reg defining register NAME that's 128 bits on all
2420 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2422 /* Return a struct reg defining floating-point register NAME. */
2423 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2425 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2426 long on all systems. */
2427 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2429 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2430 systems and that doesn't exist on 64-bit systems. */
2431 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2433 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2434 systems and that doesn't exist on 32-bit systems. */
2435 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2437 /* Return a struct reg placeholder for a register that doesn't exist. */
2438 #define R0 { 0, 0, 0, 0, 0, -1 }
2440 /* Return a struct reg defining an anonymous raw register that's 32
2441 bits on all systems. */
2442 #define A4 { 0, 4, 4, 0, 0, -1 }
2444 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2445 32-bit systems and 64 bits on 64-bit systems. */
2446 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2448 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2450 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2452 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2453 all systems, and whose SPR number is NUMBER. */
2454 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2456 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2457 64-bit systems and that doesn't exist on 32-bit systems. */
2458 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2460 /* UISA registers common across all architectures, including POWER. */
2462 #define COMMON_UISA_REGS \
2463 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2464 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2465 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2466 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2467 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2468 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2469 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2470 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2471 /* 64 */ R(pc), R(ps)
2473 /* UISA-level SPRs for PowerPC. */
2474 #define PPC_UISA_SPRS \
2475 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2477 /* UISA-level SPRs for PowerPC without floating point support. */
2478 #define PPC_UISA_NOFP_SPRS \
2479 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2481 /* Segment registers, for PowerPC. */
2482 #define PPC_SEGMENT_REGS \
2483 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2484 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2485 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2486 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2488 /* OEA SPRs for PowerPC. */
2489 #define PPC_OEA_SPRS \
2491 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2492 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2493 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2494 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2495 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2496 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2497 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2498 /* 116 */ S4(dec), S(dabr), S4(ear)
2500 /* AltiVec registers. */
2501 #define PPC_ALTIVEC_REGS \
2502 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2503 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2504 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2505 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2506 /*151*/R4(vscr), R4(vrsave)
2509 /* On machines supporting the SPE APU, the general-purpose registers
2510 are 64 bits long. There are SIMD vector instructions to treat them
2511 as pairs of floats, but the rest of the instruction set treats them
2512 as 32-bit registers, and only operates on their lower halves.
2514 In the GDB regcache, we treat their high and low halves as separate
2515 registers. The low halves we present as the general-purpose
2516 registers, and then we have pseudo-registers that stitch together
2517 the upper and lower halves and present them as pseudo-registers. */
2519 /* SPE GPR lower halves --- raw registers. */
2520 #define PPC_SPE_GP_REGS \
2521 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2522 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2523 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2524 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2526 /* SPE GPR upper halves --- anonymous raw registers. */
2527 #define PPC_SPE_UPPER_GP_REGS \
2528 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2529 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2530 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2531 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2533 /* SPE GPR vector registers --- pseudo registers based on underlying
2534 gprs and the anonymous upper half raw registers. */
2535 #define PPC_EV_PSEUDO_REGS \
2536 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2537 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2538 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2539 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2541 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2542 user-level SPR's. */
2543 static const struct reg registers_power[] =
2546 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
2550 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2551 view of the PowerPC. */
2552 static const struct reg registers_powerpc[] =
2561 Some notes about the "tcr" special-purpose register:
2562 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2563 403's programmable interval timer, fixed interval timer, and
2565 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2566 watchdog timer, and nothing else.
2568 Some of the fields are similar between the two, but they're not
2569 compatible with each other. Since the two variants have different
2570 registers, with different numbers, but the same name, we can't
2571 splice the register name to get the SPR number. */
2572 static const struct reg registers_403[] =
2578 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2579 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2580 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2581 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2582 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2583 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
2586 /* IBM PowerPC 403GC.
2587 See the comments about 'tcr' for the 403, above. */
2588 static const struct reg registers_403GC[] =
2594 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2595 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2596 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2597 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2598 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2599 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
2600 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
2601 /* 147 */ S(tbhu), S(tblu)
2604 /* Motorola PowerPC 505. */
2605 static const struct reg registers_505[] =
2611 /* 119 */ S(eie), S(eid), S(nri)
2614 /* Motorola PowerPC 860 or 850. */
2615 static const struct reg registers_860[] =
2621 /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
2622 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
2623 /* 127 */ S(der), S(counta), S(countb), S(cmpe),
2624 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
2625 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
2626 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
2627 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
2628 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
2629 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
2630 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
2631 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
2632 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
2635 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2636 for reading and writing RTCU and RTCL. However, how one reads and writes a
2637 register is the stub's problem. */
2638 static const struct reg registers_601[] =
2644 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2645 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
2648 /* Motorola PowerPC 602.
2649 See the notes under the 403 about 'tcr'. */
2650 static const struct reg registers_602[] =
2656 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2657 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
2658 /* 127 */ S(sebr), S(ser), S(sp), S(lt)
2661 /* Motorola/IBM PowerPC 603 or 603e. */
2662 static const struct reg registers_603[] =
2668 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2669 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
2670 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
2673 /* Motorola PowerPC 604 or 604e. */
2674 static const struct reg registers_604[] =
2680 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2681 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
2682 /* 127 */ S(sia), S(sda)
2685 /* Motorola/IBM PowerPC 750 or 740. */
2686 static const struct reg registers_750[] =
2692 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2693 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
2694 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
2695 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
2696 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
2697 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
2701 /* Motorola PowerPC 7400. */
2702 static const struct reg registers_7400[] =
2704 /* gpr0-gpr31, fpr0-fpr31 */
2706 /* cr, lr, ctr, xer, fpscr */
2711 /* vr0-vr31, vrsave, vscr */
2713 /* FIXME? Add more registers? */
2716 /* Motorola e500. */
2717 static const struct reg registers_e500[] =
2719 /* 0 .. 31 */ PPC_SPE_GP_REGS,
2720 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
2721 /* 64 .. 65 */ R(pc), R(ps),
2722 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
2723 /* 71 .. 72 */ R8(acc), S4(spefscr),
2724 /* NOTE: Add new registers here the end of the raw register
2725 list and just before the first pseudo register. */
2726 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2729 /* Information about a particular processor variant. */
2733 /* Name of this variant. */
2736 /* English description of the variant. */
2739 /* bfd_arch_info.arch corresponding to variant. */
2740 enum bfd_architecture arch;
2742 /* bfd_arch_info.mach corresponding to variant. */
2745 /* Number of real registers. */
2748 /* Number of pseudo registers. */
2751 /* Number of total registers (the sum of nregs and npregs). */
2754 /* Table of register names; registers[R] is the name of the register
2756 const struct reg *regs;
2759 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2762 num_registers (const struct reg *reg_list, int num_tot_regs)
2767 for (i = 0; i < num_tot_regs; i++)
2768 if (!reg_list[i].pseudo)
2775 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2780 for (i = 0; i < num_tot_regs; i++)
2781 if (reg_list[i].pseudo)
2787 /* Information in this table comes from the following web sites:
2788 IBM: http://www.chips.ibm.com:80/products/embedded/
2789 Motorola: http://www.mot.com/SPS/PowerPC/
2791 I'm sure I've got some of the variant descriptions not quite right.
2792 Please report any inaccuracies you find to GDB's maintainer.
2794 If you add entries to this table, please be sure to allow the new
2795 value as an argument to the --with-cpu flag, in configure.in. */
2797 static struct variant variants[] =
2800 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2801 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2803 {"power", "POWER user-level", bfd_arch_rs6000,
2804 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2806 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2807 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2809 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2810 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2812 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2813 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2815 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2816 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2818 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2819 604, -1, -1, tot_num_registers (registers_604),
2821 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2822 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2824 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2825 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2827 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2828 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2830 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2831 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2833 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2834 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2836 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2837 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2841 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2842 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2844 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2845 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2847 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2848 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2850 {"a35", "PowerPC A35", bfd_arch_powerpc,
2851 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2853 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2854 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2856 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2857 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2860 /* FIXME: I haven't checked the register sets of the following. */
2861 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2862 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2864 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2865 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2867 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2868 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2871 {0, 0, 0, 0, 0, 0, 0, 0}
2874 /* Initialize the number of registers and pseudo registers in each variant. */
2877 init_variants (void)
2881 for (v = variants; v->name; v++)
2884 v->nregs = num_registers (v->regs, v->num_tot_regs);
2885 if (v->npregs == -1)
2886 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2890 /* Return the variant corresponding to architecture ARCH and machine number
2891 MACH. If no such variant exists, return null. */
2893 static const struct variant *
2894 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2896 const struct variant *v;
2898 for (v = variants; v->name; v++)
2899 if (arch == v->arch && mach == v->mach)
2906 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2908 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2909 return print_insn_big_powerpc (memaddr, info);
2911 return print_insn_little_powerpc (memaddr, info);
2915 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2917 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2920 static struct frame_id
2921 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2923 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2925 frame_pc_unwind (next_frame));
2928 struct rs6000_frame_cache
2931 CORE_ADDR initial_sp;
2932 struct trad_frame_saved_reg *saved_regs;
2935 static struct rs6000_frame_cache *
2936 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2938 struct rs6000_frame_cache *cache;
2939 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2940 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2941 struct rs6000_framedata fdata;
2942 int wordsize = tdep->wordsize;
2945 if ((*this_cache) != NULL)
2946 return (*this_cache);
2947 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2948 (*this_cache) = cache;
2949 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2951 func = frame_func_unwind (next_frame);
2952 pc = frame_pc_unwind (next_frame);
2953 skip_prologue (func, pc, &fdata);
2955 /* Figure out the parent's stack pointer. */
2957 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2958 address of the current frame. Things might be easier if the
2959 ->frame pointed to the outer-most address of the frame. In
2960 the mean time, the address of the prev frame is used as the
2961 base address of this frame. */
2962 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2964 /* If the function appears to be frameless, check a couple of likely
2965 indicators that we have simply failed to find the frame setup.
2966 Two common cases of this are missing symbols (i.e.
2967 frame_func_unwind returns the wrong address or 0), and assembly
2968 stubs which have a fast exit path but set up a frame on the slow
2971 If the LR appears to return to this function, then presume that
2972 we have an ABI compliant frame that we failed to find. */
2973 if (fdata.frameless && fdata.lr_offset == 0)
2978 saved_lr = frame_unwind_register_unsigned (next_frame,
2979 tdep->ppc_lr_regnum);
2980 if (func == 0 && saved_lr == pc)
2984 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
2985 if (func == saved_func)
2991 fdata.frameless = 0;
2992 fdata.lr_offset = wordsize;
2996 if (!fdata.frameless)
2997 /* Frameless really means stackless. */
2998 cache->base = read_memory_addr (cache->base, wordsize);
3000 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
3002 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3003 All fpr's from saved_fpr to fp31 are saved. */
3005 if (fdata.saved_fpr >= 0)
3008 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3010 /* If skip_prologue says floating-point registers were saved,
3011 but the current architecture has no floating-point registers,
3012 then that's strange. But we have no indices to even record
3013 the addresses under, so we just ignore it. */
3014 if (ppc_floating_point_unit_p (gdbarch))
3015 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3017 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3022 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3023 All gpr's from saved_gpr to gpr31 are saved. */
3025 if (fdata.saved_gpr >= 0)
3028 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3029 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3031 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3032 gpr_addr += wordsize;
3036 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3037 All vr's from saved_vr to vr31 are saved. */
3038 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3040 if (fdata.saved_vr >= 0)
3043 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3044 for (i = fdata.saved_vr; i < 32; i++)
3046 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3047 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3052 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3053 All vr's from saved_ev to ev31 are saved. ????? */
3054 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
3056 if (fdata.saved_ev >= 0)
3059 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3060 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3062 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3063 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3064 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3069 /* If != 0, fdata.cr_offset is the offset from the frame that
3071 if (fdata.cr_offset != 0)
3072 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3074 /* If != 0, fdata.lr_offset is the offset from the frame that
3076 if (fdata.lr_offset != 0)
3077 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
3078 /* The PC is found in the link register. */
3079 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
3081 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3082 holds the VRSAVE. */
3083 if (fdata.vrsave_offset != 0)
3084 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3086 if (fdata.alloca_reg < 0)
3087 /* If no alloca register used, then fi->frame is the value of the
3088 %sp for this frame, and it is good enough. */
3089 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
3091 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3098 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3099 struct frame_id *this_id)
3101 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3103 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
3107 rs6000_frame_prev_register (struct frame_info *next_frame,
3109 int regnum, int *optimizedp,
3110 enum lval_type *lvalp, CORE_ADDR *addrp,
3111 int *realnump, gdb_byte *valuep)
3113 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3115 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3116 optimizedp, lvalp, addrp, realnump, valuep);
3119 static const struct frame_unwind rs6000_frame_unwind =
3122 rs6000_frame_this_id,
3123 rs6000_frame_prev_register
3126 static const struct frame_unwind *
3127 rs6000_frame_sniffer (struct frame_info *next_frame)
3129 return &rs6000_frame_unwind;
3135 rs6000_frame_base_address (struct frame_info *next_frame,
3138 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3140 return info->initial_sp;
3143 static const struct frame_base rs6000_frame_base = {
3144 &rs6000_frame_unwind,
3145 rs6000_frame_base_address,
3146 rs6000_frame_base_address,
3147 rs6000_frame_base_address
3150 static const struct frame_base *
3151 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3153 return &rs6000_frame_base;
3156 /* Initialize the current architecture based on INFO. If possible, re-use an
3157 architecture from ARCHES, which is a list of architectures already created
3158 during this debugging session.
3160 Called e.g. at program startup, when reading a core file, and when reading
3163 static struct gdbarch *
3164 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3166 struct gdbarch *gdbarch;
3167 struct gdbarch_tdep *tdep;
3168 int wordsize, from_xcoff_exec, from_elf_exec, i, off;
3170 const struct variant *v;
3171 enum bfd_architecture arch;
3177 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3178 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3180 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3181 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3183 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3185 /* Check word size. If INFO is from a binary file, infer it from
3186 that, else choose a likely default. */
3187 if (from_xcoff_exec)
3189 if (bfd_xcoff_is_xcoff64 (info.abfd))
3194 else if (from_elf_exec)
3196 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3203 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3204 wordsize = info.bfd_arch_info->bits_per_word /
3205 info.bfd_arch_info->bits_per_byte;
3210 /* Find a candidate among extant architectures. */
3211 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3213 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3215 /* Word size in the various PowerPC bfd_arch_info structs isn't
3216 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3217 separate word size check. */
3218 tdep = gdbarch_tdep (arches->gdbarch);
3219 if (tdep && tdep->wordsize == wordsize)
3220 return arches->gdbarch;
3223 /* None found, create a new architecture from INFO, whose bfd_arch_info
3224 validity depends on the source:
3225 - executable useless
3226 - rs6000_host_arch() good
3228 - "set arch" trust blindly
3229 - GDB startup useless but harmless */
3231 if (!from_xcoff_exec)
3233 arch = info.bfd_arch_info->arch;
3234 mach = info.bfd_arch_info->mach;
3238 arch = bfd_arch_powerpc;
3239 bfd_default_set_arch_mach (&abfd, arch, 0);
3240 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3241 mach = info.bfd_arch_info->mach;
3243 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3244 tdep->wordsize = wordsize;
3246 /* For e500 executables, the apuinfo section is of help here. Such
3247 section contains the identifier and revision number of each
3248 Application-specific Processing Unit that is present on the
3249 chip. The content of the section is determined by the assembler
3250 which looks at each instruction and determines which unit (and
3251 which version of it) can execute it. In our case we just look for
3252 the existance of the section. */
3256 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3259 arch = info.bfd_arch_info->arch;
3260 mach = bfd_mach_ppc_e500;
3261 bfd_default_set_arch_mach (&abfd, arch, mach);
3262 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3266 gdbarch = gdbarch_alloc (&info, tdep);
3268 /* Initialize the number of real and pseudo registers in each variant. */
3271 /* Choose variant. */
3272 v = find_variant_by_arch (arch, mach);
3276 tdep->regs = v->regs;
3278 tdep->ppc_gp0_regnum = 0;
3279 tdep->ppc_toc_regnum = 2;
3280 tdep->ppc_ps_regnum = 65;
3281 tdep->ppc_cr_regnum = 66;
3282 tdep->ppc_lr_regnum = 67;
3283 tdep->ppc_ctr_regnum = 68;
3284 tdep->ppc_xer_regnum = 69;
3285 if (v->mach == bfd_mach_ppc_601)
3286 tdep->ppc_mq_regnum = 124;
3287 else if (arch == bfd_arch_rs6000)
3288 tdep->ppc_mq_regnum = 70;
3290 tdep->ppc_mq_regnum = -1;
3291 tdep->ppc_fp0_regnum = 32;
3292 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
3293 tdep->ppc_sr0_regnum = 71;
3294 tdep->ppc_vr0_regnum = -1;
3295 tdep->ppc_vrsave_regnum = -1;
3296 tdep->ppc_ev0_upper_regnum = -1;
3297 tdep->ppc_ev0_regnum = -1;
3298 tdep->ppc_ev31_regnum = -1;
3299 tdep->ppc_acc_regnum = -1;
3300 tdep->ppc_spefscr_regnum = -1;
3302 set_gdbarch_pc_regnum (gdbarch, 64);
3303 set_gdbarch_sp_regnum (gdbarch, 1);
3304 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
3305 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3306 if (sysv_abi && wordsize == 8)
3307 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3308 else if (sysv_abi && wordsize == 4)
3309 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3312 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
3313 set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
3316 /* Set lr_frame_offset. */
3318 tdep->lr_frame_offset = 16;
3320 tdep->lr_frame_offset = 4;
3322 tdep->lr_frame_offset = 8;
3324 if (v->arch == bfd_arch_rs6000)
3325 tdep->ppc_sr0_regnum = -1;
3326 else if (v->arch == bfd_arch_powerpc)
3330 tdep->ppc_sr0_regnum = -1;
3331 tdep->ppc_vr0_regnum = 71;
3332 tdep->ppc_vrsave_regnum = 104;
3334 case bfd_mach_ppc_7400:
3335 tdep->ppc_vr0_regnum = 119;
3336 tdep->ppc_vrsave_regnum = 152;
3338 case bfd_mach_ppc_e500:
3339 tdep->ppc_toc_regnum = -1;
3340 tdep->ppc_ev0_upper_regnum = 32;
3341 tdep->ppc_ev0_regnum = 73;
3342 tdep->ppc_ev31_regnum = 104;
3343 tdep->ppc_acc_regnum = 71;
3344 tdep->ppc_spefscr_regnum = 72;
3345 tdep->ppc_fp0_regnum = -1;
3346 tdep->ppc_fpscr_regnum = -1;
3347 tdep->ppc_sr0_regnum = -1;
3348 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3349 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3350 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
3353 case bfd_mach_ppc64:
3354 case bfd_mach_ppc_620:
3355 case bfd_mach_ppc_630:
3356 case bfd_mach_ppc_a35:
3357 case bfd_mach_ppc_rs64ii:
3358 case bfd_mach_ppc_rs64iii:
3359 /* These processor's register sets don't have segment registers. */
3360 tdep->ppc_sr0_regnum = -1;
3364 internal_error (__FILE__, __LINE__,
3365 _("rs6000_gdbarch_init: "
3366 "received unexpected BFD 'arch' value"));
3368 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3370 /* Sanity check on registers. */
3371 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
3373 /* Select instruction printer. */
3374 if (arch == bfd_arch_rs6000)
3375 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3377 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3379 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
3381 set_gdbarch_num_regs (gdbarch, v->nregs);
3382 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
3383 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3384 set_gdbarch_register_type (gdbarch, rs6000_register_type);
3385 set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p);
3387 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3388 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3389 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3390 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3391 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3392 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3393 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3395 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3397 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3398 set_gdbarch_char_signed (gdbarch, 0);
3400 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3401 if (sysv_abi && wordsize == 8)
3403 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3404 else if (!sysv_abi && wordsize == 4)
3405 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3406 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3407 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3409 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3411 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3412 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3413 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3415 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3416 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3417 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
3418 is correct for the SysV ABI when the wordsize is 8, but I'm also
3419 fairly certain that ppc_sysv_abi_push_arguments() will give even
3420 worse results since it only works for 32-bit code. So, for the moment,
3421 we're better off calling rs6000_push_arguments() since it works for
3422 64-bit code. At some point in the future, this matter needs to be
3424 if (sysv_abi && wordsize == 4)
3425 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3426 else if (sysv_abi && wordsize == 8)
3427 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3429 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3431 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
3433 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3434 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3436 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3437 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3439 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3440 for the descriptor and ".FN" for the entry-point -- a user
3441 specifying "break FN" will unexpectedly end up with a breakpoint
3442 on the descriptor and not the function. This architecture method
3443 transforms any breakpoints on descriptors into breakpoints on the
3444 corresponding entry point. */
3445 if (sysv_abi && wordsize == 8)
3446 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3448 /* Not sure on this. FIXMEmgo */
3449 set_gdbarch_frame_args_skip (gdbarch, 8);
3452 set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention);
3456 /* Handle RS/6000 function pointers (which are really function
3458 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3459 rs6000_convert_from_func_ptr_addr);
3462 /* Helpers for function argument information. */
3463 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3465 /* Hook in ABI-specific overrides, if they have been registered. */
3466 gdbarch_init_osabi (info, gdbarch);
3470 case GDB_OSABI_LINUX:
3471 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3472 have altivec registers. If not, ptrace will fail the first time it's
3473 called to access one and will not be called again. This wart will
3474 be removed when Daniel Jacobowitz's proposal for autodetecting target
3475 registers is implemented. */
3476 if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64))
3478 tdep->ppc_vr0_regnum = 71;
3479 tdep->ppc_vrsave_regnum = 104;
3482 case GDB_OSABI_NETBSD_AOUT:
3483 case GDB_OSABI_NETBSD_ELF:
3484 case GDB_OSABI_UNKNOWN:
3485 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3486 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3487 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3488 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3491 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3493 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3494 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3495 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3496 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3499 init_sim_regno_table (gdbarch);
3505 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3507 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3512 /* FIXME: Dump gdbarch_tdep. */
3515 /* Initialization code. */
3517 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3520 _initialize_rs6000_tdep (void)
3522 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3523 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);