1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 Boston, MA 02110-1301, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
52 #include "solib-svr4.h"
55 #include "gdb_assert.h"
58 #include "trad-frame.h"
59 #include "frame-unwind.h"
60 #include "frame-base.h"
62 #include "reggroups.h"
64 /* If the kernel has to deliver a signal, it pushes a sigcontext
65 structure on the stack and then calls the signal handler, passing
66 the address of the sigcontext in an argument register. Usually
67 the signal handler doesn't save this register, so we have to
68 access the sigcontext structure via an offset from the signal handler
70 The following constants were determined by experimentation on AIX 3.2. */
71 #define SIG_FRAME_PC_OFFSET 96
72 #define SIG_FRAME_LR_OFFSET 108
73 #define SIG_FRAME_FP_OFFSET 284
75 /* To be used by skip_prologue. */
77 struct rs6000_framedata
79 int offset; /* total size of frame --- the distance
80 by which we decrement sp to allocate
82 int saved_gpr; /* smallest # of saved gpr */
83 int saved_fpr; /* smallest # of saved fpr */
84 int saved_vr; /* smallest # of saved vr */
85 int saved_ev; /* smallest # of saved ev */
86 int alloca_reg; /* alloca register number (frame ptr) */
87 char frameless; /* true if frameless functions. */
88 char nosavedpc; /* true if pc not saved. */
89 int gpr_offset; /* offset of saved gprs from prev sp */
90 int fpr_offset; /* offset of saved fprs from prev sp */
91 int vr_offset; /* offset of saved vrs from prev sp */
92 int ev_offset; /* offset of saved evs from prev sp */
93 int lr_offset; /* offset of saved lr */
94 int cr_offset; /* offset of saved cr */
95 int vrsave_offset; /* offset of saved vrsave register */
98 /* Description of a single register. */
102 char *name; /* name of register */
103 unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */
104 unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */
105 unsigned char fpr; /* whether register is floating-point */
106 unsigned char pseudo; /* whether register is pseudo */
107 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
108 This is an ISA SPR number, not a GDB
112 /* Breakpoint shadows for the single step instructions will be kept here. */
114 static struct sstep_breaks
116 /* Address, or 0 if this is not in use. */
118 /* Shadow contents. */
123 /* Hook for determining the TOC address when calling functions in the
124 inferior under AIX. The initialization code in rs6000-nat.c sets
125 this hook to point to find_toc_address. */
127 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
129 /* Hook to set the current architecture when starting a child process.
130 rs6000-nat.c sets this. */
132 void (*rs6000_set_host_arch_hook) (int) = NULL;
134 /* Static function prototypes */
136 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
138 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
139 struct rs6000_framedata *);
141 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
143 altivec_register_p (int regno)
145 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
146 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
149 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
153 /* Return true if REGNO is an SPE register, false otherwise. */
155 spe_register_p (int regno)
157 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
159 /* Is it a reference to EV0 -- EV31, and do we have those? */
160 if (tdep->ppc_ev0_regnum >= 0
161 && tdep->ppc_ev31_regnum >= 0
162 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
165 /* Is it a reference to one of the raw upper GPR halves? */
166 if (tdep->ppc_ev0_upper_regnum >= 0
167 && tdep->ppc_ev0_upper_regnum <= regno
168 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
171 /* Is it a reference to the 64-bit accumulator, and do we have that? */
172 if (tdep->ppc_acc_regnum >= 0
173 && tdep->ppc_acc_regnum == regno)
176 /* Is it a reference to the SPE floating-point status and control register,
177 and do we have that? */
178 if (tdep->ppc_spefscr_regnum >= 0
179 && tdep->ppc_spefscr_regnum == regno)
186 /* Return non-zero if the architecture described by GDBARCH has
187 floating-point registers (f0 --- f31 and fpscr). */
189 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
191 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193 return (tdep->ppc_fp0_regnum >= 0
194 && tdep->ppc_fpscr_regnum >= 0);
198 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
201 This is a helper function for init_sim_regno_table, constructing
202 the table mapping GDB register numbers to sim register numbers; we
203 initialize every element in that table to -1 before we start
206 set_sim_regno (int *table, int gdb_regno, int sim_regno)
208 /* Make sure we don't try to assign any given GDB register a sim
209 register number more than once. */
210 gdb_assert (table[gdb_regno] == -1);
211 table[gdb_regno] = sim_regno;
215 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
216 numbers to simulator register numbers, based on the values placed
217 in the ARCH->tdep->ppc_foo_regnum members. */
219 init_sim_regno_table (struct gdbarch *arch)
221 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
222 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
223 const struct reg *regs = tdep->regs;
224 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
227 /* Presume that all registers not explicitly mentioned below are
228 unavailable from the sim. */
229 for (i = 0; i < total_regs; i++)
232 /* General-purpose registers. */
233 for (i = 0; i < ppc_num_gprs; i++)
234 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
236 /* Floating-point registers. */
237 if (tdep->ppc_fp0_regnum >= 0)
238 for (i = 0; i < ppc_num_fprs; i++)
239 set_sim_regno (sim_regno,
240 tdep->ppc_fp0_regnum + i,
241 sim_ppc_f0_regnum + i);
242 if (tdep->ppc_fpscr_regnum >= 0)
243 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
245 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
246 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
247 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
249 /* Segment registers. */
250 if (tdep->ppc_sr0_regnum >= 0)
251 for (i = 0; i < ppc_num_srs; i++)
252 set_sim_regno (sim_regno,
253 tdep->ppc_sr0_regnum + i,
254 sim_ppc_sr0_regnum + i);
256 /* Altivec registers. */
257 if (tdep->ppc_vr0_regnum >= 0)
259 for (i = 0; i < ppc_num_vrs; i++)
260 set_sim_regno (sim_regno,
261 tdep->ppc_vr0_regnum + i,
262 sim_ppc_vr0_regnum + i);
264 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
265 we can treat this more like the other cases. */
266 set_sim_regno (sim_regno,
267 tdep->ppc_vr0_regnum + ppc_num_vrs,
268 sim_ppc_vscr_regnum);
270 /* vsave is a special-purpose register, so the code below handles it. */
272 /* SPE APU (E500) registers. */
273 if (tdep->ppc_ev0_regnum >= 0)
274 for (i = 0; i < ppc_num_gprs; i++)
275 set_sim_regno (sim_regno,
276 tdep->ppc_ev0_regnum + i,
277 sim_ppc_ev0_regnum + i);
278 if (tdep->ppc_ev0_upper_regnum >= 0)
279 for (i = 0; i < ppc_num_gprs; i++)
280 set_sim_regno (sim_regno,
281 tdep->ppc_ev0_upper_regnum + i,
282 sim_ppc_rh0_regnum + i);
283 if (tdep->ppc_acc_regnum >= 0)
284 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
285 /* spefscr is a special-purpose register, so the code below handles it. */
287 /* Now handle all special-purpose registers. Verify that they
288 haven't mistakenly been assigned numbers by any of the above
290 for (i = 0; i < total_regs; i++)
291 if (regs[i].spr_num >= 0)
292 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
294 /* Drop the initialized array into place. */
295 tdep->sim_regno = sim_regno;
299 /* Given a GDB register number REG, return the corresponding SIM
302 rs6000_register_sim_regno (int reg)
304 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
307 gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
308 sim_regno = tdep->sim_regno[reg];
313 return LEGACY_SIM_REGNO_IGNORE;
318 /* Register set support functions. */
321 ppc_supply_reg (struct regcache *regcache, int regnum,
322 const gdb_byte *regs, size_t offset)
324 if (regnum != -1 && offset != -1)
325 regcache_raw_supply (regcache, regnum, regs + offset);
329 ppc_collect_reg (const struct regcache *regcache, int regnum,
330 gdb_byte *regs, size_t offset)
332 if (regnum != -1 && offset != -1)
333 regcache_raw_collect (regcache, regnum, regs + offset);
336 /* Supply register REGNUM in the general-purpose register set REGSET
337 from the buffer specified by GREGS and LEN to register cache
338 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
341 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
342 int regnum, const void *gregs, size_t len)
344 struct gdbarch *gdbarch = get_regcache_arch (regcache);
345 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
346 const struct ppc_reg_offsets *offsets = regset->descr;
350 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
351 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
354 if (regnum == -1 || regnum == i)
355 ppc_supply_reg (regcache, i, gregs, offset);
358 if (regnum == -1 || regnum == PC_REGNUM)
359 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
360 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
361 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
362 gregs, offsets->ps_offset);
363 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
364 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
365 gregs, offsets->cr_offset);
366 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
367 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
368 gregs, offsets->lr_offset);
369 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
370 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
371 gregs, offsets->ctr_offset);
372 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
373 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
374 gregs, offsets->cr_offset);
375 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
376 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
379 /* Supply register REGNUM in the floating-point register set REGSET
380 from the buffer specified by FPREGS and LEN to register cache
381 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
384 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
385 int regnum, const void *fpregs, size_t len)
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
389 const struct ppc_reg_offsets *offsets = regset->descr;
393 gdb_assert (ppc_floating_point_unit_p (gdbarch));
395 offset = offsets->f0_offset;
396 for (i = tdep->ppc_fp0_regnum;
397 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
400 if (regnum == -1 || regnum == i)
401 ppc_supply_reg (regcache, i, fpregs, offset);
404 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
405 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
406 fpregs, offsets->fpscr_offset);
409 /* Collect register REGNUM in the general-purpose register set
410 REGSET. from register cache REGCACHE into the buffer specified by
411 GREGS and LEN. If REGNUM is -1, do this for all registers in
415 ppc_collect_gregset (const struct regset *regset,
416 const struct regcache *regcache,
417 int regnum, void *gregs, size_t len)
419 struct gdbarch *gdbarch = get_regcache_arch (regcache);
420 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
421 const struct ppc_reg_offsets *offsets = regset->descr;
425 offset = offsets->r0_offset;
426 for (i = tdep->ppc_gp0_regnum;
427 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
430 if (regnum == -1 || regnum == i)
431 ppc_collect_reg (regcache, i, gregs, offset);
434 if (regnum == -1 || regnum == PC_REGNUM)
435 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
436 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
437 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
438 gregs, offsets->ps_offset);
439 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
440 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
441 gregs, offsets->cr_offset);
442 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
443 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
444 gregs, offsets->lr_offset);
445 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
446 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
447 gregs, offsets->ctr_offset);
448 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
449 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
450 gregs, offsets->xer_offset);
451 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
452 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
453 gregs, offsets->mq_offset);
456 /* Collect register REGNUM in the floating-point register set
457 REGSET. from register cache REGCACHE into the buffer specified by
458 FPREGS and LEN. If REGNUM is -1, do this for all registers in
462 ppc_collect_fpregset (const struct regset *regset,
463 const struct regcache *regcache,
464 int regnum, void *fpregs, size_t len)
466 struct gdbarch *gdbarch = get_regcache_arch (regcache);
467 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468 const struct ppc_reg_offsets *offsets = regset->descr;
472 gdb_assert (ppc_floating_point_unit_p (gdbarch));
474 offset = offsets->f0_offset;
475 for (i = tdep->ppc_fp0_regnum;
476 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
479 if (regnum == -1 || regnum == i)
480 ppc_collect_reg (regcache, i, fpregs, offset);
483 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
484 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
485 fpregs, offsets->fpscr_offset);
489 /* Read a LEN-byte address from debugged memory address MEMADDR. */
492 read_memory_addr (CORE_ADDR memaddr, int len)
494 return read_memory_unsigned_integer (memaddr, len);
498 rs6000_skip_prologue (CORE_ADDR pc)
500 struct rs6000_framedata frame;
501 pc = skip_prologue (pc, 0, &frame);
506 insn_changes_sp_or_jumps (unsigned long insn)
508 int opcode = (insn >> 26) & 0x03f;
509 int sd = (insn >> 21) & 0x01f;
510 int a = (insn >> 16) & 0x01f;
511 int subcode = (insn >> 1) & 0x3ff;
513 /* Changes the stack pointer. */
515 /* NOTE: There are many ways to change the value of a given register.
516 The ways below are those used when the register is R1, the SP,
517 in a funtion's epilogue. */
519 if (opcode == 31 && subcode == 444 && a == 1)
520 return 1; /* mr R1,Rn */
521 if (opcode == 14 && sd == 1)
522 return 1; /* addi R1,Rn,simm */
523 if (opcode == 58 && sd == 1)
524 return 1; /* ld R1,ds(Rn) */
526 /* Transfers control. */
532 if (opcode == 19 && subcode == 16)
534 if (opcode == 19 && subcode == 528)
535 return 1; /* bcctr */
540 /* Return true if we are in the function's epilogue, i.e. after the
541 instruction that destroyed the function's stack frame.
543 1) scan forward from the point of execution:
544 a) If you find an instruction that modifies the stack pointer
545 or transfers control (except a return), execution is not in
547 b) Stop scanning if you find a return instruction or reach the
548 end of the function or reach the hard limit for the size of
550 2) scan backward from the point of execution:
551 a) If you find an instruction that modifies the stack pointer,
552 execution *is* in an epilogue, return.
553 b) Stop scanning if you reach an instruction that transfers
554 control or the beginning of the function or reach the hard
555 limit for the size of an epilogue. */
558 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
560 bfd_byte insn_buf[PPC_INSN_SIZE];
561 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
563 struct frame_info *curfrm;
565 /* Find the search limits based on function boundaries and hard limit. */
567 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
570 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
571 if (epilogue_start < func_start) epilogue_start = func_start;
573 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
574 if (epilogue_end > func_end) epilogue_end = func_end;
576 curfrm = get_current_frame ();
578 /* Scan forward until next 'blr'. */
580 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
582 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
584 insn = extract_signed_integer (insn_buf, PPC_INSN_SIZE);
585 if (insn == 0x4e800020)
587 if (insn_changes_sp_or_jumps (insn))
591 /* Scan backward until adjustment to stack pointer (R1). */
593 for (scan_pc = pc - PPC_INSN_SIZE;
594 scan_pc >= epilogue_start;
595 scan_pc -= PPC_INSN_SIZE)
597 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
599 insn = extract_signed_integer (insn_buf, PPC_INSN_SIZE);
600 if (insn_changes_sp_or_jumps (insn))
608 /* Fill in fi->saved_regs */
610 struct frame_extra_info
612 /* Functions calling alloca() change the value of the stack
613 pointer. We need to use initial stack pointer (which is saved in
614 r31 by gcc) in such cases. If a compiler emits traceback table,
615 then we should use the alloca register specified in traceback
617 CORE_ADDR initial_sp; /* initial stack pointer. */
620 /* Get the ith function argument for the current function. */
622 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
625 return get_frame_register_unsigned (frame, 3 + argi);
628 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
631 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
638 absolute = (int) ((instr >> 1) & 1);
643 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
647 dest = pc + immediate;
651 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
655 dest = pc + immediate;
659 ext_op = (instr >> 1) & 0x3ff;
661 if (ext_op == 16) /* br conditional register */
663 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
665 /* If we are about to return from a signal handler, dest is
666 something like 0x3c90. The current frame is a signal handler
667 caller frame, upon completion of the sigreturn system call
668 execution will return to the saved PC in the frame. */
669 if (dest < TEXT_SEGMENT_BASE)
671 struct frame_info *fi;
673 fi = get_current_frame ();
675 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
676 gdbarch_tdep (current_gdbarch)->wordsize);
680 else if (ext_op == 528) /* br cond to count reg */
682 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
684 /* If we are about to execute a system call, dest is something
685 like 0x22fc or 0x3b00. Upon completion the system call
686 will return to the address in the link register. */
687 if (dest < TEXT_SEGMENT_BASE)
688 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
697 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
701 /* Sequence of bytes for breakpoint instruction. */
703 const static unsigned char *
704 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
706 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
707 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
709 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
710 return big_breakpoint;
712 return little_breakpoint;
716 /* AIX does not support PT_STEP. Simulate it. */
719 rs6000_software_single_step (enum target_signal signal,
720 int insert_breakpoints_p)
724 const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
730 if (insert_breakpoints_p)
735 insn = read_memory_integer (loc, 4);
737 breaks[0] = loc + breakp_sz;
739 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
741 /* Don't put two breakpoints on the same address. */
742 if (breaks[1] == breaks[0])
745 stepBreaks[1].address = 0;
747 for (ii = 0; ii < 2; ++ii)
750 /* ignore invalid breakpoint. */
751 if (breaks[ii] == -1)
753 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
754 stepBreaks[ii].address = breaks[ii];
761 /* remove step breakpoints. */
762 for (ii = 0; ii < 2; ++ii)
763 if (stepBreaks[ii].address != 0)
764 target_remove_breakpoint (stepBreaks[ii].address,
765 stepBreaks[ii].data);
767 errno = 0; /* FIXME, don't ignore errors! */
768 /* What errors? {read,write}_memory call error(). */
772 /* return pc value after skipping a function prologue and also return
773 information about a function frame.
775 in struct rs6000_framedata fdata:
776 - frameless is TRUE, if function does not have a frame.
777 - nosavedpc is TRUE, if function does not save %pc value in its frame.
778 - offset is the initial size of this stack frame --- the amount by
779 which we decrement the sp to allocate the frame.
780 - saved_gpr is the number of the first saved gpr.
781 - saved_fpr is the number of the first saved fpr.
782 - saved_vr is the number of the first saved vr.
783 - saved_ev is the number of the first saved ev.
784 - alloca_reg is the number of the register used for alloca() handling.
786 - gpr_offset is the offset of the first saved gpr from the previous frame.
787 - fpr_offset is the offset of the first saved fpr from the previous frame.
788 - vr_offset is the offset of the first saved vr from the previous frame.
789 - ev_offset is the offset of the first saved ev from the previous frame.
790 - lr_offset is the offset of the saved lr
791 - cr_offset is the offset of the saved cr
792 - vrsave_offset is the offset of the saved vrsave register
795 #define SIGNED_SHORT(x) \
796 ((sizeof (short) == 2) \
797 ? ((int)(short)(x)) \
798 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
800 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
802 /* Limit the number of skipped non-prologue instructions, as the examining
803 of the prologue is expensive. */
804 static int max_skip_non_prologue_insns = 10;
806 /* Given PC representing the starting address of a function, and
807 LIM_PC which is the (sloppy) limit to which to scan when looking
808 for a prologue, attempt to further refine this limit by using
809 the line data in the symbol table. If successful, a better guess
810 on where the prologue ends is returned, otherwise the previous
811 value of lim_pc is returned. */
813 /* FIXME: cagney/2004-02-14: This function and logic have largely been
814 superseded by skip_prologue_using_sal. */
817 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
819 struct symtab_and_line prologue_sal;
821 prologue_sal = find_pc_line (pc, 0);
822 if (prologue_sal.line != 0)
825 CORE_ADDR addr = prologue_sal.end;
827 /* Handle the case in which compiler's optimizer/scheduler
828 has moved instructions into the prologue. We scan ahead
829 in the function looking for address ranges whose corresponding
830 line number is less than or equal to the first one that we
831 found for the function. (It can be less than when the
832 scheduler puts a body instruction before the first prologue
834 for (i = 2 * max_skip_non_prologue_insns;
835 i > 0 && (lim_pc == 0 || addr < lim_pc);
838 struct symtab_and_line sal;
840 sal = find_pc_line (addr, 0);
843 if (sal.line <= prologue_sal.line
844 && sal.symtab == prologue_sal.symtab)
851 if (lim_pc == 0 || prologue_sal.end < lim_pc)
852 lim_pc = prologue_sal.end;
857 /* Return nonzero if the given instruction OP can be part of the prologue
858 of a function and saves a parameter on the stack. FRAMEP should be
859 set if one of the previous instructions in the function has set the
863 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
865 /* Move parameters from argument registers to temporary register. */
866 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
868 /* Rx must be scratch register r0. */
869 const int rx_regno = (op >> 16) & 31;
870 /* Ry: Only r3 - r10 are used for parameter passing. */
871 const int ry_regno = GET_SRC_REG (op);
873 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
875 *r0_contains_arg = 1;
882 /* Save a General Purpose Register on stack. */
884 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
885 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
887 /* Rx: Only r3 - r10 are used for parameter passing. */
888 const int rx_regno = GET_SRC_REG (op);
890 return (rx_regno >= 3 && rx_regno <= 10);
893 /* Save a General Purpose Register on stack via the Frame Pointer. */
896 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
897 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
898 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
900 /* Rx: Usually, only r3 - r10 are used for parameter passing.
901 However, the compiler sometimes uses r0 to hold an argument. */
902 const int rx_regno = GET_SRC_REG (op);
904 return ((rx_regno >= 3 && rx_regno <= 10)
905 || (rx_regno == 0 && *r0_contains_arg));
908 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
910 /* Only f2 - f8 are used for parameter passing. */
911 const int src_regno = GET_SRC_REG (op);
913 return (src_regno >= 2 && src_regno <= 8);
916 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
918 /* Only f2 - f8 are used for parameter passing. */
919 const int src_regno = GET_SRC_REG (op);
921 return (src_regno >= 2 && src_regno <= 8);
924 /* Not an insn that saves a parameter on stack. */
929 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
931 CORE_ADDR orig_pc = pc;
932 CORE_ADDR last_prologue_pc = pc;
933 CORE_ADDR li_found_pc = 0;
937 long vr_saved_offset = 0;
946 int minimal_toc_loaded = 0;
947 int prev_insn_was_prologue_insn = 1;
948 int num_skip_non_prologue_insns = 0;
949 int r0_contains_arg = 0;
950 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
951 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
953 /* Attempt to find the end of the prologue when no limit is specified.
954 Note that refine_prologue_limit() has been written so that it may
955 be used to "refine" the limits of non-zero PC values too, but this
956 is only safe if we 1) trust the line information provided by the
957 compiler and 2) iterate enough to actually find the end of the
960 It may become a good idea at some point (for both performance and
961 accuracy) to unconditionally call refine_prologue_limit(). But,
962 until we can make a clear determination that this is beneficial,
963 we'll play it safe and only use it to obtain a limit when none
964 has been specified. */
966 lim_pc = refine_prologue_limit (pc, lim_pc);
968 memset (fdata, 0, sizeof (struct rs6000_framedata));
969 fdata->saved_gpr = -1;
970 fdata->saved_fpr = -1;
971 fdata->saved_vr = -1;
972 fdata->saved_ev = -1;
973 fdata->alloca_reg = -1;
974 fdata->frameless = 1;
975 fdata->nosavedpc = 1;
979 /* Sometimes it isn't clear if an instruction is a prologue
980 instruction or not. When we encounter one of these ambiguous
981 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
982 Otherwise, we'll assume that it really is a prologue instruction. */
983 if (prev_insn_was_prologue_insn)
984 last_prologue_pc = pc;
986 /* Stop scanning if we've hit the limit. */
987 if (lim_pc != 0 && pc >= lim_pc)
990 prev_insn_was_prologue_insn = 1;
992 /* Fetch the instruction and convert it to an integer. */
993 if (target_read_memory (pc, buf, 4))
995 op = extract_signed_integer (buf, 4);
997 if ((op & 0xfc1fffff) == 0x7c0802a6)
999 /* Since shared library / PIC code, which needs to get its
1000 address at runtime, can appear to save more than one link
1014 remember just the first one, but skip over additional
1017 lr_reg = (op & 0x03e00000);
1019 r0_contains_arg = 0;
1022 else if ((op & 0xfc1fffff) == 0x7c000026)
1024 cr_reg = (op & 0x03e00000);
1026 r0_contains_arg = 0;
1030 else if ((op & 0xfc1f0000) == 0xd8010000)
1031 { /* stfd Rx,NUM(r1) */
1032 reg = GET_SRC_REG (op);
1033 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1035 fdata->saved_fpr = reg;
1036 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1041 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1042 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1043 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1044 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1047 reg = GET_SRC_REG (op);
1048 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1050 fdata->saved_gpr = reg;
1051 if ((op & 0xfc1f0003) == 0xf8010000)
1053 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1058 else if ((op & 0xffff0000) == 0x60000000)
1061 /* Allow nops in the prologue, but do not consider them to
1062 be part of the prologue unless followed by other prologue
1064 prev_insn_was_prologue_insn = 0;
1068 else if ((op & 0xffff0000) == 0x3c000000)
1069 { /* addis 0,0,NUM, used
1070 for >= 32k frames */
1071 fdata->offset = (op & 0x0000ffff) << 16;
1072 fdata->frameless = 0;
1073 r0_contains_arg = 0;
1077 else if ((op & 0xffff0000) == 0x60000000)
1078 { /* ori 0,0,NUM, 2nd ha
1079 lf of >= 32k frames */
1080 fdata->offset |= (op & 0x0000ffff);
1081 fdata->frameless = 0;
1082 r0_contains_arg = 0;
1086 else if (lr_reg >= 0 &&
1087 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1088 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1089 /* stw Rx, NUM(r1) */
1090 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1091 /* stwu Rx, NUM(r1) */
1092 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1093 { /* where Rx == lr */
1094 fdata->lr_offset = offset;
1095 fdata->nosavedpc = 0;
1096 /* Invalidate lr_reg, but don't set it to -1.
1097 That would mean that it had never been set. */
1099 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1100 (op & 0xfc000000) == 0x90000000) /* stw */
1102 /* Does not update r1, so add displacement to lr_offset. */
1103 fdata->lr_offset += SIGNED_SHORT (op);
1108 else if (cr_reg >= 0 &&
1109 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1110 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1111 /* stw Rx, NUM(r1) */
1112 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1113 /* stwu Rx, NUM(r1) */
1114 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1115 { /* where Rx == cr */
1116 fdata->cr_offset = offset;
1117 /* Invalidate cr_reg, but don't set it to -1.
1118 That would mean that it had never been set. */
1120 if ((op & 0xfc000003) == 0xf8000000 ||
1121 (op & 0xfc000000) == 0x90000000)
1123 /* Does not update r1, so add displacement to cr_offset. */
1124 fdata->cr_offset += SIGNED_SHORT (op);
1129 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1131 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1132 prediction bits. If the LR has already been saved, we can
1136 else if (op == 0x48000005)
1142 else if (op == 0x48000004)
1147 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1148 in V.4 -mminimal-toc */
1149 (op & 0xffff0000) == 0x3bde0000)
1150 { /* addi 30,30,foo@l */
1154 else if ((op & 0xfc000001) == 0x48000001)
1158 fdata->frameless = 0;
1159 /* Don't skip over the subroutine call if it is not within
1160 the first three instructions of the prologue and either
1161 we have no line table information or the line info tells
1162 us that the subroutine call is not part of the line
1163 associated with the prologue. */
1164 if ((pc - orig_pc) > 8)
1166 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1167 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1169 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1173 op = read_memory_integer (pc + 4, 4);
1175 /* At this point, make sure this is not a trampoline
1176 function (a function that simply calls another functions,
1177 and nothing else). If the next is not a nop, this branch
1178 was part of the function prologue. */
1180 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1181 break; /* don't skip over
1186 /* update stack pointer */
1187 else if ((op & 0xfc1f0000) == 0x94010000)
1188 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1189 fdata->frameless = 0;
1190 fdata->offset = SIGNED_SHORT (op);
1191 offset = fdata->offset;
1194 else if ((op & 0xfc1f016a) == 0x7c01016e)
1195 { /* stwux rX,r1,rY */
1196 /* no way to figure out what r1 is going to be */
1197 fdata->frameless = 0;
1198 offset = fdata->offset;
1201 else if ((op & 0xfc1f0003) == 0xf8010001)
1202 { /* stdu rX,NUM(r1) */
1203 fdata->frameless = 0;
1204 fdata->offset = SIGNED_SHORT (op & ~3UL);
1205 offset = fdata->offset;
1208 else if ((op & 0xfc1f016a) == 0x7c01016a)
1209 { /* stdux rX,r1,rY */
1210 /* no way to figure out what r1 is going to be */
1211 fdata->frameless = 0;
1212 offset = fdata->offset;
1215 /* Load up minimal toc pointer */
1216 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1217 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1218 && !minimal_toc_loaded)
1220 minimal_toc_loaded = 1;
1223 /* move parameters from argument registers to local variable
1226 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1227 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1228 (((op >> 21) & 31) <= 10) &&
1229 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1233 /* store parameters in stack */
1235 /* Move parameters from argument registers to temporary register. */
1236 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1240 /* Set up frame pointer */
1242 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1243 || op == 0x7c3f0b78)
1245 fdata->frameless = 0;
1247 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1250 /* Another way to set up the frame pointer. */
1252 else if ((op & 0xfc1fffff) == 0x38010000)
1253 { /* addi rX, r1, 0x0 */
1254 fdata->frameless = 0;
1256 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1257 + ((op & ~0x38010000) >> 21));
1260 /* AltiVec related instructions. */
1261 /* Store the vrsave register (spr 256) in another register for
1262 later manipulation, or load a register into the vrsave
1263 register. 2 instructions are used: mfvrsave and
1264 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1265 and mtspr SPR256, Rn. */
1266 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1267 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1268 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1270 vrsave_reg = GET_SRC_REG (op);
1273 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1277 /* Store the register where vrsave was saved to onto the stack:
1278 rS is the register where vrsave was stored in a previous
1280 /* 100100 sssss 00001 dddddddd dddddddd */
1281 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1283 if (vrsave_reg == GET_SRC_REG (op))
1285 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1290 /* Compute the new value of vrsave, by modifying the register
1291 where vrsave was saved to. */
1292 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1293 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1297 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1298 in a pair of insns to save the vector registers on the
1300 /* 001110 00000 00000 iiii iiii iiii iiii */
1301 /* 001110 01110 00000 iiii iiii iiii iiii */
1302 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1303 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1305 if ((op & 0xffff0000) == 0x38000000)
1306 r0_contains_arg = 0;
1308 vr_saved_offset = SIGNED_SHORT (op);
1310 /* This insn by itself is not part of the prologue, unless
1311 if part of the pair of insns mentioned above. So do not
1312 record this insn as part of the prologue yet. */
1313 prev_insn_was_prologue_insn = 0;
1315 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1316 /* 011111 sssss 11111 00000 00111001110 */
1317 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1319 if (pc == (li_found_pc + 4))
1321 vr_reg = GET_SRC_REG (op);
1322 /* If this is the first vector reg to be saved, or if
1323 it has a lower number than others previously seen,
1324 reupdate the frame info. */
1325 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1327 fdata->saved_vr = vr_reg;
1328 fdata->vr_offset = vr_saved_offset + offset;
1330 vr_saved_offset = -1;
1335 /* End AltiVec related instructions. */
1337 /* Start BookE related instructions. */
1338 /* Store gen register S at (r31+uimm).
1339 Any register less than r13 is volatile, so we don't care. */
1340 /* 000100 sssss 11111 iiiii 01100100001 */
1341 else if (arch_info->mach == bfd_mach_ppc_e500
1342 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1344 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1347 ev_reg = GET_SRC_REG (op);
1348 imm = (op >> 11) & 0x1f;
1349 ev_offset = imm * 8;
1350 /* If this is the first vector reg to be saved, or if
1351 it has a lower number than others previously seen,
1352 reupdate the frame info. */
1353 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1355 fdata->saved_ev = ev_reg;
1356 fdata->ev_offset = ev_offset + offset;
1361 /* Store gen register rS at (r1+rB). */
1362 /* 000100 sssss 00001 bbbbb 01100100000 */
1363 else if (arch_info->mach == bfd_mach_ppc_e500
1364 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1366 if (pc == (li_found_pc + 4))
1368 ev_reg = GET_SRC_REG (op);
1369 /* If this is the first vector reg to be saved, or if
1370 it has a lower number than others previously seen,
1371 reupdate the frame info. */
1372 /* We know the contents of rB from the previous instruction. */
1373 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1375 fdata->saved_ev = ev_reg;
1376 fdata->ev_offset = vr_saved_offset + offset;
1378 vr_saved_offset = -1;
1384 /* Store gen register r31 at (rA+uimm). */
1385 /* 000100 11111 aaaaa iiiii 01100100001 */
1386 else if (arch_info->mach == bfd_mach_ppc_e500
1387 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1389 /* Wwe know that the source register is 31 already, but
1390 it can't hurt to compute it. */
1391 ev_reg = GET_SRC_REG (op);
1392 ev_offset = ((op >> 11) & 0x1f) * 8;
1393 /* If this is the first vector reg to be saved, or if
1394 it has a lower number than others previously seen,
1395 reupdate the frame info. */
1396 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1398 fdata->saved_ev = ev_reg;
1399 fdata->ev_offset = ev_offset + offset;
1404 /* Store gen register S at (r31+r0).
1405 Store param on stack when offset from SP bigger than 4 bytes. */
1406 /* 000100 sssss 11111 00000 01100100000 */
1407 else if (arch_info->mach == bfd_mach_ppc_e500
1408 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1410 if (pc == (li_found_pc + 4))
1412 if ((op & 0x03e00000) >= 0x01a00000)
1414 ev_reg = GET_SRC_REG (op);
1415 /* If this is the first vector reg to be saved, or if
1416 it has a lower number than others previously seen,
1417 reupdate the frame info. */
1418 /* We know the contents of r0 from the previous
1420 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1422 fdata->saved_ev = ev_reg;
1423 fdata->ev_offset = vr_saved_offset + offset;
1427 vr_saved_offset = -1;
1432 /* End BookE related instructions. */
1436 /* Not a recognized prologue instruction.
1437 Handle optimizer code motions into the prologue by continuing
1438 the search if we have no valid frame yet or if the return
1439 address is not yet saved in the frame. */
1440 if (fdata->frameless == 0
1441 && (lr_reg == -1 || fdata->nosavedpc == 0))
1444 if (op == 0x4e800020 /* blr */
1445 || op == 0x4e800420) /* bctr */
1446 /* Do not scan past epilogue in frameless functions or
1449 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1450 /* Never skip branches. */
1453 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1454 /* Do not scan too many insns, scanning insns is expensive with
1458 /* Continue scanning. */
1459 prev_insn_was_prologue_insn = 0;
1465 /* I have problems with skipping over __main() that I need to address
1466 * sometime. Previously, I used to use misc_function_vector which
1467 * didn't work as well as I wanted to be. -MGO */
1469 /* If the first thing after skipping a prolog is a branch to a function,
1470 this might be a call to an initializer in main(), introduced by gcc2.
1471 We'd like to skip over it as well. Fortunately, xlc does some extra
1472 work before calling a function right after a prologue, thus we can
1473 single out such gcc2 behaviour. */
1476 if ((op & 0xfc000001) == 0x48000001)
1477 { /* bl foo, an initializer function? */
1478 op = read_memory_integer (pc + 4, 4);
1480 if (op == 0x4def7b82)
1481 { /* cror 0xf, 0xf, 0xf (nop) */
1483 /* Check and see if we are in main. If so, skip over this
1484 initializer function as well. */
1486 tmp = find_pc_misc_function (pc);
1488 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1494 fdata->offset = -fdata->offset;
1495 return last_prologue_pc;
1499 /*************************************************************************
1500 Support for creating pushing a dummy frame into the stack, and popping
1502 *************************************************************************/
1505 /* All the ABI's require 16 byte alignment. */
1507 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1509 return (addr & -16);
1512 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1513 the first eight words of the argument list (that might be less than
1514 eight parameters if some parameters occupy more than one word) are
1515 passed in r3..r10 registers. float and double parameters are
1516 passed in fpr's, in addition to that. Rest of the parameters if any
1517 are passed in user stack. There might be cases in which half of the
1518 parameter is copied into registers, the other half is pushed into
1521 Stack must be aligned on 64-bit boundaries when synthesizing
1524 If the function is returning a structure, then the return address is passed
1525 in r3, then the first 7 words of the parameters can be passed in registers,
1526 starting from r4. */
1529 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1530 struct regcache *regcache, CORE_ADDR bp_addr,
1531 int nargs, struct value **args, CORE_ADDR sp,
1532 int struct_return, CORE_ADDR struct_addr)
1534 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1537 int argno; /* current argument number */
1538 int argbytes; /* current argument byte */
1539 gdb_byte tmp_buffer[50];
1540 int f_argno = 0; /* current floating point argno */
1541 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1542 CORE_ADDR func_addr = find_function_addr (function, NULL);
1544 struct value *arg = 0;
1549 /* The calling convention this function implements assumes the
1550 processor has floating-point registers. We shouldn't be using it
1551 on PPC variants that lack them. */
1552 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1554 /* The first eight words of ther arguments are passed in registers.
1555 Copy them appropriately. */
1558 /* If the function is returning a `struct', then the first word
1559 (which will be passed in r3) is used for struct return address.
1560 In that case we should advance one word and start from r4
1561 register to copy parameters. */
1564 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1570 effectively indirect call... gcc does...
1572 return_val example( float, int);
1575 float in fp0, int in r3
1576 offset of stack on overflow 8/16
1577 for varargs, must go by type.
1579 float in r3&r4, int in r5
1580 offset of stack on overflow different
1582 return in r3 or f0. If no float, must study how gcc emulates floats;
1583 pay attention to arg promotion.
1584 User may have to cast\args to handle promotion correctly
1585 since gdb won't know if prototype supplied or not.
1588 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1590 int reg_size = register_size (current_gdbarch, ii + 3);
1593 type = check_typedef (value_type (arg));
1594 len = TYPE_LENGTH (type);
1596 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1599 /* Floating point arguments are passed in fpr's, as well as gpr's.
1600 There are 13 fpr's reserved for passing parameters. At this point
1601 there is no way we would run out of them. */
1603 gdb_assert (len <= 8);
1605 regcache_cooked_write (regcache,
1606 tdep->ppc_fp0_regnum + 1 + f_argno,
1607 value_contents (arg));
1614 /* Argument takes more than one register. */
1615 while (argbytes < len)
1617 gdb_byte word[MAX_REGISTER_SIZE];
1618 memset (word, 0, reg_size);
1620 ((char *) value_contents (arg)) + argbytes,
1621 (len - argbytes) > reg_size
1622 ? reg_size : len - argbytes);
1623 regcache_cooked_write (regcache,
1624 tdep->ppc_gp0_regnum + 3 + ii,
1626 ++ii, argbytes += reg_size;
1629 goto ran_out_of_registers_for_arguments;
1636 /* Argument can fit in one register. No problem. */
1637 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1638 gdb_byte word[MAX_REGISTER_SIZE];
1640 memset (word, 0, reg_size);
1641 memcpy (word, value_contents (arg), len);
1642 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1647 ran_out_of_registers_for_arguments:
1649 saved_sp = read_sp ();
1651 /* Location for 8 parameters are always reserved. */
1654 /* Another six words for back chain, TOC register, link register, etc. */
1657 /* Stack pointer must be quadword aligned. */
1660 /* If there are more arguments, allocate space for them in
1661 the stack, then push them starting from the ninth one. */
1663 if ((argno < nargs) || argbytes)
1669 space += ((len - argbytes + 3) & -4);
1675 for (; jj < nargs; ++jj)
1677 struct value *val = args[jj];
1678 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
1681 /* Add location required for the rest of the parameters. */
1682 space = (space + 15) & -16;
1685 /* This is another instance we need to be concerned about
1686 securing our stack space. If we write anything underneath %sp
1687 (r1), we might conflict with the kernel who thinks he is free
1688 to use this area. So, update %sp first before doing anything
1691 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1693 /* If the last argument copied into the registers didn't fit there
1694 completely, push the rest of it into stack. */
1698 write_memory (sp + 24 + (ii * 4),
1699 value_contents (arg) + argbytes,
1702 ii += ((len - argbytes + 3) & -4) / 4;
1705 /* Push the rest of the arguments into stack. */
1706 for (; argno < nargs; ++argno)
1710 type = check_typedef (value_type (arg));
1711 len = TYPE_LENGTH (type);
1714 /* Float types should be passed in fpr's, as well as in the
1716 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1719 gdb_assert (len <= 8);
1721 regcache_cooked_write (regcache,
1722 tdep->ppc_fp0_regnum + 1 + f_argno,
1723 value_contents (arg));
1727 write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
1728 ii += ((len + 3) & -4) / 4;
1732 /* Set the stack pointer. According to the ABI, the SP is meant to
1733 be set _before_ the corresponding stack space is used. On AIX,
1734 this even applies when the target has been completely stopped!
1735 Not doing this can lead to conflicts with the kernel which thinks
1736 that it still has control over this not-yet-allocated stack
1738 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1740 /* Set back chain properly. */
1741 store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
1742 write_memory (sp, tmp_buffer, wordsize);
1744 /* Point the inferior function call's return address at the dummy's
1746 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1748 /* Set the TOC register, get the value from the objfile reader
1749 which, in turn, gets it from the VMAP table. */
1750 if (rs6000_find_toc_address_hook != NULL)
1752 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1753 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1756 target_store_registers (-1);
1760 /* PowerOpen always puts structures in memory. Vectors, which were
1761 added later, do get returned in a register though. */
1764 rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1766 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1767 && TYPE_VECTOR (value_type))
1773 rs6000_extract_return_value (struct type *valtype, gdb_byte *regbuf,
1777 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1779 /* The calling convention this function implements assumes the
1780 processor has floating-point registers. We shouldn't be using it
1781 on PPC variants that lack them. */
1782 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1784 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1787 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1788 We need to truncate the return value into float size (4 byte) if
1791 convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
1792 (tdep->ppc_fp0_regnum + 1)],
1793 builtin_type_double,
1797 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1798 && TYPE_LENGTH (valtype) == 16
1799 && TYPE_VECTOR (valtype))
1801 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1802 TYPE_LENGTH (valtype));
1806 /* return value is copied starting from r3. */
1807 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1808 && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3))
1809 offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype);
1812 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
1813 TYPE_LENGTH (valtype));
1817 /* Return whether handle_inferior_event() should proceed through code
1818 starting at PC in function NAME when stepping.
1820 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1821 handle memory references that are too distant to fit in instructions
1822 generated by the compiler. For example, if 'foo' in the following
1827 is greater than 32767, the linker might replace the lwz with a branch to
1828 somewhere in @FIX1 that does the load in 2 instructions and then branches
1829 back to where execution should continue.
1831 GDB should silently step over @FIX code, just like AIX dbx does.
1832 Unfortunately, the linker uses the "b" instruction for the
1833 branches, meaning that the link register doesn't get set.
1834 Therefore, GDB's usual step_over_function () mechanism won't work.
1836 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1837 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1841 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1843 return name && !strncmp (name, "@FIX", 4);
1846 /* Skip code that the user doesn't want to see when stepping:
1848 1. Indirect function calls use a piece of trampoline code to do context
1849 switching, i.e. to set the new TOC table. Skip such code if we are on
1850 its first instruction (as when we have single-stepped to here).
1852 2. Skip shared library trampoline code (which is different from
1853 indirect function call trampolines).
1855 3. Skip bigtoc fixup code.
1857 Result is desired PC to step until, or NULL if we are not in
1858 code that should be skipped. */
1861 rs6000_skip_trampoline_code (CORE_ADDR pc)
1863 unsigned int ii, op;
1865 CORE_ADDR solib_target_pc;
1866 struct minimal_symbol *msymbol;
1868 static unsigned trampoline_code[] =
1870 0x800b0000, /* l r0,0x0(r11) */
1871 0x90410014, /* st r2,0x14(r1) */
1872 0x7c0903a6, /* mtctr r0 */
1873 0x804b0004, /* l r2,0x4(r11) */
1874 0x816b0008, /* l r11,0x8(r11) */
1875 0x4e800420, /* bctr */
1876 0x4e800020, /* br */
1880 /* Check for bigtoc fixup code. */
1881 msymbol = lookup_minimal_symbol_by_pc (pc);
1883 && rs6000_in_solib_return_trampoline (pc,
1884 DEPRECATED_SYMBOL_NAME (msymbol)))
1886 /* Double-check that the third instruction from PC is relative "b". */
1887 op = read_memory_integer (pc + 8, 4);
1888 if ((op & 0xfc000003) == 0x48000000)
1890 /* Extract bits 6-29 as a signed 24-bit relative word address and
1891 add it to the containing PC. */
1892 rel = ((int)(op << 6) >> 6);
1893 return pc + 8 + rel;
1897 /* If pc is in a shared library trampoline, return its target. */
1898 solib_target_pc = find_solib_trampoline_target (pc);
1899 if (solib_target_pc)
1900 return solib_target_pc;
1902 for (ii = 0; trampoline_code[ii]; ++ii)
1904 op = read_memory_integer (pc + (ii * 4), 4);
1905 if (op != trampoline_code[ii])
1908 ii = read_register (11); /* r11 holds destination addr */
1909 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1913 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1914 isn't available with that word size, return 0. */
1917 regsize (const struct reg *reg, int wordsize)
1919 return wordsize == 8 ? reg->sz64 : reg->sz32;
1922 /* Return the name of register number N, or null if no such register exists
1923 in the current architecture. */
1926 rs6000_register_name (int n)
1928 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1929 const struct reg *reg = tdep->regs + n;
1931 if (!regsize (reg, tdep->wordsize))
1936 /* Return the GDB type object for the "standard" data type
1937 of data in register N. */
1939 static struct type *
1940 rs6000_register_type (struct gdbarch *gdbarch, int n)
1942 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1943 const struct reg *reg = tdep->regs + n;
1946 return builtin_type_double;
1949 int size = regsize (reg, tdep->wordsize);
1953 return builtin_type_int0;
1955 return builtin_type_uint32;
1957 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1958 return builtin_type_vec64;
1960 return builtin_type_uint64;
1963 return builtin_type_vec128;
1966 internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"),
1972 /* Is REGNUM a member of REGGROUP? */
1974 rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1975 struct reggroup *group)
1977 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1982 if (REGISTER_NAME (regnum) == NULL
1983 || *REGISTER_NAME (regnum) == '\0')
1985 if (group == all_reggroup)
1988 float_p = (regnum == tdep->ppc_fpscr_regnum
1989 || (regnum >= tdep->ppc_fp0_regnum
1990 && regnum < tdep->ppc_fp0_regnum + 32));
1991 if (group == float_reggroup)
1994 vector_p = ((tdep->ppc_vr0_regnum >= 0
1995 && regnum >= tdep->ppc_vr0_regnum
1996 && regnum < tdep->ppc_vr0_regnum + 32)
1997 || (tdep->ppc_ev0_regnum >= 0
1998 && regnum >= tdep->ppc_ev0_regnum
1999 && regnum < tdep->ppc_ev0_regnum + 32)
2000 || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */
2001 || regnum == tdep->ppc_vrsave_regnum
2002 || regnum == tdep->ppc_acc_regnum
2003 || regnum == tdep->ppc_spefscr_regnum);
2004 if (group == vector_reggroup)
2007 /* Note that PS aka MSR isn't included - it's a system register (and
2008 besides, due to GCC's CFI foobar you do not want to restore
2010 general_p = ((regnum >= tdep->ppc_gp0_regnum
2011 && regnum < tdep->ppc_gp0_regnum + 32)
2012 || regnum == tdep->ppc_toc_regnum
2013 || regnum == tdep->ppc_cr_regnum
2014 || regnum == tdep->ppc_lr_regnum
2015 || regnum == tdep->ppc_ctr_regnum
2016 || regnum == tdep->ppc_xer_regnum
2017 || regnum == PC_REGNUM);
2018 if (group == general_reggroup)
2021 if (group == save_reggroup || group == restore_reggroup)
2022 return general_p || vector_p || float_p;
2027 /* The register format for RS/6000 floating point registers is always
2028 double, we need a conversion if the memory format is float. */
2031 rs6000_convert_register_p (int regnum, struct type *type)
2033 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2036 && TYPE_CODE (type) == TYPE_CODE_FLT
2037 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2041 rs6000_register_to_value (struct frame_info *frame,
2046 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2047 gdb_byte from[MAX_REGISTER_SIZE];
2049 gdb_assert (reg->fpr);
2050 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2052 get_frame_register (frame, regnum, from);
2053 convert_typed_floating (from, builtin_type_double, to, type);
2057 rs6000_value_to_register (struct frame_info *frame,
2060 const gdb_byte *from)
2062 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
2063 gdb_byte to[MAX_REGISTER_SIZE];
2065 gdb_assert (reg->fpr);
2066 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2068 convert_typed_floating (from, type, to, builtin_type_double);
2069 put_frame_register (frame, regnum, to);
2072 /* Move SPE vector register values between a 64-bit buffer and the two
2073 32-bit raw register halves in a regcache. This function handles
2074 both splitting a 64-bit value into two 32-bit halves, and joining
2075 two halves into a whole 64-bit value, depending on the function
2076 passed as the MOVE argument.
2078 EV_REG must be the number of an SPE evN vector register --- a
2079 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2082 Call MOVE once for each 32-bit half of that register, passing
2083 REGCACHE, the number of the raw register corresponding to that
2084 half, and the address of the appropriate half of BUFFER.
2086 For example, passing 'regcache_raw_read' as the MOVE function will
2087 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2088 'regcache_raw_supply' will supply the contents of BUFFER to the
2089 appropriate pair of raw registers in REGCACHE.
2091 You may need to cast away some 'const' qualifiers when passing
2092 MOVE, since this function can't tell at compile-time which of
2093 REGCACHE or BUFFER is acting as the source of the data. If C had
2094 co-variant type qualifiers, ... */
2096 e500_move_ev_register (void (*move) (struct regcache *regcache,
2097 int regnum, gdb_byte *buf),
2098 struct regcache *regcache, int ev_reg,
2101 struct gdbarch *arch = get_regcache_arch (regcache);
2102 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2104 gdb_byte *byte_buffer = buffer;
2106 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
2107 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
2109 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2111 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2113 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2114 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2118 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2119 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2124 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2125 int reg_nr, gdb_byte *buffer)
2127 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2128 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2130 gdb_assert (regcache_arch == gdbarch);
2132 if (tdep->ppc_ev0_regnum <= reg_nr
2133 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2134 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2136 internal_error (__FILE__, __LINE__,
2137 _("e500_pseudo_register_read: "
2138 "called on unexpected register '%s' (%d)"),
2139 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2143 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2144 int reg_nr, const gdb_byte *buffer)
2146 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2147 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2149 gdb_assert (regcache_arch == gdbarch);
2151 if (tdep->ppc_ev0_regnum <= reg_nr
2152 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2153 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2155 regcache, reg_nr, (gdb_byte *) buffer);
2157 internal_error (__FILE__, __LINE__,
2158 _("e500_pseudo_register_read: "
2159 "called on unexpected register '%s' (%d)"),
2160 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2163 /* The E500 needs a custom reggroup function: it has anonymous raw
2164 registers, and default_register_reggroup_p assumes that anonymous
2165 registers are not members of any reggroup. */
2167 e500_register_reggroup_p (struct gdbarch *gdbarch,
2169 struct reggroup *group)
2171 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2173 /* The save and restore register groups need to include the
2174 upper-half registers, even though they're anonymous. */
2175 if ((group == save_reggroup
2176 || group == restore_reggroup)
2177 && (tdep->ppc_ev0_upper_regnum <= regnum
2178 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
2181 /* In all other regards, the default reggroup definition is fine. */
2182 return default_register_reggroup_p (gdbarch, regnum, group);
2185 /* Convert a DBX STABS register number to a GDB register number. */
2187 rs6000_stab_reg_to_regnum (int num)
2189 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2191 if (0 <= num && num <= 31)
2192 return tdep->ppc_gp0_regnum + num;
2193 else if (32 <= num && num <= 63)
2194 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2195 specifies registers the architecture doesn't have? Our
2196 callers don't check the value we return. */
2197 return tdep->ppc_fp0_regnum + (num - 32);
2198 else if (77 <= num && num <= 108)
2199 return tdep->ppc_vr0_regnum + (num - 77);
2200 else if (1200 <= num && num < 1200 + 32)
2201 return tdep->ppc_ev0_regnum + (num - 1200);
2206 return tdep->ppc_mq_regnum;
2208 return tdep->ppc_lr_regnum;
2210 return tdep->ppc_ctr_regnum;
2212 return tdep->ppc_xer_regnum;
2214 return tdep->ppc_vrsave_regnum;
2216 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2218 return tdep->ppc_acc_regnum;
2220 return tdep->ppc_spefscr_regnum;
2227 /* Convert a Dwarf 2 register number to a GDB register number. */
2229 rs6000_dwarf2_reg_to_regnum (int num)
2231 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2233 if (0 <= num && num <= 31)
2234 return tdep->ppc_gp0_regnum + num;
2235 else if (32 <= num && num <= 63)
2236 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2237 specifies registers the architecture doesn't have? Our
2238 callers don't check the value we return. */
2239 return tdep->ppc_fp0_regnum + (num - 32);
2240 else if (1124 <= num && num < 1124 + 32)
2241 return tdep->ppc_vr0_regnum + (num - 1124);
2242 else if (1200 <= num && num < 1200 + 32)
2243 return tdep->ppc_ev0_regnum + (num - 1200);
2248 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2250 return tdep->ppc_acc_regnum;
2252 return tdep->ppc_mq_regnum;
2254 return tdep->ppc_xer_regnum;
2256 return tdep->ppc_lr_regnum;
2258 return tdep->ppc_ctr_regnum;
2260 return tdep->ppc_vrsave_regnum;
2262 return tdep->ppc_spefscr_regnum;
2270 rs6000_store_return_value (struct type *type,
2271 struct regcache *regcache,
2272 const gdb_byte *valbuf)
2274 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2275 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2278 /* The calling convention this function implements assumes the
2279 processor has floating-point registers. We shouldn't be using it
2280 on PPC variants that lack them. */
2281 gdb_assert (ppc_floating_point_unit_p (gdbarch));
2283 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2284 /* Floating point values are returned starting from FPR1 and up.
2285 Say a double_double_double type could be returned in
2286 FPR1/FPR2/FPR3 triple. */
2287 regnum = tdep->ppc_fp0_regnum + 1;
2288 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2290 if (TYPE_LENGTH (type) == 16
2291 && TYPE_VECTOR (type))
2292 regnum = tdep->ppc_vr0_regnum + 2;
2294 internal_error (__FILE__, __LINE__,
2295 _("rs6000_store_return_value: "
2296 "unexpected array return type"));
2299 /* Everything else is returned in GPR3 and up. */
2300 regnum = tdep->ppc_gp0_regnum + 3;
2303 size_t bytes_written = 0;
2305 while (bytes_written < TYPE_LENGTH (type))
2307 /* How much of this value can we write to this register? */
2308 size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written,
2309 register_size (gdbarch, regnum));
2310 regcache_cooked_write_part (regcache, regnum,
2312 valbuf + bytes_written);
2314 bytes_written += bytes_to_write;
2320 /* Extract from an array REGBUF containing the (raw) register state
2321 the address in which a function should return its structure value,
2322 as a CORE_ADDR (or an expression that can be used as one). */
2325 rs6000_extract_struct_value_address (struct regcache *regcache)
2327 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
2328 function call GDB knows the address of the struct return value
2329 and hence, should not need to call this function. Unfortunately,
2330 the current call_function_by_hand() code only saves the most
2331 recent struct address leading to occasional calls. The code
2332 should instead maintain a stack of such addresses (in the dummy
2334 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
2335 really got no idea where the return value is being stored. While
2336 r3, on function entry, contained the address it will have since
2337 been reused (scratch) and hence wouldn't be valid */
2341 /* Hook called when a new child process is started. */
2344 rs6000_create_inferior (int pid)
2346 if (rs6000_set_host_arch_hook)
2347 rs6000_set_host_arch_hook (pid);
2350 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2352 Usually a function pointer's representation is simply the address
2353 of the function. On the RS/6000 however, a function pointer is
2354 represented by a pointer to an OPD entry. This OPD entry contains
2355 three words, the first word is the address of the function, the
2356 second word is the TOC pointer (r2), and the third word is the
2357 static chain value. Throughout GDB it is currently assumed that a
2358 function pointer contains the address of the function, which is not
2359 easy to fix. In addition, the conversion of a function address to
2360 a function pointer would require allocation of an OPD entry in the
2361 inferior's memory space, with all its drawbacks. To be able to
2362 call C++ virtual methods in the inferior (which are called via
2363 function pointers), find_function_addr uses this function to get the
2364 function address from a function pointer. */
2366 /* Return real function address if ADDR (a function pointer) is in the data
2367 space and is therefore a special function pointer. */
2370 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2372 struct target_ops *targ)
2374 struct obj_section *s;
2376 s = find_pc_section (addr);
2377 if (s && s->the_bfd_section->flags & SEC_CODE)
2380 /* ADDR is in the data space, so it's a special function pointer. */
2381 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
2385 /* Handling the various POWER/PowerPC variants. */
2388 /* The arrays here called registers_MUMBLE hold information about available
2391 For each family of PPC variants, I've tried to isolate out the
2392 common registers and put them up front, so that as long as you get
2393 the general family right, GDB will correctly identify the registers
2394 common to that family. The common register sets are:
2396 For the 60x family: hid0 hid1 iabr dabr pir
2398 For the 505 and 860 family: eie eid nri
2400 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2401 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2404 Most of these register groups aren't anything formal. I arrived at
2405 them by looking at the registers that occurred in more than one
2408 Note: kevinb/2002-04-30: Support for the fpscr register was added
2409 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2410 for Power. For PowerPC, slot 70 was unused and was already in the
2411 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2412 slot 70 was being used for "mq", so the next available slot (71)
2413 was chosen. It would have been nice to be able to make the
2414 register numbers the same across processor cores, but this wasn't
2415 possible without either 1) renumbering some registers for some
2416 processors or 2) assigning fpscr to a really high slot that's
2417 larger than any current register number. Doing (1) is bad because
2418 existing stubs would break. Doing (2) is undesirable because it
2419 would introduce a really large gap between fpscr and the rest of
2420 the registers for most processors. */
2422 /* Convenience macros for populating register arrays. */
2424 /* Within another macro, convert S to a string. */
2428 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2429 and 64 bits on 64-bit systems. */
2430 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2432 /* Return a struct reg defining register NAME that's 32 bits on all
2434 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2436 /* Return a struct reg defining register NAME that's 64 bits on all
2438 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2440 /* Return a struct reg defining register NAME that's 128 bits on all
2442 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2444 /* Return a struct reg defining floating-point register NAME. */
2445 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2447 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2448 long on all systems. */
2449 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2451 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2452 systems and that doesn't exist on 64-bit systems. */
2453 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2455 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2456 systems and that doesn't exist on 32-bit systems. */
2457 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2459 /* Return a struct reg placeholder for a register that doesn't exist. */
2460 #define R0 { 0, 0, 0, 0, 0, -1 }
2462 /* Return a struct reg defining an anonymous raw register that's 32
2463 bits on all systems. */
2464 #define A4 { 0, 4, 4, 0, 0, -1 }
2466 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2467 32-bit systems and 64 bits on 64-bit systems. */
2468 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2470 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2472 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2474 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2475 all systems, and whose SPR number is NUMBER. */
2476 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2478 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2479 64-bit systems and that doesn't exist on 32-bit systems. */
2480 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2482 /* UISA registers common across all architectures, including POWER. */
2484 #define COMMON_UISA_REGS \
2485 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2486 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2487 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2488 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2489 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2490 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2491 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2492 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2493 /* 64 */ R(pc), R(ps)
2495 /* UISA-level SPRs for PowerPC. */
2496 #define PPC_UISA_SPRS \
2497 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2499 /* UISA-level SPRs for PowerPC without floating point support. */
2500 #define PPC_UISA_NOFP_SPRS \
2501 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2503 /* Segment registers, for PowerPC. */
2504 #define PPC_SEGMENT_REGS \
2505 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2506 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2507 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2508 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2510 /* OEA SPRs for PowerPC. */
2511 #define PPC_OEA_SPRS \
2513 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2514 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2515 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2516 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2517 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2518 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2519 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2520 /* 116 */ S4(dec), S(dabr), S4(ear)
2522 /* AltiVec registers. */
2523 #define PPC_ALTIVEC_REGS \
2524 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2525 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2526 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2527 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2528 /*151*/R4(vscr), R4(vrsave)
2531 /* On machines supporting the SPE APU, the general-purpose registers
2532 are 64 bits long. There are SIMD vector instructions to treat them
2533 as pairs of floats, but the rest of the instruction set treats them
2534 as 32-bit registers, and only operates on their lower halves.
2536 In the GDB regcache, we treat their high and low halves as separate
2537 registers. The low halves we present as the general-purpose
2538 registers, and then we have pseudo-registers that stitch together
2539 the upper and lower halves and present them as pseudo-registers. */
2541 /* SPE GPR lower halves --- raw registers. */
2542 #define PPC_SPE_GP_REGS \
2543 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2544 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2545 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2546 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2548 /* SPE GPR upper halves --- anonymous raw registers. */
2549 #define PPC_SPE_UPPER_GP_REGS \
2550 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2551 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2552 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2553 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2555 /* SPE GPR vector registers --- pseudo registers based on underlying
2556 gprs and the anonymous upper half raw registers. */
2557 #define PPC_EV_PSEUDO_REGS \
2558 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2559 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2560 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2561 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2563 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2564 user-level SPR's. */
2565 static const struct reg registers_power[] =
2568 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
2572 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2573 view of the PowerPC. */
2574 static const struct reg registers_powerpc[] =
2583 Some notes about the "tcr" special-purpose register:
2584 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2585 403's programmable interval timer, fixed interval timer, and
2587 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2588 watchdog timer, and nothing else.
2590 Some of the fields are similar between the two, but they're not
2591 compatible with each other. Since the two variants have different
2592 registers, with different numbers, but the same name, we can't
2593 splice the register name to get the SPR number. */
2594 static const struct reg registers_403[] =
2600 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2601 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2602 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2603 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2604 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2605 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
2608 /* IBM PowerPC 403GC.
2609 See the comments about 'tcr' for the 403, above. */
2610 static const struct reg registers_403GC[] =
2616 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2617 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2618 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2619 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2620 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2621 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
2622 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
2623 /* 147 */ S(tbhu), S(tblu)
2626 /* Motorola PowerPC 505. */
2627 static const struct reg registers_505[] =
2633 /* 119 */ S(eie), S(eid), S(nri)
2636 /* Motorola PowerPC 860 or 850. */
2637 static const struct reg registers_860[] =
2643 /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
2644 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
2645 /* 127 */ S(der), S(counta), S(countb), S(cmpe),
2646 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
2647 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
2648 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
2649 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
2650 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
2651 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
2652 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
2653 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
2654 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
2657 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2658 for reading and writing RTCU and RTCL. However, how one reads and writes a
2659 register is the stub's problem. */
2660 static const struct reg registers_601[] =
2666 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2667 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
2670 /* Motorola PowerPC 602.
2671 See the notes under the 403 about 'tcr'. */
2672 static const struct reg registers_602[] =
2678 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2679 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
2680 /* 127 */ S(sebr), S(ser), S(sp), S(lt)
2683 /* Motorola/IBM PowerPC 603 or 603e. */
2684 static const struct reg registers_603[] =
2690 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2691 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
2692 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
2695 /* Motorola PowerPC 604 or 604e. */
2696 static const struct reg registers_604[] =
2702 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2703 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
2704 /* 127 */ S(sia), S(sda)
2707 /* Motorola/IBM PowerPC 750 or 740. */
2708 static const struct reg registers_750[] =
2714 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2715 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
2716 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
2717 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
2718 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
2719 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
2723 /* Motorola PowerPC 7400. */
2724 static const struct reg registers_7400[] =
2726 /* gpr0-gpr31, fpr0-fpr31 */
2728 /* cr, lr, ctr, xer, fpscr */
2733 /* vr0-vr31, vrsave, vscr */
2735 /* FIXME? Add more registers? */
2738 /* Motorola e500. */
2739 static const struct reg registers_e500[] =
2741 /* 0 .. 31 */ PPC_SPE_GP_REGS,
2742 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
2743 /* 64 .. 65 */ R(pc), R(ps),
2744 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
2745 /* 71 .. 72 */ R8(acc), S4(spefscr),
2746 /* NOTE: Add new registers here the end of the raw register
2747 list and just before the first pseudo register. */
2748 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2751 /* Information about a particular processor variant. */
2755 /* Name of this variant. */
2758 /* English description of the variant. */
2761 /* bfd_arch_info.arch corresponding to variant. */
2762 enum bfd_architecture arch;
2764 /* bfd_arch_info.mach corresponding to variant. */
2767 /* Number of real registers. */
2770 /* Number of pseudo registers. */
2773 /* Number of total registers (the sum of nregs and npregs). */
2776 /* Table of register names; registers[R] is the name of the register
2778 const struct reg *regs;
2781 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2784 num_registers (const struct reg *reg_list, int num_tot_regs)
2789 for (i = 0; i < num_tot_regs; i++)
2790 if (!reg_list[i].pseudo)
2797 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2802 for (i = 0; i < num_tot_regs; i++)
2803 if (reg_list[i].pseudo)
2809 /* Information in this table comes from the following web sites:
2810 IBM: http://www.chips.ibm.com:80/products/embedded/
2811 Motorola: http://www.mot.com/SPS/PowerPC/
2813 I'm sure I've got some of the variant descriptions not quite right.
2814 Please report any inaccuracies you find to GDB's maintainer.
2816 If you add entries to this table, please be sure to allow the new
2817 value as an argument to the --with-cpu flag, in configure.in. */
2819 static struct variant variants[] =
2822 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2823 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2825 {"power", "POWER user-level", bfd_arch_rs6000,
2826 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2828 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2829 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2831 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2832 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2834 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2835 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2837 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2838 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2840 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2841 604, -1, -1, tot_num_registers (registers_604),
2843 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2844 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2846 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2847 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2849 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2850 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2852 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2853 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2855 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2856 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2858 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2859 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2863 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2864 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2866 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2867 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2869 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2870 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2872 {"a35", "PowerPC A35", bfd_arch_powerpc,
2873 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2875 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2876 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2878 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2879 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2882 /* FIXME: I haven't checked the register sets of the following. */
2883 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2884 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2886 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2887 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2889 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2890 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2893 {0, 0, 0, 0, 0, 0, 0, 0}
2896 /* Initialize the number of registers and pseudo registers in each variant. */
2899 init_variants (void)
2903 for (v = variants; v->name; v++)
2906 v->nregs = num_registers (v->regs, v->num_tot_regs);
2907 if (v->npregs == -1)
2908 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2912 /* Return the variant corresponding to architecture ARCH and machine number
2913 MACH. If no such variant exists, return null. */
2915 static const struct variant *
2916 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2918 const struct variant *v;
2920 for (v = variants; v->name; v++)
2921 if (arch == v->arch && mach == v->mach)
2928 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2930 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2931 return print_insn_big_powerpc (memaddr, info);
2933 return print_insn_little_powerpc (memaddr, info);
2937 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2939 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2942 static struct frame_id
2943 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2945 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2947 frame_pc_unwind (next_frame));
2950 struct rs6000_frame_cache
2953 CORE_ADDR initial_sp;
2954 struct trad_frame_saved_reg *saved_regs;
2957 static struct rs6000_frame_cache *
2958 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2960 struct rs6000_frame_cache *cache;
2961 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2962 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2963 struct rs6000_framedata fdata;
2964 int wordsize = tdep->wordsize;
2967 if ((*this_cache) != NULL)
2968 return (*this_cache);
2969 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2970 (*this_cache) = cache;
2971 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2973 func = frame_func_unwind (next_frame);
2974 pc = frame_pc_unwind (next_frame);
2975 skip_prologue (func, pc, &fdata);
2977 /* Figure out the parent's stack pointer. */
2979 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2980 address of the current frame. Things might be easier if the
2981 ->frame pointed to the outer-most address of the frame. In
2982 the mean time, the address of the prev frame is used as the
2983 base address of this frame. */
2984 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2986 /* If the function appears to be frameless, check a couple of likely
2987 indicators that we have simply failed to find the frame setup.
2988 Two common cases of this are missing symbols (i.e.
2989 frame_func_unwind returns the wrong address or 0), and assembly
2990 stubs which have a fast exit path but set up a frame on the slow
2993 If the LR appears to return to this function, then presume that
2994 we have an ABI compliant frame that we failed to find. */
2995 if (fdata.frameless && fdata.lr_offset == 0)
3000 saved_lr = frame_unwind_register_unsigned (next_frame,
3001 tdep->ppc_lr_regnum);
3002 if (func == 0 && saved_lr == pc)
3006 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3007 if (func == saved_func)
3013 fdata.frameless = 0;
3014 fdata.lr_offset = wordsize;
3018 if (!fdata.frameless)
3019 /* Frameless really means stackless. */
3020 cache->base = read_memory_addr (cache->base, wordsize);
3022 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
3024 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3025 All fpr's from saved_fpr to fp31 are saved. */
3027 if (fdata.saved_fpr >= 0)
3030 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3032 /* If skip_prologue says floating-point registers were saved,
3033 but the current architecture has no floating-point registers,
3034 then that's strange. But we have no indices to even record
3035 the addresses under, so we just ignore it. */
3036 if (ppc_floating_point_unit_p (gdbarch))
3037 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3039 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3044 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3045 All gpr's from saved_gpr to gpr31 are saved. */
3047 if (fdata.saved_gpr >= 0)
3050 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3051 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3053 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3054 gpr_addr += wordsize;
3058 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3059 All vr's from saved_vr to vr31 are saved. */
3060 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3062 if (fdata.saved_vr >= 0)
3065 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3066 for (i = fdata.saved_vr; i < 32; i++)
3068 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3069 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3074 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3075 All vr's from saved_ev to ev31 are saved. ????? */
3076 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
3078 if (fdata.saved_ev >= 0)
3081 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3082 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3084 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3085 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3086 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3091 /* If != 0, fdata.cr_offset is the offset from the frame that
3093 if (fdata.cr_offset != 0)
3094 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3096 /* If != 0, fdata.lr_offset is the offset from the frame that
3098 if (fdata.lr_offset != 0)
3099 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
3100 /* The PC is found in the link register. */
3101 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
3103 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3104 holds the VRSAVE. */
3105 if (fdata.vrsave_offset != 0)
3106 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3108 if (fdata.alloca_reg < 0)
3109 /* If no alloca register used, then fi->frame is the value of the
3110 %sp for this frame, and it is good enough. */
3111 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
3113 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3120 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3121 struct frame_id *this_id)
3123 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3125 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
3129 rs6000_frame_prev_register (struct frame_info *next_frame,
3131 int regnum, int *optimizedp,
3132 enum lval_type *lvalp, CORE_ADDR *addrp,
3133 int *realnump, gdb_byte *valuep)
3135 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3137 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3138 optimizedp, lvalp, addrp, realnump, valuep);
3141 static const struct frame_unwind rs6000_frame_unwind =
3144 rs6000_frame_this_id,
3145 rs6000_frame_prev_register
3148 static const struct frame_unwind *
3149 rs6000_frame_sniffer (struct frame_info *next_frame)
3151 return &rs6000_frame_unwind;
3157 rs6000_frame_base_address (struct frame_info *next_frame,
3160 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3162 return info->initial_sp;
3165 static const struct frame_base rs6000_frame_base = {
3166 &rs6000_frame_unwind,
3167 rs6000_frame_base_address,
3168 rs6000_frame_base_address,
3169 rs6000_frame_base_address
3172 static const struct frame_base *
3173 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3175 return &rs6000_frame_base;
3178 /* Initialize the current architecture based on INFO. If possible, re-use an
3179 architecture from ARCHES, which is a list of architectures already created
3180 during this debugging session.
3182 Called e.g. at program startup, when reading a core file, and when reading
3185 static struct gdbarch *
3186 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3188 struct gdbarch *gdbarch;
3189 struct gdbarch_tdep *tdep;
3190 int wordsize, from_xcoff_exec, from_elf_exec, i, off;
3192 const struct variant *v;
3193 enum bfd_architecture arch;
3199 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3200 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3202 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3203 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3205 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3207 /* Check word size. If INFO is from a binary file, infer it from
3208 that, else choose a likely default. */
3209 if (from_xcoff_exec)
3211 if (bfd_xcoff_is_xcoff64 (info.abfd))
3216 else if (from_elf_exec)
3218 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3225 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3226 wordsize = info.bfd_arch_info->bits_per_word /
3227 info.bfd_arch_info->bits_per_byte;
3232 /* Find a candidate among extant architectures. */
3233 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3235 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3237 /* Word size in the various PowerPC bfd_arch_info structs isn't
3238 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3239 separate word size check. */
3240 tdep = gdbarch_tdep (arches->gdbarch);
3241 if (tdep && tdep->wordsize == wordsize)
3242 return arches->gdbarch;
3245 /* None found, create a new architecture from INFO, whose bfd_arch_info
3246 validity depends on the source:
3247 - executable useless
3248 - rs6000_host_arch() good
3250 - "set arch" trust blindly
3251 - GDB startup useless but harmless */
3253 if (!from_xcoff_exec)
3255 arch = info.bfd_arch_info->arch;
3256 mach = info.bfd_arch_info->mach;
3260 arch = bfd_arch_powerpc;
3261 bfd_default_set_arch_mach (&abfd, arch, 0);
3262 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3263 mach = info.bfd_arch_info->mach;
3265 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3266 tdep->wordsize = wordsize;
3268 /* For e500 executables, the apuinfo section is of help here. Such
3269 section contains the identifier and revision number of each
3270 Application-specific Processing Unit that is present on the
3271 chip. The content of the section is determined by the assembler
3272 which looks at each instruction and determines which unit (and
3273 which version of it) can execute it. In our case we just look for
3274 the existance of the section. */
3278 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3281 arch = info.bfd_arch_info->arch;
3282 mach = bfd_mach_ppc_e500;
3283 bfd_default_set_arch_mach (&abfd, arch, mach);
3284 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3288 gdbarch = gdbarch_alloc (&info, tdep);
3290 /* Initialize the number of real and pseudo registers in each variant. */
3293 /* Choose variant. */
3294 v = find_variant_by_arch (arch, mach);
3298 tdep->regs = v->regs;
3300 tdep->ppc_gp0_regnum = 0;
3301 tdep->ppc_toc_regnum = 2;
3302 tdep->ppc_ps_regnum = 65;
3303 tdep->ppc_cr_regnum = 66;
3304 tdep->ppc_lr_regnum = 67;
3305 tdep->ppc_ctr_regnum = 68;
3306 tdep->ppc_xer_regnum = 69;
3307 if (v->mach == bfd_mach_ppc_601)
3308 tdep->ppc_mq_regnum = 124;
3309 else if (arch == bfd_arch_rs6000)
3310 tdep->ppc_mq_regnum = 70;
3312 tdep->ppc_mq_regnum = -1;
3313 tdep->ppc_fp0_regnum = 32;
3314 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
3315 tdep->ppc_sr0_regnum = 71;
3316 tdep->ppc_vr0_regnum = -1;
3317 tdep->ppc_vrsave_regnum = -1;
3318 tdep->ppc_ev0_upper_regnum = -1;
3319 tdep->ppc_ev0_regnum = -1;
3320 tdep->ppc_ev31_regnum = -1;
3321 tdep->ppc_acc_regnum = -1;
3322 tdep->ppc_spefscr_regnum = -1;
3324 set_gdbarch_pc_regnum (gdbarch, 64);
3325 set_gdbarch_sp_regnum (gdbarch, 1);
3326 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
3327 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3328 if (sysv_abi && wordsize == 8)
3329 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3330 else if (sysv_abi && wordsize == 4)
3331 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3334 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
3335 set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
3338 /* Set lr_frame_offset. */
3340 tdep->lr_frame_offset = 16;
3342 tdep->lr_frame_offset = 4;
3344 tdep->lr_frame_offset = 8;
3346 if (v->arch == bfd_arch_rs6000)
3347 tdep->ppc_sr0_regnum = -1;
3348 else if (v->arch == bfd_arch_powerpc)
3352 tdep->ppc_sr0_regnum = -1;
3353 tdep->ppc_vr0_regnum = 71;
3354 tdep->ppc_vrsave_regnum = 104;
3356 case bfd_mach_ppc_7400:
3357 tdep->ppc_vr0_regnum = 119;
3358 tdep->ppc_vrsave_regnum = 152;
3360 case bfd_mach_ppc_e500:
3361 tdep->ppc_toc_regnum = -1;
3362 tdep->ppc_ev0_upper_regnum = 32;
3363 tdep->ppc_ev0_regnum = 73;
3364 tdep->ppc_ev31_regnum = 104;
3365 tdep->ppc_acc_regnum = 71;
3366 tdep->ppc_spefscr_regnum = 72;
3367 tdep->ppc_fp0_regnum = -1;
3368 tdep->ppc_fpscr_regnum = -1;
3369 tdep->ppc_sr0_regnum = -1;
3370 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3371 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3372 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
3375 case bfd_mach_ppc64:
3376 case bfd_mach_ppc_620:
3377 case bfd_mach_ppc_630:
3378 case bfd_mach_ppc_a35:
3379 case bfd_mach_ppc_rs64ii:
3380 case bfd_mach_ppc_rs64iii:
3381 /* These processor's register sets don't have segment registers. */
3382 tdep->ppc_sr0_regnum = -1;
3386 internal_error (__FILE__, __LINE__,
3387 _("rs6000_gdbarch_init: "
3388 "received unexpected BFD 'arch' value"));
3390 /* Sanity check on registers. */
3391 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
3393 /* Select instruction printer. */
3394 if (arch == bfd_arch_rs6000)
3395 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3397 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3399 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
3401 set_gdbarch_num_regs (gdbarch, v->nregs);
3402 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
3403 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3404 set_gdbarch_register_type (gdbarch, rs6000_register_type);
3405 set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p);
3407 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3408 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3409 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3410 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3411 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3412 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3413 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3415 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3417 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3418 set_gdbarch_char_signed (gdbarch, 0);
3420 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3421 if (sysv_abi && wordsize == 8)
3423 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3424 else if (!sysv_abi && wordsize == 4)
3425 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3426 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3427 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3429 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3431 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3432 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3433 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3435 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3436 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3437 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
3438 is correct for the SysV ABI when the wordsize is 8, but I'm also
3439 fairly certain that ppc_sysv_abi_push_arguments() will give even
3440 worse results since it only works for 32-bit code. So, for the moment,
3441 we're better off calling rs6000_push_arguments() since it works for
3442 64-bit code. At some point in the future, this matter needs to be
3444 if (sysv_abi && wordsize == 4)
3445 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3446 else if (sysv_abi && wordsize == 8)
3447 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3449 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3451 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
3453 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3454 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3456 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3457 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3459 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3460 for the descriptor and ".FN" for the entry-point -- a user
3461 specifying "break FN" will unexpectedly end up with a breakpoint
3462 on the descriptor and not the function. This architecture method
3463 transforms any breakpoints on descriptors into breakpoints on the
3464 corresponding entry point. */
3465 if (sysv_abi && wordsize == 8)
3466 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3468 /* Not sure on this. FIXMEmgo */
3469 set_gdbarch_frame_args_skip (gdbarch, 8);
3472 set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention);
3476 /* Handle RS/6000 function pointers (which are really function
3478 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3479 rs6000_convert_from_func_ptr_addr);
3482 /* Helpers for function argument information. */
3483 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3485 /* Hook in ABI-specific overrides, if they have been registered. */
3486 gdbarch_init_osabi (info, gdbarch);
3490 case GDB_OSABI_LINUX:
3491 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems
3492 have altivec registers. If not, ptrace will fail the first time it's
3493 called to access one and will not be called again. This wart will
3494 be removed when Daniel Jacobowitz's proposal for autodetecting target
3495 registers is implemented. */
3496 if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64))
3498 tdep->ppc_vr0_regnum = 71;
3499 tdep->ppc_vrsave_regnum = 104;
3502 case GDB_OSABI_NETBSD_AOUT:
3503 case GDB_OSABI_NETBSD_ELF:
3504 case GDB_OSABI_UNKNOWN:
3505 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3506 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3507 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3508 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3511 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3513 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3514 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3515 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3516 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3519 if (from_xcoff_exec)
3521 /* NOTE: jimix/2003-06-09: This test should really check for
3522 GDB_OSABI_AIX when that is defined and becomes
3523 available. (Actually, once things are properly split apart,
3524 the test goes away.) */
3525 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
3526 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
3529 init_sim_regno_table (gdbarch);
3535 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3537 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3542 /* FIXME: Dump gdbarch_tdep. */
3545 /* Initialization code. */
3547 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3550 _initialize_rs6000_tdep (void)
3552 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3553 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);