1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
54 #include "solib-svr4.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "features/rs6000/powerpc-32.c"
65 #include "features/rs6000/powerpc-altivec32.c"
66 #include "features/rs6000/powerpc-vsx32.c"
67 #include "features/rs6000/powerpc-403.c"
68 #include "features/rs6000/powerpc-403gc.c"
69 #include "features/rs6000/powerpc-505.c"
70 #include "features/rs6000/powerpc-601.c"
71 #include "features/rs6000/powerpc-602.c"
72 #include "features/rs6000/powerpc-603.c"
73 #include "features/rs6000/powerpc-604.c"
74 #include "features/rs6000/powerpc-64.c"
75 #include "features/rs6000/powerpc-altivec64.c"
76 #include "features/rs6000/powerpc-vsx64.c"
77 #include "features/rs6000/powerpc-7400.c"
78 #include "features/rs6000/powerpc-750.c"
79 #include "features/rs6000/powerpc-860.c"
80 #include "features/rs6000/powerpc-e500.c"
81 #include "features/rs6000/rs6000.c"
83 /* Determine if regnum is an SPE pseudo-register. */
84 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
85 && (regnum) >= (tdep)->ppc_ev0_regnum \
86 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
88 /* Determine if regnum is a decimal float pseudo-register. */
89 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
90 && (regnum) >= (tdep)->ppc_dl0_regnum \
91 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
93 /* Determine if regnum is a POWER7 VSX register. */
94 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
95 && (regnum) >= (tdep)->ppc_vsr0_regnum \
96 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
98 /* Determine if regnum is a POWER7 Extended FP register. */
99 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
100 && (regnum) >= (tdep)->ppc_efpr0_regnum \
101 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_fprs)
103 /* The list of available "set powerpc ..." and "show powerpc ..."
105 static struct cmd_list_element *setpowerpccmdlist = NULL;
106 static struct cmd_list_element *showpowerpccmdlist = NULL;
108 static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
110 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
111 static const char *powerpc_vector_strings[] =
120 /* A variable that can be configured by the user. */
121 static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
122 static const char *powerpc_vector_abi_string = "auto";
124 /* To be used by skip_prologue. */
126 struct rs6000_framedata
128 int offset; /* total size of frame --- the distance
129 by which we decrement sp to allocate
131 int saved_gpr; /* smallest # of saved gpr */
132 int saved_fpr; /* smallest # of saved fpr */
133 int saved_vr; /* smallest # of saved vr */
134 int saved_ev; /* smallest # of saved ev */
135 int alloca_reg; /* alloca register number (frame ptr) */
136 char frameless; /* true if frameless functions. */
137 char nosavedpc; /* true if pc not saved. */
138 int gpr_offset; /* offset of saved gprs from prev sp */
139 int fpr_offset; /* offset of saved fprs from prev sp */
140 int vr_offset; /* offset of saved vrs from prev sp */
141 int ev_offset; /* offset of saved evs from prev sp */
142 int lr_offset; /* offset of saved lr */
143 int cr_offset; /* offset of saved cr */
144 int vrsave_offset; /* offset of saved vrsave register */
148 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
150 vsx_register_p (struct gdbarch *gdbarch, int regno)
152 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
153 if (tdep->ppc_vsr0_regnum < 0)
156 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
157 <= tdep->ppc_vsr0_upper_regnum + 31);
160 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
162 altivec_register_p (struct gdbarch *gdbarch, int regno)
164 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
165 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
168 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
172 /* Return true if REGNO is an SPE register, false otherwise. */
174 spe_register_p (struct gdbarch *gdbarch, int regno)
176 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
178 /* Is it a reference to EV0 -- EV31, and do we have those? */
179 if (IS_SPE_PSEUDOREG (tdep, regno))
182 /* Is it a reference to one of the raw upper GPR halves? */
183 if (tdep->ppc_ev0_upper_regnum >= 0
184 && tdep->ppc_ev0_upper_regnum <= regno
185 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
188 /* Is it a reference to the 64-bit accumulator, and do we have that? */
189 if (tdep->ppc_acc_regnum >= 0
190 && tdep->ppc_acc_regnum == regno)
193 /* Is it a reference to the SPE floating-point status and control register,
194 and do we have that? */
195 if (tdep->ppc_spefscr_regnum >= 0
196 && tdep->ppc_spefscr_regnum == regno)
203 /* Return non-zero if the architecture described by GDBARCH has
204 floating-point registers (f0 --- f31 and fpscr). */
206 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
208 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
210 return (tdep->ppc_fp0_regnum >= 0
211 && tdep->ppc_fpscr_regnum >= 0);
214 /* Return non-zero if the architecture described by GDBARCH has
215 VSX registers (vsr0 --- vsr63). */
217 ppc_vsx_support_p (struct gdbarch *gdbarch)
219 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
221 return tdep->ppc_vsr0_regnum >= 0;
224 /* Return non-zero if the architecture described by GDBARCH has
225 Altivec registers (vr0 --- vr31, vrsave and vscr). */
227 ppc_altivec_support_p (struct gdbarch *gdbarch)
229 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
231 return (tdep->ppc_vr0_regnum >= 0
232 && tdep->ppc_vrsave_regnum >= 0);
235 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
238 This is a helper function for init_sim_regno_table, constructing
239 the table mapping GDB register numbers to sim register numbers; we
240 initialize every element in that table to -1 before we start
243 set_sim_regno (int *table, int gdb_regno, int sim_regno)
245 /* Make sure we don't try to assign any given GDB register a sim
246 register number more than once. */
247 gdb_assert (table[gdb_regno] == -1);
248 table[gdb_regno] = sim_regno;
252 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
253 numbers to simulator register numbers, based on the values placed
254 in the ARCH->tdep->ppc_foo_regnum members. */
256 init_sim_regno_table (struct gdbarch *arch)
258 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
259 int total_regs = gdbarch_num_regs (arch);
260 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
262 static const char *const segment_regs[] = {
263 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
264 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
267 /* Presume that all registers not explicitly mentioned below are
268 unavailable from the sim. */
269 for (i = 0; i < total_regs; i++)
272 /* General-purpose registers. */
273 for (i = 0; i < ppc_num_gprs; i++)
274 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
276 /* Floating-point registers. */
277 if (tdep->ppc_fp0_regnum >= 0)
278 for (i = 0; i < ppc_num_fprs; i++)
279 set_sim_regno (sim_regno,
280 tdep->ppc_fp0_regnum + i,
281 sim_ppc_f0_regnum + i);
282 if (tdep->ppc_fpscr_regnum >= 0)
283 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
285 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
286 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
287 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
289 /* Segment registers. */
290 for (i = 0; i < ppc_num_srs; i++)
294 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
296 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
299 /* Altivec registers. */
300 if (tdep->ppc_vr0_regnum >= 0)
302 for (i = 0; i < ppc_num_vrs; i++)
303 set_sim_regno (sim_regno,
304 tdep->ppc_vr0_regnum + i,
305 sim_ppc_vr0_regnum + i);
307 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
308 we can treat this more like the other cases. */
309 set_sim_regno (sim_regno,
310 tdep->ppc_vr0_regnum + ppc_num_vrs,
311 sim_ppc_vscr_regnum);
313 /* vsave is a special-purpose register, so the code below handles it. */
315 /* SPE APU (E500) registers. */
316 if (tdep->ppc_ev0_upper_regnum >= 0)
317 for (i = 0; i < ppc_num_gprs; i++)
318 set_sim_regno (sim_regno,
319 tdep->ppc_ev0_upper_regnum + i,
320 sim_ppc_rh0_regnum + i);
321 if (tdep->ppc_acc_regnum >= 0)
322 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
323 /* spefscr is a special-purpose register, so the code below handles it. */
326 /* Now handle all special-purpose registers. Verify that they
327 haven't mistakenly been assigned numbers by any of the above
329 for (i = 0; i < sim_ppc_num_sprs; i++)
331 const char *spr_name = sim_spr_register_name (i);
334 if (spr_name != NULL)
335 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
338 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
342 /* Drop the initialized array into place. */
343 tdep->sim_regno = sim_regno;
347 /* Given a GDB register number REG, return the corresponding SIM
350 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
352 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
355 if (tdep->sim_regno == NULL)
356 init_sim_regno_table (gdbarch);
359 && reg <= gdbarch_num_regs (gdbarch)
360 + gdbarch_num_pseudo_regs (gdbarch));
361 sim_regno = tdep->sim_regno[reg];
366 return LEGACY_SIM_REGNO_IGNORE;
371 /* Register set support functions. */
373 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
374 Write the register to REGCACHE. */
377 ppc_supply_reg (struct regcache *regcache, int regnum,
378 const gdb_byte *regs, size_t offset, int regsize)
380 if (regnum != -1 && offset != -1)
384 struct gdbarch *gdbarch = get_regcache_arch (regcache);
385 int gdb_regsize = register_size (gdbarch, regnum);
386 if (gdb_regsize < regsize
387 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
388 offset += regsize - gdb_regsize;
390 regcache_raw_supply (regcache, regnum, regs + offset);
394 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
395 in a field REGSIZE wide. Zero pad as necessary. */
398 ppc_collect_reg (const struct regcache *regcache, int regnum,
399 gdb_byte *regs, size_t offset, int regsize)
401 if (regnum != -1 && offset != -1)
405 struct gdbarch *gdbarch = get_regcache_arch (regcache);
406 int gdb_regsize = register_size (gdbarch, regnum);
407 if (gdb_regsize < regsize)
409 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
411 memset (regs + offset, 0, regsize - gdb_regsize);
412 offset += regsize - gdb_regsize;
415 memset (regs + offset + regsize - gdb_regsize, 0,
416 regsize - gdb_regsize);
419 regcache_raw_collect (regcache, regnum, regs + offset);
424 ppc_greg_offset (struct gdbarch *gdbarch,
425 struct gdbarch_tdep *tdep,
426 const struct ppc_reg_offsets *offsets,
430 *regsize = offsets->gpr_size;
431 if (regnum >= tdep->ppc_gp0_regnum
432 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
433 return (offsets->r0_offset
434 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
436 if (regnum == gdbarch_pc_regnum (gdbarch))
437 return offsets->pc_offset;
439 if (regnum == tdep->ppc_ps_regnum)
440 return offsets->ps_offset;
442 if (regnum == tdep->ppc_lr_regnum)
443 return offsets->lr_offset;
445 if (regnum == tdep->ppc_ctr_regnum)
446 return offsets->ctr_offset;
448 *regsize = offsets->xr_size;
449 if (regnum == tdep->ppc_cr_regnum)
450 return offsets->cr_offset;
452 if (regnum == tdep->ppc_xer_regnum)
453 return offsets->xer_offset;
455 if (regnum == tdep->ppc_mq_regnum)
456 return offsets->mq_offset;
462 ppc_fpreg_offset (struct gdbarch_tdep *tdep,
463 const struct ppc_reg_offsets *offsets,
466 if (regnum >= tdep->ppc_fp0_regnum
467 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
468 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
470 if (regnum == tdep->ppc_fpscr_regnum)
471 return offsets->fpscr_offset;
477 ppc_vrreg_offset (struct gdbarch_tdep *tdep,
478 const struct ppc_reg_offsets *offsets,
481 if (regnum >= tdep->ppc_vr0_regnum
482 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
483 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
485 if (regnum == tdep->ppc_vrsave_regnum - 1)
486 return offsets->vscr_offset;
488 if (regnum == tdep->ppc_vrsave_regnum)
489 return offsets->vrsave_offset;
494 /* Supply register REGNUM in the general-purpose register set REGSET
495 from the buffer specified by GREGS and LEN to register cache
496 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
499 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
500 int regnum, const void *gregs, size_t len)
502 struct gdbarch *gdbarch = get_regcache_arch (regcache);
503 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
504 const struct ppc_reg_offsets *offsets = regset->descr;
511 int gpr_size = offsets->gpr_size;
513 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
514 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
515 i++, offset += gpr_size)
516 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
518 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
519 gregs, offsets->pc_offset, gpr_size);
520 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
521 gregs, offsets->ps_offset, gpr_size);
522 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
523 gregs, offsets->lr_offset, gpr_size);
524 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
525 gregs, offsets->ctr_offset, gpr_size);
526 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
527 gregs, offsets->cr_offset, offsets->xr_size);
528 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
529 gregs, offsets->xer_offset, offsets->xr_size);
530 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
531 gregs, offsets->mq_offset, offsets->xr_size);
535 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
536 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
539 /* Supply register REGNUM in the floating-point register set REGSET
540 from the buffer specified by FPREGS and LEN to register cache
541 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
544 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
545 int regnum, const void *fpregs, size_t len)
547 struct gdbarch *gdbarch = get_regcache_arch (regcache);
548 struct gdbarch_tdep *tdep;
549 const struct ppc_reg_offsets *offsets;
552 if (!ppc_floating_point_unit_p (gdbarch))
555 tdep = gdbarch_tdep (gdbarch);
556 offsets = regset->descr;
561 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
562 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
564 ppc_supply_reg (regcache, i, fpregs, offset, 8);
566 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
567 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
571 offset = ppc_fpreg_offset (tdep, offsets, regnum);
572 ppc_supply_reg (regcache, regnum, fpregs, offset,
573 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
576 /* Supply register REGNUM in the VSX register set REGSET
577 from the buffer specified by VSXREGS and LEN to register cache
578 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
581 ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
582 int regnum, const void *vsxregs, size_t len)
584 struct gdbarch *gdbarch = get_regcache_arch (regcache);
585 struct gdbarch_tdep *tdep;
587 if (!ppc_vsx_support_p (gdbarch))
590 tdep = gdbarch_tdep (gdbarch);
596 for (i = tdep->ppc_vsr0_upper_regnum;
597 i < tdep->ppc_vsr0_upper_regnum + 32;
599 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
604 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
607 /* Supply register REGNUM in the Altivec register set REGSET
608 from the buffer specified by VRREGS and LEN to register cache
609 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
612 ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
613 int regnum, const void *vrregs, size_t len)
615 struct gdbarch *gdbarch = get_regcache_arch (regcache);
616 struct gdbarch_tdep *tdep;
617 const struct ppc_reg_offsets *offsets;
620 if (!ppc_altivec_support_p (gdbarch))
623 tdep = gdbarch_tdep (gdbarch);
624 offsets = regset->descr;
629 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
630 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
632 ppc_supply_reg (regcache, i, vrregs, offset, 16);
634 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
635 vrregs, offsets->vscr_offset, 4);
637 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
638 vrregs, offsets->vrsave_offset, 4);
642 offset = ppc_vrreg_offset (tdep, offsets, regnum);
643 if (regnum != tdep->ppc_vrsave_regnum
644 && regnum != tdep->ppc_vrsave_regnum - 1)
645 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
647 ppc_supply_reg (regcache, regnum,
651 /* Collect register REGNUM in the general-purpose register set
652 REGSET from register cache REGCACHE into the buffer specified by
653 GREGS and LEN. If REGNUM is -1, do this for all registers in
657 ppc_collect_gregset (const struct regset *regset,
658 const struct regcache *regcache,
659 int regnum, void *gregs, size_t len)
661 struct gdbarch *gdbarch = get_regcache_arch (regcache);
662 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
663 const struct ppc_reg_offsets *offsets = regset->descr;
670 int gpr_size = offsets->gpr_size;
672 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
673 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
674 i++, offset += gpr_size)
675 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
677 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
678 gregs, offsets->pc_offset, gpr_size);
679 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
680 gregs, offsets->ps_offset, gpr_size);
681 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
682 gregs, offsets->lr_offset, gpr_size);
683 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
684 gregs, offsets->ctr_offset, gpr_size);
685 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
686 gregs, offsets->cr_offset, offsets->xr_size);
687 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
688 gregs, offsets->xer_offset, offsets->xr_size);
689 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
690 gregs, offsets->mq_offset, offsets->xr_size);
694 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
695 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
698 /* Collect register REGNUM in the floating-point register set
699 REGSET from register cache REGCACHE into the buffer specified by
700 FPREGS and LEN. If REGNUM is -1, do this for all registers in
704 ppc_collect_fpregset (const struct regset *regset,
705 const struct regcache *regcache,
706 int regnum, void *fpregs, size_t len)
708 struct gdbarch *gdbarch = get_regcache_arch (regcache);
709 struct gdbarch_tdep *tdep;
710 const struct ppc_reg_offsets *offsets;
713 if (!ppc_floating_point_unit_p (gdbarch))
716 tdep = gdbarch_tdep (gdbarch);
717 offsets = regset->descr;
722 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
723 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
725 ppc_collect_reg (regcache, i, fpregs, offset, 8);
727 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
728 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
732 offset = ppc_fpreg_offset (tdep, offsets, regnum);
733 ppc_collect_reg (regcache, regnum, fpregs, offset,
734 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
737 /* Collect register REGNUM in the VSX register set
738 REGSET from register cache REGCACHE into the buffer specified by
739 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
743 ppc_collect_vsxregset (const struct regset *regset,
744 const struct regcache *regcache,
745 int regnum, void *vsxregs, size_t len)
747 struct gdbarch *gdbarch = get_regcache_arch (regcache);
748 struct gdbarch_tdep *tdep;
750 if (!ppc_vsx_support_p (gdbarch))
753 tdep = gdbarch_tdep (gdbarch);
759 for (i = tdep->ppc_vsr0_upper_regnum;
760 i < tdep->ppc_vsr0_upper_regnum + 32;
762 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
767 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
771 /* Collect register REGNUM in the Altivec register set
772 REGSET from register cache REGCACHE into the buffer specified by
773 VRREGS and LEN. If REGNUM is -1, do this for all registers in
777 ppc_collect_vrregset (const struct regset *regset,
778 const struct regcache *regcache,
779 int regnum, void *vrregs, size_t len)
781 struct gdbarch *gdbarch = get_regcache_arch (regcache);
782 struct gdbarch_tdep *tdep;
783 const struct ppc_reg_offsets *offsets;
786 if (!ppc_altivec_support_p (gdbarch))
789 tdep = gdbarch_tdep (gdbarch);
790 offsets = regset->descr;
795 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
796 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
798 ppc_collect_reg (regcache, i, vrregs, offset, 16);
800 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
801 vrregs, offsets->vscr_offset, 4);
803 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
804 vrregs, offsets->vrsave_offset, 4);
808 offset = ppc_vrreg_offset (tdep, offsets, regnum);
809 if (regnum != tdep->ppc_vrsave_regnum
810 && regnum != tdep->ppc_vrsave_regnum - 1)
811 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
813 ppc_collect_reg (regcache, regnum,
819 insn_changes_sp_or_jumps (unsigned long insn)
821 int opcode = (insn >> 26) & 0x03f;
822 int sd = (insn >> 21) & 0x01f;
823 int a = (insn >> 16) & 0x01f;
824 int subcode = (insn >> 1) & 0x3ff;
826 /* Changes the stack pointer. */
828 /* NOTE: There are many ways to change the value of a given register.
829 The ways below are those used when the register is R1, the SP,
830 in a funtion's epilogue. */
832 if (opcode == 31 && subcode == 444 && a == 1)
833 return 1; /* mr R1,Rn */
834 if (opcode == 14 && sd == 1)
835 return 1; /* addi R1,Rn,simm */
836 if (opcode == 58 && sd == 1)
837 return 1; /* ld R1,ds(Rn) */
839 /* Transfers control. */
845 if (opcode == 19 && subcode == 16)
847 if (opcode == 19 && subcode == 528)
848 return 1; /* bcctr */
853 /* Return true if we are in the function's epilogue, i.e. after the
854 instruction that destroyed the function's stack frame.
856 1) scan forward from the point of execution:
857 a) If you find an instruction that modifies the stack pointer
858 or transfers control (except a return), execution is not in
860 b) Stop scanning if you find a return instruction or reach the
861 end of the function or reach the hard limit for the size of
863 2) scan backward from the point of execution:
864 a) If you find an instruction that modifies the stack pointer,
865 execution *is* in an epilogue, return.
866 b) Stop scanning if you reach an instruction that transfers
867 control or the beginning of the function or reach the hard
868 limit for the size of an epilogue. */
871 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
873 bfd_byte insn_buf[PPC_INSN_SIZE];
874 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
876 struct frame_info *curfrm;
878 /* Find the search limits based on function boundaries and hard limit. */
880 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
883 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
884 if (epilogue_start < func_start) epilogue_start = func_start;
886 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
887 if (epilogue_end > func_end) epilogue_end = func_end;
889 curfrm = get_current_frame ();
891 /* Scan forward until next 'blr'. */
893 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
895 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
897 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
898 if (insn == 0x4e800020)
900 if (insn_changes_sp_or_jumps (insn))
904 /* Scan backward until adjustment to stack pointer (R1). */
906 for (scan_pc = pc - PPC_INSN_SIZE;
907 scan_pc >= epilogue_start;
908 scan_pc -= PPC_INSN_SIZE)
910 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
912 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
913 if (insn_changes_sp_or_jumps (insn))
920 /* Get the ith function argument for the current function. */
922 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
925 return get_frame_register_unsigned (frame, 3 + argi);
928 /* Sequence of bytes for breakpoint instruction. */
930 const static unsigned char *
931 rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
934 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
935 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
937 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
938 return big_breakpoint;
940 return little_breakpoint;
943 /* Instruction masks for displaced stepping. */
944 #define BRANCH_MASK 0xfc000000
945 #define BP_MASK 0xFC0007FE
946 #define B_INSN 0x48000000
947 #define BC_INSN 0x40000000
948 #define BXL_INSN 0x4c000000
949 #define BP_INSN 0x7C000008
951 /* Fix up the state of registers and memory after having single-stepped
952 a displaced instruction. */
954 ppc_displaced_step_fixup (struct gdbarch *gdbarch,
955 struct displaced_step_closure *closure,
956 CORE_ADDR from, CORE_ADDR to,
957 struct regcache *regs)
959 /* Since we use simple_displaced_step_copy_insn, our closure is a
960 copy of the instruction. */
961 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
964 /* Offset for non PC-relative instructions. */
965 LONGEST offset = PPC_INSN_SIZE;
967 opcode = insn & BRANCH_MASK;
970 fprintf_unfiltered (gdb_stdlog,
971 "displaced: (ppc) fixup (0x%s, 0x%s)\n",
972 paddr_nz (from), paddr_nz (to));
975 /* Handle PC-relative branch instructions. */
976 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
980 /* Read the current PC value after the instruction has been executed
981 in a displaced location. Calculate the offset to be applied to the
982 original PC value before the displaced stepping. */
983 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
985 offset = current_pc - to;
987 if (opcode != BXL_INSN)
989 /* Check for AA bit indicating whether this is an absolute
990 addressing or PC-relative (1: absolute, 0: relative). */
993 /* PC-relative addressing is being used in the branch. */
997 "displaced: (ppc) branch instruction: 0x%s\n"
998 "displaced: (ppc) adjusted PC from 0x%s to 0x%s\n",
999 paddr_nz (insn), paddr_nz (current_pc),
1000 paddr_nz (from + offset));
1002 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1008 /* If we're here, it means we have a branch to LR or CTR. If the
1009 branch was taken, the offset is probably greater than 4 (the next
1010 instruction), so it's safe to assume that an offset of 4 means we
1011 did not take the branch. */
1012 if (offset == PPC_INSN_SIZE)
1013 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1014 from + PPC_INSN_SIZE);
1017 /* Check for LK bit indicating whether we should set the link
1018 register to point to the next instruction
1019 (1: Set, 0: Don't set). */
1022 /* Link register needs to be set to the next instruction's PC. */
1023 regcache_cooked_write_unsigned (regs,
1024 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1025 from + PPC_INSN_SIZE);
1026 if (debug_displaced)
1027 fprintf_unfiltered (gdb_stdlog,
1028 "displaced: (ppc) adjusted LR to 0x%s\n",
1029 paddr_nz (from + PPC_INSN_SIZE));
1033 /* Check for breakpoints in the inferior. If we've found one, place the PC
1034 right at the breakpoint instruction. */
1035 else if ((insn & BP_MASK) == BP_INSN)
1036 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1038 /* Handle any other instructions that do not fit in the categories above. */
1039 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1043 /* Instruction masks used during single-stepping of atomic sequences. */
1044 #define LWARX_MASK 0xfc0007fe
1045 #define LWARX_INSTRUCTION 0x7c000028
1046 #define LDARX_INSTRUCTION 0x7c0000A8
1047 #define STWCX_MASK 0xfc0007ff
1048 #define STWCX_INSTRUCTION 0x7c00012d
1049 #define STDCX_INSTRUCTION 0x7c0001ad
1051 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1052 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1053 is found, attempt to step through it. A breakpoint is placed at the end of
1057 ppc_deal_with_atomic_sequence (struct frame_info *frame)
1059 CORE_ADDR pc = get_frame_pc (frame);
1060 CORE_ADDR breaks[2] = {-1, -1};
1062 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
1063 int insn = read_memory_integer (loc, PPC_INSN_SIZE);
1066 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1067 const int atomic_sequence_length = 16; /* Instruction sequence length. */
1068 int opcode; /* Branch instruction's OPcode. */
1069 int bc_insn_count = 0; /* Conditional branch instruction count. */
1071 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1072 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1073 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1076 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1078 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1080 loc += PPC_INSN_SIZE;
1081 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1083 /* Assume that there is at most one conditional branch in the atomic
1084 sequence. If a conditional branch is found, put a breakpoint in
1085 its destination address. */
1086 if ((insn & BRANCH_MASK) == BC_INSN)
1088 int immediate = ((insn & ~3) << 16) >> 16;
1089 int absolute = ((insn >> 1) & 1);
1091 if (bc_insn_count >= 1)
1092 return 0; /* More than one conditional branch found, fallback
1093 to the standard single-step code. */
1096 breaks[1] = immediate;
1098 breaks[1] = pc + immediate;
1104 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1105 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1109 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1110 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1111 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1115 loc += PPC_INSN_SIZE;
1116 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1118 /* Insert a breakpoint right after the end of the atomic sequence. */
1121 /* Check for duplicated breakpoints. Check also for a breakpoint
1122 placed (branch instruction's destination) at the stwcx/stdcx
1123 instruction, this resets the reservation and take us back to the
1124 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1125 if (last_breakpoint && ((breaks[1] == breaks[0])
1126 || (breaks[1] == closing_insn)))
1127 last_breakpoint = 0;
1129 /* Effectively inserts the breakpoints. */
1130 for (index = 0; index <= last_breakpoint; index++)
1131 insert_single_step_breakpoint (breaks[index]);
1137 #define SIGNED_SHORT(x) \
1138 ((sizeof (short) == 2) \
1139 ? ((int)(short)(x)) \
1140 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1142 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1144 /* Limit the number of skipped non-prologue instructions, as the examining
1145 of the prologue is expensive. */
1146 static int max_skip_non_prologue_insns = 10;
1148 /* Return nonzero if the given instruction OP can be part of the prologue
1149 of a function and saves a parameter on the stack. FRAMEP should be
1150 set if one of the previous instructions in the function has set the
1154 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1156 /* Move parameters from argument registers to temporary register. */
1157 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1159 /* Rx must be scratch register r0. */
1160 const int rx_regno = (op >> 16) & 31;
1161 /* Ry: Only r3 - r10 are used for parameter passing. */
1162 const int ry_regno = GET_SRC_REG (op);
1164 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1166 *r0_contains_arg = 1;
1173 /* Save a General Purpose Register on stack. */
1175 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1176 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1178 /* Rx: Only r3 - r10 are used for parameter passing. */
1179 const int rx_regno = GET_SRC_REG (op);
1181 return (rx_regno >= 3 && rx_regno <= 10);
1184 /* Save a General Purpose Register on stack via the Frame Pointer. */
1187 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1188 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1189 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1191 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1192 However, the compiler sometimes uses r0 to hold an argument. */
1193 const int rx_regno = GET_SRC_REG (op);
1195 return ((rx_regno >= 3 && rx_regno <= 10)
1196 || (rx_regno == 0 && *r0_contains_arg));
1199 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1201 /* Only f2 - f8 are used for parameter passing. */
1202 const int src_regno = GET_SRC_REG (op);
1204 return (src_regno >= 2 && src_regno <= 8);
1207 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1209 /* Only f2 - f8 are used for parameter passing. */
1210 const int src_regno = GET_SRC_REG (op);
1212 return (src_regno >= 2 && src_regno <= 8);
1215 /* Not an insn that saves a parameter on stack. */
1219 /* Assuming that INSN is a "bl" instruction located at PC, return
1220 nonzero if the destination of the branch is a "blrl" instruction.
1222 This sequence is sometimes found in certain function prologues.
1223 It allows the function to load the LR register with a value that
1224 they can use to access PIC data using PC-relative offsets. */
1227 bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
1234 absolute = (int) ((insn >> 1) & 1);
1235 immediate = ((insn & ~3) << 6) >> 6;
1239 dest = pc + immediate;
1241 dest_insn = read_memory_integer (dest, 4);
1242 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1248 /* Masks for decoding a branch-and-link (bl) instruction.
1250 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1251 The former is anded with the opcode in question; if the result of
1252 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1253 question is a ``bl'' instruction.
1255 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1256 the branch displacement. */
1258 #define BL_MASK 0xfc000001
1259 #define BL_INSTRUCTION 0x48000001
1260 #define BL_DISPLACEMENT_MASK 0x03fffffc
1262 /* return pc value after skipping a function prologue and also return
1263 information about a function frame.
1265 in struct rs6000_framedata fdata:
1266 - frameless is TRUE, if function does not have a frame.
1267 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1268 - offset is the initial size of this stack frame --- the amount by
1269 which we decrement the sp to allocate the frame.
1270 - saved_gpr is the number of the first saved gpr.
1271 - saved_fpr is the number of the first saved fpr.
1272 - saved_vr is the number of the first saved vr.
1273 - saved_ev is the number of the first saved ev.
1274 - alloca_reg is the number of the register used for alloca() handling.
1276 - gpr_offset is the offset of the first saved gpr from the previous frame.
1277 - fpr_offset is the offset of the first saved fpr from the previous frame.
1278 - vr_offset is the offset of the first saved vr from the previous frame.
1279 - ev_offset is the offset of the first saved ev from the previous frame.
1280 - lr_offset is the offset of the saved lr
1281 - cr_offset is the offset of the saved cr
1282 - vrsave_offset is the offset of the saved vrsave register
1286 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1287 struct rs6000_framedata *fdata)
1289 CORE_ADDR orig_pc = pc;
1290 CORE_ADDR last_prologue_pc = pc;
1291 CORE_ADDR li_found_pc = 0;
1295 long vr_saved_offset = 0;
1301 int vrsave_reg = -1;
1304 int minimal_toc_loaded = 0;
1305 int prev_insn_was_prologue_insn = 1;
1306 int num_skip_non_prologue_insns = 0;
1307 int r0_contains_arg = 0;
1308 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1309 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1311 memset (fdata, 0, sizeof (struct rs6000_framedata));
1312 fdata->saved_gpr = -1;
1313 fdata->saved_fpr = -1;
1314 fdata->saved_vr = -1;
1315 fdata->saved_ev = -1;
1316 fdata->alloca_reg = -1;
1317 fdata->frameless = 1;
1318 fdata->nosavedpc = 1;
1322 /* Sometimes it isn't clear if an instruction is a prologue
1323 instruction or not. When we encounter one of these ambiguous
1324 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1325 Otherwise, we'll assume that it really is a prologue instruction. */
1326 if (prev_insn_was_prologue_insn)
1327 last_prologue_pc = pc;
1329 /* Stop scanning if we've hit the limit. */
1333 prev_insn_was_prologue_insn = 1;
1335 /* Fetch the instruction and convert it to an integer. */
1336 if (target_read_memory (pc, buf, 4))
1338 op = extract_unsigned_integer (buf, 4);
1340 if ((op & 0xfc1fffff) == 0x7c0802a6)
1342 /* Since shared library / PIC code, which needs to get its
1343 address at runtime, can appear to save more than one link
1357 remember just the first one, but skip over additional
1360 lr_reg = (op & 0x03e00000);
1362 r0_contains_arg = 0;
1365 else if ((op & 0xfc1fffff) == 0x7c000026)
1367 cr_reg = (op & 0x03e00000);
1369 r0_contains_arg = 0;
1373 else if ((op & 0xfc1f0000) == 0xd8010000)
1374 { /* stfd Rx,NUM(r1) */
1375 reg = GET_SRC_REG (op);
1376 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1378 fdata->saved_fpr = reg;
1379 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1384 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1385 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1386 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1387 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1390 reg = GET_SRC_REG (op);
1391 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1393 fdata->saved_gpr = reg;
1394 if ((op & 0xfc1f0003) == 0xf8010000)
1396 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1401 else if ((op & 0xffff0000) == 0x60000000)
1404 /* Allow nops in the prologue, but do not consider them to
1405 be part of the prologue unless followed by other prologue
1407 prev_insn_was_prologue_insn = 0;
1411 else if ((op & 0xffff0000) == 0x3c000000)
1412 { /* addis 0,0,NUM, used
1413 for >= 32k frames */
1414 fdata->offset = (op & 0x0000ffff) << 16;
1415 fdata->frameless = 0;
1416 r0_contains_arg = 0;
1420 else if ((op & 0xffff0000) == 0x60000000)
1421 { /* ori 0,0,NUM, 2nd ha
1422 lf of >= 32k frames */
1423 fdata->offset |= (op & 0x0000ffff);
1424 fdata->frameless = 0;
1425 r0_contains_arg = 0;
1429 else if (lr_reg >= 0 &&
1430 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1431 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1432 /* stw Rx, NUM(r1) */
1433 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1434 /* stwu Rx, NUM(r1) */
1435 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1436 { /* where Rx == lr */
1437 fdata->lr_offset = offset;
1438 fdata->nosavedpc = 0;
1439 /* Invalidate lr_reg, but don't set it to -1.
1440 That would mean that it had never been set. */
1442 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1443 (op & 0xfc000000) == 0x90000000) /* stw */
1445 /* Does not update r1, so add displacement to lr_offset. */
1446 fdata->lr_offset += SIGNED_SHORT (op);
1451 else if (cr_reg >= 0 &&
1452 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1453 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1454 /* stw Rx, NUM(r1) */
1455 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1456 /* stwu Rx, NUM(r1) */
1457 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1458 { /* where Rx == cr */
1459 fdata->cr_offset = offset;
1460 /* Invalidate cr_reg, but don't set it to -1.
1461 That would mean that it had never been set. */
1463 if ((op & 0xfc000003) == 0xf8000000 ||
1464 (op & 0xfc000000) == 0x90000000)
1466 /* Does not update r1, so add displacement to cr_offset. */
1467 fdata->cr_offset += SIGNED_SHORT (op);
1472 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1474 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1475 prediction bits. If the LR has already been saved, we can
1479 else if (op == 0x48000005)
1485 else if (op == 0x48000004)
1490 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1491 in V.4 -mminimal-toc */
1492 (op & 0xffff0000) == 0x3bde0000)
1493 { /* addi 30,30,foo@l */
1497 else if ((op & 0xfc000001) == 0x48000001)
1501 fdata->frameless = 0;
1503 /* If the return address has already been saved, we can skip
1504 calls to blrl (for PIC). */
1505 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
1508 /* Don't skip over the subroutine call if it is not within
1509 the first three instructions of the prologue and either
1510 we have no line table information or the line info tells
1511 us that the subroutine call is not part of the line
1512 associated with the prologue. */
1513 if ((pc - orig_pc) > 8)
1515 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1516 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1518 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1522 op = read_memory_integer (pc + 4, 4);
1524 /* At this point, make sure this is not a trampoline
1525 function (a function that simply calls another functions,
1526 and nothing else). If the next is not a nop, this branch
1527 was part of the function prologue. */
1529 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1530 break; /* don't skip over
1535 /* update stack pointer */
1536 else if ((op & 0xfc1f0000) == 0x94010000)
1537 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1538 fdata->frameless = 0;
1539 fdata->offset = SIGNED_SHORT (op);
1540 offset = fdata->offset;
1543 else if ((op & 0xfc1f016a) == 0x7c01016e)
1544 { /* stwux rX,r1,rY */
1545 /* no way to figure out what r1 is going to be */
1546 fdata->frameless = 0;
1547 offset = fdata->offset;
1550 else if ((op & 0xfc1f0003) == 0xf8010001)
1551 { /* stdu rX,NUM(r1) */
1552 fdata->frameless = 0;
1553 fdata->offset = SIGNED_SHORT (op & ~3UL);
1554 offset = fdata->offset;
1557 else if ((op & 0xfc1f016a) == 0x7c01016a)
1558 { /* stdux rX,r1,rY */
1559 /* no way to figure out what r1 is going to be */
1560 fdata->frameless = 0;
1561 offset = fdata->offset;
1564 else if ((op & 0xffff0000) == 0x38210000)
1565 { /* addi r1,r1,SIMM */
1566 fdata->frameless = 0;
1567 fdata->offset += SIGNED_SHORT (op);
1568 offset = fdata->offset;
1571 /* Load up minimal toc pointer. Do not treat an epilogue restore
1572 of r31 as a minimal TOC load. */
1573 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1574 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1576 && !minimal_toc_loaded)
1578 minimal_toc_loaded = 1;
1581 /* move parameters from argument registers to local variable
1584 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1585 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1586 (((op >> 21) & 31) <= 10) &&
1587 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1591 /* store parameters in stack */
1593 /* Move parameters from argument registers to temporary register. */
1594 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1598 /* Set up frame pointer */
1600 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1601 || op == 0x7c3f0b78)
1603 fdata->frameless = 0;
1605 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1608 /* Another way to set up the frame pointer. */
1610 else if ((op & 0xfc1fffff) == 0x38010000)
1611 { /* addi rX, r1, 0x0 */
1612 fdata->frameless = 0;
1614 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1615 + ((op & ~0x38010000) >> 21));
1618 /* AltiVec related instructions. */
1619 /* Store the vrsave register (spr 256) in another register for
1620 later manipulation, or load a register into the vrsave
1621 register. 2 instructions are used: mfvrsave and
1622 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1623 and mtspr SPR256, Rn. */
1624 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1625 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1626 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1628 vrsave_reg = GET_SRC_REG (op);
1631 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1635 /* Store the register where vrsave was saved to onto the stack:
1636 rS is the register where vrsave was stored in a previous
1638 /* 100100 sssss 00001 dddddddd dddddddd */
1639 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1641 if (vrsave_reg == GET_SRC_REG (op))
1643 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1648 /* Compute the new value of vrsave, by modifying the register
1649 where vrsave was saved to. */
1650 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1651 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1655 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1656 in a pair of insns to save the vector registers on the
1658 /* 001110 00000 00000 iiii iiii iiii iiii */
1659 /* 001110 01110 00000 iiii iiii iiii iiii */
1660 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1661 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1663 if ((op & 0xffff0000) == 0x38000000)
1664 r0_contains_arg = 0;
1666 vr_saved_offset = SIGNED_SHORT (op);
1668 /* This insn by itself is not part of the prologue, unless
1669 if part of the pair of insns mentioned above. So do not
1670 record this insn as part of the prologue yet. */
1671 prev_insn_was_prologue_insn = 0;
1673 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1674 /* 011111 sssss 11111 00000 00111001110 */
1675 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1677 if (pc == (li_found_pc + 4))
1679 vr_reg = GET_SRC_REG (op);
1680 /* If this is the first vector reg to be saved, or if
1681 it has a lower number than others previously seen,
1682 reupdate the frame info. */
1683 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1685 fdata->saved_vr = vr_reg;
1686 fdata->vr_offset = vr_saved_offset + offset;
1688 vr_saved_offset = -1;
1693 /* End AltiVec related instructions. */
1695 /* Start BookE related instructions. */
1696 /* Store gen register S at (r31+uimm).
1697 Any register less than r13 is volatile, so we don't care. */
1698 /* 000100 sssss 11111 iiiii 01100100001 */
1699 else if (arch_info->mach == bfd_mach_ppc_e500
1700 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1702 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1705 ev_reg = GET_SRC_REG (op);
1706 imm = (op >> 11) & 0x1f;
1707 ev_offset = imm * 8;
1708 /* If this is the first vector reg to be saved, or if
1709 it has a lower number than others previously seen,
1710 reupdate the frame info. */
1711 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1713 fdata->saved_ev = ev_reg;
1714 fdata->ev_offset = ev_offset + offset;
1719 /* Store gen register rS at (r1+rB). */
1720 /* 000100 sssss 00001 bbbbb 01100100000 */
1721 else if (arch_info->mach == bfd_mach_ppc_e500
1722 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1724 if (pc == (li_found_pc + 4))
1726 ev_reg = GET_SRC_REG (op);
1727 /* If this is the first vector reg to be saved, or if
1728 it has a lower number than others previously seen,
1729 reupdate the frame info. */
1730 /* We know the contents of rB from the previous instruction. */
1731 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1733 fdata->saved_ev = ev_reg;
1734 fdata->ev_offset = vr_saved_offset + offset;
1736 vr_saved_offset = -1;
1742 /* Store gen register r31 at (rA+uimm). */
1743 /* 000100 11111 aaaaa iiiii 01100100001 */
1744 else if (arch_info->mach == bfd_mach_ppc_e500
1745 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1747 /* Wwe know that the source register is 31 already, but
1748 it can't hurt to compute it. */
1749 ev_reg = GET_SRC_REG (op);
1750 ev_offset = ((op >> 11) & 0x1f) * 8;
1751 /* If this is the first vector reg to be saved, or if
1752 it has a lower number than others previously seen,
1753 reupdate the frame info. */
1754 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1756 fdata->saved_ev = ev_reg;
1757 fdata->ev_offset = ev_offset + offset;
1762 /* Store gen register S at (r31+r0).
1763 Store param on stack when offset from SP bigger than 4 bytes. */
1764 /* 000100 sssss 11111 00000 01100100000 */
1765 else if (arch_info->mach == bfd_mach_ppc_e500
1766 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1768 if (pc == (li_found_pc + 4))
1770 if ((op & 0x03e00000) >= 0x01a00000)
1772 ev_reg = GET_SRC_REG (op);
1773 /* If this is the first vector reg to be saved, or if
1774 it has a lower number than others previously seen,
1775 reupdate the frame info. */
1776 /* We know the contents of r0 from the previous
1778 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1780 fdata->saved_ev = ev_reg;
1781 fdata->ev_offset = vr_saved_offset + offset;
1785 vr_saved_offset = -1;
1790 /* End BookE related instructions. */
1794 /* Not a recognized prologue instruction.
1795 Handle optimizer code motions into the prologue by continuing
1796 the search if we have no valid frame yet or if the return
1797 address is not yet saved in the frame. */
1798 if (fdata->frameless == 0 && fdata->nosavedpc == 0)
1801 if (op == 0x4e800020 /* blr */
1802 || op == 0x4e800420) /* bctr */
1803 /* Do not scan past epilogue in frameless functions or
1806 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1807 /* Never skip branches. */
1810 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1811 /* Do not scan too many insns, scanning insns is expensive with
1815 /* Continue scanning. */
1816 prev_insn_was_prologue_insn = 0;
1822 /* I have problems with skipping over __main() that I need to address
1823 * sometime. Previously, I used to use misc_function_vector which
1824 * didn't work as well as I wanted to be. -MGO */
1826 /* If the first thing after skipping a prolog is a branch to a function,
1827 this might be a call to an initializer in main(), introduced by gcc2.
1828 We'd like to skip over it as well. Fortunately, xlc does some extra
1829 work before calling a function right after a prologue, thus we can
1830 single out such gcc2 behaviour. */
1833 if ((op & 0xfc000001) == 0x48000001)
1834 { /* bl foo, an initializer function? */
1835 op = read_memory_integer (pc + 4, 4);
1837 if (op == 0x4def7b82)
1838 { /* cror 0xf, 0xf, 0xf (nop) */
1840 /* Check and see if we are in main. If so, skip over this
1841 initializer function as well. */
1843 tmp = find_pc_misc_function (pc);
1845 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1851 fdata->offset = -fdata->offset;
1852 return last_prologue_pc;
1856 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1858 struct rs6000_framedata frame;
1859 CORE_ADDR limit_pc, func_addr;
1861 /* See if we can determine the end of the prologue via the symbol table.
1862 If so, then return either PC, or the PC after the prologue, whichever
1864 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1866 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
1867 if (post_prologue_pc != 0)
1868 return max (pc, post_prologue_pc);
1871 /* Can't determine prologue from the symbol table, need to examine
1874 /* Find an upper limit on the function prologue using the debug
1875 information. If the debug information could not be used to provide
1876 that bound, then use an arbitrary large number as the upper bound. */
1877 limit_pc = skip_prologue_using_sal (pc);
1879 limit_pc = pc + 100; /* Magic. */
1881 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
1885 /* When compiling for EABI, some versions of GCC emit a call to __eabi
1886 in the prologue of main().
1888 The function below examines the code pointed at by PC and checks to
1889 see if it corresponds to a call to __eabi. If so, it returns the
1890 address of the instruction following that call. Otherwise, it simply
1894 rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1899 if (target_read_memory (pc, buf, 4))
1901 op = extract_unsigned_integer (buf, 4);
1903 if ((op & BL_MASK) == BL_INSTRUCTION)
1905 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
1906 CORE_ADDR call_dest = pc + 4 + displ;
1907 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
1909 /* We check for ___eabi (three leading underscores) in addition
1910 to __eabi in case the GCC option "-fleading-underscore" was
1911 used to compile the program. */
1913 && SYMBOL_LINKAGE_NAME (s) != NULL
1914 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
1915 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
1921 /* All the ABI's require 16 byte alignment. */
1923 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1925 return (addr & -16);
1928 /* Return whether handle_inferior_event() should proceed through code
1929 starting at PC in function NAME when stepping.
1931 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1932 handle memory references that are too distant to fit in instructions
1933 generated by the compiler. For example, if 'foo' in the following
1938 is greater than 32767, the linker might replace the lwz with a branch to
1939 somewhere in @FIX1 that does the load in 2 instructions and then branches
1940 back to where execution should continue.
1942 GDB should silently step over @FIX code, just like AIX dbx does.
1943 Unfortunately, the linker uses the "b" instruction for the
1944 branches, meaning that the link register doesn't get set.
1945 Therefore, GDB's usual step_over_function () mechanism won't work.
1947 Instead, use the gdbarch_skip_trampoline_code and
1948 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
1952 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1954 return name && !strncmp (name, "@FIX", 4);
1957 /* Skip code that the user doesn't want to see when stepping:
1959 1. Indirect function calls use a piece of trampoline code to do context
1960 switching, i.e. to set the new TOC table. Skip such code if we are on
1961 its first instruction (as when we have single-stepped to here).
1963 2. Skip shared library trampoline code (which is different from
1964 indirect function call trampolines).
1966 3. Skip bigtoc fixup code.
1968 Result is desired PC to step until, or NULL if we are not in
1969 code that should be skipped. */
1972 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
1974 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
1975 unsigned int ii, op;
1977 CORE_ADDR solib_target_pc;
1978 struct minimal_symbol *msymbol;
1980 static unsigned trampoline_code[] =
1982 0x800b0000, /* l r0,0x0(r11) */
1983 0x90410014, /* st r2,0x14(r1) */
1984 0x7c0903a6, /* mtctr r0 */
1985 0x804b0004, /* l r2,0x4(r11) */
1986 0x816b0008, /* l r11,0x8(r11) */
1987 0x4e800420, /* bctr */
1988 0x4e800020, /* br */
1992 /* Check for bigtoc fixup code. */
1993 msymbol = lookup_minimal_symbol_by_pc (pc);
1995 && rs6000_in_solib_return_trampoline (pc, SYMBOL_LINKAGE_NAME (msymbol)))
1997 /* Double-check that the third instruction from PC is relative "b". */
1998 op = read_memory_integer (pc + 8, 4);
1999 if ((op & 0xfc000003) == 0x48000000)
2001 /* Extract bits 6-29 as a signed 24-bit relative word address and
2002 add it to the containing PC. */
2003 rel = ((int)(op << 6) >> 6);
2004 return pc + 8 + rel;
2008 /* If pc is in a shared library trampoline, return its target. */
2009 solib_target_pc = find_solib_trampoline_target (frame, pc);
2010 if (solib_target_pc)
2011 return solib_target_pc;
2013 for (ii = 0; trampoline_code[ii]; ++ii)
2015 op = read_memory_integer (pc + (ii * 4), 4);
2016 if (op != trampoline_code[ii])
2019 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
2020 pc = read_memory_unsigned_integer (ii, tdep->wordsize); /* (r11) value */
2024 /* ISA-specific vector types. */
2026 static struct type *
2027 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2029 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2031 if (!tdep->ppc_builtin_type_vec64)
2033 /* The type we're building is this: */
2035 union __gdb_builtin_type_vec64
2039 int32_t v2_int32[2];
2040 int16_t v4_int16[4];
2047 t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2048 append_composite_type_field (t, "uint64", builtin_type_int64);
2049 append_composite_type_field (t, "v2_float",
2050 init_vector_type (builtin_type_float, 2));
2051 append_composite_type_field (t, "v2_int32",
2052 init_vector_type (builtin_type_int32, 2));
2053 append_composite_type_field (t, "v4_int16",
2054 init_vector_type (builtin_type_int16, 4));
2055 append_composite_type_field (t, "v8_int8",
2056 init_vector_type (builtin_type_int8, 8));
2058 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR;
2059 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2060 tdep->ppc_builtin_type_vec64 = t;
2063 return tdep->ppc_builtin_type_vec64;
2066 /* Vector 128 type. */
2068 static struct type *
2069 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2071 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2073 if (!tdep->ppc_builtin_type_vec128)
2075 /* The type we're building is this
2077 type = union __ppc_builtin_type_vec128 {
2080 int32_t v4_int32[4];
2081 int16_t v8_int16[8];
2082 int8_t v16_int8[16];
2088 t = init_composite_type ("__ppc_builtin_type_vec128", TYPE_CODE_UNION);
2089 append_composite_type_field (t, "uint128", builtin_type_uint128);
2090 append_composite_type_field (t, "v4_float",
2091 init_vector_type (builtin_type (gdbarch)->builtin_float, 4));
2092 append_composite_type_field (t, "v4_int32",
2093 init_vector_type (builtin_type_int32, 4));
2094 append_composite_type_field (t, "v8_int16",
2095 init_vector_type (builtin_type_int16, 8));
2096 append_composite_type_field (t, "v16_int8",
2097 init_vector_type (builtin_type_int8, 16));
2099 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR;
2100 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2101 tdep->ppc_builtin_type_vec128 = t;
2104 return tdep->ppc_builtin_type_vec128;
2107 /* Return the name of register number REGNO, or the empty string if it
2108 is an anonymous register. */
2111 rs6000_register_name (struct gdbarch *gdbarch, int regno)
2113 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2115 /* The upper half "registers" have names in the XML description,
2116 but we present only the low GPRs and the full 64-bit registers
2118 if (tdep->ppc_ev0_upper_regnum >= 0
2119 && tdep->ppc_ev0_upper_regnum <= regno
2120 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2123 /* Hide the upper halves of the vs0~vs31 registers. */
2124 if (tdep->ppc_vsr0_regnum >= 0
2125 && tdep->ppc_vsr0_upper_regnum <= regno
2126 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2129 /* Check if the SPE pseudo registers are available. */
2130 if (IS_SPE_PSEUDOREG (tdep, regno))
2132 static const char *const spe_regnames[] = {
2133 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2134 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2135 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2136 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2138 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2141 /* Check if the decimal128 pseudo-registers are available. */
2142 if (IS_DFP_PSEUDOREG (tdep, regno))
2144 static const char *const dfp128_regnames[] = {
2145 "dl0", "dl1", "dl2", "dl3",
2146 "dl4", "dl5", "dl6", "dl7",
2147 "dl8", "dl9", "dl10", "dl11",
2148 "dl12", "dl13", "dl14", "dl15"
2150 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2153 /* Check if this is a VSX pseudo-register. */
2154 if (IS_VSX_PSEUDOREG (tdep, regno))
2156 static const char *const vsx_regnames[] = {
2157 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2158 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2159 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2160 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2161 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2162 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2163 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2164 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2165 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2167 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2170 /* Check if the this is a Extended FP pseudo-register. */
2171 if (IS_EFP_PSEUDOREG (tdep, regno))
2173 static const char *const efpr_regnames[] = {
2174 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2175 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2176 "f46", "f47", "f48", "f49", "f50", "f51",
2177 "f52", "f53", "f54", "f55", "f56", "f57",
2178 "f58", "f59", "f60", "f61", "f62", "f63"
2180 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2183 return tdesc_register_name (gdbarch, regno);
2186 /* Return the GDB type object for the "standard" data type of data in
2189 static struct type *
2190 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2192 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2194 /* These are the only pseudo-registers we support. */
2195 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2196 || IS_DFP_PSEUDOREG (tdep, regnum)
2197 || IS_VSX_PSEUDOREG (tdep, regnum)
2198 || IS_EFP_PSEUDOREG (tdep, regnum));
2200 /* These are the e500 pseudo-registers. */
2201 if (IS_SPE_PSEUDOREG (tdep, regnum))
2202 return rs6000_builtin_type_vec64 (gdbarch);
2203 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2204 /* PPC decimal128 pseudo-registers. */
2205 return builtin_type (gdbarch)->builtin_declong;
2206 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2207 /* POWER7 VSX pseudo-registers. */
2208 return rs6000_builtin_type_vec128 (gdbarch);
2210 /* POWER7 Extended FP pseudo-registers. */
2211 return builtin_type (gdbarch)->builtin_double;
2214 /* Is REGNUM a member of REGGROUP? */
2216 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2217 struct reggroup *group)
2219 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2221 /* These are the only pseudo-registers we support. */
2222 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2223 || IS_DFP_PSEUDOREG (tdep, regnum)
2224 || IS_VSX_PSEUDOREG (tdep, regnum)
2225 || IS_EFP_PSEUDOREG (tdep, regnum));
2227 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2228 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
2229 return group == all_reggroup || group == vector_reggroup;
2231 /* PPC decimal128 or Extended FP pseudo-registers. */
2232 return group == all_reggroup || group == float_reggroup;
2235 /* The register format for RS/6000 floating point registers is always
2236 double, we need a conversion if the memory format is float. */
2239 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2242 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2244 return (tdep->ppc_fp0_regnum >= 0
2245 && regnum >= tdep->ppc_fp0_regnum
2246 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2247 && TYPE_CODE (type) == TYPE_CODE_FLT
2248 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2252 rs6000_register_to_value (struct frame_info *frame,
2257 gdb_byte from[MAX_REGISTER_SIZE];
2259 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2261 get_frame_register (frame, regnum, from);
2262 convert_typed_floating (from, builtin_type_double, to, type);
2266 rs6000_value_to_register (struct frame_info *frame,
2269 const gdb_byte *from)
2271 gdb_byte to[MAX_REGISTER_SIZE];
2273 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2275 convert_typed_floating (from, type, to, builtin_type_double);
2276 put_frame_register (frame, regnum, to);
2279 /* Move SPE vector register values between a 64-bit buffer and the two
2280 32-bit raw register halves in a regcache. This function handles
2281 both splitting a 64-bit value into two 32-bit halves, and joining
2282 two halves into a whole 64-bit value, depending on the function
2283 passed as the MOVE argument.
2285 EV_REG must be the number of an SPE evN vector register --- a
2286 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2289 Call MOVE once for each 32-bit half of that register, passing
2290 REGCACHE, the number of the raw register corresponding to that
2291 half, and the address of the appropriate half of BUFFER.
2293 For example, passing 'regcache_raw_read' as the MOVE function will
2294 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2295 'regcache_raw_supply' will supply the contents of BUFFER to the
2296 appropriate pair of raw registers in REGCACHE.
2298 You may need to cast away some 'const' qualifiers when passing
2299 MOVE, since this function can't tell at compile-time which of
2300 REGCACHE or BUFFER is acting as the source of the data. If C had
2301 co-variant type qualifiers, ... */
2303 e500_move_ev_register (void (*move) (struct regcache *regcache,
2304 int regnum, gdb_byte *buf),
2305 struct regcache *regcache, int ev_reg,
2308 struct gdbarch *arch = get_regcache_arch (regcache);
2309 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2311 gdb_byte *byte_buffer = buffer;
2313 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
2315 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2317 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2319 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2320 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2324 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2325 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2330 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2331 int reg_nr, gdb_byte *buffer)
2333 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2337 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2338 int reg_nr, const gdb_byte *buffer)
2340 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2342 regcache, reg_nr, (gdb_byte *) buffer);
2345 /* Read method for DFP pseudo-registers. */
2347 dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2348 int reg_nr, gdb_byte *buffer)
2350 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2351 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2353 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2355 /* Read two FP registers to form a whole dl register. */
2356 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2357 2 * reg_index, buffer);
2358 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2359 2 * reg_index + 1, buffer + 8);
2363 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2364 2 * reg_index + 1, buffer + 8);
2365 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2366 2 * reg_index, buffer);
2370 /* Write method for DFP pseudo-registers. */
2372 dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2373 int reg_nr, const gdb_byte *buffer)
2375 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2376 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2378 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2380 /* Write each half of the dl register into a separate
2382 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2383 2 * reg_index, buffer);
2384 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2385 2 * reg_index + 1, buffer + 8);
2389 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2390 2 * reg_index + 1, buffer + 8);
2391 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2392 2 * reg_index, buffer);
2396 /* Read method for POWER7 VSX pseudo-registers. */
2398 vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2399 int reg_nr, gdb_byte *buffer)
2401 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2402 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2404 /* Read the portion that overlaps the VMX registers. */
2406 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2407 reg_index - 32, buffer);
2409 /* Read the portion that overlaps the FPR registers. */
2410 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2412 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2414 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2415 reg_index, buffer + 8);
2419 regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2420 reg_index, buffer + 8);
2421 regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2426 /* Write method for POWER7 VSX pseudo-registers. */
2428 vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2429 int reg_nr, const gdb_byte *buffer)
2431 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2432 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2434 /* Write the portion that overlaps the VMX registers. */
2436 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2437 reg_index - 32, buffer);
2439 /* Write the portion that overlaps the FPR registers. */
2440 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2442 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2444 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2445 reg_index, buffer + 8);
2449 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2450 reg_index, buffer + 8);
2451 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2456 /* Read method for POWER7 Extended FP pseudo-registers. */
2458 efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2459 int reg_nr, gdb_byte *buffer)
2461 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2462 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2464 /* Read the portion that overlaps the VMX registers. */
2465 regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2469 /* Write method for POWER7 Extended FP pseudo-registers. */
2471 efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2472 int reg_nr, const gdb_byte *buffer)
2474 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2475 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2477 /* Write the portion that overlaps the VMX registers. */
2478 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2483 rs6000_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2484 int reg_nr, gdb_byte *buffer)
2486 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2487 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2489 gdb_assert (regcache_arch == gdbarch);
2491 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2492 e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2493 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2494 dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2495 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2496 vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2497 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2498 efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2500 internal_error (__FILE__, __LINE__,
2501 _("rs6000_pseudo_register_read: "
2502 "called on unexpected register '%s' (%d)"),
2503 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2507 rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2508 struct regcache *regcache,
2509 int reg_nr, const gdb_byte *buffer)
2511 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2512 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2514 gdb_assert (regcache_arch == gdbarch);
2516 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2517 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2518 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2519 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2520 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2521 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2522 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2523 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2525 internal_error (__FILE__, __LINE__,
2526 _("rs6000_pseudo_register_write: "
2527 "called on unexpected register '%s' (%d)"),
2528 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2531 /* Convert a DBX STABS register number to a GDB register number. */
2533 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
2535 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2537 if (0 <= num && num <= 31)
2538 return tdep->ppc_gp0_regnum + num;
2539 else if (32 <= num && num <= 63)
2540 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2541 specifies registers the architecture doesn't have? Our
2542 callers don't check the value we return. */
2543 return tdep->ppc_fp0_regnum + (num - 32);
2544 else if (77 <= num && num <= 108)
2545 return tdep->ppc_vr0_regnum + (num - 77);
2546 else if (1200 <= num && num < 1200 + 32)
2547 return tdep->ppc_ev0_regnum + (num - 1200);
2552 return tdep->ppc_mq_regnum;
2554 return tdep->ppc_lr_regnum;
2556 return tdep->ppc_ctr_regnum;
2558 return tdep->ppc_xer_regnum;
2560 return tdep->ppc_vrsave_regnum;
2562 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2564 return tdep->ppc_acc_regnum;
2566 return tdep->ppc_spefscr_regnum;
2573 /* Convert a Dwarf 2 register number to a GDB register number. */
2575 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
2577 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2579 if (0 <= num && num <= 31)
2580 return tdep->ppc_gp0_regnum + num;
2581 else if (32 <= num && num <= 63)
2582 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2583 specifies registers the architecture doesn't have? Our
2584 callers don't check the value we return. */
2585 return tdep->ppc_fp0_regnum + (num - 32);
2586 else if (1124 <= num && num < 1124 + 32)
2587 return tdep->ppc_vr0_regnum + (num - 1124);
2588 else if (1200 <= num && num < 1200 + 32)
2589 return tdep->ppc_ev0_regnum + (num - 1200);
2594 return tdep->ppc_cr_regnum;
2596 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2598 return tdep->ppc_acc_regnum;
2600 return tdep->ppc_mq_regnum;
2602 return tdep->ppc_xer_regnum;
2604 return tdep->ppc_lr_regnum;
2606 return tdep->ppc_ctr_regnum;
2608 return tdep->ppc_vrsave_regnum;
2610 return tdep->ppc_spefscr_regnum;
2616 /* Translate a .eh_frame register to DWARF register, or adjust a
2617 .debug_frame register. */
2620 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2622 /* GCC releases before 3.4 use GCC internal register numbering in
2623 .debug_frame (and .debug_info, et cetera). The numbering is
2624 different from the standard SysV numbering for everything except
2625 for GPRs and FPRs. We can not detect this problem in most cases
2626 - to get accurate debug info for variables living in lr, ctr, v0,
2627 et cetera, use a newer version of GCC. But we must detect
2628 one important case - lr is in column 65 in .debug_frame output,
2631 GCC 3.4, and the "hammer" branch, have a related problem. They
2632 record lr register saves in .debug_frame as 108, but still record
2633 the return column as 65. We fix that up too.
2635 We can do this because 65 is assigned to fpsr, and GCC never
2636 generates debug info referring to it. To add support for
2637 handwritten debug info that restores fpsr, we would need to add a
2638 producer version check to this. */
2647 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2648 internal register numbering; translate that to the standard DWARF2
2649 register numbering. */
2650 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2652 else if (68 <= num && num <= 75) /* cr0-cr8 */
2653 return num - 68 + 86;
2654 else if (77 <= num && num <= 108) /* vr0-vr31 */
2655 return num - 77 + 1124;
2667 case 109: /* vrsave */
2669 case 110: /* vscr */
2671 case 111: /* spe_acc */
2673 case 112: /* spefscr */
2681 /* Handling the various POWER/PowerPC variants. */
2683 /* Information about a particular processor variant. */
2687 /* Name of this variant. */
2690 /* English description of the variant. */
2693 /* bfd_arch_info.arch corresponding to variant. */
2694 enum bfd_architecture arch;
2696 /* bfd_arch_info.mach corresponding to variant. */
2699 /* Target description for this variant. */
2700 struct target_desc **tdesc;
2703 static struct variant variants[] =
2705 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2706 bfd_mach_ppc, &tdesc_powerpc_altivec32},
2707 {"power", "POWER user-level", bfd_arch_rs6000,
2708 bfd_mach_rs6k, &tdesc_rs6000},
2709 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2710 bfd_mach_ppc_403, &tdesc_powerpc_403},
2711 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2712 bfd_mach_ppc_601, &tdesc_powerpc_601},
2713 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2714 bfd_mach_ppc_602, &tdesc_powerpc_602},
2715 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2716 bfd_mach_ppc_603, &tdesc_powerpc_603},
2717 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2718 604, &tdesc_powerpc_604},
2719 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2720 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
2721 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2722 bfd_mach_ppc_505, &tdesc_powerpc_505},
2723 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2724 bfd_mach_ppc_860, &tdesc_powerpc_860},
2725 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2726 bfd_mach_ppc_750, &tdesc_powerpc_750},
2727 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2728 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
2729 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2730 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
2733 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2734 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
2735 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2736 bfd_mach_ppc_620, &tdesc_powerpc_64},
2737 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2738 bfd_mach_ppc_630, &tdesc_powerpc_64},
2739 {"a35", "PowerPC A35", bfd_arch_powerpc,
2740 bfd_mach_ppc_a35, &tdesc_powerpc_64},
2741 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2742 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
2743 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2744 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
2746 /* FIXME: I haven't checked the register sets of the following. */
2747 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2748 bfd_mach_rs6k_rs1, &tdesc_rs6000},
2749 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2750 bfd_mach_rs6k_rsc, &tdesc_rs6000},
2751 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2752 bfd_mach_rs6k_rs2, &tdesc_rs6000},
2757 /* Return the variant corresponding to architecture ARCH and machine number
2758 MACH. If no such variant exists, return null. */
2760 static const struct variant *
2761 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2763 const struct variant *v;
2765 for (v = variants; v->name; v++)
2766 if (arch == v->arch && mach == v->mach)
2773 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2775 if (!info->disassembler_options)
2776 info->disassembler_options = "any";
2778 if (info->endian == BFD_ENDIAN_BIG)
2779 return print_insn_big_powerpc (memaddr, info);
2781 return print_insn_little_powerpc (memaddr, info);
2785 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2787 return frame_unwind_register_unsigned (next_frame,
2788 gdbarch_pc_regnum (gdbarch));
2791 static struct frame_id
2792 rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2794 return frame_id_build (get_frame_register_unsigned
2795 (this_frame, gdbarch_sp_regnum (gdbarch)),
2796 get_frame_pc (this_frame));
2799 struct rs6000_frame_cache
2802 CORE_ADDR initial_sp;
2803 struct trad_frame_saved_reg *saved_regs;
2806 static struct rs6000_frame_cache *
2807 rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
2809 struct rs6000_frame_cache *cache;
2810 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2811 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2812 struct rs6000_framedata fdata;
2813 int wordsize = tdep->wordsize;
2816 if ((*this_cache) != NULL)
2817 return (*this_cache);
2818 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2819 (*this_cache) = cache;
2820 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2822 func = get_frame_func (this_frame);
2823 pc = get_frame_pc (this_frame);
2824 skip_prologue (gdbarch, func, pc, &fdata);
2826 /* Figure out the parent's stack pointer. */
2828 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2829 address of the current frame. Things might be easier if the
2830 ->frame pointed to the outer-most address of the frame. In
2831 the mean time, the address of the prev frame is used as the
2832 base address of this frame. */
2833 cache->base = get_frame_register_unsigned
2834 (this_frame, gdbarch_sp_regnum (gdbarch));
2836 /* If the function appears to be frameless, check a couple of likely
2837 indicators that we have simply failed to find the frame setup.
2838 Two common cases of this are missing symbols (i.e.
2839 get_frame_func returns the wrong address or 0), and assembly
2840 stubs which have a fast exit path but set up a frame on the slow
2843 If the LR appears to return to this function, then presume that
2844 we have an ABI compliant frame that we failed to find. */
2845 if (fdata.frameless && fdata.lr_offset == 0)
2850 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
2851 if (func == 0 && saved_lr == pc)
2855 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
2856 if (func == saved_func)
2862 fdata.frameless = 0;
2863 fdata.lr_offset = tdep->lr_frame_offset;
2867 if (!fdata.frameless)
2868 /* Frameless really means stackless. */
2869 cache->base = read_memory_unsigned_integer (cache->base, wordsize);
2871 trad_frame_set_value (cache->saved_regs,
2872 gdbarch_sp_regnum (gdbarch), cache->base);
2874 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2875 All fpr's from saved_fpr to fp31 are saved. */
2877 if (fdata.saved_fpr >= 0)
2880 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
2882 /* If skip_prologue says floating-point registers were saved,
2883 but the current architecture has no floating-point registers,
2884 then that's strange. But we have no indices to even record
2885 the addresses under, so we just ignore it. */
2886 if (ppc_floating_point_unit_p (gdbarch))
2887 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
2889 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2894 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2895 All gpr's from saved_gpr to gpr31 are saved. */
2897 if (fdata.saved_gpr >= 0)
2900 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
2901 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
2903 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2904 gpr_addr += wordsize;
2908 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2909 All vr's from saved_vr to vr31 are saved. */
2910 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2912 if (fdata.saved_vr >= 0)
2915 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2916 for (i = fdata.saved_vr; i < 32; i++)
2918 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2919 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2924 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2925 All vr's from saved_ev to ev31 are saved. ????? */
2926 if (tdep->ppc_ev0_regnum != -1)
2928 if (fdata.saved_ev >= 0)
2931 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
2932 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
2934 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2935 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2936 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2941 /* If != 0, fdata.cr_offset is the offset from the frame that
2943 if (fdata.cr_offset != 0)
2944 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2946 /* If != 0, fdata.lr_offset is the offset from the frame that
2948 if (fdata.lr_offset != 0)
2949 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2950 /* The PC is found in the link register. */
2951 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
2952 cache->saved_regs[tdep->ppc_lr_regnum];
2954 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2955 holds the VRSAVE. */
2956 if (fdata.vrsave_offset != 0)
2957 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2959 if (fdata.alloca_reg < 0)
2960 /* If no alloca register used, then fi->frame is the value of the
2961 %sp for this frame, and it is good enough. */
2963 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
2966 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
2972 rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
2973 struct frame_id *this_id)
2975 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
2977 /* This marks the outermost frame. */
2978 if (info->base == 0)
2981 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
2984 static struct value *
2985 rs6000_frame_prev_register (struct frame_info *this_frame,
2986 void **this_cache, int regnum)
2988 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
2990 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
2993 static const struct frame_unwind rs6000_frame_unwind =
2996 rs6000_frame_this_id,
2997 rs6000_frame_prev_register,
2999 default_frame_sniffer
3004 rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
3006 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3008 return info->initial_sp;
3011 static const struct frame_base rs6000_frame_base = {
3012 &rs6000_frame_unwind,
3013 rs6000_frame_base_address,
3014 rs6000_frame_base_address,
3015 rs6000_frame_base_address
3018 static const struct frame_base *
3019 rs6000_frame_base_sniffer (struct frame_info *this_frame)
3021 return &rs6000_frame_base;
3024 /* DWARF-2 frame support. Used to handle the detection of
3025 clobbered registers during function calls. */
3028 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3029 struct dwarf2_frame_state_reg *reg,
3030 struct frame_info *this_frame)
3032 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3034 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3035 non-volatile registers. We will use the same code for both. */
3037 /* Call-saved GP registers. */
3038 if ((regnum >= tdep->ppc_gp0_regnum + 14
3039 && regnum <= tdep->ppc_gp0_regnum + 31)
3040 || (regnum == tdep->ppc_gp0_regnum + 1))
3041 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3043 /* Call-clobbered GP registers. */
3044 if ((regnum >= tdep->ppc_gp0_regnum + 3
3045 && regnum <= tdep->ppc_gp0_regnum + 12)
3046 || (regnum == tdep->ppc_gp0_regnum))
3047 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3049 /* Deal with FP registers, if supported. */
3050 if (tdep->ppc_fp0_regnum >= 0)
3052 /* Call-saved FP registers. */
3053 if ((regnum >= tdep->ppc_fp0_regnum + 14
3054 && regnum <= tdep->ppc_fp0_regnum + 31))
3055 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3057 /* Call-clobbered FP registers. */
3058 if ((regnum >= tdep->ppc_fp0_regnum
3059 && regnum <= tdep->ppc_fp0_regnum + 13))
3060 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3063 /* Deal with ALTIVEC registers, if supported. */
3064 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3066 /* Call-saved Altivec registers. */
3067 if ((regnum >= tdep->ppc_vr0_regnum + 20
3068 && regnum <= tdep->ppc_vr0_regnum + 31)
3069 || regnum == tdep->ppc_vrsave_regnum)
3070 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3072 /* Call-clobbered Altivec registers. */
3073 if ((regnum >= tdep->ppc_vr0_regnum
3074 && regnum <= tdep->ppc_vr0_regnum + 19))
3075 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3078 /* Handle PC register and Stack Pointer correctly. */
3079 if (regnum == gdbarch_pc_regnum (gdbarch))
3080 reg->how = DWARF2_FRAME_REG_RA;
3081 else if (regnum == gdbarch_sp_regnum (gdbarch))
3082 reg->how = DWARF2_FRAME_REG_CFA;
3086 /* Initialize the current architecture based on INFO. If possible, re-use an
3087 architecture from ARCHES, which is a list of architectures already created
3088 during this debugging session.
3090 Called e.g. at program startup, when reading a core file, and when reading
3093 static struct gdbarch *
3094 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3096 struct gdbarch *gdbarch;
3097 struct gdbarch_tdep *tdep;
3098 int wordsize, from_xcoff_exec, from_elf_exec;
3099 enum bfd_architecture arch;
3103 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3105 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
3106 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3108 int tdesc_wordsize = -1;
3109 const struct target_desc *tdesc = info.target_desc;
3110 struct tdesc_arch_data *tdesc_data = NULL;
3111 int num_pseudoregs = 0;
3114 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3115 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3117 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3118 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3120 /* Check word size. If INFO is from a binary file, infer it from
3121 that, else choose a likely default. */
3122 if (from_xcoff_exec)
3124 if (bfd_xcoff_is_xcoff64 (info.abfd))
3129 else if (from_elf_exec)
3131 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3136 else if (tdesc_has_registers (tdesc))
3140 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3141 wordsize = info.bfd_arch_info->bits_per_word /
3142 info.bfd_arch_info->bits_per_byte;
3147 /* Get the architecture and machine from the BFD. */
3148 arch = info.bfd_arch_info->arch;
3149 mach = info.bfd_arch_info->mach;
3151 /* For e500 executables, the apuinfo section is of help here. Such
3152 section contains the identifier and revision number of each
3153 Application-specific Processing Unit that is present on the
3154 chip. The content of the section is determined by the assembler
3155 which looks at each instruction and determines which unit (and
3156 which version of it) can execute it. In our case we just look for
3157 the existance of the section. */
3161 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3164 arch = info.bfd_arch_info->arch;
3165 mach = bfd_mach_ppc_e500;
3166 bfd_default_set_arch_mach (&abfd, arch, mach);
3167 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3171 /* Find a default target description which describes our register
3172 layout, if we do not already have one. */
3173 if (! tdesc_has_registers (tdesc))
3175 const struct variant *v;
3177 /* Choose variant. */
3178 v = find_variant_by_arch (arch, mach);
3185 gdb_assert (tdesc_has_registers (tdesc));
3187 /* Check any target description for validity. */
3188 if (tdesc_has_registers (tdesc))
3190 static const char *const gprs[] = {
3191 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3192 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3193 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3194 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3196 static const char *const segment_regs[] = {
3197 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3198 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3200 const struct tdesc_feature *feature;
3202 static const char *const msr_names[] = { "msr", "ps" };
3203 static const char *const cr_names[] = { "cr", "cnd" };
3204 static const char *const ctr_names[] = { "ctr", "cnt" };
3206 feature = tdesc_find_feature (tdesc,
3207 "org.gnu.gdb.power.core");
3208 if (feature == NULL)
3211 tdesc_data = tdesc_data_alloc ();
3214 for (i = 0; i < ppc_num_gprs; i++)
3215 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3216 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3218 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3220 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3223 /* Allow alternate names for these registers, to accomodate GDB's
3225 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3226 PPC_MSR_REGNUM, msr_names);
3227 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3228 PPC_CR_REGNUM, cr_names);
3229 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3230 PPC_CTR_REGNUM, ctr_names);
3234 tdesc_data_cleanup (tdesc_data);
3238 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3241 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3243 wordsize = tdesc_wordsize;
3245 feature = tdesc_find_feature (tdesc,
3246 "org.gnu.gdb.power.fpu");
3247 if (feature != NULL)
3249 static const char *const fprs[] = {
3250 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3251 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3252 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3253 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3256 for (i = 0; i < ppc_num_fprs; i++)
3257 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3258 PPC_F0_REGNUM + i, fprs[i]);
3259 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3260 PPC_FPSCR_REGNUM, "fpscr");
3264 tdesc_data_cleanup (tdesc_data);
3272 /* The DFP pseudo-registers will be available when there are floating
3274 have_dfp = have_fpu;
3276 feature = tdesc_find_feature (tdesc,
3277 "org.gnu.gdb.power.altivec");
3278 if (feature != NULL)
3280 static const char *const vector_regs[] = {
3281 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3282 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3283 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3284 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3288 for (i = 0; i < ppc_num_gprs; i++)
3289 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3292 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3293 PPC_VSCR_REGNUM, "vscr");
3294 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3295 PPC_VRSAVE_REGNUM, "vrsave");
3297 if (have_spe || !valid_p)
3299 tdesc_data_cleanup (tdesc_data);
3307 /* Check for POWER7 VSX registers support. */
3308 feature = tdesc_find_feature (tdesc,
3309 "org.gnu.gdb.power.vsx");
3311 if (feature != NULL)
3313 static const char *const vsx_regs[] = {
3314 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3315 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3316 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3317 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3318 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3324 for (i = 0; i < ppc_num_vshrs; i++)
3325 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3326 PPC_VSR0_UPPER_REGNUM + i,
3330 tdesc_data_cleanup (tdesc_data);
3339 /* On machines supporting the SPE APU, the general-purpose registers
3340 are 64 bits long. There are SIMD vector instructions to treat them
3341 as pairs of floats, but the rest of the instruction set treats them
3342 as 32-bit registers, and only operates on their lower halves.
3344 In the GDB regcache, we treat their high and low halves as separate
3345 registers. The low halves we present as the general-purpose
3346 registers, and then we have pseudo-registers that stitch together
3347 the upper and lower halves and present them as pseudo-registers.
3349 Thus, the target description is expected to supply the upper
3350 halves separately. */
3352 feature = tdesc_find_feature (tdesc,
3353 "org.gnu.gdb.power.spe");
3354 if (feature != NULL)
3356 static const char *const upper_spe[] = {
3357 "ev0h", "ev1h", "ev2h", "ev3h",
3358 "ev4h", "ev5h", "ev6h", "ev7h",
3359 "ev8h", "ev9h", "ev10h", "ev11h",
3360 "ev12h", "ev13h", "ev14h", "ev15h",
3361 "ev16h", "ev17h", "ev18h", "ev19h",
3362 "ev20h", "ev21h", "ev22h", "ev23h",
3363 "ev24h", "ev25h", "ev26h", "ev27h",
3364 "ev28h", "ev29h", "ev30h", "ev31h"
3368 for (i = 0; i < ppc_num_gprs; i++)
3369 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3370 PPC_SPE_UPPER_GP0_REGNUM + i,
3372 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3373 PPC_SPE_ACC_REGNUM, "acc");
3374 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3375 PPC_SPE_FSCR_REGNUM, "spefscr");
3377 if (have_mq || have_fpu || !valid_p)
3379 tdesc_data_cleanup (tdesc_data);
3388 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3389 complain for a 32-bit binary on a 64-bit target; we do not yet
3390 support that. For instance, the 32-bit ABI routines expect
3393 As long as there isn't an explicit target description, we'll
3394 choose one based on the BFD architecture and get a word size
3395 matching the binary (probably powerpc:common or
3396 powerpc:common64). So there is only trouble if a 64-bit target
3397 supplies a 64-bit description while debugging a 32-bit
3399 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3401 tdesc_data_cleanup (tdesc_data);
3406 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3408 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3409 Tag_GNU_Power_ABI_FP))
3412 soft_float_flag = AUTO_BOOLEAN_FALSE;
3415 soft_float_flag = AUTO_BOOLEAN_TRUE;
3422 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3424 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3425 Tag_GNU_Power_ABI_Vector))
3428 vector_abi = POWERPC_VEC_GENERIC;
3431 vector_abi = POWERPC_VEC_ALTIVEC;
3434 vector_abi = POWERPC_VEC_SPE;
3442 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3444 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3447 soft_float = !have_fpu;
3449 /* If we have a hard float binary or setting but no floating point
3450 registers, downgrade to soft float anyway. We're still somewhat
3451 useful in this scenario. */
3452 if (!soft_float && !have_fpu)
3455 /* Similarly for vector registers. */
3456 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3457 vector_abi = POWERPC_VEC_GENERIC;
3459 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3460 vector_abi = POWERPC_VEC_GENERIC;
3462 if (vector_abi == POWERPC_VEC_AUTO)
3465 vector_abi = POWERPC_VEC_ALTIVEC;
3467 vector_abi = POWERPC_VEC_SPE;
3469 vector_abi = POWERPC_VEC_GENERIC;
3472 /* Do not limit the vector ABI based on available hardware, since we
3473 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3475 /* Find a candidate among extant architectures. */
3476 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3478 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3480 /* Word size in the various PowerPC bfd_arch_info structs isn't
3481 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3482 separate word size check. */
3483 tdep = gdbarch_tdep (arches->gdbarch);
3484 if (tdep && tdep->soft_float != soft_float)
3486 if (tdep && tdep->vector_abi != vector_abi)
3488 if (tdep && tdep->wordsize == wordsize)
3490 if (tdesc_data != NULL)
3491 tdesc_data_cleanup (tdesc_data);
3492 return arches->gdbarch;
3496 /* None found, create a new architecture from INFO, whose bfd_arch_info
3497 validity depends on the source:
3498 - executable useless
3499 - rs6000_host_arch() good
3501 - "set arch" trust blindly
3502 - GDB startup useless but harmless */
3504 tdep = XCALLOC (1, struct gdbarch_tdep);
3505 tdep->wordsize = wordsize;
3506 tdep->soft_float = soft_float;
3507 tdep->vector_abi = vector_abi;
3509 gdbarch = gdbarch_alloc (&info, tdep);
3511 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3512 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3513 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3514 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3515 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3516 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3517 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3518 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3520 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3521 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
3522 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
3523 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3524 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3525 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3526 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3527 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3529 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3530 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3531 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3532 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
3533 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3535 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3536 GDB traditionally called it "ps", though, so let GDB add an
3538 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3541 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3543 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3545 /* Set lr_frame_offset. */
3547 tdep->lr_frame_offset = 16;
3549 tdep->lr_frame_offset = 4;
3551 if (have_spe || have_dfp || have_vsx)
3553 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
3554 set_gdbarch_pseudo_register_write (gdbarch, rs6000_pseudo_register_write);
3557 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3559 /* Select instruction printer. */
3560 if (arch == bfd_arch_rs6000)
3561 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3563 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3565 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
3568 num_pseudoregs += 32;
3570 num_pseudoregs += 16;
3572 /* Include both VSX and Extended FP registers. */
3573 num_pseudoregs += 96;
3575 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
3577 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3578 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3579 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3580 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3581 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3582 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3583 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3584 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3585 set_gdbarch_char_signed (gdbarch, 0);
3587 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3590 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3592 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3593 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3594 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3596 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3597 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3600 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3601 else if (wordsize == 8)
3602 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3604 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3605 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3606 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
3608 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3609 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3611 /* The value of symbols of type N_SO and N_FUN maybe null when
3613 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
3615 /* Handles single stepping of atomic sequences. */
3616 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
3618 /* Not sure on this. FIXMEmgo */
3619 set_gdbarch_frame_args_skip (gdbarch, 8);
3621 /* Helpers for function argument information. */
3622 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3625 set_gdbarch_in_solib_return_trampoline
3626 (gdbarch, rs6000_in_solib_return_trampoline);
3627 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3629 /* Hook in the DWARF CFI frame unwinder. */
3630 dwarf2_append_unwinders (gdbarch);
3631 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3633 /* Frame handling. */
3634 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
3636 /* Hook in ABI-specific overrides, if they have been registered. */
3637 info.target_desc = tdesc;
3638 info.tdep_info = (void *) tdesc_data;
3639 gdbarch_init_osabi (info, gdbarch);
3643 case GDB_OSABI_LINUX:
3644 case GDB_OSABI_NETBSD_AOUT:
3645 case GDB_OSABI_NETBSD_ELF:
3646 case GDB_OSABI_UNKNOWN:
3647 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3648 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3649 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
3650 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3653 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3655 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3656 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
3657 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
3658 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3661 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
3662 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3663 rs6000_pseudo_register_reggroup_p);
3664 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3666 /* Override the normal target description method to make the SPE upper
3667 halves anonymous. */
3668 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3670 /* Choose register numbers for all supported pseudo-registers. */
3671 tdep->ppc_ev0_regnum = -1;
3672 tdep->ppc_dl0_regnum = -1;
3673 tdep->ppc_vsr0_regnum = -1;
3674 tdep->ppc_efpr0_regnum = -1;
3676 cur_reg = gdbarch_num_regs (gdbarch);
3680 tdep->ppc_ev0_regnum = cur_reg;
3685 tdep->ppc_dl0_regnum = cur_reg;
3690 tdep->ppc_vsr0_regnum = cur_reg;
3692 tdep->ppc_efpr0_regnum = cur_reg;
3696 gdb_assert (gdbarch_num_regs (gdbarch)
3697 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
3699 /* Setup displaced stepping. */
3700 set_gdbarch_displaced_step_copy_insn (gdbarch,
3701 simple_displaced_step_copy_insn);
3702 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
3703 set_gdbarch_displaced_step_free_closure (gdbarch,
3704 simple_displaced_step_free_closure);
3705 set_gdbarch_displaced_step_location (gdbarch,
3706 displaced_step_at_entry_point);
3708 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
3714 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3716 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3721 /* FIXME: Dump gdbarch_tdep. */
3724 /* PowerPC-specific commands. */
3727 set_powerpc_command (char *args, int from_tty)
3729 printf_unfiltered (_("\
3730 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
3731 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
3735 show_powerpc_command (char *args, int from_tty)
3737 cmd_show_list (showpowerpccmdlist, from_tty, "");
3741 powerpc_set_soft_float (char *args, int from_tty,
3742 struct cmd_list_element *c)
3744 struct gdbarch_info info;
3746 /* Update the architecture. */
3747 gdbarch_info_init (&info);
3748 if (!gdbarch_update_p (info))
3749 internal_error (__FILE__, __LINE__, "could not update architecture");
3753 powerpc_set_vector_abi (char *args, int from_tty,
3754 struct cmd_list_element *c)
3756 struct gdbarch_info info;
3757 enum powerpc_vector_abi vector_abi;
3759 for (vector_abi = POWERPC_VEC_AUTO;
3760 vector_abi != POWERPC_VEC_LAST;
3762 if (strcmp (powerpc_vector_abi_string,
3763 powerpc_vector_strings[vector_abi]) == 0)
3765 powerpc_vector_abi_global = vector_abi;
3769 if (vector_abi == POWERPC_VEC_LAST)
3770 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
3771 powerpc_vector_abi_string);
3773 /* Update the architecture. */
3774 gdbarch_info_init (&info);
3775 if (!gdbarch_update_p (info))
3776 internal_error (__FILE__, __LINE__, "could not update architecture");
3779 /* Initialization code. */
3781 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3784 _initialize_rs6000_tdep (void)
3786 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3787 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
3789 /* Initialize the standard target descriptions. */
3790 initialize_tdesc_powerpc_32 ();
3791 initialize_tdesc_powerpc_altivec32 ();
3792 initialize_tdesc_powerpc_vsx32 ();
3793 initialize_tdesc_powerpc_403 ();
3794 initialize_tdesc_powerpc_403gc ();
3795 initialize_tdesc_powerpc_505 ();
3796 initialize_tdesc_powerpc_601 ();
3797 initialize_tdesc_powerpc_602 ();
3798 initialize_tdesc_powerpc_603 ();
3799 initialize_tdesc_powerpc_604 ();
3800 initialize_tdesc_powerpc_64 ();
3801 initialize_tdesc_powerpc_altivec64 ();
3802 initialize_tdesc_powerpc_vsx64 ();
3803 initialize_tdesc_powerpc_7400 ();
3804 initialize_tdesc_powerpc_750 ();
3805 initialize_tdesc_powerpc_860 ();
3806 initialize_tdesc_powerpc_e500 ();
3807 initialize_tdesc_rs6000 ();
3809 /* Add root prefix command for all "set powerpc"/"show powerpc"
3811 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
3812 _("Various PowerPC-specific commands."),
3813 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
3815 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
3816 _("Various PowerPC-specific commands."),
3817 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
3819 /* Add a command to allow the user to force the ABI. */
3820 add_setshow_auto_boolean_cmd ("soft-float", class_support,
3821 &powerpc_soft_float_global,
3822 _("Set whether to use a soft-float ABI."),
3823 _("Show whether to use a soft-float ABI."),
3825 powerpc_set_soft_float, NULL,
3826 &setpowerpccmdlist, &showpowerpccmdlist);
3828 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
3829 &powerpc_vector_abi_string,
3830 _("Set the vector ABI."),
3831 _("Show the vector ABI."),
3832 NULL, powerpc_set_vector_abi, NULL,
3833 &setpowerpccmdlist, &showpowerpccmdlist);