1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
54 #include "solib-svr4.h"
57 #include "gdb_assert.h"
60 #include "trad-frame.h"
61 #include "frame-unwind.h"
62 #include "frame-base.h"
64 #include "rs6000-tdep.h"
66 #include "features/rs6000/powerpc-32.c"
67 #include "features/rs6000/powerpc-403.c"
68 #include "features/rs6000/powerpc-403gc.c"
69 #include "features/rs6000/powerpc-505.c"
70 #include "features/rs6000/powerpc-601.c"
71 #include "features/rs6000/powerpc-602.c"
72 #include "features/rs6000/powerpc-603.c"
73 #include "features/rs6000/powerpc-604.c"
74 #include "features/rs6000/powerpc-64.c"
75 #include "features/rs6000/powerpc-7400.c"
76 #include "features/rs6000/powerpc-750.c"
77 #include "features/rs6000/powerpc-860.c"
78 #include "features/rs6000/powerpc-e500.c"
79 #include "features/rs6000/rs6000.c"
81 /* Determine if regnum is an SPE pseudo-register. */
82 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
83 && (regnum) >= (tdep)->ppc_ev0_regnum \
84 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
86 /* The list of available "set powerpc ..." and "show powerpc ..."
88 static struct cmd_list_element *setpowerpccmdlist = NULL;
89 static struct cmd_list_element *showpowerpccmdlist = NULL;
91 static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
93 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
94 static const char *powerpc_vector_strings[] =
103 /* A variable that can be configured by the user. */
104 static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
105 static const char *powerpc_vector_abi_string = "auto";
107 /* If the kernel has to deliver a signal, it pushes a sigcontext
108 structure on the stack and then calls the signal handler, passing
109 the address of the sigcontext in an argument register. Usually
110 the signal handler doesn't save this register, so we have to
111 access the sigcontext structure via an offset from the signal handler
113 The following constants were determined by experimentation on AIX 3.2. */
114 #define SIG_FRAME_PC_OFFSET 96
115 #define SIG_FRAME_LR_OFFSET 108
116 #define SIG_FRAME_FP_OFFSET 284
118 /* To be used by skip_prologue. */
120 struct rs6000_framedata
122 int offset; /* total size of frame --- the distance
123 by which we decrement sp to allocate
125 int saved_gpr; /* smallest # of saved gpr */
126 int saved_fpr; /* smallest # of saved fpr */
127 int saved_vr; /* smallest # of saved vr */
128 int saved_ev; /* smallest # of saved ev */
129 int alloca_reg; /* alloca register number (frame ptr) */
130 char frameless; /* true if frameless functions. */
131 char nosavedpc; /* true if pc not saved. */
132 int gpr_offset; /* offset of saved gprs from prev sp */
133 int fpr_offset; /* offset of saved fprs from prev sp */
134 int vr_offset; /* offset of saved vrs from prev sp */
135 int ev_offset; /* offset of saved evs from prev sp */
136 int lr_offset; /* offset of saved lr */
137 int cr_offset; /* offset of saved cr */
138 int vrsave_offset; /* offset of saved vrsave register */
141 /* Description of a single register. */
145 char *name; /* name of register */
146 unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */
147 unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */
148 unsigned char fpr; /* whether register is floating-point */
149 unsigned char pseudo; /* whether register is pseudo */
150 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
151 This is an ISA SPR number, not a GDB
155 /* Hook for determining the TOC address when calling functions in the
156 inferior under AIX. The initialization code in rs6000-nat.c sets
157 this hook to point to find_toc_address. */
159 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
161 /* Static function prototypes */
163 static CORE_ADDR branch_dest (struct frame_info *frame, int opcode,
164 int instr, CORE_ADDR pc, CORE_ADDR safety);
165 static CORE_ADDR skip_prologue (struct gdbarch *, CORE_ADDR, CORE_ADDR,
166 struct rs6000_framedata *);
168 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
170 altivec_register_p (struct gdbarch *gdbarch, int regno)
172 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
173 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
176 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
180 /* Return true if REGNO is an SPE register, false otherwise. */
182 spe_register_p (struct gdbarch *gdbarch, int regno)
184 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
186 /* Is it a reference to EV0 -- EV31, and do we have those? */
187 if (IS_SPE_PSEUDOREG (tdep, regno))
190 /* Is it a reference to one of the raw upper GPR halves? */
191 if (tdep->ppc_ev0_upper_regnum >= 0
192 && tdep->ppc_ev0_upper_regnum <= regno
193 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
196 /* Is it a reference to the 64-bit accumulator, and do we have that? */
197 if (tdep->ppc_acc_regnum >= 0
198 && tdep->ppc_acc_regnum == regno)
201 /* Is it a reference to the SPE floating-point status and control register,
202 and do we have that? */
203 if (tdep->ppc_spefscr_regnum >= 0
204 && tdep->ppc_spefscr_regnum == regno)
211 /* Return non-zero if the architecture described by GDBARCH has
212 floating-point registers (f0 --- f31 and fpscr). */
214 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
216 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
218 return (tdep->ppc_fp0_regnum >= 0
219 && tdep->ppc_fpscr_regnum >= 0);
222 /* Return non-zero if the architecture described by GDBARCH has
223 Altivec registers (vr0 --- vr31, vrsave and vscr). */
225 ppc_altivec_support_p (struct gdbarch *gdbarch)
227 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
229 return (tdep->ppc_vr0_regnum >= 0
230 && tdep->ppc_vrsave_regnum >= 0);
233 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
236 This is a helper function for init_sim_regno_table, constructing
237 the table mapping GDB register numbers to sim register numbers; we
238 initialize every element in that table to -1 before we start
241 set_sim_regno (int *table, int gdb_regno, int sim_regno)
243 /* Make sure we don't try to assign any given GDB register a sim
244 register number more than once. */
245 gdb_assert (table[gdb_regno] == -1);
246 table[gdb_regno] = sim_regno;
250 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
251 numbers to simulator register numbers, based on the values placed
252 in the ARCH->tdep->ppc_foo_regnum members. */
254 init_sim_regno_table (struct gdbarch *arch)
256 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
257 int total_regs = gdbarch_num_regs (arch);
258 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
260 static const char *const segment_regs[] = {
261 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
262 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
265 /* Presume that all registers not explicitly mentioned below are
266 unavailable from the sim. */
267 for (i = 0; i < total_regs; i++)
270 /* General-purpose registers. */
271 for (i = 0; i < ppc_num_gprs; i++)
272 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
274 /* Floating-point registers. */
275 if (tdep->ppc_fp0_regnum >= 0)
276 for (i = 0; i < ppc_num_fprs; i++)
277 set_sim_regno (sim_regno,
278 tdep->ppc_fp0_regnum + i,
279 sim_ppc_f0_regnum + i);
280 if (tdep->ppc_fpscr_regnum >= 0)
281 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
283 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
284 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
285 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
287 /* Segment registers. */
288 for (i = 0; i < ppc_num_srs; i++)
292 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
294 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
297 /* Altivec registers. */
298 if (tdep->ppc_vr0_regnum >= 0)
300 for (i = 0; i < ppc_num_vrs; i++)
301 set_sim_regno (sim_regno,
302 tdep->ppc_vr0_regnum + i,
303 sim_ppc_vr0_regnum + i);
305 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
306 we can treat this more like the other cases. */
307 set_sim_regno (sim_regno,
308 tdep->ppc_vr0_regnum + ppc_num_vrs,
309 sim_ppc_vscr_regnum);
311 /* vsave is a special-purpose register, so the code below handles it. */
313 /* SPE APU (E500) registers. */
314 if (tdep->ppc_ev0_upper_regnum >= 0)
315 for (i = 0; i < ppc_num_gprs; i++)
316 set_sim_regno (sim_regno,
317 tdep->ppc_ev0_upper_regnum + i,
318 sim_ppc_rh0_regnum + i);
319 if (tdep->ppc_acc_regnum >= 0)
320 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
321 /* spefscr is a special-purpose register, so the code below handles it. */
324 /* Now handle all special-purpose registers. Verify that they
325 haven't mistakenly been assigned numbers by any of the above
327 for (i = 0; i < sim_ppc_num_sprs; i++)
329 const char *spr_name = sim_spr_register_name (i);
332 if (spr_name != NULL)
333 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
336 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
340 /* Drop the initialized array into place. */
341 tdep->sim_regno = sim_regno;
345 /* Given a GDB register number REG, return the corresponding SIM
348 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
350 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
353 if (tdep->sim_regno == NULL)
354 init_sim_regno_table (gdbarch);
357 && reg <= gdbarch_num_regs (gdbarch)
358 + gdbarch_num_pseudo_regs (gdbarch));
359 sim_regno = tdep->sim_regno[reg];
364 return LEGACY_SIM_REGNO_IGNORE;
369 /* Register set support functions. */
371 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
372 Write the register to REGCACHE. */
375 ppc_supply_reg (struct regcache *regcache, int regnum,
376 const gdb_byte *regs, size_t offset, int regsize)
378 if (regnum != -1 && offset != -1)
382 struct gdbarch *gdbarch = get_regcache_arch (regcache);
383 int gdb_regsize = register_size (gdbarch, regnum);
384 if (gdb_regsize < regsize
385 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
386 offset += regsize - gdb_regsize;
388 regcache_raw_supply (regcache, regnum, regs + offset);
392 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
393 in a field REGSIZE wide. Zero pad as necessary. */
396 ppc_collect_reg (const struct regcache *regcache, int regnum,
397 gdb_byte *regs, size_t offset, int regsize)
399 if (regnum != -1 && offset != -1)
403 struct gdbarch *gdbarch = get_regcache_arch (regcache);
404 int gdb_regsize = register_size (gdbarch, regnum);
405 if (gdb_regsize < regsize)
407 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
409 memset (regs + offset, 0, regsize - gdb_regsize);
410 offset += regsize - gdb_regsize;
413 memset (regs + offset + regsize - gdb_regsize, 0,
414 regsize - gdb_regsize);
417 regcache_raw_collect (regcache, regnum, regs + offset);
422 ppc_greg_offset (struct gdbarch *gdbarch,
423 struct gdbarch_tdep *tdep,
424 const struct ppc_reg_offsets *offsets,
428 *regsize = offsets->gpr_size;
429 if (regnum >= tdep->ppc_gp0_regnum
430 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
431 return (offsets->r0_offset
432 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
434 if (regnum == gdbarch_pc_regnum (gdbarch))
435 return offsets->pc_offset;
437 if (regnum == tdep->ppc_ps_regnum)
438 return offsets->ps_offset;
440 if (regnum == tdep->ppc_lr_regnum)
441 return offsets->lr_offset;
443 if (regnum == tdep->ppc_ctr_regnum)
444 return offsets->ctr_offset;
446 *regsize = offsets->xr_size;
447 if (regnum == tdep->ppc_cr_regnum)
448 return offsets->cr_offset;
450 if (regnum == tdep->ppc_xer_regnum)
451 return offsets->xer_offset;
453 if (regnum == tdep->ppc_mq_regnum)
454 return offsets->mq_offset;
460 ppc_fpreg_offset (struct gdbarch_tdep *tdep,
461 const struct ppc_reg_offsets *offsets,
464 if (regnum >= tdep->ppc_fp0_regnum
465 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
466 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
468 if (regnum == tdep->ppc_fpscr_regnum)
469 return offsets->fpscr_offset;
475 ppc_vrreg_offset (struct gdbarch_tdep *tdep,
476 const struct ppc_reg_offsets *offsets,
479 if (regnum >= tdep->ppc_vr0_regnum
480 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
481 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
483 if (regnum == tdep->ppc_vrsave_regnum - 1)
484 return offsets->vscr_offset;
486 if (regnum == tdep->ppc_vrsave_regnum)
487 return offsets->vrsave_offset;
492 /* Supply register REGNUM in the general-purpose register set REGSET
493 from the buffer specified by GREGS and LEN to register cache
494 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
497 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
498 int regnum, const void *gregs, size_t len)
500 struct gdbarch *gdbarch = get_regcache_arch (regcache);
501 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
502 const struct ppc_reg_offsets *offsets = regset->descr;
509 int gpr_size = offsets->gpr_size;
511 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
512 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
513 i++, offset += gpr_size)
514 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
516 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
517 gregs, offsets->pc_offset, gpr_size);
518 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
519 gregs, offsets->ps_offset, gpr_size);
520 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
521 gregs, offsets->lr_offset, gpr_size);
522 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
523 gregs, offsets->ctr_offset, gpr_size);
524 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
525 gregs, offsets->cr_offset, offsets->xr_size);
526 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
527 gregs, offsets->xer_offset, offsets->xr_size);
528 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
529 gregs, offsets->mq_offset, offsets->xr_size);
533 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
534 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
537 /* Supply register REGNUM in the floating-point register set REGSET
538 from the buffer specified by FPREGS and LEN to register cache
539 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
542 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
543 int regnum, const void *fpregs, size_t len)
545 struct gdbarch *gdbarch = get_regcache_arch (regcache);
546 struct gdbarch_tdep *tdep;
547 const struct ppc_reg_offsets *offsets;
550 if (!ppc_floating_point_unit_p (gdbarch))
553 tdep = gdbarch_tdep (gdbarch);
554 offsets = regset->descr;
559 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
560 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
562 ppc_supply_reg (regcache, i, fpregs, offset, 8);
564 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
565 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
569 offset = ppc_fpreg_offset (tdep, offsets, regnum);
570 ppc_supply_reg (regcache, regnum, fpregs, offset,
571 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
574 /* Supply register REGNUM in the Altivec register set REGSET
575 from the buffer specified by VRREGS and LEN to register cache
576 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
579 ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
580 int regnum, const void *vrregs, size_t len)
582 struct gdbarch *gdbarch = get_regcache_arch (regcache);
583 struct gdbarch_tdep *tdep;
584 const struct ppc_reg_offsets *offsets;
587 if (!ppc_altivec_support_p (gdbarch))
590 tdep = gdbarch_tdep (gdbarch);
591 offsets = regset->descr;
596 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
597 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
599 ppc_supply_reg (regcache, i, vrregs, offset, 16);
601 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
602 vrregs, offsets->vscr_offset, 4);
604 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
605 vrregs, offsets->vrsave_offset, 4);
609 offset = ppc_vrreg_offset (tdep, offsets, regnum);
610 if (regnum != tdep->ppc_vrsave_regnum
611 && regnum != tdep->ppc_vrsave_regnum - 1)
612 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
614 ppc_supply_reg (regcache, regnum,
618 /* Collect register REGNUM in the general-purpose register set
619 REGSET from register cache REGCACHE into the buffer specified by
620 GREGS and LEN. If REGNUM is -1, do this for all registers in
624 ppc_collect_gregset (const struct regset *regset,
625 const struct regcache *regcache,
626 int regnum, void *gregs, size_t len)
628 struct gdbarch *gdbarch = get_regcache_arch (regcache);
629 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
630 const struct ppc_reg_offsets *offsets = regset->descr;
637 int gpr_size = offsets->gpr_size;
639 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
640 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
641 i++, offset += gpr_size)
642 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
644 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
645 gregs, offsets->pc_offset, gpr_size);
646 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
647 gregs, offsets->ps_offset, gpr_size);
648 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
649 gregs, offsets->lr_offset, gpr_size);
650 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
651 gregs, offsets->ctr_offset, gpr_size);
652 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
653 gregs, offsets->cr_offset, offsets->xr_size);
654 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
655 gregs, offsets->xer_offset, offsets->xr_size);
656 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
657 gregs, offsets->mq_offset, offsets->xr_size);
661 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
662 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
665 /* Collect register REGNUM in the floating-point register set
666 REGSET from register cache REGCACHE into the buffer specified by
667 FPREGS and LEN. If REGNUM is -1, do this for all registers in
671 ppc_collect_fpregset (const struct regset *regset,
672 const struct regcache *regcache,
673 int regnum, void *fpregs, size_t len)
675 struct gdbarch *gdbarch = get_regcache_arch (regcache);
676 struct gdbarch_tdep *tdep;
677 const struct ppc_reg_offsets *offsets;
680 if (!ppc_floating_point_unit_p (gdbarch))
683 tdep = gdbarch_tdep (gdbarch);
684 offsets = regset->descr;
689 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
690 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
692 ppc_collect_reg (regcache, i, fpregs, offset, 8);
694 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
695 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
699 offset = ppc_fpreg_offset (tdep, offsets, regnum);
700 ppc_collect_reg (regcache, regnum, fpregs, offset,
701 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
704 /* Collect register REGNUM in the Altivec register set
705 REGSET from register cache REGCACHE into the buffer specified by
706 VRREGS and LEN. If REGNUM is -1, do this for all registers in
710 ppc_collect_vrregset (const struct regset *regset,
711 const struct regcache *regcache,
712 int regnum, void *vrregs, size_t len)
714 struct gdbarch *gdbarch = get_regcache_arch (regcache);
715 struct gdbarch_tdep *tdep;
716 const struct ppc_reg_offsets *offsets;
719 if (!ppc_altivec_support_p (gdbarch))
722 tdep = gdbarch_tdep (gdbarch);
723 offsets = regset->descr;
728 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
729 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
731 ppc_collect_reg (regcache, i, vrregs, offset, 16);
733 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
734 vrregs, offsets->vscr_offset, 4);
736 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
737 vrregs, offsets->vrsave_offset, 4);
741 offset = ppc_vrreg_offset (tdep, offsets, regnum);
742 if (regnum != tdep->ppc_vrsave_regnum
743 && regnum != tdep->ppc_vrsave_regnum - 1)
744 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
746 ppc_collect_reg (regcache, regnum,
751 /* Read a LEN-byte address from debugged memory address MEMADDR. */
754 read_memory_addr (CORE_ADDR memaddr, int len)
756 return read_memory_unsigned_integer (memaddr, len);
760 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
762 struct rs6000_framedata frame;
763 CORE_ADDR limit_pc, func_addr;
765 /* See if we can determine the end of the prologue via the symbol table.
766 If so, then return either PC, or the PC after the prologue, whichever
768 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
770 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
771 if (post_prologue_pc != 0)
772 return max (pc, post_prologue_pc);
775 /* Can't determine prologue from the symbol table, need to examine
778 /* Find an upper limit on the function prologue using the debug
779 information. If the debug information could not be used to provide
780 that bound, then use an arbitrary large number as the upper bound. */
781 limit_pc = skip_prologue_using_sal (pc);
783 limit_pc = pc + 100; /* Magic. */
785 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
790 insn_changes_sp_or_jumps (unsigned long insn)
792 int opcode = (insn >> 26) & 0x03f;
793 int sd = (insn >> 21) & 0x01f;
794 int a = (insn >> 16) & 0x01f;
795 int subcode = (insn >> 1) & 0x3ff;
797 /* Changes the stack pointer. */
799 /* NOTE: There are many ways to change the value of a given register.
800 The ways below are those used when the register is R1, the SP,
801 in a funtion's epilogue. */
803 if (opcode == 31 && subcode == 444 && a == 1)
804 return 1; /* mr R1,Rn */
805 if (opcode == 14 && sd == 1)
806 return 1; /* addi R1,Rn,simm */
807 if (opcode == 58 && sd == 1)
808 return 1; /* ld R1,ds(Rn) */
810 /* Transfers control. */
816 if (opcode == 19 && subcode == 16)
818 if (opcode == 19 && subcode == 528)
819 return 1; /* bcctr */
824 /* Return true if we are in the function's epilogue, i.e. after the
825 instruction that destroyed the function's stack frame.
827 1) scan forward from the point of execution:
828 a) If you find an instruction that modifies the stack pointer
829 or transfers control (except a return), execution is not in
831 b) Stop scanning if you find a return instruction or reach the
832 end of the function or reach the hard limit for the size of
834 2) scan backward from the point of execution:
835 a) If you find an instruction that modifies the stack pointer,
836 execution *is* in an epilogue, return.
837 b) Stop scanning if you reach an instruction that transfers
838 control or the beginning of the function or reach the hard
839 limit for the size of an epilogue. */
842 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
844 bfd_byte insn_buf[PPC_INSN_SIZE];
845 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
847 struct frame_info *curfrm;
849 /* Find the search limits based on function boundaries and hard limit. */
851 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
854 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
855 if (epilogue_start < func_start) epilogue_start = func_start;
857 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
858 if (epilogue_end > func_end) epilogue_end = func_end;
860 curfrm = get_current_frame ();
862 /* Scan forward until next 'blr'. */
864 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
866 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
868 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
869 if (insn == 0x4e800020)
871 if (insn_changes_sp_or_jumps (insn))
875 /* Scan backward until adjustment to stack pointer (R1). */
877 for (scan_pc = pc - PPC_INSN_SIZE;
878 scan_pc >= epilogue_start;
879 scan_pc -= PPC_INSN_SIZE)
881 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
883 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
884 if (insn_changes_sp_or_jumps (insn))
891 /* Get the ith function argument for the current function. */
893 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
896 return get_frame_register_unsigned (frame, 3 + argi);
899 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
902 branch_dest (struct frame_info *frame, int opcode, int instr,
903 CORE_ADDR pc, CORE_ADDR safety)
905 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
911 absolute = (int) ((instr >> 1) & 1);
916 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
920 dest = pc + immediate;
924 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
928 dest = pc + immediate;
932 ext_op = (instr >> 1) & 0x3ff;
934 if (ext_op == 16) /* br conditional register */
936 dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3;
938 /* If we are about to return from a signal handler, dest is
939 something like 0x3c90. The current frame is a signal handler
940 caller frame, upon completion of the sigreturn system call
941 execution will return to the saved PC in the frame. */
942 if (dest < tdep->text_segment_base)
943 dest = read_memory_addr (get_frame_base (frame) + SIG_FRAME_PC_OFFSET,
947 else if (ext_op == 528) /* br cond to count reg */
949 dest = get_frame_register_unsigned (frame, tdep->ppc_ctr_regnum) & ~3;
951 /* If we are about to execute a system call, dest is something
952 like 0x22fc or 0x3b00. Upon completion the system call
953 will return to the address in the link register. */
954 if (dest < tdep->text_segment_base)
955 dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3;
964 return (dest < tdep->text_segment_base) ? safety : dest;
968 /* Sequence of bytes for breakpoint instruction. */
970 const static unsigned char *
971 rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
974 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
975 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
977 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
978 return big_breakpoint;
980 return little_breakpoint;
984 /* Instruction masks used during single-stepping of atomic sequences. */
985 #define LWARX_MASK 0xfc0007fe
986 #define LWARX_INSTRUCTION 0x7c000028
987 #define LDARX_INSTRUCTION 0x7c0000A8
988 #define STWCX_MASK 0xfc0007ff
989 #define STWCX_INSTRUCTION 0x7c00012d
990 #define STDCX_INSTRUCTION 0x7c0001ad
991 #define BC_MASK 0xfc000000
992 #define BC_INSTRUCTION 0x40000000
994 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
995 instruction and ending with a STWCX/STDCX instruction. If such a sequence
996 is found, attempt to step through it. A breakpoint is placed at the end of
1000 deal_with_atomic_sequence (struct frame_info *frame)
1002 CORE_ADDR pc = get_frame_pc (frame);
1003 CORE_ADDR breaks[2] = {-1, -1};
1005 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
1006 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
1007 int insn = read_memory_integer (loc, PPC_INSN_SIZE);
1010 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1011 const int atomic_sequence_length = 16; /* Instruction sequence length. */
1012 int opcode; /* Branch instruction's OPcode. */
1013 int bc_insn_count = 0; /* Conditional branch instruction count. */
1015 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1016 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1017 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1020 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1022 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1024 loc += PPC_INSN_SIZE;
1025 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1027 /* Assume that there is at most one conditional branch in the atomic
1028 sequence. If a conditional branch is found, put a breakpoint in
1029 its destination address. */
1030 if ((insn & BC_MASK) == BC_INSTRUCTION)
1032 if (bc_insn_count >= 1)
1033 return 0; /* More than one conditional branch found, fallback
1034 to the standard single-step code. */
1036 opcode = insn >> 26;
1037 branch_bp = branch_dest (frame, opcode, insn, pc, breaks[0]);
1039 if (branch_bp != -1)
1041 breaks[1] = branch_bp;
1047 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1048 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1052 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1053 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1054 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1058 loc += PPC_INSN_SIZE;
1059 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1061 /* Insert a breakpoint right after the end of the atomic sequence. */
1064 /* Check for duplicated breakpoints. Check also for a breakpoint
1065 placed (branch instruction's destination) at the stwcx/stdcx
1066 instruction, this resets the reservation and take us back to the
1067 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1068 if (last_breakpoint && ((breaks[1] == breaks[0])
1069 || (breaks[1] == closing_insn)))
1070 last_breakpoint = 0;
1072 /* Effectively inserts the breakpoints. */
1073 for (index = 0; index <= last_breakpoint; index++)
1074 insert_single_step_breakpoint (breaks[index]);
1079 /* AIX does not support PT_STEP. Simulate it. */
1082 rs6000_software_single_step (struct frame_info *frame)
1086 const gdb_byte *breakp
1087 = rs6000_breakpoint_from_pc (get_frame_arch (frame), &dummy, &breakp_sz);
1090 CORE_ADDR breaks[2];
1093 loc = get_frame_pc (frame);
1095 insn = read_memory_integer (loc, 4);
1097 if (deal_with_atomic_sequence (frame))
1100 breaks[0] = loc + breakp_sz;
1101 opcode = insn >> 26;
1102 breaks[1] = branch_dest (frame, opcode, insn, loc, breaks[0]);
1104 /* Don't put two breakpoints on the same address. */
1105 if (breaks[1] == breaks[0])
1108 for (ii = 0; ii < 2; ++ii)
1110 /* ignore invalid breakpoint. */
1111 if (breaks[ii] == -1)
1113 insert_single_step_breakpoint (breaks[ii]);
1116 errno = 0; /* FIXME, don't ignore errors! */
1117 /* What errors? {read,write}_memory call error(). */
1122 #define SIGNED_SHORT(x) \
1123 ((sizeof (short) == 2) \
1124 ? ((int)(short)(x)) \
1125 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1127 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1129 /* Limit the number of skipped non-prologue instructions, as the examining
1130 of the prologue is expensive. */
1131 static int max_skip_non_prologue_insns = 10;
1133 /* Return nonzero if the given instruction OP can be part of the prologue
1134 of a function and saves a parameter on the stack. FRAMEP should be
1135 set if one of the previous instructions in the function has set the
1139 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1141 /* Move parameters from argument registers to temporary register. */
1142 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1144 /* Rx must be scratch register r0. */
1145 const int rx_regno = (op >> 16) & 31;
1146 /* Ry: Only r3 - r10 are used for parameter passing. */
1147 const int ry_regno = GET_SRC_REG (op);
1149 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1151 *r0_contains_arg = 1;
1158 /* Save a General Purpose Register on stack. */
1160 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1161 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1163 /* Rx: Only r3 - r10 are used for parameter passing. */
1164 const int rx_regno = GET_SRC_REG (op);
1166 return (rx_regno >= 3 && rx_regno <= 10);
1169 /* Save a General Purpose Register on stack via the Frame Pointer. */
1172 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1173 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1174 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1176 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1177 However, the compiler sometimes uses r0 to hold an argument. */
1178 const int rx_regno = GET_SRC_REG (op);
1180 return ((rx_regno >= 3 && rx_regno <= 10)
1181 || (rx_regno == 0 && *r0_contains_arg));
1184 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1186 /* Only f2 - f8 are used for parameter passing. */
1187 const int src_regno = GET_SRC_REG (op);
1189 return (src_regno >= 2 && src_regno <= 8);
1192 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1194 /* Only f2 - f8 are used for parameter passing. */
1195 const int src_regno = GET_SRC_REG (op);
1197 return (src_regno >= 2 && src_regno <= 8);
1200 /* Not an insn that saves a parameter on stack. */
1204 /* Assuming that INSN is a "bl" instruction located at PC, return
1205 nonzero if the destination of the branch is a "blrl" instruction.
1207 This sequence is sometimes found in certain function prologues.
1208 It allows the function to load the LR register with a value that
1209 they can use to access PIC data using PC-relative offsets. */
1212 bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
1219 absolute = (int) ((insn >> 1) & 1);
1220 immediate = ((insn & ~3) << 6) >> 6;
1224 dest = pc + immediate;
1226 dest_insn = read_memory_integer (dest, 4);
1227 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1233 /* return pc value after skipping a function prologue and also return
1234 information about a function frame.
1236 in struct rs6000_framedata fdata:
1237 - frameless is TRUE, if function does not have a frame.
1238 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1239 - offset is the initial size of this stack frame --- the amount by
1240 which we decrement the sp to allocate the frame.
1241 - saved_gpr is the number of the first saved gpr.
1242 - saved_fpr is the number of the first saved fpr.
1243 - saved_vr is the number of the first saved vr.
1244 - saved_ev is the number of the first saved ev.
1245 - alloca_reg is the number of the register used for alloca() handling.
1247 - gpr_offset is the offset of the first saved gpr from the previous frame.
1248 - fpr_offset is the offset of the first saved fpr from the previous frame.
1249 - vr_offset is the offset of the first saved vr from the previous frame.
1250 - ev_offset is the offset of the first saved ev from the previous frame.
1251 - lr_offset is the offset of the saved lr
1252 - cr_offset is the offset of the saved cr
1253 - vrsave_offset is the offset of the saved vrsave register
1257 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1258 struct rs6000_framedata *fdata)
1260 CORE_ADDR orig_pc = pc;
1261 CORE_ADDR last_prologue_pc = pc;
1262 CORE_ADDR li_found_pc = 0;
1266 long vr_saved_offset = 0;
1272 int vrsave_reg = -1;
1275 int minimal_toc_loaded = 0;
1276 int prev_insn_was_prologue_insn = 1;
1277 int num_skip_non_prologue_insns = 0;
1278 int r0_contains_arg = 0;
1279 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1280 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1282 memset (fdata, 0, sizeof (struct rs6000_framedata));
1283 fdata->saved_gpr = -1;
1284 fdata->saved_fpr = -1;
1285 fdata->saved_vr = -1;
1286 fdata->saved_ev = -1;
1287 fdata->alloca_reg = -1;
1288 fdata->frameless = 1;
1289 fdata->nosavedpc = 1;
1293 /* Sometimes it isn't clear if an instruction is a prologue
1294 instruction or not. When we encounter one of these ambiguous
1295 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1296 Otherwise, we'll assume that it really is a prologue instruction. */
1297 if (prev_insn_was_prologue_insn)
1298 last_prologue_pc = pc;
1300 /* Stop scanning if we've hit the limit. */
1304 prev_insn_was_prologue_insn = 1;
1306 /* Fetch the instruction and convert it to an integer. */
1307 if (target_read_memory (pc, buf, 4))
1309 op = extract_unsigned_integer (buf, 4);
1311 if ((op & 0xfc1fffff) == 0x7c0802a6)
1313 /* Since shared library / PIC code, which needs to get its
1314 address at runtime, can appear to save more than one link
1328 remember just the first one, but skip over additional
1331 lr_reg = (op & 0x03e00000);
1333 r0_contains_arg = 0;
1336 else if ((op & 0xfc1fffff) == 0x7c000026)
1338 cr_reg = (op & 0x03e00000);
1340 r0_contains_arg = 0;
1344 else if ((op & 0xfc1f0000) == 0xd8010000)
1345 { /* stfd Rx,NUM(r1) */
1346 reg = GET_SRC_REG (op);
1347 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1349 fdata->saved_fpr = reg;
1350 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1355 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1356 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1357 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1358 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1361 reg = GET_SRC_REG (op);
1362 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1364 fdata->saved_gpr = reg;
1365 if ((op & 0xfc1f0003) == 0xf8010000)
1367 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1372 else if ((op & 0xffff0000) == 0x60000000)
1375 /* Allow nops in the prologue, but do not consider them to
1376 be part of the prologue unless followed by other prologue
1378 prev_insn_was_prologue_insn = 0;
1382 else if ((op & 0xffff0000) == 0x3c000000)
1383 { /* addis 0,0,NUM, used
1384 for >= 32k frames */
1385 fdata->offset = (op & 0x0000ffff) << 16;
1386 fdata->frameless = 0;
1387 r0_contains_arg = 0;
1391 else if ((op & 0xffff0000) == 0x60000000)
1392 { /* ori 0,0,NUM, 2nd ha
1393 lf of >= 32k frames */
1394 fdata->offset |= (op & 0x0000ffff);
1395 fdata->frameless = 0;
1396 r0_contains_arg = 0;
1400 else if (lr_reg >= 0 &&
1401 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1402 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1403 /* stw Rx, NUM(r1) */
1404 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1405 /* stwu Rx, NUM(r1) */
1406 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1407 { /* where Rx == lr */
1408 fdata->lr_offset = offset;
1409 fdata->nosavedpc = 0;
1410 /* Invalidate lr_reg, but don't set it to -1.
1411 That would mean that it had never been set. */
1413 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1414 (op & 0xfc000000) == 0x90000000) /* stw */
1416 /* Does not update r1, so add displacement to lr_offset. */
1417 fdata->lr_offset += SIGNED_SHORT (op);
1422 else if (cr_reg >= 0 &&
1423 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1424 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1425 /* stw Rx, NUM(r1) */
1426 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1427 /* stwu Rx, NUM(r1) */
1428 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1429 { /* where Rx == cr */
1430 fdata->cr_offset = offset;
1431 /* Invalidate cr_reg, but don't set it to -1.
1432 That would mean that it had never been set. */
1434 if ((op & 0xfc000003) == 0xf8000000 ||
1435 (op & 0xfc000000) == 0x90000000)
1437 /* Does not update r1, so add displacement to cr_offset. */
1438 fdata->cr_offset += SIGNED_SHORT (op);
1443 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1445 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1446 prediction bits. If the LR has already been saved, we can
1450 else if (op == 0x48000005)
1456 else if (op == 0x48000004)
1461 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1462 in V.4 -mminimal-toc */
1463 (op & 0xffff0000) == 0x3bde0000)
1464 { /* addi 30,30,foo@l */
1468 else if ((op & 0xfc000001) == 0x48000001)
1472 fdata->frameless = 0;
1474 /* If the return address has already been saved, we can skip
1475 calls to blrl (for PIC). */
1476 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
1479 /* Don't skip over the subroutine call if it is not within
1480 the first three instructions of the prologue and either
1481 we have no line table information or the line info tells
1482 us that the subroutine call is not part of the line
1483 associated with the prologue. */
1484 if ((pc - orig_pc) > 8)
1486 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1487 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1489 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1493 op = read_memory_integer (pc + 4, 4);
1495 /* At this point, make sure this is not a trampoline
1496 function (a function that simply calls another functions,
1497 and nothing else). If the next is not a nop, this branch
1498 was part of the function prologue. */
1500 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1501 break; /* don't skip over
1506 /* update stack pointer */
1507 else if ((op & 0xfc1f0000) == 0x94010000)
1508 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1509 fdata->frameless = 0;
1510 fdata->offset = SIGNED_SHORT (op);
1511 offset = fdata->offset;
1514 else if ((op & 0xfc1f016a) == 0x7c01016e)
1515 { /* stwux rX,r1,rY */
1516 /* no way to figure out what r1 is going to be */
1517 fdata->frameless = 0;
1518 offset = fdata->offset;
1521 else if ((op & 0xfc1f0003) == 0xf8010001)
1522 { /* stdu rX,NUM(r1) */
1523 fdata->frameless = 0;
1524 fdata->offset = SIGNED_SHORT (op & ~3UL);
1525 offset = fdata->offset;
1528 else if ((op & 0xfc1f016a) == 0x7c01016a)
1529 { /* stdux rX,r1,rY */
1530 /* no way to figure out what r1 is going to be */
1531 fdata->frameless = 0;
1532 offset = fdata->offset;
1535 else if ((op & 0xffff0000) == 0x38210000)
1536 { /* addi r1,r1,SIMM */
1537 fdata->frameless = 0;
1538 fdata->offset += SIGNED_SHORT (op);
1539 offset = fdata->offset;
1542 /* Load up minimal toc pointer. Do not treat an epilogue restore
1543 of r31 as a minimal TOC load. */
1544 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1545 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1547 && !minimal_toc_loaded)
1549 minimal_toc_loaded = 1;
1552 /* move parameters from argument registers to local variable
1555 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1556 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1557 (((op >> 21) & 31) <= 10) &&
1558 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1562 /* store parameters in stack */
1564 /* Move parameters from argument registers to temporary register. */
1565 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1569 /* Set up frame pointer */
1571 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1572 || op == 0x7c3f0b78)
1574 fdata->frameless = 0;
1576 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1579 /* Another way to set up the frame pointer. */
1581 else if ((op & 0xfc1fffff) == 0x38010000)
1582 { /* addi rX, r1, 0x0 */
1583 fdata->frameless = 0;
1585 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1586 + ((op & ~0x38010000) >> 21));
1589 /* AltiVec related instructions. */
1590 /* Store the vrsave register (spr 256) in another register for
1591 later manipulation, or load a register into the vrsave
1592 register. 2 instructions are used: mfvrsave and
1593 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1594 and mtspr SPR256, Rn. */
1595 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1596 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1597 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1599 vrsave_reg = GET_SRC_REG (op);
1602 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1606 /* Store the register where vrsave was saved to onto the stack:
1607 rS is the register where vrsave was stored in a previous
1609 /* 100100 sssss 00001 dddddddd dddddddd */
1610 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1612 if (vrsave_reg == GET_SRC_REG (op))
1614 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1619 /* Compute the new value of vrsave, by modifying the register
1620 where vrsave was saved to. */
1621 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1622 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1626 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1627 in a pair of insns to save the vector registers on the
1629 /* 001110 00000 00000 iiii iiii iiii iiii */
1630 /* 001110 01110 00000 iiii iiii iiii iiii */
1631 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1632 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1634 if ((op & 0xffff0000) == 0x38000000)
1635 r0_contains_arg = 0;
1637 vr_saved_offset = SIGNED_SHORT (op);
1639 /* This insn by itself is not part of the prologue, unless
1640 if part of the pair of insns mentioned above. So do not
1641 record this insn as part of the prologue yet. */
1642 prev_insn_was_prologue_insn = 0;
1644 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1645 /* 011111 sssss 11111 00000 00111001110 */
1646 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1648 if (pc == (li_found_pc + 4))
1650 vr_reg = GET_SRC_REG (op);
1651 /* If this is the first vector reg to be saved, or if
1652 it has a lower number than others previously seen,
1653 reupdate the frame info. */
1654 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1656 fdata->saved_vr = vr_reg;
1657 fdata->vr_offset = vr_saved_offset + offset;
1659 vr_saved_offset = -1;
1664 /* End AltiVec related instructions. */
1666 /* Start BookE related instructions. */
1667 /* Store gen register S at (r31+uimm).
1668 Any register less than r13 is volatile, so we don't care. */
1669 /* 000100 sssss 11111 iiiii 01100100001 */
1670 else if (arch_info->mach == bfd_mach_ppc_e500
1671 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1673 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1676 ev_reg = GET_SRC_REG (op);
1677 imm = (op >> 11) & 0x1f;
1678 ev_offset = imm * 8;
1679 /* If this is the first vector reg to be saved, or if
1680 it has a lower number than others previously seen,
1681 reupdate the frame info. */
1682 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1684 fdata->saved_ev = ev_reg;
1685 fdata->ev_offset = ev_offset + offset;
1690 /* Store gen register rS at (r1+rB). */
1691 /* 000100 sssss 00001 bbbbb 01100100000 */
1692 else if (arch_info->mach == bfd_mach_ppc_e500
1693 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1695 if (pc == (li_found_pc + 4))
1697 ev_reg = GET_SRC_REG (op);
1698 /* If this is the first vector reg to be saved, or if
1699 it has a lower number than others previously seen,
1700 reupdate the frame info. */
1701 /* We know the contents of rB from the previous instruction. */
1702 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1704 fdata->saved_ev = ev_reg;
1705 fdata->ev_offset = vr_saved_offset + offset;
1707 vr_saved_offset = -1;
1713 /* Store gen register r31 at (rA+uimm). */
1714 /* 000100 11111 aaaaa iiiii 01100100001 */
1715 else if (arch_info->mach == bfd_mach_ppc_e500
1716 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1718 /* Wwe know that the source register is 31 already, but
1719 it can't hurt to compute it. */
1720 ev_reg = GET_SRC_REG (op);
1721 ev_offset = ((op >> 11) & 0x1f) * 8;
1722 /* If this is the first vector reg to be saved, or if
1723 it has a lower number than others previously seen,
1724 reupdate the frame info. */
1725 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1727 fdata->saved_ev = ev_reg;
1728 fdata->ev_offset = ev_offset + offset;
1733 /* Store gen register S at (r31+r0).
1734 Store param on stack when offset from SP bigger than 4 bytes. */
1735 /* 000100 sssss 11111 00000 01100100000 */
1736 else if (arch_info->mach == bfd_mach_ppc_e500
1737 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1739 if (pc == (li_found_pc + 4))
1741 if ((op & 0x03e00000) >= 0x01a00000)
1743 ev_reg = GET_SRC_REG (op);
1744 /* If this is the first vector reg to be saved, or if
1745 it has a lower number than others previously seen,
1746 reupdate the frame info. */
1747 /* We know the contents of r0 from the previous
1749 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1751 fdata->saved_ev = ev_reg;
1752 fdata->ev_offset = vr_saved_offset + offset;
1756 vr_saved_offset = -1;
1761 /* End BookE related instructions. */
1765 /* Not a recognized prologue instruction.
1766 Handle optimizer code motions into the prologue by continuing
1767 the search if we have no valid frame yet or if the return
1768 address is not yet saved in the frame. */
1769 if (fdata->frameless == 0 && fdata->nosavedpc == 0)
1772 if (op == 0x4e800020 /* blr */
1773 || op == 0x4e800420) /* bctr */
1774 /* Do not scan past epilogue in frameless functions or
1777 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1778 /* Never skip branches. */
1781 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1782 /* Do not scan too many insns, scanning insns is expensive with
1786 /* Continue scanning. */
1787 prev_insn_was_prologue_insn = 0;
1793 /* I have problems with skipping over __main() that I need to address
1794 * sometime. Previously, I used to use misc_function_vector which
1795 * didn't work as well as I wanted to be. -MGO */
1797 /* If the first thing after skipping a prolog is a branch to a function,
1798 this might be a call to an initializer in main(), introduced by gcc2.
1799 We'd like to skip over it as well. Fortunately, xlc does some extra
1800 work before calling a function right after a prologue, thus we can
1801 single out such gcc2 behaviour. */
1804 if ((op & 0xfc000001) == 0x48000001)
1805 { /* bl foo, an initializer function? */
1806 op = read_memory_integer (pc + 4, 4);
1808 if (op == 0x4def7b82)
1809 { /* cror 0xf, 0xf, 0xf (nop) */
1811 /* Check and see if we are in main. If so, skip over this
1812 initializer function as well. */
1814 tmp = find_pc_misc_function (pc);
1816 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1822 fdata->offset = -fdata->offset;
1823 return last_prologue_pc;
1827 /*************************************************************************
1828 Support for creating pushing a dummy frame into the stack, and popping
1830 *************************************************************************/
1833 /* All the ABI's require 16 byte alignment. */
1835 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1837 return (addr & -16);
1840 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1841 the first eight words of the argument list (that might be less than
1842 eight parameters if some parameters occupy more than one word) are
1843 passed in r3..r10 registers. float and double parameters are
1844 passed in fpr's, in addition to that. Rest of the parameters if any
1845 are passed in user stack. There might be cases in which half of the
1846 parameter is copied into registers, the other half is pushed into
1849 Stack must be aligned on 64-bit boundaries when synthesizing
1852 If the function is returning a structure, then the return address is passed
1853 in r3, then the first 7 words of the parameters can be passed in registers,
1854 starting from r4. */
1857 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1858 struct regcache *regcache, CORE_ADDR bp_addr,
1859 int nargs, struct value **args, CORE_ADDR sp,
1860 int struct_return, CORE_ADDR struct_addr)
1862 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1865 int argno; /* current argument number */
1866 int argbytes; /* current argument byte */
1867 gdb_byte tmp_buffer[50];
1868 int f_argno = 0; /* current floating point argno */
1869 int wordsize = gdbarch_tdep (gdbarch)->wordsize;
1870 CORE_ADDR func_addr = find_function_addr (function, NULL);
1872 struct value *arg = 0;
1877 /* The calling convention this function implements assumes the
1878 processor has floating-point registers. We shouldn't be using it
1879 on PPC variants that lack them. */
1880 gdb_assert (ppc_floating_point_unit_p (gdbarch));
1882 /* The first eight words of ther arguments are passed in registers.
1883 Copy them appropriately. */
1886 /* If the function is returning a `struct', then the first word
1887 (which will be passed in r3) is used for struct return address.
1888 In that case we should advance one word and start from r4
1889 register to copy parameters. */
1892 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1898 effectively indirect call... gcc does...
1900 return_val example( float, int);
1903 float in fp0, int in r3
1904 offset of stack on overflow 8/16
1905 for varargs, must go by type.
1907 float in r3&r4, int in r5
1908 offset of stack on overflow different
1910 return in r3 or f0. If no float, must study how gcc emulates floats;
1911 pay attention to arg promotion.
1912 User may have to cast\args to handle promotion correctly
1913 since gdb won't know if prototype supplied or not.
1916 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1918 int reg_size = register_size (gdbarch, ii + 3);
1921 type = check_typedef (value_type (arg));
1922 len = TYPE_LENGTH (type);
1924 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1927 /* Floating point arguments are passed in fpr's, as well as gpr's.
1928 There are 13 fpr's reserved for passing parameters. At this point
1929 there is no way we would run out of them. */
1931 gdb_assert (len <= 8);
1933 regcache_cooked_write (regcache,
1934 tdep->ppc_fp0_regnum + 1 + f_argno,
1935 value_contents (arg));
1942 /* Argument takes more than one register. */
1943 while (argbytes < len)
1945 gdb_byte word[MAX_REGISTER_SIZE];
1946 memset (word, 0, reg_size);
1948 ((char *) value_contents (arg)) + argbytes,
1949 (len - argbytes) > reg_size
1950 ? reg_size : len - argbytes);
1951 regcache_cooked_write (regcache,
1952 tdep->ppc_gp0_regnum + 3 + ii,
1954 ++ii, argbytes += reg_size;
1957 goto ran_out_of_registers_for_arguments;
1964 /* Argument can fit in one register. No problem. */
1965 int adj = gdbarch_byte_order (gdbarch)
1966 == BFD_ENDIAN_BIG ? reg_size - len : 0;
1967 gdb_byte word[MAX_REGISTER_SIZE];
1969 memset (word, 0, reg_size);
1970 memcpy (word, value_contents (arg), len);
1971 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1976 ran_out_of_registers_for_arguments:
1978 regcache_cooked_read_unsigned (regcache,
1979 gdbarch_sp_regnum (gdbarch),
1982 /* Location for 8 parameters are always reserved. */
1985 /* Another six words for back chain, TOC register, link register, etc. */
1988 /* Stack pointer must be quadword aligned. */
1991 /* If there are more arguments, allocate space for them in
1992 the stack, then push them starting from the ninth one. */
1994 if ((argno < nargs) || argbytes)
2000 space += ((len - argbytes + 3) & -4);
2006 for (; jj < nargs; ++jj)
2008 struct value *val = args[jj];
2009 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
2012 /* Add location required for the rest of the parameters. */
2013 space = (space + 15) & -16;
2016 /* This is another instance we need to be concerned about
2017 securing our stack space. If we write anything underneath %sp
2018 (r1), we might conflict with the kernel who thinks he is free
2019 to use this area. So, update %sp first before doing anything
2022 regcache_raw_write_signed (regcache,
2023 gdbarch_sp_regnum (gdbarch), sp);
2025 /* If the last argument copied into the registers didn't fit there
2026 completely, push the rest of it into stack. */
2030 write_memory (sp + 24 + (ii * 4),
2031 value_contents (arg) + argbytes,
2034 ii += ((len - argbytes + 3) & -4) / 4;
2037 /* Push the rest of the arguments into stack. */
2038 for (; argno < nargs; ++argno)
2042 type = check_typedef (value_type (arg));
2043 len = TYPE_LENGTH (type);
2046 /* Float types should be passed in fpr's, as well as in the
2048 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
2051 gdb_assert (len <= 8);
2053 regcache_cooked_write (regcache,
2054 tdep->ppc_fp0_regnum + 1 + f_argno,
2055 value_contents (arg));
2059 write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
2060 ii += ((len + 3) & -4) / 4;
2064 /* Set the stack pointer. According to the ABI, the SP is meant to
2065 be set _before_ the corresponding stack space is used. On AIX,
2066 this even applies when the target has been completely stopped!
2067 Not doing this can lead to conflicts with the kernel which thinks
2068 that it still has control over this not-yet-allocated stack
2070 regcache_raw_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
2072 /* Set back chain properly. */
2073 store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
2074 write_memory (sp, tmp_buffer, wordsize);
2076 /* Point the inferior function call's return address at the dummy's
2078 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
2080 /* Set the TOC register, get the value from the objfile reader
2081 which, in turn, gets it from the VMAP table. */
2082 if (rs6000_find_toc_address_hook != NULL)
2084 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
2085 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
2088 target_store_registers (regcache, -1);
2092 static enum return_value_convention
2093 rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype,
2094 struct regcache *regcache, gdb_byte *readbuf,
2095 const gdb_byte *writebuf)
2097 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2100 /* The calling convention this function implements assumes the
2101 processor has floating-point registers. We shouldn't be using it
2102 on PowerPC variants that lack them. */
2103 gdb_assert (ppc_floating_point_unit_p (gdbarch));
2105 /* AltiVec extension: Functions that declare a vector data type as a
2106 return value place that return value in VR2. */
2107 if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype)
2108 && TYPE_LENGTH (valtype) == 16)
2111 regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
2113 regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
2115 return RETURN_VALUE_REGISTER_CONVENTION;
2118 /* If the called subprogram returns an aggregate, there exists an
2119 implicit first argument, whose value is the address of a caller-
2120 allocated buffer into which the callee is assumed to store its
2121 return value. All explicit parameters are appropriately
2123 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2124 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2125 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2126 return RETURN_VALUE_STRUCT_CONVENTION;
2128 /* Scalar floating-point values are returned in FPR1 for float or
2129 double, and in FPR1:FPR2 for quadword precision. Fortran
2130 complex*8 and complex*16 are returned in FPR1:FPR2, and
2131 complex*32 is returned in FPR1:FPR4. */
2132 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
2133 && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8))
2135 struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
2138 /* FIXME: kettenis/2007-01-01: Add support for quadword
2139 precision and complex. */
2143 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
2144 convert_typed_floating (regval, regtype, readbuf, valtype);
2148 convert_typed_floating (writebuf, valtype, regval, regtype);
2149 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
2152 return RETURN_VALUE_REGISTER_CONVENTION;
2155 /* Values of the types int, long, short, pointer, and char (length
2156 is less than or equal to four bytes), as well as bit values of
2157 lengths less than or equal to 32 bits, must be returned right
2158 justified in GPR3 with signed values sign extended and unsigned
2159 values zero extended, as necessary. */
2160 if (TYPE_LENGTH (valtype) <= tdep->wordsize)
2166 /* For reading we don't have to worry about sign extension. */
2167 regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
2169 store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval);
2173 /* For writing, use unpack_long since that should handle any
2174 required sign extension. */
2175 regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
2176 unpack_long (valtype, writebuf));
2179 return RETURN_VALUE_REGISTER_CONVENTION;
2182 /* Eight-byte non-floating-point scalar values must be returned in
2185 if (TYPE_LENGTH (valtype) == 8)
2187 gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT);
2188 gdb_assert (tdep->wordsize == 4);
2194 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval);
2195 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
2197 memcpy (readbuf, regval, 8);
2201 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
2202 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
2206 return RETURN_VALUE_REGISTER_CONVENTION;
2209 return RETURN_VALUE_STRUCT_CONVENTION;
2212 /* Return whether handle_inferior_event() should proceed through code
2213 starting at PC in function NAME when stepping.
2215 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2216 handle memory references that are too distant to fit in instructions
2217 generated by the compiler. For example, if 'foo' in the following
2222 is greater than 32767, the linker might replace the lwz with a branch to
2223 somewhere in @FIX1 that does the load in 2 instructions and then branches
2224 back to where execution should continue.
2226 GDB should silently step over @FIX code, just like AIX dbx does.
2227 Unfortunately, the linker uses the "b" instruction for the
2228 branches, meaning that the link register doesn't get set.
2229 Therefore, GDB's usual step_over_function () mechanism won't work.
2231 Instead, use the gdbarch_skip_trampoline_code and
2232 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2236 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
2238 return name && !strncmp (name, "@FIX", 4);
2241 /* Skip code that the user doesn't want to see when stepping:
2243 1. Indirect function calls use a piece of trampoline code to do context
2244 switching, i.e. to set the new TOC table. Skip such code if we are on
2245 its first instruction (as when we have single-stepped to here).
2247 2. Skip shared library trampoline code (which is different from
2248 indirect function call trampolines).
2250 3. Skip bigtoc fixup code.
2252 Result is desired PC to step until, or NULL if we are not in
2253 code that should be skipped. */
2256 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
2258 unsigned int ii, op;
2260 CORE_ADDR solib_target_pc;
2261 struct minimal_symbol *msymbol;
2263 static unsigned trampoline_code[] =
2265 0x800b0000, /* l r0,0x0(r11) */
2266 0x90410014, /* st r2,0x14(r1) */
2267 0x7c0903a6, /* mtctr r0 */
2268 0x804b0004, /* l r2,0x4(r11) */
2269 0x816b0008, /* l r11,0x8(r11) */
2270 0x4e800420, /* bctr */
2271 0x4e800020, /* br */
2275 /* Check for bigtoc fixup code. */
2276 msymbol = lookup_minimal_symbol_by_pc (pc);
2278 && rs6000_in_solib_return_trampoline (pc,
2279 DEPRECATED_SYMBOL_NAME (msymbol)))
2281 /* Double-check that the third instruction from PC is relative "b". */
2282 op = read_memory_integer (pc + 8, 4);
2283 if ((op & 0xfc000003) == 0x48000000)
2285 /* Extract bits 6-29 as a signed 24-bit relative word address and
2286 add it to the containing PC. */
2287 rel = ((int)(op << 6) >> 6);
2288 return pc + 8 + rel;
2292 /* If pc is in a shared library trampoline, return its target. */
2293 solib_target_pc = find_solib_trampoline_target (frame, pc);
2294 if (solib_target_pc)
2295 return solib_target_pc;
2297 for (ii = 0; trampoline_code[ii]; ++ii)
2299 op = read_memory_integer (pc + (ii * 4), 4);
2300 if (op != trampoline_code[ii])
2303 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
2304 pc = read_memory_addr (ii,
2305 gdbarch_tdep (get_frame_arch (frame))->wordsize); /* (r11) value */
2309 /* ISA-specific vector types. */
2311 static struct type *
2312 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2314 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2316 if (!tdep->ppc_builtin_type_vec64)
2318 /* The type we're building is this: */
2320 union __gdb_builtin_type_vec64
2324 int32_t v2_int32[2];
2325 int16_t v4_int16[4];
2332 t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2333 append_composite_type_field (t, "uint64", builtin_type_int64);
2334 append_composite_type_field (t, "v2_float",
2335 init_vector_type (builtin_type_float, 2));
2336 append_composite_type_field (t, "v2_int32",
2337 init_vector_type (builtin_type_int32, 2));
2338 append_composite_type_field (t, "v4_int16",
2339 init_vector_type (builtin_type_int16, 4));
2340 append_composite_type_field (t, "v8_int8",
2341 init_vector_type (builtin_type_int8, 8));
2343 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR;
2344 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2345 tdep->ppc_builtin_type_vec64 = t;
2348 return tdep->ppc_builtin_type_vec64;
2351 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
2352 isn't available with that word size, return 0. */
2355 regsize (const struct reg *reg, int wordsize)
2357 return wordsize == 8 ? reg->sz64 : reg->sz32;
2360 /* Return the name of register number REGNO, or the empty string if it
2361 is an anonymous register. */
2364 rs6000_register_name (struct gdbarch *gdbarch, int regno)
2366 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2368 /* The upper half "registers" have names in the XML description,
2369 but we present only the low GPRs and the full 64-bit registers
2371 if (tdep->ppc_ev0_upper_regnum >= 0
2372 && tdep->ppc_ev0_upper_regnum <= regno
2373 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2376 /* Check if the SPE pseudo registers are available. */
2377 if (IS_SPE_PSEUDOREG (tdep, regno))
2379 static const char *const spe_regnames[] = {
2380 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2381 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2382 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2383 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2385 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2388 return tdesc_register_name (gdbarch, regno);
2391 /* Return the GDB type object for the "standard" data type of data in
2394 static struct type *
2395 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2397 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2399 /* These are the only pseudo-registers we support. */
2400 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum));
2402 return rs6000_builtin_type_vec64 (gdbarch);
2405 /* Is REGNUM a member of REGGROUP? */
2407 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2408 struct reggroup *group)
2410 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2412 /* These are the only pseudo-registers we support. */
2413 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum));
2415 if (group == all_reggroup || group == vector_reggroup)
2421 /* The register format for RS/6000 floating point registers is always
2422 double, we need a conversion if the memory format is float. */
2425 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2428 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2430 return (tdep->ppc_fp0_regnum >= 0
2431 && regnum >= tdep->ppc_fp0_regnum
2432 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2433 && TYPE_CODE (type) == TYPE_CODE_FLT
2434 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2438 rs6000_register_to_value (struct frame_info *frame,
2443 gdb_byte from[MAX_REGISTER_SIZE];
2445 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2447 get_frame_register (frame, regnum, from);
2448 convert_typed_floating (from, builtin_type_double, to, type);
2452 rs6000_value_to_register (struct frame_info *frame,
2455 const gdb_byte *from)
2457 gdb_byte to[MAX_REGISTER_SIZE];
2459 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2461 convert_typed_floating (from, type, to, builtin_type_double);
2462 put_frame_register (frame, regnum, to);
2465 /* Move SPE vector register values between a 64-bit buffer and the two
2466 32-bit raw register halves in a regcache. This function handles
2467 both splitting a 64-bit value into two 32-bit halves, and joining
2468 two halves into a whole 64-bit value, depending on the function
2469 passed as the MOVE argument.
2471 EV_REG must be the number of an SPE evN vector register --- a
2472 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2475 Call MOVE once for each 32-bit half of that register, passing
2476 REGCACHE, the number of the raw register corresponding to that
2477 half, and the address of the appropriate half of BUFFER.
2479 For example, passing 'regcache_raw_read' as the MOVE function will
2480 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2481 'regcache_raw_supply' will supply the contents of BUFFER to the
2482 appropriate pair of raw registers in REGCACHE.
2484 You may need to cast away some 'const' qualifiers when passing
2485 MOVE, since this function can't tell at compile-time which of
2486 REGCACHE or BUFFER is acting as the source of the data. If C had
2487 co-variant type qualifiers, ... */
2489 e500_move_ev_register (void (*move) (struct regcache *regcache,
2490 int regnum, gdb_byte *buf),
2491 struct regcache *regcache, int ev_reg,
2494 struct gdbarch *arch = get_regcache_arch (regcache);
2495 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2497 gdb_byte *byte_buffer = buffer;
2499 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
2501 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2503 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2505 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2506 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2510 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2511 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2516 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2517 int reg_nr, gdb_byte *buffer)
2519 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2520 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2522 gdb_assert (regcache_arch == gdbarch);
2524 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2525 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2527 internal_error (__FILE__, __LINE__,
2528 _("e500_pseudo_register_read: "
2529 "called on unexpected register '%s' (%d)"),
2530 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2534 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2535 int reg_nr, const gdb_byte *buffer)
2537 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2538 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2540 gdb_assert (regcache_arch == gdbarch);
2542 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2543 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2545 regcache, reg_nr, (gdb_byte *) buffer);
2547 internal_error (__FILE__, __LINE__,
2548 _("e500_pseudo_register_read: "
2549 "called on unexpected register '%s' (%d)"),
2550 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2553 /* Convert a DBX STABS register number to a GDB register number. */
2555 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
2557 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2559 if (0 <= num && num <= 31)
2560 return tdep->ppc_gp0_regnum + num;
2561 else if (32 <= num && num <= 63)
2562 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2563 specifies registers the architecture doesn't have? Our
2564 callers don't check the value we return. */
2565 return tdep->ppc_fp0_regnum + (num - 32);
2566 else if (77 <= num && num <= 108)
2567 return tdep->ppc_vr0_regnum + (num - 77);
2568 else if (1200 <= num && num < 1200 + 32)
2569 return tdep->ppc_ev0_regnum + (num - 1200);
2574 return tdep->ppc_mq_regnum;
2576 return tdep->ppc_lr_regnum;
2578 return tdep->ppc_ctr_regnum;
2580 return tdep->ppc_xer_regnum;
2582 return tdep->ppc_vrsave_regnum;
2584 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2586 return tdep->ppc_acc_regnum;
2588 return tdep->ppc_spefscr_regnum;
2595 /* Convert a Dwarf 2 register number to a GDB register number. */
2597 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
2599 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2601 if (0 <= num && num <= 31)
2602 return tdep->ppc_gp0_regnum + num;
2603 else if (32 <= num && num <= 63)
2604 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2605 specifies registers the architecture doesn't have? Our
2606 callers don't check the value we return. */
2607 return tdep->ppc_fp0_regnum + (num - 32);
2608 else if (1124 <= num && num < 1124 + 32)
2609 return tdep->ppc_vr0_regnum + (num - 1124);
2610 else if (1200 <= num && num < 1200 + 32)
2611 return tdep->ppc_ev0_regnum + (num - 1200);
2616 return tdep->ppc_cr_regnum;
2618 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2620 return tdep->ppc_acc_regnum;
2622 return tdep->ppc_mq_regnum;
2624 return tdep->ppc_xer_regnum;
2626 return tdep->ppc_lr_regnum;
2628 return tdep->ppc_ctr_regnum;
2630 return tdep->ppc_vrsave_regnum;
2632 return tdep->ppc_spefscr_regnum;
2638 /* Translate a .eh_frame register to DWARF register, or adjust a
2639 .debug_frame register. */
2642 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2644 /* GCC releases before 3.4 use GCC internal register numbering in
2645 .debug_frame (and .debug_info, et cetera). The numbering is
2646 different from the standard SysV numbering for everything except
2647 for GPRs and FPRs. We can not detect this problem in most cases
2648 - to get accurate debug info for variables living in lr, ctr, v0,
2649 et cetera, use a newer version of GCC. But we must detect
2650 one important case - lr is in column 65 in .debug_frame output,
2653 GCC 3.4, and the "hammer" branch, have a related problem. They
2654 record lr register saves in .debug_frame as 108, but still record
2655 the return column as 65. We fix that up too.
2657 We can do this because 65 is assigned to fpsr, and GCC never
2658 generates debug info referring to it. To add support for
2659 handwritten debug info that restores fpsr, we would need to add a
2660 producer version check to this. */
2669 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2670 internal register numbering; translate that to the standard DWARF2
2671 register numbering. */
2672 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2674 else if (68 <= num && num <= 75) /* cr0-cr8 */
2675 return num - 68 + 86;
2676 else if (77 <= num && num <= 108) /* vr0-vr31 */
2677 return num - 77 + 1124;
2689 case 109: /* vrsave */
2691 case 110: /* vscr */
2693 case 111: /* spe_acc */
2695 case 112: /* spefscr */
2702 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2704 Usually a function pointer's representation is simply the address
2705 of the function. On the RS/6000 however, a function pointer is
2706 represented by a pointer to an OPD entry. This OPD entry contains
2707 three words, the first word is the address of the function, the
2708 second word is the TOC pointer (r2), and the third word is the
2709 static chain value. Throughout GDB it is currently assumed that a
2710 function pointer contains the address of the function, which is not
2711 easy to fix. In addition, the conversion of a function address to
2712 a function pointer would require allocation of an OPD entry in the
2713 inferior's memory space, with all its drawbacks. To be able to
2714 call C++ virtual methods in the inferior (which are called via
2715 function pointers), find_function_addr uses this function to get the
2716 function address from a function pointer. */
2718 /* Return real function address if ADDR (a function pointer) is in the data
2719 space and is therefore a special function pointer. */
2722 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2724 struct target_ops *targ)
2726 struct obj_section *s;
2728 s = find_pc_section (addr);
2729 if (s && s->the_bfd_section->flags & SEC_CODE)
2732 /* ADDR is in the data space, so it's a special function pointer. */
2733 return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize);
2737 /* Handling the various POWER/PowerPC variants. */
2739 /* Information about a particular processor variant. */
2743 /* Name of this variant. */
2746 /* English description of the variant. */
2749 /* bfd_arch_info.arch corresponding to variant. */
2750 enum bfd_architecture arch;
2752 /* bfd_arch_info.mach corresponding to variant. */
2755 /* Target description for this variant. */
2756 struct target_desc **tdesc;
2759 static struct variant variants[] =
2761 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2762 bfd_mach_ppc, &tdesc_powerpc_32},
2763 {"power", "POWER user-level", bfd_arch_rs6000,
2764 bfd_mach_rs6k, &tdesc_rs6000},
2765 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2766 bfd_mach_ppc_403, &tdesc_powerpc_403},
2767 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2768 bfd_mach_ppc_601, &tdesc_powerpc_601},
2769 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2770 bfd_mach_ppc_602, &tdesc_powerpc_602},
2771 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2772 bfd_mach_ppc_603, &tdesc_powerpc_603},
2773 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2774 604, &tdesc_powerpc_604},
2775 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2776 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
2777 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2778 bfd_mach_ppc_505, &tdesc_powerpc_505},
2779 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2780 bfd_mach_ppc_860, &tdesc_powerpc_860},
2781 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2782 bfd_mach_ppc_750, &tdesc_powerpc_750},
2783 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2784 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
2785 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2786 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
2789 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2790 bfd_mach_ppc64, &tdesc_powerpc_64},
2791 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2792 bfd_mach_ppc_620, &tdesc_powerpc_64},
2793 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2794 bfd_mach_ppc_630, &tdesc_powerpc_64},
2795 {"a35", "PowerPC A35", bfd_arch_powerpc,
2796 bfd_mach_ppc_a35, &tdesc_powerpc_64},
2797 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2798 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
2799 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2800 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
2802 /* FIXME: I haven't checked the register sets of the following. */
2803 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2804 bfd_mach_rs6k_rs1, &tdesc_rs6000},
2805 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2806 bfd_mach_rs6k_rsc, &tdesc_rs6000},
2807 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2808 bfd_mach_rs6k_rs2, &tdesc_rs6000},
2813 /* Return the variant corresponding to architecture ARCH and machine number
2814 MACH. If no such variant exists, return null. */
2816 static const struct variant *
2817 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2819 const struct variant *v;
2821 for (v = variants; v->name; v++)
2822 if (arch == v->arch && mach == v->mach)
2829 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2831 if (!info->disassembler_options)
2832 info->disassembler_options = "any";
2834 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
2835 return print_insn_big_powerpc (memaddr, info);
2837 return print_insn_little_powerpc (memaddr, info);
2841 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2843 return frame_unwind_register_unsigned (next_frame,
2844 gdbarch_pc_regnum (gdbarch));
2847 static struct frame_id
2848 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2850 return frame_id_build (frame_unwind_register_unsigned
2851 (next_frame, gdbarch_sp_regnum (gdbarch)),
2852 frame_pc_unwind (next_frame));
2855 struct rs6000_frame_cache
2858 CORE_ADDR initial_sp;
2859 struct trad_frame_saved_reg *saved_regs;
2862 static struct rs6000_frame_cache *
2863 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2865 struct rs6000_frame_cache *cache;
2866 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2867 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2868 struct rs6000_framedata fdata;
2869 int wordsize = tdep->wordsize;
2872 if ((*this_cache) != NULL)
2873 return (*this_cache);
2874 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2875 (*this_cache) = cache;
2876 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2878 func = frame_func_unwind (next_frame, NORMAL_FRAME);
2879 pc = frame_pc_unwind (next_frame);
2880 skip_prologue (gdbarch, func, pc, &fdata);
2882 /* Figure out the parent's stack pointer. */
2884 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2885 address of the current frame. Things might be easier if the
2886 ->frame pointed to the outer-most address of the frame. In
2887 the mean time, the address of the prev frame is used as the
2888 base address of this frame. */
2889 cache->base = frame_unwind_register_unsigned
2890 (next_frame, gdbarch_sp_regnum (gdbarch));
2892 /* If the function appears to be frameless, check a couple of likely
2893 indicators that we have simply failed to find the frame setup.
2894 Two common cases of this are missing symbols (i.e.
2895 frame_func_unwind returns the wrong address or 0), and assembly
2896 stubs which have a fast exit path but set up a frame on the slow
2899 If the LR appears to return to this function, then presume that
2900 we have an ABI compliant frame that we failed to find. */
2901 if (fdata.frameless && fdata.lr_offset == 0)
2906 saved_lr = frame_unwind_register_unsigned (next_frame,
2907 tdep->ppc_lr_regnum);
2908 if (func == 0 && saved_lr == pc)
2912 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
2913 if (func == saved_func)
2919 fdata.frameless = 0;
2920 fdata.lr_offset = tdep->lr_frame_offset;
2924 if (!fdata.frameless)
2925 /* Frameless really means stackless. */
2926 cache->base = read_memory_addr (cache->base, wordsize);
2928 trad_frame_set_value (cache->saved_regs,
2929 gdbarch_sp_regnum (gdbarch), cache->base);
2931 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2932 All fpr's from saved_fpr to fp31 are saved. */
2934 if (fdata.saved_fpr >= 0)
2937 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
2939 /* If skip_prologue says floating-point registers were saved,
2940 but the current architecture has no floating-point registers,
2941 then that's strange. But we have no indices to even record
2942 the addresses under, so we just ignore it. */
2943 if (ppc_floating_point_unit_p (gdbarch))
2944 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
2946 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2951 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2952 All gpr's from saved_gpr to gpr31 are saved. */
2954 if (fdata.saved_gpr >= 0)
2957 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
2958 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
2960 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2961 gpr_addr += wordsize;
2965 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2966 All vr's from saved_vr to vr31 are saved. */
2967 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2969 if (fdata.saved_vr >= 0)
2972 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2973 for (i = fdata.saved_vr; i < 32; i++)
2975 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2976 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2981 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2982 All vr's from saved_ev to ev31 are saved. ????? */
2983 if (tdep->ppc_ev0_regnum != -1)
2985 if (fdata.saved_ev >= 0)
2988 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
2989 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
2991 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2992 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2993 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2998 /* If != 0, fdata.cr_offset is the offset from the frame that
3000 if (fdata.cr_offset != 0)
3001 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
3003 /* If != 0, fdata.lr_offset is the offset from the frame that
3005 if (fdata.lr_offset != 0)
3006 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
3007 /* The PC is found in the link register. */
3008 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3009 cache->saved_regs[tdep->ppc_lr_regnum];
3011 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3012 holds the VRSAVE. */
3013 if (fdata.vrsave_offset != 0)
3014 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
3016 if (fdata.alloca_reg < 0)
3017 /* If no alloca register used, then fi->frame is the value of the
3018 %sp for this frame, and it is good enough. */
3019 cache->initial_sp = frame_unwind_register_unsigned
3020 (next_frame, gdbarch_sp_regnum (gdbarch));
3022 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3029 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3030 struct frame_id *this_id)
3032 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3034 (*this_id) = frame_id_build (info->base,
3035 frame_func_unwind (next_frame, NORMAL_FRAME));
3039 rs6000_frame_prev_register (struct frame_info *next_frame,
3041 int regnum, int *optimizedp,
3042 enum lval_type *lvalp, CORE_ADDR *addrp,
3043 int *realnump, gdb_byte *valuep)
3045 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3047 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3048 optimizedp, lvalp, addrp, realnump, valuep);
3051 static const struct frame_unwind rs6000_frame_unwind =
3054 rs6000_frame_this_id,
3055 rs6000_frame_prev_register
3058 static const struct frame_unwind *
3059 rs6000_frame_sniffer (struct frame_info *next_frame)
3061 return &rs6000_frame_unwind;
3067 rs6000_frame_base_address (struct frame_info *next_frame,
3070 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3072 return info->initial_sp;
3075 static const struct frame_base rs6000_frame_base = {
3076 &rs6000_frame_unwind,
3077 rs6000_frame_base_address,
3078 rs6000_frame_base_address,
3079 rs6000_frame_base_address
3082 static const struct frame_base *
3083 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3085 return &rs6000_frame_base;
3088 /* DWARF-2 frame support. Used to handle the detection of
3089 clobbered registers during function calls. */
3092 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3093 struct dwarf2_frame_state_reg *reg,
3094 struct frame_info *next_frame)
3096 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3098 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3099 non-volatile registers. We will use the same code for both. */
3101 /* Call-saved GP registers. */
3102 if ((regnum >= tdep->ppc_gp0_regnum + 14
3103 && regnum <= tdep->ppc_gp0_regnum + 31)
3104 || (regnum == tdep->ppc_gp0_regnum + 1))
3105 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3107 /* Call-clobbered GP registers. */
3108 if ((regnum >= tdep->ppc_gp0_regnum + 3
3109 && regnum <= tdep->ppc_gp0_regnum + 12)
3110 || (regnum == tdep->ppc_gp0_regnum))
3111 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3113 /* Deal with FP registers, if supported. */
3114 if (tdep->ppc_fp0_regnum >= 0)
3116 /* Call-saved FP registers. */
3117 if ((regnum >= tdep->ppc_fp0_regnum + 14
3118 && regnum <= tdep->ppc_fp0_regnum + 31))
3119 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3121 /* Call-clobbered FP registers. */
3122 if ((regnum >= tdep->ppc_fp0_regnum
3123 && regnum <= tdep->ppc_fp0_regnum + 13))
3124 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3127 /* Deal with ALTIVEC registers, if supported. */
3128 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3130 /* Call-saved Altivec registers. */
3131 if ((regnum >= tdep->ppc_vr0_regnum + 20
3132 && regnum <= tdep->ppc_vr0_regnum + 31)
3133 || regnum == tdep->ppc_vrsave_regnum)
3134 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3136 /* Call-clobbered Altivec registers. */
3137 if ((regnum >= tdep->ppc_vr0_regnum
3138 && regnum <= tdep->ppc_vr0_regnum + 19))
3139 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3142 /* Handle PC register and Stack Pointer correctly. */
3143 if (regnum == gdbarch_pc_regnum (gdbarch))
3144 reg->how = DWARF2_FRAME_REG_RA;
3145 else if (regnum == gdbarch_sp_regnum (gdbarch))
3146 reg->how = DWARF2_FRAME_REG_CFA;
3150 /* Initialize the current architecture based on INFO. If possible, re-use an
3151 architecture from ARCHES, which is a list of architectures already created
3152 during this debugging session.
3154 Called e.g. at program startup, when reading a core file, and when reading
3157 static struct gdbarch *
3158 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3160 struct gdbarch *gdbarch;
3161 struct gdbarch_tdep *tdep;
3162 int wordsize, from_xcoff_exec, from_elf_exec;
3163 enum bfd_architecture arch;
3168 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3170 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
3171 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0;
3172 int tdesc_wordsize = -1;
3173 const struct target_desc *tdesc = info.target_desc;
3174 struct tdesc_arch_data *tdesc_data = NULL;
3176 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3177 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3179 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3180 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3182 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3184 /* Check word size. If INFO is from a binary file, infer it from
3185 that, else choose a likely default. */
3186 if (from_xcoff_exec)
3188 if (bfd_xcoff_is_xcoff64 (info.abfd))
3193 else if (from_elf_exec)
3195 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3200 else if (tdesc_has_registers (tdesc))
3204 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3205 wordsize = info.bfd_arch_info->bits_per_word /
3206 info.bfd_arch_info->bits_per_byte;
3211 if (!from_xcoff_exec)
3213 arch = info.bfd_arch_info->arch;
3214 mach = info.bfd_arch_info->mach;
3218 arch = bfd_arch_powerpc;
3219 bfd_default_set_arch_mach (&abfd, arch, 0);
3220 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3221 mach = info.bfd_arch_info->mach;
3224 /* For e500 executables, the apuinfo section is of help here. Such
3225 section contains the identifier and revision number of each
3226 Application-specific Processing Unit that is present on the
3227 chip. The content of the section is determined by the assembler
3228 which looks at each instruction and determines which unit (and
3229 which version of it) can execute it. In our case we just look for
3230 the existance of the section. */
3234 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3237 arch = info.bfd_arch_info->arch;
3238 mach = bfd_mach_ppc_e500;
3239 bfd_default_set_arch_mach (&abfd, arch, mach);
3240 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3244 /* Find a default target description which describes our register
3245 layout, if we do not already have one. */
3246 if (! tdesc_has_registers (tdesc))
3248 const struct variant *v;
3250 /* Choose variant. */
3251 v = find_variant_by_arch (arch, mach);
3258 gdb_assert (tdesc_has_registers (tdesc));
3260 /* Check any target description for validity. */
3261 if (tdesc_has_registers (tdesc))
3263 static const char *const gprs[] = {
3264 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3265 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3266 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3267 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3269 static const char *const segment_regs[] = {
3270 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3271 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3273 const struct tdesc_feature *feature;
3275 static const char *const msr_names[] = { "msr", "ps" };
3276 static const char *const cr_names[] = { "cr", "cnd" };
3277 static const char *const ctr_names[] = { "ctr", "cnt" };
3279 feature = tdesc_find_feature (tdesc,
3280 "org.gnu.gdb.power.core");
3281 if (feature == NULL)
3284 tdesc_data = tdesc_data_alloc ();
3287 for (i = 0; i < ppc_num_gprs; i++)
3288 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3289 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3291 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3293 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3296 /* Allow alternate names for these registers, to accomodate GDB's
3298 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3299 PPC_MSR_REGNUM, msr_names);
3300 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3301 PPC_CR_REGNUM, cr_names);
3302 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3303 PPC_CTR_REGNUM, ctr_names);
3307 tdesc_data_cleanup (tdesc_data);
3311 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3314 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3316 wordsize = tdesc_wordsize;
3318 feature = tdesc_find_feature (tdesc,
3319 "org.gnu.gdb.power.fpu");
3320 if (feature != NULL)
3322 static const char *const fprs[] = {
3323 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3324 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3325 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3326 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3329 for (i = 0; i < ppc_num_fprs; i++)
3330 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3331 PPC_F0_REGNUM + i, fprs[i]);
3332 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3333 PPC_FPSCR_REGNUM, "fpscr");
3337 tdesc_data_cleanup (tdesc_data);
3345 feature = tdesc_find_feature (tdesc,
3346 "org.gnu.gdb.power.altivec");
3347 if (feature != NULL)
3349 static const char *const vector_regs[] = {
3350 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3351 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3352 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3353 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3357 for (i = 0; i < ppc_num_gprs; i++)
3358 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3361 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3362 PPC_VSCR_REGNUM, "vscr");
3363 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3364 PPC_VRSAVE_REGNUM, "vrsave");
3366 if (have_spe || !valid_p)
3368 tdesc_data_cleanup (tdesc_data);
3376 /* On machines supporting the SPE APU, the general-purpose registers
3377 are 64 bits long. There are SIMD vector instructions to treat them
3378 as pairs of floats, but the rest of the instruction set treats them
3379 as 32-bit registers, and only operates on their lower halves.
3381 In the GDB regcache, we treat their high and low halves as separate
3382 registers. The low halves we present as the general-purpose
3383 registers, and then we have pseudo-registers that stitch together
3384 the upper and lower halves and present them as pseudo-registers.
3386 Thus, the target description is expected to supply the upper
3387 halves separately. */
3389 feature = tdesc_find_feature (tdesc,
3390 "org.gnu.gdb.power.spe");
3391 if (feature != NULL)
3393 static const char *const upper_spe[] = {
3394 "ev0h", "ev1h", "ev2h", "ev3h",
3395 "ev4h", "ev5h", "ev6h", "ev7h",
3396 "ev8h", "ev9h", "ev10h", "ev11h",
3397 "ev12h", "ev13h", "ev14h", "ev15h",
3398 "ev16h", "ev17h", "ev18h", "ev19h",
3399 "ev20h", "ev21h", "ev22h", "ev23h",
3400 "ev24h", "ev25h", "ev26h", "ev27h",
3401 "ev28h", "ev29h", "ev30h", "ev31h"
3405 for (i = 0; i < ppc_num_gprs; i++)
3406 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3407 PPC_SPE_UPPER_GP0_REGNUM + i,
3409 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3410 PPC_SPE_ACC_REGNUM, "acc");
3411 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3412 PPC_SPE_FSCR_REGNUM, "spefscr");
3414 if (have_mq || have_fpu || !valid_p)
3416 tdesc_data_cleanup (tdesc_data);
3425 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3426 complain for a 32-bit binary on a 64-bit target; we do not yet
3427 support that. For instance, the 32-bit ABI routines expect
3430 As long as there isn't an explicit target description, we'll
3431 choose one based on the BFD architecture and get a word size
3432 matching the binary (probably powerpc:common or
3433 powerpc:common64). So there is only trouble if a 64-bit target
3434 supplies a 64-bit description while debugging a 32-bit
3436 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3438 tdesc_data_cleanup (tdesc_data);
3443 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3445 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3446 Tag_GNU_Power_ABI_FP))
3449 soft_float_flag = AUTO_BOOLEAN_FALSE;
3452 soft_float_flag = AUTO_BOOLEAN_TRUE;
3459 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3461 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3462 Tag_GNU_Power_ABI_Vector))
3465 vector_abi = POWERPC_VEC_GENERIC;
3468 vector_abi = POWERPC_VEC_ALTIVEC;
3471 vector_abi = POWERPC_VEC_SPE;
3479 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3481 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3484 soft_float = !have_fpu;
3486 /* If we have a hard float binary or setting but no floating point
3487 registers, downgrade to soft float anyway. We're still somewhat
3488 useful in this scenario. */
3489 if (!soft_float && !have_fpu)
3492 /* Similarly for vector registers. */
3493 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3494 vector_abi = POWERPC_VEC_GENERIC;
3496 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3497 vector_abi = POWERPC_VEC_GENERIC;
3499 if (vector_abi == POWERPC_VEC_AUTO)
3502 vector_abi = POWERPC_VEC_ALTIVEC;
3504 vector_abi = POWERPC_VEC_SPE;
3506 vector_abi = POWERPC_VEC_GENERIC;
3509 /* Do not limit the vector ABI based on available hardware, since we
3510 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3512 /* Find a candidate among extant architectures. */
3513 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3515 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3517 /* Word size in the various PowerPC bfd_arch_info structs isn't
3518 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3519 separate word size check. */
3520 tdep = gdbarch_tdep (arches->gdbarch);
3521 if (tdep && tdep->soft_float != soft_float)
3523 if (tdep && tdep->vector_abi != vector_abi)
3525 if (tdep && tdep->wordsize == wordsize)
3527 if (tdesc_data != NULL)
3528 tdesc_data_cleanup (tdesc_data);
3529 return arches->gdbarch;
3533 /* None found, create a new architecture from INFO, whose bfd_arch_info
3534 validity depends on the source:
3535 - executable useless
3536 - rs6000_host_arch() good
3538 - "set arch" trust blindly
3539 - GDB startup useless but harmless */
3541 tdep = XCALLOC (1, struct gdbarch_tdep);
3542 tdep->wordsize = wordsize;
3543 tdep->soft_float = soft_float;
3544 tdep->vector_abi = vector_abi;
3546 gdbarch = gdbarch_alloc (&info, tdep);
3548 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3549 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3550 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3551 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3552 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3553 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3554 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3555 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3557 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3558 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
3559 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3560 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3561 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3562 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3563 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3565 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3566 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3567 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3568 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
3569 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3571 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3572 GDB traditionally called it "ps", though, so let GDB add an
3574 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3576 if (sysv_abi && wordsize == 8)
3577 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3578 else if (sysv_abi && wordsize == 4)
3579 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3581 set_gdbarch_return_value (gdbarch, rs6000_return_value);
3583 /* Set lr_frame_offset. */
3585 tdep->lr_frame_offset = 16;
3587 tdep->lr_frame_offset = 4;
3589 tdep->lr_frame_offset = 8;
3593 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3594 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3597 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3599 /* Select instruction printer. */
3600 if (arch == bfd_arch_rs6000)
3601 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3603 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3605 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
3606 set_gdbarch_num_pseudo_regs (gdbarch, have_spe ? 32 : 0);
3608 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3609 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3610 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3611 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3612 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3613 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3614 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3616 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3618 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3619 set_gdbarch_char_signed (gdbarch, 0);
3621 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3622 if (sysv_abi && wordsize == 8)
3624 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3625 else if (!sysv_abi && wordsize == 4)
3626 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3627 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3628 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3630 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3632 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3633 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3634 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3636 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3637 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3639 if (sysv_abi && wordsize == 4)
3640 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3641 else if (sysv_abi && wordsize == 8)
3642 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3644 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3646 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3647 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3649 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3650 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3652 /* The value of symbols of type N_SO and N_FUN maybe null when
3654 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
3656 /* Handles single stepping of atomic sequences. */
3657 set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence);
3659 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3660 for the descriptor and ".FN" for the entry-point -- a user
3661 specifying "break FN" will unexpectedly end up with a breakpoint
3662 on the descriptor and not the function. This architecture method
3663 transforms any breakpoints on descriptors into breakpoints on the
3664 corresponding entry point. */
3665 if (sysv_abi && wordsize == 8)
3666 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3668 /* Not sure on this. FIXMEmgo */
3669 set_gdbarch_frame_args_skip (gdbarch, 8);
3673 /* Handle RS/6000 function pointers (which are really function
3675 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3676 rs6000_convert_from_func_ptr_addr);
3679 /* Helpers for function argument information. */
3680 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3683 set_gdbarch_in_solib_return_trampoline
3684 (gdbarch, rs6000_in_solib_return_trampoline);
3685 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3687 /* Hook in the DWARF CFI frame unwinder. */
3688 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3689 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3691 /* Frame handling. */
3692 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
3694 /* Hook in ABI-specific overrides, if they have been registered. */
3695 gdbarch_init_osabi (info, gdbarch);
3699 case GDB_OSABI_LINUX:
3700 case GDB_OSABI_NETBSD_AOUT:
3701 case GDB_OSABI_NETBSD_ELF:
3702 case GDB_OSABI_UNKNOWN:
3703 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3704 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3705 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3706 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3709 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3711 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3712 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3713 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3714 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3717 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
3718 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3719 rs6000_pseudo_register_reggroup_p);
3720 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3722 /* Override the normal target description method to make the SPE upper
3723 halves anonymous. */
3724 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3726 /* Recording the numbering of pseudo registers. */
3727 tdep->ppc_ev0_regnum = have_spe ? gdbarch_num_regs (gdbarch) : -1;
3733 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3735 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3740 /* FIXME: Dump gdbarch_tdep. */
3743 /* PowerPC-specific commands. */
3746 set_powerpc_command (char *args, int from_tty)
3748 printf_unfiltered (_("\
3749 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
3750 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
3754 show_powerpc_command (char *args, int from_tty)
3756 cmd_show_list (showpowerpccmdlist, from_tty, "");
3760 powerpc_set_soft_float (char *args, int from_tty,
3761 struct cmd_list_element *c)
3763 struct gdbarch_info info;
3765 /* Update the architecture. */
3766 gdbarch_info_init (&info);
3767 if (!gdbarch_update_p (info))
3768 internal_error (__FILE__, __LINE__, "could not update architecture");
3772 powerpc_set_vector_abi (char *args, int from_tty,
3773 struct cmd_list_element *c)
3775 struct gdbarch_info info;
3776 enum powerpc_vector_abi vector_abi;
3778 for (vector_abi = POWERPC_VEC_AUTO;
3779 vector_abi != POWERPC_VEC_LAST;
3781 if (strcmp (powerpc_vector_abi_string,
3782 powerpc_vector_strings[vector_abi]) == 0)
3784 powerpc_vector_abi_global = vector_abi;
3788 if (vector_abi == POWERPC_VEC_LAST)
3789 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
3790 powerpc_vector_abi_string);
3792 /* Update the architecture. */
3793 gdbarch_info_init (&info);
3794 if (!gdbarch_update_p (info))
3795 internal_error (__FILE__, __LINE__, "could not update architecture");
3798 /* Initialization code. */
3800 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3803 _initialize_rs6000_tdep (void)
3805 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3806 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
3808 /* Initialize the standard target descriptions. */
3809 initialize_tdesc_powerpc_32 ();
3810 initialize_tdesc_powerpc_403 ();
3811 initialize_tdesc_powerpc_403gc ();
3812 initialize_tdesc_powerpc_505 ();
3813 initialize_tdesc_powerpc_601 ();
3814 initialize_tdesc_powerpc_602 ();
3815 initialize_tdesc_powerpc_603 ();
3816 initialize_tdesc_powerpc_604 ();
3817 initialize_tdesc_powerpc_64 ();
3818 initialize_tdesc_powerpc_7400 ();
3819 initialize_tdesc_powerpc_750 ();
3820 initialize_tdesc_powerpc_860 ();
3821 initialize_tdesc_powerpc_e500 ();
3822 initialize_tdesc_rs6000 ();
3824 /* Add root prefix command for all "set powerpc"/"show powerpc"
3826 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
3827 _("Various PowerPC-specific commands."),
3828 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
3830 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
3831 _("Various PowerPC-specific commands."),
3832 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
3834 /* Add a command to allow the user to force the ABI. */
3835 add_setshow_auto_boolean_cmd ("soft-float", class_support,
3836 &powerpc_soft_float_global,
3837 _("Set whether to use a soft-float ABI."),
3838 _("Show whether to use a soft-float ABI."),
3840 powerpc_set_soft_float, NULL,
3841 &setpowerpccmdlist, &showpowerpccmdlist);
3843 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
3844 &powerpc_vector_abi_string,
3845 _("Set the vector ABI."),
3846 _("Show the vector ABI."),
3847 NULL, powerpc_set_vector_abi, NULL,
3848 &setpowerpccmdlist, &showpowerpccmdlist);