1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "sim-regno.h"
41 #include "gdb/sim-ppc.h"
42 #include "reggroups.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
52 #include "solib-svr4.h"
55 #include "gdb_assert.h"
58 #include "trad-frame.h"
59 #include "frame-unwind.h"
60 #include "frame-base.h"
62 #include "reggroups.h"
64 /* If the kernel has to deliver a signal, it pushes a sigcontext
65 structure on the stack and then calls the signal handler, passing
66 the address of the sigcontext in an argument register. Usually
67 the signal handler doesn't save this register, so we have to
68 access the sigcontext structure via an offset from the signal handler
70 The following constants were determined by experimentation on AIX 3.2. */
71 #define SIG_FRAME_PC_OFFSET 96
72 #define SIG_FRAME_LR_OFFSET 108
73 #define SIG_FRAME_FP_OFFSET 284
75 /* To be used by skip_prologue. */
77 struct rs6000_framedata
79 int offset; /* total size of frame --- the distance
80 by which we decrement sp to allocate
82 int saved_gpr; /* smallest # of saved gpr */
83 int saved_fpr; /* smallest # of saved fpr */
84 int saved_vr; /* smallest # of saved vr */
85 int saved_ev; /* smallest # of saved ev */
86 int alloca_reg; /* alloca register number (frame ptr) */
87 char frameless; /* true if frameless functions. */
88 char nosavedpc; /* true if pc not saved. */
89 int gpr_offset; /* offset of saved gprs from prev sp */
90 int fpr_offset; /* offset of saved fprs from prev sp */
91 int vr_offset; /* offset of saved vrs from prev sp */
92 int ev_offset; /* offset of saved evs from prev sp */
93 int lr_offset; /* offset of saved lr */
94 int cr_offset; /* offset of saved cr */
95 int vrsave_offset; /* offset of saved vrsave register */
98 /* Description of a single register. */
102 char *name; /* name of register */
103 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
104 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
105 unsigned char fpr; /* whether register is floating-point */
106 unsigned char pseudo; /* whether register is pseudo */
107 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
108 This is an ISA SPR number, not a GDB
112 /* Breakpoint shadows for the single step instructions will be kept here. */
114 static struct sstep_breaks
116 /* Address, or 0 if this is not in use. */
118 /* Shadow contents. */
123 /* Hook for determining the TOC address when calling functions in the
124 inferior under AIX. The initialization code in rs6000-nat.c sets
125 this hook to point to find_toc_address. */
127 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
129 /* Hook to set the current architecture when starting a child process.
130 rs6000-nat.c sets this. */
132 void (*rs6000_set_host_arch_hook) (int) = NULL;
134 /* Static function prototypes */
136 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
138 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
139 struct rs6000_framedata *);
141 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
143 altivec_register_p (int regno)
145 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
146 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
149 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
153 /* Return true if REGNO is an SPE register, false otherwise. */
155 spe_register_p (int regno)
157 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
159 /* Is it a reference to EV0 -- EV31, and do we have those? */
160 if (tdep->ppc_ev0_regnum >= 0
161 && tdep->ppc_ev31_regnum >= 0
162 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
165 /* Is it a reference to one of the raw upper GPR halves? */
166 if (tdep->ppc_ev0_upper_regnum >= 0
167 && tdep->ppc_ev0_upper_regnum <= regno
168 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
171 /* Is it a reference to the 64-bit accumulator, and do we have that? */
172 if (tdep->ppc_acc_regnum >= 0
173 && tdep->ppc_acc_regnum == regno)
176 /* Is it a reference to the SPE floating-point status and control register,
177 and do we have that? */
178 if (tdep->ppc_spefscr_regnum >= 0
179 && tdep->ppc_spefscr_regnum == regno)
186 /* Return non-zero if the architecture described by GDBARCH has
187 floating-point registers (f0 --- f31 and fpscr). */
189 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
191 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193 return (tdep->ppc_fp0_regnum >= 0
194 && tdep->ppc_fpscr_regnum >= 0);
198 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
201 This is a helper function for init_sim_regno_table, constructing
202 the table mapping GDB register numbers to sim register numbers; we
203 initialize every element in that table to -1 before we start
206 set_sim_regno (int *table, int gdb_regno, int sim_regno)
208 /* Make sure we don't try to assign any given GDB register a sim
209 register number more than once. */
210 gdb_assert (table[gdb_regno] == -1);
211 table[gdb_regno] = sim_regno;
215 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
216 numbers to simulator register numbers, based on the values placed
217 in the ARCH->tdep->ppc_foo_regnum members. */
219 init_sim_regno_table (struct gdbarch *arch)
221 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
222 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch);
223 const struct reg *regs = tdep->regs;
224 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
227 /* Presume that all registers not explicitly mentioned below are
228 unavailable from the sim. */
229 for (i = 0; i < total_regs; i++)
232 /* General-purpose registers. */
233 for (i = 0; i < ppc_num_gprs; i++)
234 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
236 /* Floating-point registers. */
237 if (tdep->ppc_fp0_regnum >= 0)
238 for (i = 0; i < ppc_num_fprs; i++)
239 set_sim_regno (sim_regno,
240 tdep->ppc_fp0_regnum + i,
241 sim_ppc_f0_regnum + i);
242 if (tdep->ppc_fpscr_regnum >= 0)
243 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
245 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
246 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
247 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
249 /* Segment registers. */
250 if (tdep->ppc_sr0_regnum >= 0)
251 for (i = 0; i < ppc_num_srs; i++)
252 set_sim_regno (sim_regno,
253 tdep->ppc_sr0_regnum + i,
254 sim_ppc_sr0_regnum + i);
256 /* Altivec registers. */
257 if (tdep->ppc_vr0_regnum >= 0)
259 for (i = 0; i < ppc_num_vrs; i++)
260 set_sim_regno (sim_regno,
261 tdep->ppc_vr0_regnum + i,
262 sim_ppc_vr0_regnum + i);
264 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
265 we can treat this more like the other cases. */
266 set_sim_regno (sim_regno,
267 tdep->ppc_vr0_regnum + ppc_num_vrs,
268 sim_ppc_vscr_regnum);
270 /* vsave is a special-purpose register, so the code below handles it. */
272 /* SPE APU (E500) registers. */
273 if (tdep->ppc_ev0_regnum >= 0)
274 for (i = 0; i < ppc_num_gprs; i++)
275 set_sim_regno (sim_regno,
276 tdep->ppc_ev0_regnum + i,
277 sim_ppc_ev0_regnum + i);
278 if (tdep->ppc_ev0_upper_regnum >= 0)
279 for (i = 0; i < ppc_num_gprs; i++)
280 set_sim_regno (sim_regno,
281 tdep->ppc_ev0_upper_regnum + i,
282 sim_ppc_rh0_regnum + i);
283 if (tdep->ppc_acc_regnum >= 0)
284 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
285 /* spefscr is a special-purpose register, so the code below handles it. */
287 /* Now handle all special-purpose registers. Verify that they
288 haven't mistakenly been assigned numbers by any of the above
290 for (i = 0; i < total_regs; i++)
291 if (regs[i].spr_num >= 0)
292 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum);
294 /* Drop the initialized array into place. */
295 tdep->sim_regno = sim_regno;
299 /* Given a GDB register number REG, return the corresponding SIM
302 rs6000_register_sim_regno (int reg)
304 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
307 gdb_assert (0 <= reg && reg <= NUM_REGS + NUM_PSEUDO_REGS);
308 sim_regno = tdep->sim_regno[reg];
313 return LEGACY_SIM_REGNO_IGNORE;
318 /* Register set support functions. */
321 ppc_supply_reg (struct regcache *regcache, int regnum,
322 const char *regs, size_t offset)
324 if (regnum != -1 && offset != -1)
325 regcache_raw_supply (regcache, regnum, regs + offset);
329 ppc_collect_reg (const struct regcache *regcache, int regnum,
330 char *regs, size_t offset)
332 if (regnum != -1 && offset != -1)
333 regcache_raw_collect (regcache, regnum, regs + offset);
336 /* Supply register REGNUM in the general-purpose register set REGSET
337 from the buffer specified by GREGS and LEN to register cache
338 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
341 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
342 int regnum, const void *gregs, size_t len)
344 struct gdbarch *gdbarch = get_regcache_arch (regcache);
345 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
346 const struct ppc_reg_offsets *offsets = regset->descr;
350 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
351 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
354 if (regnum == -1 || regnum == i)
355 ppc_supply_reg (regcache, i, gregs, offset);
358 if (regnum == -1 || regnum == PC_REGNUM)
359 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
360 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
361 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
362 gregs, offsets->ps_offset);
363 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
364 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
365 gregs, offsets->cr_offset);
366 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
367 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
368 gregs, offsets->lr_offset);
369 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
370 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
371 gregs, offsets->ctr_offset);
372 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
373 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
374 gregs, offsets->cr_offset);
375 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
376 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
379 /* Supply register REGNUM in the floating-point register set REGSET
380 from the buffer specified by FPREGS and LEN to register cache
381 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
384 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
385 int regnum, const void *fpregs, size_t len)
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
389 const struct ppc_reg_offsets *offsets = regset->descr;
393 gdb_assert (ppc_floating_point_unit_p (gdbarch));
395 offset = offsets->f0_offset;
396 for (i = tdep->ppc_fp0_regnum;
397 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
400 if (regnum == -1 || regnum == i)
401 ppc_supply_reg (regcache, i, fpregs, offset);
404 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
405 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
406 fpregs, offsets->fpscr_offset);
409 /* Collect register REGNUM in the general-purpose register set
410 REGSET. from register cache REGCACHE into the buffer specified by
411 GREGS and LEN. If REGNUM is -1, do this for all registers in
415 ppc_collect_gregset (const struct regset *regset,
416 const struct regcache *regcache,
417 int regnum, void *gregs, size_t len)
419 struct gdbarch *gdbarch = get_regcache_arch (regcache);
420 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
421 const struct ppc_reg_offsets *offsets = regset->descr;
425 offset = offsets->r0_offset;
426 for (i = tdep->ppc_gp0_regnum;
427 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
430 if (regnum == -1 || regnum == i)
431 ppc_collect_reg (regcache, i, gregs, offset);
434 if (regnum == -1 || regnum == PC_REGNUM)
435 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
436 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
437 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
438 gregs, offsets->ps_offset);
439 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
440 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
441 gregs, offsets->cr_offset);
442 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
443 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
444 gregs, offsets->lr_offset);
445 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
446 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
447 gregs, offsets->ctr_offset);
448 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
449 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
450 gregs, offsets->xer_offset);
451 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
452 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
453 gregs, offsets->mq_offset);
456 /* Collect register REGNUM in the floating-point register set
457 REGSET. from register cache REGCACHE into the buffer specified by
458 FPREGS and LEN. If REGNUM is -1, do this for all registers in
462 ppc_collect_fpregset (const struct regset *regset,
463 const struct regcache *regcache,
464 int regnum, void *fpregs, size_t len)
466 struct gdbarch *gdbarch = get_regcache_arch (regcache);
467 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
468 const struct ppc_reg_offsets *offsets = regset->descr;
472 gdb_assert (ppc_floating_point_unit_p (gdbarch));
474 offset = offsets->f0_offset;
475 for (i = tdep->ppc_fp0_regnum;
476 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
479 if (regnum == -1 || regnum == i)
480 ppc_collect_reg (regcache, i, fpregs, offset);
483 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
484 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
485 fpregs, offsets->fpscr_offset);
489 /* Read a LEN-byte address from debugged memory address MEMADDR. */
492 read_memory_addr (CORE_ADDR memaddr, int len)
494 return read_memory_unsigned_integer (memaddr, len);
498 rs6000_skip_prologue (CORE_ADDR pc)
500 struct rs6000_framedata frame;
501 pc = skip_prologue (pc, 0, &frame);
506 /* Fill in fi->saved_regs */
508 struct frame_extra_info
510 /* Functions calling alloca() change the value of the stack
511 pointer. We need to use initial stack pointer (which is saved in
512 r31 by gcc) in such cases. If a compiler emits traceback table,
513 then we should use the alloca register specified in traceback
515 CORE_ADDR initial_sp; /* initial stack pointer. */
518 /* Get the ith function argument for the current function. */
520 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
524 get_frame_register (frame, 3 + argi, &addr);
528 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
531 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
538 absolute = (int) ((instr >> 1) & 1);
543 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
547 dest = pc + immediate;
551 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
555 dest = pc + immediate;
559 ext_op = (instr >> 1) & 0x3ff;
561 if (ext_op == 16) /* br conditional register */
563 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
565 /* If we are about to return from a signal handler, dest is
566 something like 0x3c90. The current frame is a signal handler
567 caller frame, upon completion of the sigreturn system call
568 execution will return to the saved PC in the frame. */
569 if (dest < TEXT_SEGMENT_BASE)
571 struct frame_info *fi;
573 fi = get_current_frame ();
575 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
576 gdbarch_tdep (current_gdbarch)->wordsize);
580 else if (ext_op == 528) /* br cond to count reg */
582 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
584 /* If we are about to execute a system call, dest is something
585 like 0x22fc or 0x3b00. Upon completion the system call
586 will return to the address in the link register. */
587 if (dest < TEXT_SEGMENT_BASE)
588 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
597 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
601 /* Sequence of bytes for breakpoint instruction. */
603 const static unsigned char *
604 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
606 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
607 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
609 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
610 return big_breakpoint;
612 return little_breakpoint;
616 /* AIX does not support PT_STEP. Simulate it. */
619 rs6000_software_single_step (enum target_signal signal,
620 int insert_breakpoints_p)
624 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
630 if (insert_breakpoints_p)
635 insn = read_memory_integer (loc, 4);
637 breaks[0] = loc + breakp_sz;
639 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
641 /* Don't put two breakpoints on the same address. */
642 if (breaks[1] == breaks[0])
645 stepBreaks[1].address = 0;
647 for (ii = 0; ii < 2; ++ii)
650 /* ignore invalid breakpoint. */
651 if (breaks[ii] == -1)
653 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
654 stepBreaks[ii].address = breaks[ii];
661 /* remove step breakpoints. */
662 for (ii = 0; ii < 2; ++ii)
663 if (stepBreaks[ii].address != 0)
664 target_remove_breakpoint (stepBreaks[ii].address,
665 stepBreaks[ii].data);
667 errno = 0; /* FIXME, don't ignore errors! */
668 /* What errors? {read,write}_memory call error(). */
672 /* return pc value after skipping a function prologue and also return
673 information about a function frame.
675 in struct rs6000_framedata fdata:
676 - frameless is TRUE, if function does not have a frame.
677 - nosavedpc is TRUE, if function does not save %pc value in its frame.
678 - offset is the initial size of this stack frame --- the amount by
679 which we decrement the sp to allocate the frame.
680 - saved_gpr is the number of the first saved gpr.
681 - saved_fpr is the number of the first saved fpr.
682 - saved_vr is the number of the first saved vr.
683 - saved_ev is the number of the first saved ev.
684 - alloca_reg is the number of the register used for alloca() handling.
686 - gpr_offset is the offset of the first saved gpr from the previous frame.
687 - fpr_offset is the offset of the first saved fpr from the previous frame.
688 - vr_offset is the offset of the first saved vr from the previous frame.
689 - ev_offset is the offset of the first saved ev from the previous frame.
690 - lr_offset is the offset of the saved lr
691 - cr_offset is the offset of the saved cr
692 - vrsave_offset is the offset of the saved vrsave register
695 #define SIGNED_SHORT(x) \
696 ((sizeof (short) == 2) \
697 ? ((int)(short)(x)) \
698 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
700 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
702 /* Limit the number of skipped non-prologue instructions, as the examining
703 of the prologue is expensive. */
704 static int max_skip_non_prologue_insns = 10;
706 /* Given PC representing the starting address of a function, and
707 LIM_PC which is the (sloppy) limit to which to scan when looking
708 for a prologue, attempt to further refine this limit by using
709 the line data in the symbol table. If successful, a better guess
710 on where the prologue ends is returned, otherwise the previous
711 value of lim_pc is returned. */
713 /* FIXME: cagney/2004-02-14: This function and logic have largely been
714 superseded by skip_prologue_using_sal. */
717 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
719 struct symtab_and_line prologue_sal;
721 prologue_sal = find_pc_line (pc, 0);
722 if (prologue_sal.line != 0)
725 CORE_ADDR addr = prologue_sal.end;
727 /* Handle the case in which compiler's optimizer/scheduler
728 has moved instructions into the prologue. We scan ahead
729 in the function looking for address ranges whose corresponding
730 line number is less than or equal to the first one that we
731 found for the function. (It can be less than when the
732 scheduler puts a body instruction before the first prologue
734 for (i = 2 * max_skip_non_prologue_insns;
735 i > 0 && (lim_pc == 0 || addr < lim_pc);
738 struct symtab_and_line sal;
740 sal = find_pc_line (addr, 0);
743 if (sal.line <= prologue_sal.line
744 && sal.symtab == prologue_sal.symtab)
751 if (lim_pc == 0 || prologue_sal.end < lim_pc)
752 lim_pc = prologue_sal.end;
757 /* Return nonzero if the given instruction OP can be part of the prologue
758 of a function and saves a parameter on the stack. FRAMEP should be
759 set if one of the previous instructions in the function has set the
763 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
765 /* Move parameters from argument registers to temporary register. */
766 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
768 /* Rx must be scratch register r0. */
769 const int rx_regno = (op >> 16) & 31;
770 /* Ry: Only r3 - r10 are used for parameter passing. */
771 const int ry_regno = GET_SRC_REG (op);
773 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
775 *r0_contains_arg = 1;
782 /* Save a General Purpose Register on stack. */
784 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
785 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
787 /* Rx: Only r3 - r10 are used for parameter passing. */
788 const int rx_regno = GET_SRC_REG (op);
790 return (rx_regno >= 3 && rx_regno <= 10);
793 /* Save a General Purpose Register on stack via the Frame Pointer. */
796 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
797 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
798 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
800 /* Rx: Usually, only r3 - r10 are used for parameter passing.
801 However, the compiler sometimes uses r0 to hold an argument. */
802 const int rx_regno = GET_SRC_REG (op);
804 return ((rx_regno >= 3 && rx_regno <= 10)
805 || (rx_regno == 0 && *r0_contains_arg));
808 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
810 /* Only f2 - f8 are used for parameter passing. */
811 const int src_regno = GET_SRC_REG (op);
813 return (src_regno >= 2 && src_regno <= 8);
816 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
818 /* Only f2 - f8 are used for parameter passing. */
819 const int src_regno = GET_SRC_REG (op);
821 return (src_regno >= 2 && src_regno <= 8);
824 /* Not an insn that saves a parameter on stack. */
829 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
831 CORE_ADDR orig_pc = pc;
832 CORE_ADDR last_prologue_pc = pc;
833 CORE_ADDR li_found_pc = 0;
837 long vr_saved_offset = 0;
846 int minimal_toc_loaded = 0;
847 int prev_insn_was_prologue_insn = 1;
848 int num_skip_non_prologue_insns = 0;
849 int r0_contains_arg = 0;
850 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
851 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
853 /* Attempt to find the end of the prologue when no limit is specified.
854 Note that refine_prologue_limit() has been written so that it may
855 be used to "refine" the limits of non-zero PC values too, but this
856 is only safe if we 1) trust the line information provided by the
857 compiler and 2) iterate enough to actually find the end of the
860 It may become a good idea at some point (for both performance and
861 accuracy) to unconditionally call refine_prologue_limit(). But,
862 until we can make a clear determination that this is beneficial,
863 we'll play it safe and only use it to obtain a limit when none
864 has been specified. */
866 lim_pc = refine_prologue_limit (pc, lim_pc);
868 memset (fdata, 0, sizeof (struct rs6000_framedata));
869 fdata->saved_gpr = -1;
870 fdata->saved_fpr = -1;
871 fdata->saved_vr = -1;
872 fdata->saved_ev = -1;
873 fdata->alloca_reg = -1;
874 fdata->frameless = 1;
875 fdata->nosavedpc = 1;
879 /* Sometimes it isn't clear if an instruction is a prologue
880 instruction or not. When we encounter one of these ambiguous
881 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
882 Otherwise, we'll assume that it really is a prologue instruction. */
883 if (prev_insn_was_prologue_insn)
884 last_prologue_pc = pc;
886 /* Stop scanning if we've hit the limit. */
887 if (lim_pc != 0 && pc >= lim_pc)
890 prev_insn_was_prologue_insn = 1;
892 /* Fetch the instruction and convert it to an integer. */
893 if (target_read_memory (pc, buf, 4))
895 op = extract_signed_integer (buf, 4);
897 if ((op & 0xfc1fffff) == 0x7c0802a6)
899 /* Since shared library / PIC code, which needs to get its
900 address at runtime, can appear to save more than one link
914 remember just the first one, but skip over additional
917 lr_reg = (op & 0x03e00000);
922 else if ((op & 0xfc1fffff) == 0x7c000026)
924 cr_reg = (op & 0x03e00000);
930 else if ((op & 0xfc1f0000) == 0xd8010000)
931 { /* stfd Rx,NUM(r1) */
932 reg = GET_SRC_REG (op);
933 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
935 fdata->saved_fpr = reg;
936 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
941 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
942 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
943 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
944 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
947 reg = GET_SRC_REG (op);
948 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
950 fdata->saved_gpr = reg;
951 if ((op & 0xfc1f0003) == 0xf8010000)
953 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
958 else if ((op & 0xffff0000) == 0x60000000)
961 /* Allow nops in the prologue, but do not consider them to
962 be part of the prologue unless followed by other prologue
964 prev_insn_was_prologue_insn = 0;
968 else if ((op & 0xffff0000) == 0x3c000000)
969 { /* addis 0,0,NUM, used
971 fdata->offset = (op & 0x0000ffff) << 16;
972 fdata->frameless = 0;
977 else if ((op & 0xffff0000) == 0x60000000)
978 { /* ori 0,0,NUM, 2nd ha
979 lf of >= 32k frames */
980 fdata->offset |= (op & 0x0000ffff);
981 fdata->frameless = 0;
986 else if (lr_reg >= 0 &&
987 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
988 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
989 /* stw Rx, NUM(r1) */
990 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
991 /* stwu Rx, NUM(r1) */
992 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
993 { /* where Rx == lr */
994 fdata->lr_offset = offset;
995 fdata->nosavedpc = 0;
996 /* Invalidate lr_reg, but don't set it to -1.
997 That would mean that it had never been set. */
999 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1000 (op & 0xfc000000) == 0x90000000) /* stw */
1002 /* Does not update r1, so add displacement to lr_offset. */
1003 fdata->lr_offset += SIGNED_SHORT (op);
1008 else if (cr_reg >= 0 &&
1009 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1010 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1011 /* stw Rx, NUM(r1) */
1012 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1013 /* stwu Rx, NUM(r1) */
1014 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1015 { /* where Rx == cr */
1016 fdata->cr_offset = offset;
1017 /* Invalidate cr_reg, but don't set it to -1.
1018 That would mean that it had never been set. */
1020 if ((op & 0xfc000003) == 0xf8000000 ||
1021 (op & 0xfc000000) == 0x90000000)
1023 /* Does not update r1, so add displacement to cr_offset. */
1024 fdata->cr_offset += SIGNED_SHORT (op);
1029 else if (op == 0x48000005)
1035 else if (op == 0x48000004)
1040 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1041 in V.4 -mminimal-toc */
1042 (op & 0xffff0000) == 0x3bde0000)
1043 { /* addi 30,30,foo@l */
1047 else if ((op & 0xfc000001) == 0x48000001)
1051 fdata->frameless = 0;
1052 /* Don't skip over the subroutine call if it is not within
1053 the first three instructions of the prologue and either
1054 we have no line table information or the line info tells
1055 us that the subroutine call is not part of the line
1056 associated with the prologue. */
1057 if ((pc - orig_pc) > 8)
1059 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1060 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1062 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1066 op = read_memory_integer (pc + 4, 4);
1068 /* At this point, make sure this is not a trampoline
1069 function (a function that simply calls another functions,
1070 and nothing else). If the next is not a nop, this branch
1071 was part of the function prologue. */
1073 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1074 break; /* don't skip over
1079 /* update stack pointer */
1080 else if ((op & 0xfc1f0000) == 0x94010000)
1081 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1082 fdata->frameless = 0;
1083 fdata->offset = SIGNED_SHORT (op);
1084 offset = fdata->offset;
1087 else if ((op & 0xfc1f016a) == 0x7c01016e)
1088 { /* stwux rX,r1,rY */
1089 /* no way to figure out what r1 is going to be */
1090 fdata->frameless = 0;
1091 offset = fdata->offset;
1094 else if ((op & 0xfc1f0003) == 0xf8010001)
1095 { /* stdu rX,NUM(r1) */
1096 fdata->frameless = 0;
1097 fdata->offset = SIGNED_SHORT (op & ~3UL);
1098 offset = fdata->offset;
1101 else if ((op & 0xfc1f016a) == 0x7c01016a)
1102 { /* stdux rX,r1,rY */
1103 /* no way to figure out what r1 is going to be */
1104 fdata->frameless = 0;
1105 offset = fdata->offset;
1108 /* Load up minimal toc pointer */
1109 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1110 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1111 && !minimal_toc_loaded)
1113 minimal_toc_loaded = 1;
1116 /* move parameters from argument registers to local variable
1119 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1120 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1121 (((op >> 21) & 31) <= 10) &&
1122 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1126 /* store parameters in stack */
1128 /* Move parameters from argument registers to temporary register. */
1129 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1133 /* Set up frame pointer */
1135 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1136 || op == 0x7c3f0b78)
1138 fdata->frameless = 0;
1140 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1143 /* Another way to set up the frame pointer. */
1145 else if ((op & 0xfc1fffff) == 0x38010000)
1146 { /* addi rX, r1, 0x0 */
1147 fdata->frameless = 0;
1149 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1150 + ((op & ~0x38010000) >> 21));
1153 /* AltiVec related instructions. */
1154 /* Store the vrsave register (spr 256) in another register for
1155 later manipulation, or load a register into the vrsave
1156 register. 2 instructions are used: mfvrsave and
1157 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1158 and mtspr SPR256, Rn. */
1159 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1160 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1161 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1163 vrsave_reg = GET_SRC_REG (op);
1166 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1170 /* Store the register where vrsave was saved to onto the stack:
1171 rS is the register where vrsave was stored in a previous
1173 /* 100100 sssss 00001 dddddddd dddddddd */
1174 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1176 if (vrsave_reg == GET_SRC_REG (op))
1178 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1183 /* Compute the new value of vrsave, by modifying the register
1184 where vrsave was saved to. */
1185 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1186 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1190 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1191 in a pair of insns to save the vector registers on the
1193 /* 001110 00000 00000 iiii iiii iiii iiii */
1194 /* 001110 01110 00000 iiii iiii iiii iiii */
1195 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1196 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1198 if ((op & 0xffff0000) == 0x38000000)
1199 r0_contains_arg = 0;
1201 vr_saved_offset = SIGNED_SHORT (op);
1203 /* This insn by itself is not part of the prologue, unless
1204 if part of the pair of insns mentioned above. So do not
1205 record this insn as part of the prologue yet. */
1206 prev_insn_was_prologue_insn = 0;
1208 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1209 /* 011111 sssss 11111 00000 00111001110 */
1210 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1212 if (pc == (li_found_pc + 4))
1214 vr_reg = GET_SRC_REG (op);
1215 /* If this is the first vector reg to be saved, or if
1216 it has a lower number than others previously seen,
1217 reupdate the frame info. */
1218 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1220 fdata->saved_vr = vr_reg;
1221 fdata->vr_offset = vr_saved_offset + offset;
1223 vr_saved_offset = -1;
1228 /* End AltiVec related instructions. */
1230 /* Start BookE related instructions. */
1231 /* Store gen register S at (r31+uimm).
1232 Any register less than r13 is volatile, so we don't care. */
1233 /* 000100 sssss 11111 iiiii 01100100001 */
1234 else if (arch_info->mach == bfd_mach_ppc_e500
1235 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1237 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1240 ev_reg = GET_SRC_REG (op);
1241 imm = (op >> 11) & 0x1f;
1242 ev_offset = imm * 8;
1243 /* If this is the first vector reg to be saved, or if
1244 it has a lower number than others previously seen,
1245 reupdate the frame info. */
1246 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1248 fdata->saved_ev = ev_reg;
1249 fdata->ev_offset = ev_offset + offset;
1254 /* Store gen register rS at (r1+rB). */
1255 /* 000100 sssss 00001 bbbbb 01100100000 */
1256 else if (arch_info->mach == bfd_mach_ppc_e500
1257 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1259 if (pc == (li_found_pc + 4))
1261 ev_reg = GET_SRC_REG (op);
1262 /* If this is the first vector reg to be saved, or if
1263 it has a lower number than others previously seen,
1264 reupdate the frame info. */
1265 /* We know the contents of rB from the previous instruction. */
1266 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1268 fdata->saved_ev = ev_reg;
1269 fdata->ev_offset = vr_saved_offset + offset;
1271 vr_saved_offset = -1;
1277 /* Store gen register r31 at (rA+uimm). */
1278 /* 000100 11111 aaaaa iiiii 01100100001 */
1279 else if (arch_info->mach == bfd_mach_ppc_e500
1280 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1282 /* Wwe know that the source register is 31 already, but
1283 it can't hurt to compute it. */
1284 ev_reg = GET_SRC_REG (op);
1285 ev_offset = ((op >> 11) & 0x1f) * 8;
1286 /* If this is the first vector reg to be saved, or if
1287 it has a lower number than others previously seen,
1288 reupdate the frame info. */
1289 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1291 fdata->saved_ev = ev_reg;
1292 fdata->ev_offset = ev_offset + offset;
1297 /* Store gen register S at (r31+r0).
1298 Store param on stack when offset from SP bigger than 4 bytes. */
1299 /* 000100 sssss 11111 00000 01100100000 */
1300 else if (arch_info->mach == bfd_mach_ppc_e500
1301 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1303 if (pc == (li_found_pc + 4))
1305 if ((op & 0x03e00000) >= 0x01a00000)
1307 ev_reg = GET_SRC_REG (op);
1308 /* If this is the first vector reg to be saved, or if
1309 it has a lower number than others previously seen,
1310 reupdate the frame info. */
1311 /* We know the contents of r0 from the previous
1313 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1315 fdata->saved_ev = ev_reg;
1316 fdata->ev_offset = vr_saved_offset + offset;
1320 vr_saved_offset = -1;
1325 /* End BookE related instructions. */
1329 /* Not a recognized prologue instruction.
1330 Handle optimizer code motions into the prologue by continuing
1331 the search if we have no valid frame yet or if the return
1332 address is not yet saved in the frame. */
1333 if (fdata->frameless == 0
1334 && (lr_reg == -1 || fdata->nosavedpc == 0))
1337 if (op == 0x4e800020 /* blr */
1338 || op == 0x4e800420) /* bctr */
1339 /* Do not scan past epilogue in frameless functions or
1342 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1343 /* Never skip branches. */
1346 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1347 /* Do not scan too many insns, scanning insns is expensive with
1351 /* Continue scanning. */
1352 prev_insn_was_prologue_insn = 0;
1358 /* I have problems with skipping over __main() that I need to address
1359 * sometime. Previously, I used to use misc_function_vector which
1360 * didn't work as well as I wanted to be. -MGO */
1362 /* If the first thing after skipping a prolog is a branch to a function,
1363 this might be a call to an initializer in main(), introduced by gcc2.
1364 We'd like to skip over it as well. Fortunately, xlc does some extra
1365 work before calling a function right after a prologue, thus we can
1366 single out such gcc2 behaviour. */
1369 if ((op & 0xfc000001) == 0x48000001)
1370 { /* bl foo, an initializer function? */
1371 op = read_memory_integer (pc + 4, 4);
1373 if (op == 0x4def7b82)
1374 { /* cror 0xf, 0xf, 0xf (nop) */
1376 /* Check and see if we are in main. If so, skip over this
1377 initializer function as well. */
1379 tmp = find_pc_misc_function (pc);
1381 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1387 fdata->offset = -fdata->offset;
1388 return last_prologue_pc;
1392 /*************************************************************************
1393 Support for creating pushing a dummy frame into the stack, and popping
1395 *************************************************************************/
1398 /* All the ABI's require 16 byte alignment. */
1400 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1402 return (addr & -16);
1405 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1406 the first eight words of the argument list (that might be less than
1407 eight parameters if some parameters occupy more than one word) are
1408 passed in r3..r10 registers. float and double parameters are
1409 passed in fpr's, in addition to that. Rest of the parameters if any
1410 are passed in user stack. There might be cases in which half of the
1411 parameter is copied into registers, the other half is pushed into
1414 Stack must be aligned on 64-bit boundaries when synthesizing
1417 If the function is returning a structure, then the return address is passed
1418 in r3, then the first 7 words of the parameters can be passed in registers,
1419 starting from r4. */
1422 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1423 struct regcache *regcache, CORE_ADDR bp_addr,
1424 int nargs, struct value **args, CORE_ADDR sp,
1425 int struct_return, CORE_ADDR struct_addr)
1427 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1430 int argno; /* current argument number */
1431 int argbytes; /* current argument byte */
1432 char tmp_buffer[50];
1433 int f_argno = 0; /* current floating point argno */
1434 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1435 CORE_ADDR func_addr = find_function_addr (function, NULL);
1437 struct value *arg = 0;
1442 /* The calling convention this function implements assumes the
1443 processor has floating-point registers. We shouldn't be using it
1444 on PPC variants that lack them. */
1445 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1447 /* The first eight words of ther arguments are passed in registers.
1448 Copy them appropriately. */
1451 /* If the function is returning a `struct', then the first word
1452 (which will be passed in r3) is used for struct return address.
1453 In that case we should advance one word and start from r4
1454 register to copy parameters. */
1457 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1463 effectively indirect call... gcc does...
1465 return_val example( float, int);
1468 float in fp0, int in r3
1469 offset of stack on overflow 8/16
1470 for varargs, must go by type.
1472 float in r3&r4, int in r5
1473 offset of stack on overflow different
1475 return in r3 or f0. If no float, must study how gcc emulates floats;
1476 pay attention to arg promotion.
1477 User may have to cast\args to handle promotion correctly
1478 since gdb won't know if prototype supplied or not.
1481 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1483 int reg_size = register_size (current_gdbarch, ii + 3);
1486 type = check_typedef (value_type (arg));
1487 len = TYPE_LENGTH (type);
1489 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1492 /* Floating point arguments are passed in fpr's, as well as gpr's.
1493 There are 13 fpr's reserved for passing parameters. At this point
1494 there is no way we would run out of them. */
1496 gdb_assert (len <= 8);
1498 regcache_cooked_write (regcache,
1499 tdep->ppc_fp0_regnum + 1 + f_argno,
1500 value_contents (arg));
1507 /* Argument takes more than one register. */
1508 while (argbytes < len)
1510 char word[MAX_REGISTER_SIZE];
1511 memset (word, 0, reg_size);
1513 ((char *) value_contents (arg)) + argbytes,
1514 (len - argbytes) > reg_size
1515 ? reg_size : len - argbytes);
1516 regcache_cooked_write (regcache,
1517 tdep->ppc_gp0_regnum + 3 + ii,
1519 ++ii, argbytes += reg_size;
1522 goto ran_out_of_registers_for_arguments;
1529 /* Argument can fit in one register. No problem. */
1530 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1531 char word[MAX_REGISTER_SIZE];
1533 memset (word, 0, reg_size);
1534 memcpy (word, value_contents (arg), len);
1535 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1540 ran_out_of_registers_for_arguments:
1542 saved_sp = read_sp ();
1544 /* Location for 8 parameters are always reserved. */
1547 /* Another six words for back chain, TOC register, link register, etc. */
1550 /* Stack pointer must be quadword aligned. */
1553 /* If there are more arguments, allocate space for them in
1554 the stack, then push them starting from the ninth one. */
1556 if ((argno < nargs) || argbytes)
1562 space += ((len - argbytes + 3) & -4);
1568 for (; jj < nargs; ++jj)
1570 struct value *val = args[jj];
1571 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
1574 /* Add location required for the rest of the parameters. */
1575 space = (space + 15) & -16;
1578 /* This is another instance we need to be concerned about
1579 securing our stack space. If we write anything underneath %sp
1580 (r1), we might conflict with the kernel who thinks he is free
1581 to use this area. So, update %sp first before doing anything
1584 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1586 /* If the last argument copied into the registers didn't fit there
1587 completely, push the rest of it into stack. */
1591 write_memory (sp + 24 + (ii * 4),
1592 ((char *) value_contents (arg)) + argbytes,
1595 ii += ((len - argbytes + 3) & -4) / 4;
1598 /* Push the rest of the arguments into stack. */
1599 for (; argno < nargs; ++argno)
1603 type = check_typedef (value_type (arg));
1604 len = TYPE_LENGTH (type);
1607 /* Float types should be passed in fpr's, as well as in the
1609 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1612 gdb_assert (len <= 8);
1614 regcache_cooked_write (regcache,
1615 tdep->ppc_fp0_regnum + 1 + f_argno,
1616 value_contents (arg));
1620 write_memory (sp + 24 + (ii * 4),
1621 (char *) value_contents (arg),
1623 ii += ((len + 3) & -4) / 4;
1627 /* Set the stack pointer. According to the ABI, the SP is meant to
1628 be set _before_ the corresponding stack space is used. On AIX,
1629 this even applies when the target has been completely stopped!
1630 Not doing this can lead to conflicts with the kernel which thinks
1631 that it still has control over this not-yet-allocated stack
1633 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1635 /* Set back chain properly. */
1636 store_unsigned_integer (tmp_buffer, 4, saved_sp);
1637 write_memory (sp, tmp_buffer, 4);
1639 /* Point the inferior function call's return address at the dummy's
1641 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1643 /* Set the TOC register, get the value from the objfile reader
1644 which, in turn, gets it from the VMAP table. */
1645 if (rs6000_find_toc_address_hook != NULL)
1647 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1648 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1651 target_store_registers (-1);
1655 /* PowerOpen always puts structures in memory. Vectors, which were
1656 added later, do get returned in a register though. */
1659 rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1661 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1662 && TYPE_VECTOR (value_type))
1668 rs6000_extract_return_value (struct type *valtype, bfd_byte *regbuf,
1672 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1674 /* The calling convention this function implements assumes the
1675 processor has floating-point registers. We shouldn't be using it
1676 on PPC variants that lack them. */
1677 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1679 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1682 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1683 We need to truncate the return value into float size (4 byte) if
1686 convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
1687 (tdep->ppc_fp0_regnum + 1)],
1688 builtin_type_double,
1692 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1693 && TYPE_LENGTH (valtype) == 16
1694 && TYPE_VECTOR (valtype))
1696 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1697 TYPE_LENGTH (valtype));
1701 /* return value is copied starting from r3. */
1702 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1703 && TYPE_LENGTH (valtype) < register_size (current_gdbarch, 3))
1704 offset = register_size (current_gdbarch, 3) - TYPE_LENGTH (valtype);
1707 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
1708 TYPE_LENGTH (valtype));
1712 /* Return whether handle_inferior_event() should proceed through code
1713 starting at PC in function NAME when stepping.
1715 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1716 handle memory references that are too distant to fit in instructions
1717 generated by the compiler. For example, if 'foo' in the following
1722 is greater than 32767, the linker might replace the lwz with a branch to
1723 somewhere in @FIX1 that does the load in 2 instructions and then branches
1724 back to where execution should continue.
1726 GDB should silently step over @FIX code, just like AIX dbx does.
1727 Unfortunately, the linker uses the "b" instruction for the
1728 branches, meaning that the link register doesn't get set.
1729 Therefore, GDB's usual step_over_function () mechanism won't work.
1731 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and
1732 SKIP_TRAMPOLINE_CODE hooks in handle_inferior_event() to skip past
1736 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1738 return name && !strncmp (name, "@FIX", 4);
1741 /* Skip code that the user doesn't want to see when stepping:
1743 1. Indirect function calls use a piece of trampoline code to do context
1744 switching, i.e. to set the new TOC table. Skip such code if we are on
1745 its first instruction (as when we have single-stepped to here).
1747 2. Skip shared library trampoline code (which is different from
1748 indirect function call trampolines).
1750 3. Skip bigtoc fixup code.
1752 Result is desired PC to step until, or NULL if we are not in
1753 code that should be skipped. */
1756 rs6000_skip_trampoline_code (CORE_ADDR pc)
1758 unsigned int ii, op;
1760 CORE_ADDR solib_target_pc;
1761 struct minimal_symbol *msymbol;
1763 static unsigned trampoline_code[] =
1765 0x800b0000, /* l r0,0x0(r11) */
1766 0x90410014, /* st r2,0x14(r1) */
1767 0x7c0903a6, /* mtctr r0 */
1768 0x804b0004, /* l r2,0x4(r11) */
1769 0x816b0008, /* l r11,0x8(r11) */
1770 0x4e800420, /* bctr */
1771 0x4e800020, /* br */
1775 /* Check for bigtoc fixup code. */
1776 msymbol = lookup_minimal_symbol_by_pc (pc);
1778 && rs6000_in_solib_return_trampoline (pc,
1779 DEPRECATED_SYMBOL_NAME (msymbol)))
1781 /* Double-check that the third instruction from PC is relative "b". */
1782 op = read_memory_integer (pc + 8, 4);
1783 if ((op & 0xfc000003) == 0x48000000)
1785 /* Extract bits 6-29 as a signed 24-bit relative word address and
1786 add it to the containing PC. */
1787 rel = ((int)(op << 6) >> 6);
1788 return pc + 8 + rel;
1792 /* If pc is in a shared library trampoline, return its target. */
1793 solib_target_pc = find_solib_trampoline_target (pc);
1794 if (solib_target_pc)
1795 return solib_target_pc;
1797 for (ii = 0; trampoline_code[ii]; ++ii)
1799 op = read_memory_integer (pc + (ii * 4), 4);
1800 if (op != trampoline_code[ii])
1803 ii = read_register (11); /* r11 holds destination addr */
1804 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1808 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1809 isn't available with that word size, return 0. */
1812 regsize (const struct reg *reg, int wordsize)
1814 return wordsize == 8 ? reg->sz64 : reg->sz32;
1817 /* Return the name of register number N, or null if no such register exists
1818 in the current architecture. */
1821 rs6000_register_name (int n)
1823 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1824 const struct reg *reg = tdep->regs + n;
1826 if (!regsize (reg, tdep->wordsize))
1831 /* Return the GDB type object for the "standard" data type
1832 of data in register N. */
1834 static struct type *
1835 rs6000_register_type (struct gdbarch *gdbarch, int n)
1837 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1838 const struct reg *reg = tdep->regs + n;
1841 return builtin_type_double;
1844 int size = regsize (reg, tdep->wordsize);
1848 return builtin_type_int0;
1850 return builtin_type_uint32;
1852 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1853 return builtin_type_vec64;
1855 return builtin_type_uint64;
1858 return builtin_type_vec128;
1861 internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"),
1867 /* Is REGNUM a member of REGGROUP? */
1869 rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
1870 struct reggroup *group)
1872 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1877 if (REGISTER_NAME (regnum) == NULL
1878 || *REGISTER_NAME (regnum) == '\0')
1880 if (group == all_reggroup)
1883 float_p = (regnum == tdep->ppc_fpscr_regnum
1884 || (regnum >= tdep->ppc_fp0_regnum
1885 && regnum < tdep->ppc_fp0_regnum + 32));
1886 if (group == float_reggroup)
1889 vector_p = ((regnum >= tdep->ppc_vr0_regnum
1890 && regnum < tdep->ppc_vr0_regnum + 32)
1891 || (regnum >= tdep->ppc_ev0_regnum
1892 && regnum < tdep->ppc_ev0_regnum + 32)
1893 || regnum == tdep->ppc_vrsave_regnum
1894 || regnum == tdep->ppc_acc_regnum
1895 || regnum == tdep->ppc_spefscr_regnum);
1896 if (group == vector_reggroup)
1899 /* Note that PS aka MSR isn't included - it's a system register (and
1900 besides, due to GCC's CFI foobar you do not want to restore
1902 general_p = ((regnum >= tdep->ppc_gp0_regnum
1903 && regnum < tdep->ppc_gp0_regnum + 32)
1904 || regnum == tdep->ppc_toc_regnum
1905 || regnum == tdep->ppc_cr_regnum
1906 || regnum == tdep->ppc_lr_regnum
1907 || regnum == tdep->ppc_ctr_regnum
1908 || regnum == tdep->ppc_xer_regnum
1909 || regnum == PC_REGNUM);
1910 if (group == general_reggroup)
1913 if (group == save_reggroup || group == restore_reggroup)
1914 return general_p || vector_p || float_p;
1919 /* The register format for RS/6000 floating point registers is always
1920 double, we need a conversion if the memory format is float. */
1923 rs6000_convert_register_p (int regnum, struct type *type)
1925 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1928 && TYPE_CODE (type) == TYPE_CODE_FLT
1929 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
1933 rs6000_register_to_value (struct frame_info *frame,
1938 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1939 char from[MAX_REGISTER_SIZE];
1941 gdb_assert (reg->fpr);
1942 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
1944 get_frame_register (frame, regnum, from);
1945 convert_typed_floating (from, builtin_type_double, to, type);
1949 rs6000_value_to_register (struct frame_info *frame,
1954 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum;
1955 char to[MAX_REGISTER_SIZE];
1957 gdb_assert (reg->fpr);
1958 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
1960 convert_typed_floating (from, type, to, builtin_type_double);
1961 put_frame_register (frame, regnum, to);
1964 /* Move SPE vector register values between a 64-bit buffer and the two
1965 32-bit raw register halves in a regcache. This function handles
1966 both splitting a 64-bit value into two 32-bit halves, and joining
1967 two halves into a whole 64-bit value, depending on the function
1968 passed as the MOVE argument.
1970 EV_REG must be the number of an SPE evN vector register --- a
1971 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
1974 Call MOVE once for each 32-bit half of that register, passing
1975 REGCACHE, the number of the raw register corresponding to that
1976 half, and the address of the appropriate half of BUFFER.
1978 For example, passing 'regcache_raw_read' as the MOVE function will
1979 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
1980 'regcache_raw_supply' will supply the contents of BUFFER to the
1981 appropriate pair of raw registers in REGCACHE.
1983 You may need to cast away some 'const' qualifiers when passing
1984 MOVE, since this function can't tell at compile-time which of
1985 REGCACHE or BUFFER is acting as the source of the data. If C had
1986 co-variant type qualifiers, ... */
1988 e500_move_ev_register (void (*move) (struct regcache *regcache,
1989 int regnum, void *buf),
1990 struct regcache *regcache, int ev_reg,
1993 struct gdbarch *arch = get_regcache_arch (regcache);
1994 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
1996 char *byte_buffer = buffer;
1998 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
1999 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
2001 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2003 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2005 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2006 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2010 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2011 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2016 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2017 int reg_nr, void *buffer)
2019 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2020 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2022 gdb_assert (regcache_arch == gdbarch);
2024 if (tdep->ppc_ev0_regnum <= reg_nr
2025 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2026 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2028 internal_error (__FILE__, __LINE__,
2029 _("e500_pseudo_register_read: "
2030 "called on unexpected register '%s' (%d)"),
2031 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2035 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2036 int reg_nr, const void *buffer)
2038 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2039 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2041 gdb_assert (regcache_arch == gdbarch);
2043 if (tdep->ppc_ev0_regnum <= reg_nr
2044 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2045 e500_move_ev_register ((void (*) (struct regcache *, int, void *))
2047 regcache, reg_nr, (void *) buffer);
2049 internal_error (__FILE__, __LINE__,
2050 _("e500_pseudo_register_read: "
2051 "called on unexpected register '%s' (%d)"),
2052 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2055 /* The E500 needs a custom reggroup function: it has anonymous raw
2056 registers, and default_register_reggroup_p assumes that anonymous
2057 registers are not members of any reggroup. */
2059 e500_register_reggroup_p (struct gdbarch *gdbarch,
2061 struct reggroup *group)
2063 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2065 /* The save and restore register groups need to include the
2066 upper-half registers, even though they're anonymous. */
2067 if ((group == save_reggroup
2068 || group == restore_reggroup)
2069 && (tdep->ppc_ev0_upper_regnum <= regnum
2070 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs))
2073 /* In all other regards, the default reggroup definition is fine. */
2074 return default_register_reggroup_p (gdbarch, regnum, group);
2077 /* Convert a DBX STABS register number to a GDB register number. */
2079 rs6000_stab_reg_to_regnum (int num)
2081 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2083 if (0 <= num && num <= 31)
2084 return tdep->ppc_gp0_regnum + num;
2085 else if (32 <= num && num <= 63)
2086 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2087 specifies registers the architecture doesn't have? Our
2088 callers don't check the value we return. */
2089 return tdep->ppc_fp0_regnum + (num - 32);
2090 else if (77 <= num && num <= 108)
2091 return tdep->ppc_vr0_regnum + (num - 77);
2092 else if (1200 <= num && num < 1200 + 32)
2093 return tdep->ppc_ev0_regnum + (num - 1200);
2098 return tdep->ppc_mq_regnum;
2100 return tdep->ppc_lr_regnum;
2102 return tdep->ppc_ctr_regnum;
2104 return tdep->ppc_xer_regnum;
2106 return tdep->ppc_vrsave_regnum;
2108 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2110 return tdep->ppc_acc_regnum;
2112 return tdep->ppc_spefscr_regnum;
2119 /* Convert a Dwarf 2 register number to a GDB register number. */
2121 rs6000_dwarf2_reg_to_regnum (int num)
2123 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2125 if (0 <= num && num <= 31)
2126 return tdep->ppc_gp0_regnum + num;
2127 else if (32 <= num && num <= 63)
2128 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2129 specifies registers the architecture doesn't have? Our
2130 callers don't check the value we return. */
2131 return tdep->ppc_fp0_regnum + (num - 32);
2132 else if (1124 <= num && num < 1124 + 32)
2133 return tdep->ppc_vr0_regnum + (num - 1124);
2134 else if (1200 <= num && num < 1200 + 32)
2135 return tdep->ppc_ev0_regnum + (num - 1200);
2140 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2142 return tdep->ppc_acc_regnum;
2144 return tdep->ppc_mq_regnum;
2146 return tdep->ppc_xer_regnum;
2148 return tdep->ppc_lr_regnum;
2150 return tdep->ppc_ctr_regnum;
2152 return tdep->ppc_vrsave_regnum;
2154 return tdep->ppc_spefscr_regnum;
2162 rs6000_store_return_value (struct type *type,
2163 struct regcache *regcache,
2166 struct gdbarch *gdbarch = get_regcache_arch (regcache);
2167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2170 /* The calling convention this function implements assumes the
2171 processor has floating-point registers. We shouldn't be using it
2172 on PPC variants that lack them. */
2173 gdb_assert (ppc_floating_point_unit_p (gdbarch));
2175 if (TYPE_CODE (type) == TYPE_CODE_FLT)
2176 /* Floating point values are returned starting from FPR1 and up.
2177 Say a double_double_double type could be returned in
2178 FPR1/FPR2/FPR3 triple. */
2179 regnum = tdep->ppc_fp0_regnum + 1;
2180 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
2182 if (TYPE_LENGTH (type) == 16
2183 && TYPE_VECTOR (type))
2184 regnum = tdep->ppc_vr0_regnum + 2;
2186 internal_error (__FILE__, __LINE__,
2187 _("rs6000_store_return_value: "
2188 "unexpected array return type"));
2191 /* Everything else is returned in GPR3 and up. */
2192 regnum = tdep->ppc_gp0_regnum + 3;
2195 size_t bytes_written = 0;
2197 while (bytes_written < TYPE_LENGTH (type))
2199 /* How much of this value can we write to this register? */
2200 size_t bytes_to_write = min (TYPE_LENGTH (type) - bytes_written,
2201 register_size (gdbarch, regnum));
2202 regcache_cooked_write_part (regcache, regnum,
2204 (char *) valbuf + bytes_written);
2206 bytes_written += bytes_to_write;
2212 /* Extract from an array REGBUF containing the (raw) register state
2213 the address in which a function should return its structure value,
2214 as a CORE_ADDR (or an expression that can be used as one). */
2217 rs6000_extract_struct_value_address (struct regcache *regcache)
2219 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
2220 function call GDB knows the address of the struct return value
2221 and hence, should not need to call this function. Unfortunately,
2222 the current call_function_by_hand() code only saves the most
2223 recent struct address leading to occasional calls. The code
2224 should instead maintain a stack of such addresses (in the dummy
2226 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
2227 really got no idea where the return value is being stored. While
2228 r3, on function entry, contained the address it will have since
2229 been reused (scratch) and hence wouldn't be valid */
2233 /* Hook called when a new child process is started. */
2236 rs6000_create_inferior (int pid)
2238 if (rs6000_set_host_arch_hook)
2239 rs6000_set_host_arch_hook (pid);
2242 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2244 Usually a function pointer's representation is simply the address
2245 of the function. On the RS/6000 however, a function pointer is
2246 represented by a pointer to a TOC entry. This TOC entry contains
2247 three words, the first word is the address of the function, the
2248 second word is the TOC pointer (r2), and the third word is the
2249 static chain value. Throughout GDB it is currently assumed that a
2250 function pointer contains the address of the function, which is not
2251 easy to fix. In addition, the conversion of a function address to
2252 a function pointer would require allocation of a TOC entry in the
2253 inferior's memory space, with all its drawbacks. To be able to
2254 call C++ virtual methods in the inferior (which are called via
2255 function pointers), find_function_addr uses this function to get the
2256 function address from a function pointer. */
2258 /* Return real function address if ADDR (a function pointer) is in the data
2259 space and is therefore a special function pointer. */
2262 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2264 struct target_ops *targ)
2266 struct obj_section *s;
2268 s = find_pc_section (addr);
2269 if (s && s->the_bfd_section->flags & SEC_CODE)
2272 /* ADDR is in the data space, so it's a special function pointer. */
2273 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
2277 /* Handling the various POWER/PowerPC variants. */
2280 /* The arrays here called registers_MUMBLE hold information about available
2283 For each family of PPC variants, I've tried to isolate out the
2284 common registers and put them up front, so that as long as you get
2285 the general family right, GDB will correctly identify the registers
2286 common to that family. The common register sets are:
2288 For the 60x family: hid0 hid1 iabr dabr pir
2290 For the 505 and 860 family: eie eid nri
2292 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
2293 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
2296 Most of these register groups aren't anything formal. I arrived at
2297 them by looking at the registers that occurred in more than one
2300 Note: kevinb/2002-04-30: Support for the fpscr register was added
2301 during April, 2002. Slot 70 is being used for PowerPC and slot 71
2302 for Power. For PowerPC, slot 70 was unused and was already in the
2303 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
2304 slot 70 was being used for "mq", so the next available slot (71)
2305 was chosen. It would have been nice to be able to make the
2306 register numbers the same across processor cores, but this wasn't
2307 possible without either 1) renumbering some registers for some
2308 processors or 2) assigning fpscr to a really high slot that's
2309 larger than any current register number. Doing (1) is bad because
2310 existing stubs would break. Doing (2) is undesirable because it
2311 would introduce a really large gap between fpscr and the rest of
2312 the registers for most processors. */
2314 /* Convenience macros for populating register arrays. */
2316 /* Within another macro, convert S to a string. */
2320 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
2321 and 64 bits on 64-bit systems. */
2322 #define R(name) { STR(name), 4, 8, 0, 0, -1 }
2324 /* Return a struct reg defining register NAME that's 32 bits on all
2326 #define R4(name) { STR(name), 4, 4, 0, 0, -1 }
2328 /* Return a struct reg defining register NAME that's 64 bits on all
2330 #define R8(name) { STR(name), 8, 8, 0, 0, -1 }
2332 /* Return a struct reg defining register NAME that's 128 bits on all
2334 #define R16(name) { STR(name), 16, 16, 0, 0, -1 }
2336 /* Return a struct reg defining floating-point register NAME. */
2337 #define F(name) { STR(name), 8, 8, 1, 0, -1 }
2339 /* Return a struct reg defining a pseudo register NAME that is 64 bits
2340 long on all systems. */
2341 #define P8(name) { STR(name), 8, 8, 0, 1, -1 }
2343 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
2344 systems and that doesn't exist on 64-bit systems. */
2345 #define R32(name) { STR(name), 4, 0, 0, 0, -1 }
2347 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
2348 systems and that doesn't exist on 32-bit systems. */
2349 #define R64(name) { STR(name), 0, 8, 0, 0, -1 }
2351 /* Return a struct reg placeholder for a register that doesn't exist. */
2352 #define R0 { 0, 0, 0, 0, 0, -1 }
2354 /* Return a struct reg defining an anonymous raw register that's 32
2355 bits on all systems. */
2356 #define A4 { 0, 4, 4, 0, 0, -1 }
2358 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2359 32-bit systems and 64 bits on 64-bit systems. */
2360 #define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name }
2362 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2364 #define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name }
2366 /* Return a struct reg defining an SPR named NAME that is 32 bits on
2367 all systems, and whose SPR number is NUMBER. */
2368 #define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) }
2370 /* Return a struct reg defining an SPR named NAME that's 64 bits on
2371 64-bit systems and that doesn't exist on 32-bit systems. */
2372 #define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name }
2374 /* UISA registers common across all architectures, including POWER. */
2376 #define COMMON_UISA_REGS \
2377 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
2378 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
2379 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
2380 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
2381 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
2382 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
2383 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
2384 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
2385 /* 64 */ R(pc), R(ps)
2387 /* UISA-level SPRs for PowerPC. */
2388 #define PPC_UISA_SPRS \
2389 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr)
2391 /* UISA-level SPRs for PowerPC without floating point support. */
2392 #define PPC_UISA_NOFP_SPRS \
2393 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0
2395 /* Segment registers, for PowerPC. */
2396 #define PPC_SEGMENT_REGS \
2397 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
2398 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
2399 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
2400 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
2402 /* OEA SPRs for PowerPC. */
2403 #define PPC_OEA_SPRS \
2405 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \
2406 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \
2407 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \
2408 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \
2409 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \
2410 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \
2411 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \
2412 /* 116 */ S4(dec), S(dabr), S4(ear)
2414 /* AltiVec registers. */
2415 #define PPC_ALTIVEC_REGS \
2416 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2417 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2418 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2419 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2420 /*151*/R4(vscr), R4(vrsave)
2423 /* On machines supporting the SPE APU, the general-purpose registers
2424 are 64 bits long. There are SIMD vector instructions to treat them
2425 as pairs of floats, but the rest of the instruction set treats them
2426 as 32-bit registers, and only operates on their lower halves.
2428 In the GDB regcache, we treat their high and low halves as separate
2429 registers. The low halves we present as the general-purpose
2430 registers, and then we have pseudo-registers that stitch together
2431 the upper and lower halves and present them as pseudo-registers. */
2433 /* SPE GPR lower halves --- raw registers. */
2434 #define PPC_SPE_GP_REGS \
2435 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \
2436 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \
2437 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \
2438 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31)
2440 /* SPE GPR upper halves --- anonymous raw registers. */
2441 #define PPC_SPE_UPPER_GP_REGS \
2442 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2443 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2444 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \
2445 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4
2447 /* SPE GPR vector registers --- pseudo registers based on underlying
2448 gprs and the anonymous upper half raw registers. */
2449 #define PPC_EV_PSEUDO_REGS \
2450 /* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \
2451 /* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\
2452 /*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\
2453 /*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31)
2455 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2456 user-level SPR's. */
2457 static const struct reg registers_power[] =
2460 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq),
2464 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2465 view of the PowerPC. */
2466 static const struct reg registers_powerpc[] =
2475 Some notes about the "tcr" special-purpose register:
2476 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the
2477 403's programmable interval timer, fixed interval timer, and
2479 - On the 602, SPR 984 is named "tcr", and it controls the 602's
2480 watchdog timer, and nothing else.
2482 Some of the fields are similar between the two, but they're not
2483 compatible with each other. Since the two variants have different
2484 registers, with different numbers, but the same name, we can't
2485 splice the register name to get the SPR number. */
2486 static const struct reg registers_403[] =
2492 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2493 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2494 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2495 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2496 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2497 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2)
2500 /* IBM PowerPC 403GC.
2501 See the comments about 'tcr' for the 403, above. */
2502 static const struct reg registers_403GC[] =
2508 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr),
2509 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit),
2510 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3),
2511 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2),
2512 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr),
2513 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2),
2514 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr),
2515 /* 147 */ S(tbhu), S(tblu)
2518 /* Motorola PowerPC 505. */
2519 static const struct reg registers_505[] =
2525 /* 119 */ S(eie), S(eid), S(nri)
2528 /* Motorola PowerPC 860 or 850. */
2529 static const struct reg registers_860[] =
2535 /* 119 */ S(eie), S(eid), S(nri), S(cmpa),
2536 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr),
2537 /* 127 */ S(der), S(counta), S(countb), S(cmpe),
2538 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1),
2539 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst),
2540 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr),
2541 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr),
2542 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc),
2543 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap),
2544 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn),
2545 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1),
2546 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1)
2549 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2550 for reading and writing RTCU and RTCL. However, how one reads and writes a
2551 register is the stub's problem. */
2552 static const struct reg registers_601[] =
2558 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2559 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl)
2562 /* Motorola PowerPC 602.
2563 See the notes under the 403 about 'tcr'. */
2564 static const struct reg registers_602[] =
2570 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2571 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr),
2572 /* 127 */ S(sebr), S(ser), S(sp), S(lt)
2575 /* Motorola/IBM PowerPC 603 or 603e. */
2576 static const struct reg registers_603[] =
2582 /* 119 */ S(hid0), S(hid1), S(iabr), R0,
2583 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1),
2584 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa)
2587 /* Motorola PowerPC 604 or 604e. */
2588 static const struct reg registers_604[] =
2594 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2595 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2),
2596 /* 127 */ S(sia), S(sda)
2599 /* Motorola/IBM PowerPC 750 or 740. */
2600 static const struct reg registers_750[] =
2606 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr),
2607 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2),
2608 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4),
2609 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia),
2610 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr),
2611 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3)
2615 /* Motorola PowerPC 7400. */
2616 static const struct reg registers_7400[] =
2618 /* gpr0-gpr31, fpr0-fpr31 */
2620 /* cr, lr, ctr, xer, fpscr */
2625 /* vr0-vr31, vrsave, vscr */
2627 /* FIXME? Add more registers? */
2630 /* Motorola e500. */
2631 static const struct reg registers_e500[] =
2633 /* 0 .. 31 */ PPC_SPE_GP_REGS,
2634 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS,
2635 /* 64 .. 65 */ R(pc), R(ps),
2636 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS,
2637 /* 71 .. 72 */ R8(acc), S4(spefscr),
2638 /* NOTE: Add new registers here the end of the raw register
2639 list and just before the first pseudo register. */
2640 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS
2643 /* Information about a particular processor variant. */
2647 /* Name of this variant. */
2650 /* English description of the variant. */
2653 /* bfd_arch_info.arch corresponding to variant. */
2654 enum bfd_architecture arch;
2656 /* bfd_arch_info.mach corresponding to variant. */
2659 /* Number of real registers. */
2662 /* Number of pseudo registers. */
2665 /* Number of total registers (the sum of nregs and npregs). */
2668 /* Table of register names; registers[R] is the name of the register
2670 const struct reg *regs;
2673 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2676 num_registers (const struct reg *reg_list, int num_tot_regs)
2681 for (i = 0; i < num_tot_regs; i++)
2682 if (!reg_list[i].pseudo)
2689 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2694 for (i = 0; i < num_tot_regs; i++)
2695 if (reg_list[i].pseudo)
2701 /* Information in this table comes from the following web sites:
2702 IBM: http://www.chips.ibm.com:80/products/embedded/
2703 Motorola: http://www.mot.com/SPS/PowerPC/
2705 I'm sure I've got some of the variant descriptions not quite right.
2706 Please report any inaccuracies you find to GDB's maintainer.
2708 If you add entries to this table, please be sure to allow the new
2709 value as an argument to the --with-cpu flag, in configure.in. */
2711 static struct variant variants[] =
2714 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2715 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2717 {"power", "POWER user-level", bfd_arch_rs6000,
2718 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2720 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2721 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2723 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2724 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2726 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2727 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2729 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2730 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2732 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2733 604, -1, -1, tot_num_registers (registers_604),
2735 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2736 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2738 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2739 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2741 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2742 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2744 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2745 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2747 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2748 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2750 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2751 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2755 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2756 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2758 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2759 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2761 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2762 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2764 {"a35", "PowerPC A35", bfd_arch_powerpc,
2765 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2767 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2768 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2770 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2771 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2774 /* FIXME: I haven't checked the register sets of the following. */
2775 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2776 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2778 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2779 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2781 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2782 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2785 {0, 0, 0, 0, 0, 0, 0, 0}
2788 /* Initialize the number of registers and pseudo registers in each variant. */
2791 init_variants (void)
2795 for (v = variants; v->name; v++)
2798 v->nregs = num_registers (v->regs, v->num_tot_regs);
2799 if (v->npregs == -1)
2800 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2804 /* Return the variant corresponding to architecture ARCH and machine number
2805 MACH. If no such variant exists, return null. */
2807 static const struct variant *
2808 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2810 const struct variant *v;
2812 for (v = variants; v->name; v++)
2813 if (arch == v->arch && mach == v->mach)
2820 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2822 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2823 return print_insn_big_powerpc (memaddr, info);
2825 return print_insn_little_powerpc (memaddr, info);
2829 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2831 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2834 static struct frame_id
2835 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2837 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2839 frame_pc_unwind (next_frame));
2842 struct rs6000_frame_cache
2845 CORE_ADDR initial_sp;
2846 struct trad_frame_saved_reg *saved_regs;
2849 static struct rs6000_frame_cache *
2850 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2852 struct rs6000_frame_cache *cache;
2853 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2854 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2855 struct rs6000_framedata fdata;
2856 int wordsize = tdep->wordsize;
2858 if ((*this_cache) != NULL)
2859 return (*this_cache);
2860 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2861 (*this_cache) = cache;
2862 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2864 skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame),
2867 /* If there were any saved registers, figure out parent's stack
2869 /* The following is true only if the frame doesn't have a call to
2872 if (fdata.saved_fpr == 0
2873 && fdata.saved_gpr == 0
2874 && fdata.saved_vr == 0
2875 && fdata.saved_ev == 0
2876 && fdata.lr_offset == 0
2877 && fdata.cr_offset == 0
2878 && fdata.vr_offset == 0
2879 && fdata.ev_offset == 0)
2880 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2883 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2884 address of the current frame. Things might be easier if the
2885 ->frame pointed to the outer-most address of the frame. In
2886 the mean time, the address of the prev frame is used as the
2887 base address of this frame. */
2888 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2889 if (!fdata.frameless)
2890 /* Frameless really means stackless. */
2891 cache->base = read_memory_addr (cache->base, wordsize);
2893 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
2895 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2896 All fpr's from saved_fpr to fp31 are saved. */
2898 if (fdata.saved_fpr >= 0)
2901 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
2903 /* If skip_prologue says floating-point registers were saved,
2904 but the current architecture has no floating-point registers,
2905 then that's strange. But we have no indices to even record
2906 the addresses under, so we just ignore it. */
2907 if (ppc_floating_point_unit_p (gdbarch))
2908 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
2910 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2915 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2916 All gpr's from saved_gpr to gpr31 are saved. */
2918 if (fdata.saved_gpr >= 0)
2921 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
2922 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
2924 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2925 gpr_addr += wordsize;
2929 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2930 All vr's from saved_vr to vr31 are saved. */
2931 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2933 if (fdata.saved_vr >= 0)
2936 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2937 for (i = fdata.saved_vr; i < 32; i++)
2939 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2940 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2945 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2946 All vr's from saved_ev to ev31 are saved. ????? */
2947 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
2949 if (fdata.saved_ev >= 0)
2952 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
2953 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
2955 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2956 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2957 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2962 /* If != 0, fdata.cr_offset is the offset from the frame that
2964 if (fdata.cr_offset != 0)
2965 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2967 /* If != 0, fdata.lr_offset is the offset from the frame that
2969 if (fdata.lr_offset != 0)
2970 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2971 /* The PC is found in the link register. */
2972 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
2974 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2975 holds the VRSAVE. */
2976 if (fdata.vrsave_offset != 0)
2977 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2979 if (fdata.alloca_reg < 0)
2980 /* If no alloca register used, then fi->frame is the value of the
2981 %sp for this frame, and it is good enough. */
2982 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2984 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
2991 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
2992 struct frame_id *this_id)
2994 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2996 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
3000 rs6000_frame_prev_register (struct frame_info *next_frame,
3002 int regnum, int *optimizedp,
3003 enum lval_type *lvalp, CORE_ADDR *addrp,
3004 int *realnump, void *valuep)
3006 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3008 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3009 optimizedp, lvalp, addrp, realnump, valuep);
3012 static const struct frame_unwind rs6000_frame_unwind =
3015 rs6000_frame_this_id,
3016 rs6000_frame_prev_register
3019 static const struct frame_unwind *
3020 rs6000_frame_sniffer (struct frame_info *next_frame)
3022 return &rs6000_frame_unwind;
3028 rs6000_frame_base_address (struct frame_info *next_frame,
3031 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3033 return info->initial_sp;
3036 static const struct frame_base rs6000_frame_base = {
3037 &rs6000_frame_unwind,
3038 rs6000_frame_base_address,
3039 rs6000_frame_base_address,
3040 rs6000_frame_base_address
3043 static const struct frame_base *
3044 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3046 return &rs6000_frame_base;
3049 /* Initialize the current architecture based on INFO. If possible, re-use an
3050 architecture from ARCHES, which is a list of architectures already created
3051 during this debugging session.
3053 Called e.g. at program startup, when reading a core file, and when reading
3056 static struct gdbarch *
3057 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3059 struct gdbarch *gdbarch;
3060 struct gdbarch_tdep *tdep;
3061 int wordsize, from_xcoff_exec, from_elf_exec, i, off;
3063 const struct variant *v;
3064 enum bfd_architecture arch;
3070 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3071 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3073 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3074 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3076 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3078 /* Check word size. If INFO is from a binary file, infer it from
3079 that, else choose a likely default. */
3080 if (from_xcoff_exec)
3082 if (bfd_xcoff_is_xcoff64 (info.abfd))
3087 else if (from_elf_exec)
3089 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3096 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3097 wordsize = info.bfd_arch_info->bits_per_word /
3098 info.bfd_arch_info->bits_per_byte;
3103 /* Find a candidate among extant architectures. */
3104 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3106 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3108 /* Word size in the various PowerPC bfd_arch_info structs isn't
3109 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3110 separate word size check. */
3111 tdep = gdbarch_tdep (arches->gdbarch);
3112 if (tdep && tdep->wordsize == wordsize)
3113 return arches->gdbarch;
3116 /* None found, create a new architecture from INFO, whose bfd_arch_info
3117 validity depends on the source:
3118 - executable useless
3119 - rs6000_host_arch() good
3121 - "set arch" trust blindly
3122 - GDB startup useless but harmless */
3124 if (!from_xcoff_exec)
3126 arch = info.bfd_arch_info->arch;
3127 mach = info.bfd_arch_info->mach;
3131 arch = bfd_arch_powerpc;
3132 bfd_default_set_arch_mach (&abfd, arch, 0);
3133 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3134 mach = info.bfd_arch_info->mach;
3136 tdep = xmalloc (sizeof (struct gdbarch_tdep));
3137 tdep->wordsize = wordsize;
3139 /* For e500 executables, the apuinfo section is of help here. Such
3140 section contains the identifier and revision number of each
3141 Application-specific Processing Unit that is present on the
3142 chip. The content of the section is determined by the assembler
3143 which looks at each instruction and determines which unit (and
3144 which version of it) can execute it. In our case we just look for
3145 the existance of the section. */
3149 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3152 arch = info.bfd_arch_info->arch;
3153 mach = bfd_mach_ppc_e500;
3154 bfd_default_set_arch_mach (&abfd, arch, mach);
3155 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3159 gdbarch = gdbarch_alloc (&info, tdep);
3161 /* Initialize the number of real and pseudo registers in each variant. */
3164 /* Choose variant. */
3165 v = find_variant_by_arch (arch, mach);
3169 tdep->regs = v->regs;
3171 tdep->ppc_gp0_regnum = 0;
3172 tdep->ppc_toc_regnum = 2;
3173 tdep->ppc_ps_regnum = 65;
3174 tdep->ppc_cr_regnum = 66;
3175 tdep->ppc_lr_regnum = 67;
3176 tdep->ppc_ctr_regnum = 68;
3177 tdep->ppc_xer_regnum = 69;
3178 if (v->mach == bfd_mach_ppc_601)
3179 tdep->ppc_mq_regnum = 124;
3180 else if (arch == bfd_arch_rs6000)
3181 tdep->ppc_mq_regnum = 70;
3183 tdep->ppc_mq_regnum = -1;
3184 tdep->ppc_fp0_regnum = 32;
3185 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70;
3186 tdep->ppc_sr0_regnum = 71;
3187 tdep->ppc_vr0_regnum = -1;
3188 tdep->ppc_vrsave_regnum = -1;
3189 tdep->ppc_ev0_upper_regnum = -1;
3190 tdep->ppc_ev0_regnum = -1;
3191 tdep->ppc_ev31_regnum = -1;
3192 tdep->ppc_acc_regnum = -1;
3193 tdep->ppc_spefscr_regnum = -1;
3195 set_gdbarch_pc_regnum (gdbarch, 64);
3196 set_gdbarch_sp_regnum (gdbarch, 1);
3197 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
3198 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3199 if (sysv_abi && wordsize == 8)
3200 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3201 else if (sysv_abi && wordsize == 4)
3202 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3205 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
3206 set_gdbarch_store_return_value (gdbarch, rs6000_store_return_value);
3209 /* Set lr_frame_offset. */
3211 tdep->lr_frame_offset = 16;
3213 tdep->lr_frame_offset = 4;
3215 tdep->lr_frame_offset = 8;
3217 if (v->arch == bfd_arch_rs6000)
3218 tdep->ppc_sr0_regnum = -1;
3219 else if (v->arch == bfd_arch_powerpc)
3223 tdep->ppc_sr0_regnum = -1;
3224 tdep->ppc_vr0_regnum = 71;
3225 tdep->ppc_vrsave_regnum = 104;
3227 case bfd_mach_ppc_7400:
3228 tdep->ppc_vr0_regnum = 119;
3229 tdep->ppc_vrsave_regnum = 152;
3231 case bfd_mach_ppc_e500:
3232 tdep->ppc_toc_regnum = -1;
3233 tdep->ppc_ev0_upper_regnum = 32;
3234 tdep->ppc_ev0_regnum = 73;
3235 tdep->ppc_ev31_regnum = 104;
3236 tdep->ppc_acc_regnum = 71;
3237 tdep->ppc_spefscr_regnum = 72;
3238 tdep->ppc_fp0_regnum = -1;
3239 tdep->ppc_fpscr_regnum = -1;
3240 tdep->ppc_sr0_regnum = -1;
3241 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3242 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3243 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p);
3246 case bfd_mach_ppc64:
3247 case bfd_mach_ppc_620:
3248 case bfd_mach_ppc_630:
3249 case bfd_mach_ppc_a35:
3250 case bfd_mach_ppc_rs64ii:
3251 case bfd_mach_ppc_rs64iii:
3252 /* These processor's register sets don't have segment registers. */
3253 tdep->ppc_sr0_regnum = -1;
3257 internal_error (__FILE__, __LINE__,
3258 _("rs6000_gdbarch_init: "
3259 "received unexpected BFD 'arch' value"));
3261 /* Sanity check on registers. */
3262 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
3264 /* Select instruction printer. */
3265 if (arch == bfd_arch_rs6000)
3266 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3268 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3270 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
3272 set_gdbarch_num_regs (gdbarch, v->nregs);
3273 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
3274 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3275 set_gdbarch_register_type (gdbarch, rs6000_register_type);
3276 set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p);
3278 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3279 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3280 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3281 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3282 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3283 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3284 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3286 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3288 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3289 set_gdbarch_char_signed (gdbarch, 0);
3291 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3292 if (sysv_abi && wordsize == 8)
3294 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3295 else if (!sysv_abi && wordsize == 4)
3296 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3297 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3298 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3300 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3302 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3303 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3304 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3306 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3307 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3308 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
3309 is correct for the SysV ABI when the wordsize is 8, but I'm also
3310 fairly certain that ppc_sysv_abi_push_arguments() will give even
3311 worse results since it only works for 32-bit code. So, for the moment,
3312 we're better off calling rs6000_push_arguments() since it works for
3313 64-bit code. At some point in the future, this matter needs to be
3315 if (sysv_abi && wordsize == 4)
3316 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3317 else if (sysv_abi && wordsize == 8)
3318 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3320 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3322 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
3324 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3325 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3326 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3328 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3329 for the descriptor and ".FN" for the entry-point -- a user
3330 specifying "break FN" will unexpectedly end up with a breakpoint
3331 on the descriptor and not the function. This architecture method
3332 transforms any breakpoints on descriptors into breakpoints on the
3333 corresponding entry point. */
3334 if (sysv_abi && wordsize == 8)
3335 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3337 /* Not sure on this. FIXMEmgo */
3338 set_gdbarch_frame_args_skip (gdbarch, 8);
3341 set_gdbarch_deprecated_use_struct_convention (gdbarch, rs6000_use_struct_convention);
3345 /* Handle RS/6000 function pointers (which are really function
3347 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3348 rs6000_convert_from_func_ptr_addr);
3351 /* Helpers for function argument information. */
3352 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3354 /* Hook in ABI-specific overrides, if they have been registered. */
3355 gdbarch_init_osabi (info, gdbarch);
3359 case GDB_OSABI_NETBSD_AOUT:
3360 case GDB_OSABI_NETBSD_ELF:
3361 case GDB_OSABI_UNKNOWN:
3362 case GDB_OSABI_LINUX:
3363 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3364 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3365 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3366 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3369 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3371 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3372 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3373 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3374 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3377 if (from_xcoff_exec)
3379 /* NOTE: jimix/2003-06-09: This test should really check for
3380 GDB_OSABI_AIX when that is defined and becomes
3381 available. (Actually, once things are properly split apart,
3382 the test goes away.) */
3383 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
3384 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
3387 init_sim_regno_table (gdbarch);
3393 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
3395 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
3400 /* FIXME: Dump gdbarch_tdep. */
3403 static struct cmd_list_element *info_powerpc_cmdlist = NULL;
3406 rs6000_info_powerpc_command (char *args, int from_tty)
3408 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
3411 /* Initialization code. */
3413 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3416 _initialize_rs6000_tdep (void)
3418 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3419 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
3421 /* Add root prefix command for "info powerpc" commands */
3422 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
3423 _("Various POWERPC info specific commands."),
3424 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);