1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "libbfd.h" /* for bfd_default_set_arch_mach */
41 #include "coff/internal.h" /* for libcoff.h */
42 #include "libcoff.h" /* for xcoff_data */
43 #include "coff/xcoff.h"
48 #include "solib-svr4.h"
51 #include "gdb_assert.h"
54 #include "trad-frame.h"
55 #include "frame-unwind.h"
56 #include "frame-base.h"
58 /* If the kernel has to deliver a signal, it pushes a sigcontext
59 structure on the stack and then calls the signal handler, passing
60 the address of the sigcontext in an argument register. Usually
61 the signal handler doesn't save this register, so we have to
62 access the sigcontext structure via an offset from the signal handler
64 The following constants were determined by experimentation on AIX 3.2. */
65 #define SIG_FRAME_PC_OFFSET 96
66 #define SIG_FRAME_LR_OFFSET 108
67 #define SIG_FRAME_FP_OFFSET 284
69 /* To be used by skip_prologue. */
71 struct rs6000_framedata
73 int offset; /* total size of frame --- the distance
74 by which we decrement sp to allocate
76 int saved_gpr; /* smallest # of saved gpr */
77 int saved_fpr; /* smallest # of saved fpr */
78 int saved_vr; /* smallest # of saved vr */
79 int saved_ev; /* smallest # of saved ev */
80 int alloca_reg; /* alloca register number (frame ptr) */
81 char frameless; /* true if frameless functions. */
82 char nosavedpc; /* true if pc not saved. */
83 int gpr_offset; /* offset of saved gprs from prev sp */
84 int fpr_offset; /* offset of saved fprs from prev sp */
85 int vr_offset; /* offset of saved vrs from prev sp */
86 int ev_offset; /* offset of saved evs from prev sp */
87 int lr_offset; /* offset of saved lr */
88 int cr_offset; /* offset of saved cr */
89 int vrsave_offset; /* offset of saved vrsave register */
92 /* Description of a single register. */
96 char *name; /* name of register */
97 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
98 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
99 unsigned char fpr; /* whether register is floating-point */
100 unsigned char pseudo; /* whether register is pseudo */
103 /* Breakpoint shadows for the single step instructions will be kept here. */
105 static struct sstep_breaks
107 /* Address, or 0 if this is not in use. */
109 /* Shadow contents. */
114 /* Hook for determining the TOC address when calling functions in the
115 inferior under AIX. The initialization code in rs6000-nat.c sets
116 this hook to point to find_toc_address. */
118 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
120 /* Hook to set the current architecture when starting a child process.
121 rs6000-nat.c sets this. */
123 void (*rs6000_set_host_arch_hook) (int) = NULL;
125 /* Static function prototypes */
127 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
129 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
130 struct rs6000_framedata *);
132 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
134 altivec_register_p (int regno)
136 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
137 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
140 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
144 /* Return non-zero if the architecture described by GDBARCH has
145 floating-point registers (f0 --- f31 and fpscr). */
147 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
149 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
151 return (tdep->ppc_fp0_regnum >= 0
152 && tdep->ppc_fpscr_regnum >= 0);
156 /* Register set support functions. */
159 ppc_supply_reg (struct regcache *regcache, int regnum,
160 const char *regs, size_t offset)
162 if (regnum != -1 && offset != -1)
163 regcache_raw_supply (regcache, regnum, regs + offset);
167 ppc_collect_reg (const struct regcache *regcache, int regnum,
168 char *regs, size_t offset)
170 if (regnum != -1 && offset != -1)
171 regcache_raw_collect (regcache, regnum, regs + offset);
174 /* Supply register REGNUM in the general-purpose register set REGSET
175 from the buffer specified by GREGS and LEN to register cache
176 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
179 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
180 int regnum, const void *gregs, size_t len)
182 struct gdbarch *gdbarch = get_regcache_arch (regcache);
183 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
184 const struct ppc_reg_offsets *offsets = regset->descr;
188 for (i = 0, offset = offsets->r0_offset; i < 32; i++, offset += 4)
190 if (regnum == -1 || regnum == i)
191 ppc_supply_reg (regcache, i, gregs, offset);
194 if (regnum == -1 || regnum == PC_REGNUM)
195 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
196 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
197 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
198 gregs, offsets->ps_offset);
199 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
200 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
201 gregs, offsets->cr_offset);
202 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
203 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
204 gregs, offsets->lr_offset);
205 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
206 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
207 gregs, offsets->ctr_offset);
208 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
209 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
210 gregs, offsets->cr_offset);
211 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
212 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
215 /* Supply register REGNUM in the floating-point register set REGSET
216 from the buffer specified by FPREGS and LEN to register cache
217 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
220 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
221 int regnum, const void *fpregs, size_t len)
223 struct gdbarch *gdbarch = get_regcache_arch (regcache);
224 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
225 const struct ppc_reg_offsets *offsets = regset->descr;
229 gdb_assert (ppc_floating_point_unit_p (gdbarch));
231 offset = offsets->f0_offset;
232 for (i = tdep->ppc_fp0_regnum;
233 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
236 if (regnum == -1 || regnum == i)
237 ppc_supply_reg (regcache, i, fpregs, offset);
240 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
241 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
242 fpregs, offsets->fpscr_offset);
245 /* Collect register REGNUM in the general-purpose register set
246 REGSET. from register cache REGCACHE into the buffer specified by
247 GREGS and LEN. If REGNUM is -1, do this for all registers in
251 ppc_collect_gregset (const struct regset *regset,
252 const struct regcache *regcache,
253 int regnum, void *gregs, size_t len)
255 struct gdbarch *gdbarch = get_regcache_arch (regcache);
256 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
257 const struct ppc_reg_offsets *offsets = regset->descr;
261 offset = offsets->r0_offset;
262 for (i = 0; i < 32; i++, offset += 4)
264 if (regnum == -1 || regnum == i)
265 ppc_collect_reg (regcache, i, gregs, offset);
268 if (regnum == -1 || regnum == PC_REGNUM)
269 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
270 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
271 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
272 gregs, offsets->ps_offset);
273 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
274 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
275 gregs, offsets->cr_offset);
276 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
277 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
278 gregs, offsets->lr_offset);
279 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
280 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
281 gregs, offsets->ctr_offset);
282 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
283 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
284 gregs, offsets->xer_offset);
285 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
286 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
287 gregs, offsets->mq_offset);
290 /* Collect register REGNUM in the floating-point register set
291 REGSET. from register cache REGCACHE into the buffer specified by
292 FPREGS and LEN. If REGNUM is -1, do this for all registers in
296 ppc_collect_fpregset (const struct regset *regset,
297 const struct regcache *regcache,
298 int regnum, void *fpregs, size_t len)
300 struct gdbarch *gdbarch = get_regcache_arch (regcache);
301 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
302 const struct ppc_reg_offsets *offsets = regset->descr;
306 gdb_assert (ppc_floating_point_unit_p (gdbarch));
308 offset = offsets->f0_offset;
309 for (i = tdep->ppc_fp0_regnum;
310 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
313 if (regnum == -1 || regnum == i)
314 ppc_collect_reg (regcache, regnum, fpregs, offset);
317 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
318 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
319 fpregs, offsets->fpscr_offset);
323 /* Read a LEN-byte address from debugged memory address MEMADDR. */
326 read_memory_addr (CORE_ADDR memaddr, int len)
328 return read_memory_unsigned_integer (memaddr, len);
332 rs6000_skip_prologue (CORE_ADDR pc)
334 struct rs6000_framedata frame;
335 pc = skip_prologue (pc, 0, &frame);
340 /* Fill in fi->saved_regs */
342 struct frame_extra_info
344 /* Functions calling alloca() change the value of the stack
345 pointer. We need to use initial stack pointer (which is saved in
346 r31 by gcc) in such cases. If a compiler emits traceback table,
347 then we should use the alloca register specified in traceback
349 CORE_ADDR initial_sp; /* initial stack pointer. */
352 /* Get the ith function argument for the current function. */
354 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
358 get_frame_register (frame, 3 + argi, &addr);
362 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
365 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
372 absolute = (int) ((instr >> 1) & 1);
377 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
381 dest = pc + immediate;
385 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
389 dest = pc + immediate;
393 ext_op = (instr >> 1) & 0x3ff;
395 if (ext_op == 16) /* br conditional register */
397 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
399 /* If we are about to return from a signal handler, dest is
400 something like 0x3c90. The current frame is a signal handler
401 caller frame, upon completion of the sigreturn system call
402 execution will return to the saved PC in the frame. */
403 if (dest < TEXT_SEGMENT_BASE)
405 struct frame_info *fi;
407 fi = get_current_frame ();
409 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
410 gdbarch_tdep (current_gdbarch)->wordsize);
414 else if (ext_op == 528) /* br cond to count reg */
416 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
418 /* If we are about to execute a system call, dest is something
419 like 0x22fc or 0x3b00. Upon completion the system call
420 will return to the address in the link register. */
421 if (dest < TEXT_SEGMENT_BASE)
422 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
431 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
435 /* Sequence of bytes for breakpoint instruction. */
437 const static unsigned char *
438 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
440 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
441 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
443 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
444 return big_breakpoint;
446 return little_breakpoint;
450 /* AIX does not support PT_STEP. Simulate it. */
453 rs6000_software_single_step (enum target_signal signal,
454 int insert_breakpoints_p)
458 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
464 if (insert_breakpoints_p)
469 insn = read_memory_integer (loc, 4);
471 breaks[0] = loc + breakp_sz;
473 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
475 /* Don't put two breakpoints on the same address. */
476 if (breaks[1] == breaks[0])
479 stepBreaks[1].address = 0;
481 for (ii = 0; ii < 2; ++ii)
484 /* ignore invalid breakpoint. */
485 if (breaks[ii] == -1)
487 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
488 stepBreaks[ii].address = breaks[ii];
495 /* remove step breakpoints. */
496 for (ii = 0; ii < 2; ++ii)
497 if (stepBreaks[ii].address != 0)
498 target_remove_breakpoint (stepBreaks[ii].address,
499 stepBreaks[ii].data);
501 errno = 0; /* FIXME, don't ignore errors! */
502 /* What errors? {read,write}_memory call error(). */
506 /* return pc value after skipping a function prologue and also return
507 information about a function frame.
509 in struct rs6000_framedata fdata:
510 - frameless is TRUE, if function does not have a frame.
511 - nosavedpc is TRUE, if function does not save %pc value in its frame.
512 - offset is the initial size of this stack frame --- the amount by
513 which we decrement the sp to allocate the frame.
514 - saved_gpr is the number of the first saved gpr.
515 - saved_fpr is the number of the first saved fpr.
516 - saved_vr is the number of the first saved vr.
517 - saved_ev is the number of the first saved ev.
518 - alloca_reg is the number of the register used for alloca() handling.
520 - gpr_offset is the offset of the first saved gpr from the previous frame.
521 - fpr_offset is the offset of the first saved fpr from the previous frame.
522 - vr_offset is the offset of the first saved vr from the previous frame.
523 - ev_offset is the offset of the first saved ev from the previous frame.
524 - lr_offset is the offset of the saved lr
525 - cr_offset is the offset of the saved cr
526 - vrsave_offset is the offset of the saved vrsave register
529 #define SIGNED_SHORT(x) \
530 ((sizeof (short) == 2) \
531 ? ((int)(short)(x)) \
532 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
534 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
536 /* Limit the number of skipped non-prologue instructions, as the examining
537 of the prologue is expensive. */
538 static int max_skip_non_prologue_insns = 10;
540 /* Given PC representing the starting address of a function, and
541 LIM_PC which is the (sloppy) limit to which to scan when looking
542 for a prologue, attempt to further refine this limit by using
543 the line data in the symbol table. If successful, a better guess
544 on where the prologue ends is returned, otherwise the previous
545 value of lim_pc is returned. */
547 /* FIXME: cagney/2004-02-14: This function and logic have largely been
548 superseded by skip_prologue_using_sal. */
551 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
553 struct symtab_and_line prologue_sal;
555 prologue_sal = find_pc_line (pc, 0);
556 if (prologue_sal.line != 0)
559 CORE_ADDR addr = prologue_sal.end;
561 /* Handle the case in which compiler's optimizer/scheduler
562 has moved instructions into the prologue. We scan ahead
563 in the function looking for address ranges whose corresponding
564 line number is less than or equal to the first one that we
565 found for the function. (It can be less than when the
566 scheduler puts a body instruction before the first prologue
568 for (i = 2 * max_skip_non_prologue_insns;
569 i > 0 && (lim_pc == 0 || addr < lim_pc);
572 struct symtab_and_line sal;
574 sal = find_pc_line (addr, 0);
577 if (sal.line <= prologue_sal.line
578 && sal.symtab == prologue_sal.symtab)
585 if (lim_pc == 0 || prologue_sal.end < lim_pc)
586 lim_pc = prologue_sal.end;
593 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
595 CORE_ADDR orig_pc = pc;
596 CORE_ADDR last_prologue_pc = pc;
597 CORE_ADDR li_found_pc = 0;
601 long vr_saved_offset = 0;
610 int minimal_toc_loaded = 0;
611 int prev_insn_was_prologue_insn = 1;
612 int num_skip_non_prologue_insns = 0;
613 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
614 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
616 /* Attempt to find the end of the prologue when no limit is specified.
617 Note that refine_prologue_limit() has been written so that it may
618 be used to "refine" the limits of non-zero PC values too, but this
619 is only safe if we 1) trust the line information provided by the
620 compiler and 2) iterate enough to actually find the end of the
623 It may become a good idea at some point (for both performance and
624 accuracy) to unconditionally call refine_prologue_limit(). But,
625 until we can make a clear determination that this is beneficial,
626 we'll play it safe and only use it to obtain a limit when none
627 has been specified. */
629 lim_pc = refine_prologue_limit (pc, lim_pc);
631 memset (fdata, 0, sizeof (struct rs6000_framedata));
632 fdata->saved_gpr = -1;
633 fdata->saved_fpr = -1;
634 fdata->saved_vr = -1;
635 fdata->saved_ev = -1;
636 fdata->alloca_reg = -1;
637 fdata->frameless = 1;
638 fdata->nosavedpc = 1;
642 /* Sometimes it isn't clear if an instruction is a prologue
643 instruction or not. When we encounter one of these ambiguous
644 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
645 Otherwise, we'll assume that it really is a prologue instruction. */
646 if (prev_insn_was_prologue_insn)
647 last_prologue_pc = pc;
649 /* Stop scanning if we've hit the limit. */
650 if (lim_pc != 0 && pc >= lim_pc)
653 prev_insn_was_prologue_insn = 1;
655 /* Fetch the instruction and convert it to an integer. */
656 if (target_read_memory (pc, buf, 4))
658 op = extract_signed_integer (buf, 4);
660 if ((op & 0xfc1fffff) == 0x7c0802a6)
662 /* Since shared library / PIC code, which needs to get its
663 address at runtime, can appear to save more than one link
677 remember just the first one, but skip over additional
680 lr_reg = (op & 0x03e00000);
683 else if ((op & 0xfc1fffff) == 0x7c000026)
685 cr_reg = (op & 0x03e00000);
689 else if ((op & 0xfc1f0000) == 0xd8010000)
690 { /* stfd Rx,NUM(r1) */
691 reg = GET_SRC_REG (op);
692 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
694 fdata->saved_fpr = reg;
695 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
700 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
701 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
702 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
703 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
706 reg = GET_SRC_REG (op);
707 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
709 fdata->saved_gpr = reg;
710 if ((op & 0xfc1f0003) == 0xf8010000)
712 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
717 else if ((op & 0xffff0000) == 0x60000000)
720 /* Allow nops in the prologue, but do not consider them to
721 be part of the prologue unless followed by other prologue
723 prev_insn_was_prologue_insn = 0;
727 else if ((op & 0xffff0000) == 0x3c000000)
728 { /* addis 0,0,NUM, used
730 fdata->offset = (op & 0x0000ffff) << 16;
731 fdata->frameless = 0;
735 else if ((op & 0xffff0000) == 0x60000000)
736 { /* ori 0,0,NUM, 2nd ha
737 lf of >= 32k frames */
738 fdata->offset |= (op & 0x0000ffff);
739 fdata->frameless = 0;
743 else if (lr_reg != -1 &&
744 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
745 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
746 /* stw Rx, NUM(r1) */
747 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
748 /* stwu Rx, NUM(r1) */
749 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
750 { /* where Rx == lr */
751 fdata->lr_offset = offset;
752 fdata->nosavedpc = 0;
754 if ((op & 0xfc000003) == 0xf8000000 || /* std */
755 (op & 0xfc000000) == 0x90000000) /* stw */
757 /* Does not update r1, so add displacement to lr_offset. */
758 fdata->lr_offset += SIGNED_SHORT (op);
763 else if (cr_reg != -1 &&
764 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
765 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
766 /* stw Rx, NUM(r1) */
767 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
768 /* stwu Rx, NUM(r1) */
769 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
770 { /* where Rx == cr */
771 fdata->cr_offset = offset;
773 if ((op & 0xfc000003) == 0xf8000000 ||
774 (op & 0xfc000000) == 0x90000000)
776 /* Does not update r1, so add displacement to cr_offset. */
777 fdata->cr_offset += SIGNED_SHORT (op);
782 else if (op == 0x48000005)
788 else if (op == 0x48000004)
793 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
794 in V.4 -mminimal-toc */
795 (op & 0xffff0000) == 0x3bde0000)
796 { /* addi 30,30,foo@l */
800 else if ((op & 0xfc000001) == 0x48000001)
804 fdata->frameless = 0;
805 /* Don't skip over the subroutine call if it is not within
806 the first three instructions of the prologue. */
807 if ((pc - orig_pc) > 8)
810 op = read_memory_integer (pc + 4, 4);
812 /* At this point, make sure this is not a trampoline
813 function (a function that simply calls another functions,
814 and nothing else). If the next is not a nop, this branch
815 was part of the function prologue. */
817 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
818 break; /* don't skip over
823 /* update stack pointer */
824 else if ((op & 0xfc1f0000) == 0x94010000)
825 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
826 fdata->frameless = 0;
827 fdata->offset = SIGNED_SHORT (op);
828 offset = fdata->offset;
831 else if ((op & 0xfc1f016a) == 0x7c01016e)
832 { /* stwux rX,r1,rY */
833 /* no way to figure out what r1 is going to be */
834 fdata->frameless = 0;
835 offset = fdata->offset;
838 else if ((op & 0xfc1f0003) == 0xf8010001)
839 { /* stdu rX,NUM(r1) */
840 fdata->frameless = 0;
841 fdata->offset = SIGNED_SHORT (op & ~3UL);
842 offset = fdata->offset;
845 else if ((op & 0xfc1f016a) == 0x7c01016a)
846 { /* stdux rX,r1,rY */
847 /* no way to figure out what r1 is going to be */
848 fdata->frameless = 0;
849 offset = fdata->offset;
852 /* Load up minimal toc pointer */
853 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
854 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
855 && !minimal_toc_loaded)
857 minimal_toc_loaded = 1;
860 /* move parameters from argument registers to local variable
863 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
864 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
865 (((op >> 21) & 31) <= 10) &&
866 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
870 /* store parameters in stack */
872 /* Move parameters from argument registers to temporary register. */
873 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
874 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
875 (((op >> 21) & 31) <= 10) &&
876 (((op >> 16) & 31) == 0)) /* Rx: scratch register r0 */
880 else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
881 (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
882 (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
886 /* store parameters in stack via frame pointer */
889 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
890 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
891 (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r31) */
892 (op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
896 /* Set up frame pointer */
898 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
901 fdata->frameless = 0;
903 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
906 /* Another way to set up the frame pointer. */
908 else if ((op & 0xfc1fffff) == 0x38010000)
909 { /* addi rX, r1, 0x0 */
910 fdata->frameless = 0;
912 fdata->alloca_reg = (tdep->ppc_gp0_regnum
913 + ((op & ~0x38010000) >> 21));
916 /* AltiVec related instructions. */
917 /* Store the vrsave register (spr 256) in another register for
918 later manipulation, or load a register into the vrsave
919 register. 2 instructions are used: mfvrsave and
920 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
921 and mtspr SPR256, Rn. */
922 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
923 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
924 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
926 vrsave_reg = GET_SRC_REG (op);
929 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
933 /* Store the register where vrsave was saved to onto the stack:
934 rS is the register where vrsave was stored in a previous
936 /* 100100 sssss 00001 dddddddd dddddddd */
937 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
939 if (vrsave_reg == GET_SRC_REG (op))
941 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
946 /* Compute the new value of vrsave, by modifying the register
947 where vrsave was saved to. */
948 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
949 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
953 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
954 in a pair of insns to save the vector registers on the
956 /* 001110 00000 00000 iiii iiii iiii iiii */
957 /* 001110 01110 00000 iiii iiii iiii iiii */
958 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
959 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
962 vr_saved_offset = SIGNED_SHORT (op);
964 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
965 /* 011111 sssss 11111 00000 00111001110 */
966 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
968 if (pc == (li_found_pc + 4))
970 vr_reg = GET_SRC_REG (op);
971 /* If this is the first vector reg to be saved, or if
972 it has a lower number than others previously seen,
973 reupdate the frame info. */
974 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
976 fdata->saved_vr = vr_reg;
977 fdata->vr_offset = vr_saved_offset + offset;
979 vr_saved_offset = -1;
984 /* End AltiVec related instructions. */
986 /* Start BookE related instructions. */
987 /* Store gen register S at (r31+uimm).
988 Any register less than r13 is volatile, so we don't care. */
989 /* 000100 sssss 11111 iiiii 01100100001 */
990 else if (arch_info->mach == bfd_mach_ppc_e500
991 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
993 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
996 ev_reg = GET_SRC_REG (op);
997 imm = (op >> 11) & 0x1f;
999 /* If this is the first vector reg to be saved, or if
1000 it has a lower number than others previously seen,
1001 reupdate the frame info. */
1002 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1004 fdata->saved_ev = ev_reg;
1005 fdata->ev_offset = ev_offset + offset;
1010 /* Store gen register rS at (r1+rB). */
1011 /* 000100 sssss 00001 bbbbb 01100100000 */
1012 else if (arch_info->mach == bfd_mach_ppc_e500
1013 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1015 if (pc == (li_found_pc + 4))
1017 ev_reg = GET_SRC_REG (op);
1018 /* If this is the first vector reg to be saved, or if
1019 it has a lower number than others previously seen,
1020 reupdate the frame info. */
1021 /* We know the contents of rB from the previous instruction. */
1022 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1024 fdata->saved_ev = ev_reg;
1025 fdata->ev_offset = vr_saved_offset + offset;
1027 vr_saved_offset = -1;
1033 /* Store gen register r31 at (rA+uimm). */
1034 /* 000100 11111 aaaaa iiiii 01100100001 */
1035 else if (arch_info->mach == bfd_mach_ppc_e500
1036 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1038 /* Wwe know that the source register is 31 already, but
1039 it can't hurt to compute it. */
1040 ev_reg = GET_SRC_REG (op);
1041 ev_offset = ((op >> 11) & 0x1f) * 8;
1042 /* If this is the first vector reg to be saved, or if
1043 it has a lower number than others previously seen,
1044 reupdate the frame info. */
1045 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1047 fdata->saved_ev = ev_reg;
1048 fdata->ev_offset = ev_offset + offset;
1053 /* Store gen register S at (r31+r0).
1054 Store param on stack when offset from SP bigger than 4 bytes. */
1055 /* 000100 sssss 11111 00000 01100100000 */
1056 else if (arch_info->mach == bfd_mach_ppc_e500
1057 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1059 if (pc == (li_found_pc + 4))
1061 if ((op & 0x03e00000) >= 0x01a00000)
1063 ev_reg = GET_SRC_REG (op);
1064 /* If this is the first vector reg to be saved, or if
1065 it has a lower number than others previously seen,
1066 reupdate the frame info. */
1067 /* We know the contents of r0 from the previous
1069 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1071 fdata->saved_ev = ev_reg;
1072 fdata->ev_offset = vr_saved_offset + offset;
1076 vr_saved_offset = -1;
1081 /* End BookE related instructions. */
1085 /* Not a recognized prologue instruction.
1086 Handle optimizer code motions into the prologue by continuing
1087 the search if we have no valid frame yet or if the return
1088 address is not yet saved in the frame. */
1089 if (fdata->frameless == 0
1090 && (lr_reg == -1 || fdata->nosavedpc == 0))
1093 if (op == 0x4e800020 /* blr */
1094 || op == 0x4e800420) /* bctr */
1095 /* Do not scan past epilogue in frameless functions or
1098 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1099 /* Never skip branches. */
1102 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1103 /* Do not scan too many insns, scanning insns is expensive with
1107 /* Continue scanning. */
1108 prev_insn_was_prologue_insn = 0;
1114 /* I have problems with skipping over __main() that I need to address
1115 * sometime. Previously, I used to use misc_function_vector which
1116 * didn't work as well as I wanted to be. -MGO */
1118 /* If the first thing after skipping a prolog is a branch to a function,
1119 this might be a call to an initializer in main(), introduced by gcc2.
1120 We'd like to skip over it as well. Fortunately, xlc does some extra
1121 work before calling a function right after a prologue, thus we can
1122 single out such gcc2 behaviour. */
1125 if ((op & 0xfc000001) == 0x48000001)
1126 { /* bl foo, an initializer function? */
1127 op = read_memory_integer (pc + 4, 4);
1129 if (op == 0x4def7b82)
1130 { /* cror 0xf, 0xf, 0xf (nop) */
1132 /* Check and see if we are in main. If so, skip over this
1133 initializer function as well. */
1135 tmp = find_pc_misc_function (pc);
1137 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1143 fdata->offset = -fdata->offset;
1144 return last_prologue_pc;
1148 /*************************************************************************
1149 Support for creating pushing a dummy frame into the stack, and popping
1151 *************************************************************************/
1154 /* All the ABI's require 16 byte alignment. */
1156 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1158 return (addr & -16);
1161 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1162 the first eight words of the argument list (that might be less than
1163 eight parameters if some parameters occupy more than one word) are
1164 passed in r3..r10 registers. float and double parameters are
1165 passed in fpr's, in addition to that. Rest of the parameters if any
1166 are passed in user stack. There might be cases in which half of the
1167 parameter is copied into registers, the other half is pushed into
1170 Stack must be aligned on 64-bit boundaries when synthesizing
1173 If the function is returning a structure, then the return address is passed
1174 in r3, then the first 7 words of the parameters can be passed in registers,
1175 starting from r4. */
1178 rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1179 struct regcache *regcache, CORE_ADDR bp_addr,
1180 int nargs, struct value **args, CORE_ADDR sp,
1181 int struct_return, CORE_ADDR struct_addr)
1183 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1186 int argno; /* current argument number */
1187 int argbytes; /* current argument byte */
1188 char tmp_buffer[50];
1189 int f_argno = 0; /* current floating point argno */
1190 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1192 struct value *arg = 0;
1197 /* The calling convention this function implements assumes the
1198 processor has floating-point registers. We shouldn't be using it
1199 on PPC variants that lack them. */
1200 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1202 /* The first eight words of ther arguments are passed in registers.
1203 Copy them appropriately. */
1206 /* If the function is returning a `struct', then the first word
1207 (which will be passed in r3) is used for struct return address.
1208 In that case we should advance one word and start from r4
1209 register to copy parameters. */
1212 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1218 effectively indirect call... gcc does...
1220 return_val example( float, int);
1223 float in fp0, int in r3
1224 offset of stack on overflow 8/16
1225 for varargs, must go by type.
1227 float in r3&r4, int in r5
1228 offset of stack on overflow different
1230 return in r3 or f0. If no float, must study how gcc emulates floats;
1231 pay attention to arg promotion.
1232 User may have to cast\args to handle promotion correctly
1233 since gdb won't know if prototype supplied or not.
1236 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1238 int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3);
1241 type = check_typedef (VALUE_TYPE (arg));
1242 len = TYPE_LENGTH (type);
1244 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1247 /* Floating point arguments are passed in fpr's, as well as gpr's.
1248 There are 13 fpr's reserved for passing parameters. At this point
1249 there is no way we would run out of them. */
1253 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
1255 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE
1256 (tdep->ppc_fp0_regnum + 1 + f_argno)],
1257 VALUE_CONTENTS (arg),
1265 /* Argument takes more than one register. */
1266 while (argbytes < len)
1268 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0,
1270 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)],
1271 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1272 (len - argbytes) > reg_size
1273 ? reg_size : len - argbytes);
1274 ++ii, argbytes += reg_size;
1277 goto ran_out_of_registers_for_arguments;
1284 /* Argument can fit in one register. No problem. */
1285 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1286 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size);
1287 memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj,
1288 VALUE_CONTENTS (arg), len);
1293 ran_out_of_registers_for_arguments:
1295 saved_sp = read_sp ();
1297 /* Location for 8 parameters are always reserved. */
1300 /* Another six words for back chain, TOC register, link register, etc. */
1303 /* Stack pointer must be quadword aligned. */
1306 /* If there are more arguments, allocate space for them in
1307 the stack, then push them starting from the ninth one. */
1309 if ((argno < nargs) || argbytes)
1315 space += ((len - argbytes + 3) & -4);
1321 for (; jj < nargs; ++jj)
1323 struct value *val = args[jj];
1324 space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
1327 /* Add location required for the rest of the parameters. */
1328 space = (space + 15) & -16;
1331 /* This is another instance we need to be concerned about
1332 securing our stack space. If we write anything underneath %sp
1333 (r1), we might conflict with the kernel who thinks he is free
1334 to use this area. So, update %sp first before doing anything
1337 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1339 /* If the last argument copied into the registers didn't fit there
1340 completely, push the rest of it into stack. */
1344 write_memory (sp + 24 + (ii * 4),
1345 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1348 ii += ((len - argbytes + 3) & -4) / 4;
1351 /* Push the rest of the arguments into stack. */
1352 for (; argno < nargs; ++argno)
1356 type = check_typedef (VALUE_TYPE (arg));
1357 len = TYPE_LENGTH (type);
1360 /* Float types should be passed in fpr's, as well as in the
1362 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1367 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
1369 memcpy (&(deprecated_registers
1370 [DEPRECATED_REGISTER_BYTE
1371 (tdep->ppc_fp0_regnum + 1 + f_argno)]),
1372 VALUE_CONTENTS (arg),
1377 write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len);
1378 ii += ((len + 3) & -4) / 4;
1382 /* Set the stack pointer. According to the ABI, the SP is meant to
1383 be set _before_ the corresponding stack space is used. On AIX,
1384 this even applies when the target has been completely stopped!
1385 Not doing this can lead to conflicts with the kernel which thinks
1386 that it still has control over this not-yet-allocated stack
1388 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1390 /* Set back chain properly. */
1391 store_unsigned_integer (tmp_buffer, 4, saved_sp);
1392 write_memory (sp, tmp_buffer, 4);
1394 /* Point the inferior function call's return address at the dummy's
1396 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1398 /* Set the TOC register, get the value from the objfile reader
1399 which, in turn, gets it from the VMAP table. */
1400 if (rs6000_find_toc_address_hook != NULL)
1402 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1403 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1406 target_store_registers (-1);
1410 /* PowerOpen always puts structures in memory. Vectors, which were
1411 added later, do get returned in a register though. */
1414 rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1416 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1417 && TYPE_VECTOR (value_type))
1423 rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
1426 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1428 /* The calling convention this function implements assumes the
1429 processor has floating-point registers. We shouldn't be using it
1430 on PPC variants that lack them. */
1431 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1433 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1436 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1437 We need to truncate the return value into float size (4 byte) if
1440 convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
1441 (tdep->ppc_fp0_regnum + 1)],
1442 builtin_type_double,
1446 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1447 && TYPE_LENGTH (valtype) == 16
1448 && TYPE_VECTOR (valtype))
1450 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1451 TYPE_LENGTH (valtype));
1455 /* return value is copied starting from r3. */
1456 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1457 && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3))
1458 offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype);
1461 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
1462 TYPE_LENGTH (valtype));
1466 /* Return whether handle_inferior_event() should proceed through code
1467 starting at PC in function NAME when stepping.
1469 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1470 handle memory references that are too distant to fit in instructions
1471 generated by the compiler. For example, if 'foo' in the following
1476 is greater than 32767, the linker might replace the lwz with a branch to
1477 somewhere in @FIX1 that does the load in 2 instructions and then branches
1478 back to where execution should continue.
1480 GDB should silently step over @FIX code, just like AIX dbx does.
1481 Unfortunately, the linker uses the "b" instruction for the branches,
1482 meaning that the link register doesn't get set. Therefore, GDB's usual
1483 step_over_function() mechanism won't work.
1485 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1486 in handle_inferior_event() to skip past @FIX code. */
1489 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1491 return name && !strncmp (name, "@FIX", 4);
1494 /* Skip code that the user doesn't want to see when stepping:
1496 1. Indirect function calls use a piece of trampoline code to do context
1497 switching, i.e. to set the new TOC table. Skip such code if we are on
1498 its first instruction (as when we have single-stepped to here).
1500 2. Skip shared library trampoline code (which is different from
1501 indirect function call trampolines).
1503 3. Skip bigtoc fixup code.
1505 Result is desired PC to step until, or NULL if we are not in
1506 code that should be skipped. */
1509 rs6000_skip_trampoline_code (CORE_ADDR pc)
1511 unsigned int ii, op;
1513 CORE_ADDR solib_target_pc;
1514 struct minimal_symbol *msymbol;
1516 static unsigned trampoline_code[] =
1518 0x800b0000, /* l r0,0x0(r11) */
1519 0x90410014, /* st r2,0x14(r1) */
1520 0x7c0903a6, /* mtctr r0 */
1521 0x804b0004, /* l r2,0x4(r11) */
1522 0x816b0008, /* l r11,0x8(r11) */
1523 0x4e800420, /* bctr */
1524 0x4e800020, /* br */
1528 /* Check for bigtoc fixup code. */
1529 msymbol = lookup_minimal_symbol_by_pc (pc);
1530 if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol)))
1532 /* Double-check that the third instruction from PC is relative "b". */
1533 op = read_memory_integer (pc + 8, 4);
1534 if ((op & 0xfc000003) == 0x48000000)
1536 /* Extract bits 6-29 as a signed 24-bit relative word address and
1537 add it to the containing PC. */
1538 rel = ((int)(op << 6) >> 6);
1539 return pc + 8 + rel;
1543 /* If pc is in a shared library trampoline, return its target. */
1544 solib_target_pc = find_solib_trampoline_target (pc);
1545 if (solib_target_pc)
1546 return solib_target_pc;
1548 for (ii = 0; trampoline_code[ii]; ++ii)
1550 op = read_memory_integer (pc + (ii * 4), 4);
1551 if (op != trampoline_code[ii])
1554 ii = read_register (11); /* r11 holds destination addr */
1555 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1559 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1560 isn't available with that word size, return 0. */
1563 regsize (const struct reg *reg, int wordsize)
1565 return wordsize == 8 ? reg->sz64 : reg->sz32;
1568 /* Return the name of register number N, or null if no such register exists
1569 in the current architecture. */
1572 rs6000_register_name (int n)
1574 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1575 const struct reg *reg = tdep->regs + n;
1577 if (!regsize (reg, tdep->wordsize))
1582 /* Index within `registers' of the first byte of the space for
1586 rs6000_register_byte (int n)
1588 return gdbarch_tdep (current_gdbarch)->regoff[n];
1591 /* Return the number of bytes of storage in the actual machine representation
1592 for register N if that register is available, else return 0. */
1595 rs6000_register_raw_size (int n)
1597 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1598 const struct reg *reg = tdep->regs + n;
1599 return regsize (reg, tdep->wordsize);
1602 /* Return the GDB type object for the "standard" data type
1603 of data in register N. */
1605 static struct type *
1606 rs6000_register_virtual_type (int n)
1608 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1609 const struct reg *reg = tdep->regs + n;
1612 return builtin_type_double;
1615 int size = regsize (reg, tdep->wordsize);
1619 return builtin_type_int0;
1621 return builtin_type_uint32;
1623 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1624 return builtin_type_vec64;
1626 return builtin_type_uint64;
1629 return builtin_type_vec128;
1632 internal_error (__FILE__, __LINE__, "Register %d size %d unknown",
1638 /* Return whether register N requires conversion when moving from raw format
1641 The register format for RS/6000 floating point registers is always
1642 double, we need a conversion if the memory format is float. */
1645 rs6000_register_convertible (int n)
1647 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n;
1651 /* Convert data from raw format for register N in buffer FROM
1652 to virtual format with type TYPE in buffer TO. */
1655 rs6000_register_convert_to_virtual (int n, struct type *type,
1656 char *from, char *to)
1658 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n))
1660 double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n));
1661 deprecated_store_floating (to, TYPE_LENGTH (type), val);
1664 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n));
1667 /* Convert data from virtual format with type TYPE in buffer FROM
1668 to raw format for register N in buffer TO. */
1671 rs6000_register_convert_to_raw (struct type *type, int n,
1672 const char *from, char *to)
1674 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n))
1676 double val = deprecated_extract_floating (from, TYPE_LENGTH (type));
1677 deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val);
1680 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n));
1684 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1685 int reg_nr, void *buffer)
1689 char temp_buffer[MAX_REGISTER_SIZE];
1690 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1692 if (reg_nr >= tdep->ppc_gp0_regnum
1693 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
1695 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1697 /* Build the value in the provided buffer. */
1698 /* Read the raw register of which this one is the lower portion. */
1699 regcache_raw_read (regcache, base_regnum, temp_buffer);
1700 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1702 memcpy ((char *) buffer, temp_buffer + offset, 4);
1707 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1708 int reg_nr, const void *buffer)
1712 char temp_buffer[MAX_REGISTER_SIZE];
1713 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1715 if (reg_nr >= tdep->ppc_gp0_regnum
1716 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
1718 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1719 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1720 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1723 /* Let's read the value of the base register into a temporary
1724 buffer, so that overwriting the last four bytes with the new
1725 value of the pseudo will leave the upper 4 bytes unchanged. */
1726 regcache_raw_read (regcache, base_regnum, temp_buffer);
1728 /* Write as an 8 byte quantity. */
1729 memcpy (temp_buffer + offset, (char *) buffer, 4);
1730 regcache_raw_write (regcache, base_regnum, temp_buffer);
1734 /* Convert a dbx stab or Dwarf 2 register number (from `r'
1735 declaration) to a gdb REGNUM. */
1737 rs6000_dwarf2_stab_reg_to_regnum (int num)
1739 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1741 if (0 <= num && num <= 31)
1742 return tdep->ppc_gp0_regnum + num;
1743 else if (32 <= num && num <= 63)
1744 /* FIXME: jimb/2004-05-05: What should we do when the debug info
1745 specifies registers the architecture doesn't have? Our
1746 callers don't check the value we return. */
1747 return tdep->ppc_fp0_regnum + (num - 32);
1748 else if (1200 <= num && num < 1200 + 32)
1749 return tdep->ppc_ev0_regnum + (num - 1200);
1754 return tdep->ppc_mq_regnum;
1756 return tdep->ppc_lr_regnum;
1758 return tdep->ppc_ctr_regnum;
1760 return tdep->ppc_xer_regnum;
1762 return tdep->ppc_vrsave_regnum;
1767 /* FIXME: jimb/2004-03-28: Doesn't something need to be done here
1768 for the Altivec registers, too?
1770 Looking at GCC, the headers in config/rs6000 never define a
1771 DBX_REGISTER_NUMBER macro, so the debug info uses the same
1772 numbers GCC does internally. Then, looking at the REGISTER_NAMES
1773 macro defined in config/rs6000/rs6000.h, it seems that GCC gives
1774 v0 -- v31 the numbers 77 -- 108. But we number them 119 -- 150.
1776 I don't have a way to test this ready to hand, but I noticed it
1777 and thought I should include a note. */
1781 rs6000_store_return_value (struct type *type, char *valbuf)
1783 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1785 /* The calling convention this function implements assumes the
1786 processor has floating-point registers. We shouldn't be using it
1787 on PPC variants that lack them. */
1788 gdb_assert (ppc_floating_point_unit_p (current_gdbarch));
1790 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1792 /* Floating point values are returned starting from FPR1 and up.
1793 Say a double_double_double type could be returned in
1794 FPR1/FPR2/FPR3 triple. */
1796 deprecated_write_register_bytes
1797 (DEPRECATED_REGISTER_BYTE (tdep->ppc_fp0_regnum + 1),
1799 TYPE_LENGTH (type));
1800 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1802 if (TYPE_LENGTH (type) == 16
1803 && TYPE_VECTOR (type))
1804 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1805 valbuf, TYPE_LENGTH (type));
1808 /* Everything else is returned in GPR3 and up. */
1809 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3),
1810 valbuf, TYPE_LENGTH (type));
1813 /* Extract from an array REGBUF containing the (raw) register state
1814 the address in which a function should return its structure value,
1815 as a CORE_ADDR (or an expression that can be used as one). */
1818 rs6000_extract_struct_value_address (struct regcache *regcache)
1820 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
1821 function call GDB knows the address of the struct return value
1822 and hence, should not need to call this function. Unfortunately,
1823 the current call_function_by_hand() code only saves the most
1824 recent struct address leading to occasional calls. The code
1825 should instead maintain a stack of such addresses (in the dummy
1827 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
1828 really got no idea where the return value is being stored. While
1829 r3, on function entry, contained the address it will have since
1830 been reused (scratch) and hence wouldn't be valid */
1834 /* Hook called when a new child process is started. */
1837 rs6000_create_inferior (int pid)
1839 if (rs6000_set_host_arch_hook)
1840 rs6000_set_host_arch_hook (pid);
1843 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
1845 Usually a function pointer's representation is simply the address
1846 of the function. On the RS/6000 however, a function pointer is
1847 represented by a pointer to a TOC entry. This TOC entry contains
1848 three words, the first word is the address of the function, the
1849 second word is the TOC pointer (r2), and the third word is the
1850 static chain value. Throughout GDB it is currently assumed that a
1851 function pointer contains the address of the function, which is not
1852 easy to fix. In addition, the conversion of a function address to
1853 a function pointer would require allocation of a TOC entry in the
1854 inferior's memory space, with all its drawbacks. To be able to
1855 call C++ virtual methods in the inferior (which are called via
1856 function pointers), find_function_addr uses this function to get the
1857 function address from a function pointer. */
1859 /* Return real function address if ADDR (a function pointer) is in the data
1860 space and is therefore a special function pointer. */
1863 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
1865 struct target_ops *targ)
1867 struct obj_section *s;
1869 s = find_pc_section (addr);
1870 if (s && s->the_bfd_section->flags & SEC_CODE)
1873 /* ADDR is in the data space, so it's a special function pointer. */
1874 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
1878 /* Handling the various POWER/PowerPC variants. */
1881 /* The arrays here called registers_MUMBLE hold information about available
1884 For each family of PPC variants, I've tried to isolate out the
1885 common registers and put them up front, so that as long as you get
1886 the general family right, GDB will correctly identify the registers
1887 common to that family. The common register sets are:
1889 For the 60x family: hid0 hid1 iabr dabr pir
1891 For the 505 and 860 family: eie eid nri
1893 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
1894 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
1897 Most of these register groups aren't anything formal. I arrived at
1898 them by looking at the registers that occurred in more than one
1901 Note: kevinb/2002-04-30: Support for the fpscr register was added
1902 during April, 2002. Slot 70 is being used for PowerPC and slot 71
1903 for Power. For PowerPC, slot 70 was unused and was already in the
1904 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
1905 slot 70 was being used for "mq", so the next available slot (71)
1906 was chosen. It would have been nice to be able to make the
1907 register numbers the same across processor cores, but this wasn't
1908 possible without either 1) renumbering some registers for some
1909 processors or 2) assigning fpscr to a really high slot that's
1910 larger than any current register number. Doing (1) is bad because
1911 existing stubs would break. Doing (2) is undesirable because it
1912 would introduce a really large gap between fpscr and the rest of
1913 the registers for most processors. */
1915 /* Convenience macros for populating register arrays. */
1917 /* Within another macro, convert S to a string. */
1921 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
1922 and 64 bits on 64-bit systems. */
1923 #define R(name) { STR(name), 4, 8, 0, 0 }
1925 /* Return a struct reg defining register NAME that's 32 bits on all
1927 #define R4(name) { STR(name), 4, 4, 0, 0 }
1929 /* Return a struct reg defining register NAME that's 64 bits on all
1931 #define R8(name) { STR(name), 8, 8, 0, 0 }
1933 /* Return a struct reg defining register NAME that's 128 bits on all
1935 #define R16(name) { STR(name), 16, 16, 0, 0 }
1937 /* Return a struct reg defining floating-point register NAME. */
1938 #define F(name) { STR(name), 8, 8, 1, 0 }
1940 /* Return a struct reg defining a pseudo register NAME. */
1941 #define P(name) { STR(name), 4, 8, 0, 1}
1943 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
1944 systems and that doesn't exist on 64-bit systems. */
1945 #define R32(name) { STR(name), 4, 0, 0, 0 }
1947 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
1948 systems and that doesn't exist on 32-bit systems. */
1949 #define R64(name) { STR(name), 0, 8, 0, 0 }
1951 /* Return a struct reg placeholder for a register that doesn't exist. */
1952 #define R0 { 0, 0, 0, 0, 0 }
1954 /* UISA registers common across all architectures, including POWER. */
1956 #define COMMON_UISA_REGS \
1957 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1958 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1959 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1960 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1961 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
1962 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
1963 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
1964 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
1965 /* 64 */ R(pc), R(ps)
1967 #define COMMON_UISA_NOFP_REGS \
1968 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1969 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1970 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1971 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1972 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1973 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1974 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1975 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1976 /* 64 */ R(pc), R(ps)
1978 /* UISA-level SPRs for PowerPC. */
1979 #define PPC_UISA_SPRS \
1980 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
1982 /* UISA-level SPRs for PowerPC without floating point support. */
1983 #define PPC_UISA_NOFP_SPRS \
1984 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
1986 /* Segment registers, for PowerPC. */
1987 #define PPC_SEGMENT_REGS \
1988 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
1989 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
1990 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
1991 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
1993 /* OEA SPRs for PowerPC. */
1994 #define PPC_OEA_SPRS \
1996 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
1997 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
1998 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
1999 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
2000 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
2001 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
2002 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
2003 /* 116 */ R4(dec), R(dabr), R4(ear)
2005 /* AltiVec registers. */
2006 #define PPC_ALTIVEC_REGS \
2007 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
2008 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
2009 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
2010 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
2011 /*151*/R4(vscr), R4(vrsave)
2013 /* Vectors of hi-lo general purpose registers. */
2014 #define PPC_EV_REGS \
2015 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
2016 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
2017 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
2018 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
2020 /* Lower half of the EV registers. */
2021 #define PPC_GPRS_PSEUDO_REGS \
2022 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
2023 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
2024 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
2025 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31)
2027 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2028 user-level SPR's. */
2029 static const struct reg registers_power[] =
2032 /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
2036 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2037 view of the PowerPC. */
2038 static const struct reg registers_powerpc[] =
2045 /* PowerPC UISA - a PPC processor as viewed by user-level
2046 code, but without floating point registers. */
2047 static const struct reg registers_powerpc_nofp[] =
2049 COMMON_UISA_NOFP_REGS,
2053 /* IBM PowerPC 403. */
2054 static const struct reg registers_403[] =
2060 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2061 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2062 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2063 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2064 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2065 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2)
2068 /* IBM PowerPC 403GC. */
2069 static const struct reg registers_403GC[] =
2075 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2076 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2077 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2078 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2079 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2080 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2),
2081 /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr),
2082 /* 147 */ R(tbhu), R(tblu)
2085 /* Motorola PowerPC 505. */
2086 static const struct reg registers_505[] =
2092 /* 119 */ R(eie), R(eid), R(nri)
2095 /* Motorola PowerPC 860 or 850. */
2096 static const struct reg registers_860[] =
2102 /* 119 */ R(eie), R(eid), R(nri), R(cmpa),
2103 /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr),
2104 /* 127 */ R(der), R(counta), R(countb), R(cmpe),
2105 /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1),
2106 /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst),
2107 /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr),
2108 /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr),
2109 /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc),
2110 /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap),
2111 /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn),
2112 /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1),
2113 /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1)
2116 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2117 for reading and writing RTCU and RTCL. However, how one reads and writes a
2118 register is the stub's problem. */
2119 static const struct reg registers_601[] =
2125 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2126 /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl)
2129 /* Motorola PowerPC 602. */
2130 static const struct reg registers_602[] =
2136 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2137 /* 123 */ R0, R(tcr), R(ibr), R(esassr),
2138 /* 127 */ R(sebr), R(ser), R(sp), R(lt)
2141 /* Motorola/IBM PowerPC 603 or 603e. */
2142 static const struct reg registers_603[] =
2148 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2149 /* 123 */ R0, R(dmiss), R(dcmp), R(hash1),
2150 /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa)
2153 /* Motorola PowerPC 604 or 604e. */
2154 static const struct reg registers_604[] =
2160 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2161 /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2),
2162 /* 127 */ R(sia), R(sda)
2165 /* Motorola/IBM PowerPC 750 or 740. */
2166 static const struct reg registers_750[] =
2172 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2173 /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2),
2174 /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4),
2175 /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia),
2176 /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr),
2177 /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3)
2181 /* Motorola PowerPC 7400. */
2182 static const struct reg registers_7400[] =
2184 /* gpr0-gpr31, fpr0-fpr31 */
2186 /* cr, lr, ctr, xer, fpscr */
2191 /* vr0-vr31, vrsave, vscr */
2193 /* FIXME? Add more registers? */
2196 /* Motorola e500. */
2197 static const struct reg registers_e500[] =
2200 /* cr, lr, ctr, xer, "" */
2204 R8(acc), R(spefscr),
2205 /* NOTE: Add new registers here the end of the raw register
2206 list and just before the first pseudo register. */
2208 PPC_GPRS_PSEUDO_REGS
2211 /* Information about a particular processor variant. */
2215 /* Name of this variant. */
2218 /* English description of the variant. */
2221 /* bfd_arch_info.arch corresponding to variant. */
2222 enum bfd_architecture arch;
2224 /* bfd_arch_info.mach corresponding to variant. */
2227 /* Number of real registers. */
2230 /* Number of pseudo registers. */
2233 /* Number of total registers (the sum of nregs and npregs). */
2236 /* Table of register names; registers[R] is the name of the register
2238 const struct reg *regs;
2241 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2244 num_registers (const struct reg *reg_list, int num_tot_regs)
2249 for (i = 0; i < num_tot_regs; i++)
2250 if (!reg_list[i].pseudo)
2257 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2262 for (i = 0; i < num_tot_regs; i++)
2263 if (reg_list[i].pseudo)
2269 /* Information in this table comes from the following web sites:
2270 IBM: http://www.chips.ibm.com:80/products/embedded/
2271 Motorola: http://www.mot.com/SPS/PowerPC/
2273 I'm sure I've got some of the variant descriptions not quite right.
2274 Please report any inaccuracies you find to GDB's maintainer.
2276 If you add entries to this table, please be sure to allow the new
2277 value as an argument to the --with-cpu flag, in configure.in. */
2279 static struct variant variants[] =
2282 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2283 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2285 {"power", "POWER user-level", bfd_arch_rs6000,
2286 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2288 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2289 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2291 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2292 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2294 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2295 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2297 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2298 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2300 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2301 604, -1, -1, tot_num_registers (registers_604),
2303 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2304 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2306 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2307 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2309 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2310 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2312 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2313 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2315 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2316 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2318 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2319 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2323 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2324 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2326 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2327 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2329 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2330 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2332 {"a35", "PowerPC A35", bfd_arch_powerpc,
2333 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2335 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2336 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2338 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2339 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2342 /* FIXME: I haven't checked the register sets of the following. */
2343 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2344 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2346 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2347 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2349 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2350 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2353 {0, 0, 0, 0, 0, 0, 0, 0}
2356 /* Initialize the number of registers and pseudo registers in each variant. */
2359 init_variants (void)
2363 for (v = variants; v->name; v++)
2366 v->nregs = num_registers (v->regs, v->num_tot_regs);
2367 if (v->npregs == -1)
2368 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2372 /* Return the variant corresponding to architecture ARCH and machine number
2373 MACH. If no such variant exists, return null. */
2375 static const struct variant *
2376 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2378 const struct variant *v;
2380 for (v = variants; v->name; v++)
2381 if (arch == v->arch && mach == v->mach)
2388 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2390 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2391 return print_insn_big_powerpc (memaddr, info);
2393 return print_insn_little_powerpc (memaddr, info);
2397 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2399 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2402 static struct frame_id
2403 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2405 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2407 frame_pc_unwind (next_frame));
2410 struct rs6000_frame_cache
2413 CORE_ADDR initial_sp;
2414 struct trad_frame_saved_reg *saved_regs;
2417 static struct rs6000_frame_cache *
2418 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2420 struct rs6000_frame_cache *cache;
2421 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2422 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2423 struct rs6000_framedata fdata;
2424 int wordsize = tdep->wordsize;
2426 if ((*this_cache) != NULL)
2427 return (*this_cache);
2428 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2429 (*this_cache) = cache;
2430 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2432 skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame),
2435 /* If there were any saved registers, figure out parent's stack
2437 /* The following is true only if the frame doesn't have a call to
2440 if (fdata.saved_fpr == 0
2441 && fdata.saved_gpr == 0
2442 && fdata.saved_vr == 0
2443 && fdata.saved_ev == 0
2444 && fdata.lr_offset == 0
2445 && fdata.cr_offset == 0
2446 && fdata.vr_offset == 0
2447 && fdata.ev_offset == 0)
2448 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2451 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2452 address of the current frame. Things might be easier if the
2453 ->frame pointed to the outer-most address of the frame. In
2454 the mean time, the address of the prev frame is used as the
2455 base address of this frame. */
2456 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2457 if (!fdata.frameless)
2458 /* Frameless really means stackless. */
2459 cache->base = read_memory_addr (cache->base, wordsize);
2461 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
2463 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2464 All fpr's from saved_fpr to fp31 are saved. */
2466 if (fdata.saved_fpr >= 0)
2469 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
2471 /* If skip_prologue says floating-point registers were saved,
2472 but the current architecture has no floating-point registers,
2473 then that's strange. But we have no indices to even record
2474 the addresses under, so we just ignore it. */
2475 if (ppc_floating_point_unit_p (gdbarch))
2476 for (i = fdata.saved_fpr; i < 32; i++)
2478 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2483 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2484 All gpr's from saved_gpr to gpr31 are saved. */
2486 if (fdata.saved_gpr >= 0)
2489 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
2490 for (i = fdata.saved_gpr; i < 32; i++)
2492 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2493 gpr_addr += wordsize;
2497 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2498 All vr's from saved_vr to vr31 are saved. */
2499 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2501 if (fdata.saved_vr >= 0)
2504 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2505 for (i = fdata.saved_vr; i < 32; i++)
2507 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2508 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2513 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2514 All vr's from saved_ev to ev31 are saved. ????? */
2515 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
2517 if (fdata.saved_ev >= 0)
2520 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
2521 for (i = fdata.saved_ev; i < 32; i++)
2523 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2524 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2525 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2530 /* If != 0, fdata.cr_offset is the offset from the frame that
2532 if (fdata.cr_offset != 0)
2533 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2535 /* If != 0, fdata.lr_offset is the offset from the frame that
2537 if (fdata.lr_offset != 0)
2538 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2539 /* The PC is found in the link register. */
2540 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
2542 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2543 holds the VRSAVE. */
2544 if (fdata.vrsave_offset != 0)
2545 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2547 if (fdata.alloca_reg < 0)
2548 /* If no alloca register used, then fi->frame is the value of the
2549 %sp for this frame, and it is good enough. */
2550 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2552 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
2559 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
2560 struct frame_id *this_id)
2562 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2564 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
2568 rs6000_frame_prev_register (struct frame_info *next_frame,
2570 int regnum, int *optimizedp,
2571 enum lval_type *lvalp, CORE_ADDR *addrp,
2572 int *realnump, void *valuep)
2574 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2576 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
2577 optimizedp, lvalp, addrp, realnump, valuep);
2580 static const struct frame_unwind rs6000_frame_unwind =
2583 rs6000_frame_this_id,
2584 rs6000_frame_prev_register
2587 static const struct frame_unwind *
2588 rs6000_frame_sniffer (struct frame_info *next_frame)
2590 return &rs6000_frame_unwind;
2596 rs6000_frame_base_address (struct frame_info *next_frame,
2599 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2601 return info->initial_sp;
2604 static const struct frame_base rs6000_frame_base = {
2605 &rs6000_frame_unwind,
2606 rs6000_frame_base_address,
2607 rs6000_frame_base_address,
2608 rs6000_frame_base_address
2611 static const struct frame_base *
2612 rs6000_frame_base_sniffer (struct frame_info *next_frame)
2614 return &rs6000_frame_base;
2617 /* Initialize the current architecture based on INFO. If possible, re-use an
2618 architecture from ARCHES, which is a list of architectures already created
2619 during this debugging session.
2621 Called e.g. at program startup, when reading a core file, and when reading
2624 static struct gdbarch *
2625 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2627 struct gdbarch *gdbarch;
2628 struct gdbarch_tdep *tdep;
2629 int wordsize, from_xcoff_exec, from_elf_exec, power, i, off;
2631 const struct variant *v;
2632 enum bfd_architecture arch;
2638 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
2639 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
2641 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
2642 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2644 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2646 /* Check word size. If INFO is from a binary file, infer it from
2647 that, else choose a likely default. */
2648 if (from_xcoff_exec)
2650 if (bfd_xcoff_is_xcoff64 (info.abfd))
2655 else if (from_elf_exec)
2657 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
2664 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
2665 wordsize = info.bfd_arch_info->bits_per_word /
2666 info.bfd_arch_info->bits_per_byte;
2671 /* Find a candidate among extant architectures. */
2672 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2674 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2676 /* Word size in the various PowerPC bfd_arch_info structs isn't
2677 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
2678 separate word size check. */
2679 tdep = gdbarch_tdep (arches->gdbarch);
2680 if (tdep && tdep->wordsize == wordsize)
2681 return arches->gdbarch;
2684 /* None found, create a new architecture from INFO, whose bfd_arch_info
2685 validity depends on the source:
2686 - executable useless
2687 - rs6000_host_arch() good
2689 - "set arch" trust blindly
2690 - GDB startup useless but harmless */
2692 if (!from_xcoff_exec)
2694 arch = info.bfd_arch_info->arch;
2695 mach = info.bfd_arch_info->mach;
2699 arch = bfd_arch_powerpc;
2700 bfd_default_set_arch_mach (&abfd, arch, 0);
2701 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2702 mach = info.bfd_arch_info->mach;
2704 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2705 tdep->wordsize = wordsize;
2707 /* For e500 executables, the apuinfo section is of help here. Such
2708 section contains the identifier and revision number of each
2709 Application-specific Processing Unit that is present on the
2710 chip. The content of the section is determined by the assembler
2711 which looks at each instruction and determines which unit (and
2712 which version of it) can execute it. In our case we just look for
2713 the existance of the section. */
2717 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
2720 arch = info.bfd_arch_info->arch;
2721 mach = bfd_mach_ppc_e500;
2722 bfd_default_set_arch_mach (&abfd, arch, mach);
2723 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2727 gdbarch = gdbarch_alloc (&info, tdep);
2728 power = arch == bfd_arch_rs6000;
2730 /* Initialize the number of real and pseudo registers in each variant. */
2733 /* Choose variant. */
2734 v = find_variant_by_arch (arch, mach);
2738 tdep->regs = v->regs;
2740 tdep->ppc_gp0_regnum = 0;
2741 tdep->ppc_toc_regnum = 2;
2742 tdep->ppc_ps_regnum = 65;
2743 tdep->ppc_cr_regnum = 66;
2744 tdep->ppc_lr_regnum = 67;
2745 tdep->ppc_ctr_regnum = 68;
2746 tdep->ppc_xer_regnum = 69;
2747 if (v->mach == bfd_mach_ppc_601)
2748 tdep->ppc_mq_regnum = 124;
2750 tdep->ppc_mq_regnum = 70;
2752 tdep->ppc_mq_regnum = -1;
2753 tdep->ppc_fp0_regnum = 32;
2754 tdep->ppc_fpscr_regnum = power ? 71 : 70;
2756 set_gdbarch_pc_regnum (gdbarch, 64);
2757 set_gdbarch_sp_regnum (gdbarch, 1);
2758 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
2759 if (sysv_abi && wordsize == 8)
2760 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
2761 else if (sysv_abi && wordsize == 4)
2762 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
2765 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
2766 set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value);
2769 if (v->arch == bfd_arch_powerpc)
2773 tdep->ppc_vr0_regnum = 71;
2774 tdep->ppc_vrsave_regnum = 104;
2775 tdep->ppc_ev0_regnum = -1;
2776 tdep->ppc_ev31_regnum = -1;
2778 case bfd_mach_ppc_7400:
2779 tdep->ppc_vr0_regnum = 119;
2780 tdep->ppc_vrsave_regnum = 152;
2781 tdep->ppc_ev0_regnum = -1;
2782 tdep->ppc_ev31_regnum = -1;
2784 case bfd_mach_ppc_e500:
2785 tdep->ppc_gp0_regnum = 41;
2786 tdep->ppc_toc_regnum = -1;
2787 tdep->ppc_ps_regnum = 1;
2788 tdep->ppc_cr_regnum = 2;
2789 tdep->ppc_lr_regnum = 3;
2790 tdep->ppc_ctr_regnum = 4;
2791 tdep->ppc_xer_regnum = 5;
2792 tdep->ppc_ev0_regnum = 7;
2793 tdep->ppc_ev31_regnum = 38;
2794 tdep->ppc_fp0_regnum = -1;
2795 tdep->ppc_fpscr_regnum = -1;
2796 set_gdbarch_pc_regnum (gdbarch, 0);
2797 set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
2798 set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
2799 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
2800 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
2803 tdep->ppc_vr0_regnum = -1;
2804 tdep->ppc_vrsave_regnum = -1;
2805 tdep->ppc_ev0_regnum = -1;
2806 tdep->ppc_ev31_regnum = -1;
2810 /* Sanity check on registers. */
2811 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
2813 /* Set lr_frame_offset. */
2815 tdep->lr_frame_offset = 16;
2817 tdep->lr_frame_offset = 4;
2819 tdep->lr_frame_offset = 8;
2821 /* Calculate byte offsets in raw register array. */
2822 tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int));
2823 for (i = off = 0; i < v->num_tot_regs; i++)
2825 tdep->regoff[i] = off;
2826 off += regsize (v->regs + i, wordsize);
2829 /* Select instruction printer. */
2831 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
2833 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
2835 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2837 set_gdbarch_num_regs (gdbarch, v->nregs);
2838 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
2839 set_gdbarch_register_name (gdbarch, rs6000_register_name);
2840 set_gdbarch_deprecated_register_size (gdbarch, wordsize);
2841 set_gdbarch_deprecated_register_bytes (gdbarch, off);
2842 set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte);
2843 set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size);
2844 set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type);
2846 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2847 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2848 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2849 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2850 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2851 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2852 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2854 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
2856 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2857 set_gdbarch_char_signed (gdbarch, 0);
2859 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
2860 if (sysv_abi && wordsize == 8)
2862 set_gdbarch_frame_red_zone_size (gdbarch, 288);
2863 else if (!sysv_abi && wordsize == 4)
2864 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
2865 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
2866 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
2868 set_gdbarch_frame_red_zone_size (gdbarch, 224);
2870 set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible);
2871 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual);
2872 set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw);
2873 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
2874 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
2875 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
2876 is correct for the SysV ABI when the wordsize is 8, but I'm also
2877 fairly certain that ppc_sysv_abi_push_arguments() will give even
2878 worse results since it only works for 32-bit code. So, for the moment,
2879 we're better off calling rs6000_push_arguments() since it works for
2880 64-bit code. At some point in the future, this matter needs to be
2882 if (sysv_abi && wordsize == 4)
2883 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
2884 else if (sysv_abi && wordsize == 8)
2885 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
2887 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
2889 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
2891 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
2892 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2893 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
2895 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
2896 for the descriptor and ".FN" for the entry-point -- a user
2897 specifying "break FN" will unexpectedly end up with a breakpoint
2898 on the descriptor and not the function. This architecture method
2899 transforms any breakpoints on descriptors into breakpoints on the
2900 corresponding entry point. */
2901 if (sysv_abi && wordsize == 8)
2902 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
2904 /* Not sure on this. FIXMEmgo */
2905 set_gdbarch_frame_args_skip (gdbarch, 8);
2908 set_gdbarch_use_struct_convention (gdbarch,
2909 rs6000_use_struct_convention);
2913 /* Handle RS/6000 function pointers (which are really function
2915 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
2916 rs6000_convert_from_func_ptr_addr);
2919 /* Helpers for function argument information. */
2920 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
2922 /* Hook in ABI-specific overrides, if they have been registered. */
2923 gdbarch_init_osabi (info, gdbarch);
2927 case GDB_OSABI_NETBSD_AOUT:
2928 case GDB_OSABI_NETBSD_ELF:
2929 case GDB_OSABI_UNKNOWN:
2930 case GDB_OSABI_LINUX:
2931 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
2932 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
2933 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
2934 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
2937 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2939 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
2940 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
2941 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
2942 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
2945 if (from_xcoff_exec)
2947 /* NOTE: jimix/2003-06-09: This test should really check for
2948 GDB_OSABI_AIX when that is defined and becomes
2949 available. (Actually, once things are properly split apart,
2950 the test goes away.) */
2951 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
2952 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
2959 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2961 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2966 /* FIXME: Dump gdbarch_tdep. */
2969 static struct cmd_list_element *info_powerpc_cmdlist = NULL;
2972 rs6000_info_powerpc_command (char *args, int from_tty)
2974 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
2977 /* Initialization code. */
2979 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
2982 _initialize_rs6000_tdep (void)
2984 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
2985 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
2987 /* Add root prefix command for "info powerpc" commands */
2988 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
2989 "Various POWERPC info specific commands.",
2990 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);