1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996,
4 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004 Free Software
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
32 #include "arch-utils.h"
37 #include "parser-defs.h"
40 #include "libbfd.h" /* for bfd_default_set_arch_mach */
41 #include "coff/internal.h" /* for libcoff.h */
42 #include "libcoff.h" /* for xcoff_data */
43 #include "coff/xcoff.h"
48 #include "solib-svr4.h"
51 #include "gdb_assert.h"
54 #include "trad-frame.h"
55 #include "frame-unwind.h"
56 #include "frame-base.h"
58 /* If the kernel has to deliver a signal, it pushes a sigcontext
59 structure on the stack and then calls the signal handler, passing
60 the address of the sigcontext in an argument register. Usually
61 the signal handler doesn't save this register, so we have to
62 access the sigcontext structure via an offset from the signal handler
64 The following constants were determined by experimentation on AIX 3.2. */
65 #define SIG_FRAME_PC_OFFSET 96
66 #define SIG_FRAME_LR_OFFSET 108
67 #define SIG_FRAME_FP_OFFSET 284
69 /* To be used by skip_prologue. */
71 struct rs6000_framedata
73 int offset; /* total size of frame --- the distance
74 by which we decrement sp to allocate
76 int saved_gpr; /* smallest # of saved gpr */
77 int saved_fpr; /* smallest # of saved fpr */
78 int saved_vr; /* smallest # of saved vr */
79 int saved_ev; /* smallest # of saved ev */
80 int alloca_reg; /* alloca register number (frame ptr) */
81 char frameless; /* true if frameless functions. */
82 char nosavedpc; /* true if pc not saved. */
83 int gpr_offset; /* offset of saved gprs from prev sp */
84 int fpr_offset; /* offset of saved fprs from prev sp */
85 int vr_offset; /* offset of saved vrs from prev sp */
86 int ev_offset; /* offset of saved evs from prev sp */
87 int lr_offset; /* offset of saved lr */
88 int cr_offset; /* offset of saved cr */
89 int vrsave_offset; /* offset of saved vrsave register */
92 /* Description of a single register. */
96 char *name; /* name of register */
97 unsigned char sz32; /* size on 32-bit arch, 0 if nonextant */
98 unsigned char sz64; /* size on 64-bit arch, 0 if nonextant */
99 unsigned char fpr; /* whether register is floating-point */
100 unsigned char pseudo; /* whether register is pseudo */
103 /* Breakpoint shadows for the single step instructions will be kept here. */
105 static struct sstep_breaks
107 /* Address, or 0 if this is not in use. */
109 /* Shadow contents. */
114 /* Hook for determining the TOC address when calling functions in the
115 inferior under AIX. The initialization code in rs6000-nat.c sets
116 this hook to point to find_toc_address. */
118 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
120 /* Hook to set the current architecture when starting a child process.
121 rs6000-nat.c sets this. */
123 void (*rs6000_set_host_arch_hook) (int) = NULL;
125 /* Static function prototypes */
127 static CORE_ADDR branch_dest (int opcode, int instr, CORE_ADDR pc,
129 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
130 struct rs6000_framedata *);
132 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
134 altivec_register_p (int regno)
136 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
137 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
140 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
143 /* Use the architectures FP registers? */
145 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
147 const struct bfd_arch_info *info = gdbarch_bfd_arch_info (gdbarch);
148 if (info->arch == bfd_arch_powerpc)
149 return (info->mach != bfd_mach_ppc_e500);
150 if (info->arch == bfd_arch_rs6000)
156 /* Register set support functions. */
159 ppc_supply_reg (struct regcache *regcache, int regnum,
160 const char *regs, size_t offset)
162 if (regnum != -1 && offset != -1)
163 regcache_raw_supply (regcache, regnum, regs + offset);
167 ppc_collect_reg (const struct regcache *regcache, int regnum,
168 char *regs, size_t offset)
170 if (regnum != -1 && offset != -1)
171 regcache_raw_collect (regcache, regnum, regs + offset);
174 /* Supply register REGNUM in the general-purpose register set REGSET
175 from the buffer specified by GREGS and LEN to register cache
176 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
179 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
180 int regnum, const void *gregs, size_t len)
182 struct gdbarch *gdbarch = get_regcache_arch (regcache);
183 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
184 const struct ppc_reg_offsets *offsets = regset->descr;
188 for (i = 0, offset = offsets->r0_offset; i < 32; i++, offset += 4)
190 if (regnum == -1 || regnum == i)
191 ppc_supply_reg (regcache, i, gregs, offset);
194 if (regnum == -1 || regnum == PC_REGNUM)
195 ppc_supply_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
196 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
197 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
198 gregs, offsets->ps_offset);
199 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
200 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
201 gregs, offsets->cr_offset);
202 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
203 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
204 gregs, offsets->lr_offset);
205 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
206 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
207 gregs, offsets->ctr_offset);
208 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
209 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
210 gregs, offsets->cr_offset);
211 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
212 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, gregs, offsets->mq_offset);
215 /* Supply register REGNUM in the floating-point register set REGSET
216 from the buffer specified by FPREGS and LEN to register cache
217 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
220 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
221 int regnum, const void *fpregs, size_t len)
223 struct gdbarch *gdbarch = get_regcache_arch (regcache);
224 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
225 const struct ppc_reg_offsets *offsets = regset->descr;
229 offset = offsets->f0_offset;
230 for (i = tdep->ppc_fp0_regnum;
231 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
234 if (regnum == -1 || regnum == i)
235 ppc_supply_reg (regcache, i, fpregs, offset);
238 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
239 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
240 fpregs, offsets->fpscr_offset);
243 /* Collect register REGNUM in the general-purpose register set
244 REGSET. from register cache REGCACHE into the buffer specified by
245 GREGS and LEN. If REGNUM is -1, do this for all registers in
249 ppc_collect_gregset (const struct regset *regset,
250 const struct regcache *regcache,
251 int regnum, void *gregs, size_t len)
253 struct gdbarch *gdbarch = get_regcache_arch (regcache);
254 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
255 const struct ppc_reg_offsets *offsets = regset->descr;
259 offset = offsets->r0_offset;
260 for (i = 0; i <= 32; i++, offset += 4)
262 if (regnum == -1 || regnum == i)
263 ppc_collect_reg (regcache, regnum, gregs, offset);
266 if (regnum == -1 || regnum == PC_REGNUM)
267 ppc_collect_reg (regcache, PC_REGNUM, gregs, offsets->pc_offset);
268 if (regnum == -1 || regnum == tdep->ppc_ps_regnum)
269 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
270 gregs, offsets->ps_offset);
271 if (regnum == -1 || regnum == tdep->ppc_cr_regnum)
272 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
273 gregs, offsets->cr_offset);
274 if (regnum == -1 || regnum == tdep->ppc_lr_regnum)
275 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
276 gregs, offsets->lr_offset);
277 if (regnum == -1 || regnum == tdep->ppc_ctr_regnum)
278 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
279 gregs, offsets->ctr_offset);
280 if (regnum == -1 || regnum == tdep->ppc_xer_regnum)
281 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
282 gregs, offsets->xer_offset);
283 if (regnum == -1 || regnum == tdep->ppc_mq_regnum)
284 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
285 gregs, offsets->mq_offset);
288 /* Collect register REGNUM in the floating-point register set
289 REGSET. from register cache REGCACHE into the buffer specified by
290 FPREGS and LEN. If REGNUM is -1, do this for all registers in
294 ppc_collect_fpregset (const struct regset *regset,
295 const struct regcache *regcache,
296 int regnum, void *fpregs, size_t len)
298 struct gdbarch *gdbarch = get_regcache_arch (regcache);
299 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
300 const struct ppc_reg_offsets *offsets = regset->descr;
304 offset = offsets->f0_offset;
305 for (i = tdep->ppc_fp0_regnum;
306 i <= tdep->ppc_fp0_regnum + ppc_num_fprs;
309 if (regnum == -1 || regnum == i)
310 ppc_collect_reg (regcache, regnum, fpregs, offset);
313 if (regnum == -1 || regnum == tdep->ppc_fpscr_regnum)
314 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
315 fpregs, offsets->fpscr_offset);
319 /* Read a LEN-byte address from debugged memory address MEMADDR. */
322 read_memory_addr (CORE_ADDR memaddr, int len)
324 return read_memory_unsigned_integer (memaddr, len);
328 rs6000_skip_prologue (CORE_ADDR pc)
330 struct rs6000_framedata frame;
331 pc = skip_prologue (pc, 0, &frame);
336 /* Fill in fi->saved_regs */
338 struct frame_extra_info
340 /* Functions calling alloca() change the value of the stack
341 pointer. We need to use initial stack pointer (which is saved in
342 r31 by gcc) in such cases. If a compiler emits traceback table,
343 then we should use the alloca register specified in traceback
345 CORE_ADDR initial_sp; /* initial stack pointer. */
348 /* Get the ith function argument for the current function. */
350 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
354 get_frame_register (frame, 3 + argi, &addr);
358 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
361 branch_dest (int opcode, int instr, CORE_ADDR pc, CORE_ADDR safety)
368 absolute = (int) ((instr >> 1) & 1);
373 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
377 dest = pc + immediate;
381 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
385 dest = pc + immediate;
389 ext_op = (instr >> 1) & 0x3ff;
391 if (ext_op == 16) /* br conditional register */
393 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
395 /* If we are about to return from a signal handler, dest is
396 something like 0x3c90. The current frame is a signal handler
397 caller frame, upon completion of the sigreturn system call
398 execution will return to the saved PC in the frame. */
399 if (dest < TEXT_SEGMENT_BASE)
401 struct frame_info *fi;
403 fi = get_current_frame ();
405 dest = read_memory_addr (get_frame_base (fi) + SIG_FRAME_PC_OFFSET,
406 gdbarch_tdep (current_gdbarch)->wordsize);
410 else if (ext_op == 528) /* br cond to count reg */
412 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_ctr_regnum) & ~3;
414 /* If we are about to execute a system call, dest is something
415 like 0x22fc or 0x3b00. Upon completion the system call
416 will return to the address in the link register. */
417 if (dest < TEXT_SEGMENT_BASE)
418 dest = read_register (gdbarch_tdep (current_gdbarch)->ppc_lr_regnum) & ~3;
427 return (dest < TEXT_SEGMENT_BASE) ? safety : dest;
431 /* Sequence of bytes for breakpoint instruction. */
433 const static unsigned char *
434 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
436 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
437 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
439 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
440 return big_breakpoint;
442 return little_breakpoint;
446 /* AIX does not support PT_STEP. Simulate it. */
449 rs6000_software_single_step (enum target_signal signal,
450 int insert_breakpoints_p)
454 const char *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
460 if (insert_breakpoints_p)
465 insn = read_memory_integer (loc, 4);
467 breaks[0] = loc + breakp_sz;
469 breaks[1] = branch_dest (opcode, insn, loc, breaks[0]);
471 /* Don't put two breakpoints on the same address. */
472 if (breaks[1] == breaks[0])
475 stepBreaks[1].address = 0;
477 for (ii = 0; ii < 2; ++ii)
480 /* ignore invalid breakpoint. */
481 if (breaks[ii] == -1)
483 target_insert_breakpoint (breaks[ii], stepBreaks[ii].data);
484 stepBreaks[ii].address = breaks[ii];
491 /* remove step breakpoints. */
492 for (ii = 0; ii < 2; ++ii)
493 if (stepBreaks[ii].address != 0)
494 target_remove_breakpoint (stepBreaks[ii].address,
495 stepBreaks[ii].data);
497 errno = 0; /* FIXME, don't ignore errors! */
498 /* What errors? {read,write}_memory call error(). */
502 /* return pc value after skipping a function prologue and also return
503 information about a function frame.
505 in struct rs6000_framedata fdata:
506 - frameless is TRUE, if function does not have a frame.
507 - nosavedpc is TRUE, if function does not save %pc value in its frame.
508 - offset is the initial size of this stack frame --- the amount by
509 which we decrement the sp to allocate the frame.
510 - saved_gpr is the number of the first saved gpr.
511 - saved_fpr is the number of the first saved fpr.
512 - saved_vr is the number of the first saved vr.
513 - saved_ev is the number of the first saved ev.
514 - alloca_reg is the number of the register used for alloca() handling.
516 - gpr_offset is the offset of the first saved gpr from the previous frame.
517 - fpr_offset is the offset of the first saved fpr from the previous frame.
518 - vr_offset is the offset of the first saved vr from the previous frame.
519 - ev_offset is the offset of the first saved ev from the previous frame.
520 - lr_offset is the offset of the saved lr
521 - cr_offset is the offset of the saved cr
522 - vrsave_offset is the offset of the saved vrsave register
525 #define SIGNED_SHORT(x) \
526 ((sizeof (short) == 2) \
527 ? ((int)(short)(x)) \
528 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
530 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
532 /* Limit the number of skipped non-prologue instructions, as the examining
533 of the prologue is expensive. */
534 static int max_skip_non_prologue_insns = 10;
536 /* Given PC representing the starting address of a function, and
537 LIM_PC which is the (sloppy) limit to which to scan when looking
538 for a prologue, attempt to further refine this limit by using
539 the line data in the symbol table. If successful, a better guess
540 on where the prologue ends is returned, otherwise the previous
541 value of lim_pc is returned. */
543 /* FIXME: cagney/2004-02-14: This function and logic have largely been
544 superseded by skip_prologue_using_sal. */
547 refine_prologue_limit (CORE_ADDR pc, CORE_ADDR lim_pc)
549 struct symtab_and_line prologue_sal;
551 prologue_sal = find_pc_line (pc, 0);
552 if (prologue_sal.line != 0)
555 CORE_ADDR addr = prologue_sal.end;
557 /* Handle the case in which compiler's optimizer/scheduler
558 has moved instructions into the prologue. We scan ahead
559 in the function looking for address ranges whose corresponding
560 line number is less than or equal to the first one that we
561 found for the function. (It can be less than when the
562 scheduler puts a body instruction before the first prologue
564 for (i = 2 * max_skip_non_prologue_insns;
565 i > 0 && (lim_pc == 0 || addr < lim_pc);
568 struct symtab_and_line sal;
570 sal = find_pc_line (addr, 0);
573 if (sal.line <= prologue_sal.line
574 && sal.symtab == prologue_sal.symtab)
581 if (lim_pc == 0 || prologue_sal.end < lim_pc)
582 lim_pc = prologue_sal.end;
589 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
591 CORE_ADDR orig_pc = pc;
592 CORE_ADDR last_prologue_pc = pc;
593 CORE_ADDR li_found_pc = 0;
597 long vr_saved_offset = 0;
606 int minimal_toc_loaded = 0;
607 int prev_insn_was_prologue_insn = 1;
608 int num_skip_non_prologue_insns = 0;
609 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
610 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
612 /* Attempt to find the end of the prologue when no limit is specified.
613 Note that refine_prologue_limit() has been written so that it may
614 be used to "refine" the limits of non-zero PC values too, but this
615 is only safe if we 1) trust the line information provided by the
616 compiler and 2) iterate enough to actually find the end of the
619 It may become a good idea at some point (for both performance and
620 accuracy) to unconditionally call refine_prologue_limit(). But,
621 until we can make a clear determination that this is beneficial,
622 we'll play it safe and only use it to obtain a limit when none
623 has been specified. */
625 lim_pc = refine_prologue_limit (pc, lim_pc);
627 memset (fdata, 0, sizeof (struct rs6000_framedata));
628 fdata->saved_gpr = -1;
629 fdata->saved_fpr = -1;
630 fdata->saved_vr = -1;
631 fdata->saved_ev = -1;
632 fdata->alloca_reg = -1;
633 fdata->frameless = 1;
634 fdata->nosavedpc = 1;
638 /* Sometimes it isn't clear if an instruction is a prologue
639 instruction or not. When we encounter one of these ambiguous
640 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
641 Otherwise, we'll assume that it really is a prologue instruction. */
642 if (prev_insn_was_prologue_insn)
643 last_prologue_pc = pc;
645 /* Stop scanning if we've hit the limit. */
646 if (lim_pc != 0 && pc >= lim_pc)
649 prev_insn_was_prologue_insn = 1;
651 /* Fetch the instruction and convert it to an integer. */
652 if (target_read_memory (pc, buf, 4))
654 op = extract_signed_integer (buf, 4);
656 if ((op & 0xfc1fffff) == 0x7c0802a6)
658 /* Since shared library / PIC code, which needs to get its
659 address at runtime, can appear to save more than one link
673 remember just the first one, but skip over additional
676 lr_reg = (op & 0x03e00000);
679 else if ((op & 0xfc1fffff) == 0x7c000026)
681 cr_reg = (op & 0x03e00000);
685 else if ((op & 0xfc1f0000) == 0xd8010000)
686 { /* stfd Rx,NUM(r1) */
687 reg = GET_SRC_REG (op);
688 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
690 fdata->saved_fpr = reg;
691 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
696 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
697 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
698 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
699 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
702 reg = GET_SRC_REG (op);
703 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
705 fdata->saved_gpr = reg;
706 if ((op & 0xfc1f0003) == 0xf8010000)
708 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
713 else if ((op & 0xffff0000) == 0x60000000)
716 /* Allow nops in the prologue, but do not consider them to
717 be part of the prologue unless followed by other prologue
719 prev_insn_was_prologue_insn = 0;
723 else if ((op & 0xffff0000) == 0x3c000000)
724 { /* addis 0,0,NUM, used
726 fdata->offset = (op & 0x0000ffff) << 16;
727 fdata->frameless = 0;
731 else if ((op & 0xffff0000) == 0x60000000)
732 { /* ori 0,0,NUM, 2nd ha
733 lf of >= 32k frames */
734 fdata->offset |= (op & 0x0000ffff);
735 fdata->frameless = 0;
739 else if (lr_reg != -1 &&
740 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
741 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
742 /* stw Rx, NUM(r1) */
743 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
744 /* stwu Rx, NUM(r1) */
745 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
746 { /* where Rx == lr */
747 fdata->lr_offset = offset;
748 fdata->nosavedpc = 0;
750 if ((op & 0xfc000003) == 0xf8000000 || /* std */
751 (op & 0xfc000000) == 0x90000000) /* stw */
753 /* Does not update r1, so add displacement to lr_offset. */
754 fdata->lr_offset += SIGNED_SHORT (op);
759 else if (cr_reg != -1 &&
760 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
761 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
762 /* stw Rx, NUM(r1) */
763 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
764 /* stwu Rx, NUM(r1) */
765 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
766 { /* where Rx == cr */
767 fdata->cr_offset = offset;
769 if ((op & 0xfc000003) == 0xf8000000 ||
770 (op & 0xfc000000) == 0x90000000)
772 /* Does not update r1, so add displacement to cr_offset. */
773 fdata->cr_offset += SIGNED_SHORT (op);
778 else if (op == 0x48000005)
784 else if (op == 0x48000004)
789 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
790 in V.4 -mminimal-toc */
791 (op & 0xffff0000) == 0x3bde0000)
792 { /* addi 30,30,foo@l */
796 else if ((op & 0xfc000001) == 0x48000001)
800 fdata->frameless = 0;
801 /* Don't skip over the subroutine call if it is not within
802 the first three instructions of the prologue. */
803 if ((pc - orig_pc) > 8)
806 op = read_memory_integer (pc + 4, 4);
808 /* At this point, make sure this is not a trampoline
809 function (a function that simply calls another functions,
810 and nothing else). If the next is not a nop, this branch
811 was part of the function prologue. */
813 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
814 break; /* don't skip over
819 /* update stack pointer */
820 else if ((op & 0xfc1f0000) == 0x94010000)
821 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
822 fdata->frameless = 0;
823 fdata->offset = SIGNED_SHORT (op);
824 offset = fdata->offset;
827 else if ((op & 0xfc1f016a) == 0x7c01016e)
828 { /* stwux rX,r1,rY */
829 /* no way to figure out what r1 is going to be */
830 fdata->frameless = 0;
831 offset = fdata->offset;
834 else if ((op & 0xfc1f0003) == 0xf8010001)
835 { /* stdu rX,NUM(r1) */
836 fdata->frameless = 0;
837 fdata->offset = SIGNED_SHORT (op & ~3UL);
838 offset = fdata->offset;
841 else if ((op & 0xfc1f016a) == 0x7c01016a)
842 { /* stdux rX,r1,rY */
843 /* no way to figure out what r1 is going to be */
844 fdata->frameless = 0;
845 offset = fdata->offset;
848 /* Load up minimal toc pointer */
849 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
850 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
851 && !minimal_toc_loaded)
853 minimal_toc_loaded = 1;
856 /* move parameters from argument registers to local variable
859 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
860 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
861 (((op >> 21) & 31) <= 10) &&
862 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
866 /* store parameters in stack */
868 /* Move parameters from argument registers to temporary register. */
869 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
870 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
871 (((op >> 21) & 31) <= 10) &&
872 (((op >> 16) & 31) == 0)) /* Rx: scratch register r0 */
876 else if ((op & 0xfc1f0003) == 0xf8010000 || /* std rx,NUM(r1) */
877 (op & 0xfc1f0000) == 0xd8010000 || /* stfd Rx,NUM(r1) */
878 (op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
882 /* store parameters in stack via frame pointer */
885 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
886 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
887 (op & 0xfc1f0000) == 0xd81f0000 || /* stfd Rx,NUM(r31) */
888 (op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
892 /* Set up frame pointer */
894 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
897 fdata->frameless = 0;
899 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
902 /* Another way to set up the frame pointer. */
904 else if ((op & 0xfc1fffff) == 0x38010000)
905 { /* addi rX, r1, 0x0 */
906 fdata->frameless = 0;
908 fdata->alloca_reg = (tdep->ppc_gp0_regnum
909 + ((op & ~0x38010000) >> 21));
912 /* AltiVec related instructions. */
913 /* Store the vrsave register (spr 256) in another register for
914 later manipulation, or load a register into the vrsave
915 register. 2 instructions are used: mfvrsave and
916 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
917 and mtspr SPR256, Rn. */
918 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
919 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
920 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
922 vrsave_reg = GET_SRC_REG (op);
925 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
929 /* Store the register where vrsave was saved to onto the stack:
930 rS is the register where vrsave was stored in a previous
932 /* 100100 sssss 00001 dddddddd dddddddd */
933 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
935 if (vrsave_reg == GET_SRC_REG (op))
937 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
942 /* Compute the new value of vrsave, by modifying the register
943 where vrsave was saved to. */
944 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
945 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
949 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
950 in a pair of insns to save the vector registers on the
952 /* 001110 00000 00000 iiii iiii iiii iiii */
953 /* 001110 01110 00000 iiii iiii iiii iiii */
954 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
955 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
958 vr_saved_offset = SIGNED_SHORT (op);
960 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
961 /* 011111 sssss 11111 00000 00111001110 */
962 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
964 if (pc == (li_found_pc + 4))
966 vr_reg = GET_SRC_REG (op);
967 /* If this is the first vector reg to be saved, or if
968 it has a lower number than others previously seen,
969 reupdate the frame info. */
970 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
972 fdata->saved_vr = vr_reg;
973 fdata->vr_offset = vr_saved_offset + offset;
975 vr_saved_offset = -1;
980 /* End AltiVec related instructions. */
982 /* Start BookE related instructions. */
983 /* Store gen register S at (r31+uimm).
984 Any register less than r13 is volatile, so we don't care. */
985 /* 000100 sssss 11111 iiiii 01100100001 */
986 else if (arch_info->mach == bfd_mach_ppc_e500
987 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
989 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
992 ev_reg = GET_SRC_REG (op);
993 imm = (op >> 11) & 0x1f;
995 /* If this is the first vector reg to be saved, or if
996 it has a lower number than others previously seen,
997 reupdate the frame info. */
998 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1000 fdata->saved_ev = ev_reg;
1001 fdata->ev_offset = ev_offset + offset;
1006 /* Store gen register rS at (r1+rB). */
1007 /* 000100 sssss 00001 bbbbb 01100100000 */
1008 else if (arch_info->mach == bfd_mach_ppc_e500
1009 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1011 if (pc == (li_found_pc + 4))
1013 ev_reg = GET_SRC_REG (op);
1014 /* If this is the first vector reg to be saved, or if
1015 it has a lower number than others previously seen,
1016 reupdate the frame info. */
1017 /* We know the contents of rB from the previous instruction. */
1018 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1020 fdata->saved_ev = ev_reg;
1021 fdata->ev_offset = vr_saved_offset + offset;
1023 vr_saved_offset = -1;
1029 /* Store gen register r31 at (rA+uimm). */
1030 /* 000100 11111 aaaaa iiiii 01100100001 */
1031 else if (arch_info->mach == bfd_mach_ppc_e500
1032 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1034 /* Wwe know that the source register is 31 already, but
1035 it can't hurt to compute it. */
1036 ev_reg = GET_SRC_REG (op);
1037 ev_offset = ((op >> 11) & 0x1f) * 8;
1038 /* If this is the first vector reg to be saved, or if
1039 it has a lower number than others previously seen,
1040 reupdate the frame info. */
1041 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1043 fdata->saved_ev = ev_reg;
1044 fdata->ev_offset = ev_offset + offset;
1049 /* Store gen register S at (r31+r0).
1050 Store param on stack when offset from SP bigger than 4 bytes. */
1051 /* 000100 sssss 11111 00000 01100100000 */
1052 else if (arch_info->mach == bfd_mach_ppc_e500
1053 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1055 if (pc == (li_found_pc + 4))
1057 if ((op & 0x03e00000) >= 0x01a00000)
1059 ev_reg = GET_SRC_REG (op);
1060 /* If this is the first vector reg to be saved, or if
1061 it has a lower number than others previously seen,
1062 reupdate the frame info. */
1063 /* We know the contents of r0 from the previous
1065 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1067 fdata->saved_ev = ev_reg;
1068 fdata->ev_offset = vr_saved_offset + offset;
1072 vr_saved_offset = -1;
1077 /* End BookE related instructions. */
1081 /* Not a recognized prologue instruction.
1082 Handle optimizer code motions into the prologue by continuing
1083 the search if we have no valid frame yet or if the return
1084 address is not yet saved in the frame. */
1085 if (fdata->frameless == 0
1086 && (lr_reg == -1 || fdata->nosavedpc == 0))
1089 if (op == 0x4e800020 /* blr */
1090 || op == 0x4e800420) /* bctr */
1091 /* Do not scan past epilogue in frameless functions or
1094 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1095 /* Never skip branches. */
1098 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1099 /* Do not scan too many insns, scanning insns is expensive with
1103 /* Continue scanning. */
1104 prev_insn_was_prologue_insn = 0;
1110 /* I have problems with skipping over __main() that I need to address
1111 * sometime. Previously, I used to use misc_function_vector which
1112 * didn't work as well as I wanted to be. -MGO */
1114 /* If the first thing after skipping a prolog is a branch to a function,
1115 this might be a call to an initializer in main(), introduced by gcc2.
1116 We'd like to skip over it as well. Fortunately, xlc does some extra
1117 work before calling a function right after a prologue, thus we can
1118 single out such gcc2 behaviour. */
1121 if ((op & 0xfc000001) == 0x48000001)
1122 { /* bl foo, an initializer function? */
1123 op = read_memory_integer (pc + 4, 4);
1125 if (op == 0x4def7b82)
1126 { /* cror 0xf, 0xf, 0xf (nop) */
1128 /* Check and see if we are in main. If so, skip over this
1129 initializer function as well. */
1131 tmp = find_pc_misc_function (pc);
1133 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1139 fdata->offset = -fdata->offset;
1140 return last_prologue_pc;
1144 /*************************************************************************
1145 Support for creating pushing a dummy frame into the stack, and popping
1147 *************************************************************************/
1150 /* All the ABI's require 16 byte alignment. */
1152 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1154 return (addr & -16);
1157 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1158 the first eight words of the argument list (that might be less than
1159 eight parameters if some parameters occupy more than one word) are
1160 passed in r3..r10 registers. float and double parameters are
1161 passed in fpr's, in addition to that. Rest of the parameters if any
1162 are passed in user stack. There might be cases in which half of the
1163 parameter is copied into registers, the other half is pushed into
1166 Stack must be aligned on 64-bit boundaries when synthesizing
1169 If the function is returning a structure, then the return address is passed
1170 in r3, then the first 7 words of the parameters can be passed in registers,
1171 starting from r4. */
1174 rs6000_push_dummy_call (struct gdbarch *gdbarch, CORE_ADDR func_addr,
1175 struct regcache *regcache, CORE_ADDR bp_addr,
1176 int nargs, struct value **args, CORE_ADDR sp,
1177 int struct_return, CORE_ADDR struct_addr)
1179 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1182 int argno; /* current argument number */
1183 int argbytes; /* current argument byte */
1184 char tmp_buffer[50];
1185 int f_argno = 0; /* current floating point argno */
1186 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize;
1188 struct value *arg = 0;
1193 /* The first eight words of ther arguments are passed in registers.
1194 Copy them appropriately. */
1197 /* If the function is returning a `struct', then the first word
1198 (which will be passed in r3) is used for struct return address.
1199 In that case we should advance one word and start from r4
1200 register to copy parameters. */
1203 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1209 effectively indirect call... gcc does...
1211 return_val example( float, int);
1214 float in fp0, int in r3
1215 offset of stack on overflow 8/16
1216 for varargs, must go by type.
1218 float in r3&r4, int in r5
1219 offset of stack on overflow different
1221 return in r3 or f0. If no float, must study how gcc emulates floats;
1222 pay attention to arg promotion.
1223 User may have to cast\args to handle promotion correctly
1224 since gdb won't know if prototype supplied or not.
1227 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1229 int reg_size = DEPRECATED_REGISTER_RAW_SIZE (ii + 3);
1232 type = check_typedef (VALUE_TYPE (arg));
1233 len = TYPE_LENGTH (type);
1235 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1238 /* Floating point arguments are passed in fpr's, as well as gpr's.
1239 There are 13 fpr's reserved for passing parameters. At this point
1240 there is no way we would run out of them. */
1244 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
1246 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE
1247 (tdep->ppc_fp0_regnum + 1 + f_argno)],
1248 VALUE_CONTENTS (arg),
1256 /* Argument takes more than one register. */
1257 while (argbytes < len)
1259 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0,
1261 memcpy (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)],
1262 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1263 (len - argbytes) > reg_size
1264 ? reg_size : len - argbytes);
1265 ++ii, argbytes += reg_size;
1268 goto ran_out_of_registers_for_arguments;
1275 /* Argument can fit in one register. No problem. */
1276 int adj = TARGET_BYTE_ORDER == BFD_ENDIAN_BIG ? reg_size - len : 0;
1277 memset (&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)], 0, reg_size);
1278 memcpy ((char *)&deprecated_registers[DEPRECATED_REGISTER_BYTE (ii + 3)] + adj,
1279 VALUE_CONTENTS (arg), len);
1284 ran_out_of_registers_for_arguments:
1286 saved_sp = read_sp ();
1288 /* Location for 8 parameters are always reserved. */
1291 /* Another six words for back chain, TOC register, link register, etc. */
1294 /* Stack pointer must be quadword aligned. */
1297 /* If there are more arguments, allocate space for them in
1298 the stack, then push them starting from the ninth one. */
1300 if ((argno < nargs) || argbytes)
1306 space += ((len - argbytes + 3) & -4);
1312 for (; jj < nargs; ++jj)
1314 struct value *val = args[jj];
1315 space += ((TYPE_LENGTH (VALUE_TYPE (val))) + 3) & -4;
1318 /* Add location required for the rest of the parameters. */
1319 space = (space + 15) & -16;
1322 /* This is another instance we need to be concerned about
1323 securing our stack space. If we write anything underneath %sp
1324 (r1), we might conflict with the kernel who thinks he is free
1325 to use this area. So, update %sp first before doing anything
1328 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1330 /* If the last argument copied into the registers didn't fit there
1331 completely, push the rest of it into stack. */
1335 write_memory (sp + 24 + (ii * 4),
1336 ((char *) VALUE_CONTENTS (arg)) + argbytes,
1339 ii += ((len - argbytes + 3) & -4) / 4;
1342 /* Push the rest of the arguments into stack. */
1343 for (; argno < nargs; ++argno)
1347 type = check_typedef (VALUE_TYPE (arg));
1348 len = TYPE_LENGTH (type);
1351 /* Float types should be passed in fpr's, as well as in the
1353 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
1358 "Fatal Error: a floating point parameter #%d with a size > 8 is found!\n", argno);
1360 memcpy (&(deprecated_registers
1361 [DEPRECATED_REGISTER_BYTE
1362 (tdep->ppc_fp0_regnum + 1 + f_argno)]),
1363 VALUE_CONTENTS (arg),
1368 write_memory (sp + 24 + (ii * 4), (char *) VALUE_CONTENTS (arg), len);
1369 ii += ((len + 3) & -4) / 4;
1373 /* Set the stack pointer. According to the ABI, the SP is meant to
1374 be set _before_ the corresponding stack space is used. On AIX,
1375 this even applies when the target has been completely stopped!
1376 Not doing this can lead to conflicts with the kernel which thinks
1377 that it still has control over this not-yet-allocated stack
1379 regcache_raw_write_signed (regcache, SP_REGNUM, sp);
1381 /* Set back chain properly. */
1382 store_unsigned_integer (tmp_buffer, 4, saved_sp);
1383 write_memory (sp, tmp_buffer, 4);
1385 /* Point the inferior function call's return address at the dummy's
1387 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
1389 /* Set the TOC register, get the value from the objfile reader
1390 which, in turn, gets it from the VMAP table. */
1391 if (rs6000_find_toc_address_hook != NULL)
1393 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
1394 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
1397 target_store_registers (-1);
1401 /* PowerOpen always puts structures in memory. Vectors, which were
1402 added later, do get returned in a register though. */
1405 rs6000_use_struct_convention (int gcc_p, struct type *value_type)
1407 if ((TYPE_LENGTH (value_type) == 16 || TYPE_LENGTH (value_type) == 8)
1408 && TYPE_VECTOR (value_type))
1414 rs6000_extract_return_value (struct type *valtype, char *regbuf, char *valbuf)
1417 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1419 if (TYPE_CODE (valtype) == TYPE_CODE_FLT)
1422 /* floats and doubles are returned in fpr1. fpr's have a size of 8 bytes.
1423 We need to truncate the return value into float size (4 byte) if
1426 convert_typed_floating (®buf[DEPRECATED_REGISTER_BYTE
1427 (tdep->ppc_fp0_regnum + 1)],
1428 builtin_type_double,
1432 else if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY
1433 && TYPE_LENGTH (valtype) == 16
1434 && TYPE_VECTOR (valtype))
1436 memcpy (valbuf, regbuf + DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1437 TYPE_LENGTH (valtype));
1441 /* return value is copied starting from r3. */
1442 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG
1443 && TYPE_LENGTH (valtype) < DEPRECATED_REGISTER_RAW_SIZE (3))
1444 offset = DEPRECATED_REGISTER_RAW_SIZE (3) - TYPE_LENGTH (valtype);
1447 regbuf + DEPRECATED_REGISTER_BYTE (3) + offset,
1448 TYPE_LENGTH (valtype));
1452 /* Return whether handle_inferior_event() should proceed through code
1453 starting at PC in function NAME when stepping.
1455 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
1456 handle memory references that are too distant to fit in instructions
1457 generated by the compiler. For example, if 'foo' in the following
1462 is greater than 32767, the linker might replace the lwz with a branch to
1463 somewhere in @FIX1 that does the load in 2 instructions and then branches
1464 back to where execution should continue.
1466 GDB should silently step over @FIX code, just like AIX dbx does.
1467 Unfortunately, the linker uses the "b" instruction for the branches,
1468 meaning that the link register doesn't get set. Therefore, GDB's usual
1469 step_over_function() mechanism won't work.
1471 Instead, use the IN_SOLIB_RETURN_TRAMPOLINE and SKIP_TRAMPOLINE_CODE hooks
1472 in handle_inferior_event() to skip past @FIX code. */
1475 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
1477 return name && !strncmp (name, "@FIX", 4);
1480 /* Skip code that the user doesn't want to see when stepping:
1482 1. Indirect function calls use a piece of trampoline code to do context
1483 switching, i.e. to set the new TOC table. Skip such code if we are on
1484 its first instruction (as when we have single-stepped to here).
1486 2. Skip shared library trampoline code (which is different from
1487 indirect function call trampolines).
1489 3. Skip bigtoc fixup code.
1491 Result is desired PC to step until, or NULL if we are not in
1492 code that should be skipped. */
1495 rs6000_skip_trampoline_code (CORE_ADDR pc)
1497 unsigned int ii, op;
1499 CORE_ADDR solib_target_pc;
1500 struct minimal_symbol *msymbol;
1502 static unsigned trampoline_code[] =
1504 0x800b0000, /* l r0,0x0(r11) */
1505 0x90410014, /* st r2,0x14(r1) */
1506 0x7c0903a6, /* mtctr r0 */
1507 0x804b0004, /* l r2,0x4(r11) */
1508 0x816b0008, /* l r11,0x8(r11) */
1509 0x4e800420, /* bctr */
1510 0x4e800020, /* br */
1514 /* Check for bigtoc fixup code. */
1515 msymbol = lookup_minimal_symbol_by_pc (pc);
1516 if (msymbol && rs6000_in_solib_return_trampoline (pc, DEPRECATED_SYMBOL_NAME (msymbol)))
1518 /* Double-check that the third instruction from PC is relative "b". */
1519 op = read_memory_integer (pc + 8, 4);
1520 if ((op & 0xfc000003) == 0x48000000)
1522 /* Extract bits 6-29 as a signed 24-bit relative word address and
1523 add it to the containing PC. */
1524 rel = ((int)(op << 6) >> 6);
1525 return pc + 8 + rel;
1529 /* If pc is in a shared library trampoline, return its target. */
1530 solib_target_pc = find_solib_trampoline_target (pc);
1531 if (solib_target_pc)
1532 return solib_target_pc;
1534 for (ii = 0; trampoline_code[ii]; ++ii)
1536 op = read_memory_integer (pc + (ii * 4), 4);
1537 if (op != trampoline_code[ii])
1540 ii = read_register (11); /* r11 holds destination addr */
1541 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */
1545 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
1546 isn't available with that word size, return 0. */
1549 regsize (const struct reg *reg, int wordsize)
1551 return wordsize == 8 ? reg->sz64 : reg->sz32;
1554 /* Return the name of register number N, or null if no such register exists
1555 in the current architecture. */
1558 rs6000_register_name (int n)
1560 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1561 const struct reg *reg = tdep->regs + n;
1563 if (!regsize (reg, tdep->wordsize))
1568 /* Index within `registers' of the first byte of the space for
1572 rs6000_register_byte (int n)
1574 return gdbarch_tdep (current_gdbarch)->regoff[n];
1577 /* Return the number of bytes of storage in the actual machine representation
1578 for register N if that register is available, else return 0. */
1581 rs6000_register_raw_size (int n)
1583 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1584 const struct reg *reg = tdep->regs + n;
1585 return regsize (reg, tdep->wordsize);
1588 /* Return the GDB type object for the "standard" data type
1589 of data in register N. */
1591 static struct type *
1592 rs6000_register_virtual_type (int n)
1594 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1595 const struct reg *reg = tdep->regs + n;
1598 return builtin_type_double;
1601 int size = regsize (reg, tdep->wordsize);
1605 return builtin_type_int0;
1607 return builtin_type_uint32;
1609 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum)
1610 return builtin_type_vec64;
1612 return builtin_type_uint64;
1615 return builtin_type_vec128;
1618 internal_error (__FILE__, __LINE__, "Register %d size %d unknown",
1624 /* Return whether register N requires conversion when moving from raw format
1627 The register format for RS/6000 floating point registers is always
1628 double, we need a conversion if the memory format is float. */
1631 rs6000_register_convertible (int n)
1633 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + n;
1637 /* Convert data from raw format for register N in buffer FROM
1638 to virtual format with type TYPE in buffer TO. */
1641 rs6000_register_convert_to_virtual (int n, struct type *type,
1642 char *from, char *to)
1644 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n))
1646 double val = deprecated_extract_floating (from, DEPRECATED_REGISTER_RAW_SIZE (n));
1647 deprecated_store_floating (to, TYPE_LENGTH (type), val);
1650 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n));
1653 /* Convert data from virtual format with type TYPE in buffer FROM
1654 to raw format for register N in buffer TO. */
1657 rs6000_register_convert_to_raw (struct type *type, int n,
1658 const char *from, char *to)
1660 if (TYPE_LENGTH (type) != DEPRECATED_REGISTER_RAW_SIZE (n))
1662 double val = deprecated_extract_floating (from, TYPE_LENGTH (type));
1663 deprecated_store_floating (to, DEPRECATED_REGISTER_RAW_SIZE (n), val);
1666 memcpy (to, from, DEPRECATED_REGISTER_RAW_SIZE (n));
1670 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
1671 int reg_nr, void *buffer)
1675 char temp_buffer[MAX_REGISTER_SIZE];
1676 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1678 if (reg_nr >= tdep->ppc_gp0_regnum
1679 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
1681 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1683 /* Build the value in the provided buffer. */
1684 /* Read the raw register of which this one is the lower portion. */
1685 regcache_raw_read (regcache, base_regnum, temp_buffer);
1686 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1688 memcpy ((char *) buffer, temp_buffer + offset, 4);
1693 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
1694 int reg_nr, const void *buffer)
1698 char temp_buffer[MAX_REGISTER_SIZE];
1699 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1701 if (reg_nr >= tdep->ppc_gp0_regnum
1702 && reg_nr < tdep->ppc_gp0_regnum + ppc_num_gprs)
1704 base_regnum = reg_nr - tdep->ppc_gp0_regnum + tdep->ppc_ev0_regnum;
1705 /* reg_nr is 32 bit here, and base_regnum is 64 bits. */
1706 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
1709 /* Let's read the value of the base register into a temporary
1710 buffer, so that overwriting the last four bytes with the new
1711 value of the pseudo will leave the upper 4 bytes unchanged. */
1712 regcache_raw_read (regcache, base_regnum, temp_buffer);
1714 /* Write as an 8 byte quantity. */
1715 memcpy (temp_buffer + offset, (char *) buffer, 4);
1716 regcache_raw_write (regcache, base_regnum, temp_buffer);
1720 /* Convert a dbx stab or Dwarf 2 register number (from `r'
1721 declaration) to a gdb REGNUM. */
1723 rs6000_dwarf2_stab_reg_to_regnum (int num)
1725 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1727 if (0 <= num && num <= 31)
1728 return tdep->ppc_gp0_regnum + num;
1729 else if (32 <= num && num <= 63)
1730 return tdep->ppc_fp0_regnum + (num - 32);
1731 else if (1200 <= num && num < 1200 + 32)
1732 return tdep->ppc_ev0_regnum + (num - 1200);
1737 return tdep->ppc_mq_regnum;
1739 return tdep->ppc_lr_regnum;
1741 return tdep->ppc_ctr_regnum;
1743 return tdep->ppc_xer_regnum;
1745 return tdep->ppc_vrsave_regnum;
1750 /* FIXME: jimb/2004-03-28: Doesn't something need to be done here
1751 for the Altivec registers, too?
1753 Looking at GCC, the headers in config/rs6000 never define a
1754 DBX_REGISTER_NUMBER macro, so the debug info uses the same
1755 numbers GCC does internally. Then, looking at the REGISTER_NAMES
1756 macro defined in config/rs6000/rs6000.h, it seems that GCC gives
1757 v0 -- v31 the numbers 77 -- 108. But we number them 119 -- 150.
1759 I don't have a way to test this ready to hand, but I noticed it
1760 and thought I should include a note. */
1764 rs6000_store_return_value (struct type *type, char *valbuf)
1766 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1768 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1770 /* Floating point values are returned starting from FPR1 and up.
1771 Say a double_double_double type could be returned in
1772 FPR1/FPR2/FPR3 triple. */
1774 deprecated_write_register_bytes
1775 (DEPRECATED_REGISTER_BYTE (tdep->ppc_fp0_regnum + 1),
1777 TYPE_LENGTH (type));
1778 else if (TYPE_CODE (type) == TYPE_CODE_ARRAY)
1780 if (TYPE_LENGTH (type) == 16
1781 && TYPE_VECTOR (type))
1782 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (tdep->ppc_vr0_regnum + 2),
1783 valbuf, TYPE_LENGTH (type));
1786 /* Everything else is returned in GPR3 and up. */
1787 deprecated_write_register_bytes (DEPRECATED_REGISTER_BYTE (gdbarch_tdep (current_gdbarch)->ppc_gp0_regnum + 3),
1788 valbuf, TYPE_LENGTH (type));
1791 /* Extract from an array REGBUF containing the (raw) register state
1792 the address in which a function should return its structure value,
1793 as a CORE_ADDR (or an expression that can be used as one). */
1796 rs6000_extract_struct_value_address (struct regcache *regcache)
1798 /* FIXME: cagney/2002-09-26: PR gdb/724: When making an inferior
1799 function call GDB knows the address of the struct return value
1800 and hence, should not need to call this function. Unfortunately,
1801 the current call_function_by_hand() code only saves the most
1802 recent struct address leading to occasional calls. The code
1803 should instead maintain a stack of such addresses (in the dummy
1805 /* NOTE: cagney/2002-09-26: Return 0 which indicates that we've
1806 really got no idea where the return value is being stored. While
1807 r3, on function entry, contained the address it will have since
1808 been reused (scratch) and hence wouldn't be valid */
1812 /* Hook called when a new child process is started. */
1815 rs6000_create_inferior (int pid)
1817 if (rs6000_set_host_arch_hook)
1818 rs6000_set_host_arch_hook (pid);
1821 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
1823 Usually a function pointer's representation is simply the address
1824 of the function. On the RS/6000 however, a function pointer is
1825 represented by a pointer to a TOC entry. This TOC entry contains
1826 three words, the first word is the address of the function, the
1827 second word is the TOC pointer (r2), and the third word is the
1828 static chain value. Throughout GDB it is currently assumed that a
1829 function pointer contains the address of the function, which is not
1830 easy to fix. In addition, the conversion of a function address to
1831 a function pointer would require allocation of a TOC entry in the
1832 inferior's memory space, with all its drawbacks. To be able to
1833 call C++ virtual methods in the inferior (which are called via
1834 function pointers), find_function_addr uses this function to get the
1835 function address from a function pointer. */
1837 /* Return real function address if ADDR (a function pointer) is in the data
1838 space and is therefore a special function pointer. */
1841 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
1843 struct target_ops *targ)
1845 struct obj_section *s;
1847 s = find_pc_section (addr);
1848 if (s && s->the_bfd_section->flags & SEC_CODE)
1851 /* ADDR is in the data space, so it's a special function pointer. */
1852 return read_memory_addr (addr, gdbarch_tdep (current_gdbarch)->wordsize);
1856 /* Handling the various POWER/PowerPC variants. */
1859 /* The arrays here called registers_MUMBLE hold information about available
1862 For each family of PPC variants, I've tried to isolate out the
1863 common registers and put them up front, so that as long as you get
1864 the general family right, GDB will correctly identify the registers
1865 common to that family. The common register sets are:
1867 For the 60x family: hid0 hid1 iabr dabr pir
1869 For the 505 and 860 family: eie eid nri
1871 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi
1872 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1
1875 Most of these register groups aren't anything formal. I arrived at
1876 them by looking at the registers that occurred in more than one
1879 Note: kevinb/2002-04-30: Support for the fpscr register was added
1880 during April, 2002. Slot 70 is being used for PowerPC and slot 71
1881 for Power. For PowerPC, slot 70 was unused and was already in the
1882 PPC_UISA_SPRS which is ideally where fpscr should go. For Power,
1883 slot 70 was being used for "mq", so the next available slot (71)
1884 was chosen. It would have been nice to be able to make the
1885 register numbers the same across processor cores, but this wasn't
1886 possible without either 1) renumbering some registers for some
1887 processors or 2) assigning fpscr to a really high slot that's
1888 larger than any current register number. Doing (1) is bad because
1889 existing stubs would break. Doing (2) is undesirable because it
1890 would introduce a really large gap between fpscr and the rest of
1891 the registers for most processors. */
1893 /* Convenience macros for populating register arrays. */
1895 /* Within another macro, convert S to a string. */
1899 /* Return a struct reg defining register NAME that's 32 bits on 32-bit systems
1900 and 64 bits on 64-bit systems. */
1901 #define R(name) { STR(name), 4, 8, 0, 0 }
1903 /* Return a struct reg defining register NAME that's 32 bits on all
1905 #define R4(name) { STR(name), 4, 4, 0, 0 }
1907 /* Return a struct reg defining register NAME that's 64 bits on all
1909 #define R8(name) { STR(name), 8, 8, 0, 0 }
1911 /* Return a struct reg defining register NAME that's 128 bits on all
1913 #define R16(name) { STR(name), 16, 16, 0, 0 }
1915 /* Return a struct reg defining floating-point register NAME. */
1916 #define F(name) { STR(name), 8, 8, 1, 0 }
1918 /* Return a struct reg defining a pseudo register NAME. */
1919 #define P(name) { STR(name), 4, 8, 0, 1}
1921 /* Return a struct reg defining register NAME that's 32 bits on 32-bit
1922 systems and that doesn't exist on 64-bit systems. */
1923 #define R32(name) { STR(name), 4, 0, 0, 0 }
1925 /* Return a struct reg defining register NAME that's 64 bits on 64-bit
1926 systems and that doesn't exist on 32-bit systems. */
1927 #define R64(name) { STR(name), 0, 8, 0, 0 }
1929 /* Return a struct reg placeholder for a register that doesn't exist. */
1930 #define R0 { 0, 0, 0, 0, 0 }
1932 /* UISA registers common across all architectures, including POWER. */
1934 #define COMMON_UISA_REGS \
1935 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1936 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1937 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1938 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1939 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \
1940 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \
1941 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \
1942 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \
1943 /* 64 */ R(pc), R(ps)
1945 #define COMMON_UISA_NOFP_REGS \
1946 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \
1947 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \
1948 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \
1949 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \
1950 /* 32 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1951 /* 40 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1952 /* 48 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1953 /* 56 */ R0, R0, R0, R0, R0, R0, R0, R0, \
1954 /* 64 */ R(pc), R(ps)
1956 /* UISA-level SPRs for PowerPC. */
1957 #define PPC_UISA_SPRS \
1958 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R4(fpscr)
1960 /* UISA-level SPRs for PowerPC without floating point support. */
1961 #define PPC_UISA_NOFP_SPRS \
1962 /* 66 */ R4(cr), R(lr), R(ctr), R4(xer), R0
1964 /* Segment registers, for PowerPC. */
1965 #define PPC_SEGMENT_REGS \
1966 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \
1967 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \
1968 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \
1969 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15)
1971 /* OEA SPRs for PowerPC. */
1972 #define PPC_OEA_SPRS \
1974 /* 88 */ R(ibat0u), R(ibat0l), R(ibat1u), R(ibat1l), \
1975 /* 92 */ R(ibat2u), R(ibat2l), R(ibat3u), R(ibat3l), \
1976 /* 96 */ R(dbat0u), R(dbat0l), R(dbat1u), R(dbat1l), \
1977 /* 100 */ R(dbat2u), R(dbat2l), R(dbat3u), R(dbat3l), \
1978 /* 104 */ R(sdr1), R64(asr), R(dar), R4(dsisr), \
1979 /* 108 */ R(sprg0), R(sprg1), R(sprg2), R(sprg3), \
1980 /* 112 */ R(srr0), R(srr1), R(tbl), R(tbu), \
1981 /* 116 */ R4(dec), R(dabr), R4(ear)
1983 /* AltiVec registers. */
1984 #define PPC_ALTIVEC_REGS \
1985 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \
1986 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \
1987 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \
1988 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \
1989 /*151*/R4(vscr), R4(vrsave)
1991 /* Vectors of hi-lo general purpose registers. */
1992 #define PPC_EV_REGS \
1993 /* 0*/R8(ev0), R8(ev1), R8(ev2), R8(ev3), R8(ev4), R8(ev5), R8(ev6), R8(ev7), \
1994 /* 8*/R8(ev8), R8(ev9), R8(ev10),R8(ev11),R8(ev12),R8(ev13),R8(ev14),R8(ev15), \
1995 /*16*/R8(ev16),R8(ev17),R8(ev18),R8(ev19),R8(ev20),R8(ev21),R8(ev22),R8(ev23), \
1996 /*24*/R8(ev24),R8(ev25),R8(ev26),R8(ev27),R8(ev28),R8(ev29),R8(ev30),R8(ev31)
1998 /* Lower half of the EV registers. */
1999 #define PPC_GPRS_PSEUDO_REGS \
2000 /* 0 */ P(r0), P(r1), P(r2), P(r3), P(r4), P(r5), P(r6), P(r7), \
2001 /* 8 */ P(r8), P(r9), P(r10),P(r11),P(r12),P(r13),P(r14),P(r15), \
2002 /* 16 */ P(r16),P(r17),P(r18),P(r19),P(r20),P(r21),P(r22),P(r23), \
2003 /* 24 */ P(r24),P(r25),P(r26),P(r27),P(r28),P(r29),P(r30),P(r31)
2005 /* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover
2006 user-level SPR's. */
2007 static const struct reg registers_power[] =
2010 /* 66 */ R4(cnd), R(lr), R(cnt), R4(xer), R4(mq),
2014 /* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only
2015 view of the PowerPC. */
2016 static const struct reg registers_powerpc[] =
2023 /* PowerPC UISA - a PPC processor as viewed by user-level
2024 code, but without floating point registers. */
2025 static const struct reg registers_powerpc_nofp[] =
2027 COMMON_UISA_NOFP_REGS,
2031 /* IBM PowerPC 403. */
2032 static const struct reg registers_403[] =
2038 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2039 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2040 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2041 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2042 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2043 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2)
2046 /* IBM PowerPC 403GC. */
2047 static const struct reg registers_403GC[] =
2053 /* 119 */ R(icdbdr), R(esr), R(dear), R(evpr),
2054 /* 123 */ R(cdbcr), R(tsr), R(tcr), R(pit),
2055 /* 127 */ R(tbhi), R(tblo), R(srr2), R(srr3),
2056 /* 131 */ R(dbsr), R(dbcr), R(iac1), R(iac2),
2057 /* 135 */ R(dac1), R(dac2), R(dccr), R(iccr),
2058 /* 139 */ R(pbl1), R(pbu1), R(pbl2), R(pbu2),
2059 /* 143 */ R(zpr), R(pid), R(sgr), R(dcwr),
2060 /* 147 */ R(tbhu), R(tblu)
2063 /* Motorola PowerPC 505. */
2064 static const struct reg registers_505[] =
2070 /* 119 */ R(eie), R(eid), R(nri)
2073 /* Motorola PowerPC 860 or 850. */
2074 static const struct reg registers_860[] =
2080 /* 119 */ R(eie), R(eid), R(nri), R(cmpa),
2081 /* 123 */ R(cmpb), R(cmpc), R(cmpd), R(icr),
2082 /* 127 */ R(der), R(counta), R(countb), R(cmpe),
2083 /* 131 */ R(cmpf), R(cmpg), R(cmph), R(lctrl1),
2084 /* 135 */ R(lctrl2), R(ictrl), R(bar), R(ic_cst),
2085 /* 139 */ R(ic_adr), R(ic_dat), R(dc_cst), R(dc_adr),
2086 /* 143 */ R(dc_dat), R(dpdr), R(dpir), R(immr),
2087 /* 147 */ R(mi_ctr), R(mi_ap), R(mi_epn), R(mi_twc),
2088 /* 151 */ R(mi_rpn), R(md_ctr), R(m_casid), R(md_ap),
2089 /* 155 */ R(md_epn), R(md_twb), R(md_twc), R(md_rpn),
2090 /* 159 */ R(m_tw), R(mi_dbcam), R(mi_dbram0), R(mi_dbram1),
2091 /* 163 */ R(md_dbcam), R(md_dbram0), R(md_dbram1)
2094 /* Motorola PowerPC 601. Note that the 601 has different register numbers
2095 for reading and writing RTCU and RTCL. However, how one reads and writes a
2096 register is the stub's problem. */
2097 static const struct reg registers_601[] =
2103 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2104 /* 123 */ R(pir), R(mq), R(rtcu), R(rtcl)
2107 /* Motorola PowerPC 602. */
2108 static const struct reg registers_602[] =
2114 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2115 /* 123 */ R0, R(tcr), R(ibr), R(esassr),
2116 /* 127 */ R(sebr), R(ser), R(sp), R(lt)
2119 /* Motorola/IBM PowerPC 603 or 603e. */
2120 static const struct reg registers_603[] =
2126 /* 119 */ R(hid0), R(hid1), R(iabr), R0,
2127 /* 123 */ R0, R(dmiss), R(dcmp), R(hash1),
2128 /* 127 */ R(hash2), R(imiss), R(icmp), R(rpa)
2131 /* Motorola PowerPC 604 or 604e. */
2132 static const struct reg registers_604[] =
2138 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2139 /* 123 */ R(pir), R(mmcr0), R(pmc1), R(pmc2),
2140 /* 127 */ R(sia), R(sda)
2143 /* Motorola/IBM PowerPC 750 or 740. */
2144 static const struct reg registers_750[] =
2150 /* 119 */ R(hid0), R(hid1), R(iabr), R(dabr),
2151 /* 123 */ R0, R(ummcr0), R(upmc1), R(upmc2),
2152 /* 127 */ R(usia), R(ummcr1), R(upmc3), R(upmc4),
2153 /* 131 */ R(mmcr0), R(pmc1), R(pmc2), R(sia),
2154 /* 135 */ R(mmcr1), R(pmc3), R(pmc4), R(l2cr),
2155 /* 139 */ R(ictc), R(thrm1), R(thrm2), R(thrm3)
2159 /* Motorola PowerPC 7400. */
2160 static const struct reg registers_7400[] =
2162 /* gpr0-gpr31, fpr0-fpr31 */
2164 /* cr, lr, ctr, xer, fpscr */
2169 /* vr0-vr31, vrsave, vscr */
2171 /* FIXME? Add more registers? */
2174 /* Motorola e500. */
2175 static const struct reg registers_e500[] =
2178 /* cr, lr, ctr, xer, "" */
2182 R8(acc), R(spefscr),
2183 /* NOTE: Add new registers here the end of the raw register
2184 list and just before the first pseudo register. */
2186 PPC_GPRS_PSEUDO_REGS
2189 /* Information about a particular processor variant. */
2193 /* Name of this variant. */
2196 /* English description of the variant. */
2199 /* bfd_arch_info.arch corresponding to variant. */
2200 enum bfd_architecture arch;
2202 /* bfd_arch_info.mach corresponding to variant. */
2205 /* Number of real registers. */
2208 /* Number of pseudo registers. */
2211 /* Number of total registers (the sum of nregs and npregs). */
2214 /* Table of register names; registers[R] is the name of the register
2216 const struct reg *regs;
2219 #define tot_num_registers(list) (sizeof (list) / sizeof((list)[0]))
2222 num_registers (const struct reg *reg_list, int num_tot_regs)
2227 for (i = 0; i < num_tot_regs; i++)
2228 if (!reg_list[i].pseudo)
2235 num_pseudo_registers (const struct reg *reg_list, int num_tot_regs)
2240 for (i = 0; i < num_tot_regs; i++)
2241 if (reg_list[i].pseudo)
2247 /* Information in this table comes from the following web sites:
2248 IBM: http://www.chips.ibm.com:80/products/embedded/
2249 Motorola: http://www.mot.com/SPS/PowerPC/
2251 I'm sure I've got some of the variant descriptions not quite right.
2252 Please report any inaccuracies you find to GDB's maintainer.
2254 If you add entries to this table, please be sure to allow the new
2255 value as an argument to the --with-cpu flag, in configure.in. */
2257 static struct variant variants[] =
2260 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2261 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc),
2263 {"power", "POWER user-level", bfd_arch_rs6000,
2264 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power),
2266 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2267 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403),
2269 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2270 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601),
2272 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2273 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602),
2275 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2276 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603),
2278 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2279 604, -1, -1, tot_num_registers (registers_604),
2281 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2282 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC),
2284 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2285 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505),
2287 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2288 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860),
2290 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2291 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750),
2293 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2294 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400),
2296 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2297 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500),
2301 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2302 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc),
2304 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2305 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc),
2307 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2308 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc),
2310 {"a35", "PowerPC A35", bfd_arch_powerpc,
2311 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc),
2313 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2314 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc),
2316 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2317 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc),
2320 /* FIXME: I haven't checked the register sets of the following. */
2321 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2322 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power),
2324 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2325 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power),
2327 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2328 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power),
2331 {0, 0, 0, 0, 0, 0, 0, 0}
2334 /* Initialize the number of registers and pseudo registers in each variant. */
2337 init_variants (void)
2341 for (v = variants; v->name; v++)
2344 v->nregs = num_registers (v->regs, v->num_tot_regs);
2345 if (v->npregs == -1)
2346 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs);
2350 /* Return the variant corresponding to architecture ARCH and machine number
2351 MACH. If no such variant exists, return null. */
2353 static const struct variant *
2354 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2356 const struct variant *v;
2358 for (v = variants; v->name; v++)
2359 if (arch == v->arch && mach == v->mach)
2366 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2368 if (TARGET_BYTE_ORDER == BFD_ENDIAN_BIG)
2369 return print_insn_big_powerpc (memaddr, info);
2371 return print_insn_little_powerpc (memaddr, info);
2375 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2377 return frame_unwind_register_unsigned (next_frame, PC_REGNUM);
2380 static struct frame_id
2381 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2383 return frame_id_build (frame_unwind_register_unsigned (next_frame,
2385 frame_pc_unwind (next_frame));
2388 struct rs6000_frame_cache
2391 CORE_ADDR initial_sp;
2392 struct trad_frame_saved_reg *saved_regs;
2395 static struct rs6000_frame_cache *
2396 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2398 struct rs6000_frame_cache *cache;
2399 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2400 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2401 struct rs6000_framedata fdata;
2402 int wordsize = tdep->wordsize;
2404 if ((*this_cache) != NULL)
2405 return (*this_cache);
2406 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2407 (*this_cache) = cache;
2408 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2410 skip_prologue (frame_func_unwind (next_frame), frame_pc_unwind (next_frame),
2413 /* If there were any saved registers, figure out parent's stack
2415 /* The following is true only if the frame doesn't have a call to
2418 if (fdata.saved_fpr == 0
2419 && fdata.saved_gpr == 0
2420 && fdata.saved_vr == 0
2421 && fdata.saved_ev == 0
2422 && fdata.lr_offset == 0
2423 && fdata.cr_offset == 0
2424 && fdata.vr_offset == 0
2425 && fdata.ev_offset == 0)
2426 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2429 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2430 address of the current frame. Things might be easier if the
2431 ->frame pointed to the outer-most address of the frame. In
2432 the mean time, the address of the prev frame is used as the
2433 base address of this frame. */
2434 cache->base = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2435 if (!fdata.frameless)
2436 /* Frameless really means stackless. */
2437 cache->base = read_memory_addr (cache->base, wordsize);
2439 trad_frame_set_value (cache->saved_regs, SP_REGNUM, cache->base);
2441 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2442 All fpr's from saved_fpr to fp31 are saved. */
2444 if (fdata.saved_fpr >= 0)
2447 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
2448 for (i = fdata.saved_fpr; i < 32; i++)
2450 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2455 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2456 All gpr's from saved_gpr to gpr31 are saved. */
2458 if (fdata.saved_gpr >= 0)
2461 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
2462 for (i = fdata.saved_gpr; i < 32; i++)
2464 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2465 gpr_addr += wordsize;
2469 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2470 All vr's from saved_vr to vr31 are saved. */
2471 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2473 if (fdata.saved_vr >= 0)
2476 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2477 for (i = fdata.saved_vr; i < 32; i++)
2479 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2480 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2485 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2486 All vr's from saved_ev to ev31 are saved. ????? */
2487 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
2489 if (fdata.saved_ev >= 0)
2492 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
2493 for (i = fdata.saved_ev; i < 32; i++)
2495 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2496 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2497 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2502 /* If != 0, fdata.cr_offset is the offset from the frame that
2504 if (fdata.cr_offset != 0)
2505 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2507 /* If != 0, fdata.lr_offset is the offset from the frame that
2509 if (fdata.lr_offset != 0)
2510 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2511 /* The PC is found in the link register. */
2512 cache->saved_regs[PC_REGNUM] = cache->saved_regs[tdep->ppc_lr_regnum];
2514 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2515 holds the VRSAVE. */
2516 if (fdata.vrsave_offset != 0)
2517 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2519 if (fdata.alloca_reg < 0)
2520 /* If no alloca register used, then fi->frame is the value of the
2521 %sp for this frame, and it is good enough. */
2522 cache->initial_sp = frame_unwind_register_unsigned (next_frame, SP_REGNUM);
2524 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
2531 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
2532 struct frame_id *this_id)
2534 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2536 (*this_id) = frame_id_build (info->base, frame_func_unwind (next_frame));
2540 rs6000_frame_prev_register (struct frame_info *next_frame,
2542 int regnum, int *optimizedp,
2543 enum lval_type *lvalp, CORE_ADDR *addrp,
2544 int *realnump, void *valuep)
2546 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2548 trad_frame_prev_register (next_frame, info->saved_regs, regnum,
2549 optimizedp, lvalp, addrp, realnump, valuep);
2552 static const struct frame_unwind rs6000_frame_unwind =
2555 rs6000_frame_this_id,
2556 rs6000_frame_prev_register
2559 static const struct frame_unwind *
2560 rs6000_frame_sniffer (struct frame_info *next_frame)
2562 return &rs6000_frame_unwind;
2568 rs6000_frame_base_address (struct frame_info *next_frame,
2571 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
2573 return info->initial_sp;
2576 static const struct frame_base rs6000_frame_base = {
2577 &rs6000_frame_unwind,
2578 rs6000_frame_base_address,
2579 rs6000_frame_base_address,
2580 rs6000_frame_base_address
2583 static const struct frame_base *
2584 rs6000_frame_base_sniffer (struct frame_info *next_frame)
2586 return &rs6000_frame_base;
2589 /* Initialize the current architecture based on INFO. If possible, re-use an
2590 architecture from ARCHES, which is a list of architectures already created
2591 during this debugging session.
2593 Called e.g. at program startup, when reading a core file, and when reading
2596 static struct gdbarch *
2597 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2599 struct gdbarch *gdbarch;
2600 struct gdbarch_tdep *tdep;
2601 int wordsize, from_xcoff_exec, from_elf_exec, power, i, off;
2603 const struct variant *v;
2604 enum bfd_architecture arch;
2610 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
2611 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
2613 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
2614 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2616 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
2618 /* Check word size. If INFO is from a binary file, infer it from
2619 that, else choose a likely default. */
2620 if (from_xcoff_exec)
2622 if (bfd_xcoff_is_xcoff64 (info.abfd))
2627 else if (from_elf_exec)
2629 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
2636 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
2637 wordsize = info.bfd_arch_info->bits_per_word /
2638 info.bfd_arch_info->bits_per_byte;
2643 /* Find a candidate among extant architectures. */
2644 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2646 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2648 /* Word size in the various PowerPC bfd_arch_info structs isn't
2649 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
2650 separate word size check. */
2651 tdep = gdbarch_tdep (arches->gdbarch);
2652 if (tdep && tdep->wordsize == wordsize)
2653 return arches->gdbarch;
2656 /* None found, create a new architecture from INFO, whose bfd_arch_info
2657 validity depends on the source:
2658 - executable useless
2659 - rs6000_host_arch() good
2661 - "set arch" trust blindly
2662 - GDB startup useless but harmless */
2664 if (!from_xcoff_exec)
2666 arch = info.bfd_arch_info->arch;
2667 mach = info.bfd_arch_info->mach;
2671 arch = bfd_arch_powerpc;
2672 bfd_default_set_arch_mach (&abfd, arch, 0);
2673 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2674 mach = info.bfd_arch_info->mach;
2676 tdep = xmalloc (sizeof (struct gdbarch_tdep));
2677 tdep->wordsize = wordsize;
2679 /* For e500 executables, the apuinfo section is of help here. Such
2680 section contains the identifier and revision number of each
2681 Application-specific Processing Unit that is present on the
2682 chip. The content of the section is determined by the assembler
2683 which looks at each instruction and determines which unit (and
2684 which version of it) can execute it. In our case we just look for
2685 the existance of the section. */
2689 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
2692 arch = info.bfd_arch_info->arch;
2693 mach = bfd_mach_ppc_e500;
2694 bfd_default_set_arch_mach (&abfd, arch, mach);
2695 info.bfd_arch_info = bfd_get_arch_info (&abfd);
2699 gdbarch = gdbarch_alloc (&info, tdep);
2700 power = arch == bfd_arch_rs6000;
2702 /* Initialize the number of real and pseudo registers in each variant. */
2705 /* Choose variant. */
2706 v = find_variant_by_arch (arch, mach);
2710 tdep->regs = v->regs;
2712 tdep->ppc_gp0_regnum = 0;
2713 tdep->ppc_toc_regnum = 2;
2714 tdep->ppc_ps_regnum = 65;
2715 tdep->ppc_cr_regnum = 66;
2716 tdep->ppc_lr_regnum = 67;
2717 tdep->ppc_ctr_regnum = 68;
2718 tdep->ppc_xer_regnum = 69;
2719 if (v->mach == bfd_mach_ppc_601)
2720 tdep->ppc_mq_regnum = 124;
2722 tdep->ppc_mq_regnum = 70;
2724 tdep->ppc_mq_regnum = -1;
2725 tdep->ppc_fp0_regnum = 32;
2726 tdep->ppc_fpscr_regnum = power ? 71 : 70;
2728 set_gdbarch_pc_regnum (gdbarch, 64);
2729 set_gdbarch_sp_regnum (gdbarch, 1);
2730 set_gdbarch_deprecated_fp_regnum (gdbarch, 1);
2731 if (sysv_abi && wordsize == 8)
2732 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
2733 else if (sysv_abi && wordsize == 4)
2734 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
2737 set_gdbarch_deprecated_extract_return_value (gdbarch, rs6000_extract_return_value);
2738 set_gdbarch_deprecated_store_return_value (gdbarch, rs6000_store_return_value);
2741 if (v->arch == bfd_arch_powerpc)
2745 tdep->ppc_vr0_regnum = 71;
2746 tdep->ppc_vrsave_regnum = 104;
2747 tdep->ppc_ev0_regnum = -1;
2748 tdep->ppc_ev31_regnum = -1;
2750 case bfd_mach_ppc_7400:
2751 tdep->ppc_vr0_regnum = 119;
2752 tdep->ppc_vrsave_regnum = 152;
2753 tdep->ppc_ev0_regnum = -1;
2754 tdep->ppc_ev31_regnum = -1;
2756 case bfd_mach_ppc_e500:
2757 tdep->ppc_gp0_regnum = 41;
2758 tdep->ppc_toc_regnum = -1;
2759 tdep->ppc_ps_regnum = 1;
2760 tdep->ppc_cr_regnum = 2;
2761 tdep->ppc_lr_regnum = 3;
2762 tdep->ppc_ctr_regnum = 4;
2763 tdep->ppc_xer_regnum = 5;
2764 tdep->ppc_ev0_regnum = 7;
2765 tdep->ppc_ev31_regnum = 38;
2766 set_gdbarch_pc_regnum (gdbarch, 0);
2767 set_gdbarch_sp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
2768 set_gdbarch_deprecated_fp_regnum (gdbarch, tdep->ppc_gp0_regnum + 1);
2769 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
2770 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
2773 tdep->ppc_vr0_regnum = -1;
2774 tdep->ppc_vrsave_regnum = -1;
2775 tdep->ppc_ev0_regnum = -1;
2776 tdep->ppc_ev31_regnum = -1;
2780 /* Sanity check on registers. */
2781 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0);
2783 /* Set lr_frame_offset. */
2785 tdep->lr_frame_offset = 16;
2787 tdep->lr_frame_offset = 4;
2789 tdep->lr_frame_offset = 8;
2791 /* Calculate byte offsets in raw register array. */
2792 tdep->regoff = xmalloc (v->num_tot_regs * sizeof (int));
2793 for (i = off = 0; i < v->num_tot_regs; i++)
2795 tdep->regoff[i] = off;
2796 off += regsize (v->regs + i, wordsize);
2799 /* Select instruction printer. */
2801 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
2803 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
2805 set_gdbarch_write_pc (gdbarch, generic_target_write_pc);
2807 set_gdbarch_num_regs (gdbarch, v->nregs);
2808 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs);
2809 set_gdbarch_register_name (gdbarch, rs6000_register_name);
2810 set_gdbarch_deprecated_register_size (gdbarch, wordsize);
2811 set_gdbarch_deprecated_register_bytes (gdbarch, off);
2812 set_gdbarch_deprecated_register_byte (gdbarch, rs6000_register_byte);
2813 set_gdbarch_deprecated_register_raw_size (gdbarch, rs6000_register_raw_size);
2814 set_gdbarch_deprecated_register_virtual_type (gdbarch, rs6000_register_virtual_type);
2816 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2817 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
2818 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2819 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
2820 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2821 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
2822 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2824 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
2826 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
2827 set_gdbarch_char_signed (gdbarch, 0);
2829 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
2830 if (sysv_abi && wordsize == 8)
2832 set_gdbarch_frame_red_zone_size (gdbarch, 288);
2833 else if (!sysv_abi && wordsize == 4)
2834 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
2835 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
2836 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
2838 set_gdbarch_frame_red_zone_size (gdbarch, 224);
2840 set_gdbarch_deprecated_register_convertible (gdbarch, rs6000_register_convertible);
2841 set_gdbarch_deprecated_register_convert_to_virtual (gdbarch, rs6000_register_convert_to_virtual);
2842 set_gdbarch_deprecated_register_convert_to_raw (gdbarch, rs6000_register_convert_to_raw);
2843 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
2844 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_stab_reg_to_regnum);
2845 /* Note: kevinb/2002-04-12: I'm not convinced that rs6000_push_arguments()
2846 is correct for the SysV ABI when the wordsize is 8, but I'm also
2847 fairly certain that ppc_sysv_abi_push_arguments() will give even
2848 worse results since it only works for 32-bit code. So, for the moment,
2849 we're better off calling rs6000_push_arguments() since it works for
2850 64-bit code. At some point in the future, this matter needs to be
2852 if (sysv_abi && wordsize == 4)
2853 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
2854 else if (sysv_abi && wordsize == 8)
2855 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
2857 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
2859 set_gdbarch_deprecated_extract_struct_value_address (gdbarch, rs6000_extract_struct_value_address);
2861 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
2862 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2863 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
2865 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
2866 for the descriptor and ".FN" for the entry-point -- a user
2867 specifying "break FN" will unexpectedly end up with a breakpoint
2868 on the descriptor and not the function. This architecture method
2869 transforms any breakpoints on descriptors into breakpoints on the
2870 corresponding entry point. */
2871 if (sysv_abi && wordsize == 8)
2872 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
2874 /* Not sure on this. FIXMEmgo */
2875 set_gdbarch_frame_args_skip (gdbarch, 8);
2878 set_gdbarch_use_struct_convention (gdbarch,
2879 rs6000_use_struct_convention);
2883 /* Handle RS/6000 function pointers (which are really function
2885 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
2886 rs6000_convert_from_func_ptr_addr);
2889 /* Helpers for function argument information. */
2890 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
2892 /* Hook in ABI-specific overrides, if they have been registered. */
2893 gdbarch_init_osabi (info, gdbarch);
2897 case GDB_OSABI_NETBSD_AOUT:
2898 case GDB_OSABI_NETBSD_ELF:
2899 case GDB_OSABI_UNKNOWN:
2900 case GDB_OSABI_LINUX:
2901 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
2902 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
2903 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
2904 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
2907 set_gdbarch_deprecated_save_dummy_frame_tos (gdbarch, generic_save_dummy_frame_tos);
2908 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
2910 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
2911 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
2912 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
2913 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
2916 if (from_xcoff_exec)
2918 /* NOTE: jimix/2003-06-09: This test should really check for
2919 GDB_OSABI_AIX when that is defined and becomes
2920 available. (Actually, once things are properly split apart,
2921 the test goes away.) */
2922 /* RS6000/AIX does not support PT_STEP. Has to be simulated. */
2923 set_gdbarch_software_single_step (gdbarch, rs6000_software_single_step);
2930 rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file)
2932 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2937 /* FIXME: Dump gdbarch_tdep. */
2940 static struct cmd_list_element *info_powerpc_cmdlist = NULL;
2943 rs6000_info_powerpc_command (char *args, int from_tty)
2945 help_list (info_powerpc_cmdlist, "info powerpc ", class_info, gdb_stdout);
2948 /* Initialization code. */
2950 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
2953 _initialize_rs6000_tdep (void)
2955 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
2956 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
2958 /* Add root prefix command for "info powerpc" commands */
2959 add_prefix_cmd ("powerpc", class_info, rs6000_info_powerpc_command,
2960 "Various POWERPC info specific commands.",
2961 &info_powerpc_cmdlist, "info powerpc ", 0, &infolist);