1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-1987, 1989, 1991-2012 Free Software Foundation,
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
44 #include "libbfd.h" /* for bfd_default_set_arch_mach */
45 #include "coff/internal.h" /* for libcoff.h */
46 #include "libcoff.h" /* for xcoff_data */
47 #include "coff/xcoff.h"
53 #include "solib-svr4.h"
56 #include "gdb_assert.h"
59 #include "trad-frame.h"
60 #include "frame-unwind.h"
61 #include "frame-base.h"
63 #include "features/rs6000/powerpc-32.c"
64 #include "features/rs6000/powerpc-altivec32.c"
65 #include "features/rs6000/powerpc-vsx32.c"
66 #include "features/rs6000/powerpc-403.c"
67 #include "features/rs6000/powerpc-403gc.c"
68 #include "features/rs6000/powerpc-405.c"
69 #include "features/rs6000/powerpc-505.c"
70 #include "features/rs6000/powerpc-601.c"
71 #include "features/rs6000/powerpc-602.c"
72 #include "features/rs6000/powerpc-603.c"
73 #include "features/rs6000/powerpc-604.c"
74 #include "features/rs6000/powerpc-64.c"
75 #include "features/rs6000/powerpc-altivec64.c"
76 #include "features/rs6000/powerpc-vsx64.c"
77 #include "features/rs6000/powerpc-7400.c"
78 #include "features/rs6000/powerpc-750.c"
79 #include "features/rs6000/powerpc-860.c"
80 #include "features/rs6000/powerpc-e500.c"
81 #include "features/rs6000/rs6000.c"
83 /* Determine if regnum is an SPE pseudo-register. */
84 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
85 && (regnum) >= (tdep)->ppc_ev0_regnum \
86 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
88 /* Determine if regnum is a decimal float pseudo-register. */
89 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
90 && (regnum) >= (tdep)->ppc_dl0_regnum \
91 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
93 /* Determine if regnum is a POWER7 VSX register. */
94 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
95 && (regnum) >= (tdep)->ppc_vsr0_regnum \
96 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
98 /* Determine if regnum is a POWER7 Extended FP register. */
99 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
100 && (regnum) >= (tdep)->ppc_efpr0_regnum \
101 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
103 /* The list of available "set powerpc ..." and "show powerpc ..."
105 static struct cmd_list_element *setpowerpccmdlist = NULL;
106 static struct cmd_list_element *showpowerpccmdlist = NULL;
108 static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
110 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
111 static const char *const powerpc_vector_strings[] =
120 /* A variable that can be configured by the user. */
121 static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
122 static const char *powerpc_vector_abi_string = "auto";
124 /* To be used by skip_prologue. */
126 struct rs6000_framedata
128 int offset; /* total size of frame --- the distance
129 by which we decrement sp to allocate
131 int saved_gpr; /* smallest # of saved gpr */
132 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
133 int saved_fpr; /* smallest # of saved fpr */
134 int saved_vr; /* smallest # of saved vr */
135 int saved_ev; /* smallest # of saved ev */
136 int alloca_reg; /* alloca register number (frame ptr) */
137 char frameless; /* true if frameless functions. */
138 char nosavedpc; /* true if pc not saved. */
139 char used_bl; /* true if link register clobbered */
140 int gpr_offset; /* offset of saved gprs from prev sp */
141 int fpr_offset; /* offset of saved fprs from prev sp */
142 int vr_offset; /* offset of saved vrs from prev sp */
143 int ev_offset; /* offset of saved evs from prev sp */
144 int lr_offset; /* offset of saved lr */
145 int lr_register; /* register of saved lr, if trustworthy */
146 int cr_offset; /* offset of saved cr */
147 int vrsave_offset; /* offset of saved vrsave register */
151 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
153 vsx_register_p (struct gdbarch *gdbarch, int regno)
155 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
156 if (tdep->ppc_vsr0_regnum < 0)
159 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
160 <= tdep->ppc_vsr0_upper_regnum + 31);
163 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
165 altivec_register_p (struct gdbarch *gdbarch, int regno)
167 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
168 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
171 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
175 /* Return true if REGNO is an SPE register, false otherwise. */
177 spe_register_p (struct gdbarch *gdbarch, int regno)
179 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
181 /* Is it a reference to EV0 -- EV31, and do we have those? */
182 if (IS_SPE_PSEUDOREG (tdep, regno))
185 /* Is it a reference to one of the raw upper GPR halves? */
186 if (tdep->ppc_ev0_upper_regnum >= 0
187 && tdep->ppc_ev0_upper_regnum <= regno
188 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
191 /* Is it a reference to the 64-bit accumulator, and do we have that? */
192 if (tdep->ppc_acc_regnum >= 0
193 && tdep->ppc_acc_regnum == regno)
196 /* Is it a reference to the SPE floating-point status and control register,
197 and do we have that? */
198 if (tdep->ppc_spefscr_regnum >= 0
199 && tdep->ppc_spefscr_regnum == regno)
206 /* Return non-zero if the architecture described by GDBARCH has
207 floating-point registers (f0 --- f31 and fpscr). */
209 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
211 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
213 return (tdep->ppc_fp0_regnum >= 0
214 && tdep->ppc_fpscr_regnum >= 0);
217 /* Return non-zero if the architecture described by GDBARCH has
218 VSX registers (vsr0 --- vsr63). */
220 ppc_vsx_support_p (struct gdbarch *gdbarch)
222 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
224 return tdep->ppc_vsr0_regnum >= 0;
227 /* Return non-zero if the architecture described by GDBARCH has
228 Altivec registers (vr0 --- vr31, vrsave and vscr). */
230 ppc_altivec_support_p (struct gdbarch *gdbarch)
232 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
234 return (tdep->ppc_vr0_regnum >= 0
235 && tdep->ppc_vrsave_regnum >= 0);
238 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
241 This is a helper function for init_sim_regno_table, constructing
242 the table mapping GDB register numbers to sim register numbers; we
243 initialize every element in that table to -1 before we start
246 set_sim_regno (int *table, int gdb_regno, int sim_regno)
248 /* Make sure we don't try to assign any given GDB register a sim
249 register number more than once. */
250 gdb_assert (table[gdb_regno] == -1);
251 table[gdb_regno] = sim_regno;
255 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
256 numbers to simulator register numbers, based on the values placed
257 in the ARCH->tdep->ppc_foo_regnum members. */
259 init_sim_regno_table (struct gdbarch *arch)
261 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
262 int total_regs = gdbarch_num_regs (arch);
263 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
265 static const char *const segment_regs[] = {
266 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
267 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
270 /* Presume that all registers not explicitly mentioned below are
271 unavailable from the sim. */
272 for (i = 0; i < total_regs; i++)
275 /* General-purpose registers. */
276 for (i = 0; i < ppc_num_gprs; i++)
277 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
279 /* Floating-point registers. */
280 if (tdep->ppc_fp0_regnum >= 0)
281 for (i = 0; i < ppc_num_fprs; i++)
282 set_sim_regno (sim_regno,
283 tdep->ppc_fp0_regnum + i,
284 sim_ppc_f0_regnum + i);
285 if (tdep->ppc_fpscr_regnum >= 0)
286 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
288 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
289 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
290 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
292 /* Segment registers. */
293 for (i = 0; i < ppc_num_srs; i++)
297 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
299 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
302 /* Altivec registers. */
303 if (tdep->ppc_vr0_regnum >= 0)
305 for (i = 0; i < ppc_num_vrs; i++)
306 set_sim_regno (sim_regno,
307 tdep->ppc_vr0_regnum + i,
308 sim_ppc_vr0_regnum + i);
310 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
311 we can treat this more like the other cases. */
312 set_sim_regno (sim_regno,
313 tdep->ppc_vr0_regnum + ppc_num_vrs,
314 sim_ppc_vscr_regnum);
316 /* vsave is a special-purpose register, so the code below handles it. */
318 /* SPE APU (E500) registers. */
319 if (tdep->ppc_ev0_upper_regnum >= 0)
320 for (i = 0; i < ppc_num_gprs; i++)
321 set_sim_regno (sim_regno,
322 tdep->ppc_ev0_upper_regnum + i,
323 sim_ppc_rh0_regnum + i);
324 if (tdep->ppc_acc_regnum >= 0)
325 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
326 /* spefscr is a special-purpose register, so the code below handles it. */
329 /* Now handle all special-purpose registers. Verify that they
330 haven't mistakenly been assigned numbers by any of the above
332 for (i = 0; i < sim_ppc_num_sprs; i++)
334 const char *spr_name = sim_spr_register_name (i);
337 if (spr_name != NULL)
338 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
341 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
345 /* Drop the initialized array into place. */
346 tdep->sim_regno = sim_regno;
350 /* Given a GDB register number REG, return the corresponding SIM
353 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
355 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
358 if (tdep->sim_regno == NULL)
359 init_sim_regno_table (gdbarch);
362 && reg <= gdbarch_num_regs (gdbarch)
363 + gdbarch_num_pseudo_regs (gdbarch));
364 sim_regno = tdep->sim_regno[reg];
369 return LEGACY_SIM_REGNO_IGNORE;
374 /* Register set support functions. */
376 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
377 Write the register to REGCACHE. */
380 ppc_supply_reg (struct regcache *regcache, int regnum,
381 const gdb_byte *regs, size_t offset, int regsize)
383 if (regnum != -1 && offset != -1)
387 struct gdbarch *gdbarch = get_regcache_arch (regcache);
388 int gdb_regsize = register_size (gdbarch, regnum);
389 if (gdb_regsize < regsize
390 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
391 offset += regsize - gdb_regsize;
393 regcache_raw_supply (regcache, regnum, regs + offset);
397 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
398 in a field REGSIZE wide. Zero pad as necessary. */
401 ppc_collect_reg (const struct regcache *regcache, int regnum,
402 gdb_byte *regs, size_t offset, int regsize)
404 if (regnum != -1 && offset != -1)
408 struct gdbarch *gdbarch = get_regcache_arch (regcache);
409 int gdb_regsize = register_size (gdbarch, regnum);
410 if (gdb_regsize < regsize)
412 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
414 memset (regs + offset, 0, regsize - gdb_regsize);
415 offset += regsize - gdb_regsize;
418 memset (regs + offset + regsize - gdb_regsize, 0,
419 regsize - gdb_regsize);
422 regcache_raw_collect (regcache, regnum, regs + offset);
427 ppc_greg_offset (struct gdbarch *gdbarch,
428 struct gdbarch_tdep *tdep,
429 const struct ppc_reg_offsets *offsets,
433 *regsize = offsets->gpr_size;
434 if (regnum >= tdep->ppc_gp0_regnum
435 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
436 return (offsets->r0_offset
437 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
439 if (regnum == gdbarch_pc_regnum (gdbarch))
440 return offsets->pc_offset;
442 if (regnum == tdep->ppc_ps_regnum)
443 return offsets->ps_offset;
445 if (regnum == tdep->ppc_lr_regnum)
446 return offsets->lr_offset;
448 if (regnum == tdep->ppc_ctr_regnum)
449 return offsets->ctr_offset;
451 *regsize = offsets->xr_size;
452 if (regnum == tdep->ppc_cr_regnum)
453 return offsets->cr_offset;
455 if (regnum == tdep->ppc_xer_regnum)
456 return offsets->xer_offset;
458 if (regnum == tdep->ppc_mq_regnum)
459 return offsets->mq_offset;
465 ppc_fpreg_offset (struct gdbarch_tdep *tdep,
466 const struct ppc_reg_offsets *offsets,
469 if (regnum >= tdep->ppc_fp0_regnum
470 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
471 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
473 if (regnum == tdep->ppc_fpscr_regnum)
474 return offsets->fpscr_offset;
480 ppc_vrreg_offset (struct gdbarch_tdep *tdep,
481 const struct ppc_reg_offsets *offsets,
484 if (regnum >= tdep->ppc_vr0_regnum
485 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
486 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
488 if (regnum == tdep->ppc_vrsave_regnum - 1)
489 return offsets->vscr_offset;
491 if (regnum == tdep->ppc_vrsave_regnum)
492 return offsets->vrsave_offset;
497 /* Supply register REGNUM in the general-purpose register set REGSET
498 from the buffer specified by GREGS and LEN to register cache
499 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
502 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
503 int regnum, const void *gregs, size_t len)
505 struct gdbarch *gdbarch = get_regcache_arch (regcache);
506 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
507 const struct ppc_reg_offsets *offsets = regset->descr;
514 int gpr_size = offsets->gpr_size;
516 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
517 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
518 i++, offset += gpr_size)
519 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
521 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
522 gregs, offsets->pc_offset, gpr_size);
523 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
524 gregs, offsets->ps_offset, gpr_size);
525 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
526 gregs, offsets->lr_offset, gpr_size);
527 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
528 gregs, offsets->ctr_offset, gpr_size);
529 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
530 gregs, offsets->cr_offset, offsets->xr_size);
531 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
532 gregs, offsets->xer_offset, offsets->xr_size);
533 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
534 gregs, offsets->mq_offset, offsets->xr_size);
538 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
539 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
542 /* Supply register REGNUM in the floating-point register set REGSET
543 from the buffer specified by FPREGS and LEN to register cache
544 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
547 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
548 int regnum, const void *fpregs, size_t len)
550 struct gdbarch *gdbarch = get_regcache_arch (regcache);
551 struct gdbarch_tdep *tdep;
552 const struct ppc_reg_offsets *offsets;
555 if (!ppc_floating_point_unit_p (gdbarch))
558 tdep = gdbarch_tdep (gdbarch);
559 offsets = regset->descr;
564 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
565 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
567 ppc_supply_reg (regcache, i, fpregs, offset, 8);
569 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
570 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
574 offset = ppc_fpreg_offset (tdep, offsets, regnum);
575 ppc_supply_reg (regcache, regnum, fpregs, offset,
576 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
579 /* Supply register REGNUM in the VSX register set REGSET
580 from the buffer specified by VSXREGS and LEN to register cache
581 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
584 ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
585 int regnum, const void *vsxregs, size_t len)
587 struct gdbarch *gdbarch = get_regcache_arch (regcache);
588 struct gdbarch_tdep *tdep;
590 if (!ppc_vsx_support_p (gdbarch))
593 tdep = gdbarch_tdep (gdbarch);
599 for (i = tdep->ppc_vsr0_upper_regnum;
600 i < tdep->ppc_vsr0_upper_regnum + 32;
602 ppc_supply_reg (regcache, i, vsxregs, 0, 8);
607 ppc_supply_reg (regcache, regnum, vsxregs, 0, 8);
610 /* Supply register REGNUM in the Altivec register set REGSET
611 from the buffer specified by VRREGS and LEN to register cache
612 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
615 ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
616 int regnum, const void *vrregs, size_t len)
618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
619 struct gdbarch_tdep *tdep;
620 const struct ppc_reg_offsets *offsets;
623 if (!ppc_altivec_support_p (gdbarch))
626 tdep = gdbarch_tdep (gdbarch);
627 offsets = regset->descr;
632 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
633 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
635 ppc_supply_reg (regcache, i, vrregs, offset, 16);
637 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
638 vrregs, offsets->vscr_offset, 4);
640 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
641 vrregs, offsets->vrsave_offset, 4);
645 offset = ppc_vrreg_offset (tdep, offsets, regnum);
646 if (regnum != tdep->ppc_vrsave_regnum
647 && regnum != tdep->ppc_vrsave_regnum - 1)
648 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
650 ppc_supply_reg (regcache, regnum,
654 /* Collect register REGNUM in the general-purpose register set
655 REGSET from register cache REGCACHE into the buffer specified by
656 GREGS and LEN. If REGNUM is -1, do this for all registers in
660 ppc_collect_gregset (const struct regset *regset,
661 const struct regcache *regcache,
662 int regnum, void *gregs, size_t len)
664 struct gdbarch *gdbarch = get_regcache_arch (regcache);
665 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
666 const struct ppc_reg_offsets *offsets = regset->descr;
673 int gpr_size = offsets->gpr_size;
675 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
676 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
677 i++, offset += gpr_size)
678 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
680 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
681 gregs, offsets->pc_offset, gpr_size);
682 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
683 gregs, offsets->ps_offset, gpr_size);
684 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
685 gregs, offsets->lr_offset, gpr_size);
686 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
687 gregs, offsets->ctr_offset, gpr_size);
688 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
689 gregs, offsets->cr_offset, offsets->xr_size);
690 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
691 gregs, offsets->xer_offset, offsets->xr_size);
692 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
693 gregs, offsets->mq_offset, offsets->xr_size);
697 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
698 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
701 /* Collect register REGNUM in the floating-point register set
702 REGSET from register cache REGCACHE into the buffer specified by
703 FPREGS and LEN. If REGNUM is -1, do this for all registers in
707 ppc_collect_fpregset (const struct regset *regset,
708 const struct regcache *regcache,
709 int regnum, void *fpregs, size_t len)
711 struct gdbarch *gdbarch = get_regcache_arch (regcache);
712 struct gdbarch_tdep *tdep;
713 const struct ppc_reg_offsets *offsets;
716 if (!ppc_floating_point_unit_p (gdbarch))
719 tdep = gdbarch_tdep (gdbarch);
720 offsets = regset->descr;
725 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
726 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
728 ppc_collect_reg (regcache, i, fpregs, offset, 8);
730 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
731 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
735 offset = ppc_fpreg_offset (tdep, offsets, regnum);
736 ppc_collect_reg (regcache, regnum, fpregs, offset,
737 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
740 /* Collect register REGNUM in the VSX register set
741 REGSET from register cache REGCACHE into the buffer specified by
742 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
746 ppc_collect_vsxregset (const struct regset *regset,
747 const struct regcache *regcache,
748 int regnum, void *vsxregs, size_t len)
750 struct gdbarch *gdbarch = get_regcache_arch (regcache);
751 struct gdbarch_tdep *tdep;
753 if (!ppc_vsx_support_p (gdbarch))
756 tdep = gdbarch_tdep (gdbarch);
762 for (i = tdep->ppc_vsr0_upper_regnum;
763 i < tdep->ppc_vsr0_upper_regnum + 32;
765 ppc_collect_reg (regcache, i, vsxregs, 0, 8);
770 ppc_collect_reg (regcache, regnum, vsxregs, 0, 8);
774 /* Collect register REGNUM in the Altivec register set
775 REGSET from register cache REGCACHE into the buffer specified by
776 VRREGS and LEN. If REGNUM is -1, do this for all registers in
780 ppc_collect_vrregset (const struct regset *regset,
781 const struct regcache *regcache,
782 int regnum, void *vrregs, size_t len)
784 struct gdbarch *gdbarch = get_regcache_arch (regcache);
785 struct gdbarch_tdep *tdep;
786 const struct ppc_reg_offsets *offsets;
789 if (!ppc_altivec_support_p (gdbarch))
792 tdep = gdbarch_tdep (gdbarch);
793 offsets = regset->descr;
798 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
799 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
801 ppc_collect_reg (regcache, i, vrregs, offset, 16);
803 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
804 vrregs, offsets->vscr_offset, 4);
806 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
807 vrregs, offsets->vrsave_offset, 4);
811 offset = ppc_vrreg_offset (tdep, offsets, regnum);
812 if (regnum != tdep->ppc_vrsave_regnum
813 && regnum != tdep->ppc_vrsave_regnum - 1)
814 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
816 ppc_collect_reg (regcache, regnum,
822 insn_changes_sp_or_jumps (unsigned long insn)
824 int opcode = (insn >> 26) & 0x03f;
825 int sd = (insn >> 21) & 0x01f;
826 int a = (insn >> 16) & 0x01f;
827 int subcode = (insn >> 1) & 0x3ff;
829 /* Changes the stack pointer. */
831 /* NOTE: There are many ways to change the value of a given register.
832 The ways below are those used when the register is R1, the SP,
833 in a funtion's epilogue. */
835 if (opcode == 31 && subcode == 444 && a == 1)
836 return 1; /* mr R1,Rn */
837 if (opcode == 14 && sd == 1)
838 return 1; /* addi R1,Rn,simm */
839 if (opcode == 58 && sd == 1)
840 return 1; /* ld R1,ds(Rn) */
842 /* Transfers control. */
848 if (opcode == 19 && subcode == 16)
850 if (opcode == 19 && subcode == 528)
851 return 1; /* bcctr */
856 /* Return true if we are in the function's epilogue, i.e. after the
857 instruction that destroyed the function's stack frame.
859 1) scan forward from the point of execution:
860 a) If you find an instruction that modifies the stack pointer
861 or transfers control (except a return), execution is not in
863 b) Stop scanning if you find a return instruction or reach the
864 end of the function or reach the hard limit for the size of
866 2) scan backward from the point of execution:
867 a) If you find an instruction that modifies the stack pointer,
868 execution *is* in an epilogue, return.
869 b) Stop scanning if you reach an instruction that transfers
870 control or the beginning of the function or reach the hard
871 limit for the size of an epilogue. */
874 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
876 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
877 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
878 bfd_byte insn_buf[PPC_INSN_SIZE];
879 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
881 struct frame_info *curfrm;
883 /* Find the search limits based on function boundaries and hard limit. */
885 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
888 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
889 if (epilogue_start < func_start) epilogue_start = func_start;
891 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
892 if (epilogue_end > func_end) epilogue_end = func_end;
894 curfrm = get_current_frame ();
896 /* Scan forward until next 'blr'. */
898 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
900 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
902 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
903 if (insn == 0x4e800020)
905 /* Assume a bctr is a tail call unless it points strictly within
907 if (insn == 0x4e800420)
909 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
910 tdep->ppc_ctr_regnum);
911 if (ctr > func_start && ctr < func_end)
916 if (insn_changes_sp_or_jumps (insn))
920 /* Scan backward until adjustment to stack pointer (R1). */
922 for (scan_pc = pc - PPC_INSN_SIZE;
923 scan_pc >= epilogue_start;
924 scan_pc -= PPC_INSN_SIZE)
926 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
928 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
929 if (insn_changes_sp_or_jumps (insn))
936 /* Get the ith function argument for the current function. */
938 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
941 return get_frame_register_unsigned (frame, 3 + argi);
944 /* Sequence of bytes for breakpoint instruction. */
946 const static unsigned char *
947 rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
950 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
951 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
953 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
954 return big_breakpoint;
956 return little_breakpoint;
959 /* Instruction masks for displaced stepping. */
960 #define BRANCH_MASK 0xfc000000
961 #define BP_MASK 0xFC0007FE
962 #define B_INSN 0x48000000
963 #define BC_INSN 0x40000000
964 #define BXL_INSN 0x4c000000
965 #define BP_INSN 0x7C000008
967 /* Fix up the state of registers and memory after having single-stepped
968 a displaced instruction. */
970 ppc_displaced_step_fixup (struct gdbarch *gdbarch,
971 struct displaced_step_closure *closure,
972 CORE_ADDR from, CORE_ADDR to,
973 struct regcache *regs)
975 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
976 /* Since we use simple_displaced_step_copy_insn, our closure is a
977 copy of the instruction. */
978 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
979 PPC_INSN_SIZE, byte_order);
981 /* Offset for non PC-relative instructions. */
982 LONGEST offset = PPC_INSN_SIZE;
984 opcode = insn & BRANCH_MASK;
987 fprintf_unfiltered (gdb_stdlog,
988 "displaced: (ppc) fixup (%s, %s)\n",
989 paddress (gdbarch, from), paddress (gdbarch, to));
992 /* Handle PC-relative branch instructions. */
993 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
997 /* Read the current PC value after the instruction has been executed
998 in a displaced location. Calculate the offset to be applied to the
999 original PC value before the displaced stepping. */
1000 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1002 offset = current_pc - to;
1004 if (opcode != BXL_INSN)
1006 /* Check for AA bit indicating whether this is an absolute
1007 addressing or PC-relative (1: absolute, 0: relative). */
1010 /* PC-relative addressing is being used in the branch. */
1011 if (debug_displaced)
1014 "displaced: (ppc) branch instruction: %s\n"
1015 "displaced: (ppc) adjusted PC from %s to %s\n",
1016 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1017 paddress (gdbarch, from + offset));
1019 regcache_cooked_write_unsigned (regs,
1020 gdbarch_pc_regnum (gdbarch),
1026 /* If we're here, it means we have a branch to LR or CTR. If the
1027 branch was taken, the offset is probably greater than 4 (the next
1028 instruction), so it's safe to assume that an offset of 4 means we
1029 did not take the branch. */
1030 if (offset == PPC_INSN_SIZE)
1031 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1032 from + PPC_INSN_SIZE);
1035 /* Check for LK bit indicating whether we should set the link
1036 register to point to the next instruction
1037 (1: Set, 0: Don't set). */
1040 /* Link register needs to be set to the next instruction's PC. */
1041 regcache_cooked_write_unsigned (regs,
1042 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1043 from + PPC_INSN_SIZE);
1044 if (debug_displaced)
1045 fprintf_unfiltered (gdb_stdlog,
1046 "displaced: (ppc) adjusted LR to %s\n",
1047 paddress (gdbarch, from + PPC_INSN_SIZE));
1051 /* Check for breakpoints in the inferior. If we've found one, place the PC
1052 right at the breakpoint instruction. */
1053 else if ((insn & BP_MASK) == BP_INSN)
1054 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1056 /* Handle any other instructions that do not fit in the categories above. */
1057 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1061 /* Always use hardware single-stepping to execute the
1062 displaced instruction. */
1064 ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1065 struct displaced_step_closure *closure)
1070 /* Instruction masks used during single-stepping of atomic sequences. */
1071 #define LWARX_MASK 0xfc0007fe
1072 #define LWARX_INSTRUCTION 0x7c000028
1073 #define LDARX_INSTRUCTION 0x7c0000A8
1074 #define STWCX_MASK 0xfc0007ff
1075 #define STWCX_INSTRUCTION 0x7c00012d
1076 #define STDCX_INSTRUCTION 0x7c0001ad
1078 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1079 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1080 is found, attempt to step through it. A breakpoint is placed at the end of
1084 ppc_deal_with_atomic_sequence (struct frame_info *frame)
1086 struct gdbarch *gdbarch = get_frame_arch (frame);
1087 struct address_space *aspace = get_frame_address_space (frame);
1088 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1089 CORE_ADDR pc = get_frame_pc (frame);
1090 CORE_ADDR breaks[2] = {-1, -1};
1092 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
1093 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1096 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1097 const int atomic_sequence_length = 16; /* Instruction sequence length. */
1098 int opcode; /* Branch instruction's OPcode. */
1099 int bc_insn_count = 0; /* Conditional branch instruction count. */
1101 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1102 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1103 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1106 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1108 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1110 loc += PPC_INSN_SIZE;
1111 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1113 /* Assume that there is at most one conditional branch in the atomic
1114 sequence. If a conditional branch is found, put a breakpoint in
1115 its destination address. */
1116 if ((insn & BRANCH_MASK) == BC_INSN)
1118 int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1119 int absolute = insn & 2;
1121 if (bc_insn_count >= 1)
1122 return 0; /* More than one conditional branch found, fallback
1123 to the standard single-step code. */
1126 breaks[1] = immediate;
1128 breaks[1] = loc + immediate;
1134 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1135 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1139 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1140 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1141 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1145 loc += PPC_INSN_SIZE;
1146 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1148 /* Insert a breakpoint right after the end of the atomic sequence. */
1151 /* Check for duplicated breakpoints. Check also for a breakpoint
1152 placed (branch instruction's destination) anywhere in sequence. */
1154 && (breaks[1] == breaks[0]
1155 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
1156 last_breakpoint = 0;
1158 /* Effectively inserts the breakpoints. */
1159 for (index = 0; index <= last_breakpoint; index++)
1160 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
1166 #define SIGNED_SHORT(x) \
1167 ((sizeof (short) == 2) \
1168 ? ((int)(short)(x)) \
1169 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1171 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1173 /* Limit the number of skipped non-prologue instructions, as the examining
1174 of the prologue is expensive. */
1175 static int max_skip_non_prologue_insns = 10;
1177 /* Return nonzero if the given instruction OP can be part of the prologue
1178 of a function and saves a parameter on the stack. FRAMEP should be
1179 set if one of the previous instructions in the function has set the
1183 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1185 /* Move parameters from argument registers to temporary register. */
1186 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1188 /* Rx must be scratch register r0. */
1189 const int rx_regno = (op >> 16) & 31;
1190 /* Ry: Only r3 - r10 are used for parameter passing. */
1191 const int ry_regno = GET_SRC_REG (op);
1193 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1195 *r0_contains_arg = 1;
1202 /* Save a General Purpose Register on stack. */
1204 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1205 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1207 /* Rx: Only r3 - r10 are used for parameter passing. */
1208 const int rx_regno = GET_SRC_REG (op);
1210 return (rx_regno >= 3 && rx_regno <= 10);
1213 /* Save a General Purpose Register on stack via the Frame Pointer. */
1216 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1217 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1218 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1220 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1221 However, the compiler sometimes uses r0 to hold an argument. */
1222 const int rx_regno = GET_SRC_REG (op);
1224 return ((rx_regno >= 3 && rx_regno <= 10)
1225 || (rx_regno == 0 && *r0_contains_arg));
1228 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1230 /* Only f2 - f8 are used for parameter passing. */
1231 const int src_regno = GET_SRC_REG (op);
1233 return (src_regno >= 2 && src_regno <= 8);
1236 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1238 /* Only f2 - f8 are used for parameter passing. */
1239 const int src_regno = GET_SRC_REG (op);
1241 return (src_regno >= 2 && src_regno <= 8);
1244 /* Not an insn that saves a parameter on stack. */
1248 /* Assuming that INSN is a "bl" instruction located at PC, return
1249 nonzero if the destination of the branch is a "blrl" instruction.
1251 This sequence is sometimes found in certain function prologues.
1252 It allows the function to load the LR register with a value that
1253 they can use to access PIC data using PC-relative offsets. */
1256 bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
1263 absolute = (int) ((insn >> 1) & 1);
1264 immediate = ((insn & ~3) << 6) >> 6;
1268 dest = pc + immediate;
1270 dest_insn = read_memory_integer (dest, 4, byte_order);
1271 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1277 /* Masks for decoding a branch-and-link (bl) instruction.
1279 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1280 The former is anded with the opcode in question; if the result of
1281 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1282 question is a ``bl'' instruction.
1284 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1285 the branch displacement. */
1287 #define BL_MASK 0xfc000001
1288 #define BL_INSTRUCTION 0x48000001
1289 #define BL_DISPLACEMENT_MASK 0x03fffffc
1291 static unsigned long
1292 rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
1294 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1298 /* Fetch the instruction and convert it to an integer. */
1299 if (target_read_memory (pc, buf, 4))
1301 op = extract_unsigned_integer (buf, 4, byte_order);
1306 /* GCC generates several well-known sequences of instructions at the begining
1307 of each function prologue when compiling with -fstack-check. If one of
1308 such sequences starts at START_PC, then return the address of the
1309 instruction immediately past this sequence. Otherwise, return START_PC. */
1312 rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
1314 CORE_ADDR pc = start_pc;
1315 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
1317 /* First possible sequence: A small number of probes.
1318 stw 0, -<some immediate>(1)
1319 [repeat this instruction any (small) number of times]. */
1321 if ((op & 0xffff0000) == 0x90010000)
1323 while ((op & 0xffff0000) == 0x90010000)
1326 op = rs6000_fetch_instruction (gdbarch, pc);
1331 /* Second sequence: A probing loop.
1332 addi 12,1,-<some immediate>
1333 lis 0,-<some immediate>
1334 [possibly ori 0,0,<some immediate>]
1338 addi 12,12,-<some immediate>
1341 [possibly one last probe: stw 0,<some immediate>(12)]. */
1345 /* addi 12,1,-<some immediate> */
1346 if ((op & 0xffff0000) != 0x39810000)
1349 /* lis 0,-<some immediate> */
1351 op = rs6000_fetch_instruction (gdbarch, pc);
1352 if ((op & 0xffff0000) != 0x3c000000)
1356 op = rs6000_fetch_instruction (gdbarch, pc);
1357 /* [possibly ori 0,0,<some immediate>] */
1358 if ((op & 0xffff0000) == 0x60000000)
1361 op = rs6000_fetch_instruction (gdbarch, pc);
1364 if (op != 0x7c0c0214)
1369 op = rs6000_fetch_instruction (gdbarch, pc);
1370 if (op != 0x7c0c0000)
1375 op = rs6000_fetch_instruction (gdbarch, pc);
1376 if ((op & 0xff9f0001) != 0x41820000)
1379 /* addi 12,12,-<some immediate> */
1381 op = rs6000_fetch_instruction (gdbarch, pc);
1382 if ((op & 0xffff0000) != 0x398c0000)
1387 op = rs6000_fetch_instruction (gdbarch, pc);
1388 if (op != 0x900c0000)
1393 op = rs6000_fetch_instruction (gdbarch, pc);
1394 if ((op & 0xfc000001) != 0x48000000)
1397 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1399 op = rs6000_fetch_instruction (gdbarch, pc);
1400 if ((op & 0xffff0000) == 0x900c0000)
1403 op = rs6000_fetch_instruction (gdbarch, pc);
1406 /* We found a valid stack-check sequence, return the new PC. */
1410 /* Third sequence: No probe; instead, a comparizon between the stack size
1411 limit (saved in a run-time global variable) and the current stack
1414 addi 0,1,-<some immediate>
1415 lis 12,__gnat_stack_limit@ha
1416 lwz 12,__gnat_stack_limit@l(12)
1419 or, with a small variant in the case of a bigger stack frame:
1420 addis 0,1,<some immediate>
1421 addic 0,0,-<some immediate>
1422 lis 12,__gnat_stack_limit@ha
1423 lwz 12,__gnat_stack_limit@l(12)
1428 /* addi 0,1,-<some immediate> */
1429 if ((op & 0xffff0000) != 0x38010000)
1431 /* small stack frame variant not recognized; try the
1432 big stack frame variant: */
1434 /* addis 0,1,<some immediate> */
1435 if ((op & 0xffff0000) != 0x3c010000)
1438 /* addic 0,0,-<some immediate> */
1440 op = rs6000_fetch_instruction (gdbarch, pc);
1441 if ((op & 0xffff0000) != 0x30000000)
1445 /* lis 12,<some immediate> */
1447 op = rs6000_fetch_instruction (gdbarch, pc);
1448 if ((op & 0xffff0000) != 0x3d800000)
1451 /* lwz 12,<some immediate>(12) */
1453 op = rs6000_fetch_instruction (gdbarch, pc);
1454 if ((op & 0xffff0000) != 0x818c0000)
1459 op = rs6000_fetch_instruction (gdbarch, pc);
1460 if ((op & 0xfffffffe) != 0x7c406008)
1463 /* We found a valid stack-check sequence, return the new PC. */
1467 /* No stack check code in our prologue, return the start_pc. */
1471 /* return pc value after skipping a function prologue and also return
1472 information about a function frame.
1474 in struct rs6000_framedata fdata:
1475 - frameless is TRUE, if function does not have a frame.
1476 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1477 - offset is the initial size of this stack frame --- the amount by
1478 which we decrement the sp to allocate the frame.
1479 - saved_gpr is the number of the first saved gpr.
1480 - saved_fpr is the number of the first saved fpr.
1481 - saved_vr is the number of the first saved vr.
1482 - saved_ev is the number of the first saved ev.
1483 - alloca_reg is the number of the register used for alloca() handling.
1485 - gpr_offset is the offset of the first saved gpr from the previous frame.
1486 - fpr_offset is the offset of the first saved fpr from the previous frame.
1487 - vr_offset is the offset of the first saved vr from the previous frame.
1488 - ev_offset is the offset of the first saved ev from the previous frame.
1489 - lr_offset is the offset of the saved lr
1490 - cr_offset is the offset of the saved cr
1491 - vrsave_offset is the offset of the saved vrsave register. */
1494 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1495 struct rs6000_framedata *fdata)
1497 CORE_ADDR orig_pc = pc;
1498 CORE_ADDR last_prologue_pc = pc;
1499 CORE_ADDR li_found_pc = 0;
1503 long vr_saved_offset = 0;
1509 int vrsave_reg = -1;
1512 int minimal_toc_loaded = 0;
1513 int prev_insn_was_prologue_insn = 1;
1514 int num_skip_non_prologue_insns = 0;
1515 int r0_contains_arg = 0;
1516 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1517 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1518 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1520 memset (fdata, 0, sizeof (struct rs6000_framedata));
1521 fdata->saved_gpr = -1;
1522 fdata->saved_fpr = -1;
1523 fdata->saved_vr = -1;
1524 fdata->saved_ev = -1;
1525 fdata->alloca_reg = -1;
1526 fdata->frameless = 1;
1527 fdata->nosavedpc = 1;
1528 fdata->lr_register = -1;
1530 pc = rs6000_skip_stack_check (gdbarch, pc);
1536 /* Sometimes it isn't clear if an instruction is a prologue
1537 instruction or not. When we encounter one of these ambiguous
1538 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1539 Otherwise, we'll assume that it really is a prologue instruction. */
1540 if (prev_insn_was_prologue_insn)
1541 last_prologue_pc = pc;
1543 /* Stop scanning if we've hit the limit. */
1547 prev_insn_was_prologue_insn = 1;
1549 /* Fetch the instruction and convert it to an integer. */
1550 if (target_read_memory (pc, buf, 4))
1552 op = extract_unsigned_integer (buf, 4, byte_order);
1554 if ((op & 0xfc1fffff) == 0x7c0802a6)
1556 /* Since shared library / PIC code, which needs to get its
1557 address at runtime, can appear to save more than one link
1571 remember just the first one, but skip over additional
1574 lr_reg = (op & 0x03e00000) >> 21;
1576 r0_contains_arg = 0;
1579 else if ((op & 0xfc1fffff) == 0x7c000026)
1581 cr_reg = (op & 0x03e00000);
1583 r0_contains_arg = 0;
1587 else if ((op & 0xfc1f0000) == 0xd8010000)
1588 { /* stfd Rx,NUM(r1) */
1589 reg = GET_SRC_REG (op);
1590 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1592 fdata->saved_fpr = reg;
1593 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1598 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1599 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1600 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1601 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1604 reg = GET_SRC_REG (op);
1605 if ((op & 0xfc1f0000) == 0xbc010000)
1606 fdata->gpr_mask |= ~((1U << reg) - 1);
1608 fdata->gpr_mask |= 1U << reg;
1609 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1611 fdata->saved_gpr = reg;
1612 if ((op & 0xfc1f0003) == 0xf8010000)
1614 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1619 else if ((op & 0xffff0000) == 0x60000000)
1622 /* Allow nops in the prologue, but do not consider them to
1623 be part of the prologue unless followed by other prologue
1625 prev_insn_was_prologue_insn = 0;
1629 else if ((op & 0xffff0000) == 0x3c000000)
1630 { /* addis 0,0,NUM, used
1631 for >= 32k frames */
1632 fdata->offset = (op & 0x0000ffff) << 16;
1633 fdata->frameless = 0;
1634 r0_contains_arg = 0;
1638 else if ((op & 0xffff0000) == 0x60000000)
1639 { /* ori 0,0,NUM, 2nd ha
1640 lf of >= 32k frames */
1641 fdata->offset |= (op & 0x0000ffff);
1642 fdata->frameless = 0;
1643 r0_contains_arg = 0;
1647 else if (lr_reg >= 0 &&
1648 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1649 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1650 /* stw Rx, NUM(r1) */
1651 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1652 /* stwu Rx, NUM(r1) */
1653 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1654 { /* where Rx == lr */
1655 fdata->lr_offset = offset;
1656 fdata->nosavedpc = 0;
1657 /* Invalidate lr_reg, but don't set it to -1.
1658 That would mean that it had never been set. */
1660 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1661 (op & 0xfc000000) == 0x90000000) /* stw */
1663 /* Does not update r1, so add displacement to lr_offset. */
1664 fdata->lr_offset += SIGNED_SHORT (op);
1669 else if (cr_reg >= 0 &&
1670 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1671 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1672 /* stw Rx, NUM(r1) */
1673 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1674 /* stwu Rx, NUM(r1) */
1675 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1676 { /* where Rx == cr */
1677 fdata->cr_offset = offset;
1678 /* Invalidate cr_reg, but don't set it to -1.
1679 That would mean that it had never been set. */
1681 if ((op & 0xfc000003) == 0xf8000000 ||
1682 (op & 0xfc000000) == 0x90000000)
1684 /* Does not update r1, so add displacement to cr_offset. */
1685 fdata->cr_offset += SIGNED_SHORT (op);
1690 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1692 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1693 prediction bits. If the LR has already been saved, we can
1697 else if (op == 0x48000005)
1704 else if (op == 0x48000004)
1709 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1710 in V.4 -mminimal-toc */
1711 (op & 0xffff0000) == 0x3bde0000)
1712 { /* addi 30,30,foo@l */
1716 else if ((op & 0xfc000001) == 0x48000001)
1720 fdata->frameless = 0;
1722 /* If the return address has already been saved, we can skip
1723 calls to blrl (for PIC). */
1724 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
1730 /* Don't skip over the subroutine call if it is not within
1731 the first three instructions of the prologue and either
1732 we have no line table information or the line info tells
1733 us that the subroutine call is not part of the line
1734 associated with the prologue. */
1735 if ((pc - orig_pc) > 8)
1737 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1738 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1740 if ((prologue_sal.line == 0)
1741 || (prologue_sal.line != this_sal.line))
1745 op = read_memory_integer (pc + 4, 4, byte_order);
1747 /* At this point, make sure this is not a trampoline
1748 function (a function that simply calls another functions,
1749 and nothing else). If the next is not a nop, this branch
1750 was part of the function prologue. */
1752 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1753 break; /* Don't skip over
1759 /* update stack pointer */
1760 else if ((op & 0xfc1f0000) == 0x94010000)
1761 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1762 fdata->frameless = 0;
1763 fdata->offset = SIGNED_SHORT (op);
1764 offset = fdata->offset;
1767 else if ((op & 0xfc1f016a) == 0x7c01016e)
1768 { /* stwux rX,r1,rY */
1769 /* No way to figure out what r1 is going to be. */
1770 fdata->frameless = 0;
1771 offset = fdata->offset;
1774 else if ((op & 0xfc1f0003) == 0xf8010001)
1775 { /* stdu rX,NUM(r1) */
1776 fdata->frameless = 0;
1777 fdata->offset = SIGNED_SHORT (op & ~3UL);
1778 offset = fdata->offset;
1781 else if ((op & 0xfc1f016a) == 0x7c01016a)
1782 { /* stdux rX,r1,rY */
1783 /* No way to figure out what r1 is going to be. */
1784 fdata->frameless = 0;
1785 offset = fdata->offset;
1788 else if ((op & 0xffff0000) == 0x38210000)
1789 { /* addi r1,r1,SIMM */
1790 fdata->frameless = 0;
1791 fdata->offset += SIGNED_SHORT (op);
1792 offset = fdata->offset;
1795 /* Load up minimal toc pointer. Do not treat an epilogue restore
1796 of r31 as a minimal TOC load. */
1797 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1798 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1800 && !minimal_toc_loaded)
1802 minimal_toc_loaded = 1;
1805 /* move parameters from argument registers to local variable
1808 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1809 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1810 (((op >> 21) & 31) <= 10) &&
1811 ((long) ((op >> 16) & 31)
1812 >= fdata->saved_gpr)) /* Rx: local var reg */
1816 /* store parameters in stack */
1818 /* Move parameters from argument registers to temporary register. */
1819 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1823 /* Set up frame pointer */
1825 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1826 || op == 0x7c3f0b78)
1828 fdata->frameless = 0;
1830 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1833 /* Another way to set up the frame pointer. */
1835 else if ((op & 0xfc1fffff) == 0x38010000)
1836 { /* addi rX, r1, 0x0 */
1837 fdata->frameless = 0;
1839 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1840 + ((op & ~0x38010000) >> 21));
1843 /* AltiVec related instructions. */
1844 /* Store the vrsave register (spr 256) in another register for
1845 later manipulation, or load a register into the vrsave
1846 register. 2 instructions are used: mfvrsave and
1847 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1848 and mtspr SPR256, Rn. */
1849 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1850 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1851 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1853 vrsave_reg = GET_SRC_REG (op);
1856 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1860 /* Store the register where vrsave was saved to onto the stack:
1861 rS is the register where vrsave was stored in a previous
1863 /* 100100 sssss 00001 dddddddd dddddddd */
1864 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1866 if (vrsave_reg == GET_SRC_REG (op))
1868 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1873 /* Compute the new value of vrsave, by modifying the register
1874 where vrsave was saved to. */
1875 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1876 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1880 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1881 in a pair of insns to save the vector registers on the
1883 /* 001110 00000 00000 iiii iiii iiii iiii */
1884 /* 001110 01110 00000 iiii iiii iiii iiii */
1885 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1886 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1888 if ((op & 0xffff0000) == 0x38000000)
1889 r0_contains_arg = 0;
1891 vr_saved_offset = SIGNED_SHORT (op);
1893 /* This insn by itself is not part of the prologue, unless
1894 if part of the pair of insns mentioned above. So do not
1895 record this insn as part of the prologue yet. */
1896 prev_insn_was_prologue_insn = 0;
1898 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1899 /* 011111 sssss 11111 00000 00111001110 */
1900 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1902 if (pc == (li_found_pc + 4))
1904 vr_reg = GET_SRC_REG (op);
1905 /* If this is the first vector reg to be saved, or if
1906 it has a lower number than others previously seen,
1907 reupdate the frame info. */
1908 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1910 fdata->saved_vr = vr_reg;
1911 fdata->vr_offset = vr_saved_offset + offset;
1913 vr_saved_offset = -1;
1918 /* End AltiVec related instructions. */
1920 /* Start BookE related instructions. */
1921 /* Store gen register S at (r31+uimm).
1922 Any register less than r13 is volatile, so we don't care. */
1923 /* 000100 sssss 11111 iiiii 01100100001 */
1924 else if (arch_info->mach == bfd_mach_ppc_e500
1925 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1927 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1930 ev_reg = GET_SRC_REG (op);
1931 imm = (op >> 11) & 0x1f;
1932 ev_offset = imm * 8;
1933 /* If this is the first vector reg to be saved, or if
1934 it has a lower number than others previously seen,
1935 reupdate the frame info. */
1936 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1938 fdata->saved_ev = ev_reg;
1939 fdata->ev_offset = ev_offset + offset;
1944 /* Store gen register rS at (r1+rB). */
1945 /* 000100 sssss 00001 bbbbb 01100100000 */
1946 else if (arch_info->mach == bfd_mach_ppc_e500
1947 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1949 if (pc == (li_found_pc + 4))
1951 ev_reg = GET_SRC_REG (op);
1952 /* If this is the first vector reg to be saved, or if
1953 it has a lower number than others previously seen,
1954 reupdate the frame info. */
1955 /* We know the contents of rB from the previous instruction. */
1956 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1958 fdata->saved_ev = ev_reg;
1959 fdata->ev_offset = vr_saved_offset + offset;
1961 vr_saved_offset = -1;
1967 /* Store gen register r31 at (rA+uimm). */
1968 /* 000100 11111 aaaaa iiiii 01100100001 */
1969 else if (arch_info->mach == bfd_mach_ppc_e500
1970 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1972 /* Wwe know that the source register is 31 already, but
1973 it can't hurt to compute it. */
1974 ev_reg = GET_SRC_REG (op);
1975 ev_offset = ((op >> 11) & 0x1f) * 8;
1976 /* If this is the first vector reg to be saved, or if
1977 it has a lower number than others previously seen,
1978 reupdate the frame info. */
1979 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1981 fdata->saved_ev = ev_reg;
1982 fdata->ev_offset = ev_offset + offset;
1987 /* Store gen register S at (r31+r0).
1988 Store param on stack when offset from SP bigger than 4 bytes. */
1989 /* 000100 sssss 11111 00000 01100100000 */
1990 else if (arch_info->mach == bfd_mach_ppc_e500
1991 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1993 if (pc == (li_found_pc + 4))
1995 if ((op & 0x03e00000) >= 0x01a00000)
1997 ev_reg = GET_SRC_REG (op);
1998 /* If this is the first vector reg to be saved, or if
1999 it has a lower number than others previously seen,
2000 reupdate the frame info. */
2001 /* We know the contents of r0 from the previous
2003 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2005 fdata->saved_ev = ev_reg;
2006 fdata->ev_offset = vr_saved_offset + offset;
2010 vr_saved_offset = -1;
2015 /* End BookE related instructions. */
2019 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2021 /* Not a recognized prologue instruction.
2022 Handle optimizer code motions into the prologue by continuing
2023 the search if we have no valid frame yet or if the return
2024 address is not yet saved in the frame. Also skip instructions
2025 if some of the GPRs expected to be saved are not yet saved. */
2026 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2027 && (fdata->gpr_mask & all_mask) == all_mask)
2030 if (op == 0x4e800020 /* blr */
2031 || op == 0x4e800420) /* bctr */
2032 /* Do not scan past epilogue in frameless functions or
2035 if ((op & 0xf4000000) == 0x40000000) /* bxx */
2036 /* Never skip branches. */
2039 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2040 /* Do not scan too many insns, scanning insns is expensive with
2044 /* Continue scanning. */
2045 prev_insn_was_prologue_insn = 0;
2051 /* I have problems with skipping over __main() that I need to address
2052 * sometime. Previously, I used to use misc_function_vector which
2053 * didn't work as well as I wanted to be. -MGO */
2055 /* If the first thing after skipping a prolog is a branch to a function,
2056 this might be a call to an initializer in main(), introduced by gcc2.
2057 We'd like to skip over it as well. Fortunately, xlc does some extra
2058 work before calling a function right after a prologue, thus we can
2059 single out such gcc2 behaviour. */
2062 if ((op & 0xfc000001) == 0x48000001)
2063 { /* bl foo, an initializer function? */
2064 op = read_memory_integer (pc + 4, 4, byte_order);
2066 if (op == 0x4def7b82)
2067 { /* cror 0xf, 0xf, 0xf (nop) */
2069 /* Check and see if we are in main. If so, skip over this
2070 initializer function as well. */
2072 tmp = find_pc_misc_function (pc);
2074 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
2080 if (pc == lim_pc && lr_reg >= 0)
2081 fdata->lr_register = lr_reg;
2083 fdata->offset = -fdata->offset;
2084 return last_prologue_pc;
2088 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2090 struct rs6000_framedata frame;
2091 CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
2093 /* See if we can determine the end of the prologue via the symbol table.
2094 If so, then return either PC, or the PC after the prologue, whichever
2096 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
2098 CORE_ADDR post_prologue_pc
2099 = skip_prologue_using_sal (gdbarch, func_addr);
2100 if (post_prologue_pc != 0)
2101 return max (pc, post_prologue_pc);
2104 /* Can't determine prologue from the symbol table, need to examine
2107 /* Find an upper limit on the function prologue using the debug
2108 information. If the debug information could not be used to provide
2109 that bound, then use an arbitrary large number as the upper bound. */
2110 limit_pc = skip_prologue_using_sal (gdbarch, pc);
2112 limit_pc = pc + 100; /* Magic. */
2114 /* Do not allow limit_pc to be past the function end, if we know
2115 where that end is... */
2116 if (func_end_addr && limit_pc > func_end_addr)
2117 limit_pc = func_end_addr;
2119 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2123 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2124 in the prologue of main().
2126 The function below examines the code pointed at by PC and checks to
2127 see if it corresponds to a call to __eabi. If so, it returns the
2128 address of the instruction following that call. Otherwise, it simply
2132 rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2134 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2138 if (target_read_memory (pc, buf, 4))
2140 op = extract_unsigned_integer (buf, 4, byte_order);
2142 if ((op & BL_MASK) == BL_INSTRUCTION)
2144 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2145 CORE_ADDR call_dest = pc + 4 + displ;
2146 struct minimal_symbol *s = lookup_minimal_symbol_by_pc (call_dest);
2148 /* We check for ___eabi (three leading underscores) in addition
2149 to __eabi in case the GCC option "-fleading-underscore" was
2150 used to compile the program. */
2152 && SYMBOL_LINKAGE_NAME (s) != NULL
2153 && (strcmp (SYMBOL_LINKAGE_NAME (s), "__eabi") == 0
2154 || strcmp (SYMBOL_LINKAGE_NAME (s), "___eabi") == 0))
2160 /* All the ABI's require 16 byte alignment. */
2162 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2164 return (addr & -16);
2167 /* Return whether handle_inferior_event() should proceed through code
2168 starting at PC in function NAME when stepping.
2170 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2171 handle memory references that are too distant to fit in instructions
2172 generated by the compiler. For example, if 'foo' in the following
2177 is greater than 32767, the linker might replace the lwz with a branch to
2178 somewhere in @FIX1 that does the load in 2 instructions and then branches
2179 back to where execution should continue.
2181 GDB should silently step over @FIX code, just like AIX dbx does.
2182 Unfortunately, the linker uses the "b" instruction for the
2183 branches, meaning that the link register doesn't get set.
2184 Therefore, GDB's usual step_over_function () mechanism won't work.
2186 Instead, use the gdbarch_skip_trampoline_code and
2187 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2191 rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2192 CORE_ADDR pc, const char *name)
2194 return name && !strncmp (name, "@FIX", 4);
2197 /* Skip code that the user doesn't want to see when stepping:
2199 1. Indirect function calls use a piece of trampoline code to do context
2200 switching, i.e. to set the new TOC table. Skip such code if we are on
2201 its first instruction (as when we have single-stepped to here).
2203 2. Skip shared library trampoline code (which is different from
2204 indirect function call trampolines).
2206 3. Skip bigtoc fixup code.
2208 Result is desired PC to step until, or NULL if we are not in
2209 code that should be skipped. */
2212 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
2214 struct gdbarch *gdbarch = get_frame_arch (frame);
2215 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2216 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2217 unsigned int ii, op;
2219 CORE_ADDR solib_target_pc;
2220 struct minimal_symbol *msymbol;
2222 static unsigned trampoline_code[] =
2224 0x800b0000, /* l r0,0x0(r11) */
2225 0x90410014, /* st r2,0x14(r1) */
2226 0x7c0903a6, /* mtctr r0 */
2227 0x804b0004, /* l r2,0x4(r11) */
2228 0x816b0008, /* l r11,0x8(r11) */
2229 0x4e800420, /* bctr */
2230 0x4e800020, /* br */
2234 /* Check for bigtoc fixup code. */
2235 msymbol = lookup_minimal_symbol_by_pc (pc);
2237 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2238 SYMBOL_LINKAGE_NAME (msymbol)))
2240 /* Double-check that the third instruction from PC is relative "b". */
2241 op = read_memory_integer (pc + 8, 4, byte_order);
2242 if ((op & 0xfc000003) == 0x48000000)
2244 /* Extract bits 6-29 as a signed 24-bit relative word address and
2245 add it to the containing PC. */
2246 rel = ((int)(op << 6) >> 6);
2247 return pc + 8 + rel;
2251 /* If pc is in a shared library trampoline, return its target. */
2252 solib_target_pc = find_solib_trampoline_target (frame, pc);
2253 if (solib_target_pc)
2254 return solib_target_pc;
2256 for (ii = 0; trampoline_code[ii]; ++ii)
2258 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
2259 if (op != trampoline_code[ii])
2262 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
2264 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
2268 /* ISA-specific vector types. */
2270 static struct type *
2271 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2273 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2275 if (!tdep->ppc_builtin_type_vec64)
2277 const struct builtin_type *bt = builtin_type (gdbarch);
2279 /* The type we're building is this: */
2281 union __gdb_builtin_type_vec64
2285 int32_t v2_int32[2];
2286 int16_t v4_int16[4];
2293 t = arch_composite_type (gdbarch,
2294 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2295 append_composite_type_field (t, "uint64", bt->builtin_int64);
2296 append_composite_type_field (t, "v2_float",
2297 init_vector_type (bt->builtin_float, 2));
2298 append_composite_type_field (t, "v2_int32",
2299 init_vector_type (bt->builtin_int32, 2));
2300 append_composite_type_field (t, "v4_int16",
2301 init_vector_type (bt->builtin_int16, 4));
2302 append_composite_type_field (t, "v8_int8",
2303 init_vector_type (bt->builtin_int8, 8));
2305 TYPE_VECTOR (t) = 1;
2306 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2307 tdep->ppc_builtin_type_vec64 = t;
2310 return tdep->ppc_builtin_type_vec64;
2313 /* Vector 128 type. */
2315 static struct type *
2316 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2318 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2320 if (!tdep->ppc_builtin_type_vec128)
2322 const struct builtin_type *bt = builtin_type (gdbarch);
2324 /* The type we're building is this
2326 type = union __ppc_builtin_type_vec128 {
2328 double v2_double[2];
2330 int32_t v4_int32[4];
2331 int16_t v8_int16[8];
2332 int8_t v16_int8[16];
2338 t = arch_composite_type (gdbarch,
2339 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
2340 append_composite_type_field (t, "uint128", bt->builtin_uint128);
2341 append_composite_type_field (t, "v2_double",
2342 init_vector_type (bt->builtin_double, 2));
2343 append_composite_type_field (t, "v4_float",
2344 init_vector_type (bt->builtin_float, 4));
2345 append_composite_type_field (t, "v4_int32",
2346 init_vector_type (bt->builtin_int32, 4));
2347 append_composite_type_field (t, "v8_int16",
2348 init_vector_type (bt->builtin_int16, 8));
2349 append_composite_type_field (t, "v16_int8",
2350 init_vector_type (bt->builtin_int8, 16));
2352 TYPE_VECTOR (t) = 1;
2353 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2354 tdep->ppc_builtin_type_vec128 = t;
2357 return tdep->ppc_builtin_type_vec128;
2360 /* Return the name of register number REGNO, or the empty string if it
2361 is an anonymous register. */
2364 rs6000_register_name (struct gdbarch *gdbarch, int regno)
2366 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2368 /* The upper half "registers" have names in the XML description,
2369 but we present only the low GPRs and the full 64-bit registers
2371 if (tdep->ppc_ev0_upper_regnum >= 0
2372 && tdep->ppc_ev0_upper_regnum <= regno
2373 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2376 /* Hide the upper halves of the vs0~vs31 registers. */
2377 if (tdep->ppc_vsr0_regnum >= 0
2378 && tdep->ppc_vsr0_upper_regnum <= regno
2379 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2382 /* Check if the SPE pseudo registers are available. */
2383 if (IS_SPE_PSEUDOREG (tdep, regno))
2385 static const char *const spe_regnames[] = {
2386 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2387 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2388 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2389 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2391 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2394 /* Check if the decimal128 pseudo-registers are available. */
2395 if (IS_DFP_PSEUDOREG (tdep, regno))
2397 static const char *const dfp128_regnames[] = {
2398 "dl0", "dl1", "dl2", "dl3",
2399 "dl4", "dl5", "dl6", "dl7",
2400 "dl8", "dl9", "dl10", "dl11",
2401 "dl12", "dl13", "dl14", "dl15"
2403 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2406 /* Check if this is a VSX pseudo-register. */
2407 if (IS_VSX_PSEUDOREG (tdep, regno))
2409 static const char *const vsx_regnames[] = {
2410 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2411 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2412 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2413 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2414 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2415 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2416 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2417 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2418 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2420 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2423 /* Check if the this is a Extended FP pseudo-register. */
2424 if (IS_EFP_PSEUDOREG (tdep, regno))
2426 static const char *const efpr_regnames[] = {
2427 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2428 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2429 "f46", "f47", "f48", "f49", "f50", "f51",
2430 "f52", "f53", "f54", "f55", "f56", "f57",
2431 "f58", "f59", "f60", "f61", "f62", "f63"
2433 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2436 return tdesc_register_name (gdbarch, regno);
2439 /* Return the GDB type object for the "standard" data type of data in
2442 static struct type *
2443 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2445 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2447 /* These are the only pseudo-registers we support. */
2448 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2449 || IS_DFP_PSEUDOREG (tdep, regnum)
2450 || IS_VSX_PSEUDOREG (tdep, regnum)
2451 || IS_EFP_PSEUDOREG (tdep, regnum));
2453 /* These are the e500 pseudo-registers. */
2454 if (IS_SPE_PSEUDOREG (tdep, regnum))
2455 return rs6000_builtin_type_vec64 (gdbarch);
2456 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2457 /* PPC decimal128 pseudo-registers. */
2458 return builtin_type (gdbarch)->builtin_declong;
2459 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2460 /* POWER7 VSX pseudo-registers. */
2461 return rs6000_builtin_type_vec128 (gdbarch);
2463 /* POWER7 Extended FP pseudo-registers. */
2464 return builtin_type (gdbarch)->builtin_double;
2467 /* Is REGNUM a member of REGGROUP? */
2469 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2470 struct reggroup *group)
2472 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2474 /* These are the only pseudo-registers we support. */
2475 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2476 || IS_DFP_PSEUDOREG (tdep, regnum)
2477 || IS_VSX_PSEUDOREG (tdep, regnum)
2478 || IS_EFP_PSEUDOREG (tdep, regnum));
2480 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2481 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
2482 return group == all_reggroup || group == vector_reggroup;
2484 /* PPC decimal128 or Extended FP pseudo-registers. */
2485 return group == all_reggroup || group == float_reggroup;
2488 /* The register format for RS/6000 floating point registers is always
2489 double, we need a conversion if the memory format is float. */
2492 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2495 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2497 return (tdep->ppc_fp0_regnum >= 0
2498 && regnum >= tdep->ppc_fp0_regnum
2499 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2500 && TYPE_CODE (type) == TYPE_CODE_FLT
2501 && TYPE_LENGTH (type)
2502 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
2506 rs6000_register_to_value (struct frame_info *frame,
2510 int *optimizedp, int *unavailablep)
2512 struct gdbarch *gdbarch = get_frame_arch (frame);
2513 gdb_byte from[MAX_REGISTER_SIZE];
2515 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2517 if (!get_frame_register_bytes (frame, regnum, 0,
2518 register_size (gdbarch, regnum),
2519 from, optimizedp, unavailablep))
2522 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2524 *optimizedp = *unavailablep = 0;
2529 rs6000_value_to_register (struct frame_info *frame,
2532 const gdb_byte *from)
2534 struct gdbarch *gdbarch = get_frame_arch (frame);
2535 gdb_byte to[MAX_REGISTER_SIZE];
2537 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2539 convert_typed_floating (from, type,
2540 to, builtin_type (gdbarch)->builtin_double);
2541 put_frame_register (frame, regnum, to);
2544 /* The type of a function that moves the value of REG between CACHE
2545 or BUF --- in either direction. */
2546 typedef enum register_status (*move_ev_register_func) (struct regcache *,
2549 /* Move SPE vector register values between a 64-bit buffer and the two
2550 32-bit raw register halves in a regcache. This function handles
2551 both splitting a 64-bit value into two 32-bit halves, and joining
2552 two halves into a whole 64-bit value, depending on the function
2553 passed as the MOVE argument.
2555 EV_REG must be the number of an SPE evN vector register --- a
2556 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2559 Call MOVE once for each 32-bit half of that register, passing
2560 REGCACHE, the number of the raw register corresponding to that
2561 half, and the address of the appropriate half of BUFFER.
2563 For example, passing 'regcache_raw_read' as the MOVE function will
2564 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2565 'regcache_raw_supply' will supply the contents of BUFFER to the
2566 appropriate pair of raw registers in REGCACHE.
2568 You may need to cast away some 'const' qualifiers when passing
2569 MOVE, since this function can't tell at compile-time which of
2570 REGCACHE or BUFFER is acting as the source of the data. If C had
2571 co-variant type qualifiers, ... */
2573 static enum register_status
2574 e500_move_ev_register (move_ev_register_func move,
2575 struct regcache *regcache, int ev_reg, void *buffer)
2577 struct gdbarch *arch = get_regcache_arch (regcache);
2578 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2580 gdb_byte *byte_buffer = buffer;
2581 enum register_status status;
2583 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
2585 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2587 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2589 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2591 if (status == REG_VALID)
2592 status = move (regcache, tdep->ppc_gp0_regnum + reg_index,
2597 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2598 if (status == REG_VALID)
2599 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2606 static enum register_status
2607 do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer)
2609 return regcache_raw_read (regcache, regnum, buffer);
2612 static enum register_status
2613 do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer)
2615 regcache_raw_write (regcache, regnum, buffer);
2620 static enum register_status
2621 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2622 int reg_nr, gdb_byte *buffer)
2624 return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer);
2628 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2629 int reg_nr, const gdb_byte *buffer)
2631 e500_move_ev_register (do_regcache_raw_write, regcache,
2632 reg_nr, (void *) buffer);
2635 /* Read method for DFP pseudo-registers. */
2636 static enum register_status
2637 dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2638 int reg_nr, gdb_byte *buffer)
2640 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2641 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2642 enum register_status status;
2644 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2646 /* Read two FP registers to form a whole dl register. */
2647 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2648 2 * reg_index, buffer);
2649 if (status == REG_VALID)
2650 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2651 2 * reg_index + 1, buffer + 8);
2655 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2656 2 * reg_index + 1, buffer + 8);
2657 if (status == REG_VALID)
2658 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2659 2 * reg_index, buffer);
2665 /* Write method for DFP pseudo-registers. */
2667 dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2668 int reg_nr, const gdb_byte *buffer)
2670 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2671 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2673 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2675 /* Write each half of the dl register into a separate
2677 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2678 2 * reg_index, buffer);
2679 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2680 2 * reg_index + 1, buffer + 8);
2684 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2685 2 * reg_index + 1, buffer + 8);
2686 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2687 2 * reg_index, buffer);
2691 /* Read method for POWER7 VSX pseudo-registers. */
2692 static enum register_status
2693 vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2694 int reg_nr, gdb_byte *buffer)
2696 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2697 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2698 enum register_status status;
2700 /* Read the portion that overlaps the VMX registers. */
2702 status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2703 reg_index - 32, buffer);
2705 /* Read the portion that overlaps the FPR registers. */
2706 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2708 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2710 if (status == REG_VALID)
2711 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2712 reg_index, buffer + 8);
2716 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2717 reg_index, buffer + 8);
2718 if (status == REG_VALID)
2719 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2726 /* Write method for POWER7 VSX pseudo-registers. */
2728 vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2729 int reg_nr, const gdb_byte *buffer)
2731 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2732 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2734 /* Write the portion that overlaps the VMX registers. */
2736 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2737 reg_index - 32, buffer);
2739 /* Write the portion that overlaps the FPR registers. */
2740 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2742 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2744 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2745 reg_index, buffer + 8);
2749 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2750 reg_index, buffer + 8);
2751 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2756 /* Read method for POWER7 Extended FP pseudo-registers. */
2757 static enum register_status
2758 efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2759 int reg_nr, gdb_byte *buffer)
2761 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2762 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2764 /* Read the portion that overlaps the VMX register. */
2765 return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2766 register_size (gdbarch, reg_nr), buffer);
2769 /* Write method for POWER7 Extended FP pseudo-registers. */
2771 efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2772 int reg_nr, const gdb_byte *buffer)
2774 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2775 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2777 /* Write the portion that overlaps the VMX register. */
2778 regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index, 0,
2779 register_size (gdbarch, reg_nr), buffer);
2782 static enum register_status
2783 rs6000_pseudo_register_read (struct gdbarch *gdbarch,
2784 struct regcache *regcache,
2785 int reg_nr, gdb_byte *buffer)
2787 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2788 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2790 gdb_assert (regcache_arch == gdbarch);
2792 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2793 return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2794 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2795 return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2796 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2797 return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2798 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2799 return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2801 internal_error (__FILE__, __LINE__,
2802 _("rs6000_pseudo_register_read: "
2803 "called on unexpected register '%s' (%d)"),
2804 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2808 rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2809 struct regcache *regcache,
2810 int reg_nr, const gdb_byte *buffer)
2812 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2813 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2815 gdb_assert (regcache_arch == gdbarch);
2817 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2818 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2819 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2820 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2821 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2822 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2823 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2824 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2826 internal_error (__FILE__, __LINE__,
2827 _("rs6000_pseudo_register_write: "
2828 "called on unexpected register '%s' (%d)"),
2829 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2832 /* Convert a DBX STABS register number to a GDB register number. */
2834 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
2836 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2838 if (0 <= num && num <= 31)
2839 return tdep->ppc_gp0_regnum + num;
2840 else if (32 <= num && num <= 63)
2841 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2842 specifies registers the architecture doesn't have? Our
2843 callers don't check the value we return. */
2844 return tdep->ppc_fp0_regnum + (num - 32);
2845 else if (77 <= num && num <= 108)
2846 return tdep->ppc_vr0_regnum + (num - 77);
2847 else if (1200 <= num && num < 1200 + 32)
2848 return tdep->ppc_ev0_regnum + (num - 1200);
2853 return tdep->ppc_mq_regnum;
2855 return tdep->ppc_lr_regnum;
2857 return tdep->ppc_ctr_regnum;
2859 return tdep->ppc_xer_regnum;
2861 return tdep->ppc_vrsave_regnum;
2863 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2865 return tdep->ppc_acc_regnum;
2867 return tdep->ppc_spefscr_regnum;
2874 /* Convert a Dwarf 2 register number to a GDB register number. */
2876 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
2878 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2880 if (0 <= num && num <= 31)
2881 return tdep->ppc_gp0_regnum + num;
2882 else if (32 <= num && num <= 63)
2883 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2884 specifies registers the architecture doesn't have? Our
2885 callers don't check the value we return. */
2886 return tdep->ppc_fp0_regnum + (num - 32);
2887 else if (1124 <= num && num < 1124 + 32)
2888 return tdep->ppc_vr0_regnum + (num - 1124);
2889 else if (1200 <= num && num < 1200 + 32)
2890 return tdep->ppc_ev0_regnum + (num - 1200);
2895 return tdep->ppc_cr_regnum;
2897 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2899 return tdep->ppc_acc_regnum;
2901 return tdep->ppc_mq_regnum;
2903 return tdep->ppc_xer_regnum;
2905 return tdep->ppc_lr_regnum;
2907 return tdep->ppc_ctr_regnum;
2909 return tdep->ppc_vrsave_regnum;
2911 return tdep->ppc_spefscr_regnum;
2917 /* Translate a .eh_frame register to DWARF register, or adjust a
2918 .debug_frame register. */
2921 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2923 /* GCC releases before 3.4 use GCC internal register numbering in
2924 .debug_frame (and .debug_info, et cetera). The numbering is
2925 different from the standard SysV numbering for everything except
2926 for GPRs and FPRs. We can not detect this problem in most cases
2927 - to get accurate debug info for variables living in lr, ctr, v0,
2928 et cetera, use a newer version of GCC. But we must detect
2929 one important case - lr is in column 65 in .debug_frame output,
2932 GCC 3.4, and the "hammer" branch, have a related problem. They
2933 record lr register saves in .debug_frame as 108, but still record
2934 the return column as 65. We fix that up too.
2936 We can do this because 65 is assigned to fpsr, and GCC never
2937 generates debug info referring to it. To add support for
2938 handwritten debug info that restores fpsr, we would need to add a
2939 producer version check to this. */
2948 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2949 internal register numbering; translate that to the standard DWARF2
2950 register numbering. */
2951 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2953 else if (68 <= num && num <= 75) /* cr0-cr8 */
2954 return num - 68 + 86;
2955 else if (77 <= num && num <= 108) /* vr0-vr31 */
2956 return num - 77 + 1124;
2968 case 109: /* vrsave */
2970 case 110: /* vscr */
2972 case 111: /* spe_acc */
2974 case 112: /* spefscr */
2982 /* Handling the various POWER/PowerPC variants. */
2984 /* Information about a particular processor variant. */
2988 /* Name of this variant. */
2991 /* English description of the variant. */
2994 /* bfd_arch_info.arch corresponding to variant. */
2995 enum bfd_architecture arch;
2997 /* bfd_arch_info.mach corresponding to variant. */
3000 /* Target description for this variant. */
3001 struct target_desc **tdesc;
3004 static struct variant variants[] =
3006 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
3007 bfd_mach_ppc, &tdesc_powerpc_altivec32},
3008 {"power", "POWER user-level", bfd_arch_rs6000,
3009 bfd_mach_rs6k, &tdesc_rs6000},
3010 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
3011 bfd_mach_ppc_403, &tdesc_powerpc_403},
3012 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
3013 bfd_mach_ppc_405, &tdesc_powerpc_405},
3014 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
3015 bfd_mach_ppc_601, &tdesc_powerpc_601},
3016 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
3017 bfd_mach_ppc_602, &tdesc_powerpc_602},
3018 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
3019 bfd_mach_ppc_603, &tdesc_powerpc_603},
3020 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
3021 604, &tdesc_powerpc_604},
3022 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
3023 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
3024 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
3025 bfd_mach_ppc_505, &tdesc_powerpc_505},
3026 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
3027 bfd_mach_ppc_860, &tdesc_powerpc_860},
3028 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
3029 bfd_mach_ppc_750, &tdesc_powerpc_750},
3030 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
3031 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
3032 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
3033 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
3036 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
3037 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
3038 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
3039 bfd_mach_ppc_620, &tdesc_powerpc_64},
3040 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
3041 bfd_mach_ppc_630, &tdesc_powerpc_64},
3042 {"a35", "PowerPC A35", bfd_arch_powerpc,
3043 bfd_mach_ppc_a35, &tdesc_powerpc_64},
3044 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
3045 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
3046 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
3047 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
3049 /* FIXME: I haven't checked the register sets of the following. */
3050 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
3051 bfd_mach_rs6k_rs1, &tdesc_rs6000},
3052 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
3053 bfd_mach_rs6k_rsc, &tdesc_rs6000},
3054 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
3055 bfd_mach_rs6k_rs2, &tdesc_rs6000},
3060 /* Return the variant corresponding to architecture ARCH and machine number
3061 MACH. If no such variant exists, return null. */
3063 static const struct variant *
3064 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
3066 const struct variant *v;
3068 for (v = variants; v->name; v++)
3069 if (arch == v->arch && mach == v->mach)
3076 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3078 if (!info->disassembler_options)
3080 /* When debugging E500 binaries and disassembling code containing
3081 E500-specific (SPE) instructions, one sometimes sees AltiVec
3082 instructions instead. The opcode spaces for SPE instructions
3083 and AltiVec instructions overlap, and specifiying the "any" cpu
3084 looks for AltiVec instructions first. If we know we're
3085 debugging an E500 binary, however, we can specify the "e500x2"
3086 cpu and get much more sane disassembly output. */
3087 if (info->mach == bfd_mach_ppc_e500)
3088 info->disassembler_options = "e500x2";
3090 info->disassembler_options = "any";
3093 if (info->endian == BFD_ENDIAN_BIG)
3094 return print_insn_big_powerpc (memaddr, info);
3096 return print_insn_little_powerpc (memaddr, info);
3100 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3102 return frame_unwind_register_unsigned (next_frame,
3103 gdbarch_pc_regnum (gdbarch));
3106 static struct frame_id
3107 rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3109 return frame_id_build (get_frame_register_unsigned
3110 (this_frame, gdbarch_sp_regnum (gdbarch)),
3111 get_frame_pc (this_frame));
3114 struct rs6000_frame_cache
3117 CORE_ADDR initial_sp;
3118 struct trad_frame_saved_reg *saved_regs;
3121 static struct rs6000_frame_cache *
3122 rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
3124 struct rs6000_frame_cache *cache;
3125 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3126 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3127 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3128 struct rs6000_framedata fdata;
3129 int wordsize = tdep->wordsize;
3132 if ((*this_cache) != NULL)
3133 return (*this_cache);
3134 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3135 (*this_cache) = cache;
3136 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3138 func = get_frame_func (this_frame);
3139 pc = get_frame_pc (this_frame);
3140 skip_prologue (gdbarch, func, pc, &fdata);
3142 /* Figure out the parent's stack pointer. */
3144 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3145 address of the current frame. Things might be easier if the
3146 ->frame pointed to the outer-most address of the frame. In
3147 the mean time, the address of the prev frame is used as the
3148 base address of this frame. */
3149 cache->base = get_frame_register_unsigned
3150 (this_frame, gdbarch_sp_regnum (gdbarch));
3152 /* If the function appears to be frameless, check a couple of likely
3153 indicators that we have simply failed to find the frame setup.
3154 Two common cases of this are missing symbols (i.e.
3155 get_frame_func returns the wrong address or 0), and assembly
3156 stubs which have a fast exit path but set up a frame on the slow
3159 If the LR appears to return to this function, then presume that
3160 we have an ABI compliant frame that we failed to find. */
3161 if (fdata.frameless && fdata.lr_offset == 0)
3166 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
3167 if (func == 0 && saved_lr == pc)
3171 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3172 if (func == saved_func)
3178 fdata.frameless = 0;
3179 fdata.lr_offset = tdep->lr_frame_offset;
3183 if (!fdata.frameless)
3184 /* Frameless really means stackless. */
3186 = read_memory_unsigned_integer (cache->base, wordsize, byte_order);
3188 trad_frame_set_value (cache->saved_regs,
3189 gdbarch_sp_regnum (gdbarch), cache->base);
3191 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3192 All fpr's from saved_fpr to fp31 are saved. */
3194 if (fdata.saved_fpr >= 0)
3197 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3199 /* If skip_prologue says floating-point registers were saved,
3200 but the current architecture has no floating-point registers,
3201 then that's strange. But we have no indices to even record
3202 the addresses under, so we just ignore it. */
3203 if (ppc_floating_point_unit_p (gdbarch))
3204 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3206 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3211 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3212 All gpr's from saved_gpr to gpr31 are saved (except during the
3215 if (fdata.saved_gpr >= 0)
3218 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3219 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3221 if (fdata.gpr_mask & (1U << i))
3222 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3223 gpr_addr += wordsize;
3227 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3228 All vr's from saved_vr to vr31 are saved. */
3229 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3231 if (fdata.saved_vr >= 0)
3234 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3235 for (i = fdata.saved_vr; i < 32; i++)
3237 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3238 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3243 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3244 All vr's from saved_ev to ev31 are saved. ????? */
3245 if (tdep->ppc_ev0_regnum != -1)
3247 if (fdata.saved_ev >= 0)
3250 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3251 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3253 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3254 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
3255 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3260 /* If != 0, fdata.cr_offset is the offset from the frame that
3262 if (fdata.cr_offset != 0)
3263 cache->saved_regs[tdep->ppc_cr_regnum].addr
3264 = cache->base + fdata.cr_offset;
3266 /* If != 0, fdata.lr_offset is the offset from the frame that
3268 if (fdata.lr_offset != 0)
3269 cache->saved_regs[tdep->ppc_lr_regnum].addr
3270 = cache->base + fdata.lr_offset;
3271 else if (fdata.lr_register != -1)
3272 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
3273 /* The PC is found in the link register. */
3274 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3275 cache->saved_regs[tdep->ppc_lr_regnum];
3277 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3278 holds the VRSAVE. */
3279 if (fdata.vrsave_offset != 0)
3280 cache->saved_regs[tdep->ppc_vrsave_regnum].addr
3281 = cache->base + fdata.vrsave_offset;
3283 if (fdata.alloca_reg < 0)
3284 /* If no alloca register used, then fi->frame is the value of the
3285 %sp for this frame, and it is good enough. */
3287 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
3290 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
3296 rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
3297 struct frame_id *this_id)
3299 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3301 /* This marks the outermost frame. */
3302 if (info->base == 0)
3305 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3308 static struct value *
3309 rs6000_frame_prev_register (struct frame_info *this_frame,
3310 void **this_cache, int regnum)
3312 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3314 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3317 static const struct frame_unwind rs6000_frame_unwind =
3320 default_frame_unwind_stop_reason,
3321 rs6000_frame_this_id,
3322 rs6000_frame_prev_register,
3324 default_frame_sniffer
3329 rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
3331 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3333 return info->initial_sp;
3336 static const struct frame_base rs6000_frame_base = {
3337 &rs6000_frame_unwind,
3338 rs6000_frame_base_address,
3339 rs6000_frame_base_address,
3340 rs6000_frame_base_address
3343 static const struct frame_base *
3344 rs6000_frame_base_sniffer (struct frame_info *this_frame)
3346 return &rs6000_frame_base;
3349 /* DWARF-2 frame support. Used to handle the detection of
3350 clobbered registers during function calls. */
3353 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3354 struct dwarf2_frame_state_reg *reg,
3355 struct frame_info *this_frame)
3357 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3359 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3360 non-volatile registers. We will use the same code for both. */
3362 /* Call-saved GP registers. */
3363 if ((regnum >= tdep->ppc_gp0_regnum + 14
3364 && regnum <= tdep->ppc_gp0_regnum + 31)
3365 || (regnum == tdep->ppc_gp0_regnum + 1))
3366 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3368 /* Call-clobbered GP registers. */
3369 if ((regnum >= tdep->ppc_gp0_regnum + 3
3370 && regnum <= tdep->ppc_gp0_regnum + 12)
3371 || (regnum == tdep->ppc_gp0_regnum))
3372 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3374 /* Deal with FP registers, if supported. */
3375 if (tdep->ppc_fp0_regnum >= 0)
3377 /* Call-saved FP registers. */
3378 if ((regnum >= tdep->ppc_fp0_regnum + 14
3379 && regnum <= tdep->ppc_fp0_regnum + 31))
3380 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3382 /* Call-clobbered FP registers. */
3383 if ((regnum >= tdep->ppc_fp0_regnum
3384 && regnum <= tdep->ppc_fp0_regnum + 13))
3385 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3388 /* Deal with ALTIVEC registers, if supported. */
3389 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3391 /* Call-saved Altivec registers. */
3392 if ((regnum >= tdep->ppc_vr0_regnum + 20
3393 && regnum <= tdep->ppc_vr0_regnum + 31)
3394 || regnum == tdep->ppc_vrsave_regnum)
3395 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3397 /* Call-clobbered Altivec registers. */
3398 if ((regnum >= tdep->ppc_vr0_regnum
3399 && regnum <= tdep->ppc_vr0_regnum + 19))
3400 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3403 /* Handle PC register and Stack Pointer correctly. */
3404 if (regnum == gdbarch_pc_regnum (gdbarch))
3405 reg->how = DWARF2_FRAME_REG_RA;
3406 else if (regnum == gdbarch_sp_regnum (gdbarch))
3407 reg->how = DWARF2_FRAME_REG_CFA;
3411 /* Return true if a .gnu_attributes section exists in BFD and it
3412 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3413 section exists in BFD and it indicates that SPE extensions are in
3414 use. Check the .gnu.attributes section first, as the binary might be
3415 compiled for SPE, but not actually using SPE instructions. */
3418 bfd_uses_spe_extensions (bfd *abfd)
3421 gdb_byte *contents = NULL;
3431 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3432 could be using the SPE vector abi without actually using any spe
3433 bits whatsoever. But it's close enough for now. */
3434 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3435 Tag_GNU_Power_ABI_Vector);
3436 if (vector_abi == 3)
3440 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3444 size = bfd_get_section_size (sect);
3445 contents = xmalloc (size);
3446 if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3452 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3458 char name[name_len rounded up to 4-byte alignment];
3459 char data[data_len];
3462 Technically, there's only supposed to be one such structure in a
3463 given apuinfo section, but the linker is not always vigilant about
3464 merging apuinfo sections from input files. Just go ahead and parse
3465 them all, exiting early when we discover the binary uses SPE
3468 It's not specified in what endianness the information in this
3469 section is stored. Assume that it's the endianness of the BFD. */
3473 unsigned int name_len;
3474 unsigned int data_len;
3477 /* If we can't read the first three fields, we're done. */
3481 name_len = bfd_get_32 (abfd, ptr);
3482 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3483 data_len = bfd_get_32 (abfd, ptr + 4);
3484 type = bfd_get_32 (abfd, ptr + 8);
3487 /* The name must be "APUinfo\0". */
3489 && strcmp ((const char *) ptr, "APUinfo") != 0)
3493 /* The type must be 2. */
3497 /* The data is stored as a series of uint32. The upper half of
3498 each uint32 indicates the particular APU used and the lower
3499 half indicates the revision of that APU. We just care about
3502 /* Not 4-byte quantities. */
3508 unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3509 unsigned int apu = apuinfo >> 16;
3513 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3515 if (apu == 0x100 || apu == 0x101)
3530 /* Initialize the current architecture based on INFO. If possible, re-use an
3531 architecture from ARCHES, which is a list of architectures already created
3532 during this debugging session.
3534 Called e.g. at program startup, when reading a core file, and when reading
3537 static struct gdbarch *
3538 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3540 struct gdbarch *gdbarch;
3541 struct gdbarch_tdep *tdep;
3542 int wordsize, from_xcoff_exec, from_elf_exec;
3543 enum bfd_architecture arch;
3547 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
3549 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
3550 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
3552 int tdesc_wordsize = -1;
3553 const struct target_desc *tdesc = info.target_desc;
3554 struct tdesc_arch_data *tdesc_data = NULL;
3555 int num_pseudoregs = 0;
3558 /* INFO may refer to a binary that is not of the PowerPC architecture,
3559 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
3560 In this case, we must not attempt to infer properties of the (PowerPC
3561 side) of the target system from properties of that executable. Trust
3562 the target description instead. */
3564 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
3565 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
3568 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3569 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3571 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3572 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3574 /* Check word size. If INFO is from a binary file, infer it from
3575 that, else choose a likely default. */
3576 if (from_xcoff_exec)
3578 if (bfd_xcoff_is_xcoff64 (info.abfd))
3583 else if (from_elf_exec)
3585 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3590 else if (tdesc_has_registers (tdesc))
3594 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3595 wordsize = info.bfd_arch_info->bits_per_word /
3596 info.bfd_arch_info->bits_per_byte;
3601 /* Get the architecture and machine from the BFD. */
3602 arch = info.bfd_arch_info->arch;
3603 mach = info.bfd_arch_info->mach;
3605 /* For e500 executables, the apuinfo section is of help here. Such
3606 section contains the identifier and revision number of each
3607 Application-specific Processing Unit that is present on the
3608 chip. The content of the section is determined by the assembler
3609 which looks at each instruction and determines which unit (and
3610 which version of it) can execute it. Grovel through the section
3611 looking for relevant e500 APUs. */
3613 if (bfd_uses_spe_extensions (info.abfd))
3615 arch = info.bfd_arch_info->arch;
3616 mach = bfd_mach_ppc_e500;
3617 bfd_default_set_arch_mach (&abfd, arch, mach);
3618 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3621 /* Find a default target description which describes our register
3622 layout, if we do not already have one. */
3623 if (! tdesc_has_registers (tdesc))
3625 const struct variant *v;
3627 /* Choose variant. */
3628 v = find_variant_by_arch (arch, mach);
3635 gdb_assert (tdesc_has_registers (tdesc));
3637 /* Check any target description for validity. */
3638 if (tdesc_has_registers (tdesc))
3640 static const char *const gprs[] = {
3641 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3642 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3643 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3644 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3646 static const char *const segment_regs[] = {
3647 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3648 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3650 const struct tdesc_feature *feature;
3652 static const char *const msr_names[] = { "msr", "ps" };
3653 static const char *const cr_names[] = { "cr", "cnd" };
3654 static const char *const ctr_names[] = { "ctr", "cnt" };
3656 feature = tdesc_find_feature (tdesc,
3657 "org.gnu.gdb.power.core");
3658 if (feature == NULL)
3661 tdesc_data = tdesc_data_alloc ();
3664 for (i = 0; i < ppc_num_gprs; i++)
3665 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3666 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3668 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3670 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3673 /* Allow alternate names for these registers, to accomodate GDB's
3675 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3676 PPC_MSR_REGNUM, msr_names);
3677 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3678 PPC_CR_REGNUM, cr_names);
3679 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3680 PPC_CTR_REGNUM, ctr_names);
3684 tdesc_data_cleanup (tdesc_data);
3688 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3691 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3693 wordsize = tdesc_wordsize;
3695 feature = tdesc_find_feature (tdesc,
3696 "org.gnu.gdb.power.fpu");
3697 if (feature != NULL)
3699 static const char *const fprs[] = {
3700 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3701 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3702 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3703 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3706 for (i = 0; i < ppc_num_fprs; i++)
3707 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3708 PPC_F0_REGNUM + i, fprs[i]);
3709 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3710 PPC_FPSCR_REGNUM, "fpscr");
3714 tdesc_data_cleanup (tdesc_data);
3722 /* The DFP pseudo-registers will be available when there are floating
3724 have_dfp = have_fpu;
3726 feature = tdesc_find_feature (tdesc,
3727 "org.gnu.gdb.power.altivec");
3728 if (feature != NULL)
3730 static const char *const vector_regs[] = {
3731 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3732 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3733 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3734 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3738 for (i = 0; i < ppc_num_gprs; i++)
3739 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3742 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3743 PPC_VSCR_REGNUM, "vscr");
3744 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3745 PPC_VRSAVE_REGNUM, "vrsave");
3747 if (have_spe || !valid_p)
3749 tdesc_data_cleanup (tdesc_data);
3757 /* Check for POWER7 VSX registers support. */
3758 feature = tdesc_find_feature (tdesc,
3759 "org.gnu.gdb.power.vsx");
3761 if (feature != NULL)
3763 static const char *const vsx_regs[] = {
3764 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
3765 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
3766 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
3767 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
3768 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
3774 for (i = 0; i < ppc_num_vshrs; i++)
3775 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3776 PPC_VSR0_UPPER_REGNUM + i,
3780 tdesc_data_cleanup (tdesc_data);
3789 /* On machines supporting the SPE APU, the general-purpose registers
3790 are 64 bits long. There are SIMD vector instructions to treat them
3791 as pairs of floats, but the rest of the instruction set treats them
3792 as 32-bit registers, and only operates on their lower halves.
3794 In the GDB regcache, we treat their high and low halves as separate
3795 registers. The low halves we present as the general-purpose
3796 registers, and then we have pseudo-registers that stitch together
3797 the upper and lower halves and present them as pseudo-registers.
3799 Thus, the target description is expected to supply the upper
3800 halves separately. */
3802 feature = tdesc_find_feature (tdesc,
3803 "org.gnu.gdb.power.spe");
3804 if (feature != NULL)
3806 static const char *const upper_spe[] = {
3807 "ev0h", "ev1h", "ev2h", "ev3h",
3808 "ev4h", "ev5h", "ev6h", "ev7h",
3809 "ev8h", "ev9h", "ev10h", "ev11h",
3810 "ev12h", "ev13h", "ev14h", "ev15h",
3811 "ev16h", "ev17h", "ev18h", "ev19h",
3812 "ev20h", "ev21h", "ev22h", "ev23h",
3813 "ev24h", "ev25h", "ev26h", "ev27h",
3814 "ev28h", "ev29h", "ev30h", "ev31h"
3818 for (i = 0; i < ppc_num_gprs; i++)
3819 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3820 PPC_SPE_UPPER_GP0_REGNUM + i,
3822 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3823 PPC_SPE_ACC_REGNUM, "acc");
3824 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3825 PPC_SPE_FSCR_REGNUM, "spefscr");
3827 if (have_mq || have_fpu || !valid_p)
3829 tdesc_data_cleanup (tdesc_data);
3838 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3839 complain for a 32-bit binary on a 64-bit target; we do not yet
3840 support that. For instance, the 32-bit ABI routines expect
3843 As long as there isn't an explicit target description, we'll
3844 choose one based on the BFD architecture and get a word size
3845 matching the binary (probably powerpc:common or
3846 powerpc:common64). So there is only trouble if a 64-bit target
3847 supplies a 64-bit description while debugging a 32-bit
3849 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3851 tdesc_data_cleanup (tdesc_data);
3856 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
3858 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3859 Tag_GNU_Power_ABI_FP))
3862 soft_float_flag = AUTO_BOOLEAN_FALSE;
3865 soft_float_flag = AUTO_BOOLEAN_TRUE;
3872 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
3874 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
3875 Tag_GNU_Power_ABI_Vector))
3878 vector_abi = POWERPC_VEC_GENERIC;
3881 vector_abi = POWERPC_VEC_ALTIVEC;
3884 vector_abi = POWERPC_VEC_SPE;
3892 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
3894 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
3897 soft_float = !have_fpu;
3899 /* If we have a hard float binary or setting but no floating point
3900 registers, downgrade to soft float anyway. We're still somewhat
3901 useful in this scenario. */
3902 if (!soft_float && !have_fpu)
3905 /* Similarly for vector registers. */
3906 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
3907 vector_abi = POWERPC_VEC_GENERIC;
3909 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
3910 vector_abi = POWERPC_VEC_GENERIC;
3912 if (vector_abi == POWERPC_VEC_AUTO)
3915 vector_abi = POWERPC_VEC_ALTIVEC;
3917 vector_abi = POWERPC_VEC_SPE;
3919 vector_abi = POWERPC_VEC_GENERIC;
3922 /* Do not limit the vector ABI based on available hardware, since we
3923 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
3925 /* Find a candidate among extant architectures. */
3926 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3928 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3930 /* Word size in the various PowerPC bfd_arch_info structs isn't
3931 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3932 separate word size check. */
3933 tdep = gdbarch_tdep (arches->gdbarch);
3934 if (tdep && tdep->soft_float != soft_float)
3936 if (tdep && tdep->vector_abi != vector_abi)
3938 if (tdep && tdep->wordsize == wordsize)
3940 if (tdesc_data != NULL)
3941 tdesc_data_cleanup (tdesc_data);
3942 return arches->gdbarch;
3946 /* None found, create a new architecture from INFO, whose bfd_arch_info
3947 validity depends on the source:
3948 - executable useless
3949 - rs6000_host_arch() good
3951 - "set arch" trust blindly
3952 - GDB startup useless but harmless */
3954 tdep = XCALLOC (1, struct gdbarch_tdep);
3955 tdep->wordsize = wordsize;
3956 tdep->soft_float = soft_float;
3957 tdep->vector_abi = vector_abi;
3959 gdbarch = gdbarch_alloc (&info, tdep);
3961 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3962 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3963 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3964 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3965 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3966 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3967 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3968 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3970 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3971 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
3972 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
3973 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3974 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3975 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3976 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3977 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3979 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3980 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3981 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3982 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
3983 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3985 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3986 GDB traditionally called it "ps", though, so let GDB add an
3988 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3991 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3993 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3995 /* Set lr_frame_offset. */
3997 tdep->lr_frame_offset = 16;
3999 tdep->lr_frame_offset = 4;
4001 if (have_spe || have_dfp || have_vsx)
4003 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
4004 set_gdbarch_pseudo_register_write (gdbarch,
4005 rs6000_pseudo_register_write);
4008 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
4010 /* Select instruction printer. */
4011 if (arch == bfd_arch_rs6000)
4012 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
4014 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
4016 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
4019 num_pseudoregs += 32;
4021 num_pseudoregs += 16;
4023 /* Include both VSX and Extended FP registers. */
4024 num_pseudoregs += 96;
4026 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
4028 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4029 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
4030 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4031 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
4032 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4033 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
4034 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
4035 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
4036 set_gdbarch_char_signed (gdbarch, 0);
4038 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
4041 set_gdbarch_frame_red_zone_size (gdbarch, 288);
4043 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
4044 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
4045 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
4047 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
4048 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
4051 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
4052 else if (wordsize == 8)
4053 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
4055 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
4056 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
4057 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
4059 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
4060 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
4062 /* The value of symbols of type N_SO and N_FUN maybe null when
4064 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
4066 /* Handles single stepping of atomic sequences. */
4067 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
4069 /* Not sure on this. FIXMEmgo */
4070 set_gdbarch_frame_args_skip (gdbarch, 8);
4072 /* Helpers for function argument information. */
4073 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
4076 set_gdbarch_in_solib_return_trampoline
4077 (gdbarch, rs6000_in_solib_return_trampoline);
4078 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
4080 /* Hook in the DWARF CFI frame unwinder. */
4081 dwarf2_append_unwinders (gdbarch);
4082 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
4084 /* Frame handling. */
4085 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
4087 /* Setup displaced stepping. */
4088 set_gdbarch_displaced_step_copy_insn (gdbarch,
4089 simple_displaced_step_copy_insn);
4090 set_gdbarch_displaced_step_hw_singlestep (gdbarch,
4091 ppc_displaced_step_hw_singlestep);
4092 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
4093 set_gdbarch_displaced_step_free_closure (gdbarch,
4094 simple_displaced_step_free_closure);
4095 set_gdbarch_displaced_step_location (gdbarch,
4096 displaced_step_at_entry_point);
4098 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
4100 /* Hook in ABI-specific overrides, if they have been registered. */
4101 info.target_desc = tdesc;
4102 info.tdep_info = (void *) tdesc_data;
4103 gdbarch_init_osabi (info, gdbarch);
4107 case GDB_OSABI_LINUX:
4108 case GDB_OSABI_NETBSD_AOUT:
4109 case GDB_OSABI_NETBSD_ELF:
4110 case GDB_OSABI_UNKNOWN:
4111 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
4112 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4113 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
4114 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
4117 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
4119 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
4120 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
4121 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
4122 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
4125 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
4126 set_tdesc_pseudo_register_reggroup_p (gdbarch,
4127 rs6000_pseudo_register_reggroup_p);
4128 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
4130 /* Override the normal target description method to make the SPE upper
4131 halves anonymous. */
4132 set_gdbarch_register_name (gdbarch, rs6000_register_name);
4134 /* Choose register numbers for all supported pseudo-registers. */
4135 tdep->ppc_ev0_regnum = -1;
4136 tdep->ppc_dl0_regnum = -1;
4137 tdep->ppc_vsr0_regnum = -1;
4138 tdep->ppc_efpr0_regnum = -1;
4140 cur_reg = gdbarch_num_regs (gdbarch);
4144 tdep->ppc_ev0_regnum = cur_reg;
4149 tdep->ppc_dl0_regnum = cur_reg;
4154 tdep->ppc_vsr0_regnum = cur_reg;
4156 tdep->ppc_efpr0_regnum = cur_reg;
4160 gdb_assert (gdbarch_num_regs (gdbarch)
4161 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
4167 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
4169 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4174 /* FIXME: Dump gdbarch_tdep. */
4177 /* PowerPC-specific commands. */
4180 set_powerpc_command (char *args, int from_tty)
4182 printf_unfiltered (_("\
4183 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
4184 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
4188 show_powerpc_command (char *args, int from_tty)
4190 cmd_show_list (showpowerpccmdlist, from_tty, "");
4194 powerpc_set_soft_float (char *args, int from_tty,
4195 struct cmd_list_element *c)
4197 struct gdbarch_info info;
4199 /* Update the architecture. */
4200 gdbarch_info_init (&info);
4201 if (!gdbarch_update_p (info))
4202 internal_error (__FILE__, __LINE__, _("could not update architecture"));
4206 powerpc_set_vector_abi (char *args, int from_tty,
4207 struct cmd_list_element *c)
4209 struct gdbarch_info info;
4210 enum powerpc_vector_abi vector_abi;
4212 for (vector_abi = POWERPC_VEC_AUTO;
4213 vector_abi != POWERPC_VEC_LAST;
4215 if (strcmp (powerpc_vector_abi_string,
4216 powerpc_vector_strings[vector_abi]) == 0)
4218 powerpc_vector_abi_global = vector_abi;
4222 if (vector_abi == POWERPC_VEC_LAST)
4223 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
4224 powerpc_vector_abi_string);
4226 /* Update the architecture. */
4227 gdbarch_info_init (&info);
4228 if (!gdbarch_update_p (info))
4229 internal_error (__FILE__, __LINE__, _("could not update architecture"));
4232 /* Show the current setting of the exact watchpoints flag. */
4235 show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty,
4236 struct cmd_list_element *c,
4239 fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value);
4242 /* Initialization code. */
4244 /* -Wmissing-prototypes */
4245 extern initialize_file_ftype _initialize_rs6000_tdep;
4248 _initialize_rs6000_tdep (void)
4250 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
4251 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
4253 /* Initialize the standard target descriptions. */
4254 initialize_tdesc_powerpc_32 ();
4255 initialize_tdesc_powerpc_altivec32 ();
4256 initialize_tdesc_powerpc_vsx32 ();
4257 initialize_tdesc_powerpc_403 ();
4258 initialize_tdesc_powerpc_403gc ();
4259 initialize_tdesc_powerpc_405 ();
4260 initialize_tdesc_powerpc_505 ();
4261 initialize_tdesc_powerpc_601 ();
4262 initialize_tdesc_powerpc_602 ();
4263 initialize_tdesc_powerpc_603 ();
4264 initialize_tdesc_powerpc_604 ();
4265 initialize_tdesc_powerpc_64 ();
4266 initialize_tdesc_powerpc_altivec64 ();
4267 initialize_tdesc_powerpc_vsx64 ();
4268 initialize_tdesc_powerpc_7400 ();
4269 initialize_tdesc_powerpc_750 ();
4270 initialize_tdesc_powerpc_860 ();
4271 initialize_tdesc_powerpc_e500 ();
4272 initialize_tdesc_rs6000 ();
4274 /* Add root prefix command for all "set powerpc"/"show powerpc"
4276 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
4277 _("Various PowerPC-specific commands."),
4278 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
4280 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
4281 _("Various PowerPC-specific commands."),
4282 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
4284 /* Add a command to allow the user to force the ABI. */
4285 add_setshow_auto_boolean_cmd ("soft-float", class_support,
4286 &powerpc_soft_float_global,
4287 _("Set whether to use a soft-float ABI."),
4288 _("Show whether to use a soft-float ABI."),
4290 powerpc_set_soft_float, NULL,
4291 &setpowerpccmdlist, &showpowerpccmdlist);
4293 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
4294 &powerpc_vector_abi_string,
4295 _("Set the vector ABI."),
4296 _("Show the vector ABI."),
4297 NULL, powerpc_set_vector_abi, NULL,
4298 &setpowerpccmdlist, &showpowerpccmdlist);
4300 add_setshow_boolean_cmd ("exact-watchpoints", class_support,
4301 &target_exact_watchpoints,
4303 Set whether to use just one debug register for watchpoints on scalars."),
4305 Show whether to use just one debug register for watchpoints on scalars."),
4307 If true, GDB will use only one debug register when watching a variable of\n\
4308 scalar type, thus assuming that the variable is accessed through the address\n\
4309 of its first byte."),
4310 NULL, show_powerpc_exact_watchpoints,
4311 &setpowerpccmdlist, &showpowerpccmdlist);