1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997,
4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
5 Free Software Foundation, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 #include "arch-utils.h"
35 #include "parser-defs.h"
38 #include "sim-regno.h"
39 #include "gdb/sim-ppc.h"
40 #include "reggroups.h"
41 #include "dwarf2-frame.h"
42 #include "target-descriptions.h"
43 #include "user-regs.h"
45 #include "libbfd.h" /* for bfd_default_set_arch_mach */
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "solib-svr4.h"
56 #include "gdb_assert.h"
59 #include "trad-frame.h"
60 #include "frame-unwind.h"
61 #include "frame-base.h"
63 #include "rs6000-tdep.h"
65 #include "features/rs6000/powerpc-32.c"
66 #include "features/rs6000/powerpc-403.c"
67 #include "features/rs6000/powerpc-403gc.c"
68 #include "features/rs6000/powerpc-505.c"
69 #include "features/rs6000/powerpc-601.c"
70 #include "features/rs6000/powerpc-602.c"
71 #include "features/rs6000/powerpc-603.c"
72 #include "features/rs6000/powerpc-604.c"
73 #include "features/rs6000/powerpc-64.c"
74 #include "features/rs6000/powerpc-7400.c"
75 #include "features/rs6000/powerpc-750.c"
76 #include "features/rs6000/powerpc-860.c"
77 #include "features/rs6000/powerpc-e500.c"
78 #include "features/rs6000/rs6000.c"
80 /* If the kernel has to deliver a signal, it pushes a sigcontext
81 structure on the stack and then calls the signal handler, passing
82 the address of the sigcontext in an argument register. Usually
83 the signal handler doesn't save this register, so we have to
84 access the sigcontext structure via an offset from the signal handler
86 The following constants were determined by experimentation on AIX 3.2. */
87 #define SIG_FRAME_PC_OFFSET 96
88 #define SIG_FRAME_LR_OFFSET 108
89 #define SIG_FRAME_FP_OFFSET 284
91 /* To be used by skip_prologue. */
93 struct rs6000_framedata
95 int offset; /* total size of frame --- the distance
96 by which we decrement sp to allocate
98 int saved_gpr; /* smallest # of saved gpr */
99 int saved_fpr; /* smallest # of saved fpr */
100 int saved_vr; /* smallest # of saved vr */
101 int saved_ev; /* smallest # of saved ev */
102 int alloca_reg; /* alloca register number (frame ptr) */
103 char frameless; /* true if frameless functions. */
104 char nosavedpc; /* true if pc not saved. */
105 int gpr_offset; /* offset of saved gprs from prev sp */
106 int fpr_offset; /* offset of saved fprs from prev sp */
107 int vr_offset; /* offset of saved vrs from prev sp */
108 int ev_offset; /* offset of saved evs from prev sp */
109 int lr_offset; /* offset of saved lr */
110 int cr_offset; /* offset of saved cr */
111 int vrsave_offset; /* offset of saved vrsave register */
114 /* Description of a single register. */
118 char *name; /* name of register */
119 unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */
120 unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */
121 unsigned char fpr; /* whether register is floating-point */
122 unsigned char pseudo; /* whether register is pseudo */
123 int spr_num; /* PowerPC SPR number, or -1 if not an SPR.
124 This is an ISA SPR number, not a GDB
128 /* Hook for determining the TOC address when calling functions in the
129 inferior under AIX. The initialization code in rs6000-nat.c sets
130 this hook to point to find_toc_address. */
132 CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL;
134 /* Static function prototypes */
136 static CORE_ADDR branch_dest (struct frame_info *frame, int opcode,
137 int instr, CORE_ADDR pc, CORE_ADDR safety);
138 static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR,
139 struct rs6000_framedata *);
141 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
143 altivec_register_p (int regno)
145 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
146 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
149 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
153 /* Return true if REGNO is an SPE register, false otherwise. */
155 spe_register_p (int regno)
157 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
159 /* Is it a reference to EV0 -- EV31, and do we have those? */
160 if (tdep->ppc_ev0_regnum >= 0
161 && tdep->ppc_ev31_regnum >= 0
162 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum)
165 /* Is it a reference to one of the raw upper GPR halves? */
166 if (tdep->ppc_ev0_upper_regnum >= 0
167 && tdep->ppc_ev0_upper_regnum <= regno
168 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
171 /* Is it a reference to the 64-bit accumulator, and do we have that? */
172 if (tdep->ppc_acc_regnum >= 0
173 && tdep->ppc_acc_regnum == regno)
176 /* Is it a reference to the SPE floating-point status and control register,
177 and do we have that? */
178 if (tdep->ppc_spefscr_regnum >= 0
179 && tdep->ppc_spefscr_regnum == regno)
186 /* Return non-zero if the architecture described by GDBARCH has
187 floating-point registers (f0 --- f31 and fpscr). */
189 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
191 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
193 return (tdep->ppc_fp0_regnum >= 0
194 && tdep->ppc_fpscr_regnum >= 0);
197 /* Return non-zero if the architecture described by GDBARCH has
198 Altivec registers (vr0 --- vr31, vrsave and vscr). */
200 ppc_altivec_support_p (struct gdbarch *gdbarch)
202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
204 return (tdep->ppc_vr0_regnum >= 0
205 && tdep->ppc_vrsave_regnum >= 0);
208 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
211 This is a helper function for init_sim_regno_table, constructing
212 the table mapping GDB register numbers to sim register numbers; we
213 initialize every element in that table to -1 before we start
216 set_sim_regno (int *table, int gdb_regno, int sim_regno)
218 /* Make sure we don't try to assign any given GDB register a sim
219 register number more than once. */
220 gdb_assert (table[gdb_regno] == -1);
221 table[gdb_regno] = sim_regno;
225 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
226 numbers to simulator register numbers, based on the values placed
227 in the ARCH->tdep->ppc_foo_regnum members. */
229 init_sim_regno_table (struct gdbarch *arch)
231 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
232 int total_regs = gdbarch_num_regs (arch);
233 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
235 static const char *const segment_regs[] = {
236 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
237 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
240 /* Presume that all registers not explicitly mentioned below are
241 unavailable from the sim. */
242 for (i = 0; i < total_regs; i++)
245 /* General-purpose registers. */
246 for (i = 0; i < ppc_num_gprs; i++)
247 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
249 /* Floating-point registers. */
250 if (tdep->ppc_fp0_regnum >= 0)
251 for (i = 0; i < ppc_num_fprs; i++)
252 set_sim_regno (sim_regno,
253 tdep->ppc_fp0_regnum + i,
254 sim_ppc_f0_regnum + i);
255 if (tdep->ppc_fpscr_regnum >= 0)
256 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
258 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
259 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
260 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
262 /* Segment registers. */
263 for (i = 0; i < ppc_num_srs; i++)
267 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
269 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
272 /* Altivec registers. */
273 if (tdep->ppc_vr0_regnum >= 0)
275 for (i = 0; i < ppc_num_vrs; i++)
276 set_sim_regno (sim_regno,
277 tdep->ppc_vr0_regnum + i,
278 sim_ppc_vr0_regnum + i);
280 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
281 we can treat this more like the other cases. */
282 set_sim_regno (sim_regno,
283 tdep->ppc_vr0_regnum + ppc_num_vrs,
284 sim_ppc_vscr_regnum);
286 /* vsave is a special-purpose register, so the code below handles it. */
288 /* SPE APU (E500) registers. */
289 if (tdep->ppc_ev0_upper_regnum >= 0)
290 for (i = 0; i < ppc_num_gprs; i++)
291 set_sim_regno (sim_regno,
292 tdep->ppc_ev0_upper_regnum + i,
293 sim_ppc_rh0_regnum + i);
294 if (tdep->ppc_acc_regnum >= 0)
295 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
296 /* spefscr is a special-purpose register, so the code below handles it. */
299 /* Now handle all special-purpose registers. Verify that they
300 haven't mistakenly been assigned numbers by any of the above
302 for (i = 0; i < sim_ppc_num_sprs; i++)
304 const char *spr_name = sim_spr_register_name (i);
307 if (spr_name != NULL)
308 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
311 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
315 /* Drop the initialized array into place. */
316 tdep->sim_regno = sim_regno;
320 /* Given a GDB register number REG, return the corresponding SIM
323 rs6000_register_sim_regno (int reg)
325 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
328 if (tdep->sim_regno == NULL)
329 init_sim_regno_table (current_gdbarch);
332 && reg <= gdbarch_num_regs (current_gdbarch)
333 + gdbarch_num_pseudo_regs (current_gdbarch));
334 sim_regno = tdep->sim_regno[reg];
339 return LEGACY_SIM_REGNO_IGNORE;
344 /* Register set support functions. */
346 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
347 Write the register to REGCACHE. */
350 ppc_supply_reg (struct regcache *regcache, int regnum,
351 const gdb_byte *regs, size_t offset, int regsize)
353 if (regnum != -1 && offset != -1)
357 struct gdbarch *gdbarch = get_regcache_arch (regcache);
358 int gdb_regsize = register_size (gdbarch, regnum);
359 if (gdb_regsize < regsize
360 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
361 offset += regsize - gdb_regsize;
363 regcache_raw_supply (regcache, regnum, regs + offset);
367 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
368 in a field REGSIZE wide. Zero pad as necessary. */
371 ppc_collect_reg (const struct regcache *regcache, int regnum,
372 gdb_byte *regs, size_t offset, int regsize)
374 if (regnum != -1 && offset != -1)
378 struct gdbarch *gdbarch = get_regcache_arch (regcache);
379 int gdb_regsize = register_size (gdbarch, regnum);
380 if (gdb_regsize < regsize)
382 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
384 memset (regs + offset, 0, regsize - gdb_regsize);
385 offset += regsize - gdb_regsize;
388 memset (regs + offset + regsize - gdb_regsize, 0,
389 regsize - gdb_regsize);
392 regcache_raw_collect (regcache, regnum, regs + offset);
397 ppc_greg_offset (struct gdbarch *gdbarch,
398 struct gdbarch_tdep *tdep,
399 const struct ppc_reg_offsets *offsets,
403 *regsize = offsets->gpr_size;
404 if (regnum >= tdep->ppc_gp0_regnum
405 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
406 return (offsets->r0_offset
407 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
409 if (regnum == gdbarch_pc_regnum (gdbarch))
410 return offsets->pc_offset;
412 if (regnum == tdep->ppc_ps_regnum)
413 return offsets->ps_offset;
415 if (regnum == tdep->ppc_lr_regnum)
416 return offsets->lr_offset;
418 if (regnum == tdep->ppc_ctr_regnum)
419 return offsets->ctr_offset;
421 *regsize = offsets->xr_size;
422 if (regnum == tdep->ppc_cr_regnum)
423 return offsets->cr_offset;
425 if (regnum == tdep->ppc_xer_regnum)
426 return offsets->xer_offset;
428 if (regnum == tdep->ppc_mq_regnum)
429 return offsets->mq_offset;
435 ppc_fpreg_offset (struct gdbarch_tdep *tdep,
436 const struct ppc_reg_offsets *offsets,
439 if (regnum >= tdep->ppc_fp0_regnum
440 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
441 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
443 if (regnum == tdep->ppc_fpscr_regnum)
444 return offsets->fpscr_offset;
450 ppc_vrreg_offset (struct gdbarch_tdep *tdep,
451 const struct ppc_reg_offsets *offsets,
454 if (regnum >= tdep->ppc_vr0_regnum
455 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
456 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
458 if (regnum == tdep->ppc_vrsave_regnum - 1)
459 return offsets->vscr_offset;
461 if (regnum == tdep->ppc_vrsave_regnum)
462 return offsets->vrsave_offset;
467 /* Supply register REGNUM in the general-purpose register set REGSET
468 from the buffer specified by GREGS and LEN to register cache
469 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
472 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
473 int regnum, const void *gregs, size_t len)
475 struct gdbarch *gdbarch = get_regcache_arch (regcache);
476 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
477 const struct ppc_reg_offsets *offsets = regset->descr;
484 int gpr_size = offsets->gpr_size;
486 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
487 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
488 i++, offset += gpr_size)
489 ppc_supply_reg (regcache, i, gregs, offset, gpr_size);
491 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
492 gregs, offsets->pc_offset, gpr_size);
493 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
494 gregs, offsets->ps_offset, gpr_size);
495 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
496 gregs, offsets->lr_offset, gpr_size);
497 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
498 gregs, offsets->ctr_offset, gpr_size);
499 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
500 gregs, offsets->cr_offset, offsets->xr_size);
501 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
502 gregs, offsets->xer_offset, offsets->xr_size);
503 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
504 gregs, offsets->mq_offset, offsets->xr_size);
508 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
509 ppc_supply_reg (regcache, regnum, gregs, offset, regsize);
512 /* Supply register REGNUM in the floating-point register set REGSET
513 from the buffer specified by FPREGS and LEN to register cache
514 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
517 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
518 int regnum, const void *fpregs, size_t len)
520 struct gdbarch *gdbarch = get_regcache_arch (regcache);
521 struct gdbarch_tdep *tdep;
522 const struct ppc_reg_offsets *offsets;
525 if (!ppc_floating_point_unit_p (gdbarch))
528 tdep = gdbarch_tdep (gdbarch);
529 offsets = regset->descr;
534 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
535 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
537 ppc_supply_reg (regcache, i, fpregs, offset, 8);
539 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
540 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
544 offset = ppc_fpreg_offset (tdep, offsets, regnum);
545 ppc_supply_reg (regcache, regnum, fpregs, offset,
546 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
549 /* Supply register REGNUM in the Altivec register set REGSET
550 from the buffer specified by VRREGS and LEN to register cache
551 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
554 ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
555 int regnum, const void *vrregs, size_t len)
557 struct gdbarch *gdbarch = get_regcache_arch (regcache);
558 struct gdbarch_tdep *tdep;
559 const struct ppc_reg_offsets *offsets;
562 if (!ppc_altivec_support_p (gdbarch))
565 tdep = gdbarch_tdep (gdbarch);
566 offsets = regset->descr;
571 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
572 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
574 ppc_supply_reg (regcache, i, vrregs, offset, 16);
576 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
577 vrregs, offsets->vscr_offset, 4);
579 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
580 vrregs, offsets->vrsave_offset, 4);
584 offset = ppc_vrreg_offset (tdep, offsets, regnum);
585 if (regnum != tdep->ppc_vrsave_regnum
586 && regnum != tdep->ppc_vrsave_regnum - 1)
587 ppc_supply_reg (regcache, regnum, vrregs, offset, 16);
589 ppc_supply_reg (regcache, regnum,
593 /* Collect register REGNUM in the general-purpose register set
594 REGSET from register cache REGCACHE into the buffer specified by
595 GREGS and LEN. If REGNUM is -1, do this for all registers in
599 ppc_collect_gregset (const struct regset *regset,
600 const struct regcache *regcache,
601 int regnum, void *gregs, size_t len)
603 struct gdbarch *gdbarch = get_regcache_arch (regcache);
604 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
605 const struct ppc_reg_offsets *offsets = regset->descr;
612 int gpr_size = offsets->gpr_size;
614 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
615 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
616 i++, offset += gpr_size)
617 ppc_collect_reg (regcache, i, gregs, offset, gpr_size);
619 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
620 gregs, offsets->pc_offset, gpr_size);
621 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
622 gregs, offsets->ps_offset, gpr_size);
623 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
624 gregs, offsets->lr_offset, gpr_size);
625 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
626 gregs, offsets->ctr_offset, gpr_size);
627 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
628 gregs, offsets->cr_offset, offsets->xr_size);
629 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
630 gregs, offsets->xer_offset, offsets->xr_size);
631 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
632 gregs, offsets->mq_offset, offsets->xr_size);
636 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
637 ppc_collect_reg (regcache, regnum, gregs, offset, regsize);
640 /* Collect register REGNUM in the floating-point register set
641 REGSET from register cache REGCACHE into the buffer specified by
642 FPREGS and LEN. If REGNUM is -1, do this for all registers in
646 ppc_collect_fpregset (const struct regset *regset,
647 const struct regcache *regcache,
648 int regnum, void *fpregs, size_t len)
650 struct gdbarch *gdbarch = get_regcache_arch (regcache);
651 struct gdbarch_tdep *tdep;
652 const struct ppc_reg_offsets *offsets;
655 if (!ppc_floating_point_unit_p (gdbarch))
658 tdep = gdbarch_tdep (gdbarch);
659 offsets = regset->descr;
664 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
665 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
667 ppc_collect_reg (regcache, i, fpregs, offset, 8);
669 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
670 fpregs, offsets->fpscr_offset, offsets->fpscr_size);
674 offset = ppc_fpreg_offset (tdep, offsets, regnum);
675 ppc_collect_reg (regcache, regnum, fpregs, offset,
676 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
679 /* Collect register REGNUM in the Altivec register set
680 REGSET from register cache REGCACHE into the buffer specified by
681 VRREGS and LEN. If REGNUM is -1, do this for all registers in
685 ppc_collect_vrregset (const struct regset *regset,
686 const struct regcache *regcache,
687 int regnum, void *vrregs, size_t len)
689 struct gdbarch *gdbarch = get_regcache_arch (regcache);
690 struct gdbarch_tdep *tdep;
691 const struct ppc_reg_offsets *offsets;
694 if (!ppc_altivec_support_p (gdbarch))
697 tdep = gdbarch_tdep (gdbarch);
698 offsets = regset->descr;
703 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
704 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
706 ppc_collect_reg (regcache, i, vrregs, offset, 16);
708 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
709 vrregs, offsets->vscr_offset, 4);
711 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
712 vrregs, offsets->vrsave_offset, 4);
716 offset = ppc_vrreg_offset (tdep, offsets, regnum);
717 if (regnum != tdep->ppc_vrsave_regnum
718 && regnum != tdep->ppc_vrsave_regnum - 1)
719 ppc_collect_reg (regcache, regnum, vrregs, offset, 16);
721 ppc_collect_reg (regcache, regnum,
726 /* Read a LEN-byte address from debugged memory address MEMADDR. */
729 read_memory_addr (CORE_ADDR memaddr, int len)
731 return read_memory_unsigned_integer (memaddr, len);
735 rs6000_skip_prologue (CORE_ADDR pc)
737 struct rs6000_framedata frame;
738 CORE_ADDR limit_pc, func_addr;
740 /* See if we can determine the end of the prologue via the symbol table.
741 If so, then return either PC, or the PC after the prologue, whichever
743 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
745 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr);
746 if (post_prologue_pc != 0)
747 return max (pc, post_prologue_pc);
750 /* Can't determine prologue from the symbol table, need to examine
753 /* Find an upper limit on the function prologue using the debug
754 information. If the debug information could not be used to provide
755 that bound, then use an arbitrary large number as the upper bound. */
756 limit_pc = skip_prologue_using_sal (pc);
758 limit_pc = pc + 100; /* Magic. */
760 pc = skip_prologue (pc, limit_pc, &frame);
765 insn_changes_sp_or_jumps (unsigned long insn)
767 int opcode = (insn >> 26) & 0x03f;
768 int sd = (insn >> 21) & 0x01f;
769 int a = (insn >> 16) & 0x01f;
770 int subcode = (insn >> 1) & 0x3ff;
772 /* Changes the stack pointer. */
774 /* NOTE: There are many ways to change the value of a given register.
775 The ways below are those used when the register is R1, the SP,
776 in a funtion's epilogue. */
778 if (opcode == 31 && subcode == 444 && a == 1)
779 return 1; /* mr R1,Rn */
780 if (opcode == 14 && sd == 1)
781 return 1; /* addi R1,Rn,simm */
782 if (opcode == 58 && sd == 1)
783 return 1; /* ld R1,ds(Rn) */
785 /* Transfers control. */
791 if (opcode == 19 && subcode == 16)
793 if (opcode == 19 && subcode == 528)
794 return 1; /* bcctr */
799 /* Return true if we are in the function's epilogue, i.e. after the
800 instruction that destroyed the function's stack frame.
802 1) scan forward from the point of execution:
803 a) If you find an instruction that modifies the stack pointer
804 or transfers control (except a return), execution is not in
806 b) Stop scanning if you find a return instruction or reach the
807 end of the function or reach the hard limit for the size of
809 2) scan backward from the point of execution:
810 a) If you find an instruction that modifies the stack pointer,
811 execution *is* in an epilogue, return.
812 b) Stop scanning if you reach an instruction that transfers
813 control or the beginning of the function or reach the hard
814 limit for the size of an epilogue. */
817 rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc)
819 bfd_byte insn_buf[PPC_INSN_SIZE];
820 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
822 struct frame_info *curfrm;
824 /* Find the search limits based on function boundaries and hard limit. */
826 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
829 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
830 if (epilogue_start < func_start) epilogue_start = func_start;
832 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
833 if (epilogue_end > func_end) epilogue_end = func_end;
835 curfrm = get_current_frame ();
837 /* Scan forward until next 'blr'. */
839 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
841 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
843 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
844 if (insn == 0x4e800020)
846 if (insn_changes_sp_or_jumps (insn))
850 /* Scan backward until adjustment to stack pointer (R1). */
852 for (scan_pc = pc - PPC_INSN_SIZE;
853 scan_pc >= epilogue_start;
854 scan_pc -= PPC_INSN_SIZE)
856 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
858 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE);
859 if (insn_changes_sp_or_jumps (insn))
866 /* Get the ith function argument for the current function. */
868 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
871 return get_frame_register_unsigned (frame, 3 + argi);
874 /* Calculate the destination of a branch/jump. Return -1 if not a branch. */
877 branch_dest (struct frame_info *frame, int opcode, int instr,
878 CORE_ADDR pc, CORE_ADDR safety)
880 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame));
886 absolute = (int) ((instr >> 1) & 1);
891 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */
895 dest = pc + immediate;
899 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */
903 dest = pc + immediate;
907 ext_op = (instr >> 1) & 0x3ff;
909 if (ext_op == 16) /* br conditional register */
911 dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3;
913 /* If we are about to return from a signal handler, dest is
914 something like 0x3c90. The current frame is a signal handler
915 caller frame, upon completion of the sigreturn system call
916 execution will return to the saved PC in the frame. */
917 if (dest < tdep->text_segment_base)
918 dest = read_memory_addr (get_frame_base (frame) + SIG_FRAME_PC_OFFSET,
922 else if (ext_op == 528) /* br cond to count reg */
924 dest = get_frame_register_unsigned (frame, tdep->ppc_ctr_regnum) & ~3;
926 /* If we are about to execute a system call, dest is something
927 like 0x22fc or 0x3b00. Upon completion the system call
928 will return to the address in the link register. */
929 if (dest < tdep->text_segment_base)
930 dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3;
939 return (dest < tdep->text_segment_base) ? safety : dest;
943 /* Sequence of bytes for breakpoint instruction. */
945 const static unsigned char *
946 rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size)
948 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
949 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
951 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
952 return big_breakpoint;
954 return little_breakpoint;
958 /* Instruction masks used during single-stepping of atomic sequences. */
959 #define LWARX_MASK 0xfc0007fe
960 #define LWARX_INSTRUCTION 0x7c000028
961 #define LDARX_INSTRUCTION 0x7c0000A8
962 #define STWCX_MASK 0xfc0007ff
963 #define STWCX_INSTRUCTION 0x7c00012d
964 #define STDCX_INSTRUCTION 0x7c0001ad
965 #define BC_MASK 0xfc000000
966 #define BC_INSTRUCTION 0x40000000
968 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
969 instruction and ending with a STWCX/STDCX instruction. If such a sequence
970 is found, attempt to step through it. A breakpoint is placed at the end of
974 deal_with_atomic_sequence (struct frame_info *frame)
976 CORE_ADDR pc = get_frame_pc (frame);
977 CORE_ADDR breaks[2] = {-1, -1};
979 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */
980 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
981 int insn = read_memory_integer (loc, PPC_INSN_SIZE);
984 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
985 const int atomic_sequence_length = 16; /* Instruction sequence length. */
986 int opcode; /* Branch instruction's OPcode. */
987 int bc_insn_count = 0; /* Conditional branch instruction count. */
989 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
990 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
991 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
994 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
996 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
998 loc += PPC_INSN_SIZE;
999 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1001 /* Assume that there is at most one conditional branch in the atomic
1002 sequence. If a conditional branch is found, put a breakpoint in
1003 its destination address. */
1004 if ((insn & BC_MASK) == BC_INSTRUCTION)
1006 if (bc_insn_count >= 1)
1007 return 0; /* More than one conditional branch found, fallback
1008 to the standard single-step code. */
1010 opcode = insn >> 26;
1011 branch_bp = branch_dest (frame, opcode, insn, pc, breaks[0]);
1013 if (branch_bp != -1)
1015 breaks[1] = branch_bp;
1021 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1022 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1026 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1027 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1028 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1032 loc += PPC_INSN_SIZE;
1033 insn = read_memory_integer (loc, PPC_INSN_SIZE);
1035 /* Insert a breakpoint right after the end of the atomic sequence. */
1038 /* Check for duplicated breakpoints. Check also for a breakpoint
1039 placed (branch instruction's destination) at the stwcx/stdcx
1040 instruction, this resets the reservation and take us back to the
1041 lwarx/ldarx instruction at the beginning of the atomic sequence. */
1042 if (last_breakpoint && ((breaks[1] == breaks[0])
1043 || (breaks[1] == closing_insn)))
1044 last_breakpoint = 0;
1046 /* Effectively inserts the breakpoints. */
1047 for (index = 0; index <= last_breakpoint; index++)
1048 insert_single_step_breakpoint (breaks[index]);
1053 /* AIX does not support PT_STEP. Simulate it. */
1056 rs6000_software_single_step (struct frame_info *frame)
1060 const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz);
1063 CORE_ADDR breaks[2];
1066 loc = get_frame_pc (frame);
1068 insn = read_memory_integer (loc, 4);
1070 if (deal_with_atomic_sequence (frame))
1073 breaks[0] = loc + breakp_sz;
1074 opcode = insn >> 26;
1075 breaks[1] = branch_dest (frame, opcode, insn, loc, breaks[0]);
1077 /* Don't put two breakpoints on the same address. */
1078 if (breaks[1] == breaks[0])
1081 for (ii = 0; ii < 2; ++ii)
1083 /* ignore invalid breakpoint. */
1084 if (breaks[ii] == -1)
1086 insert_single_step_breakpoint (breaks[ii]);
1089 errno = 0; /* FIXME, don't ignore errors! */
1090 /* What errors? {read,write}_memory call error(). */
1095 #define SIGNED_SHORT(x) \
1096 ((sizeof (short) == 2) \
1097 ? ((int)(short)(x)) \
1098 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1100 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1102 /* Limit the number of skipped non-prologue instructions, as the examining
1103 of the prologue is expensive. */
1104 static int max_skip_non_prologue_insns = 10;
1106 /* Return nonzero if the given instruction OP can be part of the prologue
1107 of a function and saves a parameter on the stack. FRAMEP should be
1108 set if one of the previous instructions in the function has set the
1112 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1114 /* Move parameters from argument registers to temporary register. */
1115 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1117 /* Rx must be scratch register r0. */
1118 const int rx_regno = (op >> 16) & 31;
1119 /* Ry: Only r3 - r10 are used for parameter passing. */
1120 const int ry_regno = GET_SRC_REG (op);
1122 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1124 *r0_contains_arg = 1;
1131 /* Save a General Purpose Register on stack. */
1133 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1134 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1136 /* Rx: Only r3 - r10 are used for parameter passing. */
1137 const int rx_regno = GET_SRC_REG (op);
1139 return (rx_regno >= 3 && rx_regno <= 10);
1142 /* Save a General Purpose Register on stack via the Frame Pointer. */
1145 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1146 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1147 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1149 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1150 However, the compiler sometimes uses r0 to hold an argument. */
1151 const int rx_regno = GET_SRC_REG (op);
1153 return ((rx_regno >= 3 && rx_regno <= 10)
1154 || (rx_regno == 0 && *r0_contains_arg));
1157 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1159 /* Only f2 - f8 are used for parameter passing. */
1160 const int src_regno = GET_SRC_REG (op);
1162 return (src_regno >= 2 && src_regno <= 8);
1165 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1167 /* Only f2 - f8 are used for parameter passing. */
1168 const int src_regno = GET_SRC_REG (op);
1170 return (src_regno >= 2 && src_regno <= 8);
1173 /* Not an insn that saves a parameter on stack. */
1177 /* Assuming that INSN is a "bl" instruction located at PC, return
1178 nonzero if the destination of the branch is a "blrl" instruction.
1180 This sequence is sometimes found in certain function prologues.
1181 It allows the function to load the LR register with a value that
1182 they can use to access PIC data using PC-relative offsets. */
1185 bl_to_blrl_insn_p (CORE_ADDR pc, int insn)
1192 absolute = (int) ((insn >> 1) & 1);
1193 immediate = ((insn & ~3) << 6) >> 6;
1197 dest = pc + immediate;
1199 dest_insn = read_memory_integer (dest, 4);
1200 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1206 /* return pc value after skipping a function prologue and also return
1207 information about a function frame.
1209 in struct rs6000_framedata fdata:
1210 - frameless is TRUE, if function does not have a frame.
1211 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1212 - offset is the initial size of this stack frame --- the amount by
1213 which we decrement the sp to allocate the frame.
1214 - saved_gpr is the number of the first saved gpr.
1215 - saved_fpr is the number of the first saved fpr.
1216 - saved_vr is the number of the first saved vr.
1217 - saved_ev is the number of the first saved ev.
1218 - alloca_reg is the number of the register used for alloca() handling.
1220 - gpr_offset is the offset of the first saved gpr from the previous frame.
1221 - fpr_offset is the offset of the first saved fpr from the previous frame.
1222 - vr_offset is the offset of the first saved vr from the previous frame.
1223 - ev_offset is the offset of the first saved ev from the previous frame.
1224 - lr_offset is the offset of the saved lr
1225 - cr_offset is the offset of the saved cr
1226 - vrsave_offset is the offset of the saved vrsave register
1230 skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata)
1232 CORE_ADDR orig_pc = pc;
1233 CORE_ADDR last_prologue_pc = pc;
1234 CORE_ADDR li_found_pc = 0;
1238 long vr_saved_offset = 0;
1244 int vrsave_reg = -1;
1247 int minimal_toc_loaded = 0;
1248 int prev_insn_was_prologue_insn = 1;
1249 int num_skip_non_prologue_insns = 0;
1250 int r0_contains_arg = 0;
1251 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch);
1252 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
1254 memset (fdata, 0, sizeof (struct rs6000_framedata));
1255 fdata->saved_gpr = -1;
1256 fdata->saved_fpr = -1;
1257 fdata->saved_vr = -1;
1258 fdata->saved_ev = -1;
1259 fdata->alloca_reg = -1;
1260 fdata->frameless = 1;
1261 fdata->nosavedpc = 1;
1265 /* Sometimes it isn't clear if an instruction is a prologue
1266 instruction or not. When we encounter one of these ambiguous
1267 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1268 Otherwise, we'll assume that it really is a prologue instruction. */
1269 if (prev_insn_was_prologue_insn)
1270 last_prologue_pc = pc;
1272 /* Stop scanning if we've hit the limit. */
1276 prev_insn_was_prologue_insn = 1;
1278 /* Fetch the instruction and convert it to an integer. */
1279 if (target_read_memory (pc, buf, 4))
1281 op = extract_unsigned_integer (buf, 4);
1283 if ((op & 0xfc1fffff) == 0x7c0802a6)
1285 /* Since shared library / PIC code, which needs to get its
1286 address at runtime, can appear to save more than one link
1300 remember just the first one, but skip over additional
1303 lr_reg = (op & 0x03e00000);
1305 r0_contains_arg = 0;
1308 else if ((op & 0xfc1fffff) == 0x7c000026)
1310 cr_reg = (op & 0x03e00000);
1312 r0_contains_arg = 0;
1316 else if ((op & 0xfc1f0000) == 0xd8010000)
1317 { /* stfd Rx,NUM(r1) */
1318 reg = GET_SRC_REG (op);
1319 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1321 fdata->saved_fpr = reg;
1322 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1327 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1328 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1329 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1330 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1333 reg = GET_SRC_REG (op);
1334 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1336 fdata->saved_gpr = reg;
1337 if ((op & 0xfc1f0003) == 0xf8010000)
1339 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1344 else if ((op & 0xffff0000) == 0x60000000)
1347 /* Allow nops in the prologue, but do not consider them to
1348 be part of the prologue unless followed by other prologue
1350 prev_insn_was_prologue_insn = 0;
1354 else if ((op & 0xffff0000) == 0x3c000000)
1355 { /* addis 0,0,NUM, used
1356 for >= 32k frames */
1357 fdata->offset = (op & 0x0000ffff) << 16;
1358 fdata->frameless = 0;
1359 r0_contains_arg = 0;
1363 else if ((op & 0xffff0000) == 0x60000000)
1364 { /* ori 0,0,NUM, 2nd ha
1365 lf of >= 32k frames */
1366 fdata->offset |= (op & 0x0000ffff);
1367 fdata->frameless = 0;
1368 r0_contains_arg = 0;
1372 else if (lr_reg >= 0 &&
1373 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1374 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1375 /* stw Rx, NUM(r1) */
1376 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1377 /* stwu Rx, NUM(r1) */
1378 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1379 { /* where Rx == lr */
1380 fdata->lr_offset = offset;
1381 fdata->nosavedpc = 0;
1382 /* Invalidate lr_reg, but don't set it to -1.
1383 That would mean that it had never been set. */
1385 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1386 (op & 0xfc000000) == 0x90000000) /* stw */
1388 /* Does not update r1, so add displacement to lr_offset. */
1389 fdata->lr_offset += SIGNED_SHORT (op);
1394 else if (cr_reg >= 0 &&
1395 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1396 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1397 /* stw Rx, NUM(r1) */
1398 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1399 /* stwu Rx, NUM(r1) */
1400 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1401 { /* where Rx == cr */
1402 fdata->cr_offset = offset;
1403 /* Invalidate cr_reg, but don't set it to -1.
1404 That would mean that it had never been set. */
1406 if ((op & 0xfc000003) == 0xf8000000 ||
1407 (op & 0xfc000000) == 0x90000000)
1409 /* Does not update r1, so add displacement to cr_offset. */
1410 fdata->cr_offset += SIGNED_SHORT (op);
1415 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1417 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1418 prediction bits. If the LR has already been saved, we can
1422 else if (op == 0x48000005)
1428 else if (op == 0x48000004)
1433 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1434 in V.4 -mminimal-toc */
1435 (op & 0xffff0000) == 0x3bde0000)
1436 { /* addi 30,30,foo@l */
1440 else if ((op & 0xfc000001) == 0x48000001)
1444 fdata->frameless = 0;
1446 /* If the return address has already been saved, we can skip
1447 calls to blrl (for PIC). */
1448 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op))
1451 /* Don't skip over the subroutine call if it is not within
1452 the first three instructions of the prologue and either
1453 we have no line table information or the line info tells
1454 us that the subroutine call is not part of the line
1455 associated with the prologue. */
1456 if ((pc - orig_pc) > 8)
1458 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1459 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1461 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line))
1465 op = read_memory_integer (pc + 4, 4);
1467 /* At this point, make sure this is not a trampoline
1468 function (a function that simply calls another functions,
1469 and nothing else). If the next is not a nop, this branch
1470 was part of the function prologue. */
1472 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1473 break; /* don't skip over
1478 /* update stack pointer */
1479 else if ((op & 0xfc1f0000) == 0x94010000)
1480 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1481 fdata->frameless = 0;
1482 fdata->offset = SIGNED_SHORT (op);
1483 offset = fdata->offset;
1486 else if ((op & 0xfc1f016a) == 0x7c01016e)
1487 { /* stwux rX,r1,rY */
1488 /* no way to figure out what r1 is going to be */
1489 fdata->frameless = 0;
1490 offset = fdata->offset;
1493 else if ((op & 0xfc1f0003) == 0xf8010001)
1494 { /* stdu rX,NUM(r1) */
1495 fdata->frameless = 0;
1496 fdata->offset = SIGNED_SHORT (op & ~3UL);
1497 offset = fdata->offset;
1500 else if ((op & 0xfc1f016a) == 0x7c01016a)
1501 { /* stdux rX,r1,rY */
1502 /* no way to figure out what r1 is going to be */
1503 fdata->frameless = 0;
1504 offset = fdata->offset;
1507 else if ((op & 0xffff0000) == 0x38210000)
1508 { /* addi r1,r1,SIMM */
1509 fdata->frameless = 0;
1510 fdata->offset += SIGNED_SHORT (op);
1511 offset = fdata->offset;
1514 /* Load up minimal toc pointer. Do not treat an epilogue restore
1515 of r31 as a minimal TOC load. */
1516 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1517 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1519 && !minimal_toc_loaded)
1521 minimal_toc_loaded = 1;
1524 /* move parameters from argument registers to local variable
1527 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1528 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1529 (((op >> 21) & 31) <= 10) &&
1530 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */
1534 /* store parameters in stack */
1536 /* Move parameters from argument registers to temporary register. */
1537 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1541 /* Set up frame pointer */
1543 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1544 || op == 0x7c3f0b78)
1546 fdata->frameless = 0;
1548 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1551 /* Another way to set up the frame pointer. */
1553 else if ((op & 0xfc1fffff) == 0x38010000)
1554 { /* addi rX, r1, 0x0 */
1555 fdata->frameless = 0;
1557 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1558 + ((op & ~0x38010000) >> 21));
1561 /* AltiVec related instructions. */
1562 /* Store the vrsave register (spr 256) in another register for
1563 later manipulation, or load a register into the vrsave
1564 register. 2 instructions are used: mfvrsave and
1565 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1566 and mtspr SPR256, Rn. */
1567 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1568 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1569 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1571 vrsave_reg = GET_SRC_REG (op);
1574 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1578 /* Store the register where vrsave was saved to onto the stack:
1579 rS is the register where vrsave was stored in a previous
1581 /* 100100 sssss 00001 dddddddd dddddddd */
1582 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1584 if (vrsave_reg == GET_SRC_REG (op))
1586 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1591 /* Compute the new value of vrsave, by modifying the register
1592 where vrsave was saved to. */
1593 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1594 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1598 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1599 in a pair of insns to save the vector registers on the
1601 /* 001110 00000 00000 iiii iiii iiii iiii */
1602 /* 001110 01110 00000 iiii iiii iiii iiii */
1603 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1604 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1606 if ((op & 0xffff0000) == 0x38000000)
1607 r0_contains_arg = 0;
1609 vr_saved_offset = SIGNED_SHORT (op);
1611 /* This insn by itself is not part of the prologue, unless
1612 if part of the pair of insns mentioned above. So do not
1613 record this insn as part of the prologue yet. */
1614 prev_insn_was_prologue_insn = 0;
1616 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1617 /* 011111 sssss 11111 00000 00111001110 */
1618 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1620 if (pc == (li_found_pc + 4))
1622 vr_reg = GET_SRC_REG (op);
1623 /* If this is the first vector reg to be saved, or if
1624 it has a lower number than others previously seen,
1625 reupdate the frame info. */
1626 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1628 fdata->saved_vr = vr_reg;
1629 fdata->vr_offset = vr_saved_offset + offset;
1631 vr_saved_offset = -1;
1636 /* End AltiVec related instructions. */
1638 /* Start BookE related instructions. */
1639 /* Store gen register S at (r31+uimm).
1640 Any register less than r13 is volatile, so we don't care. */
1641 /* 000100 sssss 11111 iiiii 01100100001 */
1642 else if (arch_info->mach == bfd_mach_ppc_e500
1643 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
1645 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
1648 ev_reg = GET_SRC_REG (op);
1649 imm = (op >> 11) & 0x1f;
1650 ev_offset = imm * 8;
1651 /* If this is the first vector reg to be saved, or if
1652 it has a lower number than others previously seen,
1653 reupdate the frame info. */
1654 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1656 fdata->saved_ev = ev_reg;
1657 fdata->ev_offset = ev_offset + offset;
1662 /* Store gen register rS at (r1+rB). */
1663 /* 000100 sssss 00001 bbbbb 01100100000 */
1664 else if (arch_info->mach == bfd_mach_ppc_e500
1665 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
1667 if (pc == (li_found_pc + 4))
1669 ev_reg = GET_SRC_REG (op);
1670 /* If this is the first vector reg to be saved, or if
1671 it has a lower number than others previously seen,
1672 reupdate the frame info. */
1673 /* We know the contents of rB from the previous instruction. */
1674 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1676 fdata->saved_ev = ev_reg;
1677 fdata->ev_offset = vr_saved_offset + offset;
1679 vr_saved_offset = -1;
1685 /* Store gen register r31 at (rA+uimm). */
1686 /* 000100 11111 aaaaa iiiii 01100100001 */
1687 else if (arch_info->mach == bfd_mach_ppc_e500
1688 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
1690 /* Wwe know that the source register is 31 already, but
1691 it can't hurt to compute it. */
1692 ev_reg = GET_SRC_REG (op);
1693 ev_offset = ((op >> 11) & 0x1f) * 8;
1694 /* If this is the first vector reg to be saved, or if
1695 it has a lower number than others previously seen,
1696 reupdate the frame info. */
1697 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1699 fdata->saved_ev = ev_reg;
1700 fdata->ev_offset = ev_offset + offset;
1705 /* Store gen register S at (r31+r0).
1706 Store param on stack when offset from SP bigger than 4 bytes. */
1707 /* 000100 sssss 11111 00000 01100100000 */
1708 else if (arch_info->mach == bfd_mach_ppc_e500
1709 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
1711 if (pc == (li_found_pc + 4))
1713 if ((op & 0x03e00000) >= 0x01a00000)
1715 ev_reg = GET_SRC_REG (op);
1716 /* If this is the first vector reg to be saved, or if
1717 it has a lower number than others previously seen,
1718 reupdate the frame info. */
1719 /* We know the contents of r0 from the previous
1721 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
1723 fdata->saved_ev = ev_reg;
1724 fdata->ev_offset = vr_saved_offset + offset;
1728 vr_saved_offset = -1;
1733 /* End BookE related instructions. */
1737 /* Not a recognized prologue instruction.
1738 Handle optimizer code motions into the prologue by continuing
1739 the search if we have no valid frame yet or if the return
1740 address is not yet saved in the frame. */
1741 if (fdata->frameless == 0 && fdata->nosavedpc == 0)
1744 if (op == 0x4e800020 /* blr */
1745 || op == 0x4e800420) /* bctr */
1746 /* Do not scan past epilogue in frameless functions or
1749 if ((op & 0xf4000000) == 0x40000000) /* bxx */
1750 /* Never skip branches. */
1753 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
1754 /* Do not scan too many insns, scanning insns is expensive with
1758 /* Continue scanning. */
1759 prev_insn_was_prologue_insn = 0;
1765 /* I have problems with skipping over __main() that I need to address
1766 * sometime. Previously, I used to use misc_function_vector which
1767 * didn't work as well as I wanted to be. -MGO */
1769 /* If the first thing after skipping a prolog is a branch to a function,
1770 this might be a call to an initializer in main(), introduced by gcc2.
1771 We'd like to skip over it as well. Fortunately, xlc does some extra
1772 work before calling a function right after a prologue, thus we can
1773 single out such gcc2 behaviour. */
1776 if ((op & 0xfc000001) == 0x48000001)
1777 { /* bl foo, an initializer function? */
1778 op = read_memory_integer (pc + 4, 4);
1780 if (op == 0x4def7b82)
1781 { /* cror 0xf, 0xf, 0xf (nop) */
1783 /* Check and see if we are in main. If so, skip over this
1784 initializer function as well. */
1786 tmp = find_pc_misc_function (pc);
1788 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
1794 fdata->offset = -fdata->offset;
1795 return last_prologue_pc;
1799 /*************************************************************************
1800 Support for creating pushing a dummy frame into the stack, and popping
1802 *************************************************************************/
1805 /* All the ABI's require 16 byte alignment. */
1807 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
1809 return (addr & -16);
1812 /* Pass the arguments in either registers, or in the stack. In RS/6000,
1813 the first eight words of the argument list (that might be less than
1814 eight parameters if some parameters occupy more than one word) are
1815 passed in r3..r10 registers. float and double parameters are
1816 passed in fpr's, in addition to that. Rest of the parameters if any
1817 are passed in user stack. There might be cases in which half of the
1818 parameter is copied into registers, the other half is pushed into
1821 Stack must be aligned on 64-bit boundaries when synthesizing
1824 If the function is returning a structure, then the return address is passed
1825 in r3, then the first 7 words of the parameters can be passed in registers,
1826 starting from r4. */
1829 rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1830 struct regcache *regcache, CORE_ADDR bp_addr,
1831 int nargs, struct value **args, CORE_ADDR sp,
1832 int struct_return, CORE_ADDR struct_addr)
1834 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1837 int argno; /* current argument number */
1838 int argbytes; /* current argument byte */
1839 gdb_byte tmp_buffer[50];
1840 int f_argno = 0; /* current floating point argno */
1841 int wordsize = gdbarch_tdep (gdbarch)->wordsize;
1842 CORE_ADDR func_addr = find_function_addr (function, NULL);
1844 struct value *arg = 0;
1849 /* The calling convention this function implements assumes the
1850 processor has floating-point registers. We shouldn't be using it
1851 on PPC variants that lack them. */
1852 gdb_assert (ppc_floating_point_unit_p (gdbarch));
1854 /* The first eight words of ther arguments are passed in registers.
1855 Copy them appropriately. */
1858 /* If the function is returning a `struct', then the first word
1859 (which will be passed in r3) is used for struct return address.
1860 In that case we should advance one word and start from r4
1861 register to copy parameters. */
1864 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
1870 effectively indirect call... gcc does...
1872 return_val example( float, int);
1875 float in fp0, int in r3
1876 offset of stack on overflow 8/16
1877 for varargs, must go by type.
1879 float in r3&r4, int in r5
1880 offset of stack on overflow different
1882 return in r3 or f0. If no float, must study how gcc emulates floats;
1883 pay attention to arg promotion.
1884 User may have to cast\args to handle promotion correctly
1885 since gdb won't know if prototype supplied or not.
1888 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii)
1890 int reg_size = register_size (gdbarch, ii + 3);
1893 type = check_typedef (value_type (arg));
1894 len = TYPE_LENGTH (type);
1896 if (TYPE_CODE (type) == TYPE_CODE_FLT)
1899 /* Floating point arguments are passed in fpr's, as well as gpr's.
1900 There are 13 fpr's reserved for passing parameters. At this point
1901 there is no way we would run out of them. */
1903 gdb_assert (len <= 8);
1905 regcache_cooked_write (regcache,
1906 tdep->ppc_fp0_regnum + 1 + f_argno,
1907 value_contents (arg));
1914 /* Argument takes more than one register. */
1915 while (argbytes < len)
1917 gdb_byte word[MAX_REGISTER_SIZE];
1918 memset (word, 0, reg_size);
1920 ((char *) value_contents (arg)) + argbytes,
1921 (len - argbytes) > reg_size
1922 ? reg_size : len - argbytes);
1923 regcache_cooked_write (regcache,
1924 tdep->ppc_gp0_regnum + 3 + ii,
1926 ++ii, argbytes += reg_size;
1929 goto ran_out_of_registers_for_arguments;
1936 /* Argument can fit in one register. No problem. */
1937 int adj = gdbarch_byte_order (gdbarch)
1938 == BFD_ENDIAN_BIG ? reg_size - len : 0;
1939 gdb_byte word[MAX_REGISTER_SIZE];
1941 memset (word, 0, reg_size);
1942 memcpy (word, value_contents (arg), len);
1943 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word);
1948 ran_out_of_registers_for_arguments:
1950 regcache_cooked_read_unsigned (regcache,
1951 gdbarch_sp_regnum (gdbarch),
1954 /* Location for 8 parameters are always reserved. */
1957 /* Another six words for back chain, TOC register, link register, etc. */
1960 /* Stack pointer must be quadword aligned. */
1963 /* If there are more arguments, allocate space for them in
1964 the stack, then push them starting from the ninth one. */
1966 if ((argno < nargs) || argbytes)
1972 space += ((len - argbytes + 3) & -4);
1978 for (; jj < nargs; ++jj)
1980 struct value *val = args[jj];
1981 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4;
1984 /* Add location required for the rest of the parameters. */
1985 space = (space + 15) & -16;
1988 /* This is another instance we need to be concerned about
1989 securing our stack space. If we write anything underneath %sp
1990 (r1), we might conflict with the kernel who thinks he is free
1991 to use this area. So, update %sp first before doing anything
1994 regcache_raw_write_signed (regcache,
1995 gdbarch_sp_regnum (gdbarch), sp);
1997 /* If the last argument copied into the registers didn't fit there
1998 completely, push the rest of it into stack. */
2002 write_memory (sp + 24 + (ii * 4),
2003 value_contents (arg) + argbytes,
2006 ii += ((len - argbytes + 3) & -4) / 4;
2009 /* Push the rest of the arguments into stack. */
2010 for (; argno < nargs; ++argno)
2014 type = check_typedef (value_type (arg));
2015 len = TYPE_LENGTH (type);
2018 /* Float types should be passed in fpr's, as well as in the
2020 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13)
2023 gdb_assert (len <= 8);
2025 regcache_cooked_write (regcache,
2026 tdep->ppc_fp0_regnum + 1 + f_argno,
2027 value_contents (arg));
2031 write_memory (sp + 24 + (ii * 4), value_contents (arg), len);
2032 ii += ((len + 3) & -4) / 4;
2036 /* Set the stack pointer. According to the ABI, the SP is meant to
2037 be set _before_ the corresponding stack space is used. On AIX,
2038 this even applies when the target has been completely stopped!
2039 Not doing this can lead to conflicts with the kernel which thinks
2040 that it still has control over this not-yet-allocated stack
2042 regcache_raw_write_signed (regcache, gdbarch_sp_regnum (gdbarch), sp);
2044 /* Set back chain properly. */
2045 store_unsigned_integer (tmp_buffer, wordsize, saved_sp);
2046 write_memory (sp, tmp_buffer, wordsize);
2048 /* Point the inferior function call's return address at the dummy's
2050 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr);
2052 /* Set the TOC register, get the value from the objfile reader
2053 which, in turn, gets it from the VMAP table. */
2054 if (rs6000_find_toc_address_hook != NULL)
2056 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr);
2057 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue);
2060 target_store_registers (regcache, -1);
2064 static enum return_value_convention
2065 rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype,
2066 struct regcache *regcache, gdb_byte *readbuf,
2067 const gdb_byte *writebuf)
2069 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2072 /* The calling convention this function implements assumes the
2073 processor has floating-point registers. We shouldn't be using it
2074 on PowerPC variants that lack them. */
2075 gdb_assert (ppc_floating_point_unit_p (gdbarch));
2077 /* AltiVec extension: Functions that declare a vector data type as a
2078 return value place that return value in VR2. */
2079 if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype)
2080 && TYPE_LENGTH (valtype) == 16)
2083 regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf);
2085 regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf);
2087 return RETURN_VALUE_REGISTER_CONVENTION;
2090 /* If the called subprogram returns an aggregate, there exists an
2091 implicit first argument, whose value is the address of a caller-
2092 allocated buffer into which the callee is assumed to store its
2093 return value. All explicit parameters are appropriately
2095 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT
2096 || TYPE_CODE (valtype) == TYPE_CODE_UNION
2097 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
2098 return RETURN_VALUE_STRUCT_CONVENTION;
2100 /* Scalar floating-point values are returned in FPR1 for float or
2101 double, and in FPR1:FPR2 for quadword precision. Fortran
2102 complex*8 and complex*16 are returned in FPR1:FPR2, and
2103 complex*32 is returned in FPR1:FPR4. */
2104 if (TYPE_CODE (valtype) == TYPE_CODE_FLT
2105 && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8))
2107 struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum);
2110 /* FIXME: kettenis/2007-01-01: Add support for quadword
2111 precision and complex. */
2115 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval);
2116 convert_typed_floating (regval, regtype, readbuf, valtype);
2120 convert_typed_floating (writebuf, valtype, regval, regtype);
2121 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval);
2124 return RETURN_VALUE_REGISTER_CONVENTION;
2127 /* Values of the types int, long, short, pointer, and char (length
2128 is less than or equal to four bytes), as well as bit values of
2129 lengths less than or equal to 32 bits, must be returned right
2130 justified in GPR3 with signed values sign extended and unsigned
2131 values zero extended, as necessary. */
2132 if (TYPE_LENGTH (valtype) <= tdep->wordsize)
2138 /* For reading we don't have to worry about sign extension. */
2139 regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
2141 store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval);
2145 /* For writing, use unpack_long since that should handle any
2146 required sign extension. */
2147 regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3,
2148 unpack_long (valtype, writebuf));
2151 return RETURN_VALUE_REGISTER_CONVENTION;
2154 /* Eight-byte non-floating-point scalar values must be returned in
2157 if (TYPE_LENGTH (valtype) == 8)
2159 gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT);
2160 gdb_assert (tdep->wordsize == 4);
2166 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval);
2167 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4,
2169 memcpy (readbuf, regval, 8);
2173 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf);
2174 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4,
2178 return RETURN_VALUE_REGISTER_CONVENTION;
2181 return RETURN_VALUE_STRUCT_CONVENTION;
2184 /* Return whether handle_inferior_event() should proceed through code
2185 starting at PC in function NAME when stepping.
2187 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2188 handle memory references that are too distant to fit in instructions
2189 generated by the compiler. For example, if 'foo' in the following
2194 is greater than 32767, the linker might replace the lwz with a branch to
2195 somewhere in @FIX1 that does the load in 2 instructions and then branches
2196 back to where execution should continue.
2198 GDB should silently step over @FIX code, just like AIX dbx does.
2199 Unfortunately, the linker uses the "b" instruction for the
2200 branches, meaning that the link register doesn't get set.
2201 Therefore, GDB's usual step_over_function () mechanism won't work.
2203 Instead, use the gdbarch_skip_trampoline_code and
2204 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2208 rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name)
2210 return name && !strncmp (name, "@FIX", 4);
2213 /* Skip code that the user doesn't want to see when stepping:
2215 1. Indirect function calls use a piece of trampoline code to do context
2216 switching, i.e. to set the new TOC table. Skip such code if we are on
2217 its first instruction (as when we have single-stepped to here).
2219 2. Skip shared library trampoline code (which is different from
2220 indirect function call trampolines).
2222 3. Skip bigtoc fixup code.
2224 Result is desired PC to step until, or NULL if we are not in
2225 code that should be skipped. */
2228 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
2230 unsigned int ii, op;
2232 CORE_ADDR solib_target_pc;
2233 struct minimal_symbol *msymbol;
2235 static unsigned trampoline_code[] =
2237 0x800b0000, /* l r0,0x0(r11) */
2238 0x90410014, /* st r2,0x14(r1) */
2239 0x7c0903a6, /* mtctr r0 */
2240 0x804b0004, /* l r2,0x4(r11) */
2241 0x816b0008, /* l r11,0x8(r11) */
2242 0x4e800420, /* bctr */
2243 0x4e800020, /* br */
2247 /* Check for bigtoc fixup code. */
2248 msymbol = lookup_minimal_symbol_by_pc (pc);
2250 && rs6000_in_solib_return_trampoline (pc,
2251 DEPRECATED_SYMBOL_NAME (msymbol)))
2253 /* Double-check that the third instruction from PC is relative "b". */
2254 op = read_memory_integer (pc + 8, 4);
2255 if ((op & 0xfc000003) == 0x48000000)
2257 /* Extract bits 6-29 as a signed 24-bit relative word address and
2258 add it to the containing PC. */
2259 rel = ((int)(op << 6) >> 6);
2260 return pc + 8 + rel;
2264 /* If pc is in a shared library trampoline, return its target. */
2265 solib_target_pc = find_solib_trampoline_target (frame, pc);
2266 if (solib_target_pc)
2267 return solib_target_pc;
2269 for (ii = 0; trampoline_code[ii]; ++ii)
2271 op = read_memory_integer (pc + (ii * 4), 4);
2272 if (op != trampoline_code[ii])
2275 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */
2276 pc = read_memory_addr (ii,
2277 gdbarch_tdep (get_frame_arch (frame))->wordsize); /* (r11) value */
2281 /* ISA-specific vector types. */
2283 static struct type *
2284 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2286 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2288 if (!tdep->ppc_builtin_type_vec64)
2290 /* The type we're building is this: */
2292 union __gdb_builtin_type_vec64
2296 int32_t v2_int32[2];
2297 int16_t v4_int16[4];
2304 t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2305 append_composite_type_field (t, "uint64", builtin_type_int64);
2306 append_composite_type_field (t, "v2_float",
2307 init_vector_type (builtin_type_float, 2));
2308 append_composite_type_field (t, "v2_int32",
2309 init_vector_type (builtin_type_int32, 2));
2310 append_composite_type_field (t, "v4_int16",
2311 init_vector_type (builtin_type_int16, 4));
2312 append_composite_type_field (t, "v8_int8",
2313 init_vector_type (builtin_type_int8, 8));
2315 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR;
2316 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2317 tdep->ppc_builtin_type_vec64 = t;
2320 return tdep->ppc_builtin_type_vec64;
2323 /* Return the size of register REG when words are WORDSIZE bytes long. If REG
2324 isn't available with that word size, return 0. */
2327 regsize (const struct reg *reg, int wordsize)
2329 return wordsize == 8 ? reg->sz64 : reg->sz32;
2332 /* Return the name of register number REGNO, or the empty string if it
2333 is an anonymous register. */
2336 rs6000_register_name (int regno)
2338 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2340 /* The upper half "registers" have names in the XML description,
2341 but we present only the low GPRs and the full 64-bit registers
2343 if (tdep->ppc_ev0_upper_regnum >= 0
2344 && tdep->ppc_ev0_upper_regnum <= regno
2345 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2348 /* Check if the SPE pseudo registers are available. */
2349 if (tdep->ppc_ev0_regnum >= 0
2350 && tdep->ppc_ev0_regnum <= regno
2351 && regno < tdep->ppc_ev0_regnum + ppc_num_gprs)
2353 static const char *const spe_regnames[] = {
2354 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2355 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2356 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2357 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2359 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2362 return tdesc_register_name (regno);
2365 /* Return the GDB type object for the "standard" data type of data in
2368 static struct type *
2369 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2371 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2373 /* These are the only pseudo-registers we support. */
2374 gdb_assert (tdep->ppc_ev0_regnum >= 0
2375 && regnum >= tdep->ppc_ev0_regnum
2376 && regnum < tdep->ppc_ev0_regnum + 32);
2378 return rs6000_builtin_type_vec64 (gdbarch);
2381 /* Is REGNUM a member of REGGROUP? */
2383 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2384 struct reggroup *group)
2386 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2388 /* These are the only pseudo-registers we support. */
2389 gdb_assert (tdep->ppc_ev0_regnum >= 0
2390 && regnum >= tdep->ppc_ev0_regnum
2391 && regnum < tdep->ppc_ev0_regnum + 32);
2393 if (group == all_reggroup || group == vector_reggroup)
2399 /* The register format for RS/6000 floating point registers is always
2400 double, we need a conversion if the memory format is float. */
2403 rs6000_convert_register_p (int regnum, struct type *type)
2405 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2407 return (tdep->ppc_fp0_regnum >= 0
2408 && regnum >= tdep->ppc_fp0_regnum
2409 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2410 && TYPE_CODE (type) == TYPE_CODE_FLT
2411 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double));
2415 rs6000_register_to_value (struct frame_info *frame,
2420 gdb_byte from[MAX_REGISTER_SIZE];
2422 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2424 get_frame_register (frame, regnum, from);
2425 convert_typed_floating (from, builtin_type_double, to, type);
2429 rs6000_value_to_register (struct frame_info *frame,
2432 const gdb_byte *from)
2434 gdb_byte to[MAX_REGISTER_SIZE];
2436 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2438 convert_typed_floating (from, type, to, builtin_type_double);
2439 put_frame_register (frame, regnum, to);
2442 /* Move SPE vector register values between a 64-bit buffer and the two
2443 32-bit raw register halves in a regcache. This function handles
2444 both splitting a 64-bit value into two 32-bit halves, and joining
2445 two halves into a whole 64-bit value, depending on the function
2446 passed as the MOVE argument.
2448 EV_REG must be the number of an SPE evN vector register --- a
2449 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2452 Call MOVE once for each 32-bit half of that register, passing
2453 REGCACHE, the number of the raw register corresponding to that
2454 half, and the address of the appropriate half of BUFFER.
2456 For example, passing 'regcache_raw_read' as the MOVE function will
2457 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2458 'regcache_raw_supply' will supply the contents of BUFFER to the
2459 appropriate pair of raw registers in REGCACHE.
2461 You may need to cast away some 'const' qualifiers when passing
2462 MOVE, since this function can't tell at compile-time which of
2463 REGCACHE or BUFFER is acting as the source of the data. If C had
2464 co-variant type qualifiers, ... */
2466 e500_move_ev_register (void (*move) (struct regcache *regcache,
2467 int regnum, gdb_byte *buf),
2468 struct regcache *regcache, int ev_reg,
2471 struct gdbarch *arch = get_regcache_arch (regcache);
2472 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2474 gdb_byte *byte_buffer = buffer;
2476 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg
2477 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs);
2479 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2481 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2483 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer);
2484 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4);
2488 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2489 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4);
2494 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2495 int reg_nr, gdb_byte *buffer)
2497 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2498 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2500 gdb_assert (regcache_arch == gdbarch);
2502 if (tdep->ppc_ev0_regnum <= reg_nr
2503 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2504 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer);
2506 internal_error (__FILE__, __LINE__,
2507 _("e500_pseudo_register_read: "
2508 "called on unexpected register '%s' (%d)"),
2509 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2513 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2514 int reg_nr, const gdb_byte *buffer)
2516 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2517 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2519 gdb_assert (regcache_arch == gdbarch);
2521 if (tdep->ppc_ev0_regnum <= reg_nr
2522 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs)
2523 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *))
2525 regcache, reg_nr, (gdb_byte *) buffer);
2527 internal_error (__FILE__, __LINE__,
2528 _("e500_pseudo_register_read: "
2529 "called on unexpected register '%s' (%d)"),
2530 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2533 /* Convert a DBX STABS register number to a GDB register number. */
2535 rs6000_stab_reg_to_regnum (int num)
2537 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2539 if (0 <= num && num <= 31)
2540 return tdep->ppc_gp0_regnum + num;
2541 else if (32 <= num && num <= 63)
2542 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2543 specifies registers the architecture doesn't have? Our
2544 callers don't check the value we return. */
2545 return tdep->ppc_fp0_regnum + (num - 32);
2546 else if (77 <= num && num <= 108)
2547 return tdep->ppc_vr0_regnum + (num - 77);
2548 else if (1200 <= num && num < 1200 + 32)
2549 return tdep->ppc_ev0_regnum + (num - 1200);
2554 return tdep->ppc_mq_regnum;
2556 return tdep->ppc_lr_regnum;
2558 return tdep->ppc_ctr_regnum;
2560 return tdep->ppc_xer_regnum;
2562 return tdep->ppc_vrsave_regnum;
2564 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2566 return tdep->ppc_acc_regnum;
2568 return tdep->ppc_spefscr_regnum;
2575 /* Convert a Dwarf 2 register number to a GDB register number. */
2577 rs6000_dwarf2_reg_to_regnum (int num)
2579 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch);
2581 if (0 <= num && num <= 31)
2582 return tdep->ppc_gp0_regnum + num;
2583 else if (32 <= num && num <= 63)
2584 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2585 specifies registers the architecture doesn't have? Our
2586 callers don't check the value we return. */
2587 return tdep->ppc_fp0_regnum + (num - 32);
2588 else if (1124 <= num && num < 1124 + 32)
2589 return tdep->ppc_vr0_regnum + (num - 1124);
2590 else if (1200 <= num && num < 1200 + 32)
2591 return tdep->ppc_ev0_regnum + (num - 1200);
2596 return tdep->ppc_cr_regnum;
2598 return tdep->ppc_vrsave_regnum - 1; /* vscr */
2600 return tdep->ppc_acc_regnum;
2602 return tdep->ppc_mq_regnum;
2604 return tdep->ppc_xer_regnum;
2606 return tdep->ppc_lr_regnum;
2608 return tdep->ppc_ctr_regnum;
2610 return tdep->ppc_vrsave_regnum;
2612 return tdep->ppc_spefscr_regnum;
2618 /* Translate a .eh_frame register to DWARF register, or adjust a
2619 .debug_frame register. */
2622 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
2624 /* GCC releases before 3.4 use GCC internal register numbering in
2625 .debug_frame (and .debug_info, et cetera). The numbering is
2626 different from the standard SysV numbering for everything except
2627 for GPRs and FPRs. We can not detect this problem in most cases
2628 - to get accurate debug info for variables living in lr, ctr, v0,
2629 et cetera, use a newer version of GCC. But we must detect
2630 one important case - lr is in column 65 in .debug_frame output,
2633 GCC 3.4, and the "hammer" branch, have a related problem. They
2634 record lr register saves in .debug_frame as 108, but still record
2635 the return column as 65. We fix that up too.
2637 We can do this because 65 is assigned to fpsr, and GCC never
2638 generates debug info referring to it. To add support for
2639 handwritten debug info that restores fpsr, we would need to add a
2640 producer version check to this. */
2649 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
2650 internal register numbering; translate that to the standard DWARF2
2651 register numbering. */
2652 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
2654 else if (68 <= num && num <= 75) /* cr0-cr8 */
2655 return num - 68 + 86;
2656 else if (77 <= num && num <= 108) /* vr0-vr31 */
2657 return num - 77 + 1124;
2669 case 109: /* vrsave */
2671 case 110: /* vscr */
2673 case 111: /* spe_acc */
2675 case 112: /* spefscr */
2682 /* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG).
2684 Usually a function pointer's representation is simply the address
2685 of the function. On the RS/6000 however, a function pointer is
2686 represented by a pointer to an OPD entry. This OPD entry contains
2687 three words, the first word is the address of the function, the
2688 second word is the TOC pointer (r2), and the third word is the
2689 static chain value. Throughout GDB it is currently assumed that a
2690 function pointer contains the address of the function, which is not
2691 easy to fix. In addition, the conversion of a function address to
2692 a function pointer would require allocation of an OPD entry in the
2693 inferior's memory space, with all its drawbacks. To be able to
2694 call C++ virtual methods in the inferior (which are called via
2695 function pointers), find_function_addr uses this function to get the
2696 function address from a function pointer. */
2698 /* Return real function address if ADDR (a function pointer) is in the data
2699 space and is therefore a special function pointer. */
2702 rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch,
2704 struct target_ops *targ)
2706 struct obj_section *s;
2708 s = find_pc_section (addr);
2709 if (s && s->the_bfd_section->flags & SEC_CODE)
2712 /* ADDR is in the data space, so it's a special function pointer. */
2713 return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize);
2717 /* Handling the various POWER/PowerPC variants. */
2719 /* Information about a particular processor variant. */
2723 /* Name of this variant. */
2726 /* English description of the variant. */
2729 /* bfd_arch_info.arch corresponding to variant. */
2730 enum bfd_architecture arch;
2732 /* bfd_arch_info.mach corresponding to variant. */
2735 /* Target description for this variant. */
2736 struct target_desc **tdesc;
2739 static struct variant variants[] =
2741 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
2742 bfd_mach_ppc, &tdesc_powerpc_32},
2743 {"power", "POWER user-level", bfd_arch_rs6000,
2744 bfd_mach_rs6k, &tdesc_rs6000},
2745 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
2746 bfd_mach_ppc_403, &tdesc_powerpc_403},
2747 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
2748 bfd_mach_ppc_601, &tdesc_powerpc_601},
2749 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
2750 bfd_mach_ppc_602, &tdesc_powerpc_602},
2751 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
2752 bfd_mach_ppc_603, &tdesc_powerpc_603},
2753 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
2754 604, &tdesc_powerpc_604},
2755 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
2756 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
2757 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
2758 bfd_mach_ppc_505, &tdesc_powerpc_505},
2759 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
2760 bfd_mach_ppc_860, &tdesc_powerpc_860},
2761 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
2762 bfd_mach_ppc_750, &tdesc_powerpc_750},
2763 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
2764 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
2765 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
2766 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
2769 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
2770 bfd_mach_ppc64, &tdesc_powerpc_64},
2771 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
2772 bfd_mach_ppc_620, &tdesc_powerpc_64},
2773 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
2774 bfd_mach_ppc_630, &tdesc_powerpc_64},
2775 {"a35", "PowerPC A35", bfd_arch_powerpc,
2776 bfd_mach_ppc_a35, &tdesc_powerpc_64},
2777 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
2778 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
2779 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
2780 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
2782 /* FIXME: I haven't checked the register sets of the following. */
2783 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
2784 bfd_mach_rs6k_rs1, &tdesc_rs6000},
2785 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
2786 bfd_mach_rs6k_rsc, &tdesc_rs6000},
2787 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
2788 bfd_mach_rs6k_rs2, &tdesc_rs6000},
2793 /* Return the variant corresponding to architecture ARCH and machine number
2794 MACH. If no such variant exists, return null. */
2796 static const struct variant *
2797 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
2799 const struct variant *v;
2801 for (v = variants; v->name; v++)
2802 if (arch == v->arch && mach == v->mach)
2809 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
2811 if (!info->disassembler_options)
2812 info->disassembler_options = "any";
2814 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG)
2815 return print_insn_big_powerpc (memaddr, info);
2817 return print_insn_little_powerpc (memaddr, info);
2821 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2823 return frame_unwind_register_unsigned (next_frame,
2824 gdbarch_pc_regnum (gdbarch));
2827 static struct frame_id
2828 rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame)
2830 return frame_id_build (frame_unwind_register_unsigned
2831 (next_frame, gdbarch_sp_regnum (gdbarch)),
2832 frame_pc_unwind (next_frame));
2835 struct rs6000_frame_cache
2838 CORE_ADDR initial_sp;
2839 struct trad_frame_saved_reg *saved_regs;
2842 static struct rs6000_frame_cache *
2843 rs6000_frame_cache (struct frame_info *next_frame, void **this_cache)
2845 struct rs6000_frame_cache *cache;
2846 struct gdbarch *gdbarch = get_frame_arch (next_frame);
2847 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2848 struct rs6000_framedata fdata;
2849 int wordsize = tdep->wordsize;
2852 if ((*this_cache) != NULL)
2853 return (*this_cache);
2854 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
2855 (*this_cache) = cache;
2856 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame);
2858 func = frame_func_unwind (next_frame, NORMAL_FRAME);
2859 pc = frame_pc_unwind (next_frame);
2860 skip_prologue (func, pc, &fdata);
2862 /* Figure out the parent's stack pointer. */
2864 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
2865 address of the current frame. Things might be easier if the
2866 ->frame pointed to the outer-most address of the frame. In
2867 the mean time, the address of the prev frame is used as the
2868 base address of this frame. */
2869 cache->base = frame_unwind_register_unsigned
2870 (next_frame, gdbarch_sp_regnum (gdbarch));
2872 /* If the function appears to be frameless, check a couple of likely
2873 indicators that we have simply failed to find the frame setup.
2874 Two common cases of this are missing symbols (i.e.
2875 frame_func_unwind returns the wrong address or 0), and assembly
2876 stubs which have a fast exit path but set up a frame on the slow
2879 If the LR appears to return to this function, then presume that
2880 we have an ABI compliant frame that we failed to find. */
2881 if (fdata.frameless && fdata.lr_offset == 0)
2886 saved_lr = frame_unwind_register_unsigned (next_frame,
2887 tdep->ppc_lr_regnum);
2888 if (func == 0 && saved_lr == pc)
2892 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
2893 if (func == saved_func)
2899 fdata.frameless = 0;
2900 fdata.lr_offset = tdep->lr_frame_offset;
2904 if (!fdata.frameless)
2905 /* Frameless really means stackless. */
2906 cache->base = read_memory_addr (cache->base, wordsize);
2908 trad_frame_set_value (cache->saved_regs,
2909 gdbarch_sp_regnum (gdbarch), cache->base);
2911 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
2912 All fpr's from saved_fpr to fp31 are saved. */
2914 if (fdata.saved_fpr >= 0)
2917 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
2919 /* If skip_prologue says floating-point registers were saved,
2920 but the current architecture has no floating-point registers,
2921 then that's strange. But we have no indices to even record
2922 the addresses under, so we just ignore it. */
2923 if (ppc_floating_point_unit_p (gdbarch))
2924 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
2926 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
2931 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
2932 All gpr's from saved_gpr to gpr31 are saved. */
2934 if (fdata.saved_gpr >= 0)
2937 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
2938 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
2940 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
2941 gpr_addr += wordsize;
2945 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
2946 All vr's from saved_vr to vr31 are saved. */
2947 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
2949 if (fdata.saved_vr >= 0)
2952 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
2953 for (i = fdata.saved_vr; i < 32; i++)
2955 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
2956 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
2961 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
2962 All vr's from saved_ev to ev31 are saved. ????? */
2963 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1)
2965 if (fdata.saved_ev >= 0)
2968 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
2969 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
2971 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
2972 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4;
2973 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
2978 /* If != 0, fdata.cr_offset is the offset from the frame that
2980 if (fdata.cr_offset != 0)
2981 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset;
2983 /* If != 0, fdata.lr_offset is the offset from the frame that
2985 if (fdata.lr_offset != 0)
2986 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset;
2987 /* The PC is found in the link register. */
2988 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
2989 cache->saved_regs[tdep->ppc_lr_regnum];
2991 /* If != 0, fdata.vrsave_offset is the offset from the frame that
2992 holds the VRSAVE. */
2993 if (fdata.vrsave_offset != 0)
2994 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset;
2996 if (fdata.alloca_reg < 0)
2997 /* If no alloca register used, then fi->frame is the value of the
2998 %sp for this frame, and it is good enough. */
2999 cache->initial_sp = frame_unwind_register_unsigned
3000 (next_frame, gdbarch_sp_regnum (gdbarch));
3002 cache->initial_sp = frame_unwind_register_unsigned (next_frame,
3009 rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache,
3010 struct frame_id *this_id)
3012 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3014 (*this_id) = frame_id_build (info->base,
3015 frame_func_unwind (next_frame, NORMAL_FRAME));
3019 rs6000_frame_prev_register (struct frame_info *next_frame,
3021 int regnum, int *optimizedp,
3022 enum lval_type *lvalp, CORE_ADDR *addrp,
3023 int *realnump, gdb_byte *valuep)
3025 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3027 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum,
3028 optimizedp, lvalp, addrp, realnump, valuep);
3031 static const struct frame_unwind rs6000_frame_unwind =
3034 rs6000_frame_this_id,
3035 rs6000_frame_prev_register
3038 static const struct frame_unwind *
3039 rs6000_frame_sniffer (struct frame_info *next_frame)
3041 return &rs6000_frame_unwind;
3047 rs6000_frame_base_address (struct frame_info *next_frame,
3050 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame,
3052 return info->initial_sp;
3055 static const struct frame_base rs6000_frame_base = {
3056 &rs6000_frame_unwind,
3057 rs6000_frame_base_address,
3058 rs6000_frame_base_address,
3059 rs6000_frame_base_address
3062 static const struct frame_base *
3063 rs6000_frame_base_sniffer (struct frame_info *next_frame)
3065 return &rs6000_frame_base;
3068 /* DWARF-2 frame support. Used to handle the detection of
3069 clobbered registers during function calls. */
3072 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3073 struct dwarf2_frame_state_reg *reg,
3074 struct frame_info *next_frame)
3076 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3078 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3079 non-volatile registers. We will use the same code for both. */
3081 /* Call-saved GP registers. */
3082 if ((regnum >= tdep->ppc_gp0_regnum + 14
3083 && regnum <= tdep->ppc_gp0_regnum + 31)
3084 || (regnum == tdep->ppc_gp0_regnum + 1))
3085 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3087 /* Call-clobbered GP registers. */
3088 if ((regnum >= tdep->ppc_gp0_regnum + 3
3089 && regnum <= tdep->ppc_gp0_regnum + 12)
3090 || (regnum == tdep->ppc_gp0_regnum))
3091 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3093 /* Deal with FP registers, if supported. */
3094 if (tdep->ppc_fp0_regnum >= 0)
3096 /* Call-saved FP registers. */
3097 if ((regnum >= tdep->ppc_fp0_regnum + 14
3098 && regnum <= tdep->ppc_fp0_regnum + 31))
3099 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3101 /* Call-clobbered FP registers. */
3102 if ((regnum >= tdep->ppc_fp0_regnum
3103 && regnum <= tdep->ppc_fp0_regnum + 13))
3104 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3107 /* Deal with ALTIVEC registers, if supported. */
3108 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3110 /* Call-saved Altivec registers. */
3111 if ((regnum >= tdep->ppc_vr0_regnum + 20
3112 && regnum <= tdep->ppc_vr0_regnum + 31)
3113 || regnum == tdep->ppc_vrsave_regnum)
3114 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3116 /* Call-clobbered Altivec registers. */
3117 if ((regnum >= tdep->ppc_vr0_regnum
3118 && regnum <= tdep->ppc_vr0_regnum + 19))
3119 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3122 /* Handle PC register and Stack Pointer correctly. */
3123 if (regnum == gdbarch_pc_regnum (current_gdbarch))
3124 reg->how = DWARF2_FRAME_REG_RA;
3125 else if (regnum == gdbarch_sp_regnum (current_gdbarch))
3126 reg->how = DWARF2_FRAME_REG_CFA;
3130 /* Initialize the current architecture based on INFO. If possible, re-use an
3131 architecture from ARCHES, which is a list of architectures already created
3132 during this debugging session.
3134 Called e.g. at program startup, when reading a core file, and when reading
3137 static struct gdbarch *
3138 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3140 struct gdbarch *gdbarch;
3141 struct gdbarch_tdep *tdep;
3142 int wordsize, from_xcoff_exec, from_elf_exec;
3143 enum bfd_architecture arch;
3148 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0;
3149 int tdesc_wordsize = -1;
3150 const struct target_desc *tdesc = info.target_desc;
3151 struct tdesc_arch_data *tdesc_data = NULL;
3154 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
3155 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
3157 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
3158 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3160 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
3162 /* Check word size. If INFO is from a binary file, infer it from
3163 that, else choose a likely default. */
3164 if (from_xcoff_exec)
3166 if (bfd_xcoff_is_xcoff64 (info.abfd))
3171 else if (from_elf_exec)
3173 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
3178 else if (tdesc_has_registers (tdesc))
3182 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
3183 wordsize = info.bfd_arch_info->bits_per_word /
3184 info.bfd_arch_info->bits_per_byte;
3189 if (!from_xcoff_exec)
3191 arch = info.bfd_arch_info->arch;
3192 mach = info.bfd_arch_info->mach;
3196 arch = bfd_arch_powerpc;
3197 bfd_default_set_arch_mach (&abfd, arch, 0);
3198 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3199 mach = info.bfd_arch_info->mach;
3202 /* For e500 executables, the apuinfo section is of help here. Such
3203 section contains the identifier and revision number of each
3204 Application-specific Processing Unit that is present on the
3205 chip. The content of the section is determined by the assembler
3206 which looks at each instruction and determines which unit (and
3207 which version of it) can execute it. In our case we just look for
3208 the existance of the section. */
3212 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo");
3215 arch = info.bfd_arch_info->arch;
3216 mach = bfd_mach_ppc_e500;
3217 bfd_default_set_arch_mach (&abfd, arch, mach);
3218 info.bfd_arch_info = bfd_get_arch_info (&abfd);
3222 /* Find a default target description which describes our register
3223 layout, if we do not already have one. */
3224 if (! tdesc_has_registers (tdesc))
3226 const struct variant *v;
3228 /* Choose variant. */
3229 v = find_variant_by_arch (arch, mach);
3236 gdb_assert (tdesc_has_registers (tdesc));
3238 /* Check any target description for validity. */
3239 if (tdesc_has_registers (tdesc))
3241 static const char *const gprs[] = {
3242 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
3243 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
3244 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
3245 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
3247 static const char *const segment_regs[] = {
3248 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
3249 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
3251 const struct tdesc_feature *feature;
3253 static const char *const msr_names[] = { "msr", "ps" };
3254 static const char *const cr_names[] = { "cr", "cnd" };
3255 static const char *const ctr_names[] = { "ctr", "cnt" };
3257 feature = tdesc_find_feature (tdesc,
3258 "org.gnu.gdb.power.core");
3259 if (feature == NULL)
3262 tdesc_data = tdesc_data_alloc ();
3265 for (i = 0; i < ppc_num_gprs; i++)
3266 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
3267 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
3269 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
3271 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
3274 /* Allow alternate names for these registers, to accomodate GDB's
3276 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3277 PPC_MSR_REGNUM, msr_names);
3278 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3279 PPC_CR_REGNUM, cr_names);
3280 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
3281 PPC_CTR_REGNUM, ctr_names);
3285 tdesc_data_cleanup (tdesc_data);
3289 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
3292 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
3294 wordsize = tdesc_wordsize;
3296 feature = tdesc_find_feature (tdesc,
3297 "org.gnu.gdb.power.fpu");
3298 if (feature != NULL)
3300 static const char *const fprs[] = {
3301 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
3302 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
3303 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
3304 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
3307 for (i = 0; i < ppc_num_fprs; i++)
3308 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3309 PPC_F0_REGNUM + i, fprs[i]);
3310 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3311 PPC_FPSCR_REGNUM, "fpscr");
3315 tdesc_data_cleanup (tdesc_data);
3323 feature = tdesc_find_feature (tdesc,
3324 "org.gnu.gdb.power.altivec");
3325 if (feature != NULL)
3327 static const char *const vector_regs[] = {
3328 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
3329 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
3330 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
3331 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
3335 for (i = 0; i < ppc_num_gprs; i++)
3336 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3339 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3340 PPC_VSCR_REGNUM, "vscr");
3341 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3342 PPC_VRSAVE_REGNUM, "vrsave");
3344 if (have_spe || !valid_p)
3346 tdesc_data_cleanup (tdesc_data);
3354 /* On machines supporting the SPE APU, the general-purpose registers
3355 are 64 bits long. There are SIMD vector instructions to treat them
3356 as pairs of floats, but the rest of the instruction set treats them
3357 as 32-bit registers, and only operates on their lower halves.
3359 In the GDB regcache, we treat their high and low halves as separate
3360 registers. The low halves we present as the general-purpose
3361 registers, and then we have pseudo-registers that stitch together
3362 the upper and lower halves and present them as pseudo-registers.
3364 Thus, the target description is expected to supply the upper
3365 halves separately. */
3367 feature = tdesc_find_feature (tdesc,
3368 "org.gnu.gdb.power.spe");
3369 if (feature != NULL)
3371 static const char *const upper_spe[] = {
3372 "ev0h", "ev1h", "ev2h", "ev3h",
3373 "ev4h", "ev5h", "ev6h", "ev7h",
3374 "ev8h", "ev9h", "ev10h", "ev11h",
3375 "ev12h", "ev13h", "ev14h", "ev15h",
3376 "ev16h", "ev17h", "ev18h", "ev19h",
3377 "ev20h", "ev21h", "ev22h", "ev23h",
3378 "ev24h", "ev25h", "ev26h", "ev27h",
3379 "ev28h", "ev29h", "ev30h", "ev31h"
3383 for (i = 0; i < ppc_num_gprs; i++)
3384 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3385 PPC_SPE_UPPER_GP0_REGNUM + i,
3387 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3388 PPC_SPE_ACC_REGNUM, "acc");
3389 valid_p &= tdesc_numbered_register (feature, tdesc_data,
3390 PPC_SPE_FSCR_REGNUM, "spefscr");
3392 if (have_mq || have_fpu || !valid_p)
3394 tdesc_data_cleanup (tdesc_data);
3403 /* If we have a 64-bit binary on a 32-bit target, complain. Also
3404 complain for a 32-bit binary on a 64-bit target; we do not yet
3405 support that. For instance, the 32-bit ABI routines expect
3408 As long as there isn't an explicit target description, we'll
3409 choose one based on the BFD architecture and get a word size
3410 matching the binary (probably powerpc:common or
3411 powerpc:common64). So there is only trouble if a 64-bit target
3412 supplies a 64-bit description while debugging a 32-bit
3414 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
3416 tdesc_data_cleanup (tdesc_data);
3420 /* Find a candidate among extant architectures. */
3421 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3423 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3425 /* Word size in the various PowerPC bfd_arch_info structs isn't
3426 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
3427 separate word size check. */
3428 tdep = gdbarch_tdep (arches->gdbarch);
3429 if (tdep && tdep->wordsize == wordsize)
3431 if (tdesc_data != NULL)
3432 tdesc_data_cleanup (tdesc_data);
3433 return arches->gdbarch;
3437 /* None found, create a new architecture from INFO, whose bfd_arch_info
3438 validity depends on the source:
3439 - executable useless
3440 - rs6000_host_arch() good
3442 - "set arch" trust blindly
3443 - GDB startup useless but harmless */
3445 tdep = XCALLOC (1, struct gdbarch_tdep);
3446 tdep->wordsize = wordsize;
3448 gdbarch = gdbarch_alloc (&info, tdep);
3450 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
3451 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
3452 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
3453 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
3454 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
3455 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
3456 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
3457 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
3459 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
3460 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
3461 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
3462 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
3463 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
3464 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
3465 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
3467 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
3468 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3469 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
3470 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
3471 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
3473 /* The XML specification for PowerPC sensibly calls the MSR "msr".
3474 GDB traditionally called it "ps", though, so let GDB add an
3476 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
3478 if (sysv_abi && wordsize == 8)
3479 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
3480 else if (sysv_abi && wordsize == 4)
3481 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
3483 set_gdbarch_return_value (gdbarch, rs6000_return_value);
3485 /* Set lr_frame_offset. */
3487 tdep->lr_frame_offset = 16;
3489 tdep->lr_frame_offset = 4;
3491 tdep->lr_frame_offset = 8;
3495 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read);
3496 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write);
3499 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3501 /* Select instruction printer. */
3502 if (arch == bfd_arch_rs6000)
3503 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
3505 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
3507 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS + num_sprs);
3508 set_gdbarch_num_pseudo_regs (gdbarch, have_spe ? 32 : 0);
3510 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3511 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3512 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3513 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
3514 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3515 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
3516 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3518 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
3520 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
3521 set_gdbarch_char_signed (gdbarch, 0);
3523 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
3524 if (sysv_abi && wordsize == 8)
3526 set_gdbarch_frame_red_zone_size (gdbarch, 288);
3527 else if (!sysv_abi && wordsize == 4)
3528 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of
3529 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes.
3530 Problem is, 220 isn't frame (16 byte) aligned. Round it up to
3532 set_gdbarch_frame_red_zone_size (gdbarch, 224);
3534 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
3535 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
3536 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
3538 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
3539 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
3541 if (sysv_abi && wordsize == 4)
3542 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
3543 else if (sysv_abi && wordsize == 8)
3544 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
3546 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call);
3548 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
3549 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p);
3551 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3552 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
3554 /* The value of symbols of type N_SO and N_FUN maybe null when
3556 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
3558 /* Handles single stepping of atomic sequences. */
3559 set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence);
3561 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN"
3562 for the descriptor and ".FN" for the entry-point -- a user
3563 specifying "break FN" will unexpectedly end up with a breakpoint
3564 on the descriptor and not the function. This architecture method
3565 transforms any breakpoints on descriptors into breakpoints on the
3566 corresponding entry point. */
3567 if (sysv_abi && wordsize == 8)
3568 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address);
3570 /* Not sure on this. FIXMEmgo */
3571 set_gdbarch_frame_args_skip (gdbarch, 8);
3575 /* Handle RS/6000 function pointers (which are really function
3577 set_gdbarch_convert_from_func_ptr_addr (gdbarch,
3578 rs6000_convert_from_func_ptr_addr);
3581 /* Helpers for function argument information. */
3582 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
3585 set_gdbarch_in_solib_return_trampoline
3586 (gdbarch, rs6000_in_solib_return_trampoline);
3587 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
3589 /* Hook in the DWARF CFI frame unwinder. */
3590 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer);
3591 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
3593 /* Frame handling. */
3594 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
3596 /* Hook in ABI-specific overrides, if they have been registered. */
3597 gdbarch_init_osabi (info, gdbarch);
3601 case GDB_OSABI_LINUX:
3602 case GDB_OSABI_NETBSD_AOUT:
3603 case GDB_OSABI_NETBSD_ELF:
3604 case GDB_OSABI_UNKNOWN:
3605 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3606 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3607 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3608 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3611 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3613 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
3614 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer);
3615 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id);
3616 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
3619 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
3620 set_tdesc_pseudo_register_reggroup_p (gdbarch,
3621 rs6000_pseudo_register_reggroup_p);
3622 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3624 /* Override the normal target description method to make the SPE upper
3625 halves anonymous. */
3626 set_gdbarch_register_name (gdbarch, rs6000_register_name);
3628 /* Recording the numbering of pseudo registers. */
3629 tdep->ppc_ev0_regnum = have_spe ? gdbarch_num_regs (gdbarch) : -1;
3630 tdep->ppc_ev31_regnum = have_spe ? tdep->ppc_ev0_regnum + 31 : -1;
3636 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3638 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3643 /* FIXME: Dump gdbarch_tdep. */
3646 /* Initialization code. */
3648 extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */
3651 _initialize_rs6000_tdep (void)
3653 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
3654 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
3656 /* Initialize the standard target descriptions. */
3657 initialize_tdesc_powerpc_32 ();
3658 initialize_tdesc_powerpc_403 ();
3659 initialize_tdesc_powerpc_403gc ();
3660 initialize_tdesc_powerpc_505 ();
3661 initialize_tdesc_powerpc_601 ();
3662 initialize_tdesc_powerpc_602 ();
3663 initialize_tdesc_powerpc_603 ();
3664 initialize_tdesc_powerpc_604 ();
3665 initialize_tdesc_powerpc_64 ();
3666 initialize_tdesc_powerpc_7400 ();
3667 initialize_tdesc_powerpc_750 ();
3668 initialize_tdesc_powerpc_860 ();
3669 initialize_tdesc_powerpc_e500 ();
3670 initialize_tdesc_rs6000 ();