1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
32 #include "target-float.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "coff/internal.h" /* for libcoff.h */
47 #include "libcoff.h" /* for xcoff_data */
48 #include "coff/xcoff.h"
53 #include "elf/ppc64.h"
55 #include "solib-svr4.h"
57 #include "ppc-ravenscar-thread.h"
61 #include "trad-frame.h"
62 #include "frame-unwind.h"
63 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* Holds the current set of options to be passed to the disassembler. */
110 static char *powerpc_disassembler_options;
112 /* The list of available "set powerpc ..." and "show powerpc ..."
114 static struct cmd_list_element *setpowerpccmdlist = NULL;
115 static struct cmd_list_element *showpowerpccmdlist = NULL;
117 static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
119 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
120 static const char *const powerpc_vector_strings[] =
129 /* A variable that can be configured by the user. */
130 static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
131 static const char *powerpc_vector_abi_string = "auto";
133 /* To be used by skip_prologue. */
135 struct rs6000_framedata
137 int offset; /* total size of frame --- the distance
138 by which we decrement sp to allocate
140 int saved_gpr; /* smallest # of saved gpr */
141 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
142 int saved_fpr; /* smallest # of saved fpr */
143 int saved_vr; /* smallest # of saved vr */
144 int saved_ev; /* smallest # of saved ev */
145 int alloca_reg; /* alloca register number (frame ptr) */
146 char frameless; /* true if frameless functions. */
147 char nosavedpc; /* true if pc not saved. */
148 char used_bl; /* true if link register clobbered */
149 int gpr_offset; /* offset of saved gprs from prev sp */
150 int fpr_offset; /* offset of saved fprs from prev sp */
151 int vr_offset; /* offset of saved vrs from prev sp */
152 int ev_offset; /* offset of saved evs from prev sp */
153 int lr_offset; /* offset of saved lr */
154 int lr_register; /* register of saved lr, if trustworthy */
155 int cr_offset; /* offset of saved cr */
156 int vrsave_offset; /* offset of saved vrsave register */
160 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
162 vsx_register_p (struct gdbarch *gdbarch, int regno)
164 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
165 if (tdep->ppc_vsr0_regnum < 0)
168 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
169 <= tdep->ppc_vsr0_upper_regnum + 31);
172 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
174 altivec_register_p (struct gdbarch *gdbarch, int regno)
176 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
177 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
180 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
184 /* Return true if REGNO is an SPE register, false otherwise. */
186 spe_register_p (struct gdbarch *gdbarch, int regno)
188 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
190 /* Is it a reference to EV0 -- EV31, and do we have those? */
191 if (IS_SPE_PSEUDOREG (tdep, regno))
194 /* Is it a reference to one of the raw upper GPR halves? */
195 if (tdep->ppc_ev0_upper_regnum >= 0
196 && tdep->ppc_ev0_upper_regnum <= regno
197 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
200 /* Is it a reference to the 64-bit accumulator, and do we have that? */
201 if (tdep->ppc_acc_regnum >= 0
202 && tdep->ppc_acc_regnum == regno)
205 /* Is it a reference to the SPE floating-point status and control register,
206 and do we have that? */
207 if (tdep->ppc_spefscr_regnum >= 0
208 && tdep->ppc_spefscr_regnum == regno)
215 /* Return non-zero if the architecture described by GDBARCH has
216 floating-point registers (f0 --- f31 and fpscr). */
218 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
220 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
222 return (tdep->ppc_fp0_regnum >= 0
223 && tdep->ppc_fpscr_regnum >= 0);
226 /* Return non-zero if the architecture described by GDBARCH has
227 VSX registers (vsr0 --- vsr63). */
229 ppc_vsx_support_p (struct gdbarch *gdbarch)
231 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
233 return tdep->ppc_vsr0_regnum >= 0;
236 /* Return non-zero if the architecture described by GDBARCH has
237 Altivec registers (vr0 --- vr31, vrsave and vscr). */
239 ppc_altivec_support_p (struct gdbarch *gdbarch)
241 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
243 return (tdep->ppc_vr0_regnum >= 0
244 && tdep->ppc_vrsave_regnum >= 0);
247 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
250 This is a helper function for init_sim_regno_table, constructing
251 the table mapping GDB register numbers to sim register numbers; we
252 initialize every element in that table to -1 before we start
255 set_sim_regno (int *table, int gdb_regno, int sim_regno)
257 /* Make sure we don't try to assign any given GDB register a sim
258 register number more than once. */
259 gdb_assert (table[gdb_regno] == -1);
260 table[gdb_regno] = sim_regno;
264 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
265 numbers to simulator register numbers, based on the values placed
266 in the ARCH->tdep->ppc_foo_regnum members. */
268 init_sim_regno_table (struct gdbarch *arch)
270 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
271 int total_regs = gdbarch_num_regs (arch);
272 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
274 static const char *const segment_regs[] = {
275 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
276 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
279 /* Presume that all registers not explicitly mentioned below are
280 unavailable from the sim. */
281 for (i = 0; i < total_regs; i++)
284 /* General-purpose registers. */
285 for (i = 0; i < ppc_num_gprs; i++)
286 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
288 /* Floating-point registers. */
289 if (tdep->ppc_fp0_regnum >= 0)
290 for (i = 0; i < ppc_num_fprs; i++)
291 set_sim_regno (sim_regno,
292 tdep->ppc_fp0_regnum + i,
293 sim_ppc_f0_regnum + i);
294 if (tdep->ppc_fpscr_regnum >= 0)
295 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
297 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
298 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
299 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
301 /* Segment registers. */
302 for (i = 0; i < ppc_num_srs; i++)
306 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
308 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
311 /* Altivec registers. */
312 if (tdep->ppc_vr0_regnum >= 0)
314 for (i = 0; i < ppc_num_vrs; i++)
315 set_sim_regno (sim_regno,
316 tdep->ppc_vr0_regnum + i,
317 sim_ppc_vr0_regnum + i);
319 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
320 we can treat this more like the other cases. */
321 set_sim_regno (sim_regno,
322 tdep->ppc_vr0_regnum + ppc_num_vrs,
323 sim_ppc_vscr_regnum);
325 /* vsave is a special-purpose register, so the code below handles it. */
327 /* SPE APU (E500) registers. */
328 if (tdep->ppc_ev0_upper_regnum >= 0)
329 for (i = 0; i < ppc_num_gprs; i++)
330 set_sim_regno (sim_regno,
331 tdep->ppc_ev0_upper_regnum + i,
332 sim_ppc_rh0_regnum + i);
333 if (tdep->ppc_acc_regnum >= 0)
334 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
335 /* spefscr is a special-purpose register, so the code below handles it. */
338 /* Now handle all special-purpose registers. Verify that they
339 haven't mistakenly been assigned numbers by any of the above
341 for (i = 0; i < sim_ppc_num_sprs; i++)
343 const char *spr_name = sim_spr_register_name (i);
346 if (spr_name != NULL)
347 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
350 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
354 /* Drop the initialized array into place. */
355 tdep->sim_regno = sim_regno;
359 /* Given a GDB register number REG, return the corresponding SIM
362 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
364 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
367 if (tdep->sim_regno == NULL)
368 init_sim_regno_table (gdbarch);
371 && reg <= gdbarch_num_regs (gdbarch)
372 + gdbarch_num_pseudo_regs (gdbarch));
373 sim_regno = tdep->sim_regno[reg];
378 return LEGACY_SIM_REGNO_IGNORE;
383 /* Register set support functions. */
385 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
386 Write the register to REGCACHE. */
389 ppc_supply_reg (struct regcache *regcache, int regnum,
390 const gdb_byte *regs, size_t offset, int regsize)
392 if (regnum != -1 && offset != -1)
396 struct gdbarch *gdbarch = regcache->arch ();
397 int gdb_regsize = register_size (gdbarch, regnum);
398 if (gdb_regsize < regsize
399 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
400 offset += regsize - gdb_regsize;
402 regcache_raw_supply (regcache, regnum, regs + offset);
406 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
407 in a field REGSIZE wide. Zero pad as necessary. */
410 ppc_collect_reg (const struct regcache *regcache, int regnum,
411 gdb_byte *regs, size_t offset, int regsize)
413 if (regnum != -1 && offset != -1)
417 struct gdbarch *gdbarch = regcache->arch ();
418 int gdb_regsize = register_size (gdbarch, regnum);
419 if (gdb_regsize < regsize)
421 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
423 memset (regs + offset, 0, regsize - gdb_regsize);
424 offset += regsize - gdb_regsize;
427 memset (regs + offset + regsize - gdb_regsize, 0,
428 regsize - gdb_regsize);
431 regcache_raw_collect (regcache, regnum, regs + offset);
436 ppc_greg_offset (struct gdbarch *gdbarch,
437 struct gdbarch_tdep *tdep,
438 const struct ppc_reg_offsets *offsets,
442 *regsize = offsets->gpr_size;
443 if (regnum >= tdep->ppc_gp0_regnum
444 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
445 return (offsets->r0_offset
446 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
448 if (regnum == gdbarch_pc_regnum (gdbarch))
449 return offsets->pc_offset;
451 if (regnum == tdep->ppc_ps_regnum)
452 return offsets->ps_offset;
454 if (regnum == tdep->ppc_lr_regnum)
455 return offsets->lr_offset;
457 if (regnum == tdep->ppc_ctr_regnum)
458 return offsets->ctr_offset;
460 *regsize = offsets->xr_size;
461 if (regnum == tdep->ppc_cr_regnum)
462 return offsets->cr_offset;
464 if (regnum == tdep->ppc_xer_regnum)
465 return offsets->xer_offset;
467 if (regnum == tdep->ppc_mq_regnum)
468 return offsets->mq_offset;
474 ppc_fpreg_offset (struct gdbarch_tdep *tdep,
475 const struct ppc_reg_offsets *offsets,
478 if (regnum >= tdep->ppc_fp0_regnum
479 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
480 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
482 if (regnum == tdep->ppc_fpscr_regnum)
483 return offsets->fpscr_offset;
489 ppc_vrreg_offset (struct gdbarch_tdep *tdep,
490 const struct ppc_reg_offsets *offsets,
493 if (regnum >= tdep->ppc_vr0_regnum
494 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
495 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
497 if (regnum == tdep->ppc_vrsave_regnum - 1)
498 return offsets->vscr_offset;
500 if (regnum == tdep->ppc_vrsave_regnum)
501 return offsets->vrsave_offset;
506 /* Supply register REGNUM in the general-purpose register set REGSET
507 from the buffer specified by GREGS and LEN to register cache
508 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
511 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
512 int regnum, const void *gregs, size_t len)
514 struct gdbarch *gdbarch = regcache->arch ();
515 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
516 const struct ppc_reg_offsets *offsets
517 = (const struct ppc_reg_offsets *) regset->regmap;
524 int gpr_size = offsets->gpr_size;
526 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
527 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
528 i++, offset += gpr_size)
529 ppc_supply_reg (regcache, i, (const gdb_byte *) gregs, offset,
532 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
533 (const gdb_byte *) gregs, offsets->pc_offset, gpr_size);
534 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
535 (const gdb_byte *) gregs, offsets->ps_offset, gpr_size);
536 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
537 (const gdb_byte *) gregs, offsets->lr_offset, gpr_size);
538 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
539 (const gdb_byte *) gregs, offsets->ctr_offset, gpr_size);
540 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
541 (const gdb_byte *) gregs, offsets->cr_offset,
543 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
544 (const gdb_byte *) gregs, offsets->xer_offset,
546 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
547 (const gdb_byte *) gregs, offsets->mq_offset,
552 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
553 ppc_supply_reg (regcache, regnum, (const gdb_byte *) gregs, offset, regsize);
556 /* Supply register REGNUM in the floating-point register set REGSET
557 from the buffer specified by FPREGS and LEN to register cache
558 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
561 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
562 int regnum, const void *fpregs, size_t len)
564 struct gdbarch *gdbarch = regcache->arch ();
565 struct gdbarch_tdep *tdep;
566 const struct ppc_reg_offsets *offsets;
569 if (!ppc_floating_point_unit_p (gdbarch))
572 tdep = gdbarch_tdep (gdbarch);
573 offsets = (const struct ppc_reg_offsets *) regset->regmap;
578 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
579 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
581 ppc_supply_reg (regcache, i, (const gdb_byte *) fpregs, offset, 8);
583 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
584 (const gdb_byte *) fpregs, offsets->fpscr_offset,
585 offsets->fpscr_size);
589 offset = ppc_fpreg_offset (tdep, offsets, regnum);
590 ppc_supply_reg (regcache, regnum, (const gdb_byte *) fpregs, offset,
591 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
594 /* Supply register REGNUM in the VSX register set REGSET
595 from the buffer specified by VSXREGS and LEN to register cache
596 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
599 ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
600 int regnum, const void *vsxregs, size_t len)
602 struct gdbarch *gdbarch = regcache->arch ();
603 struct gdbarch_tdep *tdep;
605 if (!ppc_vsx_support_p (gdbarch))
608 tdep = gdbarch_tdep (gdbarch);
614 for (i = tdep->ppc_vsr0_upper_regnum;
615 i < tdep->ppc_vsr0_upper_regnum + 32;
617 ppc_supply_reg (regcache, i, (const gdb_byte *) vsxregs, 0, 8);
622 ppc_supply_reg (regcache, regnum, (const gdb_byte *) vsxregs, 0, 8);
625 /* Supply register REGNUM in the Altivec register set REGSET
626 from the buffer specified by VRREGS and LEN to register cache
627 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
630 ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
631 int regnum, const void *vrregs, size_t len)
633 struct gdbarch *gdbarch = regcache->arch ();
634 struct gdbarch_tdep *tdep;
635 const struct ppc_reg_offsets *offsets;
638 if (!ppc_altivec_support_p (gdbarch))
641 tdep = gdbarch_tdep (gdbarch);
642 offsets = (const struct ppc_reg_offsets *) regset->regmap;
647 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
648 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
650 ppc_supply_reg (regcache, i, (const gdb_byte *) vrregs, offset, 16);
652 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
653 (const gdb_byte *) vrregs, offsets->vscr_offset, 4);
655 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
656 (const gdb_byte *) vrregs, offsets->vrsave_offset, 4);
660 offset = ppc_vrreg_offset (tdep, offsets, regnum);
661 if (regnum != tdep->ppc_vrsave_regnum
662 && regnum != tdep->ppc_vrsave_regnum - 1)
663 ppc_supply_reg (regcache, regnum, (const gdb_byte *) vrregs, offset, 16);
665 ppc_supply_reg (regcache, regnum,
666 (const gdb_byte *) vrregs, offset, 4);
669 /* Collect register REGNUM in the general-purpose register set
670 REGSET from register cache REGCACHE into the buffer specified by
671 GREGS and LEN. If REGNUM is -1, do this for all registers in
675 ppc_collect_gregset (const struct regset *regset,
676 const struct regcache *regcache,
677 int regnum, void *gregs, size_t len)
679 struct gdbarch *gdbarch = regcache->arch ();
680 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
681 const struct ppc_reg_offsets *offsets
682 = (const struct ppc_reg_offsets *) regset->regmap;
689 int gpr_size = offsets->gpr_size;
691 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
692 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
693 i++, offset += gpr_size)
694 ppc_collect_reg (regcache, i, (gdb_byte *) gregs, offset, gpr_size);
696 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
697 (gdb_byte *) gregs, offsets->pc_offset, gpr_size);
698 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
699 (gdb_byte *) gregs, offsets->ps_offset, gpr_size);
700 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
701 (gdb_byte *) gregs, offsets->lr_offset, gpr_size);
702 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
703 (gdb_byte *) gregs, offsets->ctr_offset, gpr_size);
704 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
705 (gdb_byte *) gregs, offsets->cr_offset,
707 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
708 (gdb_byte *) gregs, offsets->xer_offset,
710 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
711 (gdb_byte *) gregs, offsets->mq_offset,
716 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
717 ppc_collect_reg (regcache, regnum, (gdb_byte *) gregs, offset, regsize);
720 /* Collect register REGNUM in the floating-point register set
721 REGSET from register cache REGCACHE into the buffer specified by
722 FPREGS and LEN. If REGNUM is -1, do this for all registers in
726 ppc_collect_fpregset (const struct regset *regset,
727 const struct regcache *regcache,
728 int regnum, void *fpregs, size_t len)
730 struct gdbarch *gdbarch = regcache->arch ();
731 struct gdbarch_tdep *tdep;
732 const struct ppc_reg_offsets *offsets;
735 if (!ppc_floating_point_unit_p (gdbarch))
738 tdep = gdbarch_tdep (gdbarch);
739 offsets = (const struct ppc_reg_offsets *) regset->regmap;
744 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
745 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
747 ppc_collect_reg (regcache, i, (gdb_byte *) fpregs, offset, 8);
749 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
750 (gdb_byte *) fpregs, offsets->fpscr_offset,
751 offsets->fpscr_size);
755 offset = ppc_fpreg_offset (tdep, offsets, regnum);
756 ppc_collect_reg (regcache, regnum, (gdb_byte *) fpregs, offset,
757 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
760 /* Collect register REGNUM in the VSX register set
761 REGSET from register cache REGCACHE into the buffer specified by
762 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
766 ppc_collect_vsxregset (const struct regset *regset,
767 const struct regcache *regcache,
768 int regnum, void *vsxregs, size_t len)
770 struct gdbarch *gdbarch = regcache->arch ();
771 struct gdbarch_tdep *tdep;
773 if (!ppc_vsx_support_p (gdbarch))
776 tdep = gdbarch_tdep (gdbarch);
782 for (i = tdep->ppc_vsr0_upper_regnum;
783 i < tdep->ppc_vsr0_upper_regnum + 32;
785 ppc_collect_reg (regcache, i, (gdb_byte *) vsxregs, 0, 8);
790 ppc_collect_reg (regcache, regnum, (gdb_byte *) vsxregs, 0, 8);
794 /* Collect register REGNUM in the Altivec register set
795 REGSET from register cache REGCACHE into the buffer specified by
796 VRREGS and LEN. If REGNUM is -1, do this for all registers in
800 ppc_collect_vrregset (const struct regset *regset,
801 const struct regcache *regcache,
802 int regnum, void *vrregs, size_t len)
804 struct gdbarch *gdbarch = regcache->arch ();
805 struct gdbarch_tdep *tdep;
806 const struct ppc_reg_offsets *offsets;
809 if (!ppc_altivec_support_p (gdbarch))
812 tdep = gdbarch_tdep (gdbarch);
813 offsets = (const struct ppc_reg_offsets *) regset->regmap;
818 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
819 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
821 ppc_collect_reg (regcache, i, (gdb_byte *) vrregs, offset, 16);
823 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
824 (gdb_byte *) vrregs, offsets->vscr_offset, 4);
826 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
827 (gdb_byte *) vrregs, offsets->vrsave_offset, 4);
831 offset = ppc_vrreg_offset (tdep, offsets, regnum);
832 if (regnum != tdep->ppc_vrsave_regnum
833 && regnum != tdep->ppc_vrsave_regnum - 1)
834 ppc_collect_reg (regcache, regnum, (gdb_byte *) vrregs, offset, 16);
836 ppc_collect_reg (regcache, regnum,
837 (gdb_byte *) vrregs, offset, 4);
842 insn_changes_sp_or_jumps (unsigned long insn)
844 int opcode = (insn >> 26) & 0x03f;
845 int sd = (insn >> 21) & 0x01f;
846 int a = (insn >> 16) & 0x01f;
847 int subcode = (insn >> 1) & 0x3ff;
849 /* Changes the stack pointer. */
851 /* NOTE: There are many ways to change the value of a given register.
852 The ways below are those used when the register is R1, the SP,
853 in a funtion's epilogue. */
855 if (opcode == 31 && subcode == 444 && a == 1)
856 return 1; /* mr R1,Rn */
857 if (opcode == 14 && sd == 1)
858 return 1; /* addi R1,Rn,simm */
859 if (opcode == 58 && sd == 1)
860 return 1; /* ld R1,ds(Rn) */
862 /* Transfers control. */
868 if (opcode == 19 && subcode == 16)
870 if (opcode == 19 && subcode == 528)
871 return 1; /* bcctr */
876 /* Return true if we are in the function's epilogue, i.e. after the
877 instruction that destroyed the function's stack frame.
879 1) scan forward from the point of execution:
880 a) If you find an instruction that modifies the stack pointer
881 or transfers control (except a return), execution is not in
883 b) Stop scanning if you find a return instruction or reach the
884 end of the function or reach the hard limit for the size of
886 2) scan backward from the point of execution:
887 a) If you find an instruction that modifies the stack pointer,
888 execution *is* in an epilogue, return.
889 b) Stop scanning if you reach an instruction that transfers
890 control or the beginning of the function or reach the hard
891 limit for the size of an epilogue. */
894 rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm,
895 struct gdbarch *gdbarch, CORE_ADDR pc)
897 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
898 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
899 bfd_byte insn_buf[PPC_INSN_SIZE];
900 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
903 /* Find the search limits based on function boundaries and hard limit. */
905 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
908 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
909 if (epilogue_start < func_start) epilogue_start = func_start;
911 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
912 if (epilogue_end > func_end) epilogue_end = func_end;
914 /* Scan forward until next 'blr'. */
916 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
918 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
920 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
921 if (insn == 0x4e800020)
923 /* Assume a bctr is a tail call unless it points strictly within
925 if (insn == 0x4e800420)
927 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
928 tdep->ppc_ctr_regnum);
929 if (ctr > func_start && ctr < func_end)
934 if (insn_changes_sp_or_jumps (insn))
938 /* Scan backward until adjustment to stack pointer (R1). */
940 for (scan_pc = pc - PPC_INSN_SIZE;
941 scan_pc >= epilogue_start;
942 scan_pc -= PPC_INSN_SIZE)
944 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
946 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
947 if (insn_changes_sp_or_jumps (insn))
954 /* Implement the stack_frame_destroyed_p gdbarch method. */
957 rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
959 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
963 /* Get the ith function argument for the current function. */
965 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
968 return get_frame_register_unsigned (frame, 3 + argi);
971 /* Sequence of bytes for breakpoint instruction. */
973 constexpr gdb_byte big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
974 constexpr gdb_byte little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
976 typedef BP_MANIPULATION_ENDIAN (little_breakpoint, big_breakpoint)
979 /* Instruction masks for displaced stepping. */
980 #define BRANCH_MASK 0xfc000000
981 #define BP_MASK 0xFC0007FE
982 #define B_INSN 0x48000000
983 #define BC_INSN 0x40000000
984 #define BXL_INSN 0x4c000000
985 #define BP_INSN 0x7C000008
987 /* Instruction masks used during single-stepping of atomic
989 #define LOAD_AND_RESERVE_MASK 0xfc0007fe
990 #define LWARX_INSTRUCTION 0x7c000028
991 #define LDARX_INSTRUCTION 0x7c0000A8
992 #define LBARX_INSTRUCTION 0x7c000068
993 #define LHARX_INSTRUCTION 0x7c0000e8
994 #define LQARX_INSTRUCTION 0x7c000228
995 #define STORE_CONDITIONAL_MASK 0xfc0007ff
996 #define STWCX_INSTRUCTION 0x7c00012d
997 #define STDCX_INSTRUCTION 0x7c0001ad
998 #define STBCX_INSTRUCTION 0x7c00056d
999 #define STHCX_INSTRUCTION 0x7c0005ad
1000 #define STQCX_INSTRUCTION 0x7c00016d
1002 /* Check if insn is one of the Load And Reserve instructions used for atomic
1004 #define IS_LOAD_AND_RESERVE_INSN(insn) ((insn & LOAD_AND_RESERVE_MASK) == LWARX_INSTRUCTION \
1005 || (insn & LOAD_AND_RESERVE_MASK) == LDARX_INSTRUCTION \
1006 || (insn & LOAD_AND_RESERVE_MASK) == LBARX_INSTRUCTION \
1007 || (insn & LOAD_AND_RESERVE_MASK) == LHARX_INSTRUCTION \
1008 || (insn & LOAD_AND_RESERVE_MASK) == LQARX_INSTRUCTION)
1009 /* Check if insn is one of the Store Conditional instructions used for atomic
1011 #define IS_STORE_CONDITIONAL_INSN(insn) ((insn & STORE_CONDITIONAL_MASK) == STWCX_INSTRUCTION \
1012 || (insn & STORE_CONDITIONAL_MASK) == STDCX_INSTRUCTION \
1013 || (insn & STORE_CONDITIONAL_MASK) == STBCX_INSTRUCTION \
1014 || (insn & STORE_CONDITIONAL_MASK) == STHCX_INSTRUCTION \
1015 || (insn & STORE_CONDITIONAL_MASK) == STQCX_INSTRUCTION)
1017 typedef buf_displaced_step_closure ppc_displaced_step_closure;
1019 /* We can't displaced step atomic sequences. */
1021 static struct displaced_step_closure *
1022 ppc_displaced_step_copy_insn (struct gdbarch *gdbarch,
1023 CORE_ADDR from, CORE_ADDR to,
1024 struct regcache *regs)
1026 size_t len = gdbarch_max_insn_length (gdbarch);
1027 std::unique_ptr<ppc_displaced_step_closure> closure
1028 (new ppc_displaced_step_closure (len));
1029 gdb_byte *buf = closure->buf.data ();
1030 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1033 read_memory (from, buf, len);
1035 insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order);
1037 /* Assume all atomic sequences start with a Load and Reserve instruction. */
1038 if (IS_LOAD_AND_RESERVE_INSN (insn))
1040 if (debug_displaced)
1042 fprintf_unfiltered (gdb_stdlog,
1043 "displaced: can't displaced step "
1044 "atomic sequence at %s\n",
1045 paddress (gdbarch, from));
1051 write_memory (to, buf, len);
1053 if (debug_displaced)
1055 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1056 paddress (gdbarch, from), paddress (gdbarch, to));
1057 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1060 return closure.release ();
1063 /* Fix up the state of registers and memory after having single-stepped
1064 a displaced instruction. */
1066 ppc_displaced_step_fixup (struct gdbarch *gdbarch,
1067 struct displaced_step_closure *closure_,
1068 CORE_ADDR from, CORE_ADDR to,
1069 struct regcache *regs)
1071 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1072 /* Our closure is a copy of the instruction. */
1073 ppc_displaced_step_closure *closure = (ppc_displaced_step_closure *) closure_;
1074 ULONGEST insn = extract_unsigned_integer (closure->buf.data (),
1075 PPC_INSN_SIZE, byte_order);
1076 ULONGEST opcode = 0;
1077 /* Offset for non PC-relative instructions. */
1078 LONGEST offset = PPC_INSN_SIZE;
1080 opcode = insn & BRANCH_MASK;
1082 if (debug_displaced)
1083 fprintf_unfiltered (gdb_stdlog,
1084 "displaced: (ppc) fixup (%s, %s)\n",
1085 paddress (gdbarch, from), paddress (gdbarch, to));
1088 /* Handle PC-relative branch instructions. */
1089 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
1091 ULONGEST current_pc;
1093 /* Read the current PC value after the instruction has been executed
1094 in a displaced location. Calculate the offset to be applied to the
1095 original PC value before the displaced stepping. */
1096 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1098 offset = current_pc - to;
1100 if (opcode != BXL_INSN)
1102 /* Check for AA bit indicating whether this is an absolute
1103 addressing or PC-relative (1: absolute, 0: relative). */
1106 /* PC-relative addressing is being used in the branch. */
1107 if (debug_displaced)
1110 "displaced: (ppc) branch instruction: %s\n"
1111 "displaced: (ppc) adjusted PC from %s to %s\n",
1112 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1113 paddress (gdbarch, from + offset));
1115 regcache_cooked_write_unsigned (regs,
1116 gdbarch_pc_regnum (gdbarch),
1122 /* If we're here, it means we have a branch to LR or CTR. If the
1123 branch was taken, the offset is probably greater than 4 (the next
1124 instruction), so it's safe to assume that an offset of 4 means we
1125 did not take the branch. */
1126 if (offset == PPC_INSN_SIZE)
1127 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1128 from + PPC_INSN_SIZE);
1131 /* Check for LK bit indicating whether we should set the link
1132 register to point to the next instruction
1133 (1: Set, 0: Don't set). */
1136 /* Link register needs to be set to the next instruction's PC. */
1137 regcache_cooked_write_unsigned (regs,
1138 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1139 from + PPC_INSN_SIZE);
1140 if (debug_displaced)
1141 fprintf_unfiltered (gdb_stdlog,
1142 "displaced: (ppc) adjusted LR to %s\n",
1143 paddress (gdbarch, from + PPC_INSN_SIZE));
1147 /* Check for breakpoints in the inferior. If we've found one, place the PC
1148 right at the breakpoint instruction. */
1149 else if ((insn & BP_MASK) == BP_INSN)
1150 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1152 /* Handle any other instructions that do not fit in the categories above. */
1153 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1157 /* Always use hardware single-stepping to execute the
1158 displaced instruction. */
1160 ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1161 struct displaced_step_closure *closure)
1166 /* Checks for an atomic sequence of instructions beginning with a
1167 Load And Reserve instruction and ending with a Store Conditional
1168 instruction. If such a sequence is found, attempt to step through it.
1169 A breakpoint is placed at the end of the sequence. */
1170 std::vector<CORE_ADDR>
1171 ppc_deal_with_atomic_sequence (struct regcache *regcache)
1173 struct gdbarch *gdbarch = regcache->arch ();
1174 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1175 CORE_ADDR pc = regcache_read_pc (regcache);
1176 CORE_ADDR breaks[2] = {-1, -1};
1178 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
1179 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1182 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1183 const int atomic_sequence_length = 16; /* Instruction sequence length. */
1184 int bc_insn_count = 0; /* Conditional branch instruction count. */
1186 /* Assume all atomic sequences start with a Load And Reserve instruction. */
1187 if (!IS_LOAD_AND_RESERVE_INSN (insn))
1190 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1192 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1194 loc += PPC_INSN_SIZE;
1195 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1197 /* Assume that there is at most one conditional branch in the atomic
1198 sequence. If a conditional branch is found, put a breakpoint in
1199 its destination address. */
1200 if ((insn & BRANCH_MASK) == BC_INSN)
1202 int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1203 int absolute = insn & 2;
1205 if (bc_insn_count >= 1)
1206 return {}; /* More than one conditional branch found, fallback
1207 to the standard single-step code. */
1210 breaks[1] = immediate;
1212 breaks[1] = loc + immediate;
1218 if (IS_STORE_CONDITIONAL_INSN (insn))
1222 /* Assume that the atomic sequence ends with a Store Conditional
1224 if (!IS_STORE_CONDITIONAL_INSN (insn))
1228 loc += PPC_INSN_SIZE;
1230 /* Insert a breakpoint right after the end of the atomic sequence. */
1233 /* Check for duplicated breakpoints. Check also for a breakpoint
1234 placed (branch instruction's destination) anywhere in sequence. */
1236 && (breaks[1] == breaks[0]
1237 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
1238 last_breakpoint = 0;
1240 std::vector<CORE_ADDR> next_pcs;
1242 for (index = 0; index <= last_breakpoint; index++)
1243 next_pcs.push_back (breaks[index]);
1249 #define SIGNED_SHORT(x) \
1250 ((sizeof (short) == 2) \
1251 ? ((int)(short)(x)) \
1252 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1254 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1256 /* Limit the number of skipped non-prologue instructions, as the examining
1257 of the prologue is expensive. */
1258 static int max_skip_non_prologue_insns = 10;
1260 /* Return nonzero if the given instruction OP can be part of the prologue
1261 of a function and saves a parameter on the stack. FRAMEP should be
1262 set if one of the previous instructions in the function has set the
1266 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1268 /* Move parameters from argument registers to temporary register. */
1269 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1271 /* Rx must be scratch register r0. */
1272 const int rx_regno = (op >> 16) & 31;
1273 /* Ry: Only r3 - r10 are used for parameter passing. */
1274 const int ry_regno = GET_SRC_REG (op);
1276 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1278 *r0_contains_arg = 1;
1285 /* Save a General Purpose Register on stack. */
1287 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1288 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1290 /* Rx: Only r3 - r10 are used for parameter passing. */
1291 const int rx_regno = GET_SRC_REG (op);
1293 return (rx_regno >= 3 && rx_regno <= 10);
1296 /* Save a General Purpose Register on stack via the Frame Pointer. */
1299 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1300 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1301 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1303 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1304 However, the compiler sometimes uses r0 to hold an argument. */
1305 const int rx_regno = GET_SRC_REG (op);
1307 return ((rx_regno >= 3 && rx_regno <= 10)
1308 || (rx_regno == 0 && *r0_contains_arg));
1311 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1313 /* Only f2 - f8 are used for parameter passing. */
1314 const int src_regno = GET_SRC_REG (op);
1316 return (src_regno >= 2 && src_regno <= 8);
1319 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1321 /* Only f2 - f8 are used for parameter passing. */
1322 const int src_regno = GET_SRC_REG (op);
1324 return (src_regno >= 2 && src_regno <= 8);
1327 /* Not an insn that saves a parameter on stack. */
1331 /* Assuming that INSN is a "bl" instruction located at PC, return
1332 nonzero if the destination of the branch is a "blrl" instruction.
1334 This sequence is sometimes found in certain function prologues.
1335 It allows the function to load the LR register with a value that
1336 they can use to access PIC data using PC-relative offsets. */
1339 bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
1346 absolute = (int) ((insn >> 1) & 1);
1347 immediate = ((insn & ~3) << 6) >> 6;
1351 dest = pc + immediate;
1353 dest_insn = read_memory_integer (dest, 4, byte_order);
1354 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1360 /* Masks for decoding a branch-and-link (bl) instruction.
1362 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1363 The former is anded with the opcode in question; if the result of
1364 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1365 question is a ``bl'' instruction.
1367 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1368 the branch displacement. */
1370 #define BL_MASK 0xfc000001
1371 #define BL_INSTRUCTION 0x48000001
1372 #define BL_DISPLACEMENT_MASK 0x03fffffc
1374 static unsigned long
1375 rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
1377 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1381 /* Fetch the instruction and convert it to an integer. */
1382 if (target_read_memory (pc, buf, 4))
1384 op = extract_unsigned_integer (buf, 4, byte_order);
1389 /* GCC generates several well-known sequences of instructions at the begining
1390 of each function prologue when compiling with -fstack-check. If one of
1391 such sequences starts at START_PC, then return the address of the
1392 instruction immediately past this sequence. Otherwise, return START_PC. */
1395 rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
1397 CORE_ADDR pc = start_pc;
1398 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
1400 /* First possible sequence: A small number of probes.
1401 stw 0, -<some immediate>(1)
1402 [repeat this instruction any (small) number of times]. */
1404 if ((op & 0xffff0000) == 0x90010000)
1406 while ((op & 0xffff0000) == 0x90010000)
1409 op = rs6000_fetch_instruction (gdbarch, pc);
1414 /* Second sequence: A probing loop.
1415 addi 12,1,-<some immediate>
1416 lis 0,-<some immediate>
1417 [possibly ori 0,0,<some immediate>]
1421 addi 12,12,-<some immediate>
1424 [possibly one last probe: stw 0,<some immediate>(12)]. */
1428 /* addi 12,1,-<some immediate> */
1429 if ((op & 0xffff0000) != 0x39810000)
1432 /* lis 0,-<some immediate> */
1434 op = rs6000_fetch_instruction (gdbarch, pc);
1435 if ((op & 0xffff0000) != 0x3c000000)
1439 op = rs6000_fetch_instruction (gdbarch, pc);
1440 /* [possibly ori 0,0,<some immediate>] */
1441 if ((op & 0xffff0000) == 0x60000000)
1444 op = rs6000_fetch_instruction (gdbarch, pc);
1447 if (op != 0x7c0c0214)
1452 op = rs6000_fetch_instruction (gdbarch, pc);
1453 if (op != 0x7c0c0000)
1458 op = rs6000_fetch_instruction (gdbarch, pc);
1459 if ((op & 0xff9f0001) != 0x41820000)
1462 /* addi 12,12,-<some immediate> */
1464 op = rs6000_fetch_instruction (gdbarch, pc);
1465 if ((op & 0xffff0000) != 0x398c0000)
1470 op = rs6000_fetch_instruction (gdbarch, pc);
1471 if (op != 0x900c0000)
1476 op = rs6000_fetch_instruction (gdbarch, pc);
1477 if ((op & 0xfc000001) != 0x48000000)
1480 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1482 op = rs6000_fetch_instruction (gdbarch, pc);
1483 if ((op & 0xffff0000) == 0x900c0000)
1486 op = rs6000_fetch_instruction (gdbarch, pc);
1489 /* We found a valid stack-check sequence, return the new PC. */
1493 /* Third sequence: No probe; instead, a comparizon between the stack size
1494 limit (saved in a run-time global variable) and the current stack
1497 addi 0,1,-<some immediate>
1498 lis 12,__gnat_stack_limit@ha
1499 lwz 12,__gnat_stack_limit@l(12)
1502 or, with a small variant in the case of a bigger stack frame:
1503 addis 0,1,<some immediate>
1504 addic 0,0,-<some immediate>
1505 lis 12,__gnat_stack_limit@ha
1506 lwz 12,__gnat_stack_limit@l(12)
1511 /* addi 0,1,-<some immediate> */
1512 if ((op & 0xffff0000) != 0x38010000)
1514 /* small stack frame variant not recognized; try the
1515 big stack frame variant: */
1517 /* addis 0,1,<some immediate> */
1518 if ((op & 0xffff0000) != 0x3c010000)
1521 /* addic 0,0,-<some immediate> */
1523 op = rs6000_fetch_instruction (gdbarch, pc);
1524 if ((op & 0xffff0000) != 0x30000000)
1528 /* lis 12,<some immediate> */
1530 op = rs6000_fetch_instruction (gdbarch, pc);
1531 if ((op & 0xffff0000) != 0x3d800000)
1534 /* lwz 12,<some immediate>(12) */
1536 op = rs6000_fetch_instruction (gdbarch, pc);
1537 if ((op & 0xffff0000) != 0x818c0000)
1542 op = rs6000_fetch_instruction (gdbarch, pc);
1543 if ((op & 0xfffffffe) != 0x7c406008)
1546 /* We found a valid stack-check sequence, return the new PC. */
1550 /* No stack check code in our prologue, return the start_pc. */
1554 /* return pc value after skipping a function prologue and also return
1555 information about a function frame.
1557 in struct rs6000_framedata fdata:
1558 - frameless is TRUE, if function does not have a frame.
1559 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1560 - offset is the initial size of this stack frame --- the amount by
1561 which we decrement the sp to allocate the frame.
1562 - saved_gpr is the number of the first saved gpr.
1563 - saved_fpr is the number of the first saved fpr.
1564 - saved_vr is the number of the first saved vr.
1565 - saved_ev is the number of the first saved ev.
1566 - alloca_reg is the number of the register used for alloca() handling.
1568 - gpr_offset is the offset of the first saved gpr from the previous frame.
1569 - fpr_offset is the offset of the first saved fpr from the previous frame.
1570 - vr_offset is the offset of the first saved vr from the previous frame.
1571 - ev_offset is the offset of the first saved ev from the previous frame.
1572 - lr_offset is the offset of the saved lr
1573 - cr_offset is the offset of the saved cr
1574 - vrsave_offset is the offset of the saved vrsave register. */
1577 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1578 struct rs6000_framedata *fdata)
1580 CORE_ADDR orig_pc = pc;
1581 CORE_ADDR last_prologue_pc = pc;
1582 CORE_ADDR li_found_pc = 0;
1586 long vr_saved_offset = 0;
1592 int vrsave_reg = -1;
1595 int minimal_toc_loaded = 0;
1596 int prev_insn_was_prologue_insn = 1;
1597 int num_skip_non_prologue_insns = 0;
1598 int r0_contains_arg = 0;
1599 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1600 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1601 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1603 memset (fdata, 0, sizeof (struct rs6000_framedata));
1604 fdata->saved_gpr = -1;
1605 fdata->saved_fpr = -1;
1606 fdata->saved_vr = -1;
1607 fdata->saved_ev = -1;
1608 fdata->alloca_reg = -1;
1609 fdata->frameless = 1;
1610 fdata->nosavedpc = 1;
1611 fdata->lr_register = -1;
1613 pc = rs6000_skip_stack_check (gdbarch, pc);
1619 /* Sometimes it isn't clear if an instruction is a prologue
1620 instruction or not. When we encounter one of these ambiguous
1621 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1622 Otherwise, we'll assume that it really is a prologue instruction. */
1623 if (prev_insn_was_prologue_insn)
1624 last_prologue_pc = pc;
1626 /* Stop scanning if we've hit the limit. */
1630 prev_insn_was_prologue_insn = 1;
1632 /* Fetch the instruction and convert it to an integer. */
1633 if (target_read_memory (pc, buf, 4))
1635 op = extract_unsigned_integer (buf, 4, byte_order);
1637 if ((op & 0xfc1fffff) == 0x7c0802a6)
1639 /* Since shared library / PIC code, which needs to get its
1640 address at runtime, can appear to save more than one link
1654 remember just the first one, but skip over additional
1657 lr_reg = (op & 0x03e00000) >> 21;
1659 r0_contains_arg = 0;
1662 else if ((op & 0xfc1fffff) == 0x7c000026)
1664 cr_reg = (op & 0x03e00000);
1666 r0_contains_arg = 0;
1670 else if ((op & 0xfc1f0000) == 0xd8010000)
1671 { /* stfd Rx,NUM(r1) */
1672 reg = GET_SRC_REG (op);
1673 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1675 fdata->saved_fpr = reg;
1676 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1681 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1682 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1683 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1684 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1687 reg = GET_SRC_REG (op);
1688 if ((op & 0xfc1f0000) == 0xbc010000)
1689 fdata->gpr_mask |= ~((1U << reg) - 1);
1691 fdata->gpr_mask |= 1U << reg;
1692 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1694 fdata->saved_gpr = reg;
1695 if ((op & 0xfc1f0003) == 0xf8010000)
1697 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1702 else if ((op & 0xffff0000) == 0x3c4c0000
1703 || (op & 0xffff0000) == 0x3c400000
1704 || (op & 0xffff0000) == 0x38420000)
1706 /* . 0: addis 2,12,.TOC.-0b@ha
1707 . addi 2,2,.TOC.-0b@l
1711 used by ELFv2 global entry points to set up r2. */
1714 else if (op == 0x60000000)
1717 /* Allow nops in the prologue, but do not consider them to
1718 be part of the prologue unless followed by other prologue
1720 prev_insn_was_prologue_insn = 0;
1724 else if ((op & 0xffff0000) == 0x3c000000)
1725 { /* addis 0,0,NUM, used for >= 32k frames */
1726 fdata->offset = (op & 0x0000ffff) << 16;
1727 fdata->frameless = 0;
1728 r0_contains_arg = 0;
1732 else if ((op & 0xffff0000) == 0x60000000)
1733 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1734 fdata->offset |= (op & 0x0000ffff);
1735 fdata->frameless = 0;
1736 r0_contains_arg = 0;
1740 else if (lr_reg >= 0 &&
1741 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1742 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1743 /* stw Rx, NUM(r1) */
1744 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1745 /* stwu Rx, NUM(r1) */
1746 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1747 { /* where Rx == lr */
1748 fdata->lr_offset = offset;
1749 fdata->nosavedpc = 0;
1750 /* Invalidate lr_reg, but don't set it to -1.
1751 That would mean that it had never been set. */
1753 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1754 (op & 0xfc000000) == 0x90000000) /* stw */
1756 /* Does not update r1, so add displacement to lr_offset. */
1757 fdata->lr_offset += SIGNED_SHORT (op);
1762 else if (cr_reg >= 0 &&
1763 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1764 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1765 /* stw Rx, NUM(r1) */
1766 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1767 /* stwu Rx, NUM(r1) */
1768 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1769 { /* where Rx == cr */
1770 fdata->cr_offset = offset;
1771 /* Invalidate cr_reg, but don't set it to -1.
1772 That would mean that it had never been set. */
1774 if ((op & 0xfc000003) == 0xf8000000 ||
1775 (op & 0xfc000000) == 0x90000000)
1777 /* Does not update r1, so add displacement to cr_offset. */
1778 fdata->cr_offset += SIGNED_SHORT (op);
1783 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1785 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1786 prediction bits. If the LR has already been saved, we can
1790 else if (op == 0x48000005)
1797 else if (op == 0x48000004)
1802 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1803 in V.4 -mminimal-toc */
1804 (op & 0xffff0000) == 0x3bde0000)
1805 { /* addi 30,30,foo@l */
1809 else if ((op & 0xfc000001) == 0x48000001)
1813 fdata->frameless = 0;
1815 /* If the return address has already been saved, we can skip
1816 calls to blrl (for PIC). */
1817 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
1823 /* Don't skip over the subroutine call if it is not within
1824 the first three instructions of the prologue and either
1825 we have no line table information or the line info tells
1826 us that the subroutine call is not part of the line
1827 associated with the prologue. */
1828 if ((pc - orig_pc) > 8)
1830 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1831 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1833 if ((prologue_sal.line == 0)
1834 || (prologue_sal.line != this_sal.line))
1838 op = read_memory_integer (pc + 4, 4, byte_order);
1840 /* At this point, make sure this is not a trampoline
1841 function (a function that simply calls another functions,
1842 and nothing else). If the next is not a nop, this branch
1843 was part of the function prologue. */
1845 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1846 break; /* Don't skip over
1852 /* update stack pointer */
1853 else if ((op & 0xfc1f0000) == 0x94010000)
1854 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1855 fdata->frameless = 0;
1856 fdata->offset = SIGNED_SHORT (op);
1857 offset = fdata->offset;
1860 else if ((op & 0xfc1f016a) == 0x7c01016e)
1861 { /* stwux rX,r1,rY */
1862 /* No way to figure out what r1 is going to be. */
1863 fdata->frameless = 0;
1864 offset = fdata->offset;
1867 else if ((op & 0xfc1f0003) == 0xf8010001)
1868 { /* stdu rX,NUM(r1) */
1869 fdata->frameless = 0;
1870 fdata->offset = SIGNED_SHORT (op & ~3UL);
1871 offset = fdata->offset;
1874 else if ((op & 0xfc1f016a) == 0x7c01016a)
1875 { /* stdux rX,r1,rY */
1876 /* No way to figure out what r1 is going to be. */
1877 fdata->frameless = 0;
1878 offset = fdata->offset;
1881 else if ((op & 0xffff0000) == 0x38210000)
1882 { /* addi r1,r1,SIMM */
1883 fdata->frameless = 0;
1884 fdata->offset += SIGNED_SHORT (op);
1885 offset = fdata->offset;
1888 /* Load up minimal toc pointer. Do not treat an epilogue restore
1889 of r31 as a minimal TOC load. */
1890 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1891 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1893 && !minimal_toc_loaded)
1895 minimal_toc_loaded = 1;
1898 /* move parameters from argument registers to local variable
1901 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1902 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1903 (((op >> 21) & 31) <= 10) &&
1904 ((long) ((op >> 16) & 31)
1905 >= fdata->saved_gpr)) /* Rx: local var reg */
1909 /* store parameters in stack */
1911 /* Move parameters from argument registers to temporary register. */
1912 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1916 /* Set up frame pointer */
1918 else if (op == 0x603d0000) /* oril r29, r1, 0x0 */
1920 fdata->frameless = 0;
1922 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29);
1925 /* Another way to set up the frame pointer. */
1927 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1928 || op == 0x7c3f0b78)
1930 fdata->frameless = 0;
1932 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1935 /* Another way to set up the frame pointer. */
1937 else if ((op & 0xfc1fffff) == 0x38010000)
1938 { /* addi rX, r1, 0x0 */
1939 fdata->frameless = 0;
1941 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1942 + ((op & ~0x38010000) >> 21));
1945 /* AltiVec related instructions. */
1946 /* Store the vrsave register (spr 256) in another register for
1947 later manipulation, or load a register into the vrsave
1948 register. 2 instructions are used: mfvrsave and
1949 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1950 and mtspr SPR256, Rn. */
1951 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1952 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1953 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1955 vrsave_reg = GET_SRC_REG (op);
1958 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1962 /* Store the register where vrsave was saved to onto the stack:
1963 rS is the register where vrsave was stored in a previous
1965 /* 100100 sssss 00001 dddddddd dddddddd */
1966 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1968 if (vrsave_reg == GET_SRC_REG (op))
1970 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1975 /* Compute the new value of vrsave, by modifying the register
1976 where vrsave was saved to. */
1977 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1978 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1982 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1983 in a pair of insns to save the vector registers on the
1985 /* 001110 00000 00000 iiii iiii iiii iiii */
1986 /* 001110 01110 00000 iiii iiii iiii iiii */
1987 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1988 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1990 if ((op & 0xffff0000) == 0x38000000)
1991 r0_contains_arg = 0;
1993 vr_saved_offset = SIGNED_SHORT (op);
1995 /* This insn by itself is not part of the prologue, unless
1996 if part of the pair of insns mentioned above. So do not
1997 record this insn as part of the prologue yet. */
1998 prev_insn_was_prologue_insn = 0;
2000 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
2001 /* 011111 sssss 11111 00000 00111001110 */
2002 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
2004 if (pc == (li_found_pc + 4))
2006 vr_reg = GET_SRC_REG (op);
2007 /* If this is the first vector reg to be saved, or if
2008 it has a lower number than others previously seen,
2009 reupdate the frame info. */
2010 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
2012 fdata->saved_vr = vr_reg;
2013 fdata->vr_offset = vr_saved_offset + offset;
2015 vr_saved_offset = -1;
2020 /* End AltiVec related instructions. */
2022 /* Start BookE related instructions. */
2023 /* Store gen register S at (r31+uimm).
2024 Any register less than r13 is volatile, so we don't care. */
2025 /* 000100 sssss 11111 iiiii 01100100001 */
2026 else if (arch_info->mach == bfd_mach_ppc_e500
2027 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2029 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2032 ev_reg = GET_SRC_REG (op);
2033 imm = (op >> 11) & 0x1f;
2034 ev_offset = imm * 8;
2035 /* If this is the first vector reg to be saved, or if
2036 it has a lower number than others previously seen,
2037 reupdate the frame info. */
2038 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2040 fdata->saved_ev = ev_reg;
2041 fdata->ev_offset = ev_offset + offset;
2046 /* Store gen register rS at (r1+rB). */
2047 /* 000100 sssss 00001 bbbbb 01100100000 */
2048 else if (arch_info->mach == bfd_mach_ppc_e500
2049 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2051 if (pc == (li_found_pc + 4))
2053 ev_reg = GET_SRC_REG (op);
2054 /* If this is the first vector reg to be saved, or if
2055 it has a lower number than others previously seen,
2056 reupdate the frame info. */
2057 /* We know the contents of rB from the previous instruction. */
2058 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2060 fdata->saved_ev = ev_reg;
2061 fdata->ev_offset = vr_saved_offset + offset;
2063 vr_saved_offset = -1;
2069 /* Store gen register r31 at (rA+uimm). */
2070 /* 000100 11111 aaaaa iiiii 01100100001 */
2071 else if (arch_info->mach == bfd_mach_ppc_e500
2072 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2074 /* Wwe know that the source register is 31 already, but
2075 it can't hurt to compute it. */
2076 ev_reg = GET_SRC_REG (op);
2077 ev_offset = ((op >> 11) & 0x1f) * 8;
2078 /* If this is the first vector reg to be saved, or if
2079 it has a lower number than others previously seen,
2080 reupdate the frame info. */
2081 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2083 fdata->saved_ev = ev_reg;
2084 fdata->ev_offset = ev_offset + offset;
2089 /* Store gen register S at (r31+r0).
2090 Store param on stack when offset from SP bigger than 4 bytes. */
2091 /* 000100 sssss 11111 00000 01100100000 */
2092 else if (arch_info->mach == bfd_mach_ppc_e500
2093 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2095 if (pc == (li_found_pc + 4))
2097 if ((op & 0x03e00000) >= 0x01a00000)
2099 ev_reg = GET_SRC_REG (op);
2100 /* If this is the first vector reg to be saved, or if
2101 it has a lower number than others previously seen,
2102 reupdate the frame info. */
2103 /* We know the contents of r0 from the previous
2105 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2107 fdata->saved_ev = ev_reg;
2108 fdata->ev_offset = vr_saved_offset + offset;
2112 vr_saved_offset = -1;
2117 /* End BookE related instructions. */
2121 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2123 /* Not a recognized prologue instruction.
2124 Handle optimizer code motions into the prologue by continuing
2125 the search if we have no valid frame yet or if the return
2126 address is not yet saved in the frame. Also skip instructions
2127 if some of the GPRs expected to be saved are not yet saved. */
2128 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2129 && (fdata->gpr_mask & all_mask) == all_mask)
2132 if (op == 0x4e800020 /* blr */
2133 || op == 0x4e800420) /* bctr */
2134 /* Do not scan past epilogue in frameless functions or
2137 if ((op & 0xf4000000) == 0x40000000) /* bxx */
2138 /* Never skip branches. */
2141 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2142 /* Do not scan too many insns, scanning insns is expensive with
2146 /* Continue scanning. */
2147 prev_insn_was_prologue_insn = 0;
2153 /* I have problems with skipping over __main() that I need to address
2154 * sometime. Previously, I used to use misc_function_vector which
2155 * didn't work as well as I wanted to be. -MGO */
2157 /* If the first thing after skipping a prolog is a branch to a function,
2158 this might be a call to an initializer in main(), introduced by gcc2.
2159 We'd like to skip over it as well. Fortunately, xlc does some extra
2160 work before calling a function right after a prologue, thus we can
2161 single out such gcc2 behaviour. */
2164 if ((op & 0xfc000001) == 0x48000001)
2165 { /* bl foo, an initializer function? */
2166 op = read_memory_integer (pc + 4, 4, byte_order);
2168 if (op == 0x4def7b82)
2169 { /* cror 0xf, 0xf, 0xf (nop) */
2171 /* Check and see if we are in main. If so, skip over this
2172 initializer function as well. */
2174 tmp = find_pc_misc_function (pc);
2176 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
2182 if (pc == lim_pc && lr_reg >= 0)
2183 fdata->lr_register = lr_reg;
2185 fdata->offset = -fdata->offset;
2186 return last_prologue_pc;
2190 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2192 struct rs6000_framedata frame;
2193 CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
2195 /* See if we can determine the end of the prologue via the symbol table.
2196 If so, then return either PC, or the PC after the prologue, whichever
2198 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
2200 CORE_ADDR post_prologue_pc
2201 = skip_prologue_using_sal (gdbarch, func_addr);
2202 if (post_prologue_pc != 0)
2203 return std::max (pc, post_prologue_pc);
2206 /* Can't determine prologue from the symbol table, need to examine
2209 /* Find an upper limit on the function prologue using the debug
2210 information. If the debug information could not be used to provide
2211 that bound, then use an arbitrary large number as the upper bound. */
2212 limit_pc = skip_prologue_using_sal (gdbarch, pc);
2214 limit_pc = pc + 100; /* Magic. */
2216 /* Do not allow limit_pc to be past the function end, if we know
2217 where that end is... */
2218 if (func_end_addr && limit_pc > func_end_addr)
2219 limit_pc = func_end_addr;
2221 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2225 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2226 in the prologue of main().
2228 The function below examines the code pointed at by PC and checks to
2229 see if it corresponds to a call to __eabi. If so, it returns the
2230 address of the instruction following that call. Otherwise, it simply
2234 rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2236 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2240 if (target_read_memory (pc, buf, 4))
2242 op = extract_unsigned_integer (buf, 4, byte_order);
2244 if ((op & BL_MASK) == BL_INSTRUCTION)
2246 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2247 CORE_ADDR call_dest = pc + 4 + displ;
2248 struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest);
2250 /* We check for ___eabi (three leading underscores) in addition
2251 to __eabi in case the GCC option "-fleading-underscore" was
2252 used to compile the program. */
2253 if (s.minsym != NULL
2254 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
2255 && (strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__eabi") == 0
2256 || strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "___eabi") == 0))
2262 /* All the ABI's require 16 byte alignment. */
2264 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2266 return (addr & -16);
2269 /* Return whether handle_inferior_event() should proceed through code
2270 starting at PC in function NAME when stepping.
2272 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2273 handle memory references that are too distant to fit in instructions
2274 generated by the compiler. For example, if 'foo' in the following
2279 is greater than 32767, the linker might replace the lwz with a branch to
2280 somewhere in @FIX1 that does the load in 2 instructions and then branches
2281 back to where execution should continue.
2283 GDB should silently step over @FIX code, just like AIX dbx does.
2284 Unfortunately, the linker uses the "b" instruction for the
2285 branches, meaning that the link register doesn't get set.
2286 Therefore, GDB's usual step_over_function () mechanism won't work.
2288 Instead, use the gdbarch_skip_trampoline_code and
2289 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2293 rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2294 CORE_ADDR pc, const char *name)
2296 return name && startswith (name, "@FIX");
2299 /* Skip code that the user doesn't want to see when stepping:
2301 1. Indirect function calls use a piece of trampoline code to do context
2302 switching, i.e. to set the new TOC table. Skip such code if we are on
2303 its first instruction (as when we have single-stepped to here).
2305 2. Skip shared library trampoline code (which is different from
2306 indirect function call trampolines).
2308 3. Skip bigtoc fixup code.
2310 Result is desired PC to step until, or NULL if we are not in
2311 code that should be skipped. */
2314 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
2316 struct gdbarch *gdbarch = get_frame_arch (frame);
2317 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2318 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2319 unsigned int ii, op;
2321 CORE_ADDR solib_target_pc;
2322 struct bound_minimal_symbol msymbol;
2324 static unsigned trampoline_code[] =
2326 0x800b0000, /* l r0,0x0(r11) */
2327 0x90410014, /* st r2,0x14(r1) */
2328 0x7c0903a6, /* mtctr r0 */
2329 0x804b0004, /* l r2,0x4(r11) */
2330 0x816b0008, /* l r11,0x8(r11) */
2331 0x4e800420, /* bctr */
2332 0x4e800020, /* br */
2336 /* Check for bigtoc fixup code. */
2337 msymbol = lookup_minimal_symbol_by_pc (pc);
2339 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2340 MSYMBOL_LINKAGE_NAME (msymbol.minsym)))
2342 /* Double-check that the third instruction from PC is relative "b". */
2343 op = read_memory_integer (pc + 8, 4, byte_order);
2344 if ((op & 0xfc000003) == 0x48000000)
2346 /* Extract bits 6-29 as a signed 24-bit relative word address and
2347 add it to the containing PC. */
2348 rel = ((int)(op << 6) >> 6);
2349 return pc + 8 + rel;
2353 /* If pc is in a shared library trampoline, return its target. */
2354 solib_target_pc = find_solib_trampoline_target (frame, pc);
2355 if (solib_target_pc)
2356 return solib_target_pc;
2358 for (ii = 0; trampoline_code[ii]; ++ii)
2360 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
2361 if (op != trampoline_code[ii])
2364 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
2366 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
2370 /* ISA-specific vector types. */
2372 static struct type *
2373 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2375 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2377 if (!tdep->ppc_builtin_type_vec64)
2379 const struct builtin_type *bt = builtin_type (gdbarch);
2381 /* The type we're building is this: */
2383 union __gdb_builtin_type_vec64
2387 int32_t v2_int32[2];
2388 int16_t v4_int16[4];
2395 t = arch_composite_type (gdbarch,
2396 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2397 append_composite_type_field (t, "uint64", bt->builtin_int64);
2398 append_composite_type_field (t, "v2_float",
2399 init_vector_type (bt->builtin_float, 2));
2400 append_composite_type_field (t, "v2_int32",
2401 init_vector_type (bt->builtin_int32, 2));
2402 append_composite_type_field (t, "v4_int16",
2403 init_vector_type (bt->builtin_int16, 4));
2404 append_composite_type_field (t, "v8_int8",
2405 init_vector_type (bt->builtin_int8, 8));
2407 TYPE_VECTOR (t) = 1;
2408 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2409 tdep->ppc_builtin_type_vec64 = t;
2412 return tdep->ppc_builtin_type_vec64;
2415 /* Vector 128 type. */
2417 static struct type *
2418 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2420 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2422 if (!tdep->ppc_builtin_type_vec128)
2424 const struct builtin_type *bt = builtin_type (gdbarch);
2426 /* The type we're building is this
2428 type = union __ppc_builtin_type_vec128 {
2430 double v2_double[2];
2432 int32_t v4_int32[4];
2433 int16_t v8_int16[8];
2434 int8_t v16_int8[16];
2440 t = arch_composite_type (gdbarch,
2441 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
2442 append_composite_type_field (t, "uint128", bt->builtin_uint128);
2443 append_composite_type_field (t, "v2_double",
2444 init_vector_type (bt->builtin_double, 2));
2445 append_composite_type_field (t, "v4_float",
2446 init_vector_type (bt->builtin_float, 4));
2447 append_composite_type_field (t, "v4_int32",
2448 init_vector_type (bt->builtin_int32, 4));
2449 append_composite_type_field (t, "v8_int16",
2450 init_vector_type (bt->builtin_int16, 8));
2451 append_composite_type_field (t, "v16_int8",
2452 init_vector_type (bt->builtin_int8, 16));
2454 TYPE_VECTOR (t) = 1;
2455 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2456 tdep->ppc_builtin_type_vec128 = t;
2459 return tdep->ppc_builtin_type_vec128;
2462 /* Return the name of register number REGNO, or the empty string if it
2463 is an anonymous register. */
2466 rs6000_register_name (struct gdbarch *gdbarch, int regno)
2468 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2470 /* The upper half "registers" have names in the XML description,
2471 but we present only the low GPRs and the full 64-bit registers
2473 if (tdep->ppc_ev0_upper_regnum >= 0
2474 && tdep->ppc_ev0_upper_regnum <= regno
2475 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2478 /* Hide the upper halves of the vs0~vs31 registers. */
2479 if (tdep->ppc_vsr0_regnum >= 0
2480 && tdep->ppc_vsr0_upper_regnum <= regno
2481 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2484 /* Check if the SPE pseudo registers are available. */
2485 if (IS_SPE_PSEUDOREG (tdep, regno))
2487 static const char *const spe_regnames[] = {
2488 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2489 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2490 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2491 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2493 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2496 /* Check if the decimal128 pseudo-registers are available. */
2497 if (IS_DFP_PSEUDOREG (tdep, regno))
2499 static const char *const dfp128_regnames[] = {
2500 "dl0", "dl1", "dl2", "dl3",
2501 "dl4", "dl5", "dl6", "dl7",
2502 "dl8", "dl9", "dl10", "dl11",
2503 "dl12", "dl13", "dl14", "dl15"
2505 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2508 /* Check if this is a VSX pseudo-register. */
2509 if (IS_VSX_PSEUDOREG (tdep, regno))
2511 static const char *const vsx_regnames[] = {
2512 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2513 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2514 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2515 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2516 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2517 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2518 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2519 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2520 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2522 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2525 /* Check if the this is a Extended FP pseudo-register. */
2526 if (IS_EFP_PSEUDOREG (tdep, regno))
2528 static const char *const efpr_regnames[] = {
2529 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2530 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2531 "f46", "f47", "f48", "f49", "f50", "f51",
2532 "f52", "f53", "f54", "f55", "f56", "f57",
2533 "f58", "f59", "f60", "f61", "f62", "f63"
2535 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2538 return tdesc_register_name (gdbarch, regno);
2541 /* Return the GDB type object for the "standard" data type of data in
2544 static struct type *
2545 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2547 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2549 /* These are the only pseudo-registers we support. */
2550 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2551 || IS_DFP_PSEUDOREG (tdep, regnum)
2552 || IS_VSX_PSEUDOREG (tdep, regnum)
2553 || IS_EFP_PSEUDOREG (tdep, regnum));
2555 /* These are the e500 pseudo-registers. */
2556 if (IS_SPE_PSEUDOREG (tdep, regnum))
2557 return rs6000_builtin_type_vec64 (gdbarch);
2558 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2559 /* PPC decimal128 pseudo-registers. */
2560 return builtin_type (gdbarch)->builtin_declong;
2561 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2562 /* POWER7 VSX pseudo-registers. */
2563 return rs6000_builtin_type_vec128 (gdbarch);
2565 /* POWER7 Extended FP pseudo-registers. */
2566 return builtin_type (gdbarch)->builtin_double;
2569 /* Is REGNUM a member of REGGROUP? */
2571 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2572 struct reggroup *group)
2574 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2576 /* These are the only pseudo-registers we support. */
2577 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2578 || IS_DFP_PSEUDOREG (tdep, regnum)
2579 || IS_VSX_PSEUDOREG (tdep, regnum)
2580 || IS_EFP_PSEUDOREG (tdep, regnum));
2582 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2583 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
2584 return group == all_reggroup || group == vector_reggroup;
2586 /* PPC decimal128 or Extended FP pseudo-registers. */
2587 return group == all_reggroup || group == float_reggroup;
2590 /* The register format for RS/6000 floating point registers is always
2591 double, we need a conversion if the memory format is float. */
2594 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2597 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2599 return (tdep->ppc_fp0_regnum >= 0
2600 && regnum >= tdep->ppc_fp0_regnum
2601 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2602 && TYPE_CODE (type) == TYPE_CODE_FLT
2603 && TYPE_LENGTH (type)
2604 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
2608 rs6000_register_to_value (struct frame_info *frame,
2612 int *optimizedp, int *unavailablep)
2614 struct gdbarch *gdbarch = get_frame_arch (frame);
2615 gdb_byte from[PPC_MAX_REGISTER_SIZE];
2617 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2619 if (!get_frame_register_bytes (frame, regnum, 0,
2620 register_size (gdbarch, regnum),
2621 from, optimizedp, unavailablep))
2624 target_float_convert (from, builtin_type (gdbarch)->builtin_double,
2626 *optimizedp = *unavailablep = 0;
2631 rs6000_value_to_register (struct frame_info *frame,
2634 const gdb_byte *from)
2636 struct gdbarch *gdbarch = get_frame_arch (frame);
2637 gdb_byte to[PPC_MAX_REGISTER_SIZE];
2639 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2641 target_float_convert (from, type,
2642 to, builtin_type (gdbarch)->builtin_double);
2643 put_frame_register (frame, regnum, to);
2646 /* The type of a function that moves the value of REG between CACHE
2647 or BUF --- in either direction. */
2648 typedef enum register_status (*move_ev_register_func) (struct regcache *,
2651 /* Move SPE vector register values between a 64-bit buffer and the two
2652 32-bit raw register halves in a regcache. This function handles
2653 both splitting a 64-bit value into two 32-bit halves, and joining
2654 two halves into a whole 64-bit value, depending on the function
2655 passed as the MOVE argument.
2657 EV_REG must be the number of an SPE evN vector register --- a
2658 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2661 Call MOVE once for each 32-bit half of that register, passing
2662 REGCACHE, the number of the raw register corresponding to that
2663 half, and the address of the appropriate half of BUFFER.
2665 For example, passing 'regcache_raw_read' as the MOVE function will
2666 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2667 'regcache_raw_supply' will supply the contents of BUFFER to the
2668 appropriate pair of raw registers in REGCACHE.
2670 You may need to cast away some 'const' qualifiers when passing
2671 MOVE, since this function can't tell at compile-time which of
2672 REGCACHE or BUFFER is acting as the source of the data. If C had
2673 co-variant type qualifiers, ... */
2675 static enum register_status
2676 e500_move_ev_register (move_ev_register_func move,
2677 struct regcache *regcache, int ev_reg, void *buffer)
2679 struct gdbarch *arch = regcache->arch ();
2680 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2682 gdb_byte *byte_buffer = (gdb_byte *) buffer;
2683 enum register_status status;
2685 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
2687 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2689 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2691 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2693 if (status == REG_VALID)
2694 status = move (regcache, tdep->ppc_gp0_regnum + reg_index,
2699 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2700 if (status == REG_VALID)
2701 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2708 static enum register_status
2709 do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer)
2711 return regcache_raw_read (regcache, regnum, (gdb_byte *) buffer);
2714 static enum register_status
2715 do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer)
2717 regcache_raw_write (regcache, regnum, (const gdb_byte *) buffer);
2722 static enum register_status
2723 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2724 int reg_nr, gdb_byte *buffer)
2726 return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer);
2730 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2731 int reg_nr, const gdb_byte *buffer)
2733 e500_move_ev_register (do_regcache_raw_write, regcache,
2734 reg_nr, (void *) buffer);
2737 /* Read method for DFP pseudo-registers. */
2738 static enum register_status
2739 dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2740 int reg_nr, gdb_byte *buffer)
2742 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2743 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2744 enum register_status status;
2746 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2748 /* Read two FP registers to form a whole dl register. */
2749 status = regcache->raw_read (tdep->ppc_fp0_regnum +
2750 2 * reg_index, buffer);
2751 if (status == REG_VALID)
2752 status = regcache->raw_read (tdep->ppc_fp0_regnum +
2753 2 * reg_index + 1, buffer + 8);
2757 status = regcache->raw_read (tdep->ppc_fp0_regnum +
2758 2 * reg_index + 1, buffer);
2759 if (status == REG_VALID)
2760 status = regcache->raw_read (tdep->ppc_fp0_regnum +
2761 2 * reg_index, buffer + 8);
2767 /* Write method for DFP pseudo-registers. */
2769 dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2770 int reg_nr, const gdb_byte *buffer)
2772 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2773 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2775 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2777 /* Write each half of the dl register into a separate
2779 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2780 2 * reg_index, buffer);
2781 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2782 2 * reg_index + 1, buffer + 8);
2786 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2787 2 * reg_index + 1, buffer);
2788 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2789 2 * reg_index, buffer + 8);
2793 /* Read method for POWER7 VSX pseudo-registers. */
2794 static enum register_status
2795 vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2796 int reg_nr, gdb_byte *buffer)
2798 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2799 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2800 enum register_status status;
2802 /* Read the portion that overlaps the VMX registers. */
2804 status = regcache->raw_read (tdep->ppc_vr0_regnum +
2805 reg_index - 32, buffer);
2807 /* Read the portion that overlaps the FPR registers. */
2808 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2810 status = regcache->raw_read (tdep->ppc_fp0_regnum +
2812 if (status == REG_VALID)
2813 status = regcache->raw_read (tdep->ppc_vsr0_upper_regnum +
2814 reg_index, buffer + 8);
2818 status = regcache->raw_read (tdep->ppc_fp0_regnum +
2819 reg_index, buffer + 8);
2820 if (status == REG_VALID)
2821 status = regcache->raw_read (tdep->ppc_vsr0_upper_regnum +
2828 /* Write method for POWER7 VSX pseudo-registers. */
2830 vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2831 int reg_nr, const gdb_byte *buffer)
2833 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2834 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2836 /* Write the portion that overlaps the VMX registers. */
2838 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2839 reg_index - 32, buffer);
2841 /* Write the portion that overlaps the FPR registers. */
2842 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2844 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2846 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2847 reg_index, buffer + 8);
2851 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2852 reg_index, buffer + 8);
2853 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2858 /* Read method for POWER7 Extended FP pseudo-registers. */
2859 static enum register_status
2860 efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2861 int reg_nr, gdb_byte *buffer)
2863 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2864 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2865 int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8;
2867 /* Read the portion that overlaps the VMX register. */
2868 return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index,
2869 offset, register_size (gdbarch, reg_nr),
2873 /* Write method for POWER7 Extended FP pseudo-registers. */
2875 efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2876 int reg_nr, const gdb_byte *buffer)
2878 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2879 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2880 int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8;
2882 /* Write the portion that overlaps the VMX register. */
2883 regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index,
2884 offset, register_size (gdbarch, reg_nr),
2888 static enum register_status
2889 rs6000_pseudo_register_read (struct gdbarch *gdbarch,
2890 struct regcache *regcache,
2891 int reg_nr, gdb_byte *buffer)
2893 struct gdbarch *regcache_arch = regcache->arch ();
2894 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2896 gdb_assert (regcache_arch == gdbarch);
2898 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2899 return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2900 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2901 return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2902 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2903 return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2904 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2905 return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2907 internal_error (__FILE__, __LINE__,
2908 _("rs6000_pseudo_register_read: "
2909 "called on unexpected register '%s' (%d)"),
2910 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2914 rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2915 struct regcache *regcache,
2916 int reg_nr, const gdb_byte *buffer)
2918 struct gdbarch *regcache_arch = regcache->arch ();
2919 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2921 gdb_assert (regcache_arch == gdbarch);
2923 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2924 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2925 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2926 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2927 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2928 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2929 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2930 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2932 internal_error (__FILE__, __LINE__,
2933 _("rs6000_pseudo_register_write: "
2934 "called on unexpected register '%s' (%d)"),
2935 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2939 rs6000_ax_pseudo_register_collect (struct gdbarch *gdbarch,
2940 struct agent_expr *ax, int reg_nr)
2942 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2943 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2945 int reg_index = reg_nr - tdep->ppc_ev0_regnum;
2946 ax_reg_mask (ax, tdep->ppc_gp0_regnum + reg_index);
2947 ax_reg_mask (ax, tdep->ppc_ev0_upper_regnum + reg_index);
2949 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2951 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2952 ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index);
2953 ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index + 1);
2955 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2957 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2960 ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index - 32);
2964 ax_reg_mask (ax, tdep->ppc_fp0_regnum + reg_index);
2965 ax_reg_mask (ax, tdep->ppc_vsr0_upper_regnum + reg_index);
2968 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2970 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2971 ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index);
2974 internal_error (__FILE__, __LINE__,
2975 _("rs6000_pseudo_register_collect: "
2976 "called on unexpected register '%s' (%d)"),
2977 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2983 rs6000_gen_return_address (struct gdbarch *gdbarch,
2984 struct agent_expr *ax, struct axs_value *value,
2987 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2988 value->type = register_type (gdbarch, tdep->ppc_lr_regnum);
2989 value->kind = axs_lvalue_register;
2990 value->u.reg = tdep->ppc_lr_regnum;
2994 /* Convert a DBX STABS register number to a GDB register number. */
2996 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
2998 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3000 if (0 <= num && num <= 31)
3001 return tdep->ppc_gp0_regnum + num;
3002 else if (32 <= num && num <= 63)
3003 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3004 specifies registers the architecture doesn't have? Our
3005 callers don't check the value we return. */
3006 return tdep->ppc_fp0_regnum + (num - 32);
3007 else if (77 <= num && num <= 108)
3008 return tdep->ppc_vr0_regnum + (num - 77);
3009 else if (1200 <= num && num < 1200 + 32)
3010 return tdep->ppc_ev0_upper_regnum + (num - 1200);
3015 return tdep->ppc_mq_regnum;
3017 return tdep->ppc_lr_regnum;
3019 return tdep->ppc_ctr_regnum;
3021 return tdep->ppc_xer_regnum;
3023 return tdep->ppc_vrsave_regnum;
3025 return tdep->ppc_vrsave_regnum - 1; /* vscr */
3027 return tdep->ppc_acc_regnum;
3029 return tdep->ppc_spefscr_regnum;
3036 /* Convert a Dwarf 2 register number to a GDB register number. */
3038 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
3040 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3042 if (0 <= num && num <= 31)
3043 return tdep->ppc_gp0_regnum + num;
3044 else if (32 <= num && num <= 63)
3045 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3046 specifies registers the architecture doesn't have? Our
3047 callers don't check the value we return. */
3048 return tdep->ppc_fp0_regnum + (num - 32);
3049 else if (1124 <= num && num < 1124 + 32)
3050 return tdep->ppc_vr0_regnum + (num - 1124);
3051 else if (1200 <= num && num < 1200 + 32)
3052 return tdep->ppc_ev0_upper_regnum + (num - 1200);
3057 return tdep->ppc_cr_regnum;
3059 return tdep->ppc_vrsave_regnum - 1; /* vscr */
3061 return tdep->ppc_acc_regnum;
3063 return tdep->ppc_mq_regnum;
3065 return tdep->ppc_xer_regnum;
3067 return tdep->ppc_lr_regnum;
3069 return tdep->ppc_ctr_regnum;
3071 return tdep->ppc_vrsave_regnum;
3073 return tdep->ppc_spefscr_regnum;
3079 /* Translate a .eh_frame register to DWARF register, or adjust a
3080 .debug_frame register. */
3083 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
3085 /* GCC releases before 3.4 use GCC internal register numbering in
3086 .debug_frame (and .debug_info, et cetera). The numbering is
3087 different from the standard SysV numbering for everything except
3088 for GPRs and FPRs. We can not detect this problem in most cases
3089 - to get accurate debug info for variables living in lr, ctr, v0,
3090 et cetera, use a newer version of GCC. But we must detect
3091 one important case - lr is in column 65 in .debug_frame output,
3094 GCC 3.4, and the "hammer" branch, have a related problem. They
3095 record lr register saves in .debug_frame as 108, but still record
3096 the return column as 65. We fix that up too.
3098 We can do this because 65 is assigned to fpsr, and GCC never
3099 generates debug info referring to it. To add support for
3100 handwritten debug info that restores fpsr, we would need to add a
3101 producer version check to this. */
3110 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3111 internal register numbering; translate that to the standard DWARF2
3112 register numbering. */
3113 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
3115 else if (68 <= num && num <= 75) /* cr0-cr8 */
3116 return num - 68 + 86;
3117 else if (77 <= num && num <= 108) /* vr0-vr31 */
3118 return num - 77 + 1124;
3130 case 109: /* vrsave */
3132 case 110: /* vscr */
3134 case 111: /* spe_acc */
3136 case 112: /* spefscr */
3144 /* Handling the various POWER/PowerPC variants. */
3146 /* Information about a particular processor variant. */
3150 /* Name of this variant. */
3153 /* English description of the variant. */
3154 const char *description;
3156 /* bfd_arch_info.arch corresponding to variant. */
3157 enum bfd_architecture arch;
3159 /* bfd_arch_info.mach corresponding to variant. */
3162 /* Target description for this variant. */
3163 struct target_desc **tdesc;
3166 static struct variant variants[] =
3168 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
3169 bfd_mach_ppc, &tdesc_powerpc_altivec32},
3170 {"power", "POWER user-level", bfd_arch_rs6000,
3171 bfd_mach_rs6k, &tdesc_rs6000},
3172 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
3173 bfd_mach_ppc_403, &tdesc_powerpc_403},
3174 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
3175 bfd_mach_ppc_405, &tdesc_powerpc_405},
3176 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
3177 bfd_mach_ppc_601, &tdesc_powerpc_601},
3178 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
3179 bfd_mach_ppc_602, &tdesc_powerpc_602},
3180 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
3181 bfd_mach_ppc_603, &tdesc_powerpc_603},
3182 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
3183 604, &tdesc_powerpc_604},
3184 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
3185 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
3186 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
3187 bfd_mach_ppc_505, &tdesc_powerpc_505},
3188 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
3189 bfd_mach_ppc_860, &tdesc_powerpc_860},
3190 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
3191 bfd_mach_ppc_750, &tdesc_powerpc_750},
3192 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
3193 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
3194 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
3195 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
3198 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
3199 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
3200 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
3201 bfd_mach_ppc_620, &tdesc_powerpc_64},
3202 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
3203 bfd_mach_ppc_630, &tdesc_powerpc_64},
3204 {"a35", "PowerPC A35", bfd_arch_powerpc,
3205 bfd_mach_ppc_a35, &tdesc_powerpc_64},
3206 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
3207 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
3208 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
3209 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
3211 /* FIXME: I haven't checked the register sets of the following. */
3212 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
3213 bfd_mach_rs6k_rs1, &tdesc_rs6000},
3214 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
3215 bfd_mach_rs6k_rsc, &tdesc_rs6000},
3216 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
3217 bfd_mach_rs6k_rs2, &tdesc_rs6000},
3219 {0, 0, (enum bfd_architecture) 0, 0, 0}
3222 /* Return the variant corresponding to architecture ARCH and machine number
3223 MACH. If no such variant exists, return null. */
3225 static const struct variant *
3226 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
3228 const struct variant *v;
3230 for (v = variants; v->name; v++)
3231 if (arch == v->arch && mach == v->mach)
3239 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3241 return frame_unwind_register_unsigned (next_frame,
3242 gdbarch_pc_regnum (gdbarch));
3245 static struct frame_id
3246 rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3248 return frame_id_build (get_frame_register_unsigned
3249 (this_frame, gdbarch_sp_regnum (gdbarch)),
3250 get_frame_pc (this_frame));
3253 struct rs6000_frame_cache
3256 CORE_ADDR initial_sp;
3257 struct trad_frame_saved_reg *saved_regs;
3259 /* Set BASE_P to true if this frame cache is properly initialized.
3260 Otherwise set to false because some registers or memory cannot
3263 /* Cache PC for building unavailable frame. */
3267 static struct rs6000_frame_cache *
3268 rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
3270 struct rs6000_frame_cache *cache;
3271 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3272 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3273 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3274 struct rs6000_framedata fdata;
3275 int wordsize = tdep->wordsize;
3276 CORE_ADDR func = 0, pc = 0;
3278 if ((*this_cache) != NULL)
3279 return (struct rs6000_frame_cache *) (*this_cache);
3280 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3281 (*this_cache) = cache;
3283 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3287 func = get_frame_func (this_frame);
3289 pc = get_frame_pc (this_frame);
3290 skip_prologue (gdbarch, func, pc, &fdata);
3292 /* Figure out the parent's stack pointer. */
3294 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3295 address of the current frame. Things might be easier if the
3296 ->frame pointed to the outer-most address of the frame. In
3297 the mean time, the address of the prev frame is used as the
3298 base address of this frame. */
3299 cache->base = get_frame_register_unsigned
3300 (this_frame, gdbarch_sp_regnum (gdbarch));
3302 CATCH (ex, RETURN_MASK_ERROR)
3304 if (ex.error != NOT_AVAILABLE_ERROR)
3305 throw_exception (ex);
3306 return (struct rs6000_frame_cache *) (*this_cache);
3310 /* If the function appears to be frameless, check a couple of likely
3311 indicators that we have simply failed to find the frame setup.
3312 Two common cases of this are missing symbols (i.e.
3313 get_frame_func returns the wrong address or 0), and assembly
3314 stubs which have a fast exit path but set up a frame on the slow
3317 If the LR appears to return to this function, then presume that
3318 we have an ABI compliant frame that we failed to find. */
3319 if (fdata.frameless && fdata.lr_offset == 0)
3324 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
3325 if (func == 0 && saved_lr == pc)
3329 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3330 if (func == saved_func)
3336 fdata.frameless = 0;
3337 fdata.lr_offset = tdep->lr_frame_offset;
3341 if (!fdata.frameless)
3343 /* Frameless really means stackless. */
3346 if (safe_read_memory_unsigned_integer (cache->base, wordsize,
3347 byte_order, &backchain))
3348 cache->base = (CORE_ADDR) backchain;
3351 trad_frame_set_value (cache->saved_regs,
3352 gdbarch_sp_regnum (gdbarch), cache->base);
3354 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3355 All fpr's from saved_fpr to fp31 are saved. */
3357 if (fdata.saved_fpr >= 0)
3360 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3362 /* If skip_prologue says floating-point registers were saved,
3363 but the current architecture has no floating-point registers,
3364 then that's strange. But we have no indices to even record
3365 the addresses under, so we just ignore it. */
3366 if (ppc_floating_point_unit_p (gdbarch))
3367 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3369 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3374 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3375 All gpr's from saved_gpr to gpr31 are saved (except during the
3378 if (fdata.saved_gpr >= 0)
3381 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3382 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3384 if (fdata.gpr_mask & (1U << i))
3385 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3386 gpr_addr += wordsize;
3390 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3391 All vr's from saved_vr to vr31 are saved. */
3392 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3394 if (fdata.saved_vr >= 0)
3397 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3398 for (i = fdata.saved_vr; i < 32; i++)
3400 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3401 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3406 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3407 All vr's from saved_ev to ev31 are saved. ????? */
3408 if (tdep->ppc_ev0_regnum != -1)
3410 if (fdata.saved_ev >= 0)
3413 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3414 CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0);
3416 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3418 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3419 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off;
3420 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3425 /* If != 0, fdata.cr_offset is the offset from the frame that
3427 if (fdata.cr_offset != 0)
3428 cache->saved_regs[tdep->ppc_cr_regnum].addr
3429 = cache->base + fdata.cr_offset;
3431 /* If != 0, fdata.lr_offset is the offset from the frame that
3433 if (fdata.lr_offset != 0)
3434 cache->saved_regs[tdep->ppc_lr_regnum].addr
3435 = cache->base + fdata.lr_offset;
3436 else if (fdata.lr_register != -1)
3437 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
3438 /* The PC is found in the link register. */
3439 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3440 cache->saved_regs[tdep->ppc_lr_regnum];
3442 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3443 holds the VRSAVE. */
3444 if (fdata.vrsave_offset != 0)
3445 cache->saved_regs[tdep->ppc_vrsave_regnum].addr
3446 = cache->base + fdata.vrsave_offset;
3448 if (fdata.alloca_reg < 0)
3449 /* If no alloca register used, then fi->frame is the value of the
3450 %sp for this frame, and it is good enough. */
3452 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
3455 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
3462 rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
3463 struct frame_id *this_id)
3465 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3470 (*this_id) = frame_id_build_unavailable_stack (info->pc);
3474 /* This marks the outermost frame. */
3475 if (info->base == 0)
3478 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3481 static struct value *
3482 rs6000_frame_prev_register (struct frame_info *this_frame,
3483 void **this_cache, int regnum)
3485 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3487 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3490 static const struct frame_unwind rs6000_frame_unwind =
3493 default_frame_unwind_stop_reason,
3494 rs6000_frame_this_id,
3495 rs6000_frame_prev_register,
3497 default_frame_sniffer
3500 /* Allocate and initialize a frame cache for an epilogue frame.
3501 SP is restored and prev-PC is stored in LR. */
3503 static struct rs6000_frame_cache *
3504 rs6000_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
3506 struct rs6000_frame_cache *cache;
3507 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3508 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3511 return (struct rs6000_frame_cache *) *this_cache;
3513 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3514 (*this_cache) = cache;
3515 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3519 /* At this point the stack looks as if we just entered the
3520 function, and the return address is stored in LR. */
3523 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
3524 lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
3527 cache->initial_sp = sp;
3529 trad_frame_set_value (cache->saved_regs,
3530 gdbarch_pc_regnum (gdbarch), lr);
3532 CATCH (ex, RETURN_MASK_ERROR)
3534 if (ex.error != NOT_AVAILABLE_ERROR)
3535 throw_exception (ex);
3542 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3543 Return the frame ID of an epilogue frame. */
3546 rs6000_epilogue_frame_this_id (struct frame_info *this_frame,
3547 void **this_cache, struct frame_id *this_id)
3550 struct rs6000_frame_cache *info =
3551 rs6000_epilogue_frame_cache (this_frame, this_cache);
3553 pc = get_frame_func (this_frame);
3554 if (info->base == 0)
3555 (*this_id) = frame_id_build_unavailable_stack (pc);
3557 (*this_id) = frame_id_build (info->base, pc);
3560 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3561 Return the register value of REGNUM in previous frame. */
3563 static struct value *
3564 rs6000_epilogue_frame_prev_register (struct frame_info *this_frame,
3565 void **this_cache, int regnum)
3567 struct rs6000_frame_cache *info =
3568 rs6000_epilogue_frame_cache (this_frame, this_cache);
3569 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3572 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3573 Check whether this an epilogue frame. */
3576 rs6000_epilogue_frame_sniffer (const struct frame_unwind *self,
3577 struct frame_info *this_frame,
3578 void **this_prologue_cache)
3580 if (frame_relative_level (this_frame) == 0)
3581 return rs6000_in_function_epilogue_frame_p (this_frame,
3582 get_frame_arch (this_frame),
3583 get_frame_pc (this_frame));
3588 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3589 a function without debug information. */
3591 static const struct frame_unwind rs6000_epilogue_frame_unwind =
3594 default_frame_unwind_stop_reason,
3595 rs6000_epilogue_frame_this_id, rs6000_epilogue_frame_prev_register,
3597 rs6000_epilogue_frame_sniffer
3602 rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
3604 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3606 return info->initial_sp;
3609 static const struct frame_base rs6000_frame_base = {
3610 &rs6000_frame_unwind,
3611 rs6000_frame_base_address,
3612 rs6000_frame_base_address,
3613 rs6000_frame_base_address
3616 static const struct frame_base *
3617 rs6000_frame_base_sniffer (struct frame_info *this_frame)
3619 return &rs6000_frame_base;
3622 /* DWARF-2 frame support. Used to handle the detection of
3623 clobbered registers during function calls. */
3626 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3627 struct dwarf2_frame_state_reg *reg,
3628 struct frame_info *this_frame)
3630 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3632 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3633 non-volatile registers. We will use the same code for both. */
3635 /* Call-saved GP registers. */
3636 if ((regnum >= tdep->ppc_gp0_regnum + 14
3637 && regnum <= tdep->ppc_gp0_regnum + 31)
3638 || (regnum == tdep->ppc_gp0_regnum + 1))
3639 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3641 /* Call-clobbered GP registers. */
3642 if ((regnum >= tdep->ppc_gp0_regnum + 3
3643 && regnum <= tdep->ppc_gp0_regnum + 12)
3644 || (regnum == tdep->ppc_gp0_regnum))
3645 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3647 /* Deal with FP registers, if supported. */
3648 if (tdep->ppc_fp0_regnum >= 0)
3650 /* Call-saved FP registers. */
3651 if ((regnum >= tdep->ppc_fp0_regnum + 14
3652 && regnum <= tdep->ppc_fp0_regnum + 31))
3653 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3655 /* Call-clobbered FP registers. */
3656 if ((regnum >= tdep->ppc_fp0_regnum
3657 && regnum <= tdep->ppc_fp0_regnum + 13))
3658 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3661 /* Deal with ALTIVEC registers, if supported. */
3662 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3664 /* Call-saved Altivec registers. */
3665 if ((regnum >= tdep->ppc_vr0_regnum + 20
3666 && regnum <= tdep->ppc_vr0_regnum + 31)
3667 || regnum == tdep->ppc_vrsave_regnum)
3668 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3670 /* Call-clobbered Altivec registers. */
3671 if ((regnum >= tdep->ppc_vr0_regnum
3672 && regnum <= tdep->ppc_vr0_regnum + 19))
3673 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3676 /* Handle PC register and Stack Pointer correctly. */
3677 if (regnum == gdbarch_pc_regnum (gdbarch))
3678 reg->how = DWARF2_FRAME_REG_RA;
3679 else if (regnum == gdbarch_sp_regnum (gdbarch))
3680 reg->how = DWARF2_FRAME_REG_CFA;
3684 /* Return true if a .gnu_attributes section exists in BFD and it
3685 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3686 section exists in BFD and it indicates that SPE extensions are in
3687 use. Check the .gnu.attributes section first, as the binary might be
3688 compiled for SPE, but not actually using SPE instructions. */
3691 bfd_uses_spe_extensions (bfd *abfd)
3694 gdb_byte *contents = NULL;
3704 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3705 could be using the SPE vector abi without actually using any spe
3706 bits whatsoever. But it's close enough for now. */
3707 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3708 Tag_GNU_Power_ABI_Vector);
3709 if (vector_abi == 3)
3713 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3717 size = bfd_get_section_size (sect);
3718 contents = (gdb_byte *) xmalloc (size);
3719 if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3725 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3731 char name[name_len rounded up to 4-byte alignment];
3732 char data[data_len];
3735 Technically, there's only supposed to be one such structure in a
3736 given apuinfo section, but the linker is not always vigilant about
3737 merging apuinfo sections from input files. Just go ahead and parse
3738 them all, exiting early when we discover the binary uses SPE
3741 It's not specified in what endianness the information in this
3742 section is stored. Assume that it's the endianness of the BFD. */
3746 unsigned int name_len;
3747 unsigned int data_len;
3750 /* If we can't read the first three fields, we're done. */
3754 name_len = bfd_get_32 (abfd, ptr);
3755 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3756 data_len = bfd_get_32 (abfd, ptr + 4);
3757 type = bfd_get_32 (abfd, ptr + 8);
3760 /* The name must be "APUinfo\0". */
3762 && strcmp ((const char *) ptr, "APUinfo") != 0)
3766 /* The type must be 2. */
3770 /* The data is stored as a series of uint32. The upper half of
3771 each uint32 indicates the particular APU used and the lower
3772 half indicates the revision of that APU. We just care about
3775 /* Not 4-byte quantities. */
3781 unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3782 unsigned int apu = apuinfo >> 16;
3786 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3788 if (apu == 0x100 || apu == 0x101)
3803 /* These are macros for parsing instruction fields (I.1.6.28) */
3805 #define PPC_FIELD(value, from, len) \
3806 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3807 #define PPC_SEXT(v, bs) \
3808 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3809 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3810 - ((CORE_ADDR) 1 << ((bs) - 1)))
3811 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3812 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3813 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3814 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3815 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3816 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3817 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3818 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3819 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3820 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3821 | (PPC_FIELD (insn, 16, 5) << 5))
3822 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3823 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3824 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3825 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3826 #define PPC_DQ(insn) PPC_SEXT (PPC_FIELD (insn, 16, 12), 12)
3827 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3828 #define PPC_OE(insn) PPC_BIT (insn, 21)
3829 #define PPC_RC(insn) PPC_BIT (insn, 31)
3830 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3831 #define PPC_LK(insn) PPC_BIT (insn, 31)
3832 #define PPC_TX(insn) PPC_BIT (insn, 31)
3833 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3835 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3836 #define PPC_XER_NB(xer) (xer & 0x7f)
3838 /* Record Vector-Scalar Registers.
3839 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3840 Otherwise, it's just a VR register. Record them accordingly. */
3843 ppc_record_vsr (struct regcache *regcache, struct gdbarch_tdep *tdep, int vsr)
3845 if (vsr < 0 || vsr >= 64)
3850 if (tdep->ppc_vr0_regnum >= 0)
3851 record_full_arch_list_add_reg (regcache, tdep->ppc_vr0_regnum + vsr - 32);
3855 if (tdep->ppc_fp0_regnum >= 0)
3856 record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum + vsr);
3857 if (tdep->ppc_vsr0_upper_regnum >= 0)
3858 record_full_arch_list_add_reg (regcache,
3859 tdep->ppc_vsr0_upper_regnum + vsr);
3865 /* Parse and record instructions primary opcode-4 at ADDR.
3866 Return 0 if successful. */
3869 ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
3870 CORE_ADDR addr, uint32_t insn)
3872 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3873 int ext = PPC_FIELD (insn, 21, 11);
3874 int vra = PPC_FIELD (insn, 11, 5);
3878 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3879 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3880 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3881 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3882 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
3884 case 42: /* Vector Select */
3885 case 43: /* Vector Permute */
3886 case 59: /* Vector Permute Right-indexed */
3887 case 44: /* Vector Shift Left Double by Octet Immediate */
3888 case 45: /* Vector Permute and Exclusive-OR */
3889 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3890 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3891 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3892 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3893 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3894 case 35: /* Vector Multiply-Sum Unsigned Doubleword Modulo */
3895 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3896 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3897 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3898 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3899 case 46: /* Vector Multiply-Add Single-Precision */
3900 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3901 record_full_arch_list_add_reg (regcache,
3902 tdep->ppc_vr0_regnum + PPC_VRT (insn));
3905 case 48: /* Multiply-Add High Doubleword */
3906 case 49: /* Multiply-Add High Doubleword Unsigned */
3907 case 51: /* Multiply-Add Low Doubleword */
3908 record_full_arch_list_add_reg (regcache,
3909 tdep->ppc_gp0_regnum + PPC_RT (insn));
3913 switch ((ext & 0x1ff))
3916 if (vra != 0 /* Decimal Convert To Signed Quadword */
3917 && vra != 2 /* Decimal Convert From Signed Quadword */
3918 && vra != 4 /* Decimal Convert To Zoned */
3919 && vra != 5 /* Decimal Convert To National */
3920 && vra != 6 /* Decimal Convert From Zoned */
3921 && vra != 7 /* Decimal Convert From National */
3922 && vra != 31) /* Decimal Set Sign */
3924 /* 5.16 Decimal Integer Arithmetic Instructions */
3925 case 1: /* Decimal Add Modulo */
3926 case 65: /* Decimal Subtract Modulo */
3928 case 193: /* Decimal Shift */
3929 case 129: /* Decimal Unsigned Shift */
3930 case 449: /* Decimal Shift and Round */
3932 case 257: /* Decimal Truncate */
3933 case 321: /* Decimal Unsigned Truncate */
3935 /* Bit-21 should be set. */
3936 if (!PPC_BIT (insn, 21))
3939 record_full_arch_list_add_reg (regcache,
3940 tdep->ppc_vr0_regnum + PPC_VRT (insn));
3941 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
3945 /* Bit-21 is used for RC */
3946 switch (ext & 0x3ff)
3948 case 6: /* Vector Compare Equal To Unsigned Byte */
3949 case 70: /* Vector Compare Equal To Unsigned Halfword */
3950 case 134: /* Vector Compare Equal To Unsigned Word */
3951 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3952 case 774: /* Vector Compare Greater Than Signed Byte */
3953 case 838: /* Vector Compare Greater Than Signed Halfword */
3954 case 902: /* Vector Compare Greater Than Signed Word */
3955 case 967: /* Vector Compare Greater Than Signed Doubleword */
3956 case 518: /* Vector Compare Greater Than Unsigned Byte */
3957 case 646: /* Vector Compare Greater Than Unsigned Word */
3958 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3959 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3960 case 966: /* Vector Compare Bounds Single-Precision */
3961 case 198: /* Vector Compare Equal To Single-Precision */
3962 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3963 case 710: /* Vector Compare Greater Than Single-Precision */
3964 case 7: /* Vector Compare Not Equal Byte */
3965 case 71: /* Vector Compare Not Equal Halfword */
3966 case 135: /* Vector Compare Not Equal Word */
3967 case 263: /* Vector Compare Not Equal or Zero Byte */
3968 case 327: /* Vector Compare Not Equal or Zero Halfword */
3969 case 391: /* Vector Compare Not Equal or Zero Word */
3971 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
3972 record_full_arch_list_add_reg (regcache,
3973 tdep->ppc_vr0_regnum + PPC_VRT (insn));
3981 case 0: /* Vector Count Leading Zero Least-Significant Bits
3983 case 1: /* Vector Count Trailing Zero Least-Significant Bits
3985 record_full_arch_list_add_reg (regcache,
3986 tdep->ppc_gp0_regnum + PPC_RT (insn));
3989 case 6: /* Vector Negate Word */
3990 case 7: /* Vector Negate Doubleword */
3991 case 8: /* Vector Parity Byte Word */
3992 case 9: /* Vector Parity Byte Doubleword */
3993 case 10: /* Vector Parity Byte Quadword */
3994 case 16: /* Vector Extend Sign Byte To Word */
3995 case 17: /* Vector Extend Sign Halfword To Word */
3996 case 24: /* Vector Extend Sign Byte To Doubleword */
3997 case 25: /* Vector Extend Sign Halfword To Doubleword */
3998 case 26: /* Vector Extend Sign Word To Doubleword */
3999 case 28: /* Vector Count Trailing Zeros Byte */
4000 case 29: /* Vector Count Trailing Zeros Halfword */
4001 case 30: /* Vector Count Trailing Zeros Word */
4002 case 31: /* Vector Count Trailing Zeros Doubleword */
4003 record_full_arch_list_add_reg (regcache,
4004 tdep->ppc_vr0_regnum + PPC_VRT (insn));
4011 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
4012 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
4013 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
4014 case 334: /* Vector Pack Signed Word Unsigned Saturate */
4015 case 398: /* Vector Pack Signed Halfword Signed Saturate */
4016 case 462: /* Vector Pack Signed Word Signed Saturate */
4017 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
4018 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
4019 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
4020 case 512: /* Vector Add Unsigned Byte Saturate */
4021 case 576: /* Vector Add Unsigned Halfword Saturate */
4022 case 640: /* Vector Add Unsigned Word Saturate */
4023 case 768: /* Vector Add Signed Byte Saturate */
4024 case 832: /* Vector Add Signed Halfword Saturate */
4025 case 896: /* Vector Add Signed Word Saturate */
4026 case 1536: /* Vector Subtract Unsigned Byte Saturate */
4027 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
4028 case 1664: /* Vector Subtract Unsigned Word Saturate */
4029 case 1792: /* Vector Subtract Signed Byte Saturate */
4030 case 1856: /* Vector Subtract Signed Halfword Saturate */
4031 case 1920: /* Vector Subtract Signed Word Saturate */
4033 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
4034 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
4035 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
4036 case 1672: /* Vector Sum across Half Signed Word Saturate */
4037 case 1928: /* Vector Sum across Signed Word Saturate */
4038 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
4039 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
4040 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
4042 case 12: /* Vector Merge High Byte */
4043 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
4044 case 76: /* Vector Merge High Halfword */
4045 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
4046 case 140: /* Vector Merge High Word */
4047 case 268: /* Vector Merge Low Byte */
4048 case 332: /* Vector Merge Low Halfword */
4049 case 396: /* Vector Merge Low Word */
4050 case 526: /* Vector Unpack High Signed Byte */
4051 case 590: /* Vector Unpack High Signed Halfword */
4052 case 654: /* Vector Unpack Low Signed Byte */
4053 case 718: /* Vector Unpack Low Signed Halfword */
4054 case 782: /* Vector Pack Pixel */
4055 case 846: /* Vector Unpack High Pixel */
4056 case 974: /* Vector Unpack Low Pixel */
4057 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
4058 case 1614: /* Vector Unpack High Signed Word */
4059 case 1676: /* Vector Merge Odd Word */
4060 case 1742: /* Vector Unpack Low Signed Word */
4061 case 1932: /* Vector Merge Even Word */
4062 case 524: /* Vector Splat Byte */
4063 case 588: /* Vector Splat Halfword */
4064 case 652: /* Vector Splat Word */
4065 case 780: /* Vector Splat Immediate Signed Byte */
4066 case 844: /* Vector Splat Immediate Signed Halfword */
4067 case 908: /* Vector Splat Immediate Signed Word */
4068 case 452: /* Vector Shift Left */
4069 case 708: /* Vector Shift Right */
4070 case 1036: /* Vector Shift Left by Octet */
4071 case 1100: /* Vector Shift Right by Octet */
4072 case 0: /* Vector Add Unsigned Byte Modulo */
4073 case 64: /* Vector Add Unsigned Halfword Modulo */
4074 case 128: /* Vector Add Unsigned Word Modulo */
4075 case 192: /* Vector Add Unsigned Doubleword Modulo */
4076 case 256: /* Vector Add Unsigned Quadword Modulo */
4077 case 320: /* Vector Add & write Carry Unsigned Quadword */
4078 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4079 case 8: /* Vector Multiply Odd Unsigned Byte */
4080 case 72: /* Vector Multiply Odd Unsigned Halfword */
4081 case 136: /* Vector Multiply Odd Unsigned Word */
4082 case 264: /* Vector Multiply Odd Signed Byte */
4083 case 328: /* Vector Multiply Odd Signed Halfword */
4084 case 392: /* Vector Multiply Odd Signed Word */
4085 case 520: /* Vector Multiply Even Unsigned Byte */
4086 case 584: /* Vector Multiply Even Unsigned Halfword */
4087 case 648: /* Vector Multiply Even Unsigned Word */
4088 case 776: /* Vector Multiply Even Signed Byte */
4089 case 840: /* Vector Multiply Even Signed Halfword */
4090 case 904: /* Vector Multiply Even Signed Word */
4091 case 137: /* Vector Multiply Unsigned Word Modulo */
4092 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4093 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4094 case 1152: /* Vector Subtract Unsigned Word Modulo */
4095 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4096 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4097 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4098 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4099 case 1282: /* Vector Average Signed Byte */
4100 case 1346: /* Vector Average Signed Halfword */
4101 case 1410: /* Vector Average Signed Word */
4102 case 1026: /* Vector Average Unsigned Byte */
4103 case 1090: /* Vector Average Unsigned Halfword */
4104 case 1154: /* Vector Average Unsigned Word */
4105 case 258: /* Vector Maximum Signed Byte */
4106 case 322: /* Vector Maximum Signed Halfword */
4107 case 386: /* Vector Maximum Signed Word */
4108 case 450: /* Vector Maximum Signed Doubleword */
4109 case 2: /* Vector Maximum Unsigned Byte */
4110 case 66: /* Vector Maximum Unsigned Halfword */
4111 case 130: /* Vector Maximum Unsigned Word */
4112 case 194: /* Vector Maximum Unsigned Doubleword */
4113 case 770: /* Vector Minimum Signed Byte */
4114 case 834: /* Vector Minimum Signed Halfword */
4115 case 898: /* Vector Minimum Signed Word */
4116 case 962: /* Vector Minimum Signed Doubleword */
4117 case 514: /* Vector Minimum Unsigned Byte */
4118 case 578: /* Vector Minimum Unsigned Halfword */
4119 case 642: /* Vector Minimum Unsigned Word */
4120 case 706: /* Vector Minimum Unsigned Doubleword */
4121 case 1028: /* Vector Logical AND */
4122 case 1668: /* Vector Logical Equivalent */
4123 case 1092: /* Vector Logical AND with Complement */
4124 case 1412: /* Vector Logical NAND */
4125 case 1348: /* Vector Logical OR with Complement */
4126 case 1156: /* Vector Logical OR */
4127 case 1284: /* Vector Logical NOR */
4128 case 1220: /* Vector Logical XOR */
4129 case 4: /* Vector Rotate Left Byte */
4130 case 132: /* Vector Rotate Left Word VX-form */
4131 case 68: /* Vector Rotate Left Halfword */
4132 case 196: /* Vector Rotate Left Doubleword */
4133 case 260: /* Vector Shift Left Byte */
4134 case 388: /* Vector Shift Left Word */
4135 case 324: /* Vector Shift Left Halfword */
4136 case 1476: /* Vector Shift Left Doubleword */
4137 case 516: /* Vector Shift Right Byte */
4138 case 644: /* Vector Shift Right Word */
4139 case 580: /* Vector Shift Right Halfword */
4140 case 1732: /* Vector Shift Right Doubleword */
4141 case 772: /* Vector Shift Right Algebraic Byte */
4142 case 900: /* Vector Shift Right Algebraic Word */
4143 case 836: /* Vector Shift Right Algebraic Halfword */
4144 case 964: /* Vector Shift Right Algebraic Doubleword */
4145 case 10: /* Vector Add Single-Precision */
4146 case 74: /* Vector Subtract Single-Precision */
4147 case 1034: /* Vector Maximum Single-Precision */
4148 case 1098: /* Vector Minimum Single-Precision */
4149 case 842: /* Vector Convert From Signed Fixed-Point Word */
4150 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4151 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4152 case 522: /* Vector Round to Single-Precision Integer Nearest */
4153 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4154 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4155 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4156 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4157 case 266: /* Vector Reciprocal Estimate Single-Precision */
4158 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4159 case 1288: /* Vector AES Cipher */
4160 case 1289: /* Vector AES Cipher Last */
4161 case 1352: /* Vector AES Inverse Cipher */
4162 case 1353: /* Vector AES Inverse Cipher Last */
4163 case 1480: /* Vector AES SubBytes */
4164 case 1730: /* Vector SHA-512 Sigma Doubleword */
4165 case 1666: /* Vector SHA-256 Sigma Word */
4166 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4167 case 1160: /* Vector Polynomial Multiply-Sum Word */
4168 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4169 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4170 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4171 case 1794: /* Vector Count Leading Zeros Byte */
4172 case 1858: /* Vector Count Leading Zeros Halfword */
4173 case 1922: /* Vector Count Leading Zeros Word */
4174 case 1986: /* Vector Count Leading Zeros Doubleword */
4175 case 1795: /* Vector Population Count Byte */
4176 case 1859: /* Vector Population Count Halfword */
4177 case 1923: /* Vector Population Count Word */
4178 case 1987: /* Vector Population Count Doubleword */
4179 case 1356: /* Vector Bit Permute Quadword */
4180 case 1484: /* Vector Bit Permute Doubleword */
4181 case 513: /* Vector Multiply-by-10 Unsigned Quadword */
4182 case 1: /* Vector Multiply-by-10 & write Carry Unsigned
4184 case 577: /* Vector Multiply-by-10 Extended Unsigned Quadword */
4185 case 65: /* Vector Multiply-by-10 Extended & write Carry
4186 Unsigned Quadword */
4187 case 1027: /* Vector Absolute Difference Unsigned Byte */
4188 case 1091: /* Vector Absolute Difference Unsigned Halfword */
4189 case 1155: /* Vector Absolute Difference Unsigned Word */
4190 case 1796: /* Vector Shift Right Variable */
4191 case 1860: /* Vector Shift Left Variable */
4192 case 133: /* Vector Rotate Left Word then Mask Insert */
4193 case 197: /* Vector Rotate Left Doubleword then Mask Insert */
4194 case 389: /* Vector Rotate Left Word then AND with Mask */
4195 case 453: /* Vector Rotate Left Doubleword then AND with Mask */
4196 case 525: /* Vector Extract Unsigned Byte */
4197 case 589: /* Vector Extract Unsigned Halfword */
4198 case 653: /* Vector Extract Unsigned Word */
4199 case 717: /* Vector Extract Doubleword */
4200 case 781: /* Vector Insert Byte */
4201 case 845: /* Vector Insert Halfword */
4202 case 909: /* Vector Insert Word */
4203 case 973: /* Vector Insert Doubleword */
4204 record_full_arch_list_add_reg (regcache,
4205 tdep->ppc_vr0_regnum + PPC_VRT (insn));
4208 case 1549: /* Vector Extract Unsigned Byte Left-Indexed */
4209 case 1613: /* Vector Extract Unsigned Halfword Left-Indexed */
4210 case 1677: /* Vector Extract Unsigned Word Left-Indexed */
4211 case 1805: /* Vector Extract Unsigned Byte Right-Indexed */
4212 case 1869: /* Vector Extract Unsigned Halfword Right-Indexed */
4213 case 1933: /* Vector Extract Unsigned Word Right-Indexed */
4214 record_full_arch_list_add_reg (regcache,
4215 tdep->ppc_gp0_regnum + PPC_RT (insn));
4218 case 1604: /* Move To Vector Status and Control Register */
4219 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
4221 case 1540: /* Move From Vector Status and Control Register */
4222 record_full_arch_list_add_reg (regcache,
4223 tdep->ppc_vr0_regnum + PPC_VRT (insn));
4225 case 833: /* Decimal Copy Sign */
4226 record_full_arch_list_add_reg (regcache,
4227 tdep->ppc_vr0_regnum + PPC_VRT (insn));
4228 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4232 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4233 "at %s, 4-%d.\n", insn, paddress (gdbarch, addr), ext);
4237 /* Parse and record instructions of primary opcode-19 at ADDR.
4238 Return 0 if successful. */
4241 ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache,
4242 CORE_ADDR addr, uint32_t insn)
4244 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4245 int ext = PPC_EXTOP (insn);
4247 switch (ext & 0x01f)
4249 case 2: /* Add PC Immediate Shifted */
4250 record_full_arch_list_add_reg (regcache,
4251 tdep->ppc_gp0_regnum + PPC_RT (insn));
4257 case 0: /* Move Condition Register Field */
4258 case 33: /* Condition Register NOR */
4259 case 129: /* Condition Register AND with Complement */
4260 case 193: /* Condition Register XOR */
4261 case 225: /* Condition Register NAND */
4262 case 257: /* Condition Register AND */
4263 case 289: /* Condition Register Equivalent */
4264 case 417: /* Condition Register OR with Complement */
4265 case 449: /* Condition Register OR */
4266 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4269 case 16: /* Branch Conditional */
4270 case 560: /* Branch Conditional to Branch Target Address Register */
4271 if ((PPC_BO (insn) & 0x4) == 0)
4272 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum);
4274 case 528: /* Branch Conditional to Count Register */
4276 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
4279 case 150: /* Instruction Synchronize */
4284 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4285 "at %s, 19-%d.\n", insn, paddress (gdbarch, addr), ext);
4289 /* Parse and record instructions of primary opcode-31 at ADDR.
4290 Return 0 if successful. */
4293 ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
4294 CORE_ADDR addr, uint32_t insn)
4296 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4297 int ext = PPC_EXTOP (insn);
4299 CORE_ADDR at_dcsz, ea = 0;
4300 ULONGEST rb, ra, xer;
4303 /* These instructions have OE bit. */
4304 switch (ext & 0x1ff)
4306 /* These write RT and XER. Update CR if RC is set. */
4307 case 8: /* Subtract from carrying */
4308 case 10: /* Add carrying */
4309 case 136: /* Subtract from extended */
4310 case 138: /* Add extended */
4311 case 200: /* Subtract from zero extended */
4312 case 202: /* Add to zero extended */
4313 case 232: /* Subtract from minus one extended */
4314 case 234: /* Add to minus one extended */
4315 /* CA is always altered, but SO/OV are only altered when OE=1.
4316 In any case, XER is always altered. */
4317 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4319 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4320 record_full_arch_list_add_reg (regcache,
4321 tdep->ppc_gp0_regnum + PPC_RT (insn));
4324 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4325 case 40: /* Subtract from */
4326 case 104: /* Negate */
4327 case 233: /* Multiply low doubleword */
4328 case 235: /* Multiply low word */
4330 case 393: /* Divide Doubleword Extended Unsigned */
4331 case 395: /* Divide Word Extended Unsigned */
4332 case 425: /* Divide Doubleword Extended */
4333 case 427: /* Divide Word Extended */
4334 case 457: /* Divide Doubleword Unsigned */
4335 case 459: /* Divide Word Unsigned */
4336 case 489: /* Divide Doubleword */
4337 case 491: /* Divide Word */
4339 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4341 case 9: /* Multiply High Doubleword Unsigned */
4342 case 11: /* Multiply High Word Unsigned */
4343 case 73: /* Multiply High Doubleword */
4344 case 75: /* Multiply High Word */
4346 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4347 record_full_arch_list_add_reg (regcache,
4348 tdep->ppc_gp0_regnum + PPC_RT (insn));
4352 if ((ext & 0x1f) == 15)
4354 /* Integer Select. bit[16:20] is used for BC. */
4355 record_full_arch_list_add_reg (regcache,
4356 tdep->ppc_gp0_regnum + PPC_RT (insn));
4360 if ((ext & 0xff) == 170)
4362 /* Add Extended using alternate carry bits */
4363 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4364 record_full_arch_list_add_reg (regcache,
4365 tdep->ppc_gp0_regnum + PPC_RT (insn));
4371 case 78: /* Determine Leftmost Zero Byte */
4373 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4374 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4375 record_full_arch_list_add_reg (regcache,
4376 tdep->ppc_gp0_regnum + PPC_RT (insn));
4379 /* These only write RT. */
4380 case 19: /* Move from condition register */
4381 /* Move From One Condition Register Field */
4382 case 74: /* Add and Generate Sixes */
4383 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4384 case 302: /* Move From Branch History Rolling Buffer */
4385 case 339: /* Move From Special Purpose Register */
4386 case 371: /* Move From Time Base [Phased-Out] */
4387 case 309: /* Load Doubleword Monitored Indexed */
4388 case 128: /* Set Boolean */
4389 case 755: /* Deliver A Random Number */
4390 record_full_arch_list_add_reg (regcache,
4391 tdep->ppc_gp0_regnum + PPC_RT (insn));
4394 /* These only write to RA. */
4395 case 51: /* Move From VSR Doubleword */
4396 case 115: /* Move From VSR Word and Zero */
4397 case 122: /* Population count bytes */
4398 case 378: /* Population count words */
4399 case 506: /* Population count doublewords */
4400 case 154: /* Parity Word */
4401 case 186: /* Parity Doubleword */
4402 case 252: /* Bit Permute Doubleword */
4403 case 282: /* Convert Declets To Binary Coded Decimal */
4404 case 314: /* Convert Binary Coded Decimal To Declets */
4405 case 508: /* Compare bytes */
4406 case 307: /* Move From VSR Lower Doubleword */
4407 record_full_arch_list_add_reg (regcache,
4408 tdep->ppc_gp0_regnum + PPC_RA (insn));
4411 /* These write CR and optional RA. */
4412 case 792: /* Shift Right Algebraic Word */
4413 case 794: /* Shift Right Algebraic Doubleword */
4414 case 824: /* Shift Right Algebraic Word Immediate */
4415 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4416 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4417 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4418 record_full_arch_list_add_reg (regcache,
4419 tdep->ppc_gp0_regnum + PPC_RA (insn));
4421 case 0: /* Compare */
4422 case 32: /* Compare logical */
4423 case 144: /* Move To Condition Register Fields */
4424 /* Move To One Condition Register Field */
4425 case 192: /* Compare Ranged Byte */
4426 case 224: /* Compare Equal Byte */
4427 case 576: /* Move XER to CR Extended */
4428 case 902: /* Paste (should always fail due to single-stepping and
4429 the memory location might not be accessible, so
4431 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4434 /* These write to RT. Update RA if 'update indexed.' */
4435 case 53: /* Load Doubleword with Update Indexed */
4436 case 119: /* Load Byte and Zero with Update Indexed */
4437 case 311: /* Load Halfword and Zero with Update Indexed */
4438 case 55: /* Load Word and Zero with Update Indexed */
4439 case 375: /* Load Halfword Algebraic with Update Indexed */
4440 case 373: /* Load Word Algebraic with Update Indexed */
4441 record_full_arch_list_add_reg (regcache,
4442 tdep->ppc_gp0_regnum + PPC_RA (insn));
4444 case 21: /* Load Doubleword Indexed */
4445 case 52: /* Load Byte And Reserve Indexed */
4446 case 116: /* Load Halfword And Reserve Indexed */
4447 case 20: /* Load Word And Reserve Indexed */
4448 case 84: /* Load Doubleword And Reserve Indexed */
4449 case 87: /* Load Byte and Zero Indexed */
4450 case 279: /* Load Halfword and Zero Indexed */
4451 case 23: /* Load Word and Zero Indexed */
4452 case 343: /* Load Halfword Algebraic Indexed */
4453 case 341: /* Load Word Algebraic Indexed */
4454 case 790: /* Load Halfword Byte-Reverse Indexed */
4455 case 534: /* Load Word Byte-Reverse Indexed */
4456 case 532: /* Load Doubleword Byte-Reverse Indexed */
4457 case 582: /* Load Word Atomic */
4458 case 614: /* Load Doubleword Atomic */
4459 case 265: /* Modulo Unsigned Doubleword */
4460 case 777: /* Modulo Signed Doubleword */
4461 case 267: /* Modulo Unsigned Word */
4462 case 779: /* Modulo Signed Word */
4463 record_full_arch_list_add_reg (regcache,
4464 tdep->ppc_gp0_regnum + PPC_RT (insn));
4467 case 597: /* Load String Word Immediate */
4468 case 533: /* Load String Word Indexed */
4477 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer);
4478 nr = PPC_XER_NB (xer);
4483 /* If n=0, the contents of register RT are undefined. */
4487 for (i = 0; i < nr; i++)
4488 record_full_arch_list_add_reg (regcache,
4489 tdep->ppc_gp0_regnum
4490 + ((PPC_RT (insn) + i) & 0x1f));
4493 case 276: /* Load Quadword And Reserve Indexed */
4494 tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1);
4495 record_full_arch_list_add_reg (regcache, tmp);
4496 record_full_arch_list_add_reg (regcache, tmp + 1);
4499 /* These write VRT. */
4500 case 6: /* Load Vector for Shift Left Indexed */
4501 case 38: /* Load Vector for Shift Right Indexed */
4502 case 7: /* Load Vector Element Byte Indexed */
4503 case 39: /* Load Vector Element Halfword Indexed */
4504 case 71: /* Load Vector Element Word Indexed */
4505 case 103: /* Load Vector Indexed */
4506 case 359: /* Load Vector Indexed LRU */
4507 record_full_arch_list_add_reg (regcache,
4508 tdep->ppc_vr0_regnum + PPC_VRT (insn));
4511 /* These write FRT. Update RA if 'update indexed.' */
4512 case 567: /* Load Floating-Point Single with Update Indexed */
4513 case 631: /* Load Floating-Point Double with Update Indexed */
4514 record_full_arch_list_add_reg (regcache,
4515 tdep->ppc_gp0_regnum + PPC_RA (insn));
4517 case 535: /* Load Floating-Point Single Indexed */
4518 case 599: /* Load Floating-Point Double Indexed */
4519 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4520 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4521 record_full_arch_list_add_reg (regcache,
4522 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4525 case 791: /* Load Floating-Point Double Pair Indexed */
4526 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
4527 record_full_arch_list_add_reg (regcache, tmp);
4528 record_full_arch_list_add_reg (regcache, tmp + 1);
4531 case 179: /* Move To VSR Doubleword */
4532 case 211: /* Move To VSR Word Algebraic */
4533 case 243: /* Move To VSR Word and Zero */
4534 case 588: /* Load VSX Scalar Doubleword Indexed */
4535 case 524: /* Load VSX Scalar Single-Precision Indexed */
4536 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4537 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4538 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4539 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4540 case 780: /* Load VSX Vector Word*4 Indexed */
4541 case 268: /* Load VSX Vector Indexed */
4542 case 364: /* Load VSX Vector Word & Splat Indexed */
4543 case 812: /* Load VSX Vector Halfword*8 Indexed */
4544 case 876: /* Load VSX Vector Byte*16 Indexed */
4545 case 269: /* Load VSX Vector with Length */
4546 case 301: /* Load VSX Vector Left-justified with Length */
4547 case 781: /* Load VSX Scalar as Integer Byte & Zero Indexed */
4548 case 813: /* Load VSX Scalar as Integer Halfword & Zero Indexed */
4549 case 403: /* Move To VSR Word & Splat */
4550 case 435: /* Move To VSR Double Doubleword */
4551 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
4554 /* These write RA. Update CR if RC is set. */
4555 case 24: /* Shift Left Word */
4556 case 26: /* Count Leading Zeros Word */
4557 case 27: /* Shift Left Doubleword */
4559 case 58: /* Count Leading Zeros Doubleword */
4560 case 60: /* AND with Complement */
4562 case 284: /* Equivalent */
4564 case 476: /* NAND */
4565 case 412: /* OR with Complement */
4567 case 536: /* Shift Right Word */
4568 case 539: /* Shift Right Doubleword */
4569 case 922: /* Extend Sign Halfword */
4570 case 954: /* Extend Sign Byte */
4571 case 986: /* Extend Sign Word */
4572 case 538: /* Count Trailing Zeros Word */
4573 case 570: /* Count Trailing Zeros Doubleword */
4574 case 890: /* Extend-Sign Word and Shift Left Immediate (445) */
4575 case 890 | 1: /* Extend-Sign Word and Shift Left Immediate (445) */
4577 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4578 record_full_arch_list_add_reg (regcache,
4579 tdep->ppc_gp0_regnum + PPC_RA (insn));
4583 case 181: /* Store Doubleword with Update Indexed */
4584 case 183: /* Store Word with Update Indexed */
4585 case 247: /* Store Byte with Update Indexed */
4586 case 439: /* Store Half Word with Update Indexed */
4587 case 695: /* Store Floating-Point Single with Update Indexed */
4588 case 759: /* Store Floating-Point Double with Update Indexed */
4589 record_full_arch_list_add_reg (regcache,
4590 tdep->ppc_gp0_regnum + PPC_RA (insn));
4592 case 135: /* Store Vector Element Byte Indexed */
4593 case 167: /* Store Vector Element Halfword Indexed */
4594 case 199: /* Store Vector Element Word Indexed */
4595 case 231: /* Store Vector Indexed */
4596 case 487: /* Store Vector Indexed LRU */
4597 case 716: /* Store VSX Scalar Doubleword Indexed */
4598 case 140: /* Store VSX Scalar as Integer Word Indexed */
4599 case 652: /* Store VSX Scalar Single-Precision Indexed */
4600 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4601 case 908: /* Store VSX Vector Word*4 Indexed */
4602 case 149: /* Store Doubleword Indexed */
4603 case 151: /* Store Word Indexed */
4604 case 215: /* Store Byte Indexed */
4605 case 407: /* Store Half Word Indexed */
4606 case 694: /* Store Byte Conditional Indexed */
4607 case 726: /* Store Halfword Conditional Indexed */
4608 case 150: /* Store Word Conditional Indexed */
4609 case 214: /* Store Doubleword Conditional Indexed */
4610 case 182: /* Store Quadword Conditional Indexed */
4611 case 662: /* Store Word Byte-Reverse Indexed */
4612 case 918: /* Store Halfword Byte-Reverse Indexed */
4613 case 660: /* Store Doubleword Byte-Reverse Indexed */
4614 case 663: /* Store Floating-Point Single Indexed */
4615 case 727: /* Store Floating-Point Double Indexed */
4616 case 919: /* Store Floating-Point Double Pair Indexed */
4617 case 983: /* Store Floating-Point as Integer Word Indexed */
4618 case 396: /* Store VSX Vector Indexed */
4619 case 940: /* Store VSX Vector Halfword*8 Indexed */
4620 case 1004: /* Store VSX Vector Byte*16 Indexed */
4621 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4622 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4623 if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182)
4624 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4627 if (PPC_RA (insn) != 0)
4628 regcache_raw_read_unsigned (regcache,
4629 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4630 regcache_raw_read_unsigned (regcache,
4631 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
4636 case 183: /* Store Word with Update Indexed */
4637 case 199: /* Store Vector Element Word Indexed */
4638 case 140: /* Store VSX Scalar as Integer Word Indexed */
4639 case 652: /* Store VSX Scalar Single-Precision Indexed */
4640 case 151: /* Store Word Indexed */
4641 case 150: /* Store Word Conditional Indexed */
4642 case 662: /* Store Word Byte-Reverse Indexed */
4643 case 663: /* Store Floating-Point Single Indexed */
4644 case 695: /* Store Floating-Point Single with Update Indexed */
4645 case 983: /* Store Floating-Point as Integer Word Indexed */
4648 case 247: /* Store Byte with Update Indexed */
4649 case 135: /* Store Vector Element Byte Indexed */
4650 case 215: /* Store Byte Indexed */
4651 case 694: /* Store Byte Conditional Indexed */
4652 case 909: /* Store VSX Scalar as Integer Byte Indexed */
4655 case 439: /* Store Halfword with Update Indexed */
4656 case 167: /* Store Vector Element Halfword Indexed */
4657 case 407: /* Store Halfword Indexed */
4658 case 726: /* Store Halfword Conditional Indexed */
4659 case 918: /* Store Halfword Byte-Reverse Indexed */
4660 case 941: /* Store VSX Scalar as Integer Halfword Indexed */
4663 case 181: /* Store Doubleword with Update Indexed */
4664 case 716: /* Store VSX Scalar Doubleword Indexed */
4665 case 149: /* Store Doubleword Indexed */
4666 case 214: /* Store Doubleword Conditional Indexed */
4667 case 660: /* Store Doubleword Byte-Reverse Indexed */
4668 case 727: /* Store Floating-Point Double Indexed */
4669 case 759: /* Store Floating-Point Double with Update Indexed */
4672 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4673 case 908: /* Store VSX Vector Word*4 Indexed */
4674 case 182: /* Store Quadword Conditional Indexed */
4675 case 231: /* Store Vector Indexed */
4676 case 487: /* Store Vector Indexed LRU */
4677 case 919: /* Store Floating-Point Double Pair Indexed */
4678 case 396: /* Store VSX Vector Indexed */
4679 case 940: /* Store VSX Vector Halfword*8 Indexed */
4680 case 1004: /* Store VSX Vector Byte*16 Indexed */
4687 /* Align address for Store Vector instructions. */
4690 case 167: /* Store Vector Element Halfword Indexed */
4691 addr = addr & ~0x1ULL;
4694 case 199: /* Store Vector Element Word Indexed */
4695 addr = addr & ~0x3ULL;
4698 case 231: /* Store Vector Indexed */
4699 case 487: /* Store Vector Indexed LRU */
4700 addr = addr & ~0xfULL;
4704 record_full_arch_list_add_mem (addr, size);
4707 case 397: /* Store VSX Vector with Length */
4708 case 429: /* Store VSX Vector Left-justified with Length */
4710 if (PPC_RA (insn) != 0)
4711 regcache_raw_read_unsigned (regcache,
4712 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4714 regcache_raw_read_unsigned (regcache,
4715 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
4716 /* Store up to 16 bytes. */
4717 nb = (rb & 0xff) > 16 ? 16 : (rb & 0xff);
4719 record_full_arch_list_add_mem (ea, nb);
4722 case 710: /* Store Word Atomic */
4723 case 742: /* Store Doubleword Atomic */
4725 if (PPC_RA (insn) != 0)
4726 regcache_raw_read_unsigned (regcache,
4727 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4731 case 710: /* Store Word Atomic */
4734 case 742: /* Store Doubleword Atomic */
4740 record_full_arch_list_add_mem (ea, size);
4743 case 725: /* Store String Word Immediate */
4745 if (PPC_RA (insn) != 0)
4746 regcache_raw_read_unsigned (regcache,
4747 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4754 record_full_arch_list_add_mem (ea, nb);
4758 case 661: /* Store String Word Indexed */
4760 if (PPC_RA (insn) != 0)
4761 regcache_raw_read_unsigned (regcache,
4762 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4765 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer);
4766 nb = PPC_XER_NB (xer);
4770 regcache_raw_read_unsigned (regcache,
4771 tdep->ppc_gp0_regnum + PPC_RB (insn),
4774 record_full_arch_list_add_mem (ea, nb);
4779 case 467: /* Move To Special Purpose Register */
4780 switch (PPC_SPR (insn))
4783 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4786 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
4789 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum);
4791 case 256: /* VRSAVE */
4792 record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum);
4798 case 147: /* Move To Split Little Endian */
4799 record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum);
4802 case 512: /* Move to Condition Register from XER */
4803 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4804 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4807 case 4: /* Trap Word */
4808 case 68: /* Trap Doubleword */
4809 case 430: /* Clear BHRB */
4810 case 598: /* Synchronize */
4811 case 62: /* Wait for Interrupt */
4813 case 22: /* Instruction Cache Block Touch */
4814 case 854: /* Enforce In-order Execution of I/O */
4815 case 246: /* Data Cache Block Touch for Store */
4816 case 54: /* Data Cache Block Store */
4817 case 86: /* Data Cache Block Flush */
4818 case 278: /* Data Cache Block Touch */
4819 case 758: /* Data Cache Block Allocate */
4820 case 982: /* Instruction Cache Block Invalidate */
4821 case 774: /* Copy */
4822 case 838: /* CP_Abort */
4825 case 654: /* Transaction Begin */
4826 case 686: /* Transaction End */
4827 case 750: /* Transaction Suspend or Resume */
4828 case 782: /* Transaction Abort Word Conditional */
4829 case 814: /* Transaction Abort Doubleword Conditional */
4830 case 846: /* Transaction Abort Word Conditional Immediate */
4831 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4832 case 910: /* Transaction Abort */
4833 record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum);
4835 case 718: /* Transaction Check */
4836 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4839 case 1014: /* Data Cache Block set to Zero */
4840 if (target_auxv_search (¤t_target, AT_DCACHEBSIZE, &at_dcsz) <= 0
4842 at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */
4845 if (PPC_RA (insn) != 0)
4846 regcache_raw_read_unsigned (regcache,
4847 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4848 regcache_raw_read_unsigned (regcache,
4849 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
4850 ea = (ra + rb) & ~((ULONGEST) (at_dcsz - 1));
4851 record_full_arch_list_add_mem (ea, at_dcsz);
4856 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4857 "at %s, 31-%d.\n", insn, paddress (gdbarch, addr), ext);
4861 /* Parse and record instructions of primary opcode-59 at ADDR.
4862 Return 0 if successful. */
4865 ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache,
4866 CORE_ADDR addr, uint32_t insn)
4868 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4869 int ext = PPC_EXTOP (insn);
4873 case 18: /* Floating Divide */
4874 case 20: /* Floating Subtract */
4875 case 21: /* Floating Add */
4876 case 22: /* Floating Square Root */
4877 case 24: /* Floating Reciprocal Estimate */
4878 case 25: /* Floating Multiply */
4879 case 26: /* Floating Reciprocal Square Root Estimate */
4880 case 28: /* Floating Multiply-Subtract */
4881 case 29: /* Floating Multiply-Add */
4882 case 30: /* Floating Negative Multiply-Subtract */
4883 case 31: /* Floating Negative Multiply-Add */
4884 record_full_arch_list_add_reg (regcache,
4885 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4887 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4888 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4895 case 2: /* DFP Add */
4896 case 3: /* DFP Quantize */
4897 case 34: /* DFP Multiply */
4898 case 35: /* DFP Reround */
4899 case 67: /* DFP Quantize Immediate */
4900 case 99: /* DFP Round To FP Integer With Inexact */
4901 case 227: /* DFP Round To FP Integer Without Inexact */
4902 case 258: /* DFP Convert To DFP Long! */
4903 case 290: /* DFP Convert To Fixed */
4904 case 514: /* DFP Subtract */
4905 case 546: /* DFP Divide */
4906 case 770: /* DFP Round To DFP Short! */
4907 case 802: /* DFP Convert From Fixed */
4908 case 834: /* DFP Encode BCD To DPD */
4910 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4911 record_full_arch_list_add_reg (regcache,
4912 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4913 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4916 case 130: /* DFP Compare Ordered */
4917 case 162: /* DFP Test Exponent */
4918 case 194: /* DFP Test Data Class */
4919 case 226: /* DFP Test Data Group */
4920 case 642: /* DFP Compare Unordered */
4921 case 674: /* DFP Test Significance */
4922 case 675: /* DFP Test Significance Immediate */
4923 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4924 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4927 case 66: /* DFP Shift Significand Left Immediate */
4928 case 98: /* DFP Shift Significand Right Immediate */
4929 case 322: /* DFP Decode DPD To BCD */
4930 case 354: /* DFP Extract Biased Exponent */
4931 case 866: /* DFP Insert Biased Exponent */
4932 record_full_arch_list_add_reg (regcache,
4933 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4935 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4938 case 846: /* Floating Convert From Integer Doubleword Single */
4939 case 974: /* Floating Convert From Integer Doubleword Unsigned
4941 record_full_arch_list_add_reg (regcache,
4942 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4944 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4945 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4950 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4951 "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext);
4955 /* Parse and record instructions of primary opcode-60 at ADDR.
4956 Return 0 if successful. */
4959 ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
4960 CORE_ADDR addr, uint32_t insn)
4962 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4963 int ext = PPC_EXTOP (insn);
4967 case 0: /* VSX Scalar Add Single-Precision */
4968 case 32: /* VSX Scalar Add Double-Precision */
4969 case 24: /* VSX Scalar Divide Single-Precision */
4970 case 56: /* VSX Scalar Divide Double-Precision */
4971 case 176: /* VSX Scalar Copy Sign Double-Precision */
4972 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4973 case 41: /* ditto */
4974 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4976 case 160: /* VSX Scalar Maximum Double-Precision */
4977 case 168: /* VSX Scalar Minimum Double-Precision */
4978 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4979 case 57: /* ditto */
4980 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4981 case 25: /* ditto */
4982 case 48: /* VSX Scalar Multiply Double-Precision */
4983 case 16: /* VSX Scalar Multiply Single-Precision */
4984 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4985 case 169: /* ditto */
4986 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4987 case 137: /* ditto */
4988 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4989 case 185: /* ditto */
4990 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4991 case 153: /* ditto */
4992 case 40: /* VSX Scalar Subtract Double-Precision */
4993 case 8: /* VSX Scalar Subtract Single-Precision */
4994 case 96: /* VSX Vector Add Double-Precision */
4995 case 64: /* VSX Vector Add Single-Precision */
4996 case 120: /* VSX Vector Divide Double-Precision */
4997 case 88: /* VSX Vector Divide Single-Precision */
4998 case 97: /* VSX Vector Multiply-Add Double-Precision */
4999 case 105: /* ditto */
5000 case 65: /* VSX Vector Multiply-Add Single-Precision */
5001 case 73: /* ditto */
5002 case 224: /* VSX Vector Maximum Double-Precision */
5003 case 192: /* VSX Vector Maximum Single-Precision */
5004 case 232: /* VSX Vector Minimum Double-Precision */
5005 case 200: /* VSX Vector Minimum Single-Precision */
5006 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
5007 case 121: /* ditto */
5008 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
5009 case 89: /* ditto */
5010 case 112: /* VSX Vector Multiply Double-Precision */
5011 case 80: /* VSX Vector Multiply Single-Precision */
5012 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
5013 case 233: /* ditto */
5014 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
5015 case 201: /* ditto */
5016 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
5017 case 249: /* ditto */
5018 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
5019 case 217: /* ditto */
5020 case 104: /* VSX Vector Subtract Double-Precision */
5021 case 72: /* VSX Vector Subtract Single-Precision */
5022 case 128: /* VSX Scalar Maximum Type-C Double-Precision */
5023 case 136: /* VSX Scalar Minimum Type-C Double-Precision */
5024 case 144: /* VSX Scalar Maximum Type-J Double-Precision */
5025 case 152: /* VSX Scalar Minimum Type-J Double-Precision */
5026 case 3: /* VSX Scalar Compare Equal Double-Precision */
5027 case 11: /* VSX Scalar Compare Greater Than Double-Precision */
5028 case 19: /* VSX Scalar Compare Greater Than or Equal
5030 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5032 case 240: /* VSX Vector Copy Sign Double-Precision */
5033 case 208: /* VSX Vector Copy Sign Single-Precision */
5034 case 130: /* VSX Logical AND */
5035 case 138: /* VSX Logical AND with Complement */
5036 case 186: /* VSX Logical Equivalence */
5037 case 178: /* VSX Logical NAND */
5038 case 170: /* VSX Logical OR with Complement */
5039 case 162: /* VSX Logical NOR */
5040 case 146: /* VSX Logical OR */
5041 case 154: /* VSX Logical XOR */
5042 case 18: /* VSX Merge High Word */
5043 case 50: /* VSX Merge Low Word */
5044 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
5045 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
5046 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
5047 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
5048 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
5049 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
5050 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
5051 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
5052 case 216: /* VSX Vector Insert Exponent Single-Precision */
5053 case 248: /* VSX Vector Insert Exponent Double-Precision */
5054 case 26: /* VSX Vector Permute */
5055 case 58: /* VSX Vector Permute Right-indexed */
5056 case 213: /* VSX Vector Test Data Class Single-Precision (DC=0) */
5057 case 213 | 0x8: /* VSX Vector Test Data Class Single-Precision (DC=1) */
5058 case 245: /* VSX Vector Test Data Class Double-Precision (DC=0) */
5059 case 245 | 0x8: /* VSX Vector Test Data Class Double-Precision (DC=1) */
5060 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5063 case 61: /* VSX Scalar Test for software Divide Double-Precision */
5064 case 125: /* VSX Vector Test for software Divide Double-Precision */
5065 case 93: /* VSX Vector Test for software Divide Single-Precision */
5066 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5069 case 35: /* VSX Scalar Compare Unordered Double-Precision */
5070 case 43: /* VSX Scalar Compare Ordered Double-Precision */
5071 case 59: /* VSX Scalar Compare Exponents Double-Precision */
5072 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5073 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5077 switch ((ext >> 2) & 0x7f) /* Mask out Rc-bit. */
5079 case 99: /* VSX Vector Compare Equal To Double-Precision */
5080 case 67: /* VSX Vector Compare Equal To Single-Precision */
5081 case 115: /* VSX Vector Compare Greater Than or
5082 Equal To Double-Precision */
5083 case 83: /* VSX Vector Compare Greater Than or
5084 Equal To Single-Precision */
5085 case 107: /* VSX Vector Compare Greater Than Double-Precision */
5086 case 75: /* VSX Vector Compare Greater Than Single-Precision */
5088 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5089 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5090 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5096 case 265: /* VSX Scalar round Double-Precision to
5097 Single-Precision and Convert to
5098 Single-Precision format */
5099 case 344: /* VSX Scalar truncate Double-Precision to
5100 Integer and Convert to Signed Integer
5101 Doubleword format with Saturate */
5102 case 88: /* VSX Scalar truncate Double-Precision to
5103 Integer and Convert to Signed Integer Word
5104 Format with Saturate */
5105 case 328: /* VSX Scalar truncate Double-Precision integer
5106 and Convert to Unsigned Integer Doubleword
5107 Format with Saturate */
5108 case 72: /* VSX Scalar truncate Double-Precision to
5109 Integer and Convert to Unsigned Integer Word
5110 Format with Saturate */
5111 case 329: /* VSX Scalar Convert Single-Precision to
5112 Double-Precision format */
5113 case 376: /* VSX Scalar Convert Signed Integer
5114 Doubleword to floating-point format and
5115 Round to Double-Precision format */
5116 case 312: /* VSX Scalar Convert Signed Integer
5117 Doubleword to floating-point format and
5118 round to Single-Precision */
5119 case 360: /* VSX Scalar Convert Unsigned Integer
5120 Doubleword to floating-point format and
5121 Round to Double-Precision format */
5122 case 296: /* VSX Scalar Convert Unsigned Integer
5123 Doubleword to floating-point format and
5124 Round to Single-Precision */
5125 case 73: /* VSX Scalar Round to Double-Precision Integer
5126 Using Round to Nearest Away */
5127 case 107: /* VSX Scalar Round to Double-Precision Integer
5128 Exact using Current rounding mode */
5129 case 121: /* VSX Scalar Round to Double-Precision Integer
5130 Using Round toward -Infinity */
5131 case 105: /* VSX Scalar Round to Double-Precision Integer
5132 Using Round toward +Infinity */
5133 case 89: /* VSX Scalar Round to Double-Precision Integer
5134 Using Round toward Zero */
5135 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
5136 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
5137 case 281: /* VSX Scalar Round to Single-Precision */
5138 case 74: /* VSX Scalar Reciprocal Square Root Estimate
5140 case 10: /* VSX Scalar Reciprocal Square Root Estimate
5142 case 75: /* VSX Scalar Square Root Double-Precision */
5143 case 11: /* VSX Scalar Square Root Single-Precision */
5144 case 393: /* VSX Vector round Double-Precision to
5145 Single-Precision and Convert to
5146 Single-Precision format */
5147 case 472: /* VSX Vector truncate Double-Precision to
5148 Integer and Convert to Signed Integer
5149 Doubleword format with Saturate */
5150 case 216: /* VSX Vector truncate Double-Precision to
5151 Integer and Convert to Signed Integer Word
5152 Format with Saturate */
5153 case 456: /* VSX Vector truncate Double-Precision to
5154 Integer and Convert to Unsigned Integer
5155 Doubleword format with Saturate */
5156 case 200: /* VSX Vector truncate Double-Precision to
5157 Integer and Convert to Unsigned Integer Word
5158 Format with Saturate */
5159 case 457: /* VSX Vector Convert Single-Precision to
5160 Double-Precision format */
5161 case 408: /* VSX Vector truncate Single-Precision to
5162 Integer and Convert to Signed Integer
5163 Doubleword format with Saturate */
5164 case 152: /* VSX Vector truncate Single-Precision to
5165 Integer and Convert to Signed Integer Word
5166 Format with Saturate */
5167 case 392: /* VSX Vector truncate Single-Precision to
5168 Integer and Convert to Unsigned Integer
5169 Doubleword format with Saturate */
5170 case 136: /* VSX Vector truncate Single-Precision to
5171 Integer and Convert to Unsigned Integer Word
5172 Format with Saturate */
5173 case 504: /* VSX Vector Convert and round Signed Integer
5174 Doubleword to Double-Precision format */
5175 case 440: /* VSX Vector Convert and round Signed Integer
5176 Doubleword to Single-Precision format */
5177 case 248: /* VSX Vector Convert Signed Integer Word to
5178 Double-Precision format */
5179 case 184: /* VSX Vector Convert and round Signed Integer
5180 Word to Single-Precision format */
5181 case 488: /* VSX Vector Convert and round Unsigned
5182 Integer Doubleword to Double-Precision format */
5183 case 424: /* VSX Vector Convert and round Unsigned
5184 Integer Doubleword to Single-Precision format */
5185 case 232: /* VSX Vector Convert and round Unsigned
5186 Integer Word to Double-Precision format */
5187 case 168: /* VSX Vector Convert and round Unsigned
5188 Integer Word to Single-Precision format */
5189 case 201: /* VSX Vector Round to Double-Precision
5190 Integer using round to Nearest Away */
5191 case 235: /* VSX Vector Round to Double-Precision
5192 Integer Exact using Current rounding mode */
5193 case 249: /* VSX Vector Round to Double-Precision
5194 Integer using round toward -Infinity */
5195 case 233: /* VSX Vector Round to Double-Precision
5196 Integer using round toward +Infinity */
5197 case 217: /* VSX Vector Round to Double-Precision
5198 Integer using round toward Zero */
5199 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
5200 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
5201 case 137: /* VSX Vector Round to Single-Precision Integer
5202 Using Round to Nearest Away */
5203 case 171: /* VSX Vector Round to Single-Precision Integer
5204 Exact Using Current rounding mode */
5205 case 185: /* VSX Vector Round to Single-Precision Integer
5206 Using Round toward -Infinity */
5207 case 169: /* VSX Vector Round to Single-Precision Integer
5208 Using Round toward +Infinity */
5209 case 153: /* VSX Vector Round to Single-Precision Integer
5210 Using round toward Zero */
5211 case 202: /* VSX Vector Reciprocal Square Root Estimate
5213 case 138: /* VSX Vector Reciprocal Square Root Estimate
5215 case 203: /* VSX Vector Square Root Double-Precision */
5216 case 139: /* VSX Vector Square Root Single-Precision */
5217 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5219 case 345: /* VSX Scalar Absolute Value Double-Precision */
5220 case 267: /* VSX Scalar Convert Scalar Single-Precision to
5221 Vector Single-Precision format Non-signalling */
5222 case 331: /* VSX Scalar Convert Single-Precision to
5223 Double-Precision format Non-signalling */
5224 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
5225 case 377: /* VSX Scalar Negate Double-Precision */
5226 case 473: /* VSX Vector Absolute Value Double-Precision */
5227 case 409: /* VSX Vector Absolute Value Single-Precision */
5228 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
5229 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5230 case 505: /* VSX Vector Negate Double-Precision */
5231 case 441: /* VSX Vector Negate Single-Precision */
5232 case 164: /* VSX Splat Word */
5233 case 165: /* VSX Vector Extract Unsigned Word */
5234 case 181: /* VSX Vector Insert Word */
5235 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5238 case 298: /* VSX Scalar Test Data Class Single-Precision */
5239 case 362: /* VSX Scalar Test Data Class Double-Precision */
5240 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5242 case 106: /* VSX Scalar Test for software Square Root
5244 case 234: /* VSX Vector Test for software Square Root
5246 case 170: /* VSX Vector Test for software Square Root
5248 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5252 switch (PPC_FIELD (insn, 11, 5))
5254 case 0: /* VSX Scalar Extract Exponent Double-Precision */
5255 case 1: /* VSX Scalar Extract Significand Double-Precision */
5256 record_full_arch_list_add_reg (regcache,
5257 tdep->ppc_gp0_regnum + PPC_RT (insn));
5259 case 16: /* VSX Scalar Convert Half-Precision format to
5260 Double-Precision format */
5261 case 17: /* VSX Scalar round & Convert Double-Precision format
5262 to Half-Precision format */
5263 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5264 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5270 switch (PPC_FIELD (insn, 11, 5))
5272 case 24: /* VSX Vector Convert Half-Precision format to
5273 Single-Precision format */
5274 case 25: /* VSX Vector round and Convert Single-Precision format
5275 to Half-Precision format */
5276 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5278 case 0: /* VSX Vector Extract Exponent Double-Precision */
5279 case 1: /* VSX Vector Extract Significand Double-Precision */
5280 case 7: /* VSX Vector Byte-Reverse Halfword */
5281 case 8: /* VSX Vector Extract Exponent Single-Precision */
5282 case 9: /* VSX Vector Extract Significand Single-Precision */
5283 case 15: /* VSX Vector Byte-Reverse Word */
5284 case 23: /* VSX Vector Byte-Reverse Doubleword */
5285 case 31: /* VSX Vector Byte-Reverse Quadword */
5286 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5294 case 360: /* VSX Vector Splat Immediate Byte */
5295 if (PPC_FIELD (insn, 11, 2) == 0)
5297 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5301 case 918: /* VSX Scalar Insert Exponent Double-Precision */
5302 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5306 if (((ext >> 3) & 0x3) == 3) /* VSX Select */
5308 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5312 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
5313 "at %s, 60-%d.\n", insn, paddress (gdbarch, addr), ext);
5317 /* Parse and record instructions of primary opcode-61 at ADDR.
5318 Return 0 if successful. */
5321 ppc_process_record_op61 (struct gdbarch *gdbarch, struct regcache *regcache,
5322 CORE_ADDR addr, uint32_t insn)
5324 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5330 case 0: /* Store Floating-Point Double Pair */
5331 case 2: /* Store VSX Scalar Doubleword */
5332 case 3: /* Store VSX Scalar Single */
5333 if (PPC_RA (insn) != 0)
5334 regcache_raw_read_unsigned (regcache,
5335 tdep->ppc_gp0_regnum + PPC_RA (insn),
5337 ea += PPC_DS (insn) << 2;
5340 case 0: /* Store Floating-Point Double Pair */
5343 case 2: /* Store VSX Scalar Doubleword */
5346 case 3: /* Store VSX Scalar Single */
5352 record_full_arch_list_add_mem (ea, size);
5358 case 1: /* Load VSX Vector */
5359 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5361 case 5: /* Store VSX Vector */
5362 if (PPC_RA (insn) != 0)
5363 regcache_raw_read_unsigned (regcache,
5364 tdep->ppc_gp0_regnum + PPC_RA (insn),
5366 ea += PPC_DQ (insn) << 4;
5367 record_full_arch_list_add_mem (ea, 16);
5371 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
5372 "at %s.\n", insn, paddress (gdbarch, addr));
5376 /* Parse and record instructions of primary opcode-63 at ADDR.
5377 Return 0 if successful. */
5380 ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache,
5381 CORE_ADDR addr, uint32_t insn)
5383 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5384 int ext = PPC_EXTOP (insn);
5389 case 18: /* Floating Divide */
5390 case 20: /* Floating Subtract */
5391 case 21: /* Floating Add */
5392 case 22: /* Floating Square Root */
5393 case 24: /* Floating Reciprocal Estimate */
5394 case 25: /* Floating Multiply */
5395 case 26: /* Floating Reciprocal Square Root Estimate */
5396 case 28: /* Floating Multiply-Subtract */
5397 case 29: /* Floating Multiply-Add */
5398 case 30: /* Floating Negative Multiply-Subtract */
5399 case 31: /* Floating Negative Multiply-Add */
5400 record_full_arch_list_add_reg (regcache,
5401 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5403 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5404 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5407 case 23: /* Floating Select */
5408 record_full_arch_list_add_reg (regcache,
5409 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5411 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5417 case 5: /* VSX Scalar Round to Quad-Precision Integer */
5418 case 37: /* VSX Scalar Round Quad-Precision to Double-Extended
5420 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5421 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
5427 case 2: /* DFP Add Quad */
5428 case 3: /* DFP Quantize Quad */
5429 case 34: /* DFP Multiply Quad */
5430 case 35: /* DFP Reround Quad */
5431 case 67: /* DFP Quantize Immediate Quad */
5432 case 99: /* DFP Round To FP Integer With Inexact Quad */
5433 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5434 case 258: /* DFP Convert To DFP Extended Quad */
5435 case 514: /* DFP Subtract Quad */
5436 case 546: /* DFP Divide Quad */
5437 case 770: /* DFP Round To DFP Long Quad */
5438 case 802: /* DFP Convert From Fixed Quad */
5439 case 834: /* DFP Encode BCD To DPD Quad */
5441 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5442 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
5443 record_full_arch_list_add_reg (regcache, tmp);
5444 record_full_arch_list_add_reg (regcache, tmp + 1);
5445 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5448 case 130: /* DFP Compare Ordered Quad */
5449 case 162: /* DFP Test Exponent Quad */
5450 case 194: /* DFP Test Data Class Quad */
5451 case 226: /* DFP Test Data Group Quad */
5452 case 642: /* DFP Compare Unordered Quad */
5453 case 674: /* DFP Test Significance Quad */
5454 case 675: /* DFP Test Significance Immediate Quad */
5455 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5456 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5459 case 66: /* DFP Shift Significand Left Immediate Quad */
5460 case 98: /* DFP Shift Significand Right Immediate Quad */
5461 case 322: /* DFP Decode DPD To BCD Quad */
5462 case 866: /* DFP Insert Biased Exponent Quad */
5463 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
5464 record_full_arch_list_add_reg (regcache, tmp);
5465 record_full_arch_list_add_reg (regcache, tmp + 1);
5467 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5470 case 290: /* DFP Convert To Fixed Quad */
5471 record_full_arch_list_add_reg (regcache,
5472 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5474 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5475 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5478 case 354: /* DFP Extract Biased Exponent Quad */
5479 record_full_arch_list_add_reg (regcache,
5480 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5482 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5485 case 12: /* Floating Round to Single-Precision */
5486 case 14: /* Floating Convert To Integer Word */
5487 case 15: /* Floating Convert To Integer Word
5488 with round toward Zero */
5489 case 142: /* Floating Convert To Integer Word Unsigned */
5490 case 143: /* Floating Convert To Integer Word Unsigned
5491 with round toward Zero */
5492 case 392: /* Floating Round to Integer Nearest */
5493 case 424: /* Floating Round to Integer Toward Zero */
5494 case 456: /* Floating Round to Integer Plus */
5495 case 488: /* Floating Round to Integer Minus */
5496 case 814: /* Floating Convert To Integer Doubleword */
5497 case 815: /* Floating Convert To Integer Doubleword
5498 with round toward Zero */
5499 case 846: /* Floating Convert From Integer Doubleword */
5500 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5501 case 943: /* Floating Convert To Integer Doubleword Unsigned
5502 with round toward Zero */
5503 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5504 record_full_arch_list_add_reg (regcache,
5505 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5507 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5508 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5512 switch (PPC_FIELD (insn, 11, 5))
5514 case 1: /* Move From FPSCR & Clear Enables */
5515 case 20: /* Move From FPSCR Control & set DRN */
5516 case 21: /* Move From FPSCR Control & set DRN Immediate */
5517 case 22: /* Move From FPSCR Control & set RN */
5518 case 23: /* Move From FPSCR Control & set RN Immediate */
5519 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5520 case 0: /* Move From FPSCR */
5521 case 24: /* Move From FPSCR Lightweight */
5522 if (PPC_FIELD (insn, 11, 5) == 0 && PPC_RC (insn))
5523 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5524 record_full_arch_list_add_reg (regcache,
5525 tdep->ppc_fp0_regnum
5531 case 8: /* Floating Copy Sign */
5532 case 40: /* Floating Negate */
5533 case 72: /* Floating Move Register */
5534 case 136: /* Floating Negative Absolute Value */
5535 case 264: /* Floating Absolute Value */
5536 record_full_arch_list_add_reg (regcache,
5537 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5539 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5542 case 838: /* Floating Merge Odd Word */
5543 case 966: /* Floating Merge Even Word */
5544 record_full_arch_list_add_reg (regcache,
5545 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5548 case 38: /* Move To FPSCR Bit 1 */
5549 case 70: /* Move To FPSCR Bit 0 */
5550 case 134: /* Move To FPSCR Field Immediate */
5551 case 711: /* Move To FPSCR Fields */
5553 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5554 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5557 case 0: /* Floating Compare Unordered */
5558 case 32: /* Floating Compare Ordered */
5559 case 64: /* Move to Condition Register from FPSCR */
5560 case 132: /* VSX Scalar Compare Ordered Quad-Precision */
5561 case 164: /* VSX Scalar Compare Exponents Quad-Precision */
5562 case 644: /* VSX Scalar Compare Unordered Quad-Precision */
5563 case 708: /* VSX Scalar Test Data Class Quad-Precision */
5564 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5566 case 128: /* Floating Test for software Divide */
5567 case 160: /* Floating Test for software Square Root */
5568 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5571 case 4: /* VSX Scalar Add Quad-Precision */
5572 case 36: /* VSX Scalar Multiply Quad-Precision */
5573 case 388: /* VSX Scalar Multiply-Add Quad-Precision */
5574 case 420: /* VSX Scalar Multiply-Subtract Quad-Precision */
5575 case 452: /* VSX Scalar Negative Multiply-Add Quad-Precision */
5576 case 484: /* VSX Scalar Negative Multiply-Subtract
5578 case 516: /* VSX Scalar Subtract Quad-Precision */
5579 case 548: /* VSX Scalar Divide Quad-Precision */
5580 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5582 case 100: /* VSX Scalar Copy Sign Quad-Precision */
5583 case 868: /* VSX Scalar Insert Exponent Quad-Precision */
5584 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
5588 switch (PPC_FIELD (insn, 11, 5))
5590 case 27: /* VSX Scalar Square Root Quad-Precision */
5591 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5593 case 0: /* VSX Scalar Absolute Quad-Precision */
5594 case 2: /* VSX Scalar Extract Exponent Quad-Precision */
5595 case 8: /* VSX Scalar Negative Absolute Quad-Precision */
5596 case 16: /* VSX Scalar Negate Quad-Precision */
5597 case 18: /* VSX Scalar Extract Significand Quad-Precision */
5598 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
5604 switch (PPC_FIELD (insn, 11, 5))
5606 case 1: /* VSX Scalar truncate & Convert Quad-Precision format
5607 to Unsigned Word format */
5608 case 2: /* VSX Scalar Convert Unsigned Doubleword format to
5609 Quad-Precision format */
5610 case 9: /* VSX Scalar truncate & Convert Quad-Precision format
5611 to Signed Word format */
5612 case 10: /* VSX Scalar Convert Signed Doubleword format to
5613 Quad-Precision format */
5614 case 17: /* VSX Scalar truncate & Convert Quad-Precision format
5615 to Unsigned Doubleword format */
5616 case 20: /* VSX Scalar round & Convert Quad-Precision format to
5617 Double-Precision format */
5618 case 22: /* VSX Scalar Convert Double-Precision format to
5619 Quad-Precision format */
5620 case 25: /* VSX Scalar truncate & Convert Quad-Precision format
5621 to Signed Doubleword format */
5622 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5623 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
5628 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
5629 "at %s, 63-%d.\n", insn, paddress (gdbarch, addr), ext);
5633 /* Parse the current instruction and record the values of the registers and
5634 memory that will be changed in current instruction to "record_arch_list".
5635 Return -1 if something wrong. */
5638 ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5641 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5642 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5646 insn = read_memory_unsigned_integer (addr, 4, byte_order);
5647 op6 = PPC_OP6 (insn);
5651 case 2: /* Trap Doubleword Immediate */
5652 case 3: /* Trap Word Immediate */
5657 if (ppc_process_record_op4 (gdbarch, regcache, addr, insn) != 0)
5661 case 17: /* System call */
5662 if (PPC_LEV (insn) != 0)
5665 if (tdep->ppc_syscall_record != NULL)
5667 if (tdep->ppc_syscall_record (regcache) != 0)
5672 printf_unfiltered (_("no syscall record support\n"));
5677 case 7: /* Multiply Low Immediate */
5678 record_full_arch_list_add_reg (regcache,
5679 tdep->ppc_gp0_regnum + PPC_RT (insn));
5682 case 8: /* Subtract From Immediate Carrying */
5683 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
5684 record_full_arch_list_add_reg (regcache,
5685 tdep->ppc_gp0_regnum + PPC_RT (insn));
5688 case 10: /* Compare Logical Immediate */
5689 case 11: /* Compare Immediate */
5690 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5693 case 13: /* Add Immediate Carrying and Record */
5694 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5696 case 12: /* Add Immediate Carrying */
5697 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
5699 case 14: /* Add Immediate */
5700 case 15: /* Add Immediate Shifted */
5701 record_full_arch_list_add_reg (regcache,
5702 tdep->ppc_gp0_regnum + PPC_RT (insn));
5705 case 16: /* Branch Conditional */
5706 if ((PPC_BO (insn) & 0x4) == 0)
5707 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum);
5709 case 18: /* Branch */
5711 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
5715 if (ppc_process_record_op19 (gdbarch, regcache, addr, insn) != 0)
5719 case 20: /* Rotate Left Word Immediate then Mask Insert */
5720 case 21: /* Rotate Left Word Immediate then AND with Mask */
5721 case 23: /* Rotate Left Word then AND with Mask */
5722 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5723 /* Rotate Left Doubleword Immediate then Clear Right */
5724 /* Rotate Left Doubleword Immediate then Clear */
5725 /* Rotate Left Doubleword then Clear Left */
5726 /* Rotate Left Doubleword then Clear Right */
5727 /* Rotate Left Doubleword Immediate then Mask Insert */
5729 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5730 record_full_arch_list_add_reg (regcache,
5731 tdep->ppc_gp0_regnum + PPC_RA (insn));
5734 case 28: /* AND Immediate */
5735 case 29: /* AND Immediate Shifted */
5736 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5738 case 24: /* OR Immediate */
5739 case 25: /* OR Immediate Shifted */
5740 case 26: /* XOR Immediate */
5741 case 27: /* XOR Immediate Shifted */
5742 record_full_arch_list_add_reg (regcache,
5743 tdep->ppc_gp0_regnum + PPC_RA (insn));
5747 if (ppc_process_record_op31 (gdbarch, regcache, addr, insn) != 0)
5751 case 33: /* Load Word and Zero with Update */
5752 case 35: /* Load Byte and Zero with Update */
5753 case 41: /* Load Halfword and Zero with Update */
5754 case 43: /* Load Halfword Algebraic with Update */
5755 record_full_arch_list_add_reg (regcache,
5756 tdep->ppc_gp0_regnum + PPC_RA (insn));
5758 case 32: /* Load Word and Zero */
5759 case 34: /* Load Byte and Zero */
5760 case 40: /* Load Halfword and Zero */
5761 case 42: /* Load Halfword Algebraic */
5762 record_full_arch_list_add_reg (regcache,
5763 tdep->ppc_gp0_regnum + PPC_RT (insn));
5766 case 46: /* Load Multiple Word */
5767 for (i = PPC_RT (insn); i < 32; i++)
5768 record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i);
5771 case 56: /* Load Quadword */
5772 tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1);
5773 record_full_arch_list_add_reg (regcache, tmp);
5774 record_full_arch_list_add_reg (regcache, tmp + 1);
5777 case 49: /* Load Floating-Point Single with Update */
5778 case 51: /* Load Floating-Point Double with Update */
5779 record_full_arch_list_add_reg (regcache,
5780 tdep->ppc_gp0_regnum + PPC_RA (insn));
5782 case 48: /* Load Floating-Point Single */
5783 case 50: /* Load Floating-Point Double */
5784 record_full_arch_list_add_reg (regcache,
5785 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5788 case 47: /* Store Multiple Word */
5792 if (PPC_RA (insn) != 0)
5793 regcache_raw_read_unsigned (regcache,
5794 tdep->ppc_gp0_regnum + PPC_RA (insn),
5797 addr += PPC_D (insn);
5798 record_full_arch_list_add_mem (addr, 4 * (32 - PPC_RS (insn)));
5802 case 37: /* Store Word with Update */
5803 case 39: /* Store Byte with Update */
5804 case 45: /* Store Halfword with Update */
5805 case 53: /* Store Floating-Point Single with Update */
5806 case 55: /* Store Floating-Point Double with Update */
5807 record_full_arch_list_add_reg (regcache,
5808 tdep->ppc_gp0_regnum + PPC_RA (insn));
5810 case 36: /* Store Word */
5811 case 38: /* Store Byte */
5812 case 44: /* Store Halfword */
5813 case 52: /* Store Floating-Point Single */
5814 case 54: /* Store Floating-Point Double */
5819 if (PPC_RA (insn) != 0)
5820 regcache_raw_read_unsigned (regcache,
5821 tdep->ppc_gp0_regnum + PPC_RA (insn),
5823 addr += PPC_D (insn);
5825 if (op6 == 36 || op6 == 37 || op6 == 52 || op6 == 53)
5827 else if (op6 == 54 || op6 == 55)
5829 else if (op6 == 44 || op6 == 45)
5831 else if (op6 == 38 || op6 == 39)
5836 record_full_arch_list_add_mem (addr, size);
5843 case 0: /* Load Floating-Point Double Pair */
5844 tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
5845 record_full_arch_list_add_reg (regcache, tmp);
5846 record_full_arch_list_add_reg (regcache, tmp + 1);
5848 case 2: /* Load VSX Scalar Doubleword */
5849 case 3: /* Load VSX Scalar Single */
5850 ppc_record_vsr (regcache, tdep, PPC_VRT (insn) + 32);
5857 case 58: /* Load Doubleword */
5858 /* Load Doubleword with Update */
5859 /* Load Word Algebraic */
5860 if (PPC_FIELD (insn, 30, 2) > 2)
5863 record_full_arch_list_add_reg (regcache,
5864 tdep->ppc_gp0_regnum + PPC_RT (insn));
5865 if (PPC_BIT (insn, 31))
5866 record_full_arch_list_add_reg (regcache,
5867 tdep->ppc_gp0_regnum + PPC_RA (insn));
5871 if (ppc_process_record_op59 (gdbarch, regcache, addr, insn) != 0)
5876 if (ppc_process_record_op60 (gdbarch, regcache, addr, insn) != 0)
5881 if (ppc_process_record_op61 (gdbarch, regcache, addr, insn) != 0)
5885 case 62: /* Store Doubleword */
5886 /* Store Doubleword with Update */
5887 /* Store Quadword with Update */
5891 int sub2 = PPC_FIELD (insn, 30, 2);
5896 if (PPC_RA (insn) != 0)
5897 regcache_raw_read_unsigned (regcache,
5898 tdep->ppc_gp0_regnum + PPC_RA (insn),
5901 size = (sub2 == 2) ? 16 : 8;
5903 addr += PPC_DS (insn) << 2;
5904 record_full_arch_list_add_mem (addr, size);
5906 if (op6 == 62 && sub2 == 1)
5907 record_full_arch_list_add_reg (regcache,
5908 tdep->ppc_gp0_regnum +
5915 if (ppc_process_record_op63 (gdbarch, regcache, addr, insn) != 0)
5921 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
5922 "at %s, %d.\n", insn, paddress (gdbarch, addr), op6);
5926 if (record_full_arch_list_add_reg (regcache, PPC_PC_REGNUM))
5928 if (record_full_arch_list_add_end ())
5933 /* Initialize the current architecture based on INFO. If possible, re-use an
5934 architecture from ARCHES, which is a list of architectures already created
5935 during this debugging session.
5937 Called e.g. at program startup, when reading a core file, and when reading
5940 static struct gdbarch *
5941 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5943 struct gdbarch *gdbarch;
5944 struct gdbarch_tdep *tdep;
5945 int wordsize, from_xcoff_exec, from_elf_exec;
5946 enum bfd_architecture arch;
5949 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
5951 enum powerpc_long_double_abi long_double_abi = POWERPC_LONG_DOUBLE_AUTO;
5952 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
5953 enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
5954 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
5956 int tdesc_wordsize = -1;
5957 const struct target_desc *tdesc = info.target_desc;
5958 struct tdesc_arch_data *tdesc_data = NULL;
5959 int num_pseudoregs = 0;
5962 /* INFO may refer to a binary that is not of the PowerPC architecture,
5963 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5964 In this case, we must not attempt to infer properties of the (PowerPC
5965 side) of the target system from properties of that executable. Trust
5966 the target description instead. */
5968 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
5969 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
5972 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
5973 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
5975 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
5976 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
5978 /* Check word size. If INFO is from a binary file, infer it from
5979 that, else choose a likely default. */
5980 if (from_xcoff_exec)
5982 if (bfd_xcoff_is_xcoff64 (info.abfd))
5987 else if (from_elf_exec)
5989 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5994 else if (tdesc_has_registers (tdesc))
5998 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
5999 wordsize = (info.bfd_arch_info->bits_per_word
6000 / info.bfd_arch_info->bits_per_byte);
6005 /* Get the architecture and machine from the BFD. */
6006 arch = info.bfd_arch_info->arch;
6007 mach = info.bfd_arch_info->mach;
6009 /* For e500 executables, the apuinfo section is of help here. Such
6010 section contains the identifier and revision number of each
6011 Application-specific Processing Unit that is present on the
6012 chip. The content of the section is determined by the assembler
6013 which looks at each instruction and determines which unit (and
6014 which version of it) can execute it. Grovel through the section
6015 looking for relevant e500 APUs. */
6017 if (bfd_uses_spe_extensions (info.abfd))
6019 arch = info.bfd_arch_info->arch;
6020 mach = bfd_mach_ppc_e500;
6021 bfd_default_set_arch_mach (&abfd, arch, mach);
6022 info.bfd_arch_info = bfd_get_arch_info (&abfd);
6025 /* Find a default target description which describes our register
6026 layout, if we do not already have one. */
6027 if (! tdesc_has_registers (tdesc))
6029 const struct variant *v;
6031 /* Choose variant. */
6032 v = find_variant_by_arch (arch, mach);
6039 gdb_assert (tdesc_has_registers (tdesc));
6041 /* Check any target description for validity. */
6042 if (tdesc_has_registers (tdesc))
6044 static const char *const gprs[] = {
6045 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
6046 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
6047 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
6048 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
6050 const struct tdesc_feature *feature;
6052 static const char *const msr_names[] = { "msr", "ps" };
6053 static const char *const cr_names[] = { "cr", "cnd" };
6054 static const char *const ctr_names[] = { "ctr", "cnt" };
6056 feature = tdesc_find_feature (tdesc,
6057 "org.gnu.gdb.power.core");
6058 if (feature == NULL)
6061 tdesc_data = tdesc_data_alloc ();
6064 for (i = 0; i < ppc_num_gprs; i++)
6065 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
6066 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
6068 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
6070 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
6073 /* Allow alternate names for these registers, to accomodate GDB's
6075 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
6076 PPC_MSR_REGNUM, msr_names);
6077 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
6078 PPC_CR_REGNUM, cr_names);
6079 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
6080 PPC_CTR_REGNUM, ctr_names);
6084 tdesc_data_cleanup (tdesc_data);
6088 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
6091 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
6093 wordsize = tdesc_wordsize;
6095 feature = tdesc_find_feature (tdesc,
6096 "org.gnu.gdb.power.fpu");
6097 if (feature != NULL)
6099 static const char *const fprs[] = {
6100 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
6101 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
6102 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
6103 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
6106 for (i = 0; i < ppc_num_fprs; i++)
6107 valid_p &= tdesc_numbered_register (feature, tdesc_data,
6108 PPC_F0_REGNUM + i, fprs[i]);
6109 valid_p &= tdesc_numbered_register (feature, tdesc_data,
6110 PPC_FPSCR_REGNUM, "fpscr");
6114 tdesc_data_cleanup (tdesc_data);
6122 /* The DFP pseudo-registers will be available when there are floating
6124 have_dfp = have_fpu;
6126 feature = tdesc_find_feature (tdesc,
6127 "org.gnu.gdb.power.altivec");
6128 if (feature != NULL)
6130 static const char *const vector_regs[] = {
6131 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
6132 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
6133 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
6134 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
6138 for (i = 0; i < ppc_num_gprs; i++)
6139 valid_p &= tdesc_numbered_register (feature, tdesc_data,
6142 valid_p &= tdesc_numbered_register (feature, tdesc_data,
6143 PPC_VSCR_REGNUM, "vscr");
6144 valid_p &= tdesc_numbered_register (feature, tdesc_data,
6145 PPC_VRSAVE_REGNUM, "vrsave");
6147 if (have_spe || !valid_p)
6149 tdesc_data_cleanup (tdesc_data);
6157 /* Check for POWER7 VSX registers support. */
6158 feature = tdesc_find_feature (tdesc,
6159 "org.gnu.gdb.power.vsx");
6161 if (feature != NULL)
6163 static const char *const vsx_regs[] = {
6164 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
6165 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
6166 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
6167 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
6168 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
6174 for (i = 0; i < ppc_num_vshrs; i++)
6175 valid_p &= tdesc_numbered_register (feature, tdesc_data,
6176 PPC_VSR0_UPPER_REGNUM + i,
6180 tdesc_data_cleanup (tdesc_data);
6189 /* On machines supporting the SPE APU, the general-purpose registers
6190 are 64 bits long. There are SIMD vector instructions to treat them
6191 as pairs of floats, but the rest of the instruction set treats them
6192 as 32-bit registers, and only operates on their lower halves.
6194 In the GDB regcache, we treat their high and low halves as separate
6195 registers. The low halves we present as the general-purpose
6196 registers, and then we have pseudo-registers that stitch together
6197 the upper and lower halves and present them as pseudo-registers.
6199 Thus, the target description is expected to supply the upper
6200 halves separately. */
6202 feature = tdesc_find_feature (tdesc,
6203 "org.gnu.gdb.power.spe");
6204 if (feature != NULL)
6206 static const char *const upper_spe[] = {
6207 "ev0h", "ev1h", "ev2h", "ev3h",
6208 "ev4h", "ev5h", "ev6h", "ev7h",
6209 "ev8h", "ev9h", "ev10h", "ev11h",
6210 "ev12h", "ev13h", "ev14h", "ev15h",
6211 "ev16h", "ev17h", "ev18h", "ev19h",
6212 "ev20h", "ev21h", "ev22h", "ev23h",
6213 "ev24h", "ev25h", "ev26h", "ev27h",
6214 "ev28h", "ev29h", "ev30h", "ev31h"
6218 for (i = 0; i < ppc_num_gprs; i++)
6219 valid_p &= tdesc_numbered_register (feature, tdesc_data,
6220 PPC_SPE_UPPER_GP0_REGNUM + i,
6222 valid_p &= tdesc_numbered_register (feature, tdesc_data,
6223 PPC_SPE_ACC_REGNUM, "acc");
6224 valid_p &= tdesc_numbered_register (feature, tdesc_data,
6225 PPC_SPE_FSCR_REGNUM, "spefscr");
6227 if (have_mq || have_fpu || !valid_p)
6229 tdesc_data_cleanup (tdesc_data);
6238 /* If we have a 64-bit binary on a 32-bit target, complain. Also
6239 complain for a 32-bit binary on a 64-bit target; we do not yet
6240 support that. For instance, the 32-bit ABI routines expect
6243 As long as there isn't an explicit target description, we'll
6244 choose one based on the BFD architecture and get a word size
6245 matching the binary (probably powerpc:common or
6246 powerpc:common64). So there is only trouble if a 64-bit target
6247 supplies a 64-bit description while debugging a 32-bit
6249 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
6251 tdesc_data_cleanup (tdesc_data);
6258 switch (elf_elfheader (info.abfd)->e_flags & EF_PPC64_ABI)
6261 elf_abi = POWERPC_ELF_V1;
6264 elf_abi = POWERPC_ELF_V2;
6271 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
6273 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
6274 Tag_GNU_Power_ABI_FP) & 3)
6277 soft_float_flag = AUTO_BOOLEAN_FALSE;
6280 soft_float_flag = AUTO_BOOLEAN_TRUE;
6287 if (long_double_abi == POWERPC_LONG_DOUBLE_AUTO && from_elf_exec)
6289 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
6290 Tag_GNU_Power_ABI_FP) >> 2)
6293 long_double_abi = POWERPC_LONG_DOUBLE_IBM128;
6296 long_double_abi = POWERPC_LONG_DOUBLE_IEEE128;
6303 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
6305 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
6306 Tag_GNU_Power_ABI_Vector))
6309 vector_abi = POWERPC_VEC_GENERIC;
6312 vector_abi = POWERPC_VEC_ALTIVEC;
6315 vector_abi = POWERPC_VEC_SPE;
6323 /* At this point, the only supported ELF-based 64-bit little-endian
6324 operating system is GNU/Linux, and this uses the ELFv2 ABI by
6325 default. All other supported ELF-based operating systems use the
6326 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
6327 e.g. because we run a legacy binary, or have attached to a process
6328 and have not found any associated binary file, set the default
6329 according to this heuristic. */
6330 if (elf_abi == POWERPC_ELF_AUTO)
6332 if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE)
6333 elf_abi = POWERPC_ELF_V2;
6335 elf_abi = POWERPC_ELF_V1;
6338 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
6340 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
6343 soft_float = !have_fpu;
6345 /* If we have a hard float binary or setting but no floating point
6346 registers, downgrade to soft float anyway. We're still somewhat
6347 useful in this scenario. */
6348 if (!soft_float && !have_fpu)
6351 /* Similarly for vector registers. */
6352 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
6353 vector_abi = POWERPC_VEC_GENERIC;
6355 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
6356 vector_abi = POWERPC_VEC_GENERIC;
6358 if (vector_abi == POWERPC_VEC_AUTO)
6361 vector_abi = POWERPC_VEC_ALTIVEC;
6363 vector_abi = POWERPC_VEC_SPE;
6365 vector_abi = POWERPC_VEC_GENERIC;
6368 /* Do not limit the vector ABI based on available hardware, since we
6369 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
6371 /* Find a candidate among extant architectures. */
6372 for (arches = gdbarch_list_lookup_by_info (arches, &info);
6374 arches = gdbarch_list_lookup_by_info (arches->next, &info))
6376 /* Word size in the various PowerPC bfd_arch_info structs isn't
6377 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
6378 separate word size check. */
6379 tdep = gdbarch_tdep (arches->gdbarch);
6380 if (tdep && tdep->elf_abi != elf_abi)
6382 if (tdep && tdep->soft_float != soft_float)
6384 if (tdep && tdep->long_double_abi != long_double_abi)
6386 if (tdep && tdep->vector_abi != vector_abi)
6388 if (tdep && tdep->wordsize == wordsize)
6390 if (tdesc_data != NULL)
6391 tdesc_data_cleanup (tdesc_data);
6392 return arches->gdbarch;
6396 /* None found, create a new architecture from INFO, whose bfd_arch_info
6397 validity depends on the source:
6398 - executable useless
6399 - rs6000_host_arch() good
6401 - "set arch" trust blindly
6402 - GDB startup useless but harmless */
6404 tdep = XCNEW (struct gdbarch_tdep);
6405 tdep->wordsize = wordsize;
6406 tdep->elf_abi = elf_abi;
6407 tdep->soft_float = soft_float;
6408 tdep->long_double_abi = long_double_abi;
6409 tdep->vector_abi = vector_abi;
6411 gdbarch = gdbarch_alloc (&info, tdep);
6413 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
6414 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
6415 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
6416 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
6417 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
6418 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
6419 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
6420 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
6422 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
6423 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
6424 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
6425 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
6426 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
6427 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
6428 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
6429 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
6431 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
6432 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
6433 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
6434 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
6436 /* The XML specification for PowerPC sensibly calls the MSR "msr".
6437 GDB traditionally called it "ps", though, so let GDB add an
6439 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
6442 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
6444 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
6446 /* Set lr_frame_offset. */
6448 tdep->lr_frame_offset = 16;
6450 tdep->lr_frame_offset = 4;
6452 if (have_spe || have_dfp || have_vsx)
6454 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
6455 set_gdbarch_pseudo_register_write (gdbarch,
6456 rs6000_pseudo_register_write);
6457 set_gdbarch_ax_pseudo_register_collect (gdbarch,
6458 rs6000_ax_pseudo_register_collect);
6461 set_gdbarch_gen_return_address (gdbarch, rs6000_gen_return_address);
6463 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
6465 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
6468 num_pseudoregs += 32;
6470 num_pseudoregs += 16;
6472 /* Include both VSX and Extended FP registers. */
6473 num_pseudoregs += 96;
6475 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
6477 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
6478 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
6479 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
6480 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
6481 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
6482 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
6483 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
6484 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
6485 set_gdbarch_char_signed (gdbarch, 0);
6487 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
6490 set_gdbarch_frame_red_zone_size (gdbarch, 288);
6492 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
6493 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
6494 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
6496 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
6497 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
6500 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
6501 else if (wordsize == 8)
6502 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
6504 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
6505 set_gdbarch_stack_frame_destroyed_p (gdbarch, rs6000_stack_frame_destroyed_p);
6506 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
6508 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6510 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
6511 rs6000_breakpoint::kind_from_pc);
6512 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
6513 rs6000_breakpoint::bp_from_kind);
6515 /* The value of symbols of type N_SO and N_FUN maybe null when
6517 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
6519 /* Handles single stepping of atomic sequences. */
6520 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
6522 /* Not sure on this. FIXMEmgo */
6523 set_gdbarch_frame_args_skip (gdbarch, 8);
6525 /* Helpers for function argument information. */
6526 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
6529 set_gdbarch_in_solib_return_trampoline
6530 (gdbarch, rs6000_in_solib_return_trampoline);
6531 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
6533 /* Hook in the DWARF CFI frame unwinder. */
6534 dwarf2_append_unwinders (gdbarch);
6535 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
6537 /* Frame handling. */
6538 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
6540 /* Setup displaced stepping. */
6541 set_gdbarch_displaced_step_copy_insn (gdbarch,
6542 ppc_displaced_step_copy_insn);
6543 set_gdbarch_displaced_step_hw_singlestep (gdbarch,
6544 ppc_displaced_step_hw_singlestep);
6545 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
6546 set_gdbarch_displaced_step_location (gdbarch,
6547 displaced_step_at_entry_point);
6549 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
6551 /* Hook in ABI-specific overrides, if they have been registered. */
6552 info.target_desc = tdesc;
6553 info.tdesc_data = tdesc_data;
6554 gdbarch_init_osabi (info, gdbarch);
6558 case GDB_OSABI_LINUX:
6559 case GDB_OSABI_NETBSD:
6560 case GDB_OSABI_UNKNOWN:
6561 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
6562 frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind);
6563 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
6564 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
6565 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
6568 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
6570 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
6571 frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind);
6572 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
6573 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
6574 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
6577 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
6578 set_tdesc_pseudo_register_reggroup_p (gdbarch,
6579 rs6000_pseudo_register_reggroup_p);
6580 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
6582 /* Override the normal target description method to make the SPE upper
6583 halves anonymous. */
6584 set_gdbarch_register_name (gdbarch, rs6000_register_name);
6586 /* Choose register numbers for all supported pseudo-registers. */
6587 tdep->ppc_ev0_regnum = -1;
6588 tdep->ppc_dl0_regnum = -1;
6589 tdep->ppc_vsr0_regnum = -1;
6590 tdep->ppc_efpr0_regnum = -1;
6592 cur_reg = gdbarch_num_regs (gdbarch);
6596 tdep->ppc_ev0_regnum = cur_reg;
6601 tdep->ppc_dl0_regnum = cur_reg;
6606 tdep->ppc_vsr0_regnum = cur_reg;
6608 tdep->ppc_efpr0_regnum = cur_reg;
6612 gdb_assert (gdbarch_num_regs (gdbarch)
6613 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
6615 /* Register the ravenscar_arch_ops. */
6616 if (mach == bfd_mach_ppc_e500)
6617 register_e500_ravenscar_ops (gdbarch);
6619 register_ppc_ravenscar_ops (gdbarch);
6621 set_gdbarch_disassembler_options (gdbarch, &powerpc_disassembler_options);
6622 set_gdbarch_valid_disassembler_options (gdbarch,
6623 disassembler_options_powerpc ());
6629 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
6631 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6636 /* FIXME: Dump gdbarch_tdep. */
6639 /* PowerPC-specific commands. */
6642 set_powerpc_command (const char *args, int from_tty)
6644 printf_unfiltered (_("\
6645 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6646 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
6650 show_powerpc_command (const char *args, int from_tty)
6652 cmd_show_list (showpowerpccmdlist, from_tty, "");
6656 powerpc_set_soft_float (const char *args, int from_tty,
6657 struct cmd_list_element *c)
6659 struct gdbarch_info info;
6661 /* Update the architecture. */
6662 gdbarch_info_init (&info);
6663 if (!gdbarch_update_p (info))
6664 internal_error (__FILE__, __LINE__, _("could not update architecture"));
6668 powerpc_set_vector_abi (const char *args, int from_tty,
6669 struct cmd_list_element *c)
6671 struct gdbarch_info info;
6674 for (vector_abi = POWERPC_VEC_AUTO;
6675 vector_abi != POWERPC_VEC_LAST;
6677 if (strcmp (powerpc_vector_abi_string,
6678 powerpc_vector_strings[vector_abi]) == 0)
6680 powerpc_vector_abi_global = (enum powerpc_vector_abi) vector_abi;
6684 if (vector_abi == POWERPC_VEC_LAST)
6685 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
6686 powerpc_vector_abi_string);
6688 /* Update the architecture. */
6689 gdbarch_info_init (&info);
6690 if (!gdbarch_update_p (info))
6691 internal_error (__FILE__, __LINE__, _("could not update architecture"));
6694 /* Show the current setting of the exact watchpoints flag. */
6697 show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty,
6698 struct cmd_list_element *c,
6701 fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value);
6704 /* Read a PPC instruction from memory. */
6707 read_insn (struct frame_info *frame, CORE_ADDR pc)
6709 struct gdbarch *gdbarch = get_frame_arch (frame);
6710 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6712 return read_memory_unsigned_integer (pc, 4, byte_order);
6715 /* Return non-zero if the instructions at PC match the series
6716 described in PATTERN, or zero otherwise. PATTERN is an array of
6717 'struct ppc_insn_pattern' objects, terminated by an entry whose
6720 When the match is successful, fill INSN[i] with what PATTERN[i]
6721 matched. If PATTERN[i] is optional, and the instruction wasn't
6722 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6723 INSN should have as many elements as PATTERN. Note that, if
6724 PATTERN contains optional instructions which aren't present in
6725 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6726 i'th instruction in memory. */
6729 ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
6730 struct ppc_insn_pattern *pattern,
6731 unsigned int *insns)
6736 for (i = 0, insn = 0; pattern[i].mask; i++)
6739 insn = read_insn (frame, pc);
6741 if ((insn & pattern[i].mask) == pattern[i].data)
6747 else if (!pattern[i].optional)
6754 /* Return the 'd' field of the d-form instruction INSN, properly
6758 ppc_insn_d_field (unsigned int insn)
6760 return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000);
6763 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6764 zero bits concatenated at the right, and properly
6768 ppc_insn_ds_field (unsigned int insn)
6770 return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000);
6773 /* Initialization code. */
6776 _initialize_rs6000_tdep (void)
6778 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
6779 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
6781 /* Initialize the standard target descriptions. */
6782 initialize_tdesc_powerpc_32 ();
6783 initialize_tdesc_powerpc_altivec32 ();
6784 initialize_tdesc_powerpc_vsx32 ();
6785 initialize_tdesc_powerpc_403 ();
6786 initialize_tdesc_powerpc_403gc ();
6787 initialize_tdesc_powerpc_405 ();
6788 initialize_tdesc_powerpc_505 ();
6789 initialize_tdesc_powerpc_601 ();
6790 initialize_tdesc_powerpc_602 ();
6791 initialize_tdesc_powerpc_603 ();
6792 initialize_tdesc_powerpc_604 ();
6793 initialize_tdesc_powerpc_64 ();
6794 initialize_tdesc_powerpc_altivec64 ();
6795 initialize_tdesc_powerpc_vsx64 ();
6796 initialize_tdesc_powerpc_7400 ();
6797 initialize_tdesc_powerpc_750 ();
6798 initialize_tdesc_powerpc_860 ();
6799 initialize_tdesc_powerpc_e500 ();
6800 initialize_tdesc_rs6000 ();
6802 /* Add root prefix command for all "set powerpc"/"show powerpc"
6804 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
6805 _("Various PowerPC-specific commands."),
6806 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
6808 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
6809 _("Various PowerPC-specific commands."),
6810 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
6812 /* Add a command to allow the user to force the ABI. */
6813 add_setshow_auto_boolean_cmd ("soft-float", class_support,
6814 &powerpc_soft_float_global,
6815 _("Set whether to use a soft-float ABI."),
6816 _("Show whether to use a soft-float ABI."),
6818 powerpc_set_soft_float, NULL,
6819 &setpowerpccmdlist, &showpowerpccmdlist);
6821 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
6822 &powerpc_vector_abi_string,
6823 _("Set the vector ABI."),
6824 _("Show the vector ABI."),
6825 NULL, powerpc_set_vector_abi, NULL,
6826 &setpowerpccmdlist, &showpowerpccmdlist);
6828 add_setshow_boolean_cmd ("exact-watchpoints", class_support,
6829 &target_exact_watchpoints,
6831 Set whether to use just one debug register for watchpoints on scalars."),
6833 Show whether to use just one debug register for watchpoints on scalars."),
6835 If true, GDB will use only one debug register when watching a variable of\n\
6836 scalar type, thus assuming that the variable is accessed through the address\n\
6837 of its first byte."),
6838 NULL, show_powerpc_exact_watchpoints,
6839 &setpowerpccmdlist, &showpowerpccmdlist);