1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 1986-2016 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
29 #include "arch-utils.h"
34 #include "parser-defs.h"
37 #include "sim-regno.h"
38 #include "gdb/sim-ppc.h"
39 #include "reggroups.h"
40 #include "dwarf2-frame.h"
41 #include "target-descriptions.h"
42 #include "user-regs.h"
43 #include "record-full.h"
46 #include "libbfd.h" /* for bfd_default_set_arch_mach */
47 #include "coff/internal.h" /* for libcoff.h */
48 #include "libcoff.h" /* for xcoff_data */
49 #include "coff/xcoff.h"
54 #include "elf/ppc64.h"
56 #include "solib-svr4.h"
58 #include "ppc-ravenscar-thread.h"
62 #include "trad-frame.h"
63 #include "frame-unwind.h"
64 #include "frame-base.h"
69 #include "features/rs6000/powerpc-32.c"
70 #include "features/rs6000/powerpc-altivec32.c"
71 #include "features/rs6000/powerpc-vsx32.c"
72 #include "features/rs6000/powerpc-403.c"
73 #include "features/rs6000/powerpc-403gc.c"
74 #include "features/rs6000/powerpc-405.c"
75 #include "features/rs6000/powerpc-505.c"
76 #include "features/rs6000/powerpc-601.c"
77 #include "features/rs6000/powerpc-602.c"
78 #include "features/rs6000/powerpc-603.c"
79 #include "features/rs6000/powerpc-604.c"
80 #include "features/rs6000/powerpc-64.c"
81 #include "features/rs6000/powerpc-altivec64.c"
82 #include "features/rs6000/powerpc-vsx64.c"
83 #include "features/rs6000/powerpc-7400.c"
84 #include "features/rs6000/powerpc-750.c"
85 #include "features/rs6000/powerpc-860.c"
86 #include "features/rs6000/powerpc-e500.c"
87 #include "features/rs6000/rs6000.c"
89 /* Determine if regnum is an SPE pseudo-register. */
90 #define IS_SPE_PSEUDOREG(tdep, regnum) ((tdep)->ppc_ev0_regnum >= 0 \
91 && (regnum) >= (tdep)->ppc_ev0_regnum \
92 && (regnum) < (tdep)->ppc_ev0_regnum + 32)
94 /* Determine if regnum is a decimal float pseudo-register. */
95 #define IS_DFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_dl0_regnum >= 0 \
96 && (regnum) >= (tdep)->ppc_dl0_regnum \
97 && (regnum) < (tdep)->ppc_dl0_regnum + 16)
99 /* Determine if regnum is a POWER7 VSX register. */
100 #define IS_VSX_PSEUDOREG(tdep, regnum) ((tdep)->ppc_vsr0_regnum >= 0 \
101 && (regnum) >= (tdep)->ppc_vsr0_regnum \
102 && (regnum) < (tdep)->ppc_vsr0_regnum + ppc_num_vsrs)
104 /* Determine if regnum is a POWER7 Extended FP register. */
105 #define IS_EFP_PSEUDOREG(tdep, regnum) ((tdep)->ppc_efpr0_regnum >= 0 \
106 && (regnum) >= (tdep)->ppc_efpr0_regnum \
107 && (regnum) < (tdep)->ppc_efpr0_regnum + ppc_num_efprs)
109 /* The list of available "set powerpc ..." and "show powerpc ..."
111 static struct cmd_list_element *setpowerpccmdlist = NULL;
112 static struct cmd_list_element *showpowerpccmdlist = NULL;
114 static enum auto_boolean powerpc_soft_float_global = AUTO_BOOLEAN_AUTO;
116 /* The vector ABI to use. Keep this in sync with powerpc_vector_abi. */
117 static const char *const powerpc_vector_strings[] =
126 /* A variable that can be configured by the user. */
127 static enum powerpc_vector_abi powerpc_vector_abi_global = POWERPC_VEC_AUTO;
128 static const char *powerpc_vector_abi_string = "auto";
130 /* To be used by skip_prologue. */
132 struct rs6000_framedata
134 int offset; /* total size of frame --- the distance
135 by which we decrement sp to allocate
137 int saved_gpr; /* smallest # of saved gpr */
138 unsigned int gpr_mask; /* Each bit is an individual saved GPR. */
139 int saved_fpr; /* smallest # of saved fpr */
140 int saved_vr; /* smallest # of saved vr */
141 int saved_ev; /* smallest # of saved ev */
142 int alloca_reg; /* alloca register number (frame ptr) */
143 char frameless; /* true if frameless functions. */
144 char nosavedpc; /* true if pc not saved. */
145 char used_bl; /* true if link register clobbered */
146 int gpr_offset; /* offset of saved gprs from prev sp */
147 int fpr_offset; /* offset of saved fprs from prev sp */
148 int vr_offset; /* offset of saved vrs from prev sp */
149 int ev_offset; /* offset of saved evs from prev sp */
150 int lr_offset; /* offset of saved lr */
151 int lr_register; /* register of saved lr, if trustworthy */
152 int cr_offset; /* offset of saved cr */
153 int vrsave_offset; /* offset of saved vrsave register */
157 /* Is REGNO a VSX register? Return 1 if so, 0 otherwise. */
159 vsx_register_p (struct gdbarch *gdbarch, int regno)
161 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
162 if (tdep->ppc_vsr0_regnum < 0)
165 return (regno >= tdep->ppc_vsr0_upper_regnum && regno
166 <= tdep->ppc_vsr0_upper_regnum + 31);
169 /* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */
171 altivec_register_p (struct gdbarch *gdbarch, int regno)
173 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
174 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0)
177 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum);
181 /* Return true if REGNO is an SPE register, false otherwise. */
183 spe_register_p (struct gdbarch *gdbarch, int regno)
185 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
187 /* Is it a reference to EV0 -- EV31, and do we have those? */
188 if (IS_SPE_PSEUDOREG (tdep, regno))
191 /* Is it a reference to one of the raw upper GPR halves? */
192 if (tdep->ppc_ev0_upper_regnum >= 0
193 && tdep->ppc_ev0_upper_regnum <= regno
194 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
197 /* Is it a reference to the 64-bit accumulator, and do we have that? */
198 if (tdep->ppc_acc_regnum >= 0
199 && tdep->ppc_acc_regnum == regno)
202 /* Is it a reference to the SPE floating-point status and control register,
203 and do we have that? */
204 if (tdep->ppc_spefscr_regnum >= 0
205 && tdep->ppc_spefscr_regnum == regno)
212 /* Return non-zero if the architecture described by GDBARCH has
213 floating-point registers (f0 --- f31 and fpscr). */
215 ppc_floating_point_unit_p (struct gdbarch *gdbarch)
217 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
219 return (tdep->ppc_fp0_regnum >= 0
220 && tdep->ppc_fpscr_regnum >= 0);
223 /* Return non-zero if the architecture described by GDBARCH has
224 VSX registers (vsr0 --- vsr63). */
226 ppc_vsx_support_p (struct gdbarch *gdbarch)
228 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
230 return tdep->ppc_vsr0_regnum >= 0;
233 /* Return non-zero if the architecture described by GDBARCH has
234 Altivec registers (vr0 --- vr31, vrsave and vscr). */
236 ppc_altivec_support_p (struct gdbarch *gdbarch)
238 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
240 return (tdep->ppc_vr0_regnum >= 0
241 && tdep->ppc_vrsave_regnum >= 0);
244 /* Check that TABLE[GDB_REGNO] is not already initialized, and then
247 This is a helper function for init_sim_regno_table, constructing
248 the table mapping GDB register numbers to sim register numbers; we
249 initialize every element in that table to -1 before we start
252 set_sim_regno (int *table, int gdb_regno, int sim_regno)
254 /* Make sure we don't try to assign any given GDB register a sim
255 register number more than once. */
256 gdb_assert (table[gdb_regno] == -1);
257 table[gdb_regno] = sim_regno;
261 /* Initialize ARCH->tdep->sim_regno, the table mapping GDB register
262 numbers to simulator register numbers, based on the values placed
263 in the ARCH->tdep->ppc_foo_regnum members. */
265 init_sim_regno_table (struct gdbarch *arch)
267 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
268 int total_regs = gdbarch_num_regs (arch);
269 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int);
271 static const char *const segment_regs[] = {
272 "sr0", "sr1", "sr2", "sr3", "sr4", "sr5", "sr6", "sr7",
273 "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15"
276 /* Presume that all registers not explicitly mentioned below are
277 unavailable from the sim. */
278 for (i = 0; i < total_regs; i++)
281 /* General-purpose registers. */
282 for (i = 0; i < ppc_num_gprs; i++)
283 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i);
285 /* Floating-point registers. */
286 if (tdep->ppc_fp0_regnum >= 0)
287 for (i = 0; i < ppc_num_fprs; i++)
288 set_sim_regno (sim_regno,
289 tdep->ppc_fp0_regnum + i,
290 sim_ppc_f0_regnum + i);
291 if (tdep->ppc_fpscr_regnum >= 0)
292 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum);
294 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum);
295 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum);
296 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum);
298 /* Segment registers. */
299 for (i = 0; i < ppc_num_srs; i++)
303 gdb_regno = user_reg_map_name_to_regnum (arch, segment_regs[i], -1);
305 set_sim_regno (sim_regno, gdb_regno, sim_ppc_sr0_regnum + i);
308 /* Altivec registers. */
309 if (tdep->ppc_vr0_regnum >= 0)
311 for (i = 0; i < ppc_num_vrs; i++)
312 set_sim_regno (sim_regno,
313 tdep->ppc_vr0_regnum + i,
314 sim_ppc_vr0_regnum + i);
316 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum,
317 we can treat this more like the other cases. */
318 set_sim_regno (sim_regno,
319 tdep->ppc_vr0_regnum + ppc_num_vrs,
320 sim_ppc_vscr_regnum);
322 /* vsave is a special-purpose register, so the code below handles it. */
324 /* SPE APU (E500) registers. */
325 if (tdep->ppc_ev0_upper_regnum >= 0)
326 for (i = 0; i < ppc_num_gprs; i++)
327 set_sim_regno (sim_regno,
328 tdep->ppc_ev0_upper_regnum + i,
329 sim_ppc_rh0_regnum + i);
330 if (tdep->ppc_acc_regnum >= 0)
331 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum);
332 /* spefscr is a special-purpose register, so the code below handles it. */
335 /* Now handle all special-purpose registers. Verify that they
336 haven't mistakenly been assigned numbers by any of the above
338 for (i = 0; i < sim_ppc_num_sprs; i++)
340 const char *spr_name = sim_spr_register_name (i);
343 if (spr_name != NULL)
344 gdb_regno = user_reg_map_name_to_regnum (arch, spr_name, -1);
347 set_sim_regno (sim_regno, gdb_regno, sim_ppc_spr0_regnum + i);
351 /* Drop the initialized array into place. */
352 tdep->sim_regno = sim_regno;
356 /* Given a GDB register number REG, return the corresponding SIM
359 rs6000_register_sim_regno (struct gdbarch *gdbarch, int reg)
361 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
364 if (tdep->sim_regno == NULL)
365 init_sim_regno_table (gdbarch);
368 && reg <= gdbarch_num_regs (gdbarch)
369 + gdbarch_num_pseudo_regs (gdbarch));
370 sim_regno = tdep->sim_regno[reg];
375 return LEGACY_SIM_REGNO_IGNORE;
380 /* Register set support functions. */
382 /* REGS + OFFSET contains register REGNUM in a field REGSIZE wide.
383 Write the register to REGCACHE. */
386 ppc_supply_reg (struct regcache *regcache, int regnum,
387 const gdb_byte *regs, size_t offset, int regsize)
389 if (regnum != -1 && offset != -1)
393 struct gdbarch *gdbarch = get_regcache_arch (regcache);
394 int gdb_regsize = register_size (gdbarch, regnum);
395 if (gdb_regsize < regsize
396 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
397 offset += regsize - gdb_regsize;
399 regcache_raw_supply (regcache, regnum, regs + offset);
403 /* Read register REGNUM from REGCACHE and store to REGS + OFFSET
404 in a field REGSIZE wide. Zero pad as necessary. */
407 ppc_collect_reg (const struct regcache *regcache, int regnum,
408 gdb_byte *regs, size_t offset, int regsize)
410 if (regnum != -1 && offset != -1)
414 struct gdbarch *gdbarch = get_regcache_arch (regcache);
415 int gdb_regsize = register_size (gdbarch, regnum);
416 if (gdb_regsize < regsize)
418 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
420 memset (regs + offset, 0, regsize - gdb_regsize);
421 offset += regsize - gdb_regsize;
424 memset (regs + offset + regsize - gdb_regsize, 0,
425 regsize - gdb_regsize);
428 regcache_raw_collect (regcache, regnum, regs + offset);
433 ppc_greg_offset (struct gdbarch *gdbarch,
434 struct gdbarch_tdep *tdep,
435 const struct ppc_reg_offsets *offsets,
439 *regsize = offsets->gpr_size;
440 if (regnum >= tdep->ppc_gp0_regnum
441 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs)
442 return (offsets->r0_offset
443 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size);
445 if (regnum == gdbarch_pc_regnum (gdbarch))
446 return offsets->pc_offset;
448 if (regnum == tdep->ppc_ps_regnum)
449 return offsets->ps_offset;
451 if (regnum == tdep->ppc_lr_regnum)
452 return offsets->lr_offset;
454 if (regnum == tdep->ppc_ctr_regnum)
455 return offsets->ctr_offset;
457 *regsize = offsets->xr_size;
458 if (regnum == tdep->ppc_cr_regnum)
459 return offsets->cr_offset;
461 if (regnum == tdep->ppc_xer_regnum)
462 return offsets->xer_offset;
464 if (regnum == tdep->ppc_mq_regnum)
465 return offsets->mq_offset;
471 ppc_fpreg_offset (struct gdbarch_tdep *tdep,
472 const struct ppc_reg_offsets *offsets,
475 if (regnum >= tdep->ppc_fp0_regnum
476 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs)
477 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8;
479 if (regnum == tdep->ppc_fpscr_regnum)
480 return offsets->fpscr_offset;
486 ppc_vrreg_offset (struct gdbarch_tdep *tdep,
487 const struct ppc_reg_offsets *offsets,
490 if (regnum >= tdep->ppc_vr0_regnum
491 && regnum < tdep->ppc_vr0_regnum + ppc_num_vrs)
492 return offsets->vr0_offset + (regnum - tdep->ppc_vr0_regnum) * 16;
494 if (regnum == tdep->ppc_vrsave_regnum - 1)
495 return offsets->vscr_offset;
497 if (regnum == tdep->ppc_vrsave_regnum)
498 return offsets->vrsave_offset;
503 /* Supply register REGNUM in the general-purpose register set REGSET
504 from the buffer specified by GREGS and LEN to register cache
505 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
508 ppc_supply_gregset (const struct regset *regset, struct regcache *regcache,
509 int regnum, const void *gregs, size_t len)
511 struct gdbarch *gdbarch = get_regcache_arch (regcache);
512 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
513 const struct ppc_reg_offsets *offsets
514 = (const struct ppc_reg_offsets *) regset->regmap;
521 int gpr_size = offsets->gpr_size;
523 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
524 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
525 i++, offset += gpr_size)
526 ppc_supply_reg (regcache, i, (const gdb_byte *) gregs, offset,
529 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch),
530 (const gdb_byte *) gregs, offsets->pc_offset, gpr_size);
531 ppc_supply_reg (regcache, tdep->ppc_ps_regnum,
532 (const gdb_byte *) gregs, offsets->ps_offset, gpr_size);
533 ppc_supply_reg (regcache, tdep->ppc_lr_regnum,
534 (const gdb_byte *) gregs, offsets->lr_offset, gpr_size);
535 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum,
536 (const gdb_byte *) gregs, offsets->ctr_offset, gpr_size);
537 ppc_supply_reg (regcache, tdep->ppc_cr_regnum,
538 (const gdb_byte *) gregs, offsets->cr_offset,
540 ppc_supply_reg (regcache, tdep->ppc_xer_regnum,
541 (const gdb_byte *) gregs, offsets->xer_offset,
543 ppc_supply_reg (regcache, tdep->ppc_mq_regnum,
544 (const gdb_byte *) gregs, offsets->mq_offset,
549 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
550 ppc_supply_reg (regcache, regnum, (const gdb_byte *) gregs, offset, regsize);
553 /* Supply register REGNUM in the floating-point register set REGSET
554 from the buffer specified by FPREGS and LEN to register cache
555 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
558 ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache,
559 int regnum, const void *fpregs, size_t len)
561 struct gdbarch *gdbarch = get_regcache_arch (regcache);
562 struct gdbarch_tdep *tdep;
563 const struct ppc_reg_offsets *offsets;
566 if (!ppc_floating_point_unit_p (gdbarch))
569 tdep = gdbarch_tdep (gdbarch);
570 offsets = (const struct ppc_reg_offsets *) regset->regmap;
575 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
576 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
578 ppc_supply_reg (regcache, i, (const gdb_byte *) fpregs, offset, 8);
580 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum,
581 (const gdb_byte *) fpregs, offsets->fpscr_offset,
582 offsets->fpscr_size);
586 offset = ppc_fpreg_offset (tdep, offsets, regnum);
587 ppc_supply_reg (regcache, regnum, (const gdb_byte *) fpregs, offset,
588 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
591 /* Supply register REGNUM in the VSX register set REGSET
592 from the buffer specified by VSXREGS and LEN to register cache
593 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
596 ppc_supply_vsxregset (const struct regset *regset, struct regcache *regcache,
597 int regnum, const void *vsxregs, size_t len)
599 struct gdbarch *gdbarch = get_regcache_arch (regcache);
600 struct gdbarch_tdep *tdep;
602 if (!ppc_vsx_support_p (gdbarch))
605 tdep = gdbarch_tdep (gdbarch);
611 for (i = tdep->ppc_vsr0_upper_regnum;
612 i < tdep->ppc_vsr0_upper_regnum + 32;
614 ppc_supply_reg (regcache, i, (const gdb_byte *) vsxregs, 0, 8);
619 ppc_supply_reg (regcache, regnum, (const gdb_byte *) vsxregs, 0, 8);
622 /* Supply register REGNUM in the Altivec register set REGSET
623 from the buffer specified by VRREGS and LEN to register cache
624 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
627 ppc_supply_vrregset (const struct regset *regset, struct regcache *regcache,
628 int regnum, const void *vrregs, size_t len)
630 struct gdbarch *gdbarch = get_regcache_arch (regcache);
631 struct gdbarch_tdep *tdep;
632 const struct ppc_reg_offsets *offsets;
635 if (!ppc_altivec_support_p (gdbarch))
638 tdep = gdbarch_tdep (gdbarch);
639 offsets = (const struct ppc_reg_offsets *) regset->regmap;
644 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
645 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
647 ppc_supply_reg (regcache, i, (const gdb_byte *) vrregs, offset, 16);
649 ppc_supply_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
650 (const gdb_byte *) vrregs, offsets->vscr_offset, 4);
652 ppc_supply_reg (regcache, tdep->ppc_vrsave_regnum,
653 (const gdb_byte *) vrregs, offsets->vrsave_offset, 4);
657 offset = ppc_vrreg_offset (tdep, offsets, regnum);
658 if (regnum != tdep->ppc_vrsave_regnum
659 && regnum != tdep->ppc_vrsave_regnum - 1)
660 ppc_supply_reg (regcache, regnum, (const gdb_byte *) vrregs, offset, 16);
662 ppc_supply_reg (regcache, regnum,
663 (const gdb_byte *) vrregs, offset, 4);
666 /* Collect register REGNUM in the general-purpose register set
667 REGSET from register cache REGCACHE into the buffer specified by
668 GREGS and LEN. If REGNUM is -1, do this for all registers in
672 ppc_collect_gregset (const struct regset *regset,
673 const struct regcache *regcache,
674 int regnum, void *gregs, size_t len)
676 struct gdbarch *gdbarch = get_regcache_arch (regcache);
677 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
678 const struct ppc_reg_offsets *offsets
679 = (const struct ppc_reg_offsets *) regset->regmap;
686 int gpr_size = offsets->gpr_size;
688 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset;
689 i < tdep->ppc_gp0_regnum + ppc_num_gprs;
690 i++, offset += gpr_size)
691 ppc_collect_reg (regcache, i, (gdb_byte *) gregs, offset, gpr_size);
693 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch),
694 (gdb_byte *) gregs, offsets->pc_offset, gpr_size);
695 ppc_collect_reg (regcache, tdep->ppc_ps_regnum,
696 (gdb_byte *) gregs, offsets->ps_offset, gpr_size);
697 ppc_collect_reg (regcache, tdep->ppc_lr_regnum,
698 (gdb_byte *) gregs, offsets->lr_offset, gpr_size);
699 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum,
700 (gdb_byte *) gregs, offsets->ctr_offset, gpr_size);
701 ppc_collect_reg (regcache, tdep->ppc_cr_regnum,
702 (gdb_byte *) gregs, offsets->cr_offset,
704 ppc_collect_reg (regcache, tdep->ppc_xer_regnum,
705 (gdb_byte *) gregs, offsets->xer_offset,
707 ppc_collect_reg (regcache, tdep->ppc_mq_regnum,
708 (gdb_byte *) gregs, offsets->mq_offset,
713 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size);
714 ppc_collect_reg (regcache, regnum, (gdb_byte *) gregs, offset, regsize);
717 /* Collect register REGNUM in the floating-point register set
718 REGSET from register cache REGCACHE into the buffer specified by
719 FPREGS and LEN. If REGNUM is -1, do this for all registers in
723 ppc_collect_fpregset (const struct regset *regset,
724 const struct regcache *regcache,
725 int regnum, void *fpregs, size_t len)
727 struct gdbarch *gdbarch = get_regcache_arch (regcache);
728 struct gdbarch_tdep *tdep;
729 const struct ppc_reg_offsets *offsets;
732 if (!ppc_floating_point_unit_p (gdbarch))
735 tdep = gdbarch_tdep (gdbarch);
736 offsets = (const struct ppc_reg_offsets *) regset->regmap;
741 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset;
742 i < tdep->ppc_fp0_regnum + ppc_num_fprs;
744 ppc_collect_reg (regcache, i, (gdb_byte *) fpregs, offset, 8);
746 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum,
747 (gdb_byte *) fpregs, offsets->fpscr_offset,
748 offsets->fpscr_size);
752 offset = ppc_fpreg_offset (tdep, offsets, regnum);
753 ppc_collect_reg (regcache, regnum, (gdb_byte *) fpregs, offset,
754 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8);
757 /* Collect register REGNUM in the VSX register set
758 REGSET from register cache REGCACHE into the buffer specified by
759 VSXREGS and LEN. If REGNUM is -1, do this for all registers in
763 ppc_collect_vsxregset (const struct regset *regset,
764 const struct regcache *regcache,
765 int regnum, void *vsxregs, size_t len)
767 struct gdbarch *gdbarch = get_regcache_arch (regcache);
768 struct gdbarch_tdep *tdep;
770 if (!ppc_vsx_support_p (gdbarch))
773 tdep = gdbarch_tdep (gdbarch);
779 for (i = tdep->ppc_vsr0_upper_regnum;
780 i < tdep->ppc_vsr0_upper_regnum + 32;
782 ppc_collect_reg (regcache, i, (gdb_byte *) vsxregs, 0, 8);
787 ppc_collect_reg (regcache, regnum, (gdb_byte *) vsxregs, 0, 8);
791 /* Collect register REGNUM in the Altivec register set
792 REGSET from register cache REGCACHE into the buffer specified by
793 VRREGS and LEN. If REGNUM is -1, do this for all registers in
797 ppc_collect_vrregset (const struct regset *regset,
798 const struct regcache *regcache,
799 int regnum, void *vrregs, size_t len)
801 struct gdbarch *gdbarch = get_regcache_arch (regcache);
802 struct gdbarch_tdep *tdep;
803 const struct ppc_reg_offsets *offsets;
806 if (!ppc_altivec_support_p (gdbarch))
809 tdep = gdbarch_tdep (gdbarch);
810 offsets = (const struct ppc_reg_offsets *) regset->regmap;
815 for (i = tdep->ppc_vr0_regnum, offset = offsets->vr0_offset;
816 i < tdep->ppc_vr0_regnum + ppc_num_vrs;
818 ppc_collect_reg (regcache, i, (gdb_byte *) vrregs, offset, 16);
820 ppc_collect_reg (regcache, (tdep->ppc_vrsave_regnum - 1),
821 (gdb_byte *) vrregs, offsets->vscr_offset, 4);
823 ppc_collect_reg (regcache, tdep->ppc_vrsave_regnum,
824 (gdb_byte *) vrregs, offsets->vrsave_offset, 4);
828 offset = ppc_vrreg_offset (tdep, offsets, regnum);
829 if (regnum != tdep->ppc_vrsave_regnum
830 && regnum != tdep->ppc_vrsave_regnum - 1)
831 ppc_collect_reg (regcache, regnum, (gdb_byte *) vrregs, offset, 16);
833 ppc_collect_reg (regcache, regnum,
834 (gdb_byte *) vrregs, offset, 4);
839 insn_changes_sp_or_jumps (unsigned long insn)
841 int opcode = (insn >> 26) & 0x03f;
842 int sd = (insn >> 21) & 0x01f;
843 int a = (insn >> 16) & 0x01f;
844 int subcode = (insn >> 1) & 0x3ff;
846 /* Changes the stack pointer. */
848 /* NOTE: There are many ways to change the value of a given register.
849 The ways below are those used when the register is R1, the SP,
850 in a funtion's epilogue. */
852 if (opcode == 31 && subcode == 444 && a == 1)
853 return 1; /* mr R1,Rn */
854 if (opcode == 14 && sd == 1)
855 return 1; /* addi R1,Rn,simm */
856 if (opcode == 58 && sd == 1)
857 return 1; /* ld R1,ds(Rn) */
859 /* Transfers control. */
865 if (opcode == 19 && subcode == 16)
867 if (opcode == 19 && subcode == 528)
868 return 1; /* bcctr */
873 /* Return true if we are in the function's epilogue, i.e. after the
874 instruction that destroyed the function's stack frame.
876 1) scan forward from the point of execution:
877 a) If you find an instruction that modifies the stack pointer
878 or transfers control (except a return), execution is not in
880 b) Stop scanning if you find a return instruction or reach the
881 end of the function or reach the hard limit for the size of
883 2) scan backward from the point of execution:
884 a) If you find an instruction that modifies the stack pointer,
885 execution *is* in an epilogue, return.
886 b) Stop scanning if you reach an instruction that transfers
887 control or the beginning of the function or reach the hard
888 limit for the size of an epilogue. */
891 rs6000_in_function_epilogue_frame_p (struct frame_info *curfrm,
892 struct gdbarch *gdbarch, CORE_ADDR pc)
894 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
895 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
896 bfd_byte insn_buf[PPC_INSN_SIZE];
897 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end;
900 /* Find the search limits based on function boundaries and hard limit. */
902 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
905 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
906 if (epilogue_start < func_start) epilogue_start = func_start;
908 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE;
909 if (epilogue_end > func_end) epilogue_end = func_end;
911 /* Scan forward until next 'blr'. */
913 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE)
915 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
917 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
918 if (insn == 0x4e800020)
920 /* Assume a bctr is a tail call unless it points strictly within
922 if (insn == 0x4e800420)
924 CORE_ADDR ctr = get_frame_register_unsigned (curfrm,
925 tdep->ppc_ctr_regnum);
926 if (ctr > func_start && ctr < func_end)
931 if (insn_changes_sp_or_jumps (insn))
935 /* Scan backward until adjustment to stack pointer (R1). */
937 for (scan_pc = pc - PPC_INSN_SIZE;
938 scan_pc >= epilogue_start;
939 scan_pc -= PPC_INSN_SIZE)
941 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE))
943 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE, byte_order);
944 if (insn_changes_sp_or_jumps (insn))
951 /* Implement the stack_frame_destroyed_p gdbarch method. */
954 rs6000_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
956 return rs6000_in_function_epilogue_frame_p (get_current_frame (),
960 /* Get the ith function argument for the current function. */
962 rs6000_fetch_pointer_argument (struct frame_info *frame, int argi,
965 return get_frame_register_unsigned (frame, 3 + argi);
968 /* Sequence of bytes for breakpoint instruction. */
970 static const unsigned char *
971 rs6000_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *bp_addr,
974 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 };
975 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d };
977 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
978 return big_breakpoint;
980 return little_breakpoint;
983 /* Instruction masks for displaced stepping. */
984 #define BRANCH_MASK 0xfc000000
985 #define BP_MASK 0xFC0007FE
986 #define B_INSN 0x48000000
987 #define BC_INSN 0x40000000
988 #define BXL_INSN 0x4c000000
989 #define BP_INSN 0x7C000008
991 /* Instruction masks used during single-stepping of atomic
993 #define LWARX_MASK 0xfc0007fe
994 #define LWARX_INSTRUCTION 0x7c000028
995 #define LDARX_INSTRUCTION 0x7c0000A8
996 #define STWCX_MASK 0xfc0007ff
997 #define STWCX_INSTRUCTION 0x7c00012d
998 #define STDCX_INSTRUCTION 0x7c0001ad
1000 /* We can't displaced step atomic sequences. Otherwise this is just
1001 like simple_displaced_step_copy_insn. */
1003 static struct displaced_step_closure *
1004 ppc_displaced_step_copy_insn (struct gdbarch *gdbarch,
1005 CORE_ADDR from, CORE_ADDR to,
1006 struct regcache *regs)
1008 size_t len = gdbarch_max_insn_length (gdbarch);
1009 gdb_byte *buf = (gdb_byte *) xmalloc (len);
1010 struct cleanup *old_chain = make_cleanup (xfree, buf);
1011 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1014 read_memory (from, buf, len);
1016 insn = extract_signed_integer (buf, PPC_INSN_SIZE, byte_order);
1018 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1019 if ((insn & LWARX_MASK) == LWARX_INSTRUCTION
1020 || (insn & LWARX_MASK) == LDARX_INSTRUCTION)
1022 if (debug_displaced)
1024 fprintf_unfiltered (gdb_stdlog,
1025 "displaced: can't displaced step "
1026 "atomic sequence at %s\n",
1027 paddress (gdbarch, from));
1029 do_cleanups (old_chain);
1033 write_memory (to, buf, len);
1035 if (debug_displaced)
1037 fprintf_unfiltered (gdb_stdlog, "displaced: copy %s->%s: ",
1038 paddress (gdbarch, from), paddress (gdbarch, to));
1039 displaced_step_dump_bytes (gdb_stdlog, buf, len);
1042 discard_cleanups (old_chain);
1043 return (struct displaced_step_closure *) buf;
1046 /* Fix up the state of registers and memory after having single-stepped
1047 a displaced instruction. */
1049 ppc_displaced_step_fixup (struct gdbarch *gdbarch,
1050 struct displaced_step_closure *closure,
1051 CORE_ADDR from, CORE_ADDR to,
1052 struct regcache *regs)
1054 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1055 /* Our closure is a copy of the instruction. */
1056 ULONGEST insn = extract_unsigned_integer ((gdb_byte *) closure,
1057 PPC_INSN_SIZE, byte_order);
1058 ULONGEST opcode = 0;
1059 /* Offset for non PC-relative instructions. */
1060 LONGEST offset = PPC_INSN_SIZE;
1062 opcode = insn & BRANCH_MASK;
1064 if (debug_displaced)
1065 fprintf_unfiltered (gdb_stdlog,
1066 "displaced: (ppc) fixup (%s, %s)\n",
1067 paddress (gdbarch, from), paddress (gdbarch, to));
1070 /* Handle PC-relative branch instructions. */
1071 if (opcode == B_INSN || opcode == BC_INSN || opcode == BXL_INSN)
1073 ULONGEST current_pc;
1075 /* Read the current PC value after the instruction has been executed
1076 in a displaced location. Calculate the offset to be applied to the
1077 original PC value before the displaced stepping. */
1078 regcache_cooked_read_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1080 offset = current_pc - to;
1082 if (opcode != BXL_INSN)
1084 /* Check for AA bit indicating whether this is an absolute
1085 addressing or PC-relative (1: absolute, 0: relative). */
1088 /* PC-relative addressing is being used in the branch. */
1089 if (debug_displaced)
1092 "displaced: (ppc) branch instruction: %s\n"
1093 "displaced: (ppc) adjusted PC from %s to %s\n",
1094 paddress (gdbarch, insn), paddress (gdbarch, current_pc),
1095 paddress (gdbarch, from + offset));
1097 regcache_cooked_write_unsigned (regs,
1098 gdbarch_pc_regnum (gdbarch),
1104 /* If we're here, it means we have a branch to LR or CTR. If the
1105 branch was taken, the offset is probably greater than 4 (the next
1106 instruction), so it's safe to assume that an offset of 4 means we
1107 did not take the branch. */
1108 if (offset == PPC_INSN_SIZE)
1109 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1110 from + PPC_INSN_SIZE);
1113 /* Check for LK bit indicating whether we should set the link
1114 register to point to the next instruction
1115 (1: Set, 0: Don't set). */
1118 /* Link register needs to be set to the next instruction's PC. */
1119 regcache_cooked_write_unsigned (regs,
1120 gdbarch_tdep (gdbarch)->ppc_lr_regnum,
1121 from + PPC_INSN_SIZE);
1122 if (debug_displaced)
1123 fprintf_unfiltered (gdb_stdlog,
1124 "displaced: (ppc) adjusted LR to %s\n",
1125 paddress (gdbarch, from + PPC_INSN_SIZE));
1129 /* Check for breakpoints in the inferior. If we've found one, place the PC
1130 right at the breakpoint instruction. */
1131 else if ((insn & BP_MASK) == BP_INSN)
1132 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch), from);
1134 /* Handle any other instructions that do not fit in the categories above. */
1135 regcache_cooked_write_unsigned (regs, gdbarch_pc_regnum (gdbarch),
1139 /* Always use hardware single-stepping to execute the
1140 displaced instruction. */
1142 ppc_displaced_step_hw_singlestep (struct gdbarch *gdbarch,
1143 struct displaced_step_closure *closure)
1148 /* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX
1149 instruction and ending with a STWCX/STDCX instruction. If such a sequence
1150 is found, attempt to step through it. A breakpoint is placed at the end of
1154 ppc_deal_with_atomic_sequence (struct frame_info *frame)
1156 struct gdbarch *gdbarch = get_frame_arch (frame);
1157 struct address_space *aspace = get_frame_address_space (frame);
1158 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1159 CORE_ADDR pc = get_frame_pc (frame);
1160 CORE_ADDR breaks[2] = {-1, -1};
1162 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */
1163 int insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1166 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */
1167 const int atomic_sequence_length = 16; /* Instruction sequence length. */
1168 int bc_insn_count = 0; /* Conditional branch instruction count. */
1170 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */
1171 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION
1172 && (insn & LWARX_MASK) != LDARX_INSTRUCTION)
1175 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
1177 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count)
1179 loc += PPC_INSN_SIZE;
1180 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1182 /* Assume that there is at most one conditional branch in the atomic
1183 sequence. If a conditional branch is found, put a breakpoint in
1184 its destination address. */
1185 if ((insn & BRANCH_MASK) == BC_INSN)
1187 int immediate = ((insn & 0xfffc) ^ 0x8000) - 0x8000;
1188 int absolute = insn & 2;
1190 if (bc_insn_count >= 1)
1191 return 0; /* More than one conditional branch found, fallback
1192 to the standard single-step code. */
1195 breaks[1] = immediate;
1197 breaks[1] = loc + immediate;
1203 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION
1204 || (insn & STWCX_MASK) == STDCX_INSTRUCTION)
1208 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */
1209 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION
1210 && (insn & STWCX_MASK) != STDCX_INSTRUCTION)
1214 loc += PPC_INSN_SIZE;
1215 insn = read_memory_integer (loc, PPC_INSN_SIZE, byte_order);
1217 /* Insert a breakpoint right after the end of the atomic sequence. */
1220 /* Check for duplicated breakpoints. Check also for a breakpoint
1221 placed (branch instruction's destination) anywhere in sequence. */
1223 && (breaks[1] == breaks[0]
1224 || (breaks[1] >= pc && breaks[1] <= closing_insn)))
1225 last_breakpoint = 0;
1227 /* Effectively inserts the breakpoints. */
1228 for (index = 0; index <= last_breakpoint; index++)
1229 insert_single_step_breakpoint (gdbarch, aspace, breaks[index]);
1235 #define SIGNED_SHORT(x) \
1236 ((sizeof (short) == 2) \
1237 ? ((int)(short)(x)) \
1238 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000)))
1240 #define GET_SRC_REG(x) (((x) >> 21) & 0x1f)
1242 /* Limit the number of skipped non-prologue instructions, as the examining
1243 of the prologue is expensive. */
1244 static int max_skip_non_prologue_insns = 10;
1246 /* Return nonzero if the given instruction OP can be part of the prologue
1247 of a function and saves a parameter on the stack. FRAMEP should be
1248 set if one of the previous instructions in the function has set the
1252 store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg)
1254 /* Move parameters from argument registers to temporary register. */
1255 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */
1257 /* Rx must be scratch register r0. */
1258 const int rx_regno = (op >> 16) & 31;
1259 /* Ry: Only r3 - r10 are used for parameter passing. */
1260 const int ry_regno = GET_SRC_REG (op);
1262 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10)
1264 *r0_contains_arg = 1;
1271 /* Save a General Purpose Register on stack. */
1273 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */
1274 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */
1276 /* Rx: Only r3 - r10 are used for parameter passing. */
1277 const int rx_regno = GET_SRC_REG (op);
1279 return (rx_regno >= 3 && rx_regno <= 10);
1282 /* Save a General Purpose Register on stack via the Frame Pointer. */
1285 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */
1286 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */
1287 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */
1289 /* Rx: Usually, only r3 - r10 are used for parameter passing.
1290 However, the compiler sometimes uses r0 to hold an argument. */
1291 const int rx_regno = GET_SRC_REG (op);
1293 return ((rx_regno >= 3 && rx_regno <= 10)
1294 || (rx_regno == 0 && *r0_contains_arg));
1297 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */
1299 /* Only f2 - f8 are used for parameter passing. */
1300 const int src_regno = GET_SRC_REG (op);
1302 return (src_regno >= 2 && src_regno <= 8);
1305 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */
1307 /* Only f2 - f8 are used for parameter passing. */
1308 const int src_regno = GET_SRC_REG (op);
1310 return (src_regno >= 2 && src_regno <= 8);
1313 /* Not an insn that saves a parameter on stack. */
1317 /* Assuming that INSN is a "bl" instruction located at PC, return
1318 nonzero if the destination of the branch is a "blrl" instruction.
1320 This sequence is sometimes found in certain function prologues.
1321 It allows the function to load the LR register with a value that
1322 they can use to access PIC data using PC-relative offsets. */
1325 bl_to_blrl_insn_p (CORE_ADDR pc, int insn, enum bfd_endian byte_order)
1332 absolute = (int) ((insn >> 1) & 1);
1333 immediate = ((insn & ~3) << 6) >> 6;
1337 dest = pc + immediate;
1339 dest_insn = read_memory_integer (dest, 4, byte_order);
1340 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */
1346 /* Masks for decoding a branch-and-link (bl) instruction.
1348 BL_MASK and BL_INSTRUCTION are used in combination with each other.
1349 The former is anded with the opcode in question; if the result of
1350 this masking operation is equal to BL_INSTRUCTION, then the opcode in
1351 question is a ``bl'' instruction.
1353 BL_DISPLACMENT_MASK is anded with the opcode in order to extract
1354 the branch displacement. */
1356 #define BL_MASK 0xfc000001
1357 #define BL_INSTRUCTION 0x48000001
1358 #define BL_DISPLACEMENT_MASK 0x03fffffc
1360 static unsigned long
1361 rs6000_fetch_instruction (struct gdbarch *gdbarch, const CORE_ADDR pc)
1363 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1367 /* Fetch the instruction and convert it to an integer. */
1368 if (target_read_memory (pc, buf, 4))
1370 op = extract_unsigned_integer (buf, 4, byte_order);
1375 /* GCC generates several well-known sequences of instructions at the begining
1376 of each function prologue when compiling with -fstack-check. If one of
1377 such sequences starts at START_PC, then return the address of the
1378 instruction immediately past this sequence. Otherwise, return START_PC. */
1381 rs6000_skip_stack_check (struct gdbarch *gdbarch, const CORE_ADDR start_pc)
1383 CORE_ADDR pc = start_pc;
1384 unsigned long op = rs6000_fetch_instruction (gdbarch, pc);
1386 /* First possible sequence: A small number of probes.
1387 stw 0, -<some immediate>(1)
1388 [repeat this instruction any (small) number of times]. */
1390 if ((op & 0xffff0000) == 0x90010000)
1392 while ((op & 0xffff0000) == 0x90010000)
1395 op = rs6000_fetch_instruction (gdbarch, pc);
1400 /* Second sequence: A probing loop.
1401 addi 12,1,-<some immediate>
1402 lis 0,-<some immediate>
1403 [possibly ori 0,0,<some immediate>]
1407 addi 12,12,-<some immediate>
1410 [possibly one last probe: stw 0,<some immediate>(12)]. */
1414 /* addi 12,1,-<some immediate> */
1415 if ((op & 0xffff0000) != 0x39810000)
1418 /* lis 0,-<some immediate> */
1420 op = rs6000_fetch_instruction (gdbarch, pc);
1421 if ((op & 0xffff0000) != 0x3c000000)
1425 op = rs6000_fetch_instruction (gdbarch, pc);
1426 /* [possibly ori 0,0,<some immediate>] */
1427 if ((op & 0xffff0000) == 0x60000000)
1430 op = rs6000_fetch_instruction (gdbarch, pc);
1433 if (op != 0x7c0c0214)
1438 op = rs6000_fetch_instruction (gdbarch, pc);
1439 if (op != 0x7c0c0000)
1444 op = rs6000_fetch_instruction (gdbarch, pc);
1445 if ((op & 0xff9f0001) != 0x41820000)
1448 /* addi 12,12,-<some immediate> */
1450 op = rs6000_fetch_instruction (gdbarch, pc);
1451 if ((op & 0xffff0000) != 0x398c0000)
1456 op = rs6000_fetch_instruction (gdbarch, pc);
1457 if (op != 0x900c0000)
1462 op = rs6000_fetch_instruction (gdbarch, pc);
1463 if ((op & 0xfc000001) != 0x48000000)
1466 /* [possibly one last probe: stw 0,<some immediate>(12)]. */
1468 op = rs6000_fetch_instruction (gdbarch, pc);
1469 if ((op & 0xffff0000) == 0x900c0000)
1472 op = rs6000_fetch_instruction (gdbarch, pc);
1475 /* We found a valid stack-check sequence, return the new PC. */
1479 /* Third sequence: No probe; instead, a comparizon between the stack size
1480 limit (saved in a run-time global variable) and the current stack
1483 addi 0,1,-<some immediate>
1484 lis 12,__gnat_stack_limit@ha
1485 lwz 12,__gnat_stack_limit@l(12)
1488 or, with a small variant in the case of a bigger stack frame:
1489 addis 0,1,<some immediate>
1490 addic 0,0,-<some immediate>
1491 lis 12,__gnat_stack_limit@ha
1492 lwz 12,__gnat_stack_limit@l(12)
1497 /* addi 0,1,-<some immediate> */
1498 if ((op & 0xffff0000) != 0x38010000)
1500 /* small stack frame variant not recognized; try the
1501 big stack frame variant: */
1503 /* addis 0,1,<some immediate> */
1504 if ((op & 0xffff0000) != 0x3c010000)
1507 /* addic 0,0,-<some immediate> */
1509 op = rs6000_fetch_instruction (gdbarch, pc);
1510 if ((op & 0xffff0000) != 0x30000000)
1514 /* lis 12,<some immediate> */
1516 op = rs6000_fetch_instruction (gdbarch, pc);
1517 if ((op & 0xffff0000) != 0x3d800000)
1520 /* lwz 12,<some immediate>(12) */
1522 op = rs6000_fetch_instruction (gdbarch, pc);
1523 if ((op & 0xffff0000) != 0x818c0000)
1528 op = rs6000_fetch_instruction (gdbarch, pc);
1529 if ((op & 0xfffffffe) != 0x7c406008)
1532 /* We found a valid stack-check sequence, return the new PC. */
1536 /* No stack check code in our prologue, return the start_pc. */
1540 /* return pc value after skipping a function prologue and also return
1541 information about a function frame.
1543 in struct rs6000_framedata fdata:
1544 - frameless is TRUE, if function does not have a frame.
1545 - nosavedpc is TRUE, if function does not save %pc value in its frame.
1546 - offset is the initial size of this stack frame --- the amount by
1547 which we decrement the sp to allocate the frame.
1548 - saved_gpr is the number of the first saved gpr.
1549 - saved_fpr is the number of the first saved fpr.
1550 - saved_vr is the number of the first saved vr.
1551 - saved_ev is the number of the first saved ev.
1552 - alloca_reg is the number of the register used for alloca() handling.
1554 - gpr_offset is the offset of the first saved gpr from the previous frame.
1555 - fpr_offset is the offset of the first saved fpr from the previous frame.
1556 - vr_offset is the offset of the first saved vr from the previous frame.
1557 - ev_offset is the offset of the first saved ev from the previous frame.
1558 - lr_offset is the offset of the saved lr
1559 - cr_offset is the offset of the saved cr
1560 - vrsave_offset is the offset of the saved vrsave register. */
1563 skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc, CORE_ADDR lim_pc,
1564 struct rs6000_framedata *fdata)
1566 CORE_ADDR orig_pc = pc;
1567 CORE_ADDR last_prologue_pc = pc;
1568 CORE_ADDR li_found_pc = 0;
1572 long vr_saved_offset = 0;
1578 int vrsave_reg = -1;
1581 int minimal_toc_loaded = 0;
1582 int prev_insn_was_prologue_insn = 1;
1583 int num_skip_non_prologue_insns = 0;
1584 int r0_contains_arg = 0;
1585 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (gdbarch);
1586 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
1587 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1589 memset (fdata, 0, sizeof (struct rs6000_framedata));
1590 fdata->saved_gpr = -1;
1591 fdata->saved_fpr = -1;
1592 fdata->saved_vr = -1;
1593 fdata->saved_ev = -1;
1594 fdata->alloca_reg = -1;
1595 fdata->frameless = 1;
1596 fdata->nosavedpc = 1;
1597 fdata->lr_register = -1;
1599 pc = rs6000_skip_stack_check (gdbarch, pc);
1605 /* Sometimes it isn't clear if an instruction is a prologue
1606 instruction or not. When we encounter one of these ambiguous
1607 cases, we'll set prev_insn_was_prologue_insn to 0 (false).
1608 Otherwise, we'll assume that it really is a prologue instruction. */
1609 if (prev_insn_was_prologue_insn)
1610 last_prologue_pc = pc;
1612 /* Stop scanning if we've hit the limit. */
1616 prev_insn_was_prologue_insn = 1;
1618 /* Fetch the instruction and convert it to an integer. */
1619 if (target_read_memory (pc, buf, 4))
1621 op = extract_unsigned_integer (buf, 4, byte_order);
1623 if ((op & 0xfc1fffff) == 0x7c0802a6)
1625 /* Since shared library / PIC code, which needs to get its
1626 address at runtime, can appear to save more than one link
1640 remember just the first one, but skip over additional
1643 lr_reg = (op & 0x03e00000) >> 21;
1645 r0_contains_arg = 0;
1648 else if ((op & 0xfc1fffff) == 0x7c000026)
1650 cr_reg = (op & 0x03e00000);
1652 r0_contains_arg = 0;
1656 else if ((op & 0xfc1f0000) == 0xd8010000)
1657 { /* stfd Rx,NUM(r1) */
1658 reg = GET_SRC_REG (op);
1659 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg)
1661 fdata->saved_fpr = reg;
1662 fdata->fpr_offset = SIGNED_SHORT (op) + offset;
1667 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */
1668 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */
1669 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */
1670 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */
1673 reg = GET_SRC_REG (op);
1674 if ((op & 0xfc1f0000) == 0xbc010000)
1675 fdata->gpr_mask |= ~((1U << reg) - 1);
1677 fdata->gpr_mask |= 1U << reg;
1678 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg)
1680 fdata->saved_gpr = reg;
1681 if ((op & 0xfc1f0003) == 0xf8010000)
1683 fdata->gpr_offset = SIGNED_SHORT (op) + offset;
1688 else if ((op & 0xffff0000) == 0x3c4c0000
1689 || (op & 0xffff0000) == 0x3c400000
1690 || (op & 0xffff0000) == 0x38420000)
1692 /* . 0: addis 2,12,.TOC.-0b@ha
1693 . addi 2,2,.TOC.-0b@l
1697 used by ELFv2 global entry points to set up r2. */
1700 else if (op == 0x60000000)
1703 /* Allow nops in the prologue, but do not consider them to
1704 be part of the prologue unless followed by other prologue
1706 prev_insn_was_prologue_insn = 0;
1710 else if ((op & 0xffff0000) == 0x3c000000)
1711 { /* addis 0,0,NUM, used for >= 32k frames */
1712 fdata->offset = (op & 0x0000ffff) << 16;
1713 fdata->frameless = 0;
1714 r0_contains_arg = 0;
1718 else if ((op & 0xffff0000) == 0x60000000)
1719 { /* ori 0,0,NUM, 2nd half of >= 32k frames */
1720 fdata->offset |= (op & 0x0000ffff);
1721 fdata->frameless = 0;
1722 r0_contains_arg = 0;
1726 else if (lr_reg >= 0 &&
1727 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1728 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) ||
1729 /* stw Rx, NUM(r1) */
1730 ((op & 0xffff0000) == (lr_reg | 0x90010000)) ||
1731 /* stwu Rx, NUM(r1) */
1732 ((op & 0xffff0000) == (lr_reg | 0x94010000))))
1733 { /* where Rx == lr */
1734 fdata->lr_offset = offset;
1735 fdata->nosavedpc = 0;
1736 /* Invalidate lr_reg, but don't set it to -1.
1737 That would mean that it had never been set. */
1739 if ((op & 0xfc000003) == 0xf8000000 || /* std */
1740 (op & 0xfc000000) == 0x90000000) /* stw */
1742 /* Does not update r1, so add displacement to lr_offset. */
1743 fdata->lr_offset += SIGNED_SHORT (op);
1748 else if (cr_reg >= 0 &&
1749 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */
1750 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) ||
1751 /* stw Rx, NUM(r1) */
1752 ((op & 0xffff0000) == (cr_reg | 0x90010000)) ||
1753 /* stwu Rx, NUM(r1) */
1754 ((op & 0xffff0000) == (cr_reg | 0x94010000))))
1755 { /* where Rx == cr */
1756 fdata->cr_offset = offset;
1757 /* Invalidate cr_reg, but don't set it to -1.
1758 That would mean that it had never been set. */
1760 if ((op & 0xfc000003) == 0xf8000000 ||
1761 (op & 0xfc000000) == 0x90000000)
1763 /* Does not update r1, so add displacement to cr_offset. */
1764 fdata->cr_offset += SIGNED_SHORT (op);
1769 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1)
1771 /* bcl 20,xx,.+4 is used to get the current PC, with or without
1772 prediction bits. If the LR has already been saved, we can
1776 else if (op == 0x48000005)
1783 else if (op == 0x48000004)
1788 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used
1789 in V.4 -mminimal-toc */
1790 (op & 0xffff0000) == 0x3bde0000)
1791 { /* addi 30,30,foo@l */
1795 else if ((op & 0xfc000001) == 0x48000001)
1799 fdata->frameless = 0;
1801 /* If the return address has already been saved, we can skip
1802 calls to blrl (for PIC). */
1803 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op, byte_order))
1809 /* Don't skip over the subroutine call if it is not within
1810 the first three instructions of the prologue and either
1811 we have no line table information or the line info tells
1812 us that the subroutine call is not part of the line
1813 associated with the prologue. */
1814 if ((pc - orig_pc) > 8)
1816 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0);
1817 struct symtab_and_line this_sal = find_pc_line (pc, 0);
1819 if ((prologue_sal.line == 0)
1820 || (prologue_sal.line != this_sal.line))
1824 op = read_memory_integer (pc + 4, 4, byte_order);
1826 /* At this point, make sure this is not a trampoline
1827 function (a function that simply calls another functions,
1828 and nothing else). If the next is not a nop, this branch
1829 was part of the function prologue. */
1831 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */
1832 break; /* Don't skip over
1838 /* update stack pointer */
1839 else if ((op & 0xfc1f0000) == 0x94010000)
1840 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */
1841 fdata->frameless = 0;
1842 fdata->offset = SIGNED_SHORT (op);
1843 offset = fdata->offset;
1846 else if ((op & 0xfc1f016a) == 0x7c01016e)
1847 { /* stwux rX,r1,rY */
1848 /* No way to figure out what r1 is going to be. */
1849 fdata->frameless = 0;
1850 offset = fdata->offset;
1853 else if ((op & 0xfc1f0003) == 0xf8010001)
1854 { /* stdu rX,NUM(r1) */
1855 fdata->frameless = 0;
1856 fdata->offset = SIGNED_SHORT (op & ~3UL);
1857 offset = fdata->offset;
1860 else if ((op & 0xfc1f016a) == 0x7c01016a)
1861 { /* stdux rX,r1,rY */
1862 /* No way to figure out what r1 is going to be. */
1863 fdata->frameless = 0;
1864 offset = fdata->offset;
1867 else if ((op & 0xffff0000) == 0x38210000)
1868 { /* addi r1,r1,SIMM */
1869 fdata->frameless = 0;
1870 fdata->offset += SIGNED_SHORT (op);
1871 offset = fdata->offset;
1874 /* Load up minimal toc pointer. Do not treat an epilogue restore
1875 of r31 as a minimal TOC load. */
1876 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */
1877 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */
1879 && !minimal_toc_loaded)
1881 minimal_toc_loaded = 1;
1884 /* move parameters from argument registers to local variable
1887 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */
1888 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */
1889 (((op >> 21) & 31) <= 10) &&
1890 ((long) ((op >> 16) & 31)
1891 >= fdata->saved_gpr)) /* Rx: local var reg */
1895 /* store parameters in stack */
1897 /* Move parameters from argument registers to temporary register. */
1898 else if (store_param_on_stack_p (op, framep, &r0_contains_arg))
1902 /* Set up frame pointer */
1904 else if (op == 0x603d0000) /* oril r29, r1, 0x0 */
1906 fdata->frameless = 0;
1908 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 29);
1911 /* Another way to set up the frame pointer. */
1913 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */
1914 || op == 0x7c3f0b78)
1916 fdata->frameless = 0;
1918 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31);
1921 /* Another way to set up the frame pointer. */
1923 else if ((op & 0xfc1fffff) == 0x38010000)
1924 { /* addi rX, r1, 0x0 */
1925 fdata->frameless = 0;
1927 fdata->alloca_reg = (tdep->ppc_gp0_regnum
1928 + ((op & ~0x38010000) >> 21));
1931 /* AltiVec related instructions. */
1932 /* Store the vrsave register (spr 256) in another register for
1933 later manipulation, or load a register into the vrsave
1934 register. 2 instructions are used: mfvrsave and
1935 mtvrsave. They are shorthand notation for mfspr Rn, SPR256
1936 and mtspr SPR256, Rn. */
1937 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110
1938 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */
1939 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */
1941 vrsave_reg = GET_SRC_REG (op);
1944 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */
1948 /* Store the register where vrsave was saved to onto the stack:
1949 rS is the register where vrsave was stored in a previous
1951 /* 100100 sssss 00001 dddddddd dddddddd */
1952 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */
1954 if (vrsave_reg == GET_SRC_REG (op))
1956 fdata->vrsave_offset = SIGNED_SHORT (op) + offset;
1961 /* Compute the new value of vrsave, by modifying the register
1962 where vrsave was saved to. */
1963 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */
1964 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */
1968 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first
1969 in a pair of insns to save the vector registers on the
1971 /* 001110 00000 00000 iiii iiii iiii iiii */
1972 /* 001110 01110 00000 iiii iiii iiii iiii */
1973 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */
1974 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */
1976 if ((op & 0xffff0000) == 0x38000000)
1977 r0_contains_arg = 0;
1979 vr_saved_offset = SIGNED_SHORT (op);
1981 /* This insn by itself is not part of the prologue, unless
1982 if part of the pair of insns mentioned above. So do not
1983 record this insn as part of the prologue yet. */
1984 prev_insn_was_prologue_insn = 0;
1986 /* Store vector register S at (r31+r0) aligned to 16 bytes. */
1987 /* 011111 sssss 11111 00000 00111001110 */
1988 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */
1990 if (pc == (li_found_pc + 4))
1992 vr_reg = GET_SRC_REG (op);
1993 /* If this is the first vector reg to be saved, or if
1994 it has a lower number than others previously seen,
1995 reupdate the frame info. */
1996 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg)
1998 fdata->saved_vr = vr_reg;
1999 fdata->vr_offset = vr_saved_offset + offset;
2001 vr_saved_offset = -1;
2006 /* End AltiVec related instructions. */
2008 /* Start BookE related instructions. */
2009 /* Store gen register S at (r31+uimm).
2010 Any register less than r13 is volatile, so we don't care. */
2011 /* 000100 sssss 11111 iiiii 01100100001 */
2012 else if (arch_info->mach == bfd_mach_ppc_e500
2013 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */
2015 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */
2018 ev_reg = GET_SRC_REG (op);
2019 imm = (op >> 11) & 0x1f;
2020 ev_offset = imm * 8;
2021 /* If this is the first vector reg to be saved, or if
2022 it has a lower number than others previously seen,
2023 reupdate the frame info. */
2024 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2026 fdata->saved_ev = ev_reg;
2027 fdata->ev_offset = ev_offset + offset;
2032 /* Store gen register rS at (r1+rB). */
2033 /* 000100 sssss 00001 bbbbb 01100100000 */
2034 else if (arch_info->mach == bfd_mach_ppc_e500
2035 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */
2037 if (pc == (li_found_pc + 4))
2039 ev_reg = GET_SRC_REG (op);
2040 /* If this is the first vector reg to be saved, or if
2041 it has a lower number than others previously seen,
2042 reupdate the frame info. */
2043 /* We know the contents of rB from the previous instruction. */
2044 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2046 fdata->saved_ev = ev_reg;
2047 fdata->ev_offset = vr_saved_offset + offset;
2049 vr_saved_offset = -1;
2055 /* Store gen register r31 at (rA+uimm). */
2056 /* 000100 11111 aaaaa iiiii 01100100001 */
2057 else if (arch_info->mach == bfd_mach_ppc_e500
2058 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */
2060 /* Wwe know that the source register is 31 already, but
2061 it can't hurt to compute it. */
2062 ev_reg = GET_SRC_REG (op);
2063 ev_offset = ((op >> 11) & 0x1f) * 8;
2064 /* If this is the first vector reg to be saved, or if
2065 it has a lower number than others previously seen,
2066 reupdate the frame info. */
2067 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2069 fdata->saved_ev = ev_reg;
2070 fdata->ev_offset = ev_offset + offset;
2075 /* Store gen register S at (r31+r0).
2076 Store param on stack when offset from SP bigger than 4 bytes. */
2077 /* 000100 sssss 11111 00000 01100100000 */
2078 else if (arch_info->mach == bfd_mach_ppc_e500
2079 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */
2081 if (pc == (li_found_pc + 4))
2083 if ((op & 0x03e00000) >= 0x01a00000)
2085 ev_reg = GET_SRC_REG (op);
2086 /* If this is the first vector reg to be saved, or if
2087 it has a lower number than others previously seen,
2088 reupdate the frame info. */
2089 /* We know the contents of r0 from the previous
2091 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg)
2093 fdata->saved_ev = ev_reg;
2094 fdata->ev_offset = vr_saved_offset + offset;
2098 vr_saved_offset = -1;
2103 /* End BookE related instructions. */
2107 unsigned int all_mask = ~((1U << fdata->saved_gpr) - 1);
2109 /* Not a recognized prologue instruction.
2110 Handle optimizer code motions into the prologue by continuing
2111 the search if we have no valid frame yet or if the return
2112 address is not yet saved in the frame. Also skip instructions
2113 if some of the GPRs expected to be saved are not yet saved. */
2114 if (fdata->frameless == 0 && fdata->nosavedpc == 0
2115 && (fdata->gpr_mask & all_mask) == all_mask)
2118 if (op == 0x4e800020 /* blr */
2119 || op == 0x4e800420) /* bctr */
2120 /* Do not scan past epilogue in frameless functions or
2123 if ((op & 0xf4000000) == 0x40000000) /* bxx */
2124 /* Never skip branches. */
2127 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns)
2128 /* Do not scan too many insns, scanning insns is expensive with
2132 /* Continue scanning. */
2133 prev_insn_was_prologue_insn = 0;
2139 /* I have problems with skipping over __main() that I need to address
2140 * sometime. Previously, I used to use misc_function_vector which
2141 * didn't work as well as I wanted to be. -MGO */
2143 /* If the first thing after skipping a prolog is a branch to a function,
2144 this might be a call to an initializer in main(), introduced by gcc2.
2145 We'd like to skip over it as well. Fortunately, xlc does some extra
2146 work before calling a function right after a prologue, thus we can
2147 single out such gcc2 behaviour. */
2150 if ((op & 0xfc000001) == 0x48000001)
2151 { /* bl foo, an initializer function? */
2152 op = read_memory_integer (pc + 4, 4, byte_order);
2154 if (op == 0x4def7b82)
2155 { /* cror 0xf, 0xf, 0xf (nop) */
2157 /* Check and see if we are in main. If so, skip over this
2158 initializer function as well. */
2160 tmp = find_pc_misc_function (pc);
2162 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0)
2168 if (pc == lim_pc && lr_reg >= 0)
2169 fdata->lr_register = lr_reg;
2171 fdata->offset = -fdata->offset;
2172 return last_prologue_pc;
2176 rs6000_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2178 struct rs6000_framedata frame;
2179 CORE_ADDR limit_pc, func_addr, func_end_addr = 0;
2181 /* See if we can determine the end of the prologue via the symbol table.
2182 If so, then return either PC, or the PC after the prologue, whichever
2184 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end_addr))
2186 CORE_ADDR post_prologue_pc
2187 = skip_prologue_using_sal (gdbarch, func_addr);
2188 if (post_prologue_pc != 0)
2189 return max (pc, post_prologue_pc);
2192 /* Can't determine prologue from the symbol table, need to examine
2195 /* Find an upper limit on the function prologue using the debug
2196 information. If the debug information could not be used to provide
2197 that bound, then use an arbitrary large number as the upper bound. */
2198 limit_pc = skip_prologue_using_sal (gdbarch, pc);
2200 limit_pc = pc + 100; /* Magic. */
2202 /* Do not allow limit_pc to be past the function end, if we know
2203 where that end is... */
2204 if (func_end_addr && limit_pc > func_end_addr)
2205 limit_pc = func_end_addr;
2207 pc = skip_prologue (gdbarch, pc, limit_pc, &frame);
2211 /* When compiling for EABI, some versions of GCC emit a call to __eabi
2212 in the prologue of main().
2214 The function below examines the code pointed at by PC and checks to
2215 see if it corresponds to a call to __eabi. If so, it returns the
2216 address of the instruction following that call. Otherwise, it simply
2220 rs6000_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
2222 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2226 if (target_read_memory (pc, buf, 4))
2228 op = extract_unsigned_integer (buf, 4, byte_order);
2230 if ((op & BL_MASK) == BL_INSTRUCTION)
2232 CORE_ADDR displ = op & BL_DISPLACEMENT_MASK;
2233 CORE_ADDR call_dest = pc + 4 + displ;
2234 struct bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest);
2236 /* We check for ___eabi (three leading underscores) in addition
2237 to __eabi in case the GCC option "-fleading-underscore" was
2238 used to compile the program. */
2239 if (s.minsym != NULL
2240 && MSYMBOL_LINKAGE_NAME (s.minsym) != NULL
2241 && (strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "__eabi") == 0
2242 || strcmp (MSYMBOL_LINKAGE_NAME (s.minsym), "___eabi") == 0))
2248 /* All the ABI's require 16 byte alignment. */
2250 rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2252 return (addr & -16);
2255 /* Return whether handle_inferior_event() should proceed through code
2256 starting at PC in function NAME when stepping.
2258 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to
2259 handle memory references that are too distant to fit in instructions
2260 generated by the compiler. For example, if 'foo' in the following
2265 is greater than 32767, the linker might replace the lwz with a branch to
2266 somewhere in @FIX1 that does the load in 2 instructions and then branches
2267 back to where execution should continue.
2269 GDB should silently step over @FIX code, just like AIX dbx does.
2270 Unfortunately, the linker uses the "b" instruction for the
2271 branches, meaning that the link register doesn't get set.
2272 Therefore, GDB's usual step_over_function () mechanism won't work.
2274 Instead, use the gdbarch_skip_trampoline_code and
2275 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past
2279 rs6000_in_solib_return_trampoline (struct gdbarch *gdbarch,
2280 CORE_ADDR pc, const char *name)
2282 return name && startswith (name, "@FIX");
2285 /* Skip code that the user doesn't want to see when stepping:
2287 1. Indirect function calls use a piece of trampoline code to do context
2288 switching, i.e. to set the new TOC table. Skip such code if we are on
2289 its first instruction (as when we have single-stepped to here).
2291 2. Skip shared library trampoline code (which is different from
2292 indirect function call trampolines).
2294 3. Skip bigtoc fixup code.
2296 Result is desired PC to step until, or NULL if we are not in
2297 code that should be skipped. */
2300 rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc)
2302 struct gdbarch *gdbarch = get_frame_arch (frame);
2303 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2304 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2305 unsigned int ii, op;
2307 CORE_ADDR solib_target_pc;
2308 struct bound_minimal_symbol msymbol;
2310 static unsigned trampoline_code[] =
2312 0x800b0000, /* l r0,0x0(r11) */
2313 0x90410014, /* st r2,0x14(r1) */
2314 0x7c0903a6, /* mtctr r0 */
2315 0x804b0004, /* l r2,0x4(r11) */
2316 0x816b0008, /* l r11,0x8(r11) */
2317 0x4e800420, /* bctr */
2318 0x4e800020, /* br */
2322 /* Check for bigtoc fixup code. */
2323 msymbol = lookup_minimal_symbol_by_pc (pc);
2325 && rs6000_in_solib_return_trampoline (gdbarch, pc,
2326 MSYMBOL_LINKAGE_NAME (msymbol.minsym)))
2328 /* Double-check that the third instruction from PC is relative "b". */
2329 op = read_memory_integer (pc + 8, 4, byte_order);
2330 if ((op & 0xfc000003) == 0x48000000)
2332 /* Extract bits 6-29 as a signed 24-bit relative word address and
2333 add it to the containing PC. */
2334 rel = ((int)(op << 6) >> 6);
2335 return pc + 8 + rel;
2339 /* If pc is in a shared library trampoline, return its target. */
2340 solib_target_pc = find_solib_trampoline_target (frame, pc);
2341 if (solib_target_pc)
2342 return solib_target_pc;
2344 for (ii = 0; trampoline_code[ii]; ++ii)
2346 op = read_memory_integer (pc + (ii * 4), 4, byte_order);
2347 if (op != trampoline_code[ii])
2350 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination
2352 pc = read_memory_unsigned_integer (ii, tdep->wordsize, byte_order);
2356 /* ISA-specific vector types. */
2358 static struct type *
2359 rs6000_builtin_type_vec64 (struct gdbarch *gdbarch)
2361 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2363 if (!tdep->ppc_builtin_type_vec64)
2365 const struct builtin_type *bt = builtin_type (gdbarch);
2367 /* The type we're building is this: */
2369 union __gdb_builtin_type_vec64
2373 int32_t v2_int32[2];
2374 int16_t v4_int16[4];
2381 t = arch_composite_type (gdbarch,
2382 "__ppc_builtin_type_vec64", TYPE_CODE_UNION);
2383 append_composite_type_field (t, "uint64", bt->builtin_int64);
2384 append_composite_type_field (t, "v2_float",
2385 init_vector_type (bt->builtin_float, 2));
2386 append_composite_type_field (t, "v2_int32",
2387 init_vector_type (bt->builtin_int32, 2));
2388 append_composite_type_field (t, "v4_int16",
2389 init_vector_type (bt->builtin_int16, 4));
2390 append_composite_type_field (t, "v8_int8",
2391 init_vector_type (bt->builtin_int8, 8));
2393 TYPE_VECTOR (t) = 1;
2394 TYPE_NAME (t) = "ppc_builtin_type_vec64";
2395 tdep->ppc_builtin_type_vec64 = t;
2398 return tdep->ppc_builtin_type_vec64;
2401 /* Vector 128 type. */
2403 static struct type *
2404 rs6000_builtin_type_vec128 (struct gdbarch *gdbarch)
2406 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2408 if (!tdep->ppc_builtin_type_vec128)
2410 const struct builtin_type *bt = builtin_type (gdbarch);
2412 /* The type we're building is this
2414 type = union __ppc_builtin_type_vec128 {
2416 double v2_double[2];
2418 int32_t v4_int32[4];
2419 int16_t v8_int16[8];
2420 int8_t v16_int8[16];
2426 t = arch_composite_type (gdbarch,
2427 "__ppc_builtin_type_vec128", TYPE_CODE_UNION);
2428 append_composite_type_field (t, "uint128", bt->builtin_uint128);
2429 append_composite_type_field (t, "v2_double",
2430 init_vector_type (bt->builtin_double, 2));
2431 append_composite_type_field (t, "v4_float",
2432 init_vector_type (bt->builtin_float, 4));
2433 append_composite_type_field (t, "v4_int32",
2434 init_vector_type (bt->builtin_int32, 4));
2435 append_composite_type_field (t, "v8_int16",
2436 init_vector_type (bt->builtin_int16, 8));
2437 append_composite_type_field (t, "v16_int8",
2438 init_vector_type (bt->builtin_int8, 16));
2440 TYPE_VECTOR (t) = 1;
2441 TYPE_NAME (t) = "ppc_builtin_type_vec128";
2442 tdep->ppc_builtin_type_vec128 = t;
2445 return tdep->ppc_builtin_type_vec128;
2448 /* Return the name of register number REGNO, or the empty string if it
2449 is an anonymous register. */
2452 rs6000_register_name (struct gdbarch *gdbarch, int regno)
2454 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2456 /* The upper half "registers" have names in the XML description,
2457 but we present only the low GPRs and the full 64-bit registers
2459 if (tdep->ppc_ev0_upper_regnum >= 0
2460 && tdep->ppc_ev0_upper_regnum <= regno
2461 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)
2464 /* Hide the upper halves of the vs0~vs31 registers. */
2465 if (tdep->ppc_vsr0_regnum >= 0
2466 && tdep->ppc_vsr0_upper_regnum <= regno
2467 && regno < tdep->ppc_vsr0_upper_regnum + ppc_num_gprs)
2470 /* Check if the SPE pseudo registers are available. */
2471 if (IS_SPE_PSEUDOREG (tdep, regno))
2473 static const char *const spe_regnames[] = {
2474 "ev0", "ev1", "ev2", "ev3", "ev4", "ev5", "ev6", "ev7",
2475 "ev8", "ev9", "ev10", "ev11", "ev12", "ev13", "ev14", "ev15",
2476 "ev16", "ev17", "ev18", "ev19", "ev20", "ev21", "ev22", "ev23",
2477 "ev24", "ev25", "ev26", "ev27", "ev28", "ev29", "ev30", "ev31",
2479 return spe_regnames[regno - tdep->ppc_ev0_regnum];
2482 /* Check if the decimal128 pseudo-registers are available. */
2483 if (IS_DFP_PSEUDOREG (tdep, regno))
2485 static const char *const dfp128_regnames[] = {
2486 "dl0", "dl1", "dl2", "dl3",
2487 "dl4", "dl5", "dl6", "dl7",
2488 "dl8", "dl9", "dl10", "dl11",
2489 "dl12", "dl13", "dl14", "dl15"
2491 return dfp128_regnames[regno - tdep->ppc_dl0_regnum];
2494 /* Check if this is a VSX pseudo-register. */
2495 if (IS_VSX_PSEUDOREG (tdep, regno))
2497 static const char *const vsx_regnames[] = {
2498 "vs0", "vs1", "vs2", "vs3", "vs4", "vs5", "vs6", "vs7",
2499 "vs8", "vs9", "vs10", "vs11", "vs12", "vs13", "vs14",
2500 "vs15", "vs16", "vs17", "vs18", "vs19", "vs20", "vs21",
2501 "vs22", "vs23", "vs24", "vs25", "vs26", "vs27", "vs28",
2502 "vs29", "vs30", "vs31", "vs32", "vs33", "vs34", "vs35",
2503 "vs36", "vs37", "vs38", "vs39", "vs40", "vs41", "vs42",
2504 "vs43", "vs44", "vs45", "vs46", "vs47", "vs48", "vs49",
2505 "vs50", "vs51", "vs52", "vs53", "vs54", "vs55", "vs56",
2506 "vs57", "vs58", "vs59", "vs60", "vs61", "vs62", "vs63"
2508 return vsx_regnames[regno - tdep->ppc_vsr0_regnum];
2511 /* Check if the this is a Extended FP pseudo-register. */
2512 if (IS_EFP_PSEUDOREG (tdep, regno))
2514 static const char *const efpr_regnames[] = {
2515 "f32", "f33", "f34", "f35", "f36", "f37", "f38",
2516 "f39", "f40", "f41", "f42", "f43", "f44", "f45",
2517 "f46", "f47", "f48", "f49", "f50", "f51",
2518 "f52", "f53", "f54", "f55", "f56", "f57",
2519 "f58", "f59", "f60", "f61", "f62", "f63"
2521 return efpr_regnames[regno - tdep->ppc_efpr0_regnum];
2524 return tdesc_register_name (gdbarch, regno);
2527 /* Return the GDB type object for the "standard" data type of data in
2530 static struct type *
2531 rs6000_pseudo_register_type (struct gdbarch *gdbarch, int regnum)
2533 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2535 /* These are the only pseudo-registers we support. */
2536 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2537 || IS_DFP_PSEUDOREG (tdep, regnum)
2538 || IS_VSX_PSEUDOREG (tdep, regnum)
2539 || IS_EFP_PSEUDOREG (tdep, regnum));
2541 /* These are the e500 pseudo-registers. */
2542 if (IS_SPE_PSEUDOREG (tdep, regnum))
2543 return rs6000_builtin_type_vec64 (gdbarch);
2544 else if (IS_DFP_PSEUDOREG (tdep, regnum))
2545 /* PPC decimal128 pseudo-registers. */
2546 return builtin_type (gdbarch)->builtin_declong;
2547 else if (IS_VSX_PSEUDOREG (tdep, regnum))
2548 /* POWER7 VSX pseudo-registers. */
2549 return rs6000_builtin_type_vec128 (gdbarch);
2551 /* POWER7 Extended FP pseudo-registers. */
2552 return builtin_type (gdbarch)->builtin_double;
2555 /* Is REGNUM a member of REGGROUP? */
2557 rs6000_pseudo_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2558 struct reggroup *group)
2560 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2562 /* These are the only pseudo-registers we support. */
2563 gdb_assert (IS_SPE_PSEUDOREG (tdep, regnum)
2564 || IS_DFP_PSEUDOREG (tdep, regnum)
2565 || IS_VSX_PSEUDOREG (tdep, regnum)
2566 || IS_EFP_PSEUDOREG (tdep, regnum));
2568 /* These are the e500 pseudo-registers or the POWER7 VSX registers. */
2569 if (IS_SPE_PSEUDOREG (tdep, regnum) || IS_VSX_PSEUDOREG (tdep, regnum))
2570 return group == all_reggroup || group == vector_reggroup;
2572 /* PPC decimal128 or Extended FP pseudo-registers. */
2573 return group == all_reggroup || group == float_reggroup;
2576 /* The register format for RS/6000 floating point registers is always
2577 double, we need a conversion if the memory format is float. */
2580 rs6000_convert_register_p (struct gdbarch *gdbarch, int regnum,
2583 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2585 return (tdep->ppc_fp0_regnum >= 0
2586 && regnum >= tdep->ppc_fp0_regnum
2587 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs
2588 && TYPE_CODE (type) == TYPE_CODE_FLT
2589 && TYPE_LENGTH (type)
2590 != TYPE_LENGTH (builtin_type (gdbarch)->builtin_double));
2594 rs6000_register_to_value (struct frame_info *frame,
2598 int *optimizedp, int *unavailablep)
2600 struct gdbarch *gdbarch = get_frame_arch (frame);
2601 gdb_byte from[MAX_REGISTER_SIZE];
2603 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2605 if (!get_frame_register_bytes (frame, regnum, 0,
2606 register_size (gdbarch, regnum),
2607 from, optimizedp, unavailablep))
2610 convert_typed_floating (from, builtin_type (gdbarch)->builtin_double,
2612 *optimizedp = *unavailablep = 0;
2617 rs6000_value_to_register (struct frame_info *frame,
2620 const gdb_byte *from)
2622 struct gdbarch *gdbarch = get_frame_arch (frame);
2623 gdb_byte to[MAX_REGISTER_SIZE];
2625 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT);
2627 convert_typed_floating (from, type,
2628 to, builtin_type (gdbarch)->builtin_double);
2629 put_frame_register (frame, regnum, to);
2632 /* The type of a function that moves the value of REG between CACHE
2633 or BUF --- in either direction. */
2634 typedef enum register_status (*move_ev_register_func) (struct regcache *,
2637 /* Move SPE vector register values between a 64-bit buffer and the two
2638 32-bit raw register halves in a regcache. This function handles
2639 both splitting a 64-bit value into two 32-bit halves, and joining
2640 two halves into a whole 64-bit value, depending on the function
2641 passed as the MOVE argument.
2643 EV_REG must be the number of an SPE evN vector register --- a
2644 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a
2647 Call MOVE once for each 32-bit half of that register, passing
2648 REGCACHE, the number of the raw register corresponding to that
2649 half, and the address of the appropriate half of BUFFER.
2651 For example, passing 'regcache_raw_read' as the MOVE function will
2652 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing
2653 'regcache_raw_supply' will supply the contents of BUFFER to the
2654 appropriate pair of raw registers in REGCACHE.
2656 You may need to cast away some 'const' qualifiers when passing
2657 MOVE, since this function can't tell at compile-time which of
2658 REGCACHE or BUFFER is acting as the source of the data. If C had
2659 co-variant type qualifiers, ... */
2661 static enum register_status
2662 e500_move_ev_register (move_ev_register_func move,
2663 struct regcache *regcache, int ev_reg, void *buffer)
2665 struct gdbarch *arch = get_regcache_arch (regcache);
2666 struct gdbarch_tdep *tdep = gdbarch_tdep (arch);
2668 gdb_byte *byte_buffer = (gdb_byte *) buffer;
2669 enum register_status status;
2671 gdb_assert (IS_SPE_PSEUDOREG (tdep, ev_reg));
2673 reg_index = ev_reg - tdep->ppc_ev0_regnum;
2675 if (gdbarch_byte_order (arch) == BFD_ENDIAN_BIG)
2677 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2679 if (status == REG_VALID)
2680 status = move (regcache, tdep->ppc_gp0_regnum + reg_index,
2685 status = move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer);
2686 if (status == REG_VALID)
2687 status = move (regcache, tdep->ppc_ev0_upper_regnum + reg_index,
2694 static enum register_status
2695 do_regcache_raw_read (struct regcache *regcache, int regnum, void *buffer)
2697 return regcache_raw_read (regcache, regnum, (gdb_byte *) buffer);
2700 static enum register_status
2701 do_regcache_raw_write (struct regcache *regcache, int regnum, void *buffer)
2703 regcache_raw_write (regcache, regnum, (const gdb_byte *) buffer);
2708 static enum register_status
2709 e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2710 int reg_nr, gdb_byte *buffer)
2712 return e500_move_ev_register (do_regcache_raw_read, regcache, reg_nr, buffer);
2716 e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2717 int reg_nr, const gdb_byte *buffer)
2719 e500_move_ev_register (do_regcache_raw_write, regcache,
2720 reg_nr, (void *) buffer);
2723 /* Read method for DFP pseudo-registers. */
2724 static enum register_status
2725 dfp_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2726 int reg_nr, gdb_byte *buffer)
2728 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2729 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2730 enum register_status status;
2732 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2734 /* Read two FP registers to form a whole dl register. */
2735 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2736 2 * reg_index, buffer);
2737 if (status == REG_VALID)
2738 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2739 2 * reg_index + 1, buffer + 8);
2743 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2744 2 * reg_index + 1, buffer);
2745 if (status == REG_VALID)
2746 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2747 2 * reg_index, buffer + 8);
2753 /* Write method for DFP pseudo-registers. */
2755 dfp_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2756 int reg_nr, const gdb_byte *buffer)
2758 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2759 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2761 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2763 /* Write each half of the dl register into a separate
2765 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2766 2 * reg_index, buffer);
2767 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2768 2 * reg_index + 1, buffer + 8);
2772 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2773 2 * reg_index + 1, buffer);
2774 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2775 2 * reg_index, buffer + 8);
2779 /* Read method for POWER7 VSX pseudo-registers. */
2780 static enum register_status
2781 vsx_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2782 int reg_nr, gdb_byte *buffer)
2784 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2785 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2786 enum register_status status;
2788 /* Read the portion that overlaps the VMX registers. */
2790 status = regcache_raw_read (regcache, tdep->ppc_vr0_regnum +
2791 reg_index - 32, buffer);
2793 /* Read the portion that overlaps the FPR registers. */
2794 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2796 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2798 if (status == REG_VALID)
2799 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2800 reg_index, buffer + 8);
2804 status = regcache_raw_read (regcache, tdep->ppc_fp0_regnum +
2805 reg_index, buffer + 8);
2806 if (status == REG_VALID)
2807 status = regcache_raw_read (regcache, tdep->ppc_vsr0_upper_regnum +
2814 /* Write method for POWER7 VSX pseudo-registers. */
2816 vsx_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2817 int reg_nr, const gdb_byte *buffer)
2819 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2820 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2822 /* Write the portion that overlaps the VMX registers. */
2824 regcache_raw_write (regcache, tdep->ppc_vr0_regnum +
2825 reg_index - 32, buffer);
2827 /* Write the portion that overlaps the FPR registers. */
2828 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
2830 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2832 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2833 reg_index, buffer + 8);
2837 regcache_raw_write (regcache, tdep->ppc_fp0_regnum +
2838 reg_index, buffer + 8);
2839 regcache_raw_write (regcache, tdep->ppc_vsr0_upper_regnum +
2844 /* Read method for POWER7 Extended FP pseudo-registers. */
2845 static enum register_status
2846 efpr_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache,
2847 int reg_nr, gdb_byte *buffer)
2849 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2850 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2851 int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8;
2853 /* Read the portion that overlaps the VMX register. */
2854 return regcache_raw_read_part (regcache, tdep->ppc_vr0_regnum + reg_index,
2855 offset, register_size (gdbarch, reg_nr),
2859 /* Write method for POWER7 Extended FP pseudo-registers. */
2861 efpr_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2862 int reg_nr, const gdb_byte *buffer)
2864 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2865 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2866 int offset = gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG ? 0 : 8;
2868 /* Write the portion that overlaps the VMX register. */
2869 regcache_raw_write_part (regcache, tdep->ppc_vr0_regnum + reg_index,
2870 offset, register_size (gdbarch, reg_nr),
2874 static enum register_status
2875 rs6000_pseudo_register_read (struct gdbarch *gdbarch,
2876 struct regcache *regcache,
2877 int reg_nr, gdb_byte *buffer)
2879 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2880 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2882 gdb_assert (regcache_arch == gdbarch);
2884 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2885 return e500_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2886 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2887 return dfp_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2888 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2889 return vsx_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2890 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2891 return efpr_pseudo_register_read (gdbarch, regcache, reg_nr, buffer);
2893 internal_error (__FILE__, __LINE__,
2894 _("rs6000_pseudo_register_read: "
2895 "called on unexpected register '%s' (%d)"),
2896 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2900 rs6000_pseudo_register_write (struct gdbarch *gdbarch,
2901 struct regcache *regcache,
2902 int reg_nr, const gdb_byte *buffer)
2904 struct gdbarch *regcache_arch = get_regcache_arch (regcache);
2905 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2907 gdb_assert (regcache_arch == gdbarch);
2909 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2910 e500_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2911 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2912 dfp_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2913 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2914 vsx_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2915 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2916 efpr_pseudo_register_write (gdbarch, regcache, reg_nr, buffer);
2918 internal_error (__FILE__, __LINE__,
2919 _("rs6000_pseudo_register_write: "
2920 "called on unexpected register '%s' (%d)"),
2921 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2925 rs6000_ax_pseudo_register_collect (struct gdbarch *gdbarch,
2926 struct agent_expr *ax, int reg_nr)
2928 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2929 if (IS_SPE_PSEUDOREG (tdep, reg_nr))
2931 int reg_index = reg_nr - tdep->ppc_ev0_regnum;
2932 ax_reg_mask (ax, tdep->ppc_gp0_regnum + reg_index);
2933 ax_reg_mask (ax, tdep->ppc_ev0_upper_regnum + reg_index);
2935 else if (IS_DFP_PSEUDOREG (tdep, reg_nr))
2937 int reg_index = reg_nr - tdep->ppc_dl0_regnum;
2938 ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index);
2939 ax_reg_mask (ax, tdep->ppc_fp0_regnum + 2 * reg_index + 1);
2941 else if (IS_VSX_PSEUDOREG (tdep, reg_nr))
2943 int reg_index = reg_nr - tdep->ppc_vsr0_regnum;
2946 ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index - 32);
2950 ax_reg_mask (ax, tdep->ppc_fp0_regnum + reg_index);
2951 ax_reg_mask (ax, tdep->ppc_vsr0_upper_regnum + reg_index);
2954 else if (IS_EFP_PSEUDOREG (tdep, reg_nr))
2956 int reg_index = reg_nr - tdep->ppc_efpr0_regnum;
2957 ax_reg_mask (ax, tdep->ppc_vr0_regnum + reg_index);
2960 internal_error (__FILE__, __LINE__,
2961 _("rs6000_pseudo_register_collect: "
2962 "called on unexpected register '%s' (%d)"),
2963 gdbarch_register_name (gdbarch, reg_nr), reg_nr);
2969 rs6000_gen_return_address (struct gdbarch *gdbarch,
2970 struct agent_expr *ax, struct axs_value *value,
2973 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2974 value->type = register_type (gdbarch, tdep->ppc_lr_regnum);
2975 value->kind = axs_lvalue_register;
2976 value->u.reg = tdep->ppc_lr_regnum;
2980 /* Convert a DBX STABS register number to a GDB register number. */
2982 rs6000_stab_reg_to_regnum (struct gdbarch *gdbarch, int num)
2984 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
2986 if (0 <= num && num <= 31)
2987 return tdep->ppc_gp0_regnum + num;
2988 else if (32 <= num && num <= 63)
2989 /* FIXME: jimb/2004-05-05: What should we do when the debug info
2990 specifies registers the architecture doesn't have? Our
2991 callers don't check the value we return. */
2992 return tdep->ppc_fp0_regnum + (num - 32);
2993 else if (77 <= num && num <= 108)
2994 return tdep->ppc_vr0_regnum + (num - 77);
2995 else if (1200 <= num && num < 1200 + 32)
2996 return tdep->ppc_ev0_upper_regnum + (num - 1200);
3001 return tdep->ppc_mq_regnum;
3003 return tdep->ppc_lr_regnum;
3005 return tdep->ppc_ctr_regnum;
3007 return tdep->ppc_xer_regnum;
3009 return tdep->ppc_vrsave_regnum;
3011 return tdep->ppc_vrsave_regnum - 1; /* vscr */
3013 return tdep->ppc_acc_regnum;
3015 return tdep->ppc_spefscr_regnum;
3022 /* Convert a Dwarf 2 register number to a GDB register number. */
3024 rs6000_dwarf2_reg_to_regnum (struct gdbarch *gdbarch, int num)
3026 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3028 if (0 <= num && num <= 31)
3029 return tdep->ppc_gp0_regnum + num;
3030 else if (32 <= num && num <= 63)
3031 /* FIXME: jimb/2004-05-05: What should we do when the debug info
3032 specifies registers the architecture doesn't have? Our
3033 callers don't check the value we return. */
3034 return tdep->ppc_fp0_regnum + (num - 32);
3035 else if (1124 <= num && num < 1124 + 32)
3036 return tdep->ppc_vr0_regnum + (num - 1124);
3037 else if (1200 <= num && num < 1200 + 32)
3038 return tdep->ppc_ev0_upper_regnum + (num - 1200);
3043 return tdep->ppc_cr_regnum;
3045 return tdep->ppc_vrsave_regnum - 1; /* vscr */
3047 return tdep->ppc_acc_regnum;
3049 return tdep->ppc_mq_regnum;
3051 return tdep->ppc_xer_regnum;
3053 return tdep->ppc_lr_regnum;
3055 return tdep->ppc_ctr_regnum;
3057 return tdep->ppc_vrsave_regnum;
3059 return tdep->ppc_spefscr_regnum;
3065 /* Translate a .eh_frame register to DWARF register, or adjust a
3066 .debug_frame register. */
3069 rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p)
3071 /* GCC releases before 3.4 use GCC internal register numbering in
3072 .debug_frame (and .debug_info, et cetera). The numbering is
3073 different from the standard SysV numbering for everything except
3074 for GPRs and FPRs. We can not detect this problem in most cases
3075 - to get accurate debug info for variables living in lr, ctr, v0,
3076 et cetera, use a newer version of GCC. But we must detect
3077 one important case - lr is in column 65 in .debug_frame output,
3080 GCC 3.4, and the "hammer" branch, have a related problem. They
3081 record lr register saves in .debug_frame as 108, but still record
3082 the return column as 65. We fix that up too.
3084 We can do this because 65 is assigned to fpsr, and GCC never
3085 generates debug info referring to it. To add support for
3086 handwritten debug info that restores fpsr, we would need to add a
3087 producer version check to this. */
3096 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC
3097 internal register numbering; translate that to the standard DWARF2
3098 register numbering. */
3099 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */
3101 else if (68 <= num && num <= 75) /* cr0-cr8 */
3102 return num - 68 + 86;
3103 else if (77 <= num && num <= 108) /* vr0-vr31 */
3104 return num - 77 + 1124;
3116 case 109: /* vrsave */
3118 case 110: /* vscr */
3120 case 111: /* spe_acc */
3122 case 112: /* spefscr */
3130 /* Handling the various POWER/PowerPC variants. */
3132 /* Information about a particular processor variant. */
3136 /* Name of this variant. */
3139 /* English description of the variant. */
3142 /* bfd_arch_info.arch corresponding to variant. */
3143 enum bfd_architecture arch;
3145 /* bfd_arch_info.mach corresponding to variant. */
3148 /* Target description for this variant. */
3149 struct target_desc **tdesc;
3152 static struct variant variants[] =
3154 {"powerpc", "PowerPC user-level", bfd_arch_powerpc,
3155 bfd_mach_ppc, &tdesc_powerpc_altivec32},
3156 {"power", "POWER user-level", bfd_arch_rs6000,
3157 bfd_mach_rs6k, &tdesc_rs6000},
3158 {"403", "IBM PowerPC 403", bfd_arch_powerpc,
3159 bfd_mach_ppc_403, &tdesc_powerpc_403},
3160 {"405", "IBM PowerPC 405", bfd_arch_powerpc,
3161 bfd_mach_ppc_405, &tdesc_powerpc_405},
3162 {"601", "Motorola PowerPC 601", bfd_arch_powerpc,
3163 bfd_mach_ppc_601, &tdesc_powerpc_601},
3164 {"602", "Motorola PowerPC 602", bfd_arch_powerpc,
3165 bfd_mach_ppc_602, &tdesc_powerpc_602},
3166 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc,
3167 bfd_mach_ppc_603, &tdesc_powerpc_603},
3168 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc,
3169 604, &tdesc_powerpc_604},
3170 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc,
3171 bfd_mach_ppc_403gc, &tdesc_powerpc_403gc},
3172 {"505", "Motorola PowerPC 505", bfd_arch_powerpc,
3173 bfd_mach_ppc_505, &tdesc_powerpc_505},
3174 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc,
3175 bfd_mach_ppc_860, &tdesc_powerpc_860},
3176 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc,
3177 bfd_mach_ppc_750, &tdesc_powerpc_750},
3178 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc,
3179 bfd_mach_ppc_7400, &tdesc_powerpc_7400},
3180 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc,
3181 bfd_mach_ppc_e500, &tdesc_powerpc_e500},
3184 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc,
3185 bfd_mach_ppc64, &tdesc_powerpc_altivec64},
3186 {"620", "Motorola PowerPC 620", bfd_arch_powerpc,
3187 bfd_mach_ppc_620, &tdesc_powerpc_64},
3188 {"630", "Motorola PowerPC 630", bfd_arch_powerpc,
3189 bfd_mach_ppc_630, &tdesc_powerpc_64},
3190 {"a35", "PowerPC A35", bfd_arch_powerpc,
3191 bfd_mach_ppc_a35, &tdesc_powerpc_64},
3192 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc,
3193 bfd_mach_ppc_rs64ii, &tdesc_powerpc_64},
3194 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc,
3195 bfd_mach_ppc_rs64iii, &tdesc_powerpc_64},
3197 /* FIXME: I haven't checked the register sets of the following. */
3198 {"rs1", "IBM POWER RS1", bfd_arch_rs6000,
3199 bfd_mach_rs6k_rs1, &tdesc_rs6000},
3200 {"rsc", "IBM POWER RSC", bfd_arch_rs6000,
3201 bfd_mach_rs6k_rsc, &tdesc_rs6000},
3202 {"rs2", "IBM POWER RS2", bfd_arch_rs6000,
3203 bfd_mach_rs6k_rs2, &tdesc_rs6000},
3205 {0, 0, (enum bfd_architecture) 0, 0, 0}
3208 /* Return the variant corresponding to architecture ARCH and machine number
3209 MACH. If no such variant exists, return null. */
3211 static const struct variant *
3212 find_variant_by_arch (enum bfd_architecture arch, unsigned long mach)
3214 const struct variant *v;
3216 for (v = variants; v->name; v++)
3217 if (arch == v->arch && mach == v->mach)
3224 gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info)
3226 if (info->endian == BFD_ENDIAN_BIG)
3227 return print_insn_big_powerpc (memaddr, info);
3229 return print_insn_little_powerpc (memaddr, info);
3233 rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
3235 return frame_unwind_register_unsigned (next_frame,
3236 gdbarch_pc_regnum (gdbarch));
3239 static struct frame_id
3240 rs6000_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
3242 return frame_id_build (get_frame_register_unsigned
3243 (this_frame, gdbarch_sp_regnum (gdbarch)),
3244 get_frame_pc (this_frame));
3247 struct rs6000_frame_cache
3250 CORE_ADDR initial_sp;
3251 struct trad_frame_saved_reg *saved_regs;
3253 /* Set BASE_P to true if this frame cache is properly initialized.
3254 Otherwise set to false because some registers or memory cannot
3257 /* Cache PC for building unavailable frame. */
3261 static struct rs6000_frame_cache *
3262 rs6000_frame_cache (struct frame_info *this_frame, void **this_cache)
3264 struct rs6000_frame_cache *cache;
3265 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3266 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3267 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
3268 struct rs6000_framedata fdata;
3269 int wordsize = tdep->wordsize;
3270 CORE_ADDR func = 0, pc = 0;
3272 if ((*this_cache) != NULL)
3273 return (struct rs6000_frame_cache *) (*this_cache);
3274 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3275 (*this_cache) = cache;
3277 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3281 func = get_frame_func (this_frame);
3283 pc = get_frame_pc (this_frame);
3284 skip_prologue (gdbarch, func, pc, &fdata);
3286 /* Figure out the parent's stack pointer. */
3288 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most
3289 address of the current frame. Things might be easier if the
3290 ->frame pointed to the outer-most address of the frame. In
3291 the mean time, the address of the prev frame is used as the
3292 base address of this frame. */
3293 cache->base = get_frame_register_unsigned
3294 (this_frame, gdbarch_sp_regnum (gdbarch));
3296 CATCH (ex, RETURN_MASK_ERROR)
3298 if (ex.error != NOT_AVAILABLE_ERROR)
3299 throw_exception (ex);
3300 return (struct rs6000_frame_cache *) (*this_cache);
3304 /* If the function appears to be frameless, check a couple of likely
3305 indicators that we have simply failed to find the frame setup.
3306 Two common cases of this are missing symbols (i.e.
3307 get_frame_func returns the wrong address or 0), and assembly
3308 stubs which have a fast exit path but set up a frame on the slow
3311 If the LR appears to return to this function, then presume that
3312 we have an ABI compliant frame that we failed to find. */
3313 if (fdata.frameless && fdata.lr_offset == 0)
3318 saved_lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
3319 if (func == 0 && saved_lr == pc)
3323 CORE_ADDR saved_func = get_pc_function_start (saved_lr);
3324 if (func == saved_func)
3330 fdata.frameless = 0;
3331 fdata.lr_offset = tdep->lr_frame_offset;
3335 if (!fdata.frameless)
3337 /* Frameless really means stackless. */
3340 if (safe_read_memory_unsigned_integer (cache->base, wordsize,
3341 byte_order, &backchain))
3342 cache->base = (CORE_ADDR) backchain;
3345 trad_frame_set_value (cache->saved_regs,
3346 gdbarch_sp_regnum (gdbarch), cache->base);
3348 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr.
3349 All fpr's from saved_fpr to fp31 are saved. */
3351 if (fdata.saved_fpr >= 0)
3354 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset;
3356 /* If skip_prologue says floating-point registers were saved,
3357 but the current architecture has no floating-point registers,
3358 then that's strange. But we have no indices to even record
3359 the addresses under, so we just ignore it. */
3360 if (ppc_floating_point_unit_p (gdbarch))
3361 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++)
3363 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr;
3368 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr.
3369 All gpr's from saved_gpr to gpr31 are saved (except during the
3372 if (fdata.saved_gpr >= 0)
3375 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset;
3376 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++)
3378 if (fdata.gpr_mask & (1U << i))
3379 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr;
3380 gpr_addr += wordsize;
3384 /* if != -1, fdata.saved_vr is the smallest number of saved_vr.
3385 All vr's from saved_vr to vr31 are saved. */
3386 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1)
3388 if (fdata.saved_vr >= 0)
3391 CORE_ADDR vr_addr = cache->base + fdata.vr_offset;
3392 for (i = fdata.saved_vr; i < 32; i++)
3394 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr;
3395 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum);
3400 /* if != -1, fdata.saved_ev is the smallest number of saved_ev.
3401 All vr's from saved_ev to ev31 are saved. ????? */
3402 if (tdep->ppc_ev0_regnum != -1)
3404 if (fdata.saved_ev >= 0)
3407 CORE_ADDR ev_addr = cache->base + fdata.ev_offset;
3408 CORE_ADDR off = (byte_order == BFD_ENDIAN_BIG ? 4 : 0);
3410 for (i = fdata.saved_ev; i < ppc_num_gprs; i++)
3412 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr;
3413 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + off;
3414 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum);
3419 /* If != 0, fdata.cr_offset is the offset from the frame that
3421 if (fdata.cr_offset != 0)
3422 cache->saved_regs[tdep->ppc_cr_regnum].addr
3423 = cache->base + fdata.cr_offset;
3425 /* If != 0, fdata.lr_offset is the offset from the frame that
3427 if (fdata.lr_offset != 0)
3428 cache->saved_regs[tdep->ppc_lr_regnum].addr
3429 = cache->base + fdata.lr_offset;
3430 else if (fdata.lr_register != -1)
3431 cache->saved_regs[tdep->ppc_lr_regnum].realreg = fdata.lr_register;
3432 /* The PC is found in the link register. */
3433 cache->saved_regs[gdbarch_pc_regnum (gdbarch)] =
3434 cache->saved_regs[tdep->ppc_lr_regnum];
3436 /* If != 0, fdata.vrsave_offset is the offset from the frame that
3437 holds the VRSAVE. */
3438 if (fdata.vrsave_offset != 0)
3439 cache->saved_regs[tdep->ppc_vrsave_regnum].addr
3440 = cache->base + fdata.vrsave_offset;
3442 if (fdata.alloca_reg < 0)
3443 /* If no alloca register used, then fi->frame is the value of the
3444 %sp for this frame, and it is good enough. */
3446 = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
3449 = get_frame_register_unsigned (this_frame, fdata.alloca_reg);
3456 rs6000_frame_this_id (struct frame_info *this_frame, void **this_cache,
3457 struct frame_id *this_id)
3459 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3464 (*this_id) = frame_id_build_unavailable_stack (info->pc);
3468 /* This marks the outermost frame. */
3469 if (info->base == 0)
3472 (*this_id) = frame_id_build (info->base, get_frame_func (this_frame));
3475 static struct value *
3476 rs6000_frame_prev_register (struct frame_info *this_frame,
3477 void **this_cache, int regnum)
3479 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3481 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3484 static const struct frame_unwind rs6000_frame_unwind =
3487 default_frame_unwind_stop_reason,
3488 rs6000_frame_this_id,
3489 rs6000_frame_prev_register,
3491 default_frame_sniffer
3494 /* Allocate and initialize a frame cache for an epilogue frame.
3495 SP is restored and prev-PC is stored in LR. */
3497 static struct rs6000_frame_cache *
3498 rs6000_epilogue_frame_cache (struct frame_info *this_frame, void **this_cache)
3500 struct rs6000_frame_cache *cache;
3501 struct gdbarch *gdbarch = get_frame_arch (this_frame);
3502 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3505 return (struct rs6000_frame_cache *) *this_cache;
3507 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache);
3508 (*this_cache) = cache;
3509 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
3513 /* At this point the stack looks as if we just entered the
3514 function, and the return address is stored in LR. */
3517 sp = get_frame_register_unsigned (this_frame, gdbarch_sp_regnum (gdbarch));
3518 lr = get_frame_register_unsigned (this_frame, tdep->ppc_lr_regnum);
3521 cache->initial_sp = sp;
3523 trad_frame_set_value (cache->saved_regs,
3524 gdbarch_pc_regnum (gdbarch), lr);
3526 CATCH (ex, RETURN_MASK_ERROR)
3528 if (ex.error != NOT_AVAILABLE_ERROR)
3529 throw_exception (ex);
3536 /* Implementation of frame_unwind.this_id, as defined in frame_unwind.h.
3537 Return the frame ID of an epilogue frame. */
3540 rs6000_epilogue_frame_this_id (struct frame_info *this_frame,
3541 void **this_cache, struct frame_id *this_id)
3544 struct rs6000_frame_cache *info =
3545 rs6000_epilogue_frame_cache (this_frame, this_cache);
3547 pc = get_frame_func (this_frame);
3548 if (info->base == 0)
3549 (*this_id) = frame_id_build_unavailable_stack (pc);
3551 (*this_id) = frame_id_build (info->base, pc);
3554 /* Implementation of frame_unwind.prev_register, as defined in frame_unwind.h.
3555 Return the register value of REGNUM in previous frame. */
3557 static struct value *
3558 rs6000_epilogue_frame_prev_register (struct frame_info *this_frame,
3559 void **this_cache, int regnum)
3561 struct rs6000_frame_cache *info =
3562 rs6000_epilogue_frame_cache (this_frame, this_cache);
3563 return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
3566 /* Implementation of frame_unwind.sniffer, as defined in frame_unwind.h.
3567 Check whether this an epilogue frame. */
3570 rs6000_epilogue_frame_sniffer (const struct frame_unwind *self,
3571 struct frame_info *this_frame,
3572 void **this_prologue_cache)
3574 if (frame_relative_level (this_frame) == 0)
3575 return rs6000_in_function_epilogue_frame_p (this_frame,
3576 get_frame_arch (this_frame),
3577 get_frame_pc (this_frame));
3582 /* Frame unwinder for epilogue frame. This is required for reverse step-over
3583 a function without debug information. */
3585 static const struct frame_unwind rs6000_epilogue_frame_unwind =
3588 default_frame_unwind_stop_reason,
3589 rs6000_epilogue_frame_this_id, rs6000_epilogue_frame_prev_register,
3591 rs6000_epilogue_frame_sniffer
3596 rs6000_frame_base_address (struct frame_info *this_frame, void **this_cache)
3598 struct rs6000_frame_cache *info = rs6000_frame_cache (this_frame,
3600 return info->initial_sp;
3603 static const struct frame_base rs6000_frame_base = {
3604 &rs6000_frame_unwind,
3605 rs6000_frame_base_address,
3606 rs6000_frame_base_address,
3607 rs6000_frame_base_address
3610 static const struct frame_base *
3611 rs6000_frame_base_sniffer (struct frame_info *this_frame)
3613 return &rs6000_frame_base;
3616 /* DWARF-2 frame support. Used to handle the detection of
3617 clobbered registers during function calls. */
3620 ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
3621 struct dwarf2_frame_state_reg *reg,
3622 struct frame_info *this_frame)
3624 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3626 /* PPC32 and PPC64 ABI's are the same regarding volatile and
3627 non-volatile registers. We will use the same code for both. */
3629 /* Call-saved GP registers. */
3630 if ((regnum >= tdep->ppc_gp0_regnum + 14
3631 && regnum <= tdep->ppc_gp0_regnum + 31)
3632 || (regnum == tdep->ppc_gp0_regnum + 1))
3633 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3635 /* Call-clobbered GP registers. */
3636 if ((regnum >= tdep->ppc_gp0_regnum + 3
3637 && regnum <= tdep->ppc_gp0_regnum + 12)
3638 || (regnum == tdep->ppc_gp0_regnum))
3639 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3641 /* Deal with FP registers, if supported. */
3642 if (tdep->ppc_fp0_regnum >= 0)
3644 /* Call-saved FP registers. */
3645 if ((regnum >= tdep->ppc_fp0_regnum + 14
3646 && regnum <= tdep->ppc_fp0_regnum + 31))
3647 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3649 /* Call-clobbered FP registers. */
3650 if ((regnum >= tdep->ppc_fp0_regnum
3651 && regnum <= tdep->ppc_fp0_regnum + 13))
3652 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3655 /* Deal with ALTIVEC registers, if supported. */
3656 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0)
3658 /* Call-saved Altivec registers. */
3659 if ((regnum >= tdep->ppc_vr0_regnum + 20
3660 && regnum <= tdep->ppc_vr0_regnum + 31)
3661 || regnum == tdep->ppc_vrsave_regnum)
3662 reg->how = DWARF2_FRAME_REG_SAME_VALUE;
3664 /* Call-clobbered Altivec registers. */
3665 if ((regnum >= tdep->ppc_vr0_regnum
3666 && regnum <= tdep->ppc_vr0_regnum + 19))
3667 reg->how = DWARF2_FRAME_REG_UNDEFINED;
3670 /* Handle PC register and Stack Pointer correctly. */
3671 if (regnum == gdbarch_pc_regnum (gdbarch))
3672 reg->how = DWARF2_FRAME_REG_RA;
3673 else if (regnum == gdbarch_sp_regnum (gdbarch))
3674 reg->how = DWARF2_FRAME_REG_CFA;
3678 /* Return true if a .gnu_attributes section exists in BFD and it
3679 indicates we are using SPE extensions OR if a .PPC.EMB.apuinfo
3680 section exists in BFD and it indicates that SPE extensions are in
3681 use. Check the .gnu.attributes section first, as the binary might be
3682 compiled for SPE, but not actually using SPE instructions. */
3685 bfd_uses_spe_extensions (bfd *abfd)
3688 gdb_byte *contents = NULL;
3698 /* Using Tag_GNU_Power_ABI_Vector here is a bit of a hack, as the user
3699 could be using the SPE vector abi without actually using any spe
3700 bits whatsoever. But it's close enough for now. */
3701 vector_abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_GNU,
3702 Tag_GNU_Power_ABI_Vector);
3703 if (vector_abi == 3)
3707 sect = bfd_get_section_by_name (abfd, ".PPC.EMB.apuinfo");
3711 size = bfd_get_section_size (sect);
3712 contents = (gdb_byte *) xmalloc (size);
3713 if (!bfd_get_section_contents (abfd, sect, contents, 0, size))
3719 /* Parse the .PPC.EMB.apuinfo section. The layout is as follows:
3725 char name[name_len rounded up to 4-byte alignment];
3726 char data[data_len];
3729 Technically, there's only supposed to be one such structure in a
3730 given apuinfo section, but the linker is not always vigilant about
3731 merging apuinfo sections from input files. Just go ahead and parse
3732 them all, exiting early when we discover the binary uses SPE
3735 It's not specified in what endianness the information in this
3736 section is stored. Assume that it's the endianness of the BFD. */
3740 unsigned int name_len;
3741 unsigned int data_len;
3744 /* If we can't read the first three fields, we're done. */
3748 name_len = bfd_get_32 (abfd, ptr);
3749 name_len = (name_len + 3) & ~3U; /* Round to 4 bytes. */
3750 data_len = bfd_get_32 (abfd, ptr + 4);
3751 type = bfd_get_32 (abfd, ptr + 8);
3754 /* The name must be "APUinfo\0". */
3756 && strcmp ((const char *) ptr, "APUinfo") != 0)
3760 /* The type must be 2. */
3764 /* The data is stored as a series of uint32. The upper half of
3765 each uint32 indicates the particular APU used and the lower
3766 half indicates the revision of that APU. We just care about
3769 /* Not 4-byte quantities. */
3775 unsigned int apuinfo = bfd_get_32 (abfd, ptr);
3776 unsigned int apu = apuinfo >> 16;
3780 /* The SPE APU is 0x100; the SPEFP APU is 0x101. Accept
3782 if (apu == 0x100 || apu == 0x101)
3797 /* These are macros for parsing instruction fields (I.1.6.28) */
3799 #define PPC_FIELD(value, from, len) \
3800 (((value) >> (32 - (from) - (len))) & ((1 << (len)) - 1))
3801 #define PPC_SEXT(v, bs) \
3802 ((((CORE_ADDR) (v) & (((CORE_ADDR) 1 << (bs)) - 1)) \
3803 ^ ((CORE_ADDR) 1 << ((bs) - 1))) \
3804 - ((CORE_ADDR) 1 << ((bs) - 1)))
3805 #define PPC_OP6(insn) PPC_FIELD (insn, 0, 6)
3806 #define PPC_EXTOP(insn) PPC_FIELD (insn, 21, 10)
3807 #define PPC_RT(insn) PPC_FIELD (insn, 6, 5)
3808 #define PPC_RS(insn) PPC_FIELD (insn, 6, 5)
3809 #define PPC_RA(insn) PPC_FIELD (insn, 11, 5)
3810 #define PPC_RB(insn) PPC_FIELD (insn, 16, 5)
3811 #define PPC_NB(insn) PPC_FIELD (insn, 16, 5)
3812 #define PPC_VRT(insn) PPC_FIELD (insn, 6, 5)
3813 #define PPC_FRT(insn) PPC_FIELD (insn, 6, 5)
3814 #define PPC_SPR(insn) (PPC_FIELD (insn, 11, 5) \
3815 | (PPC_FIELD (insn, 16, 5) << 5))
3816 #define PPC_BO(insn) PPC_FIELD (insn, 6, 5)
3817 #define PPC_T(insn) PPC_FIELD (insn, 6, 5)
3818 #define PPC_D(insn) PPC_SEXT (PPC_FIELD (insn, 16, 16), 16)
3819 #define PPC_DS(insn) PPC_SEXT (PPC_FIELD (insn, 16, 14), 14)
3820 #define PPC_BIT(insn,n) ((insn & (1 << (31 - (n)))) ? 1 : 0)
3821 #define PPC_OE(insn) PPC_BIT (insn, 21)
3822 #define PPC_RC(insn) PPC_BIT (insn, 31)
3823 #define PPC_Rc(insn) PPC_BIT (insn, 21)
3824 #define PPC_LK(insn) PPC_BIT (insn, 31)
3825 #define PPC_TX(insn) PPC_BIT (insn, 31)
3826 #define PPC_LEV(insn) PPC_FIELD (insn, 20, 7)
3828 #define PPC_XT(insn) ((PPC_TX (insn) << 5) | PPC_T (insn))
3829 #define PPC_XER_NB(xer) (xer & 0x7f)
3831 /* Record Vector-Scalar Registers.
3832 For VSR less than 32, it's represented by an FPR and an VSR-upper register.
3833 Otherwise, it's just a VR register. Record them accordingly. */
3836 ppc_record_vsr (struct regcache *regcache, struct gdbarch_tdep *tdep, int vsr)
3838 if (vsr < 0 || vsr >= 64)
3843 if (tdep->ppc_vr0_regnum >= 0)
3844 record_full_arch_list_add_reg (regcache, tdep->ppc_vr0_regnum + vsr - 32);
3848 if (tdep->ppc_fp0_regnum >= 0)
3849 record_full_arch_list_add_reg (regcache, tdep->ppc_fp0_regnum + vsr);
3850 if (tdep->ppc_vsr0_upper_regnum >= 0)
3851 record_full_arch_list_add_reg (regcache,
3852 tdep->ppc_vsr0_upper_regnum + vsr);
3858 /* Parse and record instructions primary opcode-4 at ADDR.
3859 Return 0 if successful. */
3862 ppc_process_record_op4 (struct gdbarch *gdbarch, struct regcache *regcache,
3863 CORE_ADDR addr, uint32_t insn)
3865 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
3866 int ext = PPC_FIELD (insn, 21, 11);
3870 case 32: /* Vector Multiply-High-Add Signed Halfword Saturate */
3871 case 33: /* Vector Multiply-High-Round-Add Signed Halfword Saturate */
3872 case 39: /* Vector Multiply-Sum Unsigned Halfword Saturate */
3873 case 41: /* Vector Multiply-Sum Signed Halfword Saturate */
3874 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
3876 case 42: /* Vector Select */
3877 case 43: /* Vector Permute */
3878 case 44: /* Vector Shift Left Double by Octet Immediate */
3879 case 45: /* Vector Permute and Exclusive-OR */
3880 case 60: /* Vector Add Extended Unsigned Quadword Modulo */
3881 case 61: /* Vector Add Extended & write Carry Unsigned Quadword */
3882 case 62: /* Vector Subtract Extended Unsigned Quadword Modulo */
3883 case 63: /* Vector Subtract Extended & write Carry Unsigned Quadword */
3884 case 34: /* Vector Multiply-Low-Add Unsigned Halfword Modulo */
3885 case 36: /* Vector Multiply-Sum Unsigned Byte Modulo */
3886 case 37: /* Vector Multiply-Sum Mixed Byte Modulo */
3887 case 38: /* Vector Multiply-Sum Unsigned Halfword Modulo */
3888 case 40: /* Vector Multiply-Sum Signed Halfword Modulo */
3889 case 46: /* Vector Multiply-Add Single-Precision */
3890 case 47: /* Vector Negative Multiply-Subtract Single-Precision */
3891 record_full_arch_list_add_reg (regcache,
3892 tdep->ppc_vr0_regnum + PPC_VRT (insn));
3896 switch ((ext & 0x1ff))
3898 /* 5.16 Decimal Integer Arithmetic Instructions */
3899 case 1: /* Decimal Add Modulo */
3900 case 65: /* Decimal Subtract Modulo */
3902 /* Bit-21 should be set. */
3903 if (!PPC_BIT (insn, 21))
3906 record_full_arch_list_add_reg (regcache,
3907 tdep->ppc_vr0_regnum + PPC_VRT (insn));
3908 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
3912 /* Bit-21 is used for RC */
3913 switch (ext & 0x3ff)
3915 case 6: /* Vector Compare Equal To Unsigned Byte */
3916 case 70: /* Vector Compare Equal To Unsigned Halfword */
3917 case 134: /* Vector Compare Equal To Unsigned Word */
3918 case 199: /* Vector Compare Equal To Unsigned Doubleword */
3919 case 774: /* Vector Compare Greater Than Signed Byte */
3920 case 838: /* Vector Compare Greater Than Signed Halfword */
3921 case 902: /* Vector Compare Greater Than Signed Word */
3922 case 967: /* Vector Compare Greater Than Signed Doubleword */
3923 case 518: /* Vector Compare Greater Than Unsigned Byte */
3924 case 646: /* Vector Compare Greater Than Unsigned Word */
3925 case 582: /* Vector Compare Greater Than Unsigned Halfword */
3926 case 711: /* Vector Compare Greater Than Unsigned Doubleword */
3927 case 966: /* Vector Compare Bounds Single-Precision */
3928 case 198: /* Vector Compare Equal To Single-Precision */
3929 case 454: /* Vector Compare Greater Than or Equal To Single-Precision */
3930 case 710: /* Vector Compare Greater Than Single-Precision */
3932 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
3933 record_full_arch_list_add_reg (regcache,
3934 tdep->ppc_vr0_regnum + PPC_VRT (insn));
3940 case 142: /* Vector Pack Unsigned Halfword Unsigned Saturate */
3941 case 206: /* Vector Pack Unsigned Word Unsigned Saturate */
3942 case 270: /* Vector Pack Signed Halfword Unsigned Saturate */
3943 case 334: /* Vector Pack Signed Word Unsigned Saturate */
3944 case 398: /* Vector Pack Signed Halfword Signed Saturate */
3945 case 462: /* Vector Pack Signed Word Signed Saturate */
3946 case 1230: /* Vector Pack Unsigned Doubleword Unsigned Saturate */
3947 case 1358: /* Vector Pack Signed Doubleword Unsigned Saturate */
3948 case 1486: /* Vector Pack Signed Doubleword Signed Saturate */
3949 case 512: /* Vector Add Unsigned Byte Saturate */
3950 case 576: /* Vector Add Unsigned Halfword Saturate */
3951 case 640: /* Vector Add Unsigned Word Saturate */
3952 case 768: /* Vector Add Signed Byte Saturate */
3953 case 832: /* Vector Add Signed Halfword Saturate */
3954 case 896: /* Vector Add Signed Word Saturate */
3955 case 1536: /* Vector Subtract Unsigned Byte Saturate */
3956 case 1600: /* Vector Subtract Unsigned Halfword Saturate */
3957 case 1664: /* Vector Subtract Unsigned Word Saturate */
3958 case 1792: /* Vector Subtract Signed Byte Saturate */
3959 case 1856: /* Vector Subtract Signed Halfword Saturate */
3960 case 1920: /* Vector Subtract Signed Word Saturate */
3962 case 1544: /* Vector Sum across Quarter Unsigned Byte Saturate */
3963 case 1800: /* Vector Sum across Quarter Signed Byte Saturate */
3964 case 1608: /* Vector Sum across Quarter Signed Halfword Saturate */
3965 case 1672: /* Vector Sum across Half Signed Word Saturate */
3966 case 1928: /* Vector Sum across Signed Word Saturate */
3967 case 970: /* Vector Convert To Signed Fixed-Point Word Saturate */
3968 case 906: /* Vector Convert To Unsigned Fixed-Point Word Saturate */
3969 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
3971 case 12: /* Vector Merge High Byte */
3972 case 14: /* Vector Pack Unsigned Halfword Unsigned Modulo */
3973 case 76: /* Vector Merge High Halfword */
3974 case 78: /* Vector Pack Unsigned Word Unsigned Modulo */
3975 case 140: /* Vector Merge High Word */
3976 case 268: /* Vector Merge Low Byte */
3977 case 332: /* Vector Merge Low Halfword */
3978 case 396: /* Vector Merge Low Word */
3979 case 526: /* Vector Unpack High Signed Byte */
3980 case 590: /* Vector Unpack High Signed Halfword */
3981 case 654: /* Vector Unpack Low Signed Byte */
3982 case 718: /* Vector Unpack Low Signed Halfword */
3983 case 782: /* Vector Pack Pixel */
3984 case 846: /* Vector Unpack High Pixel */
3985 case 974: /* Vector Unpack Low Pixel */
3986 case 1102: /* Vector Pack Unsigned Doubleword Unsigned Modulo */
3987 case 1614: /* Vector Unpack High Signed Word */
3988 case 1676: /* Vector Merge Odd Word */
3989 case 1742: /* Vector Unpack Low Signed Word */
3990 case 1932: /* Vector Merge Even Word */
3991 case 524: /* Vector Splat Byte */
3992 case 588: /* Vector Splat Halfword */
3993 case 652: /* Vector Splat Word */
3994 case 780: /* Vector Splat Immediate Signed Byte */
3995 case 844: /* Vector Splat Immediate Signed Halfword */
3996 case 908: /* Vector Splat Immediate Signed Word */
3997 case 452: /* Vector Shift Left */
3998 case 708: /* Vector Shift Right */
3999 case 1036: /* Vector Shift Left by Octet */
4000 case 1100: /* Vector Shift Right by Octet */
4001 case 0: /* Vector Add Unsigned Byte Modulo */
4002 case 64: /* Vector Add Unsigned Halfword Modulo */
4003 case 128: /* Vector Add Unsigned Word Modulo */
4004 case 192: /* Vector Add Unsigned Doubleword Modulo */
4005 case 256: /* Vector Add Unsigned Quadword Modulo */
4006 case 320: /* Vector Add & write Carry Unsigned Quadword */
4007 case 384: /* Vector Add and Write Carry-Out Unsigned Word */
4008 case 8: /* Vector Multiply Odd Unsigned Byte */
4009 case 72: /* Vector Multiply Odd Unsigned Halfword */
4010 case 136: /* Vector Multiply Odd Unsigned Word */
4011 case 264: /* Vector Multiply Odd Signed Byte */
4012 case 328: /* Vector Multiply Odd Signed Halfword */
4013 case 392: /* Vector Multiply Odd Signed Word */
4014 case 520: /* Vector Multiply Even Unsigned Byte */
4015 case 584: /* Vector Multiply Even Unsigned Halfword */
4016 case 648: /* Vector Multiply Even Unsigned Word */
4017 case 776: /* Vector Multiply Even Signed Byte */
4018 case 840: /* Vector Multiply Even Signed Halfword */
4019 case 904: /* Vector Multiply Even Signed Word */
4020 case 137: /* Vector Multiply Unsigned Word Modulo */
4021 case 1024: /* Vector Subtract Unsigned Byte Modulo */
4022 case 1088: /* Vector Subtract Unsigned Halfword Modulo */
4023 case 1152: /* Vector Subtract Unsigned Word Modulo */
4024 case 1216: /* Vector Subtract Unsigned Doubleword Modulo */
4025 case 1280: /* Vector Subtract Unsigned Quadword Modulo */
4026 case 1344: /* Vector Subtract & write Carry Unsigned Quadword */
4027 case 1408: /* Vector Subtract and Write Carry-Out Unsigned Word */
4028 case 1282: /* Vector Average Signed Byte */
4029 case 1346: /* Vector Average Signed Halfword */
4030 case 1410: /* Vector Average Signed Word */
4031 case 1026: /* Vector Average Unsigned Byte */
4032 case 1090: /* Vector Average Unsigned Halfword */
4033 case 1154: /* Vector Average Unsigned Word */
4034 case 258: /* Vector Maximum Signed Byte */
4035 case 322: /* Vector Maximum Signed Halfword */
4036 case 386: /* Vector Maximum Signed Word */
4037 case 450: /* Vector Maximum Signed Doubleword */
4038 case 2: /* Vector Maximum Unsigned Byte */
4039 case 66: /* Vector Maximum Unsigned Halfword */
4040 case 130: /* Vector Maximum Unsigned Word */
4041 case 194: /* Vector Maximum Unsigned Doubleword */
4042 case 770: /* Vector Minimum Signed Byte */
4043 case 834: /* Vector Minimum Signed Halfword */
4044 case 898: /* Vector Minimum Signed Word */
4045 case 962: /* Vector Minimum Signed Doubleword */
4046 case 514: /* Vector Minimum Unsigned Byte */
4047 case 578: /* Vector Minimum Unsigned Halfword */
4048 case 642: /* Vector Minimum Unsigned Word */
4049 case 706: /* Vector Minimum Unsigned Doubleword */
4050 case 1028: /* Vector Logical AND */
4051 case 1668: /* Vector Logical Equivalent */
4052 case 1092: /* Vector Logical AND with Complement */
4053 case 1412: /* Vector Logical NAND */
4054 case 1348: /* Vector Logical OR with Complement */
4055 case 1156: /* Vector Logical OR */
4056 case 1284: /* Vector Logical NOR */
4057 case 1220: /* Vector Logical XOR */
4058 case 4: /* Vector Rotate Left Byte */
4059 case 132: /* Vector Rotate Left Word VX-form */
4060 case 68: /* Vector Rotate Left Halfword */
4061 case 196: /* Vector Rotate Left Doubleword */
4062 case 260: /* Vector Shift Left Byte */
4063 case 388: /* Vector Shift Left Word */
4064 case 324: /* Vector Shift Left Halfword */
4065 case 1476: /* Vector Shift Left Doubleword */
4066 case 516: /* Vector Shift Right Byte */
4067 case 644: /* Vector Shift Right Word */
4068 case 580: /* Vector Shift Right Halfword */
4069 case 1732: /* Vector Shift Right Doubleword */
4070 case 772: /* Vector Shift Right Algebraic Byte */
4071 case 900: /* Vector Shift Right Algebraic Word */
4072 case 836: /* Vector Shift Right Algebraic Halfword */
4073 case 964: /* Vector Shift Right Algebraic Doubleword */
4074 case 10: /* Vector Add Single-Precision */
4075 case 74: /* Vector Subtract Single-Precision */
4076 case 1034: /* Vector Maximum Single-Precision */
4077 case 1098: /* Vector Minimum Single-Precision */
4078 case 842: /* Vector Convert From Signed Fixed-Point Word */
4079 case 778: /* Vector Convert From Unsigned Fixed-Point Word */
4080 case 714: /* Vector Round to Single-Precision Integer toward -Infinity */
4081 case 522: /* Vector Round to Single-Precision Integer Nearest */
4082 case 650: /* Vector Round to Single-Precision Integer toward +Infinity */
4083 case 586: /* Vector Round to Single-Precision Integer toward Zero */
4084 case 394: /* Vector 2 Raised to the Exponent Estimate Floating-Point */
4085 case 458: /* Vector Log Base 2 Estimate Floating-Point */
4086 case 266: /* Vector Reciprocal Estimate Single-Precision */
4087 case 330: /* Vector Reciprocal Square Root Estimate Single-Precision */
4088 case 1288: /* Vector AES Cipher */
4089 case 1289: /* Vector AES Cipher Last */
4090 case 1352: /* Vector AES Inverse Cipher */
4091 case 1353: /* Vector AES Inverse Cipher Last */
4092 case 1480: /* Vector AES SubBytes */
4093 case 1730: /* Vector SHA-512 Sigma Doubleword */
4094 case 1666: /* Vector SHA-256 Sigma Word */
4095 case 1032: /* Vector Polynomial Multiply-Sum Byte */
4096 case 1160: /* Vector Polynomial Multiply-Sum Word */
4097 case 1096: /* Vector Polynomial Multiply-Sum Halfword */
4098 case 1224: /* Vector Polynomial Multiply-Sum Doubleword */
4099 case 1292: /* Vector Gather Bits by Bytes by Doubleword */
4100 case 1794: /* Vector Count Leading Zeros Byte */
4101 case 1858: /* Vector Count Leading Zeros Halfword */
4102 case 1922: /* Vector Count Leading Zeros Word */
4103 case 1986: /* Vector Count Leading Zeros Doubleword */
4104 case 1795: /* Vector Population Count Byte */
4105 case 1859: /* Vector Population Count Halfword */
4106 case 1923: /* Vector Population Count Word */
4107 case 1987: /* Vector Population Count Doubleword */
4108 case 1356: /* Vector Bit Permute Quadword */
4109 record_full_arch_list_add_reg (regcache,
4110 tdep->ppc_vr0_regnum + PPC_VRT (insn));
4113 case 1604: /* Move To Vector Status and Control Register */
4114 record_full_arch_list_add_reg (regcache, PPC_VSCR_REGNUM);
4116 case 1540: /* Move From Vector Status and Control Register */
4117 record_full_arch_list_add_reg (regcache,
4118 tdep->ppc_vr0_regnum + PPC_VRT (insn));
4122 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4123 "at %s, 4-%d.\n", insn, paddress (gdbarch, addr), ext);
4127 /* Parse and record instructions of primary opcode-19 at ADDR.
4128 Return 0 if successful. */
4131 ppc_process_record_op19 (struct gdbarch *gdbarch, struct regcache *regcache,
4132 CORE_ADDR addr, uint32_t insn)
4134 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4135 int ext = PPC_EXTOP (insn);
4139 case 0: /* Move Condition Register Field */
4140 case 33: /* Condition Register NOR */
4141 case 129: /* Condition Register AND with Complement */
4142 case 193: /* Condition Register XOR */
4143 case 225: /* Condition Register NAND */
4144 case 257: /* Condition Register AND */
4145 case 289: /* Condition Register Equivalent */
4146 case 417: /* Condition Register OR with Complement */
4147 case 449: /* Condition Register OR */
4148 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4151 case 16: /* Branch Conditional */
4152 case 560: /* Branch Conditional to Branch Target Address Register */
4153 if ((PPC_BO (insn) & 0x4) == 0)
4154 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum);
4156 case 528: /* Branch Conditional to Count Register */
4158 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
4161 case 150: /* Instruction Synchronize */
4166 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4167 "at %s, 19-%d.\n", insn, paddress (gdbarch, addr), ext);
4171 /* Parse and record instructions of primary opcode-31 at ADDR.
4172 Return 0 if successful. */
4175 ppc_process_record_op31 (struct gdbarch *gdbarch, struct regcache *regcache,
4176 CORE_ADDR addr, uint32_t insn)
4178 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4179 int ext = PPC_EXTOP (insn);
4181 CORE_ADDR at_dcsz, ea = 0;
4182 ULONGEST rb, ra, xer;
4185 /* These instructions have OE bit. */
4186 switch (ext & 0x1ff)
4188 /* These write RT and XER. Update CR if RC is set. */
4189 case 8: /* Subtract from carrying */
4190 case 10: /* Add carrying */
4191 case 136: /* Subtract from extended */
4192 case 138: /* Add extended */
4193 case 200: /* Subtract from zero extended */
4194 case 202: /* Add to zero extended */
4195 case 232: /* Subtract from minus one extended */
4196 case 234: /* Add to minus one extended */
4197 /* CA is always altered, but SO/OV are only altered when OE=1.
4198 In any case, XER is always altered. */
4199 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4201 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4202 record_full_arch_list_add_reg (regcache,
4203 tdep->ppc_gp0_regnum + PPC_RT (insn));
4206 /* These write RT. Update CR if RC is set and update XER if OE is set. */
4207 case 40: /* Subtract from */
4208 case 104: /* Negate */
4209 case 233: /* Multiply low doubleword */
4210 case 235: /* Multiply low word */
4212 case 393: /* Divide Doubleword Extended Unsigned */
4213 case 395: /* Divide Word Extended Unsigned */
4214 case 425: /* Divide Doubleword Extended */
4215 case 427: /* Divide Word Extended */
4216 case 457: /* Divide Doubleword Unsigned */
4217 case 459: /* Divide Word Unsigned */
4218 case 489: /* Divide Doubleword */
4219 case 491: /* Divide Word */
4221 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4223 case 9: /* Multiply High Doubleword Unsigned */
4224 case 11: /* Multiply High Word Unsigned */
4225 case 73: /* Multiply High Doubleword */
4226 case 75: /* Multiply High Word */
4228 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4229 record_full_arch_list_add_reg (regcache,
4230 tdep->ppc_gp0_regnum + PPC_RT (insn));
4234 if ((ext & 0x1f) == 15)
4236 /* Integer Select. bit[16:20] is used for BC. */
4237 record_full_arch_list_add_reg (regcache,
4238 tdep->ppc_gp0_regnum + PPC_RT (insn));
4244 case 78: /* Determine Leftmost Zero Byte */
4246 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4247 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4248 record_full_arch_list_add_reg (regcache,
4249 tdep->ppc_gp0_regnum + PPC_RT (insn));
4252 /* These only write RT. */
4253 case 19: /* Move from condition register */
4254 /* Move From One Condition Register Field */
4255 case 74: /* Add and Generate Sixes */
4256 case 74 | 0x200: /* Add and Generate Sixes (bit-21 dont-care) */
4257 case 302: /* Move From Branch History Rolling Buffer */
4258 case 339: /* Move From Special Purpose Register */
4259 case 371: /* Move From Time Base [Phased-Out] */
4260 record_full_arch_list_add_reg (regcache,
4261 tdep->ppc_gp0_regnum + PPC_RT (insn));
4264 /* These only write to RA. */
4265 case 51: /* Move From VSR Doubleword */
4266 case 115: /* Move From VSR Word and Zero */
4267 case 122: /* Population count bytes */
4268 case 378: /* Population count words */
4269 case 506: /* Population count doublewords */
4270 case 154: /* Parity Word */
4271 case 186: /* Parity Doubleword */
4272 case 252: /* Bit Permute Doubleword */
4273 case 282: /* Convert Declets To Binary Coded Decimal */
4274 case 314: /* Convert Binary Coded Decimal To Declets */
4275 case 508: /* Compare bytes */
4276 record_full_arch_list_add_reg (regcache,
4277 tdep->ppc_gp0_regnum + PPC_RA (insn));
4280 /* These write CR and optional RA. */
4281 case 792: /* Shift Right Algebraic Word */
4282 case 794: /* Shift Right Algebraic Doubleword */
4283 case 824: /* Shift Right Algebraic Word Immediate */
4284 case 826: /* Shift Right Algebraic Doubleword Immediate (413) */
4285 case 826 | 1: /* Shift Right Algebraic Doubleword Immediate (413) */
4286 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4287 record_full_arch_list_add_reg (regcache,
4288 tdep->ppc_gp0_regnum + PPC_RA (insn));
4290 case 0: /* Compare */
4291 case 32: /* Compare logical */
4292 case 144: /* Move To Condition Register Fields */
4293 /* Move To One Condition Register Field */
4294 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4297 /* These write to RT. Update RA if 'update indexed.' */
4298 case 53: /* Load Doubleword with Update Indexed */
4299 case 119: /* Load Byte and Zero with Update Indexed */
4300 case 311: /* Load Halfword and Zero with Update Indexed */
4301 case 55: /* Load Word and Zero with Update Indexed */
4302 case 375: /* Load Halfword Algebraic with Update Indexed */
4303 case 373: /* Load Word Algebraic with Update Indexed */
4304 record_full_arch_list_add_reg (regcache,
4305 tdep->ppc_gp0_regnum + PPC_RA (insn));
4307 case 21: /* Load Doubleword Indexed */
4308 case 52: /* Load Byte And Reserve Indexed */
4309 case 116: /* Load Halfword And Reserve Indexed */
4310 case 20: /* Load Word And Reserve Indexed */
4311 case 84: /* Load Doubleword And Reserve Indexed */
4312 case 87: /* Load Byte and Zero Indexed */
4313 case 279: /* Load Halfword and Zero Indexed */
4314 case 23: /* Load Word and Zero Indexed */
4315 case 343: /* Load Halfword Algebraic Indexed */
4316 case 341: /* Load Word Algebraic Indexed */
4317 case 790: /* Load Halfword Byte-Reverse Indexed */
4318 case 534: /* Load Word Byte-Reverse Indexed */
4319 case 532: /* Load Doubleword Byte-Reverse Indexed */
4320 record_full_arch_list_add_reg (regcache,
4321 tdep->ppc_gp0_regnum + PPC_RT (insn));
4324 case 597: /* Load String Word Immediate */
4325 case 533: /* Load String Word Indexed */
4334 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer);
4335 nr = PPC_XER_NB (xer);
4340 /* If n=0, the contents of register RT are undefined. */
4344 for (i = 0; i < nr; i++)
4345 record_full_arch_list_add_reg (regcache,
4346 tdep->ppc_gp0_regnum
4347 + ((PPC_RT (insn) + i) & 0x1f));
4350 case 276: /* Load Quadword And Reserve Indexed */
4351 tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1);
4352 record_full_arch_list_add_reg (regcache, tmp);
4353 record_full_arch_list_add_reg (regcache, tmp + 1);
4356 /* These write VRT. */
4357 case 6: /* Load Vector for Shift Left Indexed */
4358 case 38: /* Load Vector for Shift Right Indexed */
4359 case 7: /* Load Vector Element Byte Indexed */
4360 case 39: /* Load Vector Element Halfword Indexed */
4361 case 71: /* Load Vector Element Word Indexed */
4362 case 103: /* Load Vector Indexed */
4363 case 359: /* Load Vector Indexed LRU */
4364 record_full_arch_list_add_reg (regcache,
4365 tdep->ppc_vr0_regnum + PPC_VRT (insn));
4368 /* These write FRT. Update RA if 'update indexed.' */
4369 case 567: /* Load Floating-Point Single with Update Indexed */
4370 case 631: /* Load Floating-Point Double with Update Indexed */
4371 record_full_arch_list_add_reg (regcache,
4372 tdep->ppc_gp0_regnum + PPC_RA (insn));
4374 case 535: /* Load Floating-Point Single Indexed */
4375 case 599: /* Load Floating-Point Double Indexed */
4376 case 855: /* Load Floating-Point as Integer Word Algebraic Indexed */
4377 case 887: /* Load Floating-Point as Integer Word and Zero Indexed */
4378 record_full_arch_list_add_reg (regcache,
4379 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4382 case 791: /* Load Floating-Point Double Pair Indexed */
4383 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
4384 record_full_arch_list_add_reg (regcache, tmp);
4385 record_full_arch_list_add_reg (regcache, tmp + 1);
4388 case 179: /* Move To VSR Doubleword */
4389 case 211: /* Move To VSR Word Algebraic */
4390 case 243: /* Move To VSR Word and Zero */
4391 case 588: /* Load VSX Scalar Doubleword Indexed */
4392 case 524: /* Load VSX Scalar Single-Precision Indexed */
4393 case 76: /* Load VSX Scalar as Integer Word Algebraic Indexed */
4394 case 12: /* Load VSX Scalar as Integer Word and Zero Indexed */
4395 case 844: /* Load VSX Vector Doubleword*2 Indexed */
4396 case 332: /* Load VSX Vector Doubleword & Splat Indexed */
4397 case 780: /* Load VSX Vector Word*4 Indexed */
4398 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
4401 /* These write RA. Update CR if RC is set. */
4402 case 24: /* Shift Left Word */
4403 case 26: /* Count Leading Zeros Word */
4404 case 27: /* Shift Left Doubleword */
4406 case 58: /* Count Leading Zeros Doubleword */
4407 case 60: /* AND with Complement */
4409 case 284: /* Equivalent */
4411 case 476: /* NAND */
4412 case 412: /* OR with Complement */
4414 case 536: /* Shift Right Word */
4415 case 539: /* Shift Right Doubleword */
4416 case 922: /* Extend Sign Halfword */
4417 case 954: /* Extend Sign Byte */
4418 case 986: /* Extend Sign Word */
4420 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4421 record_full_arch_list_add_reg (regcache,
4422 tdep->ppc_gp0_regnum + PPC_RA (insn));
4426 case 181: /* Store Doubleword with Update Indexed */
4427 case 183: /* Store Word with Update Indexed */
4428 case 247: /* Store Byte with Update Indexed */
4429 case 439: /* Store Half Word with Update Indexed */
4430 case 695: /* Store Floating-Point Single with Update Indexed */
4431 case 759: /* Store Floating-Point Double with Update Indexed */
4432 record_full_arch_list_add_reg (regcache,
4433 tdep->ppc_gp0_regnum + PPC_RA (insn));
4435 case 135: /* Store Vector Element Byte Indexed */
4436 case 167: /* Store Vector Element Halfword Indexed */
4437 case 199: /* Store Vector Element Word Indexed */
4438 case 231: /* Store Vector Indexed */
4439 case 487: /* Store Vector Indexed LRU */
4440 case 716: /* Store VSX Scalar Doubleword Indexed */
4441 case 140: /* Store VSX Scalar as Integer Word Indexed */
4442 case 652: /* Store VSX Scalar Single-Precision Indexed */
4443 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4444 case 908: /* Store VSX Vector Word*4 Indexed */
4445 case 149: /* Store Doubleword Indexed */
4446 case 151: /* Store Word Indexed */
4447 case 215: /* Store Byte Indexed */
4448 case 407: /* Store Half Word Indexed */
4449 case 694: /* Store Byte Conditional Indexed */
4450 case 726: /* Store Halfword Conditional Indexed */
4451 case 150: /* Store Word Conditional Indexed */
4452 case 214: /* Store Doubleword Conditional Indexed */
4453 case 182: /* Store Quadword Conditional Indexed */
4454 case 662: /* Store Word Byte-Reverse Indexed */
4455 case 918: /* Store Halfword Byte-Reverse Indexed */
4456 case 660: /* Store Doubleword Byte-Reverse Indexed */
4457 case 663: /* Store Floating-Point Single Indexed */
4458 case 727: /* Store Floating-Point Double Indexed */
4459 case 919: /* Store Floating-Point Double Pair Indexed */
4460 case 983: /* Store Floating-Point as Integer Word Indexed */
4461 if (ext == 694 || ext == 726 || ext == 150 || ext == 214 || ext == 182)
4462 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4465 if (PPC_RA (insn) != 0)
4466 regcache_raw_read_unsigned (regcache,
4467 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4468 regcache_raw_read_unsigned (regcache,
4469 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
4474 case 183: /* Store Word with Update Indexed */
4475 case 199: /* Store Vector Element Word Indexed */
4476 case 140: /* Store VSX Scalar as Integer Word Indexed */
4477 case 652: /* Store VSX Scalar Single-Precision Indexed */
4478 case 151: /* Store Word Indexed */
4479 case 150: /* Store Word Conditional Indexed */
4480 case 662: /* Store Word Byte-Reverse Indexed */
4481 case 663: /* Store Floating-Point Single Indexed */
4482 case 695: /* Store Floating-Point Single with Update Indexed */
4483 case 983: /* Store Floating-Point as Integer Word Indexed */
4486 case 247: /* Store Byte with Update Indexed */
4487 case 135: /* Store Vector Element Byte Indexed */
4488 case 215: /* Store Byte Indexed */
4489 case 694: /* Store Byte Conditional Indexed */
4492 case 439: /* Store Halfword with Update Indexed */
4493 case 167: /* Store Vector Element Halfword Indexed */
4494 case 407: /* Store Halfword Indexed */
4495 case 726: /* Store Halfword Conditional Indexed */
4496 case 918: /* Store Halfword Byte-Reverse Indexed */
4499 case 181: /* Store Doubleword with Update Indexed */
4500 case 716: /* Store VSX Scalar Doubleword Indexed */
4501 case 149: /* Store Doubleword Indexed */
4502 case 214: /* Store Doubleword Conditional Indexed */
4503 case 660: /* Store Doubleword Byte-Reverse Indexed */
4504 case 727: /* Store Floating-Point Double Indexed */
4505 case 759: /* Store Floating-Point Double with Update Indexed */
4508 case 972: /* Store VSX Vector Doubleword*2 Indexed */
4509 case 908: /* Store VSX Vector Word*4 Indexed */
4510 case 182: /* Store Quadword Conditional Indexed */
4511 case 231: /* Store Vector Indexed */
4512 case 487: /* Store Vector Indexed LRU */
4513 case 919: /* Store Floating-Point Double Pair Indexed */
4520 /* Align address for Store Vector instructions. */
4523 case 167: /* Store Vector Element Halfword Indexed */
4524 addr = addr & ~0x1ULL;
4527 case 199: /* Store Vector Element Word Indexed */
4528 addr = addr & ~0x3ULL;
4531 case 231: /* Store Vector Indexed */
4532 case 487: /* Store Vector Indexed LRU */
4533 addr = addr & ~0xfULL;
4537 record_full_arch_list_add_mem (addr, size);
4540 case 725: /* Store String Word Immediate */
4542 if (PPC_RA (insn) != 0)
4543 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &ra);
4550 record_full_arch_list_add_mem (ea, nb);
4554 case 661: /* Store String Word Indexed */
4556 if (PPC_RA (insn) != 0)
4557 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &ra);
4560 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &xer);
4561 nb = PPC_XER_NB (xer);
4565 regcache_raw_read_unsigned (regcache, tdep->ppc_xer_regnum, &rb);
4567 record_full_arch_list_add_mem (ea, nb);
4572 case 467: /* Move To Special Purpose Register */
4573 switch (PPC_SPR (insn))
4576 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4579 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
4582 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum);
4584 case 256: /* VRSAVE */
4585 record_full_arch_list_add_reg (regcache, tdep->ppc_vrsave_regnum);
4591 case 147: /* Move To Split Little Endian */
4592 record_full_arch_list_add_reg (regcache, tdep->ppc_ps_regnum);
4595 case 512: /* Move to Condition Register from XER */
4596 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4597 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
4600 case 4: /* Trap Word */
4601 case 68: /* Trap Doubleword */
4602 case 430: /* Clear BHRB */
4603 case 598: /* Synchronize */
4604 case 62: /* Wait for Interrupt */
4605 case 22: /* Instruction Cache Block Touch */
4606 case 854: /* Enforce In-order Execution of I/O */
4607 case 246: /* Data Cache Block Touch for Store */
4608 case 54: /* Data Cache Block Store */
4609 case 86: /* Data Cache Block Flush */
4610 case 278: /* Data Cache Block Touch */
4611 case 758: /* Data Cache Block Allocate */
4612 case 982: /* Instruction Cache Block Invalidate */
4615 case 654: /* Transaction Begin */
4616 case 686: /* Transaction End */
4617 case 718: /* Transaction Check */
4618 case 750: /* Transaction Suspend or Resume */
4619 case 782: /* Transaction Abort Word Conditional */
4620 case 814: /* Transaction Abort Doubleword Conditional */
4621 case 846: /* Transaction Abort Word Conditional Immediate */
4622 case 878: /* Transaction Abort Doubleword Conditional Immediate */
4623 case 910: /* Transaction Abort */
4624 fprintf_unfiltered (gdb_stdlog, "Cannot record Transaction instructions. "
4625 "%08x at %s, 31-%d.\n",
4626 insn, paddress (gdbarch, addr), ext);
4629 case 1014: /* Data Cache Block set to Zero */
4630 if (target_auxv_search (¤t_target, AT_DCACHEBSIZE, &at_dcsz) <= 0
4632 at_dcsz = 128; /* Assume 128-byte cache line size (POWER8) */
4635 if (PPC_RA (insn) != 0)
4636 regcache_raw_read_unsigned (regcache,
4637 tdep->ppc_gp0_regnum + PPC_RA (insn), &ra);
4638 regcache_raw_read_unsigned (regcache,
4639 tdep->ppc_gp0_regnum + PPC_RB (insn), &rb);
4640 ea = (ra + rb) & ~((ULONGEST) (at_dcsz - 1));
4641 record_full_arch_list_add_mem (ea, at_dcsz);
4646 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4647 "at %s, 31-%d.\n", insn, paddress (gdbarch, addr), ext);
4651 /* Parse and record instructions of primary opcode-59 at ADDR.
4652 Return 0 if successful. */
4655 ppc_process_record_op59 (struct gdbarch *gdbarch, struct regcache *regcache,
4656 CORE_ADDR addr, uint32_t insn)
4658 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4659 int ext = PPC_EXTOP (insn);
4663 case 18: /* Floating Divide */
4664 case 20: /* Floating Subtract */
4665 case 21: /* Floating Add */
4666 case 22: /* Floating Square Root */
4667 case 24: /* Floating Reciprocal Estimate */
4668 case 25: /* Floating Multiply */
4669 case 26: /* Floating Reciprocal Square Root Estimate */
4670 case 28: /* Floating Multiply-Subtract */
4671 case 29: /* Floating Multiply-Add */
4672 case 30: /* Floating Negative Multiply-Subtract */
4673 case 31: /* Floating Negative Multiply-Add */
4674 record_full_arch_list_add_reg (regcache,
4675 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4677 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4678 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4685 case 2: /* DFP Add */
4686 case 3: /* DFP Quantize */
4687 case 34: /* DFP Multiply */
4688 case 35: /* DFP Reround */
4689 case 67: /* DFP Quantize Immediate */
4690 case 99: /* DFP Round To FP Integer With Inexact */
4691 case 227: /* DFP Round To FP Integer Without Inexact */
4692 case 258: /* DFP Convert To DFP Long! */
4693 case 290: /* DFP Convert To Fixed */
4694 case 514: /* DFP Subtract */
4695 case 546: /* DFP Divide */
4696 case 770: /* DFP Round To DFP Short! */
4697 case 802: /* DFP Convert From Fixed */
4698 case 834: /* DFP Encode BCD To DPD */
4700 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4701 record_full_arch_list_add_reg (regcache,
4702 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4703 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4706 case 130: /* DFP Compare Ordered */
4707 case 162: /* DFP Test Exponent */
4708 case 194: /* DFP Test Data Class */
4709 case 226: /* DFP Test Data Group */
4710 case 642: /* DFP Compare Unordered */
4711 case 674: /* DFP Test Significance */
4712 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4713 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4716 case 66: /* DFP Shift Significand Left Immediate */
4717 case 98: /* DFP Shift Significand Right Immediate */
4718 case 322: /* DFP Decode DPD To BCD */
4719 case 354: /* DFP Extract Biased Exponent */
4720 case 866: /* DFP Insert Biased Exponent */
4721 record_full_arch_list_add_reg (regcache,
4722 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4724 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4727 case 846: /* Floating Convert From Integer Doubleword Single */
4728 case 974: /* Floating Convert From Integer Doubleword Unsigned
4730 record_full_arch_list_add_reg (regcache,
4731 tdep->ppc_fp0_regnum + PPC_FRT (insn));
4733 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4734 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4739 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
4740 "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext);
4744 /* Parse and record instructions of primary opcode-60 at ADDR.
4745 Return 0 if successful. */
4748 ppc_process_record_op60 (struct gdbarch *gdbarch, struct regcache *regcache,
4749 CORE_ADDR addr, uint32_t insn)
4751 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
4752 int ext = PPC_EXTOP (insn);
4756 case 0: /* VSX Scalar Add Single-Precision */
4757 case 32: /* VSX Scalar Add Double-Precision */
4758 case 24: /* VSX Scalar Divide Single-Precision */
4759 case 56: /* VSX Scalar Divide Double-Precision */
4760 case 176: /* VSX Scalar Copy Sign Double-Precision */
4761 case 33: /* VSX Scalar Multiply-Add Double-Precision */
4762 case 41: /* ditto */
4763 case 1: /* VSX Scalar Multiply-Add Single-Precision */
4765 case 160: /* VSX Scalar Maximum Double-Precision */
4766 case 168: /* VSX Scalar Minimum Double-Precision */
4767 case 49: /* VSX Scalar Multiply-Subtract Double-Precision */
4768 case 57: /* ditto */
4769 case 17: /* VSX Scalar Multiply-Subtract Single-Precision */
4770 case 25: /* ditto */
4771 case 48: /* VSX Scalar Multiply Double-Precision */
4772 case 16: /* VSX Scalar Multiply Single-Precision */
4773 case 161: /* VSX Scalar Negative Multiply-Add Double-Precision */
4774 case 169: /* ditto */
4775 case 129: /* VSX Scalar Negative Multiply-Add Single-Precision */
4776 case 137: /* ditto */
4777 case 177: /* VSX Scalar Negative Multiply-Subtract Double-Precision */
4778 case 185: /* ditto */
4779 case 145: /* VSX Scalar Negative Multiply-Subtract Single-Precision */
4780 case 153: /* ditto */
4781 case 40: /* VSX Scalar Subtract Double-Precision */
4782 case 8: /* VSX Scalar Subtract Single-Precision */
4783 case 96: /* VSX Vector Add Double-Precision */
4784 case 64: /* VSX Vector Add Single-Precision */
4785 case 120: /* VSX Vector Divide Double-Precision */
4786 case 88: /* VSX Vector Divide Single-Precision */
4787 case 97: /* VSX Vector Multiply-Add Double-Precision */
4788 case 105: /* ditto */
4789 case 65: /* VSX Vector Multiply-Add Single-Precision */
4790 case 73: /* ditto */
4791 case 224: /* VSX Vector Maximum Double-Precision */
4792 case 192: /* VSX Vector Maximum Single-Precision */
4793 case 232: /* VSX Vector Minimum Double-Precision */
4794 case 200: /* VSX Vector Minimum Single-Precision */
4795 case 113: /* VSX Vector Multiply-Subtract Double-Precision */
4796 case 121: /* ditto */
4797 case 81: /* VSX Vector Multiply-Subtract Single-Precision */
4798 case 89: /* ditto */
4799 case 112: /* VSX Vector Multiply Double-Precision */
4800 case 80: /* VSX Vector Multiply Single-Precision */
4801 case 225: /* VSX Vector Negative Multiply-Add Double-Precision */
4802 case 233: /* ditto */
4803 case 193: /* VSX Vector Negative Multiply-Add Single-Precision */
4804 case 201: /* ditto */
4805 case 241: /* VSX Vector Negative Multiply-Subtract Double-Precision */
4806 case 249: /* ditto */
4807 case 209: /* VSX Vector Negative Multiply-Subtract Single-Precision */
4808 case 217: /* ditto */
4809 case 104: /* VSX Vector Subtract Double-Precision */
4810 case 72: /* VSX Vector Subtract Single-Precision */
4811 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4812 case 240: /* VSX Vector Copy Sign Double-Precision */
4813 case 208: /* VSX Vector Copy Sign Single-Precision */
4814 case 130: /* VSX Logical AND */
4815 case 138: /* VSX Logical AND with Complement */
4816 case 186: /* VSX Logical Equivalence */
4817 case 178: /* VSX Logical NAND */
4818 case 170: /* VSX Logical OR with Complement */
4819 case 162: /* VSX Logical NOR */
4820 case 146: /* VSX Logical OR */
4821 case 154: /* VSX Logical XOR */
4822 case 18: /* VSX Merge High Word */
4823 case 50: /* VSX Merge Low Word */
4824 case 10: /* VSX Permute Doubleword Immediate (DM=0) */
4825 case 10 | 0x20: /* VSX Permute Doubleword Immediate (DM=1) */
4826 case 10 | 0x40: /* VSX Permute Doubleword Immediate (DM=2) */
4827 case 10 | 0x60: /* VSX Permute Doubleword Immediate (DM=3) */
4828 case 2: /* VSX Shift Left Double by Word Immediate (SHW=0) */
4829 case 2 | 0x20: /* VSX Shift Left Double by Word Immediate (SHW=1) */
4830 case 2 | 0x40: /* VSX Shift Left Double by Word Immediate (SHW=2) */
4831 case 2 | 0x60: /* VSX Shift Left Double by Word Immediate (SHW=3) */
4832 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
4835 case 61: /* VSX Scalar Test for software Divide Double-Precision */
4836 case 125: /* VSX Vector Test for software Divide Double-Precision */
4837 case 93: /* VSX Vector Test for software Divide Single-Precision */
4838 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4841 case 35: /* VSX Scalar Compare Unordered Double-Precision */
4842 case 43: /* VSX Scalar Compare Ordered Double-Precision */
4843 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4844 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4848 switch ((ext >> 2) & 0x7f) /* Mask out Rc-bit. */
4850 case 99: /* VSX Vector Compare Equal To Double-Precision */
4851 case 67: /* VSX Vector Compare Equal To Single-Precision */
4852 case 115: /* VSX Vector Compare Greater Than or
4853 Equal To Double-Precision */
4854 case 83: /* VSX Vector Compare Greater Than or
4855 Equal To Single-Precision */
4856 case 107: /* VSX Vector Compare Greater Than Double-Precision */
4857 case 75: /* VSX Vector Compare Greater Than Single-Precision */
4859 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
4860 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4861 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
4867 case 265: /* VSX Scalar round Double-Precision to
4868 Single-Precision and Convert to
4869 Single-Precision format */
4870 case 344: /* VSX Scalar truncate Double-Precision to
4871 Integer and Convert to Signed Integer
4872 Doubleword format with Saturate */
4873 case 88: /* VSX Scalar truncate Double-Precision to
4874 Integer and Convert to Signed Integer Word
4875 Format with Saturate */
4876 case 328: /* VSX Scalar truncate Double-Precision integer
4877 and Convert to Unsigned Integer Doubleword
4878 Format with Saturate */
4879 case 72: /* VSX Scalar truncate Double-Precision to
4880 Integer and Convert to Unsigned Integer Word
4881 Format with Saturate */
4882 case 329: /* VSX Scalar Convert Single-Precision to
4883 Double-Precision format */
4884 case 376: /* VSX Scalar Convert Signed Integer
4885 Doubleword to floating-point format and
4886 Round to Double-Precision format */
4887 case 312: /* VSX Scalar Convert Signed Integer
4888 Doubleword to floating-point format and
4889 round to Single-Precision */
4890 case 360: /* VSX Scalar Convert Unsigned Integer
4891 Doubleword to floating-point format and
4892 Round to Double-Precision format */
4893 case 296: /* VSX Scalar Convert Unsigned Integer
4894 Doubleword to floating-point format and
4895 Round to Single-Precision */
4896 case 73: /* VSX Scalar Round to Double-Precision Integer
4897 Using Round to Nearest Away */
4898 case 107: /* VSX Scalar Round to Double-Precision Integer
4899 Exact using Current rounding mode */
4900 case 121: /* VSX Scalar Round to Double-Precision Integer
4901 Using Round toward -Infinity */
4902 case 105: /* VSX Scalar Round to Double-Precision Integer
4903 Using Round toward +Infinity */
4904 case 89: /* VSX Scalar Round to Double-Precision Integer
4905 Using Round toward Zero */
4906 case 90: /* VSX Scalar Reciprocal Estimate Double-Precision */
4907 case 26: /* VSX Scalar Reciprocal Estimate Single-Precision */
4908 case 281: /* VSX Scalar Round to Single-Precision */
4909 case 74: /* VSX Scalar Reciprocal Square Root Estimate
4911 case 10: /* VSX Scalar Reciprocal Square Root Estimate
4913 case 75: /* VSX Scalar Square Root Double-Precision */
4914 case 11: /* VSX Scalar Square Root Single-Precision */
4915 case 393: /* VSX Vector round Double-Precision to
4916 Single-Precision and Convert to
4917 Single-Precision format */
4918 case 472: /* VSX Vector truncate Double-Precision to
4919 Integer and Convert to Signed Integer
4920 Doubleword format with Saturate */
4921 case 216: /* VSX Vector truncate Double-Precision to
4922 Integer and Convert to Signed Integer Word
4923 Format with Saturate */
4924 case 456: /* VSX Vector truncate Double-Precision to
4925 Integer and Convert to Unsigned Integer
4926 Doubleword format with Saturate */
4927 case 200: /* VSX Vector truncate Double-Precision to
4928 Integer and Convert to Unsigned Integer Word
4929 Format with Saturate */
4930 case 457: /* VSX Vector Convert Single-Precision to
4931 Double-Precision format */
4932 case 408: /* VSX Vector truncate Single-Precision to
4933 Integer and Convert to Signed Integer
4934 Doubleword format with Saturate */
4935 case 152: /* VSX Vector truncate Single-Precision to
4936 Integer and Convert to Signed Integer Word
4937 Format with Saturate */
4938 case 392: /* VSX Vector truncate Single-Precision to
4939 Integer and Convert to Unsigned Integer
4940 Doubleword format with Saturate */
4941 case 136: /* VSX Vector truncate Single-Precision to
4942 Integer and Convert to Unsigned Integer Word
4943 Format with Saturate */
4944 case 504: /* VSX Vector Convert and round Signed Integer
4945 Doubleword to Double-Precision format */
4946 case 440: /* VSX Vector Convert and round Signed Integer
4947 Doubleword to Single-Precision format */
4948 case 248: /* VSX Vector Convert Signed Integer Word to
4949 Double-Precision format */
4950 case 184: /* VSX Vector Convert and round Signed Integer
4951 Word to Single-Precision format */
4952 case 488: /* VSX Vector Convert and round Unsigned
4953 Integer Doubleword to Double-Precision format */
4954 case 424: /* VSX Vector Convert and round Unsigned
4955 Integer Doubleword to Single-Precision format */
4956 case 232: /* VSX Vector Convert and round Unsigned
4957 Integer Word to Double-Precision format */
4958 case 168: /* VSX Vector Convert and round Unsigned
4959 Integer Word to Single-Precision format */
4960 case 201: /* VSX Vector Round to Double-Precision
4961 Integer using round to Nearest Away */
4962 case 235: /* VSX Vector Round to Double-Precision
4963 Integer Exact using Current rounding mode */
4964 case 249: /* VSX Vector Round to Double-Precision
4965 Integer using round toward -Infinity */
4966 case 233: /* VSX Vector Round to Double-Precision
4967 Integer using round toward +Infinity */
4968 case 217: /* VSX Vector Round to Double-Precision
4969 Integer using round toward Zero */
4970 case 218: /* VSX Vector Reciprocal Estimate Double-Precision */
4971 case 154: /* VSX Vector Reciprocal Estimate Single-Precision */
4972 case 137: /* VSX Vector Round to Single-Precision Integer
4973 Using Round to Nearest Away */
4974 case 171: /* VSX Vector Round to Single-Precision Integer
4975 Exact Using Current rounding mode */
4976 case 185: /* VSX Vector Round to Single-Precision Integer
4977 Using Round toward -Infinity */
4978 case 169: /* VSX Vector Round to Single-Precision Integer
4979 Using Round toward +Infinity */
4980 case 153: /* VSX Vector Round to Single-Precision Integer
4981 Using round toward Zero */
4982 case 202: /* VSX Vector Reciprocal Square Root Estimate
4984 case 138: /* VSX Vector Reciprocal Square Root Estimate
4986 case 203: /* VSX Vector Square Root Double-Precision */
4987 case 139: /* VSX Vector Square Root Single-Precision */
4988 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
4989 case 345: /* VSX Scalar Absolute Value Double-Precision */
4990 case 267: /* VSX Scalar Convert Scalar Single-Precision to
4991 Vector Single-Precision format Non-signalling */
4992 case 331: /* VSX Scalar Convert Single-Precision to
4993 Double-Precision format Non-signalling */
4994 case 361: /* VSX Scalar Negative Absolute Value Double-Precision */
4995 case 377: /* VSX Scalar Negate Double-Precision */
4996 case 473: /* VSX Vector Absolute Value Double-Precision */
4997 case 409: /* VSX Vector Absolute Value Single-Precision */
4998 case 489: /* VSX Vector Negative Absolute Value Double-Precision */
4999 case 425: /* VSX Vector Negative Absolute Value Single-Precision */
5000 case 505: /* VSX Vector Negate Double-Precision */
5001 case 441: /* VSX Vector Negate Single-Precision */
5002 case 164: /* VSX Splat Word */
5003 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5006 case 106: /* VSX Scalar Test for software Square Root
5008 case 234: /* VSX Vector Test for software Square Root
5010 case 170: /* VSX Vector Test for software Square Root
5012 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5016 if (((ext >> 3) & 0x3) == 3) /* VSX Select */
5018 ppc_record_vsr (regcache, tdep, PPC_XT (insn));
5022 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
5023 "at %s, 60-%d.\n", insn, paddress (gdbarch, addr), ext);
5027 /* Parse and record instructions of primary opcode-63 at ADDR.
5028 Return 0 if successful. */
5031 ppc_process_record_op63 (struct gdbarch *gdbarch, struct regcache *regcache,
5032 CORE_ADDR addr, uint32_t insn)
5034 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5035 int ext = PPC_EXTOP (insn);
5040 case 18: /* Floating Divide */
5041 case 20: /* Floating Subtract */
5042 case 21: /* Floating Add */
5043 case 22: /* Floating Square Root */
5044 case 24: /* Floating Reciprocal Estimate */
5045 case 25: /* Floating Multiply */
5046 case 26: /* Floating Reciprocal Square Root Estimate */
5047 case 28: /* Floating Multiply-Subtract */
5048 case 29: /* Floating Multiply-Add */
5049 case 30: /* Floating Negative Multiply-Subtract */
5050 case 31: /* Floating Negative Multiply-Add */
5051 record_full_arch_list_add_reg (regcache,
5052 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5054 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5055 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5058 case 23: /* Floating Select */
5059 record_full_arch_list_add_reg (regcache,
5060 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5062 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5067 case 2: /* DFP Add Quad */
5068 case 3: /* DFP Quantize Quad */
5069 case 34: /* DFP Multiply Quad */
5070 case 35: /* DFP Reround Quad */
5071 case 67: /* DFP Quantize Immediate Quad */
5072 case 99: /* DFP Round To FP Integer With Inexact Quad */
5073 case 227: /* DFP Round To FP Integer Without Inexact Quad */
5074 case 258: /* DFP Convert To DFP Extended Quad */
5075 case 514: /* DFP Subtract Quad */
5076 case 546: /* DFP Divide Quad */
5077 case 770: /* DFP Round To DFP Long Quad */
5078 case 802: /* DFP Convert From Fixed Quad */
5079 case 834: /* DFP Encode BCD To DPD Quad */
5081 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5082 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
5083 record_full_arch_list_add_reg (regcache, tmp);
5084 record_full_arch_list_add_reg (regcache, tmp + 1);
5085 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5088 case 130: /* DFP Compare Ordered Quad */
5089 case 162: /* DFP Test Exponent Quad */
5090 case 194: /* DFP Test Data Class Quad */
5091 case 226: /* DFP Test Data Group Quad */
5092 case 642: /* DFP Compare Unordered Quad */
5093 case 674: /* DFP Test Significance Quad */
5094 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5095 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5098 case 66: /* DFP Shift Significand Left Immediate Quad */
5099 case 98: /* DFP Shift Significand Right Immediate Quad */
5100 case 322: /* DFP Decode DPD To BCD Quad */
5101 case 866: /* DFP Insert Biased Exponent Quad */
5102 tmp = tdep->ppc_fp0_regnum + (PPC_FRT (insn) & ~1);
5103 record_full_arch_list_add_reg (regcache, tmp);
5104 record_full_arch_list_add_reg (regcache, tmp + 1);
5106 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5109 case 290: /* DFP Convert To Fixed Quad */
5110 record_full_arch_list_add_reg (regcache,
5111 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5113 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5114 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5117 case 354: /* DFP Extract Biased Exponent Quad */
5118 record_full_arch_list_add_reg (regcache,
5119 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5121 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5124 case 12: /* Floating Round to Single-Precision */
5125 case 14: /* Floating Convert To Integer Word */
5126 case 15: /* Floating Convert To Integer Word
5127 with round toward Zero */
5128 case 142: /* Floating Convert To Integer Word Unsigned */
5129 case 143: /* Floating Convert To Integer Word Unsigned
5130 with round toward Zero */
5131 case 392: /* Floating Round to Integer Nearest */
5132 case 424: /* Floating Round to Integer Toward Zero */
5133 case 456: /* Floating Round to Integer Plus */
5134 case 488: /* Floating Round to Integer Minus */
5135 case 814: /* Floating Convert To Integer Doubleword */
5136 case 815: /* Floating Convert To Integer Doubleword
5137 with round toward Zero */
5138 case 846: /* Floating Convert From Integer Doubleword */
5139 case 942: /* Floating Convert To Integer Doubleword Unsigned */
5140 case 943: /* Floating Convert To Integer Doubleword Unsigned
5141 with round toward Zero */
5142 case 974: /* Floating Convert From Integer Doubleword Unsigned */
5143 record_full_arch_list_add_reg (regcache,
5144 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5146 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5147 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5150 case 583: /* Move From FPSCR */
5151 case 8: /* Floating Copy Sign */
5152 case 40: /* Floating Negate */
5153 case 72: /* Floating Move Register */
5154 case 136: /* Floating Negative Absolute Value */
5155 case 264: /* Floating Absolute Value */
5156 record_full_arch_list_add_reg (regcache,
5157 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5159 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5162 case 838: /* Floating Merge Odd Word */
5163 case 966: /* Floating Merge Even Word */
5164 record_full_arch_list_add_reg (regcache,
5165 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5168 case 38: /* Move To FPSCR Bit 1 */
5169 case 70: /* Move To FPSCR Bit 0 */
5170 case 134: /* Move To FPSCR Field Immediate */
5171 case 711: /* Move To FPSCR Fields */
5173 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5174 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5177 case 0: /* Floating Compare Unordered */
5178 case 32: /* Floating Compare Ordered */
5179 case 64: /* Move to Condition Register from FPSCR */
5180 record_full_arch_list_add_reg (regcache, tdep->ppc_fpscr_regnum);
5182 case 128: /* Floating Test for software Divide */
5183 case 160: /* Floating Test for software Square Root */
5184 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5189 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
5190 "at %s, 59-%d.\n", insn, paddress (gdbarch, addr), ext);
5194 /* Parse the current instruction and record the values of the registers and
5195 memory that will be changed in current instruction to "record_arch_list".
5196 Return -1 if something wrong. */
5199 ppc_process_record (struct gdbarch *gdbarch, struct regcache *regcache,
5202 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
5203 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
5207 insn = read_memory_unsigned_integer (addr, 4, byte_order);
5208 op6 = PPC_OP6 (insn);
5212 case 2: /* Trap Doubleword Immediate */
5213 case 3: /* Trap Word Immediate */
5218 if (ppc_process_record_op4 (gdbarch, regcache, addr, insn) != 0)
5222 case 17: /* System call */
5223 if (PPC_LEV (insn) != 0)
5226 if (tdep->ppc_syscall_record != NULL)
5228 if (tdep->ppc_syscall_record (regcache) != 0)
5233 printf_unfiltered (_("no syscall record support\n"));
5238 case 7: /* Multiply Low Immediate */
5239 record_full_arch_list_add_reg (regcache,
5240 tdep->ppc_gp0_regnum + PPC_RT (insn));
5243 case 8: /* Subtract From Immediate Carrying */
5244 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
5245 record_full_arch_list_add_reg (regcache,
5246 tdep->ppc_gp0_regnum + PPC_RT (insn));
5249 case 10: /* Compare Logical Immediate */
5250 case 11: /* Compare Immediate */
5251 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5254 case 13: /* Add Immediate Carrying and Record */
5255 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5257 case 12: /* Add Immediate Carrying */
5258 record_full_arch_list_add_reg (regcache, tdep->ppc_xer_regnum);
5260 case 14: /* Add Immediate */
5261 case 15: /* Add Immediate Shifted */
5262 record_full_arch_list_add_reg (regcache,
5263 tdep->ppc_gp0_regnum + PPC_RT (insn));
5266 case 16: /* Branch Conditional */
5267 if ((PPC_BO (insn) & 0x4) == 0)
5268 record_full_arch_list_add_reg (regcache, tdep->ppc_ctr_regnum);
5270 case 18: /* Branch */
5272 record_full_arch_list_add_reg (regcache, tdep->ppc_lr_regnum);
5276 if (ppc_process_record_op19 (gdbarch, regcache, addr, insn) != 0)
5280 case 20: /* Rotate Left Word Immediate then Mask Insert */
5281 case 21: /* Rotate Left Word Immediate then AND with Mask */
5282 case 23: /* Rotate Left Word then AND with Mask */
5283 case 30: /* Rotate Left Doubleword Immediate then Clear Left */
5284 /* Rotate Left Doubleword Immediate then Clear Right */
5285 /* Rotate Left Doubleword Immediate then Clear */
5286 /* Rotate Left Doubleword then Clear Left */
5287 /* Rotate Left Doubleword then Clear Right */
5288 /* Rotate Left Doubleword Immediate then Mask Insert */
5290 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5291 record_full_arch_list_add_reg (regcache,
5292 tdep->ppc_gp0_regnum + PPC_RA (insn));
5295 case 28: /* AND Immediate */
5296 case 29: /* AND Immediate Shifted */
5297 record_full_arch_list_add_reg (regcache, tdep->ppc_cr_regnum);
5299 case 24: /* OR Immediate */
5300 case 25: /* OR Immediate Shifted */
5301 case 26: /* XOR Immediate */
5302 case 27: /* XOR Immediate Shifted */
5303 record_full_arch_list_add_reg (regcache,
5304 tdep->ppc_gp0_regnum + PPC_RA (insn));
5308 if (ppc_process_record_op31 (gdbarch, regcache, addr, insn) != 0)
5312 case 33: /* Load Word and Zero with Update */
5313 case 35: /* Load Byte and Zero with Update */
5314 case 41: /* Load Halfword and Zero with Update */
5315 case 43: /* Load Halfword Algebraic with Update */
5316 record_full_arch_list_add_reg (regcache,
5317 tdep->ppc_gp0_regnum + PPC_RA (insn));
5319 case 32: /* Load Word and Zero */
5320 case 34: /* Load Byte and Zero */
5321 case 40: /* Load Halfword and Zero */
5322 case 42: /* Load Halfword Algebraic */
5323 record_full_arch_list_add_reg (regcache,
5324 tdep->ppc_gp0_regnum + PPC_RT (insn));
5327 case 46: /* Load Multiple Word */
5328 for (i = PPC_RT (insn); i < 32; i++)
5329 record_full_arch_list_add_reg (regcache, tdep->ppc_gp0_regnum + i);
5332 case 56: /* Load Quadword */
5333 tmp = tdep->ppc_gp0_regnum + (PPC_RT (insn) & ~1);
5334 record_full_arch_list_add_reg (regcache, tmp);
5335 record_full_arch_list_add_reg (regcache, tmp + 1);
5338 case 49: /* Load Floating-Point Single with Update */
5339 case 51: /* Load Floating-Point Double with Update */
5340 record_full_arch_list_add_reg (regcache,
5341 tdep->ppc_gp0_regnum + PPC_RA (insn));
5343 case 48: /* Load Floating-Point Single */
5344 case 50: /* Load Floating-Point Double */
5345 record_full_arch_list_add_reg (regcache,
5346 tdep->ppc_fp0_regnum + PPC_FRT (insn));
5349 case 47: /* Store Multiple Word */
5353 if (PPC_RA (insn) != 0)
5354 regcache_raw_read_unsigned (regcache,
5355 tdep->ppc_gp0_regnum + PPC_RA (insn),
5358 addr += PPC_D (insn);
5359 record_full_arch_list_add_mem (addr, 4 * (32 - PPC_RS (insn)));
5363 case 37: /* Store Word with Update */
5364 case 39: /* Store Byte with Update */
5365 case 45: /* Store Halfword with Update */
5366 case 53: /* Store Floating-Point Single with Update */
5367 case 55: /* Store Floating-Point Double with Update */
5368 record_full_arch_list_add_reg (regcache,
5369 tdep->ppc_gp0_regnum + PPC_RA (insn));
5371 case 36: /* Store Word */
5372 case 38: /* Store Byte */
5373 case 44: /* Store Halfword */
5374 case 52: /* Store Floating-Point Single */
5375 case 54: /* Store Floating-Point Double */
5380 if (PPC_RA (insn) != 0)
5381 regcache_raw_read_unsigned (regcache,
5382 tdep->ppc_gp0_regnum + PPC_RA (insn),
5384 addr += PPC_D (insn);
5386 if (op6 == 36 || op6 == 37 || op6 == 52 || op6 == 53)
5388 else if (op6 == 54 || op6 == 55)
5390 else if (op6 == 44 || op6 == 45)
5392 else if (op6 == 38 || op6 == 39)
5397 record_full_arch_list_add_mem (addr, size);
5401 case 57: /* Load Floating-Point Double Pair */
5402 if (PPC_FIELD (insn, 30, 2) != 0)
5404 tmp = tdep->ppc_fp0_regnum + (PPC_RT (insn) & ~1);
5405 record_full_arch_list_add_reg (regcache, tmp);
5406 record_full_arch_list_add_reg (regcache, tmp + 1);
5409 case 58: /* Load Doubleword */
5410 /* Load Doubleword with Update */
5411 /* Load Word Algebraic */
5412 if (PPC_FIELD (insn, 30, 2) > 2)
5415 record_full_arch_list_add_reg (regcache,
5416 tdep->ppc_gp0_regnum + PPC_RT (insn));
5417 if (PPC_BIT (insn, 31))
5418 record_full_arch_list_add_reg (regcache,
5419 tdep->ppc_gp0_regnum + PPC_RA (insn));
5423 if (ppc_process_record_op59 (gdbarch, regcache, addr, insn) != 0)
5428 if (ppc_process_record_op60 (gdbarch, regcache, addr, insn) != 0)
5432 case 61: /* Store Floating-Point Double Pair */
5433 case 62: /* Store Doubleword */
5434 /* Store Doubleword with Update */
5435 /* Store Quadword with Update */
5439 int sub2 = PPC_FIELD (insn, 30, 2);
5441 if ((op6 == 61 && sub2 != 0) || (op6 == 62 && sub2 > 2))
5444 if (PPC_RA (insn) != 0)
5445 regcache_raw_read_unsigned (regcache,
5446 tdep->ppc_gp0_regnum + PPC_RA (insn),
5449 size = ((op6 == 61) || sub2 == 2) ? 16 : 8;
5451 addr += PPC_DS (insn) << 2;
5452 record_full_arch_list_add_mem (addr, size);
5454 if (op6 == 62 && sub2 == 1)
5455 record_full_arch_list_add_reg (regcache,
5456 tdep->ppc_gp0_regnum +
5463 if (ppc_process_record_op63 (gdbarch, regcache, addr, insn) != 0)
5469 fprintf_unfiltered (gdb_stdlog, "Warning: Don't know how to record %08x "
5470 "at %s, %d.\n", insn, paddress (gdbarch, addr), op6);
5474 if (record_full_arch_list_add_reg (regcache, PPC_PC_REGNUM))
5476 if (record_full_arch_list_add_end ())
5481 /* Initialize the current architecture based on INFO. If possible, re-use an
5482 architecture from ARCHES, which is a list of architectures already created
5483 during this debugging session.
5485 Called e.g. at program startup, when reading a core file, and when reading
5488 static struct gdbarch *
5489 rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
5491 struct gdbarch *gdbarch;
5492 struct gdbarch_tdep *tdep;
5493 int wordsize, from_xcoff_exec, from_elf_exec;
5494 enum bfd_architecture arch;
5497 enum auto_boolean soft_float_flag = powerpc_soft_float_global;
5499 enum powerpc_vector_abi vector_abi = powerpc_vector_abi_global;
5500 enum powerpc_elf_abi elf_abi = POWERPC_ELF_AUTO;
5501 int have_fpu = 1, have_spe = 0, have_mq = 0, have_altivec = 0, have_dfp = 0,
5503 int tdesc_wordsize = -1;
5504 const struct target_desc *tdesc = info.target_desc;
5505 struct tdesc_arch_data *tdesc_data = NULL;
5506 int num_pseudoregs = 0;
5509 /* INFO may refer to a binary that is not of the PowerPC architecture,
5510 e.g. when debugging a stand-alone SPE executable on a Cell/B.E. system.
5511 In this case, we must not attempt to infer properties of the (PowerPC
5512 side) of the target system from properties of that executable. Trust
5513 the target description instead. */
5515 && bfd_get_arch (info.abfd) != bfd_arch_powerpc
5516 && bfd_get_arch (info.abfd) != bfd_arch_rs6000)
5519 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object &&
5520 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour;
5522 from_elf_exec = info.abfd && info.abfd->format == bfd_object &&
5523 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour;
5525 /* Check word size. If INFO is from a binary file, infer it from
5526 that, else choose a likely default. */
5527 if (from_xcoff_exec)
5529 if (bfd_xcoff_is_xcoff64 (info.abfd))
5534 else if (from_elf_exec)
5536 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64)
5541 else if (tdesc_has_registers (tdesc))
5545 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0)
5546 wordsize = (info.bfd_arch_info->bits_per_word
5547 / info.bfd_arch_info->bits_per_byte);
5552 /* Get the architecture and machine from the BFD. */
5553 arch = info.bfd_arch_info->arch;
5554 mach = info.bfd_arch_info->mach;
5556 /* For e500 executables, the apuinfo section is of help here. Such
5557 section contains the identifier and revision number of each
5558 Application-specific Processing Unit that is present on the
5559 chip. The content of the section is determined by the assembler
5560 which looks at each instruction and determines which unit (and
5561 which version of it) can execute it. Grovel through the section
5562 looking for relevant e500 APUs. */
5564 if (bfd_uses_spe_extensions (info.abfd))
5566 arch = info.bfd_arch_info->arch;
5567 mach = bfd_mach_ppc_e500;
5568 bfd_default_set_arch_mach (&abfd, arch, mach);
5569 info.bfd_arch_info = bfd_get_arch_info (&abfd);
5572 /* Find a default target description which describes our register
5573 layout, if we do not already have one. */
5574 if (! tdesc_has_registers (tdesc))
5576 const struct variant *v;
5578 /* Choose variant. */
5579 v = find_variant_by_arch (arch, mach);
5586 gdb_assert (tdesc_has_registers (tdesc));
5588 /* Check any target description for validity. */
5589 if (tdesc_has_registers (tdesc))
5591 static const char *const gprs[] = {
5592 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5593 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5594 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5595 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5597 const struct tdesc_feature *feature;
5599 static const char *const msr_names[] = { "msr", "ps" };
5600 static const char *const cr_names[] = { "cr", "cnd" };
5601 static const char *const ctr_names[] = { "ctr", "cnt" };
5603 feature = tdesc_find_feature (tdesc,
5604 "org.gnu.gdb.power.core");
5605 if (feature == NULL)
5608 tdesc_data = tdesc_data_alloc ();
5611 for (i = 0; i < ppc_num_gprs; i++)
5612 valid_p &= tdesc_numbered_register (feature, tdesc_data, i, gprs[i]);
5613 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_PC_REGNUM,
5615 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_LR_REGNUM,
5617 valid_p &= tdesc_numbered_register (feature, tdesc_data, PPC_XER_REGNUM,
5620 /* Allow alternate names for these registers, to accomodate GDB's
5622 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
5623 PPC_MSR_REGNUM, msr_names);
5624 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
5625 PPC_CR_REGNUM, cr_names);
5626 valid_p &= tdesc_numbered_register_choices (feature, tdesc_data,
5627 PPC_CTR_REGNUM, ctr_names);
5631 tdesc_data_cleanup (tdesc_data);
5635 have_mq = tdesc_numbered_register (feature, tdesc_data, PPC_MQ_REGNUM,
5638 tdesc_wordsize = tdesc_register_size (feature, "pc") / 8;
5640 wordsize = tdesc_wordsize;
5642 feature = tdesc_find_feature (tdesc,
5643 "org.gnu.gdb.power.fpu");
5644 if (feature != NULL)
5646 static const char *const fprs[] = {
5647 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
5648 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
5649 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
5650 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31"
5653 for (i = 0; i < ppc_num_fprs; i++)
5654 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5655 PPC_F0_REGNUM + i, fprs[i]);
5656 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5657 PPC_FPSCR_REGNUM, "fpscr");
5661 tdesc_data_cleanup (tdesc_data);
5669 /* The DFP pseudo-registers will be available when there are floating
5671 have_dfp = have_fpu;
5673 feature = tdesc_find_feature (tdesc,
5674 "org.gnu.gdb.power.altivec");
5675 if (feature != NULL)
5677 static const char *const vector_regs[] = {
5678 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
5679 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
5680 "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
5681 "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31"
5685 for (i = 0; i < ppc_num_gprs; i++)
5686 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5689 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5690 PPC_VSCR_REGNUM, "vscr");
5691 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5692 PPC_VRSAVE_REGNUM, "vrsave");
5694 if (have_spe || !valid_p)
5696 tdesc_data_cleanup (tdesc_data);
5704 /* Check for POWER7 VSX registers support. */
5705 feature = tdesc_find_feature (tdesc,
5706 "org.gnu.gdb.power.vsx");
5708 if (feature != NULL)
5710 static const char *const vsx_regs[] = {
5711 "vs0h", "vs1h", "vs2h", "vs3h", "vs4h", "vs5h",
5712 "vs6h", "vs7h", "vs8h", "vs9h", "vs10h", "vs11h",
5713 "vs12h", "vs13h", "vs14h", "vs15h", "vs16h", "vs17h",
5714 "vs18h", "vs19h", "vs20h", "vs21h", "vs22h", "vs23h",
5715 "vs24h", "vs25h", "vs26h", "vs27h", "vs28h", "vs29h",
5721 for (i = 0; i < ppc_num_vshrs; i++)
5722 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5723 PPC_VSR0_UPPER_REGNUM + i,
5727 tdesc_data_cleanup (tdesc_data);
5736 /* On machines supporting the SPE APU, the general-purpose registers
5737 are 64 bits long. There are SIMD vector instructions to treat them
5738 as pairs of floats, but the rest of the instruction set treats them
5739 as 32-bit registers, and only operates on their lower halves.
5741 In the GDB regcache, we treat their high and low halves as separate
5742 registers. The low halves we present as the general-purpose
5743 registers, and then we have pseudo-registers that stitch together
5744 the upper and lower halves and present them as pseudo-registers.
5746 Thus, the target description is expected to supply the upper
5747 halves separately. */
5749 feature = tdesc_find_feature (tdesc,
5750 "org.gnu.gdb.power.spe");
5751 if (feature != NULL)
5753 static const char *const upper_spe[] = {
5754 "ev0h", "ev1h", "ev2h", "ev3h",
5755 "ev4h", "ev5h", "ev6h", "ev7h",
5756 "ev8h", "ev9h", "ev10h", "ev11h",
5757 "ev12h", "ev13h", "ev14h", "ev15h",
5758 "ev16h", "ev17h", "ev18h", "ev19h",
5759 "ev20h", "ev21h", "ev22h", "ev23h",
5760 "ev24h", "ev25h", "ev26h", "ev27h",
5761 "ev28h", "ev29h", "ev30h", "ev31h"
5765 for (i = 0; i < ppc_num_gprs; i++)
5766 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5767 PPC_SPE_UPPER_GP0_REGNUM + i,
5769 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5770 PPC_SPE_ACC_REGNUM, "acc");
5771 valid_p &= tdesc_numbered_register (feature, tdesc_data,
5772 PPC_SPE_FSCR_REGNUM, "spefscr");
5774 if (have_mq || have_fpu || !valid_p)
5776 tdesc_data_cleanup (tdesc_data);
5785 /* If we have a 64-bit binary on a 32-bit target, complain. Also
5786 complain for a 32-bit binary on a 64-bit target; we do not yet
5787 support that. For instance, the 32-bit ABI routines expect
5790 As long as there isn't an explicit target description, we'll
5791 choose one based on the BFD architecture and get a word size
5792 matching the binary (probably powerpc:common or
5793 powerpc:common64). So there is only trouble if a 64-bit target
5794 supplies a 64-bit description while debugging a 32-bit
5796 if (tdesc_wordsize != -1 && tdesc_wordsize != wordsize)
5798 tdesc_data_cleanup (tdesc_data);
5805 switch (elf_elfheader (info.abfd)->e_flags & EF_PPC64_ABI)
5808 elf_abi = POWERPC_ELF_V1;
5811 elf_abi = POWERPC_ELF_V2;
5818 if (soft_float_flag == AUTO_BOOLEAN_AUTO && from_elf_exec)
5820 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5821 Tag_GNU_Power_ABI_FP))
5824 soft_float_flag = AUTO_BOOLEAN_FALSE;
5827 soft_float_flag = AUTO_BOOLEAN_TRUE;
5834 if (vector_abi == POWERPC_VEC_AUTO && from_elf_exec)
5836 switch (bfd_elf_get_obj_attr_int (info.abfd, OBJ_ATTR_GNU,
5837 Tag_GNU_Power_ABI_Vector))
5840 vector_abi = POWERPC_VEC_GENERIC;
5843 vector_abi = POWERPC_VEC_ALTIVEC;
5846 vector_abi = POWERPC_VEC_SPE;
5854 /* At this point, the only supported ELF-based 64-bit little-endian
5855 operating system is GNU/Linux, and this uses the ELFv2 ABI by
5856 default. All other supported ELF-based operating systems use the
5857 ELFv1 ABI by default. Therefore, if the ABI marker is missing,
5858 e.g. because we run a legacy binary, or have attached to a process
5859 and have not found any associated binary file, set the default
5860 according to this heuristic. */
5861 if (elf_abi == POWERPC_ELF_AUTO)
5863 if (wordsize == 8 && info.byte_order == BFD_ENDIAN_LITTLE)
5864 elf_abi = POWERPC_ELF_V2;
5866 elf_abi = POWERPC_ELF_V1;
5869 if (soft_float_flag == AUTO_BOOLEAN_TRUE)
5871 else if (soft_float_flag == AUTO_BOOLEAN_FALSE)
5874 soft_float = !have_fpu;
5876 /* If we have a hard float binary or setting but no floating point
5877 registers, downgrade to soft float anyway. We're still somewhat
5878 useful in this scenario. */
5879 if (!soft_float && !have_fpu)
5882 /* Similarly for vector registers. */
5883 if (vector_abi == POWERPC_VEC_ALTIVEC && !have_altivec)
5884 vector_abi = POWERPC_VEC_GENERIC;
5886 if (vector_abi == POWERPC_VEC_SPE && !have_spe)
5887 vector_abi = POWERPC_VEC_GENERIC;
5889 if (vector_abi == POWERPC_VEC_AUTO)
5892 vector_abi = POWERPC_VEC_ALTIVEC;
5894 vector_abi = POWERPC_VEC_SPE;
5896 vector_abi = POWERPC_VEC_GENERIC;
5899 /* Do not limit the vector ABI based on available hardware, since we
5900 do not yet know what hardware we'll decide we have. Yuck! FIXME! */
5902 /* Find a candidate among extant architectures. */
5903 for (arches = gdbarch_list_lookup_by_info (arches, &info);
5905 arches = gdbarch_list_lookup_by_info (arches->next, &info))
5907 /* Word size in the various PowerPC bfd_arch_info structs isn't
5908 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform
5909 separate word size check. */
5910 tdep = gdbarch_tdep (arches->gdbarch);
5911 if (tdep && tdep->elf_abi != elf_abi)
5913 if (tdep && tdep->soft_float != soft_float)
5915 if (tdep && tdep->vector_abi != vector_abi)
5917 if (tdep && tdep->wordsize == wordsize)
5919 if (tdesc_data != NULL)
5920 tdesc_data_cleanup (tdesc_data);
5921 return arches->gdbarch;
5925 /* None found, create a new architecture from INFO, whose bfd_arch_info
5926 validity depends on the source:
5927 - executable useless
5928 - rs6000_host_arch() good
5930 - "set arch" trust blindly
5931 - GDB startup useless but harmless */
5933 tdep = XCNEW (struct gdbarch_tdep);
5934 tdep->wordsize = wordsize;
5935 tdep->elf_abi = elf_abi;
5936 tdep->soft_float = soft_float;
5937 tdep->vector_abi = vector_abi;
5939 gdbarch = gdbarch_alloc (&info, tdep);
5941 tdep->ppc_gp0_regnum = PPC_R0_REGNUM;
5942 tdep->ppc_toc_regnum = PPC_R0_REGNUM + 2;
5943 tdep->ppc_ps_regnum = PPC_MSR_REGNUM;
5944 tdep->ppc_cr_regnum = PPC_CR_REGNUM;
5945 tdep->ppc_lr_regnum = PPC_LR_REGNUM;
5946 tdep->ppc_ctr_regnum = PPC_CTR_REGNUM;
5947 tdep->ppc_xer_regnum = PPC_XER_REGNUM;
5948 tdep->ppc_mq_regnum = have_mq ? PPC_MQ_REGNUM : -1;
5950 tdep->ppc_fp0_regnum = have_fpu ? PPC_F0_REGNUM : -1;
5951 tdep->ppc_fpscr_regnum = have_fpu ? PPC_FPSCR_REGNUM : -1;
5952 tdep->ppc_vsr0_upper_regnum = have_vsx ? PPC_VSR0_UPPER_REGNUM : -1;
5953 tdep->ppc_vr0_regnum = have_altivec ? PPC_VR0_REGNUM : -1;
5954 tdep->ppc_vrsave_regnum = have_altivec ? PPC_VRSAVE_REGNUM : -1;
5955 tdep->ppc_ev0_upper_regnum = have_spe ? PPC_SPE_UPPER_GP0_REGNUM : -1;
5956 tdep->ppc_acc_regnum = have_spe ? PPC_SPE_ACC_REGNUM : -1;
5957 tdep->ppc_spefscr_regnum = have_spe ? PPC_SPE_FSCR_REGNUM : -1;
5959 set_gdbarch_pc_regnum (gdbarch, PPC_PC_REGNUM);
5960 set_gdbarch_sp_regnum (gdbarch, PPC_R0_REGNUM + 1);
5961 set_gdbarch_deprecated_fp_regnum (gdbarch, PPC_R0_REGNUM + 1);
5962 set_gdbarch_fp0_regnum (gdbarch, tdep->ppc_fp0_regnum);
5963 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno);
5965 /* The XML specification for PowerPC sensibly calls the MSR "msr".
5966 GDB traditionally called it "ps", though, so let GDB add an
5968 set_gdbarch_ps_regnum (gdbarch, tdep->ppc_ps_regnum);
5971 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value);
5973 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value);
5975 /* Set lr_frame_offset. */
5977 tdep->lr_frame_offset = 16;
5979 tdep->lr_frame_offset = 4;
5981 if (have_spe || have_dfp || have_vsx)
5983 set_gdbarch_pseudo_register_read (gdbarch, rs6000_pseudo_register_read);
5984 set_gdbarch_pseudo_register_write (gdbarch,
5985 rs6000_pseudo_register_write);
5986 set_gdbarch_ax_pseudo_register_collect (gdbarch,
5987 rs6000_ax_pseudo_register_collect);
5990 set_gdbarch_gen_return_address (gdbarch, rs6000_gen_return_address);
5992 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
5994 /* Select instruction printer. */
5995 if (arch == bfd_arch_rs6000)
5996 set_gdbarch_print_insn (gdbarch, print_insn_rs6000);
5998 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc);
6000 set_gdbarch_num_regs (gdbarch, PPC_NUM_REGS);
6003 num_pseudoregs += 32;
6005 num_pseudoregs += 16;
6007 /* Include both VSX and Extended FP registers. */
6008 num_pseudoregs += 96;
6010 set_gdbarch_num_pseudo_regs (gdbarch, num_pseudoregs);
6012 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
6013 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
6014 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
6015 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT);
6016 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
6017 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
6018 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
6019 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT);
6020 set_gdbarch_char_signed (gdbarch, 0);
6022 set_gdbarch_frame_align (gdbarch, rs6000_frame_align);
6025 set_gdbarch_frame_red_zone_size (gdbarch, 288);
6027 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p);
6028 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value);
6029 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register);
6031 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum);
6032 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum);
6035 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call);
6036 else if (wordsize == 8)
6037 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call);
6039 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue);
6040 set_gdbarch_stack_frame_destroyed_p (gdbarch, rs6000_stack_frame_destroyed_p);
6041 set_gdbarch_skip_main_prologue (gdbarch, rs6000_skip_main_prologue);
6043 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
6044 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc);
6046 /* The value of symbols of type N_SO and N_FUN maybe null when
6048 set_gdbarch_sofun_address_maybe_missing (gdbarch, 1);
6050 /* Handles single stepping of atomic sequences. */
6051 set_gdbarch_software_single_step (gdbarch, ppc_deal_with_atomic_sequence);
6053 /* Not sure on this. FIXMEmgo */
6054 set_gdbarch_frame_args_skip (gdbarch, 8);
6056 /* Helpers for function argument information. */
6057 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument);
6060 set_gdbarch_in_solib_return_trampoline
6061 (gdbarch, rs6000_in_solib_return_trampoline);
6062 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code);
6064 /* Hook in the DWARF CFI frame unwinder. */
6065 dwarf2_append_unwinders (gdbarch);
6066 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum);
6068 /* Frame handling. */
6069 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg);
6071 /* Setup displaced stepping. */
6072 set_gdbarch_displaced_step_copy_insn (gdbarch,
6073 ppc_displaced_step_copy_insn);
6074 set_gdbarch_displaced_step_hw_singlestep (gdbarch,
6075 ppc_displaced_step_hw_singlestep);
6076 set_gdbarch_displaced_step_fixup (gdbarch, ppc_displaced_step_fixup);
6077 set_gdbarch_displaced_step_free_closure (gdbarch,
6078 simple_displaced_step_free_closure);
6079 set_gdbarch_displaced_step_location (gdbarch,
6080 displaced_step_at_entry_point);
6082 set_gdbarch_max_insn_length (gdbarch, PPC_INSN_SIZE);
6084 /* Hook in ABI-specific overrides, if they have been registered. */
6085 info.target_desc = tdesc;
6086 info.tdep_info = tdesc_data;
6087 gdbarch_init_osabi (info, gdbarch);
6091 case GDB_OSABI_LINUX:
6092 case GDB_OSABI_NETBSD_AOUT:
6093 case GDB_OSABI_NETBSD_ELF:
6094 case GDB_OSABI_UNKNOWN:
6095 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
6096 frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind);
6097 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
6098 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
6099 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
6102 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
6104 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc);
6105 frame_unwind_append_unwinder (gdbarch, &rs6000_epilogue_frame_unwind);
6106 frame_unwind_append_unwinder (gdbarch, &rs6000_frame_unwind);
6107 set_gdbarch_dummy_id (gdbarch, rs6000_dummy_id);
6108 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer);
6111 set_tdesc_pseudo_register_type (gdbarch, rs6000_pseudo_register_type);
6112 set_tdesc_pseudo_register_reggroup_p (gdbarch,
6113 rs6000_pseudo_register_reggroup_p);
6114 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
6116 /* Override the normal target description method to make the SPE upper
6117 halves anonymous. */
6118 set_gdbarch_register_name (gdbarch, rs6000_register_name);
6120 /* Choose register numbers for all supported pseudo-registers. */
6121 tdep->ppc_ev0_regnum = -1;
6122 tdep->ppc_dl0_regnum = -1;
6123 tdep->ppc_vsr0_regnum = -1;
6124 tdep->ppc_efpr0_regnum = -1;
6126 cur_reg = gdbarch_num_regs (gdbarch);
6130 tdep->ppc_ev0_regnum = cur_reg;
6135 tdep->ppc_dl0_regnum = cur_reg;
6140 tdep->ppc_vsr0_regnum = cur_reg;
6142 tdep->ppc_efpr0_regnum = cur_reg;
6146 gdb_assert (gdbarch_num_regs (gdbarch)
6147 + gdbarch_num_pseudo_regs (gdbarch) == cur_reg);
6149 /* Register the ravenscar_arch_ops. */
6150 if (mach == bfd_mach_ppc_e500)
6151 register_e500_ravenscar_ops (gdbarch);
6153 register_ppc_ravenscar_ops (gdbarch);
6159 rs6000_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
6161 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
6166 /* FIXME: Dump gdbarch_tdep. */
6169 /* PowerPC-specific commands. */
6172 set_powerpc_command (char *args, int from_tty)
6174 printf_unfiltered (_("\
6175 \"set powerpc\" must be followed by an appropriate subcommand.\n"));
6176 help_list (setpowerpccmdlist, "set powerpc ", all_commands, gdb_stdout);
6180 show_powerpc_command (char *args, int from_tty)
6182 cmd_show_list (showpowerpccmdlist, from_tty, "");
6186 powerpc_set_soft_float (char *args, int from_tty,
6187 struct cmd_list_element *c)
6189 struct gdbarch_info info;
6191 /* Update the architecture. */
6192 gdbarch_info_init (&info);
6193 if (!gdbarch_update_p (info))
6194 internal_error (__FILE__, __LINE__, _("could not update architecture"));
6198 powerpc_set_vector_abi (char *args, int from_tty,
6199 struct cmd_list_element *c)
6201 struct gdbarch_info info;
6204 for (vector_abi = POWERPC_VEC_AUTO;
6205 vector_abi != POWERPC_VEC_LAST;
6207 if (strcmp (powerpc_vector_abi_string,
6208 powerpc_vector_strings[vector_abi]) == 0)
6210 powerpc_vector_abi_global = (enum powerpc_vector_abi) vector_abi;
6214 if (vector_abi == POWERPC_VEC_LAST)
6215 internal_error (__FILE__, __LINE__, _("Invalid vector ABI accepted: %s."),
6216 powerpc_vector_abi_string);
6218 /* Update the architecture. */
6219 gdbarch_info_init (&info);
6220 if (!gdbarch_update_p (info))
6221 internal_error (__FILE__, __LINE__, _("could not update architecture"));
6224 /* Show the current setting of the exact watchpoints flag. */
6227 show_powerpc_exact_watchpoints (struct ui_file *file, int from_tty,
6228 struct cmd_list_element *c,
6231 fprintf_filtered (file, _("Use of exact watchpoints is %s.\n"), value);
6234 /* Read a PPC instruction from memory. */
6237 read_insn (struct frame_info *frame, CORE_ADDR pc)
6239 struct gdbarch *gdbarch = get_frame_arch (frame);
6240 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
6242 return read_memory_unsigned_integer (pc, 4, byte_order);
6245 /* Return non-zero if the instructions at PC match the series
6246 described in PATTERN, or zero otherwise. PATTERN is an array of
6247 'struct ppc_insn_pattern' objects, terminated by an entry whose
6250 When the match is successful, fill INSN[i] with what PATTERN[i]
6251 matched. If PATTERN[i] is optional, and the instruction wasn't
6252 present, set INSN[i] to 0 (which is not a valid PPC instruction).
6253 INSN should have as many elements as PATTERN. Note that, if
6254 PATTERN contains optional instructions which aren't present in
6255 memory, then INSN will have holes, so INSN[i] isn't necessarily the
6256 i'th instruction in memory. */
6259 ppc_insns_match_pattern (struct frame_info *frame, CORE_ADDR pc,
6260 struct ppc_insn_pattern *pattern,
6261 unsigned int *insns)
6266 for (i = 0, insn = 0; pattern[i].mask; i++)
6269 insn = read_insn (frame, pc);
6271 if ((insn & pattern[i].mask) == pattern[i].data)
6277 else if (!pattern[i].optional)
6284 /* Return the 'd' field of the d-form instruction INSN, properly
6288 ppc_insn_d_field (unsigned int insn)
6290 return ((((CORE_ADDR) insn & 0xffff) ^ 0x8000) - 0x8000);
6293 /* Return the 'ds' field of the ds-form instruction INSN, with the two
6294 zero bits concatenated at the right, and properly
6298 ppc_insn_ds_field (unsigned int insn)
6300 return ((((CORE_ADDR) insn & 0xfffc) ^ 0x8000) - 0x8000);
6303 /* Initialization code. */
6305 /* -Wmissing-prototypes */
6306 extern initialize_file_ftype _initialize_rs6000_tdep;
6309 _initialize_rs6000_tdep (void)
6311 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep);
6312 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep);
6314 /* Initialize the standard target descriptions. */
6315 initialize_tdesc_powerpc_32 ();
6316 initialize_tdesc_powerpc_altivec32 ();
6317 initialize_tdesc_powerpc_vsx32 ();
6318 initialize_tdesc_powerpc_403 ();
6319 initialize_tdesc_powerpc_403gc ();
6320 initialize_tdesc_powerpc_405 ();
6321 initialize_tdesc_powerpc_505 ();
6322 initialize_tdesc_powerpc_601 ();
6323 initialize_tdesc_powerpc_602 ();
6324 initialize_tdesc_powerpc_603 ();
6325 initialize_tdesc_powerpc_604 ();
6326 initialize_tdesc_powerpc_64 ();
6327 initialize_tdesc_powerpc_altivec64 ();
6328 initialize_tdesc_powerpc_vsx64 ();
6329 initialize_tdesc_powerpc_7400 ();
6330 initialize_tdesc_powerpc_750 ();
6331 initialize_tdesc_powerpc_860 ();
6332 initialize_tdesc_powerpc_e500 ();
6333 initialize_tdesc_rs6000 ();
6335 /* Add root prefix command for all "set powerpc"/"show powerpc"
6337 add_prefix_cmd ("powerpc", no_class, set_powerpc_command,
6338 _("Various PowerPC-specific commands."),
6339 &setpowerpccmdlist, "set powerpc ", 0, &setlist);
6341 add_prefix_cmd ("powerpc", no_class, show_powerpc_command,
6342 _("Various PowerPC-specific commands."),
6343 &showpowerpccmdlist, "show powerpc ", 0, &showlist);
6345 /* Add a command to allow the user to force the ABI. */
6346 add_setshow_auto_boolean_cmd ("soft-float", class_support,
6347 &powerpc_soft_float_global,
6348 _("Set whether to use a soft-float ABI."),
6349 _("Show whether to use a soft-float ABI."),
6351 powerpc_set_soft_float, NULL,
6352 &setpowerpccmdlist, &showpowerpccmdlist);
6354 add_setshow_enum_cmd ("vector-abi", class_support, powerpc_vector_strings,
6355 &powerpc_vector_abi_string,
6356 _("Set the vector ABI."),
6357 _("Show the vector ABI."),
6358 NULL, powerpc_set_vector_abi, NULL,
6359 &setpowerpccmdlist, &showpowerpccmdlist);
6361 add_setshow_boolean_cmd ("exact-watchpoints", class_support,
6362 &target_exact_watchpoints,
6364 Set whether to use just one debug register for watchpoints on scalars."),
6366 Show whether to use just one debug register for watchpoints on scalars."),
6368 If true, GDB will use only one debug register when watching a variable of\n\
6369 scalar type, thus assuming that the variable is accessed through the address\n\
6370 of its first byte."),
6371 NULL, show_powerpc_exact_watchpoints,
6372 &setpowerpccmdlist, &showpowerpccmdlist);