1 /* Target-dependent code for the Renesas RL78 for GDB, the GNU debugger.
3 Copyright (C) 2011-2015 Free Software Foundation, Inc.
5 Contributed by Red Hat, Inc.
7 This file is part of GDB.
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
24 #include "prologue-value.h"
27 #include "opcode/rl78.h"
31 #include "frame-unwind.h"
32 #include "frame-base.h"
35 #include "dwarf2-frame.h"
36 #include "reggroups.h"
50 RL78_REGS_PER_BANK = 8
53 /* Register Numbers. */
57 /* All general purpose registers are 8 bits wide. */
58 RL78_RAW_BANK0_R0_REGNUM = 0,
59 RL78_RAW_BANK0_R1_REGNUM,
60 RL78_RAW_BANK0_R2_REGNUM,
61 RL78_RAW_BANK0_R3_REGNUM,
62 RL78_RAW_BANK0_R4_REGNUM,
63 RL78_RAW_BANK0_R5_REGNUM,
64 RL78_RAW_BANK0_R6_REGNUM,
65 RL78_RAW_BANK0_R7_REGNUM,
67 RL78_RAW_BANK1_R0_REGNUM,
68 RL78_RAW_BANK1_R1_REGNUM,
69 RL78_RAW_BANK1_R2_REGNUM,
70 RL78_RAW_BANK1_R3_REGNUM,
71 RL78_RAW_BANK1_R4_REGNUM,
72 RL78_RAW_BANK1_R5_REGNUM,
73 RL78_RAW_BANK1_R6_REGNUM,
74 RL78_RAW_BANK1_R7_REGNUM,
76 RL78_RAW_BANK2_R0_REGNUM,
77 RL78_RAW_BANK2_R1_REGNUM,
78 RL78_RAW_BANK2_R2_REGNUM,
79 RL78_RAW_BANK2_R3_REGNUM,
80 RL78_RAW_BANK2_R4_REGNUM,
81 RL78_RAW_BANK2_R5_REGNUM,
82 RL78_RAW_BANK2_R6_REGNUM,
83 RL78_RAW_BANK2_R7_REGNUM,
85 RL78_RAW_BANK3_R0_REGNUM,
86 RL78_RAW_BANK3_R1_REGNUM,
87 RL78_RAW_BANK3_R2_REGNUM,
88 RL78_RAW_BANK3_R3_REGNUM,
89 RL78_RAW_BANK3_R4_REGNUM,
90 RL78_RAW_BANK3_R5_REGNUM,
91 RL78_RAW_BANK3_R6_REGNUM,
92 RL78_RAW_BANK3_R7_REGNUM,
94 RL78_PSW_REGNUM, /* 8 bits */
95 RL78_ES_REGNUM, /* 8 bits */
96 RL78_CS_REGNUM, /* 8 bits */
97 RL78_RAW_PC_REGNUM, /* 20 bits; we'll use 32 bits for it. */
99 /* Fixed address SFRs (some of those above are SFRs too.) */
100 RL78_SPL_REGNUM, /* 8 bits; lower half of SP */
101 RL78_SPH_REGNUM, /* 8 bits; upper half of SP */
102 RL78_PMC_REGNUM, /* 8 bits */
103 RL78_MEM_REGNUM, /* 8 bits ?? */
107 /* Pseudo registers. */
108 RL78_PC_REGNUM = RL78_NUM_REGS,
125 RL78_BANK0_R0_REGNUM,
126 RL78_BANK0_R1_REGNUM,
127 RL78_BANK0_R2_REGNUM,
128 RL78_BANK0_R3_REGNUM,
129 RL78_BANK0_R4_REGNUM,
130 RL78_BANK0_R5_REGNUM,
131 RL78_BANK0_R6_REGNUM,
132 RL78_BANK0_R7_REGNUM,
134 RL78_BANK1_R0_REGNUM,
135 RL78_BANK1_R1_REGNUM,
136 RL78_BANK1_R2_REGNUM,
137 RL78_BANK1_R3_REGNUM,
138 RL78_BANK1_R4_REGNUM,
139 RL78_BANK1_R5_REGNUM,
140 RL78_BANK1_R6_REGNUM,
141 RL78_BANK1_R7_REGNUM,
143 RL78_BANK2_R0_REGNUM,
144 RL78_BANK2_R1_REGNUM,
145 RL78_BANK2_R2_REGNUM,
146 RL78_BANK2_R3_REGNUM,
147 RL78_BANK2_R4_REGNUM,
148 RL78_BANK2_R5_REGNUM,
149 RL78_BANK2_R6_REGNUM,
150 RL78_BANK2_R7_REGNUM,
152 RL78_BANK3_R0_REGNUM,
153 RL78_BANK3_R1_REGNUM,
154 RL78_BANK3_R2_REGNUM,
155 RL78_BANK3_R3_REGNUM,
156 RL78_BANK3_R4_REGNUM,
157 RL78_BANK3_R5_REGNUM,
158 RL78_BANK3_R6_REGNUM,
159 RL78_BANK3_R7_REGNUM,
161 RL78_BANK0_RP0_REGNUM,
162 RL78_BANK0_RP1_REGNUM,
163 RL78_BANK0_RP2_REGNUM,
164 RL78_BANK0_RP3_REGNUM,
166 RL78_BANK1_RP0_REGNUM,
167 RL78_BANK1_RP1_REGNUM,
168 RL78_BANK1_RP2_REGNUM,
169 RL78_BANK1_RP3_REGNUM,
171 RL78_BANK2_RP0_REGNUM,
172 RL78_BANK2_RP1_REGNUM,
173 RL78_BANK2_RP2_REGNUM,
174 RL78_BANK2_RP3_REGNUM,
176 RL78_BANK3_RP0_REGNUM,
177 RL78_BANK3_RP1_REGNUM,
178 RL78_BANK3_RP2_REGNUM,
179 RL78_BANK3_RP3_REGNUM,
181 /* These are the same as the above 16 registers, but have
182 a pointer type for use as base registers in expression
183 evaluation. These are not user visible registers. */
184 RL78_BANK0_RP0_PTR_REGNUM,
185 RL78_BANK0_RP1_PTR_REGNUM,
186 RL78_BANK0_RP2_PTR_REGNUM,
187 RL78_BANK0_RP3_PTR_REGNUM,
189 RL78_BANK1_RP0_PTR_REGNUM,
190 RL78_BANK1_RP1_PTR_REGNUM,
191 RL78_BANK1_RP2_PTR_REGNUM,
192 RL78_BANK1_RP3_PTR_REGNUM,
194 RL78_BANK2_RP0_PTR_REGNUM,
195 RL78_BANK2_RP1_PTR_REGNUM,
196 RL78_BANK2_RP2_PTR_REGNUM,
197 RL78_BANK2_RP3_PTR_REGNUM,
199 RL78_BANK3_RP0_PTR_REGNUM,
200 RL78_BANK3_RP1_PTR_REGNUM,
201 RL78_BANK3_RP2_PTR_REGNUM,
202 RL78_BANK3_RP3_PTR_REGNUM,
205 RL78_NUM_PSEUDO_REGS = RL78_NUM_TOTAL_REGS - RL78_NUM_REGS
208 #define RL78_SP_ADDR 0xffff8
210 /* Architecture specific data. */
214 /* The ELF header flags specify the multilib used. */
217 struct type *rl78_void,
229 /* This structure holds the results of a prologue analysis. */
233 /* The offset from the frame base to the stack pointer --- always
236 Calling this a "size" is a bit misleading, but given that the
237 stack grows downwards, using offsets for everything keeps one
238 from going completely sign-crazy: you never change anything's
239 sign for an ADD instruction; always change the second operand's
240 sign for a SUB instruction; and everything takes care of
244 /* Non-zero if this function has initialized the frame pointer from
245 the stack pointer, zero otherwise. */
248 /* If has_frame_ptr is non-zero, this is the offset from the frame
249 base to where the frame pointer points. This is always zero or
251 int frame_ptr_offset;
253 /* The address of the first instruction at which the frame has been
254 set up and the arguments are where the debug info says they are
255 --- as best as we can tell. */
256 CORE_ADDR prologue_end;
258 /* reg_offset[R] is the offset from the CFA at which register R is
259 saved, or 1 if register R has not been saved. (Real values are
260 always zero or negative.) */
261 int reg_offset[RL78_NUM_TOTAL_REGS];
264 /* Implement the "register_type" gdbarch method. */
267 rl78_register_type (struct gdbarch *gdbarch, int reg_nr)
269 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
271 if (reg_nr == RL78_PC_REGNUM)
272 return tdep->rl78_code_pointer;
273 else if (reg_nr == RL78_RAW_PC_REGNUM)
274 return tdep->rl78_uint32;
275 else if (reg_nr == RL78_PSW_REGNUM)
276 return (tdep->rl78_psw_type);
277 else if (reg_nr <= RL78_MEM_REGNUM
278 || (RL78_X_REGNUM <= reg_nr && reg_nr <= RL78_H_REGNUM)
279 || (RL78_BANK0_R0_REGNUM <= reg_nr
280 && reg_nr <= RL78_BANK3_R7_REGNUM))
281 return tdep->rl78_int8;
282 else if (reg_nr == RL78_SP_REGNUM
283 || (RL78_BANK0_RP0_PTR_REGNUM <= reg_nr
284 && reg_nr <= RL78_BANK3_RP3_PTR_REGNUM))
285 return tdep->rl78_data_pointer;
287 return tdep->rl78_int16;
290 /* Implement the "register_name" gdbarch method. */
293 rl78_register_name (struct gdbarch *gdbarch, int regnr)
295 static const char *const reg_names[] =
416 /* The 16 register slots would be named
417 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
418 want these to be user visible registers. */
419 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
422 return reg_names[regnr];
425 /* Implement the "register_name" gdbarch method for the g10 variant. */
428 rl78_g10_register_name (struct gdbarch *gdbarch, int regnr)
430 static const char *const reg_names[] =
551 /* The 16 register slots would be named
552 bank0_rp0_ptr_regnum ... bank3_rp3_ptr_regnum, but we don't
553 want these to be user visible registers. */
554 "", "", "", "", "", "", "", "", "", "", "", "", "", "", "", ""
557 return reg_names[regnr];
560 /* Implement the "register_reggroup_p" gdbarch method. */
563 rl78_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
564 struct reggroup *group)
566 if (group == all_reggroup)
569 /* All other registers are saved and restored. */
570 if (group == save_reggroup || group == restore_reggroup)
572 if ((regnum < RL78_NUM_REGS
573 && regnum != RL78_SPL_REGNUM
574 && regnum != RL78_SPH_REGNUM
575 && regnum != RL78_RAW_PC_REGNUM)
576 || regnum == RL78_SP_REGNUM
577 || regnum == RL78_PC_REGNUM)
583 if ((RL78_BANK0_R0_REGNUM <= regnum && regnum <= RL78_BANK3_R7_REGNUM)
584 || regnum == RL78_ES_REGNUM
585 || regnum == RL78_CS_REGNUM
586 || regnum == RL78_SPL_REGNUM
587 || regnum == RL78_SPH_REGNUM
588 || regnum == RL78_PMC_REGNUM
589 || regnum == RL78_MEM_REGNUM
590 || regnum == RL78_RAW_PC_REGNUM
591 || (RL78_BANK0_RP0_REGNUM <= regnum && regnum <= RL78_BANK3_RP3_REGNUM))
592 return group == system_reggroup;
594 return group == general_reggroup;
597 /* Strip bits to form an instruction address. (When fetching a
598 32-bit address from the stack, the high eight bits are garbage.
599 This function strips off those unused bits.) */
602 rl78_make_instruction_address (CORE_ADDR addr)
604 return addr & 0xffffff;
607 /* Set / clear bits necessary to make a data address. */
610 rl78_make_data_address (CORE_ADDR addr)
612 return (addr & 0xffff) | 0xf0000;
615 /* Implement the "pseudo_register_read" gdbarch method. */
617 static enum register_status
618 rl78_pseudo_register_read (struct gdbarch *gdbarch,
619 struct regcache *regcache,
620 int reg, gdb_byte *buffer)
622 enum register_status status;
624 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
626 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
627 + (reg - RL78_BANK0_R0_REGNUM);
629 status = regcache_raw_read (regcache, raw_regnum, buffer);
631 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
633 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
634 + RL78_RAW_BANK0_R0_REGNUM;
636 status = regcache_raw_read (regcache, raw_regnum, buffer);
637 if (status == REG_VALID)
638 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
640 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
642 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
643 + RL78_RAW_BANK0_R0_REGNUM;
645 status = regcache_raw_read (regcache, raw_regnum, buffer);
646 if (status == REG_VALID)
647 status = regcache_raw_read (regcache, raw_regnum + 1, buffer + 1);
649 else if (reg == RL78_SP_REGNUM)
651 status = regcache_raw_read (regcache, RL78_SPL_REGNUM, buffer);
652 if (status == REG_VALID)
653 status = regcache_raw_read (regcache, RL78_SPH_REGNUM, buffer + 1);
655 else if (reg == RL78_PC_REGNUM)
659 status = regcache_raw_read (regcache, RL78_RAW_PC_REGNUM, rawbuf);
660 memcpy (buffer, rawbuf, 3);
662 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
666 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
667 if (status == REG_VALID)
669 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
670 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
671 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
672 + (reg - RL78_X_REGNUM);
673 status = regcache_raw_read (regcache, raw_regnum, buffer);
676 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
680 status = regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
681 if (status == REG_VALID)
683 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
684 int bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
685 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
686 + 2 * (reg - RL78_AX_REGNUM);
687 status = regcache_raw_read (regcache, raw_regnum, buffer);
688 if (status == REG_VALID)
689 status = regcache_raw_read (regcache, raw_regnum + 1,
694 gdb_assert_not_reached ("invalid pseudo register number");
698 /* Implement the "pseudo_register_write" gdbarch method. */
701 rl78_pseudo_register_write (struct gdbarch *gdbarch,
702 struct regcache *regcache,
703 int reg, const gdb_byte *buffer)
705 if (RL78_BANK0_R0_REGNUM <= reg && reg <= RL78_BANK3_R7_REGNUM)
707 int raw_regnum = RL78_RAW_BANK0_R0_REGNUM
708 + (reg - RL78_BANK0_R0_REGNUM);
710 regcache_raw_write (regcache, raw_regnum, buffer);
712 else if (RL78_BANK0_RP0_REGNUM <= reg && reg <= RL78_BANK3_RP3_REGNUM)
714 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_REGNUM)
715 + RL78_RAW_BANK0_R0_REGNUM;
717 regcache_raw_write (regcache, raw_regnum, buffer);
718 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
720 else if (RL78_BANK0_RP0_PTR_REGNUM <= reg && reg <= RL78_BANK3_RP3_PTR_REGNUM)
722 int raw_regnum = 2 * (reg - RL78_BANK0_RP0_PTR_REGNUM)
723 + RL78_RAW_BANK0_R0_REGNUM;
725 regcache_raw_write (regcache, raw_regnum, buffer);
726 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
728 else if (reg == RL78_SP_REGNUM)
730 regcache_raw_write (regcache, RL78_SPL_REGNUM, buffer);
731 regcache_raw_write (regcache, RL78_SPH_REGNUM, buffer + 1);
733 else if (reg == RL78_PC_REGNUM)
737 memcpy (rawbuf, buffer, 3);
739 regcache_raw_write (regcache, RL78_RAW_PC_REGNUM, rawbuf);
741 else if (RL78_X_REGNUM <= reg && reg <= RL78_H_REGNUM)
747 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
748 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
749 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
750 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
751 + (reg - RL78_X_REGNUM);
752 regcache_raw_write (regcache, raw_regnum, buffer);
754 else if (RL78_AX_REGNUM <= reg && reg <= RL78_HL_REGNUM)
757 int bank, raw_regnum;
759 regcache_raw_read_unsigned (regcache, RL78_PSW_REGNUM, &psw);
760 bank = ((psw >> 3) & 1) | ((psw >> 4) & 1);
761 /* RSB0 is at bit 3; RSBS1 is at bit 5. */
762 raw_regnum = RL78_RAW_BANK0_R0_REGNUM + bank * RL78_REGS_PER_BANK
763 + 2 * (reg - RL78_AX_REGNUM);
764 regcache_raw_write (regcache, raw_regnum, buffer);
765 regcache_raw_write (regcache, raw_regnum + 1, buffer + 1);
768 gdb_assert_not_reached ("invalid pseudo register number");
771 /* Implement the "breakpoint_from_pc" gdbarch method. */
773 static const gdb_byte *
774 rl78_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
777 /* The documented BRK instruction is actually a two byte sequence,
778 {0x61, 0xcc}, but instructions may be as short as one byte.
779 Correspondence with Renesas revealed that the one byte sequence
780 0xff is used when a one byte breakpoint instruction is required. */
781 static gdb_byte breakpoint[] = { 0xff };
783 *lenptr = sizeof breakpoint;
787 /* Define a "handle" struct for fetching the next opcode. */
789 struct rl78_get_opcode_byte_handle
795 opc_reg_to_gdb_regnum (int opcreg)
800 return RL78_X_REGNUM;
802 return RL78_A_REGNUM;
804 return RL78_C_REGNUM;
806 return RL78_B_REGNUM;
808 return RL78_E_REGNUM;
810 return RL78_D_REGNUM;
812 return RL78_L_REGNUM;
814 return RL78_H_REGNUM;
816 return RL78_AX_REGNUM;
818 return RL78_BC_REGNUM;
820 return RL78_DE_REGNUM;
822 return RL78_HL_REGNUM;
824 return RL78_SP_REGNUM;
826 return RL78_PSW_REGNUM;
828 return RL78_CS_REGNUM;
830 return RL78_ES_REGNUM;
832 return RL78_PMC_REGNUM;
834 return RL78_MEM_REGNUM;
836 internal_error (__FILE__, __LINE__,
837 _("Undefined mapping for opc reg %d"),
845 /* Fetch a byte on behalf of the opcode decoder. HANDLE contains
846 the memory address of the next byte to fetch. If successful,
847 the address in the handle is updated and the byte fetched is
848 returned as the value of the function. If not successful, -1
852 rl78_get_opcode_byte (void *handle)
854 struct rl78_get_opcode_byte_handle *opcdata
855 = (struct rl78_get_opcode_byte_handle *) handle;
859 status = target_read_memory (opcdata->pc, &byte, 1);
869 /* Function for finding saved registers in a 'struct pv_area'; this
870 function is passed to pv_area_scan.
872 If VALUE is a saved register, ADDR says it was saved at a constant
873 offset from the frame base, and SIZE indicates that the whole
874 register was saved, record its offset. */
877 check_for_saved (void *result_untyped, pv_t addr, CORE_ADDR size,
880 struct rl78_prologue *result = (struct rl78_prologue *) result_untyped;
882 if (value.kind == pvk_register
884 && pv_is_register (addr, RL78_SP_REGNUM)
885 && size == register_size (target_gdbarch (), value.reg))
886 result->reg_offset[value.reg] = addr.k;
889 /* Analyze a prologue starting at START_PC, going no further than
890 LIMIT_PC. Fill in RESULT as appropriate. */
893 rl78_analyze_prologue (CORE_ADDR start_pc,
894 CORE_ADDR limit_pc, struct rl78_prologue *result)
896 CORE_ADDR pc, next_pc;
898 pv_t reg[RL78_NUM_TOTAL_REGS];
899 struct pv_area *stack;
900 struct cleanup *back_to;
901 CORE_ADDR after_last_frame_setup_insn = start_pc;
904 memset (result, 0, sizeof (*result));
906 for (rn = 0; rn < RL78_NUM_TOTAL_REGS; rn++)
908 reg[rn] = pv_register (rn, 0);
909 result->reg_offset[rn] = 1;
912 stack = make_pv_area (RL78_SP_REGNUM, gdbarch_addr_bit (target_gdbarch ()));
913 back_to = make_cleanup_free_pv_area (stack);
915 /* The call instruction has saved the return address on the stack. */
916 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -4);
917 pv_area_store (stack, reg[RL78_SP_REGNUM], 4, reg[RL78_PC_REGNUM]);
920 while (pc < limit_pc)
923 struct rl78_get_opcode_byte_handle opcode_handle;
924 RL78_Opcode_Decoded opc;
926 opcode_handle.pc = pc;
927 bytes_read = rl78_decode_opcode (pc, &opc, rl78_get_opcode_byte,
928 &opcode_handle, RL78_ISA_DEFAULT);
929 next_pc = pc + bytes_read;
931 if (opc.id == RLO_sel)
933 bank = opc.op[1].addend;
935 else if (opc.id == RLO_mov
936 && opc.op[0].type == RL78_Operand_PreDec
937 && opc.op[0].reg == RL78_Reg_SP
938 && opc.op[1].type == RL78_Operand_Register)
940 int rsrc = (bank * RL78_REGS_PER_BANK)
941 + 2 * (opc.op[1].reg - RL78_Reg_AX);
943 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
944 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc]);
945 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM], -1);
946 pv_area_store (stack, reg[RL78_SP_REGNUM], 1, reg[rsrc + 1]);
947 after_last_frame_setup_insn = next_pc;
949 else if (opc.id == RLO_sub
950 && opc.op[0].type == RL78_Operand_Register
951 && opc.op[0].reg == RL78_Reg_SP
952 && opc.op[1].type == RL78_Operand_Immediate)
954 int addend = opc.op[1].addend;
956 reg[RL78_SP_REGNUM] = pv_add_constant (reg[RL78_SP_REGNUM],
958 after_last_frame_setup_insn = next_pc;
960 else if (opc.id == RLO_mov
961 && opc.size == RL78_Word
962 && opc.op[0].type == RL78_Operand_Register
963 && opc.op[1].type == RL78_Operand_Indirect
964 && opc.op[1].addend == RL78_SP_ADDR)
966 reg[opc_reg_to_gdb_regnum (opc.op[0].reg)]
967 = reg[RL78_SP_REGNUM];
969 else if (opc.id == RLO_sub
970 && opc.size == RL78_Word
971 && opc.op[0].type == RL78_Operand_Register
972 && opc.op[1].type == RL78_Operand_Immediate)
974 int addend = opc.op[1].addend;
975 int regnum = opc_reg_to_gdb_regnum (opc.op[0].reg);
977 reg[regnum] = pv_add_constant (reg[regnum], -addend);
979 else if (opc.id == RLO_mov
980 && opc.size == RL78_Word
981 && opc.op[0].type == RL78_Operand_Indirect
982 && opc.op[0].addend == RL78_SP_ADDR
983 && opc.op[1].type == RL78_Operand_Register)
986 = reg[opc_reg_to_gdb_regnum (opc.op[1].reg)];
987 after_last_frame_setup_insn = next_pc;
991 /* Terminate the prologue scan. */
998 /* Is the frame size (offset, really) a known constant? */
999 if (pv_is_register (reg[RL78_SP_REGNUM], RL78_SP_REGNUM))
1000 result->frame_size = reg[RL78_SP_REGNUM].k;
1002 /* Record where all the registers were saved. */
1003 pv_area_scan (stack, check_for_saved, (void *) result);
1005 result->prologue_end = after_last_frame_setup_insn;
1007 do_cleanups (back_to);
1010 /* Implement the "addr_bits_remove" gdbarch method. */
1013 rl78_addr_bits_remove (struct gdbarch *gdbarch, CORE_ADDR addr)
1015 return addr & 0xffffff;
1018 /* Implement the "address_to_pointer" gdbarch method. */
1021 rl78_address_to_pointer (struct gdbarch *gdbarch,
1022 struct type *type, gdb_byte *buf, CORE_ADDR addr)
1024 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1026 store_unsigned_integer (buf, TYPE_LENGTH (type), byte_order,
1030 /* Implement the "pointer_to_address" gdbarch method. */
1033 rl78_pointer_to_address (struct gdbarch *gdbarch,
1034 struct type *type, const gdb_byte *buf)
1036 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1038 = extract_unsigned_integer (buf, TYPE_LENGTH (type), byte_order);
1040 /* Is it a code address? */
1041 if (TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_FUNC
1042 || TYPE_CODE (TYPE_TARGET_TYPE (type)) == TYPE_CODE_METHOD
1043 || TYPE_CODE_SPACE (TYPE_TARGET_TYPE (type))
1044 || TYPE_LENGTH (type) == 4)
1045 return rl78_make_instruction_address (addr);
1047 return rl78_make_data_address (addr);
1050 /* Implement the "skip_prologue" gdbarch method. */
1053 rl78_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1056 CORE_ADDR func_addr, func_end;
1057 struct rl78_prologue p;
1059 /* Try to find the extent of the function that contains PC. */
1060 if (!find_pc_partial_function (pc, &name, &func_addr, &func_end))
1063 rl78_analyze_prologue (pc, func_end, &p);
1064 return p.prologue_end;
1067 /* Implement the "unwind_pc" gdbarch method. */
1070 rl78_unwind_pc (struct gdbarch *arch, struct frame_info *next_frame)
1072 return rl78_addr_bits_remove
1073 (arch, frame_unwind_register_unsigned (next_frame,
1077 /* Implement the "unwind_sp" gdbarch method. */
1080 rl78_unwind_sp (struct gdbarch *arch, struct frame_info *next_frame)
1082 return frame_unwind_register_unsigned (next_frame, RL78_SP_REGNUM);
1085 /* Given a frame described by THIS_FRAME, decode the prologue of its
1086 associated function if there is not cache entry as specified by
1087 THIS_PROLOGUE_CACHE. Save the decoded prologue in the cache and
1088 return that struct as the value of this function. */
1090 static struct rl78_prologue *
1091 rl78_analyze_frame_prologue (struct frame_info *this_frame,
1092 void **this_prologue_cache)
1094 if (!*this_prologue_cache)
1096 CORE_ADDR func_start, stop_addr;
1098 *this_prologue_cache = FRAME_OBSTACK_ZALLOC (struct rl78_prologue);
1100 func_start = get_frame_func (this_frame);
1101 stop_addr = get_frame_pc (this_frame);
1103 /* If we couldn't find any function containing the PC, then
1104 just initialize the prologue cache, but don't do anything. */
1106 stop_addr = func_start;
1108 rl78_analyze_prologue (func_start, stop_addr,
1109 (struct rl78_prologue *) *this_prologue_cache);
1112 return (struct rl78_prologue *) *this_prologue_cache;
1115 /* Given a frame and a prologue cache, return this frame's base. */
1118 rl78_frame_base (struct frame_info *this_frame, void **this_prologue_cache)
1120 struct rl78_prologue *p
1121 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1122 CORE_ADDR sp = get_frame_register_unsigned (this_frame, RL78_SP_REGNUM);
1124 return rl78_make_data_address (sp - p->frame_size);
1127 /* Implement the "frame_this_id" method for unwinding frames. */
1130 rl78_this_id (struct frame_info *this_frame,
1131 void **this_prologue_cache, struct frame_id *this_id)
1133 *this_id = frame_id_build (rl78_frame_base (this_frame,
1134 this_prologue_cache),
1135 get_frame_func (this_frame));
1138 /* Implement the "frame_prev_register" method for unwinding frames. */
1140 static struct value *
1141 rl78_prev_register (struct frame_info *this_frame,
1142 void **this_prologue_cache, int regnum)
1144 struct rl78_prologue *p
1145 = rl78_analyze_frame_prologue (this_frame, this_prologue_cache);
1146 CORE_ADDR frame_base = rl78_frame_base (this_frame, this_prologue_cache);
1148 if (regnum == RL78_SP_REGNUM)
1149 return frame_unwind_got_constant (this_frame, regnum, frame_base);
1151 else if (regnum == RL78_SPL_REGNUM)
1152 return frame_unwind_got_constant (this_frame, regnum,
1153 (frame_base & 0xff));
1155 else if (regnum == RL78_SPH_REGNUM)
1156 return frame_unwind_got_constant (this_frame, regnum,
1157 ((frame_base >> 8) & 0xff));
1159 /* If prologue analysis says we saved this register somewhere,
1160 return a description of the stack slot holding it. */
1161 else if (p->reg_offset[regnum] != 1)
1164 frame_unwind_got_memory (this_frame, regnum,
1165 frame_base + p->reg_offset[regnum]);
1167 if (regnum == RL78_PC_REGNUM)
1169 ULONGEST pc = rl78_make_instruction_address (value_as_long (rv));
1171 return frame_unwind_got_constant (this_frame, regnum, pc);
1176 /* Otherwise, presume we haven't changed the value of this
1177 register, and get it from the next frame. */
1179 return frame_unwind_got_register (this_frame, regnum, regnum);
1182 static const struct frame_unwind rl78_unwind =
1185 default_frame_unwind_stop_reason,
1189 default_frame_sniffer
1192 /* Implement the "dwarf_reg_to_regnum" gdbarch method. */
1195 rl78_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
1197 if (0 <= reg && reg <= 31)
1200 /* Map even registers to their 16-bit counterparts which have a
1201 pointer type. This is usually what is required from the DWARF
1203 return (reg >> 1) + RL78_BANK0_RP0_PTR_REGNUM;
1208 return RL78_SP_REGNUM;
1212 return RL78_PSW_REGNUM;
1214 return RL78_ES_REGNUM;
1216 return RL78_CS_REGNUM;
1218 return RL78_PC_REGNUM;
1220 internal_error (__FILE__, __LINE__,
1221 _("Undefined dwarf2 register mapping of reg %d"),
1225 /* Implement the `register_sim_regno' gdbarch method. */
1228 rl78_register_sim_regno (struct gdbarch *gdbarch, int regnum)
1230 gdb_assert (regnum < RL78_NUM_REGS);
1232 /* So long as regnum is in [0, RL78_NUM_REGS), it's valid. We
1233 just want to override the default here which disallows register
1234 numbers which have no names. */
1238 /* Implement the "return_value" gdbarch method. */
1240 static enum return_value_convention
1241 rl78_return_value (struct gdbarch *gdbarch,
1242 struct value *function,
1243 struct type *valtype,
1244 struct regcache *regcache,
1245 gdb_byte *readbuf, const gdb_byte *writebuf)
1247 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1248 ULONGEST valtype_len = TYPE_LENGTH (valtype);
1249 int is_g10 = gdbarch_tdep (gdbarch)->elf_flags & E_FLAG_RL78_G10;
1251 if (valtype_len > 8)
1252 return RETURN_VALUE_STRUCT_CONVENTION;
1257 int argreg = RL78_RAW_BANK1_R0_REGNUM;
1258 CORE_ADDR g10_raddr = 0xffec8;
1261 while (valtype_len > 0)
1264 u = read_memory_integer (g10_raddr, 1,
1265 gdbarch_byte_order (gdbarch));
1267 regcache_cooked_read_unsigned (regcache, argreg, &u);
1268 store_unsigned_integer (readbuf + offset, 1, byte_order, u);
1279 int argreg = RL78_RAW_BANK1_R0_REGNUM;
1280 CORE_ADDR g10_raddr = 0xffec8;
1283 while (valtype_len > 0)
1285 u = extract_unsigned_integer (writebuf + offset, 1, byte_order);
1287 gdb_byte b = u & 0xff;
1288 write_memory (g10_raddr, &b, 1);
1291 regcache_cooked_write_unsigned (regcache, argreg, u);
1299 return RETURN_VALUE_REGISTER_CONVENTION;
1303 /* Implement the "frame_align" gdbarch method. */
1306 rl78_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
1308 return rl78_make_data_address (align_down (sp, 2));
1312 /* Implement the "dummy_id" gdbarch method. */
1314 static struct frame_id
1315 rl78_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1318 frame_id_build (rl78_make_data_address
1319 (get_frame_register_unsigned
1320 (this_frame, RL78_SP_REGNUM)),
1321 get_frame_pc (this_frame));
1325 /* Implement the "push_dummy_call" gdbarch method. */
1328 rl78_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
1329 struct regcache *regcache, CORE_ADDR bp_addr,
1330 int nargs, struct value **args, CORE_ADDR sp,
1331 int struct_return, CORE_ADDR struct_addr)
1333 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1337 /* Push arguments in reverse order. */
1338 for (i = nargs - 1; i >= 0; i--)
1340 struct type *value_type = value_enclosing_type (args[i]);
1341 int len = TYPE_LENGTH (value_type);
1342 int container_len = (len + 1) & ~1;
1344 sp -= container_len;
1345 write_memory (rl78_make_data_address (sp),
1346 value_contents_all (args[i]), len);
1349 /* Store struct value address. */
1352 store_unsigned_integer (buf, 2, byte_order, struct_addr);
1354 write_memory (rl78_make_data_address (sp), buf, 2);
1357 /* Store return address. */
1359 store_unsigned_integer (buf, 4, byte_order, bp_addr);
1360 write_memory (rl78_make_data_address (sp), buf, 4);
1362 /* Finally, update the stack pointer... */
1363 regcache_cooked_write_unsigned (regcache, RL78_SP_REGNUM, sp);
1365 /* DWARF2/GCC uses the stack address *before* the function call as a
1367 return rl78_make_data_address (sp + 4);
1370 /* Allocate and initialize a gdbarch object. */
1372 static struct gdbarch *
1373 rl78_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1375 struct gdbarch *gdbarch;
1376 struct gdbarch_tdep *tdep;
1379 /* Extract the elf_flags if available. */
1380 if (info.abfd != NULL
1381 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1382 elf_flags = elf_elfheader (info.abfd)->e_flags;
1387 /* Try to find the architecture in the list of already defined
1389 for (arches = gdbarch_list_lookup_by_info (arches, &info);
1391 arches = gdbarch_list_lookup_by_info (arches->next, &info))
1393 if (gdbarch_tdep (arches->gdbarch)->elf_flags != elf_flags)
1396 return arches->gdbarch;
1399 /* None found, create a new architecture from the information
1401 tdep = XNEW (struct gdbarch_tdep);
1402 gdbarch = gdbarch_alloc (&info, tdep);
1403 tdep->elf_flags = elf_flags;
1405 /* Initialize types. */
1406 tdep->rl78_void = arch_type (gdbarch, TYPE_CODE_VOID, 1, "void");
1407 tdep->rl78_uint8 = arch_integer_type (gdbarch, 8, 1, "uint8_t");
1408 tdep->rl78_int8 = arch_integer_type (gdbarch, 8, 0, "int8_t");
1409 tdep->rl78_uint16 = arch_integer_type (gdbarch, 16, 1, "uint16_t");
1410 tdep->rl78_int16 = arch_integer_type (gdbarch, 16, 0, "int16_t");
1411 tdep->rl78_uint32 = arch_integer_type (gdbarch, 32, 1, "uint32_t");
1412 tdep->rl78_int32 = arch_integer_type (gdbarch, 32, 0, "int32_t");
1414 tdep->rl78_data_pointer
1415 = arch_type (gdbarch, TYPE_CODE_PTR, 16 / TARGET_CHAR_BIT,
1416 xstrdup ("rl78_data_addr_t"));
1417 TYPE_TARGET_TYPE (tdep->rl78_data_pointer) = tdep->rl78_void;
1418 TYPE_UNSIGNED (tdep->rl78_data_pointer) = 1;
1420 tdep->rl78_code_pointer
1421 = arch_type (gdbarch, TYPE_CODE_PTR, 32 / TARGET_CHAR_BIT,
1422 xstrdup ("rl78_code_addr_t"));
1423 TYPE_TARGET_TYPE (tdep->rl78_code_pointer) = tdep->rl78_void;
1424 TYPE_UNSIGNED (tdep->rl78_code_pointer) = 1;
1426 tdep->rl78_psw_type = arch_flags_type (gdbarch, "builtin_type_rl78_psw", 1);
1427 append_flags_type_flag (tdep->rl78_psw_type, 0, "CY");
1428 append_flags_type_flag (tdep->rl78_psw_type, 1, "ISP0");
1429 append_flags_type_flag (tdep->rl78_psw_type, 2, "ISP1");
1430 append_flags_type_flag (tdep->rl78_psw_type, 3, "RBS0");
1431 append_flags_type_flag (tdep->rl78_psw_type, 4, "AC");
1432 append_flags_type_flag (tdep->rl78_psw_type, 5, "RBS1");
1433 append_flags_type_flag (tdep->rl78_psw_type, 6, "Z");
1434 append_flags_type_flag (tdep->rl78_psw_type, 7, "IE");
1437 set_gdbarch_num_regs (gdbarch, RL78_NUM_REGS);
1438 set_gdbarch_num_pseudo_regs (gdbarch, RL78_NUM_PSEUDO_REGS);
1439 if (tdep->elf_flags & E_FLAG_RL78_G10)
1440 set_gdbarch_register_name (gdbarch, rl78_g10_register_name);
1442 set_gdbarch_register_name (gdbarch, rl78_register_name);
1443 set_gdbarch_register_type (gdbarch, rl78_register_type);
1444 set_gdbarch_pc_regnum (gdbarch, RL78_PC_REGNUM);
1445 set_gdbarch_sp_regnum (gdbarch, RL78_SP_REGNUM);
1446 set_gdbarch_pseudo_register_read (gdbarch, rl78_pseudo_register_read);
1447 set_gdbarch_pseudo_register_write (gdbarch, rl78_pseudo_register_write);
1448 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rl78_dwarf_reg_to_regnum);
1449 set_gdbarch_register_reggroup_p (gdbarch, rl78_register_reggroup_p);
1450 set_gdbarch_register_sim_regno (gdbarch, rl78_register_sim_regno);
1453 set_gdbarch_char_signed (gdbarch, 0);
1454 set_gdbarch_short_bit (gdbarch, 16);
1455 set_gdbarch_int_bit (gdbarch, 16);
1456 set_gdbarch_long_bit (gdbarch, 32);
1457 set_gdbarch_long_long_bit (gdbarch, 64);
1458 set_gdbarch_ptr_bit (gdbarch, 16);
1459 set_gdbarch_addr_bit (gdbarch, 32);
1460 set_gdbarch_dwarf2_addr_size (gdbarch, 4);
1461 set_gdbarch_float_bit (gdbarch, 32);
1462 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
1463 set_gdbarch_double_bit (gdbarch, 32);
1464 set_gdbarch_long_double_bit (gdbarch, 64);
1465 set_gdbarch_double_format (gdbarch, floatformats_ieee_single);
1466 set_gdbarch_long_double_format (gdbarch, floatformats_ieee_double);
1467 set_gdbarch_pointer_to_address (gdbarch, rl78_pointer_to_address);
1468 set_gdbarch_address_to_pointer (gdbarch, rl78_address_to_pointer);
1469 set_gdbarch_addr_bits_remove (gdbarch, rl78_addr_bits_remove);
1472 set_gdbarch_breakpoint_from_pc (gdbarch, rl78_breakpoint_from_pc);
1473 set_gdbarch_decr_pc_after_break (gdbarch, 1);
1476 set_gdbarch_print_insn (gdbarch, print_insn_rl78);
1478 /* Frames, prologues, etc. */
1479 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1480 set_gdbarch_skip_prologue (gdbarch, rl78_skip_prologue);
1481 set_gdbarch_unwind_pc (gdbarch, rl78_unwind_pc);
1482 set_gdbarch_unwind_sp (gdbarch, rl78_unwind_sp);
1483 set_gdbarch_frame_align (gdbarch, rl78_frame_align);
1485 dwarf2_append_unwinders (gdbarch);
1486 frame_unwind_append_unwinder (gdbarch, &rl78_unwind);
1488 /* Dummy frames, return values. */
1489 set_gdbarch_dummy_id (gdbarch, rl78_dummy_id);
1490 set_gdbarch_push_dummy_call (gdbarch, rl78_push_dummy_call);
1491 set_gdbarch_return_value (gdbarch, rl78_return_value);
1493 /* Virtual tables. */
1494 set_gdbarch_vbit_in_delta (gdbarch, 1);
1499 /* -Wmissing-prototypes */
1500 extern initialize_file_ftype _initialize_rl78_tdep;
1502 /* Register the above initialization routine. */
1505 _initialize_rl78_tdep (void)
1507 register_gdbarch_init (bfd_arch_rl78, rl78_gdbarch_init);