1 /* Target-dependent header for the RISC-V architecture, for GDB, the
4 Copyright (C) 2018 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 /* RiscV register numbers. */
27 RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
28 RISCV_RA_REGNUM = 1, /* Return Address. */
29 RISCV_SP_REGNUM = 2, /* Stack Pointer. */
30 RISCV_GP_REGNUM = 3, /* Global Pointer. */
31 RISCV_TP_REGNUM = 4, /* Thread Pointer. */
32 RISCV_FP_REGNUM = 8, /* Frame Pointer. */
33 RISCV_A0_REGNUM = 10, /* First argument. */
34 RISCV_A1_REGNUM = 11, /* Second argument. */
35 RISCV_PC_REGNUM = 32, /* Program Counter. */
37 RISCV_NUM_INTEGER_REGS = 32,
39 RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
40 RISCV_FA0_REGNUM = 43,
41 RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
42 RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
44 RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
45 #define DECLARE_CSR(name, num) \
46 RISCV_ ## num ## _REGNUM = RISCV_FIRST_CSR_REGNUM + num,
47 #include "opcode/riscv-opc.h"
49 RISCV_LAST_CSR_REGNUM = 4160,
50 RISCV_CSR_LEGACY_MISA_REGNUM = 0xf10 + RISCV_FIRST_CSR_REGNUM,
52 RISCV_PRIV_REGNUM = 4161,
54 RISCV_LAST_REGNUM = RISCV_PRIV_REGNUM
57 /* RISC-V specific per-architecture information. */
62 /* Provide access to the whole ABI in one value. */
67 /* Encode the base machine length following the same rules as in the
69 unsigned base_len : 2;
71 /* Encode which floating point ABI is in use following the same rules
72 as the ELF e_flags field. */
73 unsigned float_abi : 2;
77 /* Only the least significant 26 bits are (possibly) valid, and indicate
78 features that are supported on the target. These could be cached from
79 the target, or read from the executable when available. */
80 unsigned core_features;
82 /* ISA-specific data types. */
83 struct type *riscv_fpreg_d_type;
84 struct type *riscv_fpreg_q_type;
87 /* Return the width in bytes of the general purpose registers for GDBARCH. */
88 extern int riscv_isa_xlen (struct gdbarch *gdbarch);
90 /* Single step based on where the current instruction will take us. */
91 extern std::vector<CORE_ADDR> riscv_software_single_step
92 (struct regcache *regcache);
94 #endif /* RISCV_TDEP_H */