1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
60 /* The stack must be 16-byte aligned. */
61 #define SP_ALIGNMENT 16
63 /* The biggest alignment that the target supports. */
64 #define BIGGEST_ALIGNMENT 16
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Cached information about a frame. */
78 struct riscv_unwind_cache
80 /* The register from which we can calculate the frame base. This is
81 usually $sp or $fp. */
84 /* The offset from the current value in register FRAME_BASE_REG to the
85 actual frame base address. */
86 int frame_base_offset;
88 /* Information about previous register values. */
89 struct trad_frame_saved_reg *regs;
91 /* The id for this frame. */
92 struct frame_id this_id;
94 /* The base (stack) address for this frame. This is the stack pointer
95 value on entry to this frame before any adjustments are made. */
99 /* RISC-V specific register group for CSRs. */
101 static reggroup *csr_reggroup = NULL;
103 /* A set of registers that we expect to find in a tdesc_feature. These
104 are use in RISCV_GDBARCH_INIT when processing the target description. */
106 struct riscv_register_feature
108 /* Information for a single register. */
111 /* The GDB register number for this register. */
114 /* List of names for this register. The first name in this list is the
115 preferred name, the name GDB should use when describing this
117 std::vector <const char *> names;
119 /* When true this register is required in this feature set. */
123 /* The name for this feature. This is the name used to find this feature
124 within the target description. */
127 /* List of all the registers that we expect that we might find in this
129 std::vector <struct register_info> registers;
132 /* The general x-registers feature set. */
134 static const struct riscv_register_feature riscv_xreg_feature =
136 "org.gnu.gdb.riscv.cpu",
138 { RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, true },
139 { RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, true },
140 { RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, true },
141 { RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, true },
142 { RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, true },
143 { RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, true },
144 { RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, true },
145 { RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, true },
146 { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, true },
147 { RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, true },
148 { RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, true },
149 { RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, true },
150 { RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, true },
151 { RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, true },
152 { RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, true },
153 { RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, true },
154 { RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, true },
155 { RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, true },
156 { RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, true },
157 { RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, true },
158 { RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, true },
159 { RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, true },
160 { RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, true },
161 { RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, true },
162 { RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, true },
163 { RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, true },
164 { RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, true },
165 { RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, true },
166 { RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, true },
167 { RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, true },
168 { RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, true },
169 { RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, true },
170 { RISCV_ZERO_REGNUM + 32, { "pc" }, true }
174 /* The f-registers feature set. */
176 static const struct riscv_register_feature riscv_freg_feature =
178 "org.gnu.gdb.riscv.fpu",
180 { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, true },
181 { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, true },
182 { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" }, true },
183 { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" }, true },
184 { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" }, true },
185 { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true },
186 { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true },
187 { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true },
188 { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8", "s0" }, true },
189 { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true },
190 { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true },
191 { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true },
192 { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" }, true },
193 { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" }, true },
194 { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" }, true },
195 { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" }, true },
196 { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" }, true },
197 { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" }, true },
198 { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" }, true },
199 { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" }, true },
200 { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" }, true },
201 { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" }, true },
202 { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" }, true },
203 { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" }, true },
204 { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" }, true },
205 { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" }, true },
206 { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" }, true },
207 { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" }, true },
208 { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" }, true },
209 { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" }, true },
210 { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" }, true },
211 { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" }, true },
213 { RISCV_CSR_FFLAGS_REGNUM, { "fflags" }, true },
214 { RISCV_CSR_FRM_REGNUM, { "frm" }, true },
215 { RISCV_CSR_FCSR_REGNUM, { "fcsr" }, true },
220 /* Set of virtual registers. These are not physical registers on the
221 hardware, but might be available from the target. These are not pseudo
222 registers, reading these really does result in a register read from the
223 target, it is just that there might not be a physical register backing
226 static const struct riscv_register_feature riscv_virtual_feature =
228 "org.gnu.gdb.riscv.virtual",
230 { RISCV_PRIV_REGNUM, { "priv" }, false }
234 /* Feature set for CSRs. This set is NOT constant as the register names
235 list for each register is not complete. The aliases are computed
236 during RISCV_CREATE_CSR_ALIASES. */
238 static struct riscv_register_feature riscv_csr_feature =
240 "org.gnu.gdb.riscv.csr",
242 #define DECLARE_CSR(NAME,VALUE) \
243 { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
244 #include "opcode/riscv-opc.h"
249 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
250 to the name list for each register. */
253 riscv_create_csr_aliases ()
255 for (auto ® : riscv_csr_feature.registers)
257 int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
258 const char *alias = xstrprintf ("csr%d", csr_num);
259 reg.names.push_back (alias);
263 /* Controls whether we place compressed breakpoints or not. When in auto
264 mode GDB tries to determine if the target supports compressed
265 breakpoints, and uses them if it does. */
267 static enum auto_boolean use_compressed_breakpoints;
269 /* The show callback for 'show riscv use-compressed-breakpoints'. */
272 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
273 struct cmd_list_element *c,
276 fprintf_filtered (file,
277 _("Debugger's use of compressed breakpoints is set "
281 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
283 static struct cmd_list_element *setriscvcmdlist = NULL;
284 static struct cmd_list_element *showriscvcmdlist = NULL;
286 /* The show callback for the 'show riscv' prefix command. */
289 show_riscv_command (const char *args, int from_tty)
291 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
294 /* The set callback for the 'set riscv' prefix command. */
297 set_riscv_command (const char *args, int from_tty)
300 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
301 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
304 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
306 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
307 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
309 /* The show callback for the 'show debug riscv' prefix command. */
312 show_debug_riscv_command (const char *args, int from_tty)
314 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
317 /* The set callback for the 'set debug riscv' prefix command. */
320 set_debug_riscv_command (const char *args, int from_tty)
323 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
324 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
327 /* The show callback for all 'show debug riscv VARNAME' variables. */
330 show_riscv_debug_variable (struct ui_file *file, int from_tty,
331 struct cmd_list_element *c,
334 fprintf_filtered (file,
335 _("RiscV debug variable `%s' is set to: %s\n"),
339 /* When this is set to non-zero debugging information about breakpoint
340 kinds will be printed. */
342 static unsigned int riscv_debug_breakpoints = 0;
344 /* When this is set to non-zero debugging information about inferior calls
347 static unsigned int riscv_debug_infcall = 0;
349 /* When this is set to non-zero debugging information about stack unwinding
352 static unsigned int riscv_debug_unwinder = 0;
354 /* When this is set to non-zero debugging information about gdbarch
355 initialisation will be printed. */
357 static unsigned int riscv_debug_gdbarch = 0;
359 /* See riscv-tdep.h. */
362 riscv_isa_xlen (struct gdbarch *gdbarch)
364 return gdbarch_tdep (gdbarch)->features.xlen;
367 /* See riscv-tdep.h. */
370 riscv_isa_flen (struct gdbarch *gdbarch)
372 return gdbarch_tdep (gdbarch)->features.flen;
375 /* Return true if the target for GDBARCH has floating point hardware. */
378 riscv_has_fp_regs (struct gdbarch *gdbarch)
380 return (riscv_isa_flen (gdbarch) > 0);
383 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
386 riscv_has_fp_abi (struct gdbarch *gdbarch)
388 return gdbarch_tdep (gdbarch)->features.hw_float_abi;
391 /* Return true if REGNO is a floating pointer register. */
394 riscv_is_fp_regno_p (int regno)
396 return (regno >= RISCV_FIRST_FP_REGNUM
397 && regno <= RISCV_LAST_FP_REGNUM);
400 /* Implement the breakpoint_kind_from_pc gdbarch method. */
403 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
405 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
407 bool unaligned_p = false;
410 /* Some targets don't support unaligned reads. The address can only
411 be unaligned if the C extension is supported. So it is safe to
412 use a compressed breakpoint in this case. */
417 /* Read the opcode byte to determine the instruction length. */
418 read_code (*pcptr, buf, 1);
421 if (riscv_debug_breakpoints)
423 const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
424 ? "C.EBREAK" : "EBREAK");
426 fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ",
427 bp, paddress (gdbarch, *pcptr));
429 fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n");
431 fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n",
432 riscv_insn_length (buf[0]));
434 if (unaligned_p || riscv_insn_length (buf[0]) == 2)
439 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
445 /* Implement the sw_breakpoint_from_kind gdbarch method. */
447 static const gdb_byte *
448 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
450 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
451 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
461 gdb_assert_not_reached (_("unhandled breakpoint kind"));
465 /* Callback function for user_reg_add. */
467 static struct value *
468 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
470 const int *reg_p = (const int *) baton;
471 return value_of_register (*reg_p, frame);
474 /* Implement the register_name gdbarch method. This is used instead of
475 the function supplied by calling TDESC_USE_REGISTERS so that we can
476 ensure the preferred names are offered. */
479 riscv_register_name (struct gdbarch *gdbarch, int regnum)
481 /* Lookup the name through the target description. If we get back NULL
482 then this is an unknown register. If we do get a name back then we
483 look up the registers preferred name below. */
484 const char *name = tdesc_register_name (gdbarch, regnum);
485 if (name == NULL || name[0] == '\0')
488 if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM)
490 gdb_assert (regnum < riscv_xreg_feature.registers.size ());
491 return riscv_xreg_feature.registers[regnum].names[0];
494 if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
496 if (riscv_has_fp_regs (gdbarch))
498 regnum -= RISCV_FIRST_FP_REGNUM;
499 gdb_assert (regnum < riscv_freg_feature.registers.size ());
500 return riscv_freg_feature.registers[regnum].names[0];
506 /* Check that there's no gap between the set of registers handled above,
507 and the set of registers handled next. */
508 gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM);
510 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
512 #define DECLARE_CSR(NAME,VALUE) \
513 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
517 #include "opcode/riscv-opc.h"
522 if (regnum == RISCV_PRIV_REGNUM)
525 /* It is possible that that the target provides some registers that GDB
526 is unaware of, in that case just return the NAME from the target
531 /* Construct a type for 64-bit FP registers. */
534 riscv_fpreg_d_type (struct gdbarch *gdbarch)
536 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
538 if (tdep->riscv_fpreg_d_type == nullptr)
540 const struct builtin_type *bt = builtin_type (gdbarch);
542 /* The type we're building is this: */
544 union __gdb_builtin_type_fpreg_d
553 t = arch_composite_type (gdbarch,
554 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
555 append_composite_type_field (t, "float", bt->builtin_float);
556 append_composite_type_field (t, "double", bt->builtin_double);
558 TYPE_NAME (t) = "builtin_type_fpreg_d";
559 tdep->riscv_fpreg_d_type = t;
562 return tdep->riscv_fpreg_d_type;
565 /* Implement the register_type gdbarch method. This is installed as an
566 for the override setup by TDESC_USE_REGISTERS, for most registers we
567 delegate the type choice to the target description, but for a few
568 registers we try to improve the types if the target description has
569 taken a simplistic approach. */
572 riscv_register_type (struct gdbarch *gdbarch, int regnum)
574 struct type *type = tdesc_register_type (gdbarch, regnum);
575 int xlen = riscv_isa_xlen (gdbarch);
577 /* We want to perform some specific type "fixes" in cases where we feel
578 that we really can do better than the target description. For all
579 other cases we just return what the target description says. */
580 if (riscv_is_fp_regno_p (regnum))
582 /* This spots the case for RV64 where the double is defined as
583 either 'ieee_double' or 'float' (which is the generic name that
584 converts to 'double' on 64-bit). In these cases its better to
585 present the registers using a union type. */
586 int flen = riscv_isa_flen (gdbarch);
588 && TYPE_CODE (type) == TYPE_CODE_FLT
589 && TYPE_LENGTH (type) == flen
590 && (strcmp (TYPE_NAME (type), "builtin_type_ieee_double") == 0
591 || strcmp (TYPE_NAME (type), "double") == 0))
592 type = riscv_fpreg_d_type (gdbarch);
595 if ((regnum == gdbarch_pc_regnum (gdbarch)
596 || regnum == RISCV_RA_REGNUM
597 || regnum == RISCV_FP_REGNUM
598 || regnum == RISCV_SP_REGNUM
599 || regnum == RISCV_GP_REGNUM
600 || regnum == RISCV_TP_REGNUM)
601 && TYPE_CODE (type) == TYPE_CODE_INT
602 && TYPE_LENGTH (type) == xlen)
604 /* This spots the case where some interesting registers are defined
605 as simple integers of the expected size, we force these registers
606 to be pointers as we believe that is more useful. */
607 if (regnum == gdbarch_pc_regnum (gdbarch)
608 || regnum == RISCV_RA_REGNUM)
609 type = builtin_type (gdbarch)->builtin_func_ptr;
610 else if (regnum == RISCV_FP_REGNUM
611 || regnum == RISCV_SP_REGNUM
612 || regnum == RISCV_GP_REGNUM
613 || regnum == RISCV_TP_REGNUM)
614 type = builtin_type (gdbarch)->builtin_data_ptr;
620 /* Helper for riscv_print_registers_info, prints info for a single register
624 riscv_print_one_register_info (struct gdbarch *gdbarch,
625 struct ui_file *file,
626 struct frame_info *frame,
629 const char *name = gdbarch_register_name (gdbarch, regnum);
631 struct type *regtype;
632 int print_raw_format;
633 enum tab_stops { value_column_1 = 15 };
635 fputs_filtered (name, file);
636 print_spaces_filtered (value_column_1 - strlen (name), file);
640 val = value_of_register (regnum, frame);
641 regtype = value_type (val);
643 CATCH (ex, RETURN_MASK_ERROR)
645 /* Handle failure to read a register without interrupting the entire
646 'info registers' flow. */
647 fprintf_filtered (file, "%s\n", ex.message);
652 print_raw_format = (value_entirely_available (val)
653 && !value_optimized_out (val));
655 if (TYPE_CODE (regtype) == TYPE_CODE_FLT
656 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
657 && TYPE_NFIELDS (regtype) == 2
658 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
659 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
660 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
661 && TYPE_NFIELDS (regtype) == 3
662 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
663 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
664 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
666 struct value_print_options opts;
667 const gdb_byte *valaddr = value_contents_for_printing (val);
668 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
670 get_user_print_options (&opts);
674 value_embedded_offset (val), 0,
675 file, 0, val, &opts, current_language);
677 if (print_raw_format)
679 fprintf_filtered (file, "\t(raw ");
680 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
682 fprintf_filtered (file, ")");
687 struct value_print_options opts;
689 /* Print the register in hex. */
690 get_formatted_print_options (&opts, 'x');
693 value_embedded_offset (val), 0,
694 file, 0, val, &opts, current_language);
696 if (print_raw_format)
698 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
701 int size = register_size (gdbarch, regnum);
704 /* The SD field is always in the upper bit of MSTATUS, regardless
705 of the number of bits in MSTATUS. */
706 d = value_as_long (val);
708 fprintf_filtered (file,
709 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
710 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
711 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
712 (int) ((d >> (xlen - 1)) & 0x1),
713 (int) ((d >> 24) & 0x1f),
714 (int) ((d >> 19) & 0x1),
715 (int) ((d >> 18) & 0x1),
716 (int) ((d >> 17) & 0x1),
717 (int) ((d >> 15) & 0x3),
718 (int) ((d >> 13) & 0x3),
719 (int) ((d >> 11) & 0x3),
720 (int) ((d >> 9) & 0x3),
721 (int) ((d >> 8) & 0x1),
722 (int) ((d >> 7) & 0x1),
723 (int) ((d >> 6) & 0x1),
724 (int) ((d >> 5) & 0x1),
725 (int) ((d >> 4) & 0x1),
726 (int) ((d >> 3) & 0x1),
727 (int) ((d >> 2) & 0x1),
728 (int) ((d >> 1) & 0x1),
729 (int) ((d >> 0) & 0x1));
731 else if (regnum == RISCV_CSR_MISA_REGNUM)
736 int size = register_size (gdbarch, regnum);
738 /* The MXL field is always in the upper two bits of MISA,
739 regardless of the number of bits in MISA. Mask out other
740 bits to ensure we have a positive value. */
741 d = value_as_long (val);
742 base = (d >> ((size * 8) - 2)) & 0x3;
745 for (; base > 0; base--)
747 fprintf_filtered (file, "\tRV%d", xlen);
749 for (i = 0; i < 26; i++)
752 fprintf_filtered (file, "%c", 'A' + i);
755 else if (regnum == RISCV_CSR_FCSR_REGNUM
756 || regnum == RISCV_CSR_FFLAGS_REGNUM
757 || regnum == RISCV_CSR_FRM_REGNUM)
761 d = value_as_long (val);
763 fprintf_filtered (file, "\t");
764 if (regnum != RISCV_CSR_FRM_REGNUM)
765 fprintf_filtered (file,
766 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
767 (int) ((d >> 5) & 0x7),
768 (int) ((d >> 4) & 0x1),
769 (int) ((d >> 3) & 0x1),
770 (int) ((d >> 2) & 0x1),
771 (int) ((d >> 1) & 0x1),
772 (int) ((d >> 0) & 0x1));
774 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
776 static const char * const sfrm[] =
778 "RNE (round to nearest; ties to even)",
779 "RTZ (Round towards zero)",
780 "RDN (Round down towards -INF)",
781 "RUP (Round up towards +INF)",
782 "RMM (Round to nearest; ties to max magnitude)",
785 "dynamic rounding mode",
787 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
788 ? (d >> 5) : d) & 0x3;
790 fprintf_filtered (file, "%sFRM:%i [%s]",
791 (regnum == RISCV_CSR_FCSR_REGNUM
796 else if (regnum == RISCV_PRIV_REGNUM)
801 d = value_as_long (val);
806 static const char * const sprv[] =
813 fprintf_filtered (file, "\tprv:%d [%s]",
817 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
821 /* If not a vector register, print it also according to its
823 if (TYPE_VECTOR (regtype) == 0)
825 get_user_print_options (&opts);
827 fprintf_filtered (file, "\t");
829 value_embedded_offset (val), 0,
830 file, 0, val, &opts, current_language);
835 fprintf_filtered (file, "\n");
838 /* Return true if REGNUM is a valid CSR register. The CSR register space
839 is sparsely populated, so not every number is a named CSR. */
842 riscv_is_regnum_a_named_csr (int regnum)
844 gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
845 && regnum <= RISCV_LAST_CSR_REGNUM);
849 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
850 #include "opcode/riscv-opc.h"
859 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
863 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
864 struct reggroup *reggroup)
866 /* Used by 'info registers' and 'info registers <groupname>'. */
868 if (gdbarch_register_name (gdbarch, regnum) == NULL
869 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
872 if (regnum > RISCV_LAST_REGNUM)
874 int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
878 return default_register_reggroup_p (gdbarch, regnum, reggroup);
881 if (reggroup == all_reggroup)
883 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
885 if (riscv_is_regnum_a_named_csr (regnum))
889 else if (reggroup == float_reggroup)
890 return (riscv_is_fp_regno_p (regnum)
891 || regnum == RISCV_CSR_FCSR_REGNUM
892 || regnum == RISCV_CSR_FFLAGS_REGNUM
893 || regnum == RISCV_CSR_FRM_REGNUM);
894 else if (reggroup == general_reggroup)
895 return regnum < RISCV_FIRST_FP_REGNUM;
896 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
898 if (riscv_has_fp_regs (gdbarch))
899 return regnum <= RISCV_LAST_FP_REGNUM;
901 return regnum < RISCV_FIRST_FP_REGNUM;
903 else if (reggroup == system_reggroup || reggroup == csr_reggroup)
905 if (regnum == RISCV_PRIV_REGNUM)
907 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
909 if (riscv_is_regnum_a_named_csr (regnum))
913 else if (reggroup == vector_reggroup)
919 /* Implement the print_registers_info gdbarch method. This is used by
920 'info registers' and 'info all-registers'. */
923 riscv_print_registers_info (struct gdbarch *gdbarch,
924 struct ui_file *file,
925 struct frame_info *frame,
926 int regnum, int print_all)
930 /* Print one specified register. */
931 if (gdbarch_register_name (gdbarch, regnum) == NULL
932 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
933 error (_("Not a valid register for the current processor type"));
934 riscv_print_one_register_info (gdbarch, file, frame, regnum);
938 struct reggroup *reggroup;
941 reggroup = all_reggroup;
943 reggroup = general_reggroup;
945 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
947 /* Zero never changes, so might as well hide by default. */
948 if (regnum == RISCV_ZERO_REGNUM && !print_all)
951 /* Registers with no name are not valid on this ISA. */
952 if (gdbarch_register_name (gdbarch, regnum) == NULL
953 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
956 /* Is the register in the group we're interested in? */
957 if (!gdbarch_register_reggroup_p (gdbarch, regnum, reggroup))
960 riscv_print_one_register_info (gdbarch, file, frame, regnum);
965 /* Class that handles one decoded RiscV instruction. */
971 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
974 /* Unknown value is used at initialisation time. */
977 /* These instructions are all the ones we are interested in during the
987 /* These are needed for software breakopint support. */
996 /* These are needed for stepping over atomic sequences. */
1000 /* Other instructions are not interesting during the prologue scan, and
1015 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1017 /* Get the length of the instruction in bytes. */
1019 { return m_length; }
1021 /* Get the opcode for this instruction. */
1022 enum opcode opcode () const
1023 { return m_opcode; }
1025 /* Get destination register field for this instruction. This is only
1026 valid if the OPCODE implies there is such a field for this
1031 /* Get the RS1 register field for this instruction. This is only valid
1032 if the OPCODE implies there is such a field for this instruction. */
1036 /* Get the RS2 register field for this instruction. This is only valid
1037 if the OPCODE implies there is such a field for this instruction. */
1041 /* Get the immediate for this instruction in signed form. This is only
1042 valid if the OPCODE implies there is such a field for this
1044 int imm_signed () const
1049 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1050 int decode_register_index (unsigned long opcode, int offset)
1052 return (opcode >> offset) & 0x1F;
1055 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1056 int decode_register_index_short (unsigned long opcode, int offset)
1058 return ((opcode >> offset) & 0x7) + 8;
1061 /* Helper for DECODE, decode 32-bit R-type instruction. */
1062 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1065 m_rd = decode_register_index (ival, OP_SH_RD);
1066 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1067 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1070 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1071 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1074 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1075 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1078 /* Helper for DECODE, decode 32-bit I-type instruction. */
1079 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1082 m_rd = decode_register_index (ival, OP_SH_RD);
1083 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1084 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1087 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1088 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1091 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1092 m_imm.s = EXTRACT_RVC_IMM (ival);
1095 /* Helper for DECODE, decode 32-bit S-type instruction. */
1096 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1099 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1100 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1101 m_imm.s = EXTRACT_STYPE_IMM (ival);
1104 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1105 encoding is different for each CS format instruction, so extracting
1106 the immediate is left up to the caller, who should pass the extracted
1107 immediate value through in IMM. */
1108 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1112 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1113 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1116 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1117 encoding is different for each CSS format instruction, so extracting
1118 the immediate is left up to the caller, who should pass the extracted
1119 immediate value through in IMM. */
1120 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1124 m_rs1 = RISCV_SP_REGNUM;
1125 /* Not a compressed register number in this case. */
1126 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1129 /* Helper for DECODE, decode 32-bit U-type instruction. */
1130 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1133 m_rd = decode_register_index (ival, OP_SH_RD);
1134 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1137 /* Helper for DECODE, decode 32-bit J-type instruction. */
1138 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1141 m_rd = decode_register_index (ival, OP_SH_RD);
1142 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1145 /* Helper for DECODE, decode 32-bit J-type instruction. */
1146 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1149 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1152 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1155 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1156 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1157 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1160 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1163 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1164 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1167 /* Fetch instruction from target memory at ADDR, return the content of
1168 the instruction, and update LEN with the instruction length. */
1169 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1170 CORE_ADDR addr, int *len);
1172 /* The length of the instruction in bytes. Should be 2 or 4. */
1175 /* The instruction opcode. */
1176 enum opcode m_opcode;
1178 /* The three possible registers an instruction might reference. Not
1179 every instruction fills in all of these registers. Which fields are
1180 valid depends on the opcode. The naming of these fields matches the
1181 naming in the riscv isa manual. */
1186 /* Possible instruction immediate. This is only valid if the instruction
1187 format contains an immediate, not all instruction, whether this is
1188 valid depends on the opcode. Despite only having one format for now
1189 the immediate is packed into a union, later instructions might require
1190 an unsigned formatted immediate, having the union in place now will
1191 reduce the need for code churn later. */
1192 union riscv_insn_immediate
1194 riscv_insn_immediate ()
1204 /* Fetch instruction from target memory at ADDR, return the content of the
1205 instruction, and update LEN with the instruction length. */
1208 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1209 CORE_ADDR addr, int *len)
1211 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1213 int instlen, status;
1215 /* All insns are at least 16 bits. */
1216 status = target_read_memory (addr, buf, 2);
1218 memory_error (TARGET_XFER_E_IO, addr);
1220 /* If we need more, grab it now. */
1221 instlen = riscv_insn_length (buf[0]);
1222 gdb_assert (instlen <= sizeof (buf));
1227 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1229 memory_error (TARGET_XFER_E_IO, addr + 2);
1232 return extract_unsigned_integer (buf, instlen, byte_order);
1235 /* Fetch from target memory an instruction at PC and decode it. This can
1236 throw an error if the memory access fails, callers are responsible for
1237 handling this error if that is appropriate. */
1240 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1244 /* Fetch the instruction, and the instructions length. */
1245 ival = fetch_instruction (gdbarch, pc, &m_length);
1249 if (is_add_insn (ival))
1250 decode_r_type_insn (ADD, ival);
1251 else if (is_addw_insn (ival))
1252 decode_r_type_insn (ADDW, ival);
1253 else if (is_addi_insn (ival))
1254 decode_i_type_insn (ADDI, ival);
1255 else if (is_addiw_insn (ival))
1256 decode_i_type_insn (ADDIW, ival);
1257 else if (is_auipc_insn (ival))
1258 decode_u_type_insn (AUIPC, ival);
1259 else if (is_lui_insn (ival))
1260 decode_u_type_insn (LUI, ival);
1261 else if (is_sd_insn (ival))
1262 decode_s_type_insn (SD, ival);
1263 else if (is_sw_insn (ival))
1264 decode_s_type_insn (SW, ival);
1265 else if (is_jal_insn (ival))
1266 decode_j_type_insn (JAL, ival);
1267 else if (is_jalr_insn (ival))
1268 decode_i_type_insn (JALR, ival);
1269 else if (is_beq_insn (ival))
1270 decode_b_type_insn (BEQ, ival);
1271 else if (is_bne_insn (ival))
1272 decode_b_type_insn (BNE, ival);
1273 else if (is_blt_insn (ival))
1274 decode_b_type_insn (BLT, ival);
1275 else if (is_bge_insn (ival))
1276 decode_b_type_insn (BGE, ival);
1277 else if (is_bltu_insn (ival))
1278 decode_b_type_insn (BLTU, ival);
1279 else if (is_bgeu_insn (ival))
1280 decode_b_type_insn (BGEU, ival);
1281 else if (is_lr_w_insn (ival))
1282 decode_r_type_insn (LR, ival);
1283 else if (is_lr_d_insn (ival))
1284 decode_r_type_insn (LR, ival);
1285 else if (is_sc_w_insn (ival))
1286 decode_r_type_insn (SC, ival);
1287 else if (is_sc_d_insn (ival))
1288 decode_r_type_insn (SC, ival);
1290 /* None of the other fields are valid in this case. */
1293 else if (m_length == 2)
1295 int xlen = riscv_isa_xlen (gdbarch);
1297 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1298 C_JALR. So must try to match C_JALR first as it has more bits in
1300 if (is_c_jalr_insn (ival))
1301 decode_cr_type_insn (JALR, ival);
1302 else if (is_c_add_insn (ival))
1303 decode_cr_type_insn (ADD, ival);
1304 /* C_ADDW is RV64 and RV128 only. */
1305 else if (xlen != 4 && is_c_addw_insn (ival))
1306 decode_cr_type_insn (ADDW, ival);
1307 else if (is_c_addi_insn (ival))
1308 decode_ci_type_insn (ADDI, ival);
1309 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1310 only and C_JAL is RV32 only. */
1311 else if (xlen != 4 && is_c_addiw_insn (ival))
1312 decode_ci_type_insn (ADDIW, ival);
1313 else if (xlen == 4 && is_c_jal_insn (ival))
1314 decode_cj_type_insn (JAL, ival);
1315 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1316 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1318 else if (is_c_addi16sp_insn (ival))
1321 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1322 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1324 else if (is_c_addi4spn_insn (ival))
1327 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1328 m_rs1 = RISCV_SP_REGNUM;
1329 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1331 else if (is_c_lui_insn (ival))
1334 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1335 m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
1337 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1338 and C_FSW is RV32 only. */
1339 else if (xlen != 4 && is_c_sd_insn (ival))
1340 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
1341 else if (is_c_sw_insn (ival))
1342 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1343 else if (is_c_swsp_insn (ival))
1344 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1345 else if (xlen != 4 && is_c_sdsp_insn (ival))
1346 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
1347 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1348 So must try to match C_JR first as it ahs more bits in mask. */
1349 else if (is_c_jr_insn (ival))
1350 decode_cr_type_insn (JALR, ival);
1351 else if (is_c_j_insn (ival))
1352 decode_cj_type_insn (JAL, ival);
1353 else if (is_c_beqz_insn (ival))
1354 decode_cb_type_insn (BEQ, ival);
1355 else if (is_c_bnez_insn (ival))
1356 decode_cb_type_insn (BNE, ival);
1358 /* None of the other fields of INSN are valid in this case. */
1362 internal_error (__FILE__, __LINE__,
1363 _("unable to decode %d byte instructions in "
1364 "prologue at %s"), m_length,
1365 core_addr_to_string (pc));
1368 /* The prologue scanner. This is currently only used for skipping the
1369 prologue of a function when the DWARF information is not sufficient.
1370 However, it is written with filling of the frame cache in mind, which
1371 is why different groups of stack setup instructions are split apart
1372 during the core of the inner loop. In the future, the intention is to
1373 extend this function to fully support building up a frame cache that
1374 can unwind register values when there is no DWARF information. */
1377 riscv_scan_prologue (struct gdbarch *gdbarch,
1378 CORE_ADDR start_pc, CORE_ADDR end_pc,
1379 struct riscv_unwind_cache *cache)
1381 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1382 CORE_ADDR end_prologue_addr = 0;
1384 /* Find an upper limit on the function prologue using the debug
1385 information. If the debug information could not be used to provide
1386 that bound, then use an arbitrary large number as the upper bound. */
1387 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1388 if (after_prologue_pc == 0)
1389 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1390 if (after_prologue_pc < end_pc)
1391 end_pc = after_prologue_pc;
1393 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1394 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1395 regs[regno] = pv_register (regno, 0);
1396 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1398 if (riscv_debug_unwinder)
1401 "Prologue scan for function starting at %s (limit %s)\n",
1402 core_addr_to_string (start_pc),
1403 core_addr_to_string (end_pc));
1405 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1407 struct riscv_insn insn;
1409 /* Decode the current instruction, and decide where the next
1410 instruction lives based on the size of this instruction. */
1411 insn.decode (gdbarch, cur_pc);
1412 gdb_assert (insn.length () > 0);
1413 next_pc = cur_pc + insn.length ();
1415 /* Look for common stack adjustment insns. */
1416 if ((insn.opcode () == riscv_insn::ADDI
1417 || insn.opcode () == riscv_insn::ADDIW)
1418 && insn.rd () == RISCV_SP_REGNUM
1419 && insn.rs1 () == RISCV_SP_REGNUM)
1421 /* Handle: addi sp, sp, -i
1422 or: addiw sp, sp, -i */
1423 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1424 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1426 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1428 else if ((insn.opcode () == riscv_insn::SW
1429 || insn.opcode () == riscv_insn::SD)
1430 && (insn.rs1 () == RISCV_SP_REGNUM
1431 || insn.rs1 () == RISCV_FP_REGNUM))
1433 /* Handle: sw reg, offset(sp)
1434 or: sd reg, offset(sp)
1435 or: sw reg, offset(s0)
1436 or: sd reg, offset(s0) */
1437 /* Instruction storing a register onto the stack. */
1438 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1439 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1440 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1441 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1444 else if (insn.opcode () == riscv_insn::ADDI
1445 && insn.rd () == RISCV_FP_REGNUM
1446 && insn.rs1 () == RISCV_SP_REGNUM)
1448 /* Handle: addi s0, sp, size */
1449 /* Instructions setting up the frame pointer. */
1450 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1451 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1453 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1455 else if ((insn.opcode () == riscv_insn::ADD
1456 || insn.opcode () == riscv_insn::ADDW)
1457 && insn.rd () == RISCV_FP_REGNUM
1458 && insn.rs1 () == RISCV_SP_REGNUM
1459 && insn.rs2 () == RISCV_ZERO_REGNUM)
1461 /* Handle: add s0, sp, 0
1462 or: addw s0, sp, 0 */
1463 /* Instructions setting up the frame pointer. */
1464 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1465 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1466 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1468 else if ((insn.opcode () == riscv_insn::ADDI
1469 && insn.rd () == RISCV_ZERO_REGNUM
1470 && insn.rs1 () == RISCV_ZERO_REGNUM
1471 && insn.imm_signed () == 0))
1473 /* Handle: add x0, x0, 0 (NOP) */
1475 else if (insn.opcode () == riscv_insn::AUIPC)
1477 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1478 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1480 else if (insn.opcode () == riscv_insn::LUI)
1482 /* Handle: lui REG, n
1483 Where REG is not gp register. */
1484 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1485 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1487 else if (insn.opcode () == riscv_insn::ADDI)
1489 /* Handle: addi REG1, REG2, IMM */
1490 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1491 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1493 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1495 else if (insn.opcode () == riscv_insn::ADD)
1497 /* Handle: addi REG1, REG2, IMM */
1498 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1499 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1500 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1501 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1505 end_prologue_addr = cur_pc;
1510 if (end_prologue_addr == 0)
1511 end_prologue_addr = cur_pc;
1513 if (riscv_debug_unwinder)
1514 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1515 core_addr_to_string (end_prologue_addr));
1519 /* Figure out if it is a frame pointer or just a stack pointer. Also
1520 the offset held in the pv_t is from the original register value to
1521 the current value, which for a grows down stack means a negative
1522 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1523 from the current value to the original value. */
1524 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1526 cache->frame_base_reg = RISCV_FP_REGNUM;
1527 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1531 cache->frame_base_reg = RISCV_SP_REGNUM;
1532 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1535 /* Assign offset from old SP to all saved registers. As we don't
1536 have the previous value for the frame base register at this
1537 point, we store the offset as the address in the trad_frame, and
1538 then convert this to an actual address later. */
1539 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1542 if (stack.find_reg (gdbarch, i, &offset))
1544 if (riscv_debug_unwinder)
1545 fprintf_unfiltered (gdb_stdlog,
1546 "Register $%s at stack offset %ld\n",
1547 gdbarch_register_name (gdbarch, i),
1549 trad_frame_set_addr (cache->regs, i, offset);
1554 return end_prologue_addr;
1557 /* Implement the riscv_skip_prologue gdbarch method. */
1560 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1562 CORE_ADDR func_addr;
1564 /* See if we can determine the end of the prologue via the symbol
1565 table. If so, then return either PC, or the PC after the
1566 prologue, whichever is greater. */
1567 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1569 CORE_ADDR post_prologue_pc
1570 = skip_prologue_using_sal (gdbarch, func_addr);
1572 if (post_prologue_pc != 0)
1573 return std::max (pc, post_prologue_pc);
1576 /* Can't determine prologue from the symbol table, need to examine
1577 instructions. Pass -1 for the end address to indicate the prologue
1578 scanner can scan as far as it needs to find the end of the prologue. */
1579 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1582 /* Implement the gdbarch push dummy code callback. */
1585 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1586 CORE_ADDR funaddr, struct value **args, int nargs,
1587 struct type *value_type, CORE_ADDR *real_pc,
1588 CORE_ADDR *bp_addr, struct regcache *regcache)
1590 /* Allocate space for a breakpoint, and keep the stack correctly
1598 /* Compute the alignment of the type T. Used while setting up the
1599 arguments for a dummy call. */
1602 riscv_type_alignment (struct type *t)
1604 t = check_typedef (t);
1605 switch (TYPE_CODE (t))
1608 error (_("Could not compute alignment of type"));
1610 case TYPE_CODE_RVALUE_REF:
1612 case TYPE_CODE_ENUM:
1616 case TYPE_CODE_CHAR:
1617 case TYPE_CODE_BOOL:
1618 return TYPE_LENGTH (t);
1620 case TYPE_CODE_ARRAY:
1621 if (TYPE_VECTOR (t))
1622 return std::min (TYPE_LENGTH (t), (unsigned) BIGGEST_ALIGNMENT);
1625 case TYPE_CODE_COMPLEX:
1626 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1628 case TYPE_CODE_STRUCT:
1629 case TYPE_CODE_UNION:
1634 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1636 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1638 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1648 /* Holds information about a single argument either being passed to an
1649 inferior function, or returned from an inferior function. This includes
1650 information about the size, type, etc of the argument, and also
1651 information about how the argument will be passed (or returned). */
1653 struct riscv_arg_info
1655 /* Contents of the argument. */
1656 const gdb_byte *contents;
1658 /* Length of argument. */
1661 /* Alignment required for an argument of this type. */
1664 /* The type for this argument. */
1667 /* Each argument can have either 1 or 2 locations assigned to it. Each
1668 location describes where part of the argument will be placed. The
1669 second location is valid based on the LOC_TYPE and C_LENGTH fields
1670 of the first location (which is always valid). */
1673 /* What type of location this is. */
1676 /* Argument passed in a register. */
1679 /* Argument passed as an on stack argument. */
1682 /* Argument passed by reference. The second location is always
1683 valid for a BY_REF argument, and describes where the address
1684 of the BY_REF argument should be placed. */
1688 /* Information that depends on the location type. */
1691 /* Which register number to use. */
1694 /* The offset into the stack region. */
1698 /* The length of contents covered by this location. If this is less
1699 than the total length of the argument, then the second location
1700 will be valid, and will describe where the rest of the argument
1704 /* The offset within CONTENTS for this part of the argument. Will
1705 always be 0 for the first part. For the second part of the
1706 argument, this might be the C_LENGTH value of the first part,
1707 however, if we are passing a structure in two registers, and there's
1708 is padding between the first and second field, then this offset
1709 might be greater than the length of the first argument part. When
1710 the second argument location is not holding part of the argument
1711 value, but is instead holding the address of a reference argument,
1712 then this offset will be set to 0. */
1716 /* TRUE if this is an unnamed argument. */
1720 /* Information about a set of registers being used for passing arguments as
1721 part of a function call. The register set must be numerically
1722 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1723 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1725 struct riscv_arg_reg
1727 riscv_arg_reg (int first, int last)
1728 : next_regnum (first),
1734 /* The GDB register number to use in this set. */
1737 /* The last GDB register number to use in this set. */
1741 /* Arguments can be passed as on stack arguments, or by reference. The
1742 on stack arguments must be in a continuous region starting from $sp,
1743 while the by reference arguments can be anywhere, but we'll put them
1744 on the stack after (at higher address) the on stack arguments.
1746 This might not be the right approach to take. The ABI is clear that
1747 an argument passed by reference can be modified by the callee, which
1748 us placing the argument (temporarily) onto the stack will not achieve
1749 (changes will be lost). There's also the possibility that very large
1750 arguments could overflow the stack.
1752 This struct is used to track offset into these two areas for where
1753 arguments are to be placed. */
1754 struct riscv_memory_offsets
1756 riscv_memory_offsets ()
1763 /* Offset into on stack argument area. */
1766 /* Offset into the pass by reference area. */
1770 /* Holds information about where arguments to a call will be placed. This
1771 is updated as arguments are added onto the call, and can be used to
1772 figure out where the next argument should be placed. */
1774 struct riscv_call_info
1776 riscv_call_info (struct gdbarch *gdbarch)
1777 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1778 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1780 xlen = riscv_isa_xlen (gdbarch);
1781 flen = riscv_isa_flen (gdbarch);
1783 /* Disable use of floating point registers if needed. */
1784 if (!riscv_has_fp_abi (gdbarch))
1785 float_regs.next_regnum = float_regs.last_regnum + 1;
1788 /* Track the memory areas used for holding in-memory arguments to a
1790 struct riscv_memory_offsets memory;
1792 /* Holds information about the next integer register to use for passing
1794 struct riscv_arg_reg int_regs;
1796 /* Holds information about the next floating point register to use for
1797 passing an argument. */
1798 struct riscv_arg_reg float_regs;
1800 /* The XLEN and FLEN are copied in to this structure for convenience, and
1801 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1806 /* Return the number of registers available for use as parameters in the
1807 register set REG. Returned value can be 0 or more. */
1810 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1812 if (reg->next_regnum > reg->last_regnum)
1815 return (reg->last_regnum - reg->next_regnum + 1);
1818 /* If there is at least one register available in the register set REG then
1819 the next register from REG is assigned to LOC and the length field of
1820 LOC is updated to LENGTH. The register set REG is updated to indicate
1821 that the assigned register is no longer available and the function
1824 If there are no registers available in REG then the function returns
1825 false, and LOC and REG are unchanged. */
1828 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1829 struct riscv_arg_reg *reg,
1830 int length, int offset)
1832 if (reg->next_regnum <= reg->last_regnum)
1834 loc->loc_type = riscv_arg_info::location::in_reg;
1835 loc->loc_data.regno = reg->next_regnum;
1837 loc->c_length = length;
1838 loc->c_offset = offset;
1845 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1846 record that an area of stack has been used to hold the parameter
1849 The length field of LOC is updated to LENGTH, the length of the
1850 parameter being stored, and ALIGN is the alignment required by the
1851 parameter, which will affect how memory is allocated out of MEMORY. */
1854 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1855 struct riscv_memory_offsets *memory,
1856 int length, int align)
1858 loc->loc_type = riscv_arg_info::location::on_stack;
1860 = align_up (memory->arg_offset, align);
1861 loc->loc_data.offset = memory->arg_offset;
1862 memory->arg_offset += length;
1863 loc->c_length = length;
1865 /* Offset is always 0, either we're the first location part, in which
1866 case we're reading content from the start of the argument, or we're
1867 passing the address of a reference argument, so 0. */
1871 /* Update AINFO, which describes an argument that should be passed or
1872 returned using the integer ABI. The argloc fields within AINFO are
1873 updated to describe the location in which the argument will be passed to
1874 a function, or returned from a function.
1876 The CINFO structure contains the ongoing call information, the holds
1877 information such as which argument registers are remaining to be
1878 assigned to parameter, and how much memory has been used by parameters
1881 By examining the state of CINFO a suitable location can be selected,
1882 and assigned to AINFO. */
1885 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1886 struct riscv_call_info *cinfo)
1888 if (ainfo->length > (2 * cinfo->xlen))
1890 /* Argument is going to be passed by reference. */
1891 ainfo->argloc[0].loc_type
1892 = riscv_arg_info::location::by_ref;
1893 cinfo->memory.ref_offset
1894 = align_up (cinfo->memory.ref_offset, ainfo->align);
1895 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1896 cinfo->memory.ref_offset += ainfo->length;
1897 ainfo->argloc[0].c_length = ainfo->length;
1899 /* The second location for this argument is given over to holding the
1900 address of the by-reference data. Pass 0 for the offset as this
1901 is not part of the actual argument value. */
1902 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1905 riscv_assign_stack_location (&ainfo->argloc[1],
1906 &cinfo->memory, cinfo->xlen,
1911 int len = std::min (ainfo->length, cinfo->xlen);
1912 int align = std::max (ainfo->align, cinfo->xlen);
1914 /* Unnamed arguments in registers that require 2*XLEN alignment are
1915 passed in an aligned register pair. */
1916 if (ainfo->is_unnamed && (align == cinfo->xlen * 2)
1917 && cinfo->int_regs.next_regnum & 1)
1918 cinfo->int_regs.next_regnum++;
1920 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1921 &cinfo->int_regs, len, 0))
1922 riscv_assign_stack_location (&ainfo->argloc[0],
1923 &cinfo->memory, len, align);
1925 if (len < ainfo->length)
1927 len = ainfo->length - len;
1928 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1929 &cinfo->int_regs, len,
1931 riscv_assign_stack_location (&ainfo->argloc[1],
1932 &cinfo->memory, len, cinfo->xlen);
1937 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1938 is being passed with the floating point ABI. */
1941 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1942 struct riscv_call_info *cinfo)
1944 if (ainfo->length > cinfo->flen || ainfo->is_unnamed)
1945 return riscv_call_arg_scalar_int (ainfo, cinfo);
1948 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1951 return riscv_call_arg_scalar_int (ainfo, cinfo);
1955 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1956 is a complex floating point argument, and is therefore handled
1957 differently to other argument types. */
1960 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1961 struct riscv_call_info *cinfo)
1963 if (ainfo->length <= (2 * cinfo->flen)
1964 && riscv_arg_regs_available (&cinfo->float_regs) >= 2
1965 && !ainfo->is_unnamed)
1968 int len = ainfo->length / 2;
1970 result = riscv_assign_reg_location (&ainfo->argloc[0],
1971 &cinfo->float_regs, len, len);
1972 gdb_assert (result);
1974 result = riscv_assign_reg_location (&ainfo->argloc[1],
1975 &cinfo->float_regs, len, len);
1976 gdb_assert (result);
1979 return riscv_call_arg_scalar_int (ainfo, cinfo);
1982 /* A structure used for holding information about a structure type within
1983 the inferior program. The RiscV ABI has special rules for handling some
1984 structures with a single field or with two fields. The counting of
1985 fields here is done after flattening out all nested structures. */
1987 class riscv_struct_info
1990 riscv_struct_info ()
1991 : m_number_of_fields (0),
1992 m_types { nullptr, nullptr }
1997 /* Analyse TYPE descending into nested structures, count the number of
1998 scalar fields and record the types of the first two fields found. */
1999 void analyse (struct type *type);
2001 /* The number of scalar fields found in the analysed type. This is
2002 currently only accurate if the value returned is 0, 1, or 2 as the
2003 analysis stops counting when the number of fields is 3. This is
2004 because the RiscV ABI only has special cases for 1 or 2 fields,
2005 anything else we just don't care about. */
2006 int number_of_fields () const
2007 { return m_number_of_fields; }
2009 /* Return the type for scalar field INDEX within the analysed type. Will
2010 return nullptr if there is no field at that index. Only INDEX values
2011 0 and 1 can be requested as the RiscV ABI only has special cases for
2012 structures with 1 or 2 fields. */
2013 struct type *field_type (int index) const
2015 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
2016 return m_types[index];
2020 /* The number of scalar fields found within the structure after recursing
2021 into nested structures. */
2022 int m_number_of_fields;
2024 /* The types of the first two scalar fields found within the structure
2025 after recursing into nested structures. */
2026 struct type *m_types[2];
2029 /* Analyse TYPE descending into nested structures, count the number of
2030 scalar fields and record the types of the first two fields found. */
2033 riscv_struct_info::analyse (struct type *type)
2035 unsigned int count = TYPE_NFIELDS (type);
2038 for (i = 0; i < count; ++i)
2040 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
2043 struct type *field_type = TYPE_FIELD_TYPE (type, i);
2044 field_type = check_typedef (field_type);
2046 switch (TYPE_CODE (field_type))
2048 case TYPE_CODE_STRUCT:
2049 analyse (field_type);
2053 /* RiscV only flattens out structures. Anything else does not
2054 need to be flattened, we just record the type, and when we
2055 look at the analysis results we'll realise this is not a
2056 structure we can special case, and pass the structure in
2058 if (m_number_of_fields < 2)
2059 m_types[m_number_of_fields] = field_type;
2060 m_number_of_fields++;
2064 /* RiscV only has special handling for structures with 1 or 2 scalar
2065 fields, any more than that and the structure is just passed in
2066 memory. We can safely drop out early when we find 3 or more
2069 if (m_number_of_fields > 2)
2074 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2075 is a structure. Small structures on RiscV have some special case
2076 handling in order that the structure might be passed in register.
2077 Larger structures are passed in memory. After assigning location
2078 information to AINFO, CINFO will have been updated. */
2081 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
2082 struct riscv_call_info *cinfo)
2084 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2086 struct riscv_struct_info sinfo;
2088 sinfo.analyse (ainfo->type);
2089 if (sinfo.number_of_fields () == 1
2090 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
2092 gdb_assert (TYPE_LENGTH (ainfo->type)
2093 == TYPE_LENGTH (sinfo.field_type (0)));
2094 return riscv_call_arg_complex_float (ainfo, cinfo);
2097 if (sinfo.number_of_fields () == 1
2098 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
2100 gdb_assert (TYPE_LENGTH (ainfo->type)
2101 == TYPE_LENGTH (sinfo.field_type (0)));
2102 return riscv_call_arg_scalar_float (ainfo, cinfo);
2105 if (sinfo.number_of_fields () == 2
2106 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2107 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2108 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2109 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
2110 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2112 int len0, len1, offset;
2114 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
2116 len0 = TYPE_LENGTH (sinfo.field_type (0));
2117 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2118 &cinfo->float_regs, len0, 0))
2119 error (_("failed during argument setup"));
2121 len1 = TYPE_LENGTH (sinfo.field_type (1));
2122 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2123 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2124 - TYPE_LENGTH (sinfo.field_type (0))));
2126 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2129 error (_("failed during argument setup"));
2133 if (sinfo.number_of_fields () == 2
2134 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2135 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2136 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2137 && is_integral_type (sinfo.field_type (1))
2138 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2140 int len0, len1, offset;
2142 gdb_assert (TYPE_LENGTH (ainfo->type)
2143 <= (cinfo->flen + cinfo->xlen));
2145 len0 = TYPE_LENGTH (sinfo.field_type (0));
2146 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2147 &cinfo->float_regs, len0, 0))
2148 error (_("failed during argument setup"));
2150 len1 = TYPE_LENGTH (sinfo.field_type (1));
2151 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2152 gdb_assert (len1 <= cinfo->xlen);
2153 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2154 &cinfo->int_regs, len1, offset))
2155 error (_("failed during argument setup"));
2159 if (sinfo.number_of_fields () == 2
2160 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2161 && (is_integral_type (sinfo.field_type (0))
2162 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2163 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2164 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2166 int len0, len1, offset;
2168 gdb_assert (TYPE_LENGTH (ainfo->type)
2169 <= (cinfo->flen + cinfo->xlen));
2171 len0 = TYPE_LENGTH (sinfo.field_type (0));
2172 len1 = TYPE_LENGTH (sinfo.field_type (1));
2173 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2175 gdb_assert (len0 <= cinfo->xlen);
2176 gdb_assert (len1 <= cinfo->flen);
2178 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2179 &cinfo->int_regs, len0, 0))
2180 error (_("failed during argument setup"));
2182 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2185 error (_("failed during argument setup"));
2191 /* Non of the structure flattening cases apply, so we just pass using
2193 ainfo->length = align_up (ainfo->length, cinfo->xlen);
2194 riscv_call_arg_scalar_int (ainfo, cinfo);
2197 /* Assign a location to call (or return) argument AINFO, the location is
2198 selected from CINFO which holds information about what call argument
2199 locations are available for use next. The TYPE is the type of the
2200 argument being passed, this information is recorded into AINFO (along
2201 with some additional information derived from the type). IS_UNNAMED
2202 is true if this is an unnamed (stdarg) argument, this info is also
2203 recorded into AINFO.
2205 After assigning a location to AINFO, CINFO will have been updated. */
2208 riscv_arg_location (struct gdbarch *gdbarch,
2209 struct riscv_arg_info *ainfo,
2210 struct riscv_call_info *cinfo,
2211 struct type *type, bool is_unnamed)
2214 ainfo->length = TYPE_LENGTH (ainfo->type);
2215 ainfo->align = riscv_type_alignment (ainfo->type);
2216 ainfo->is_unnamed = is_unnamed;
2217 ainfo->contents = nullptr;
2219 switch (TYPE_CODE (ainfo->type))
2222 case TYPE_CODE_BOOL:
2223 case TYPE_CODE_CHAR:
2224 case TYPE_CODE_RANGE:
2225 case TYPE_CODE_ENUM:
2227 if (ainfo->length <= cinfo->xlen)
2229 ainfo->type = builtin_type (gdbarch)->builtin_long;
2230 ainfo->length = cinfo->xlen;
2232 else if (ainfo->length <= (2 * cinfo->xlen))
2234 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2235 ainfo->length = 2 * cinfo->xlen;
2238 /* Recalculate the alignment requirement. */
2239 ainfo->align = riscv_type_alignment (ainfo->type);
2240 riscv_call_arg_scalar_int (ainfo, cinfo);
2244 riscv_call_arg_scalar_float (ainfo, cinfo);
2247 case TYPE_CODE_COMPLEX:
2248 riscv_call_arg_complex_float (ainfo, cinfo);
2251 case TYPE_CODE_STRUCT:
2252 riscv_call_arg_struct (ainfo, cinfo);
2256 riscv_call_arg_scalar_int (ainfo, cinfo);
2261 /* Used for printing debug information about the call argument location in
2262 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2263 addresses for the location of pass-by-reference and
2264 arguments-on-the-stack memory areas. */
2267 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2268 struct riscv_arg_info *info,
2269 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2271 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2272 TYPE_SAFE_NAME (info->type), info->length, info->align);
2273 switch (info->argloc[0].loc_type)
2275 case riscv_arg_info::location::in_reg:
2277 (stream, ", register %s",
2278 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2279 if (info->argloc[0].c_length < info->length)
2281 switch (info->argloc[1].loc_type)
2283 case riscv_arg_info::location::in_reg:
2285 (stream, ", register %s",
2286 gdbarch_register_name (gdbarch,
2287 info->argloc[1].loc_data.regno));
2290 case riscv_arg_info::location::on_stack:
2291 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2292 info->argloc[1].loc_data.offset);
2295 case riscv_arg_info::location::by_ref:
2297 /* The second location should never be a reference, any
2298 argument being passed by reference just places its address
2299 in the first location and is done. */
2300 error (_("invalid argument location"));
2304 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2305 fprintf_unfiltered (stream, " (offset 0x%x)",
2306 info->argloc[1].c_offset);
2310 case riscv_arg_info::location::on_stack:
2311 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2312 info->argloc[0].loc_data.offset);
2315 case riscv_arg_info::location::by_ref:
2317 (stream, ", by reference, data at offset 0x%x (%s)",
2318 info->argloc[0].loc_data.offset,
2319 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2320 if (info->argloc[1].loc_type
2321 == riscv_arg_info::location::in_reg)
2323 (stream, ", address in register %s",
2324 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2327 gdb_assert (info->argloc[1].loc_type
2328 == riscv_arg_info::location::on_stack);
2330 (stream, ", address on stack at offset 0x%x (%s)",
2331 info->argloc[1].loc_data.offset,
2332 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2337 gdb_assert_not_reached (_("unknown argument location type"));
2341 /* Implement the push dummy call gdbarch callback. */
2344 riscv_push_dummy_call (struct gdbarch *gdbarch,
2345 struct value *function,
2346 struct regcache *regcache,
2349 struct value **args,
2351 function_call_return_method return_method,
2352 CORE_ADDR struct_addr)
2355 CORE_ADDR sp_args, sp_refs;
2356 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2358 struct riscv_arg_info *arg_info =
2359 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2361 struct riscv_call_info call_info (gdbarch);
2365 struct type *ftype = check_typedef (value_type (function));
2367 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
2368 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
2370 /* We'll use register $a0 if we're returning a struct. */
2371 if (return_method == return_method_struct)
2372 ++call_info.int_regs.next_regnum;
2374 for (i = 0; i < nargs; ++i)
2376 struct value *arg_value;
2377 struct type *arg_type;
2378 struct riscv_arg_info *info = &arg_info[i];
2380 arg_value = args[i];
2381 arg_type = check_typedef (value_type (arg_value));
2383 riscv_arg_location (gdbarch, info, &call_info, arg_type,
2384 TYPE_VARARGS (ftype) && i >= TYPE_NFIELDS (ftype));
2386 if (info->type != arg_type)
2387 arg_value = value_cast (info->type, arg_value);
2388 info->contents = value_contents (arg_value);
2391 /* Adjust the stack pointer and align it. */
2392 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2393 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2395 if (riscv_debug_infcall > 0)
2397 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2398 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2399 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2400 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2401 call_info.xlen, call_info.flen);
2402 if (return_method == return_method_struct)
2403 fprintf_unfiltered (gdb_stdlog,
2404 "[*] struct return pointer in register $A0\n");
2405 for (i = 0; i < nargs; ++i)
2407 struct riscv_arg_info *info = &arg_info [i];
2409 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2410 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2411 fprintf_unfiltered (gdb_stdlog, "\n");
2413 if (call_info.memory.arg_offset > 0
2414 || call_info.memory.ref_offset > 0)
2416 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2417 core_addr_to_string (osp));
2418 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2419 call_info.memory.arg_offset);
2420 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2421 call_info.memory.ref_offset);
2422 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2423 core_addr_to_string_nz (osp - sp));
2427 /* Now load the argument into registers, or onto the stack. */
2429 if (return_method == return_method_struct)
2431 gdb_byte buf[sizeof (LONGEST)];
2433 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2434 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2437 for (i = 0; i < nargs; ++i)
2440 int second_arg_length = 0;
2441 const gdb_byte *second_arg_data;
2442 struct riscv_arg_info *info = &arg_info [i];
2444 gdb_assert (info->length > 0);
2446 switch (info->argloc[0].loc_type)
2448 case riscv_arg_info::location::in_reg:
2450 gdb_byte tmp [sizeof (ULONGEST)];
2452 gdb_assert (info->argloc[0].c_length <= info->length);
2453 /* FP values in FP registers must be NaN-boxed. */
2454 if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno)
2455 && info->argloc[0].c_length < call_info.flen)
2456 memset (tmp, -1, sizeof (tmp));
2458 memset (tmp, 0, sizeof (tmp));
2459 memcpy (tmp, info->contents, info->argloc[0].c_length);
2460 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2462 ((info->argloc[0].c_length < info->length)
2463 ? info->argloc[1].c_length : 0);
2464 second_arg_data = info->contents + info->argloc[1].c_offset;
2468 case riscv_arg_info::location::on_stack:
2469 dst = sp_args + info->argloc[0].loc_data.offset;
2470 write_memory (dst, info->contents, info->length);
2471 second_arg_length = 0;
2474 case riscv_arg_info::location::by_ref:
2475 dst = sp_refs + info->argloc[0].loc_data.offset;
2476 write_memory (dst, info->contents, info->length);
2478 second_arg_length = call_info.xlen;
2479 second_arg_data = (gdb_byte *) &dst;
2483 gdb_assert_not_reached (_("unknown argument location type"));
2486 if (second_arg_length > 0)
2488 switch (info->argloc[1].loc_type)
2490 case riscv_arg_info::location::in_reg:
2492 gdb_byte tmp [sizeof (ULONGEST)];
2494 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2495 && second_arg_length <= call_info.flen)
2496 || second_arg_length <= call_info.xlen);
2497 /* FP values in FP registers must be NaN-boxed. */
2498 if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2499 && second_arg_length < call_info.flen)
2500 memset (tmp, -1, sizeof (tmp));
2502 memset (tmp, 0, sizeof (tmp));
2503 memcpy (tmp, second_arg_data, second_arg_length);
2504 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2508 case riscv_arg_info::location::on_stack:
2512 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2513 write_memory (arg_addr, second_arg_data, second_arg_length);
2517 case riscv_arg_info::location::by_ref:
2519 /* The second location should never be a reference, any
2520 argument being passed by reference just places its address
2521 in the first location and is done. */
2522 error (_("invalid argument location"));
2528 /* Set the dummy return value to bp_addr.
2529 A dummy breakpoint will be setup to execute the call. */
2531 if (riscv_debug_infcall > 0)
2532 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2533 core_addr_to_string (bp_addr));
2534 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2536 /* Finally, update the stack pointer. */
2538 if (riscv_debug_infcall > 0)
2539 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2540 core_addr_to_string (sp));
2541 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2546 /* Implement the return_value gdbarch method. */
2548 static enum return_value_convention
2549 riscv_return_value (struct gdbarch *gdbarch,
2550 struct value *function,
2552 struct regcache *regcache,
2554 const gdb_byte *writebuf)
2556 struct riscv_call_info call_info (gdbarch);
2557 struct riscv_arg_info info;
2558 struct type *arg_type;
2560 arg_type = check_typedef (type);
2561 riscv_arg_location (gdbarch, &info, &call_info, arg_type, false);
2563 if (riscv_debug_infcall > 0)
2565 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2566 fprintf_unfiltered (gdb_stdlog, "[R] ");
2567 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2568 fprintf_unfiltered (gdb_stdlog, "\n");
2571 if (readbuf != nullptr || writebuf != nullptr)
2575 switch (info.argloc[0].loc_type)
2577 /* Return value in register(s). */
2578 case riscv_arg_info::location::in_reg:
2580 regnum = info.argloc[0].loc_data.regno;
2583 regcache->cooked_read (regnum, readbuf);
2586 regcache->cooked_write (regnum, writebuf);
2588 /* A return value in register can have a second part in a
2590 if (info.argloc[0].c_length < info.length)
2592 switch (info.argloc[1].loc_type)
2594 case riscv_arg_info::location::in_reg:
2595 regnum = info.argloc[1].loc_data.regno;
2599 readbuf += info.argloc[1].c_offset;
2600 regcache->cooked_read (regnum, readbuf);
2605 writebuf += info.argloc[1].c_offset;
2606 regcache->cooked_write (regnum, writebuf);
2610 case riscv_arg_info::location::by_ref:
2611 case riscv_arg_info::location::on_stack:
2613 error (_("invalid argument location"));
2620 /* Return value by reference will have its address in A0. */
2621 case riscv_arg_info::location::by_ref:
2625 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2627 if (readbuf != nullptr)
2628 read_memory (addr, readbuf, info.length);
2629 if (writebuf != nullptr)
2630 write_memory (addr, writebuf, info.length);
2634 case riscv_arg_info::location::on_stack:
2636 error (_("invalid argument location"));
2641 switch (info.argloc[0].loc_type)
2643 case riscv_arg_info::location::in_reg:
2644 return RETURN_VALUE_REGISTER_CONVENTION;
2645 case riscv_arg_info::location::by_ref:
2646 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2647 case riscv_arg_info::location::on_stack:
2649 error (_("invalid argument location"));
2653 /* Implement the frame_align gdbarch method. */
2656 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2658 return align_down (addr, 16);
2661 /* Implement the unwind_pc gdbarch method. */
2664 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2666 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2669 /* Implement the unwind_sp gdbarch method. */
2672 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2674 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2677 /* Implement the dummy_id gdbarch method. */
2679 static struct frame_id
2680 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2682 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2683 get_frame_pc (this_frame));
2686 /* Generate, or return the cached frame cache for the RiscV frame
2689 static struct riscv_unwind_cache *
2690 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2692 CORE_ADDR pc, start_addr;
2693 struct riscv_unwind_cache *cache;
2694 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2697 if ((*this_cache) != NULL)
2698 return (struct riscv_unwind_cache *) *this_cache;
2700 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2701 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2702 (*this_cache) = cache;
2704 /* Scan the prologue, filling in the cache. */
2705 start_addr = get_frame_func (this_frame);
2706 pc = get_frame_pc (this_frame);
2707 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2709 /* We can now calculate the frame base address. */
2711 = (get_frame_register_signed (this_frame, cache->frame_base_reg)
2712 + cache->frame_base_offset);
2713 if (riscv_debug_unwinder)
2714 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2715 core_addr_to_string (cache->frame_base),
2716 gdbarch_register_name (gdbarch,
2717 cache->frame_base_reg),
2718 cache->frame_base_offset);
2720 /* The prologue scanner sets the address of registers stored to the stack
2721 as the offset of that register from the frame base. The prologue
2722 scanner doesn't know the actual frame base value, and so is unable to
2723 compute the exact address. We do now know the frame base value, so
2724 update the address of registers stored to the stack. */
2725 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2726 for (regno = 0; regno < numregs; ++regno)
2728 if (trad_frame_addr_p (cache->regs, regno))
2729 cache->regs[regno].addr += cache->frame_base;
2732 /* The previous $pc can be found wherever the $ra value can be found.
2733 The previous $ra value is gone, this would have been stored be the
2734 previous frame if required. */
2735 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2736 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2738 /* Build the frame id. */
2739 cache->this_id = frame_id_build (cache->frame_base, start_addr);
2741 /* The previous $sp value is the frame base value. */
2742 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2748 /* Implement the this_id callback for RiscV frame unwinder. */
2751 riscv_frame_this_id (struct frame_info *this_frame,
2752 void **prologue_cache,
2753 struct frame_id *this_id)
2755 struct riscv_unwind_cache *cache;
2759 cache = riscv_frame_cache (this_frame, prologue_cache);
2760 *this_id = cache->this_id;
2762 CATCH (ex, RETURN_MASK_ERROR)
2764 /* Ignore errors, this leaves the frame id as the predefined outer
2765 frame id which terminates the backtrace at this point. */
2770 /* Implement the prev_register callback for RiscV frame unwinder. */
2772 static struct value *
2773 riscv_frame_prev_register (struct frame_info *this_frame,
2774 void **prologue_cache,
2777 struct riscv_unwind_cache *cache;
2779 cache = riscv_frame_cache (this_frame, prologue_cache);
2780 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
2783 /* Structure defining the RiscV normal frame unwind functions. Since we
2784 are the fallback unwinder (DWARF unwinder is used first), we use the
2785 default frame sniffer, which always accepts the frame. */
2787 static const struct frame_unwind riscv_frame_unwind =
2789 /*.type =*/ NORMAL_FRAME,
2790 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2791 /*.this_id =*/ riscv_frame_this_id,
2792 /*.prev_register =*/ riscv_frame_prev_register,
2793 /*.unwind_data =*/ NULL,
2794 /*.sniffer =*/ default_frame_sniffer,
2795 /*.dealloc_cache =*/ NULL,
2796 /*.prev_arch =*/ NULL,
2799 /* Extract a set of required target features out of INFO, specifically the
2800 bfd being executed is examined to see what target features it requires.
2801 IF there is no current bfd, or the bfd doesn't indicate any useful
2802 features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
2804 static struct riscv_gdbarch_features
2805 riscv_features_from_gdbarch_info (const struct gdbarch_info info)
2807 struct riscv_gdbarch_features features;
2809 /* Now try to improve on the defaults by looking at the binary we are
2810 going to execute. We assume the user knows what they are doing and
2811 that the target will match the binary. Remember, this code path is
2812 only used at all if the target hasn't given us a description, so this
2813 is really a last ditched effort to do something sane before giving
2815 if (info.abfd != NULL
2816 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2818 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2819 int e_flags = elf_elfheader (info.abfd)->e_flags;
2821 if (eclass == ELFCLASS32)
2823 else if (eclass == ELFCLASS64)
2826 internal_error (__FILE__, __LINE__,
2827 _("unknown ELF header class %d"), eclass);
2829 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2832 features.hw_float_abi = true;
2834 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2837 features.hw_float_abi = true;
2842 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2844 if (binfo->bits_per_word == 32)
2846 else if (binfo->bits_per_word == 64)
2849 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2850 binfo->bits_per_word);
2856 /* Find a suitable default target description. Use the contents of INFO,
2857 specifically the bfd object being executed, to guide the selection of a
2858 suitable default target description. */
2860 static const struct target_desc *
2861 riscv_find_default_target_description (const struct gdbarch_info info)
2863 /* Extract desired feature set from INFO. */
2864 struct riscv_gdbarch_features features
2865 = riscv_features_from_gdbarch_info (info);
2867 /* If the XLEN field is still 0 then we got nothing useful from INFO. In
2868 this case we fall back to a minimal useful target, 8-byte x-registers,
2869 with no floating point. */
2870 if (features.xlen == 0)
2873 /* Now build a target description based on the feature set. */
2874 return riscv_create_target_description (features);
2877 /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
2878 is updated with the register numbers for each register as listed in
2879 REG_SET. If any register marked as required in REG_SET is not found in
2880 FEATURE then this function returns false, otherwise, it returns true. */
2883 riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
2884 const struct tdesc_feature *feature,
2885 const struct riscv_register_feature *reg_set)
2887 for (const auto ® : reg_set->registers)
2891 for (const char *name : reg.names)
2894 tdesc_numbered_register (feature, tdesc_data, reg.regnum, name);
2900 if (!found && reg.required_p)
2907 /* Add all the expected register sets into GDBARCH. */
2910 riscv_add_reggroups (struct gdbarch *gdbarch)
2912 /* Add predefined register groups. */
2913 reggroup_add (gdbarch, all_reggroup);
2914 reggroup_add (gdbarch, save_reggroup);
2915 reggroup_add (gdbarch, restore_reggroup);
2916 reggroup_add (gdbarch, system_reggroup);
2917 reggroup_add (gdbarch, vector_reggroup);
2918 reggroup_add (gdbarch, general_reggroup);
2919 reggroup_add (gdbarch, float_reggroup);
2921 /* Add RISC-V specific register groups. */
2922 reggroup_add (gdbarch, csr_reggroup);
2925 /* Create register aliases for all the alternative names that exist for
2926 registers in REG_SET. */
2929 riscv_setup_register_aliases (struct gdbarch *gdbarch,
2930 const struct riscv_register_feature *reg_set)
2932 for (auto ® : reg_set->registers)
2934 /* The first item in the names list is the preferred name for the
2935 register, this is what RISCV_REGISTER_NAME returns, and so we
2936 don't need to create an alias with that name here. */
2937 for (int i = 1; i < reg.names.size (); ++i)
2938 user_reg_add (gdbarch, reg.names[i], value_of_riscv_user_reg,
2943 /* Initialize the current architecture based on INFO. If possible,
2944 re-use an architecture from ARCHES, which is a list of
2945 architectures already created during this debugging session.
2947 Called e.g. at program startup, when reading a core file, and when
2948 reading a binary file. */
2950 static struct gdbarch *
2951 riscv_gdbarch_init (struct gdbarch_info info,
2952 struct gdbarch_list *arches)
2954 struct gdbarch *gdbarch;
2955 struct gdbarch_tdep *tdep;
2956 struct riscv_gdbarch_features features;
2957 const struct target_desc *tdesc = info.target_desc;
2959 /* Ensure we always have a target description. */
2960 if (!tdesc_has_registers (tdesc))
2961 tdesc = riscv_find_default_target_description (info);
2964 if (riscv_debug_gdbarch)
2965 fprintf_unfiltered (gdb_stdlog, "Have got a target description\n");
2967 const struct tdesc_feature *feature_cpu
2968 = tdesc_find_feature (tdesc, riscv_xreg_feature.name);
2969 const struct tdesc_feature *feature_fpu
2970 = tdesc_find_feature (tdesc, riscv_freg_feature.name);
2971 const struct tdesc_feature *feature_virtual
2972 = tdesc_find_feature (tdesc, riscv_virtual_feature.name);
2973 const struct tdesc_feature *feature_csr
2974 = tdesc_find_feature (tdesc, riscv_csr_feature.name);
2976 if (feature_cpu == NULL)
2979 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
2981 bool valid_p = riscv_check_tdesc_feature (tdesc_data,
2983 &riscv_xreg_feature);
2986 /* Check that all of the core cpu registers have the same bitsize. */
2987 int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc");
2989 for (auto &tdesc_reg : feature_cpu->registers)
2990 valid_p &= (tdesc_reg->bitsize == xlen_bitsize);
2992 if (riscv_debug_gdbarch)
2995 "From target-description, xlen = %d\n", xlen_bitsize);
2997 features.xlen = (xlen_bitsize / 8);
3000 if (feature_fpu != NULL)
3002 valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
3003 &riscv_freg_feature);
3005 int bitsize = tdesc_register_bitsize (feature_fpu, "ft0");
3006 features.flen = (bitsize / 8);
3008 if (riscv_debug_gdbarch)
3011 "From target-description, flen = %d\n", bitsize);
3017 if (riscv_debug_gdbarch)
3020 "No FPU in target-description, assume soft-float ABI\n");
3023 if (feature_virtual)
3024 riscv_check_tdesc_feature (tdesc_data, feature_virtual,
3025 &riscv_virtual_feature);
3028 riscv_check_tdesc_feature (tdesc_data, feature_csr,
3029 &riscv_csr_feature);
3033 if (riscv_debug_gdbarch)
3034 fprintf_unfiltered (gdb_stdlog, "Target description is not valid\n");
3035 tdesc_data_cleanup (tdesc_data);
3039 /* Have a look at what the supplied (if any) bfd object requires of the
3040 target, then check that this matches with what the target is
3042 struct riscv_gdbarch_features info_features
3043 = riscv_features_from_gdbarch_info (info);
3044 if (info_features.xlen != 0 && info_features.xlen != features.xlen)
3045 error (_("bfd requires xlen %d, but target has xlen %d"),
3046 info_features.xlen, features.xlen);
3047 if (info_features.flen != 0 && info_features.flen != features.flen)
3048 error (_("bfd requires flen %d, but target has flen %d"),
3049 info_features.flen, features.flen);
3051 /* If the xlen from INFO_FEATURES is 0 then this indicates either there
3052 is no bfd object, or nothing useful could be extracted from it, in
3053 this case we enable hardware float abi if the target has floating
3056 If the xlen from INFO_FEATURES is not 0, and the flen in
3057 INFO_FEATURES is also not 0, then this indicates that the supplied
3058 bfd does require hardware floating point abi. */
3059 if (info_features.xlen == 0 || info_features.flen != 0)
3060 features.hw_float_abi = (features.flen > 0);
3062 /* Find a candidate among the list of pre-declared architectures. */
3063 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3065 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3067 /* Check that the feature set of the ARCHES matches the feature set
3068 we are looking for. If it doesn't then we can't reuse this
3070 struct gdbarch_tdep *other_tdep = gdbarch_tdep (arches->gdbarch);
3072 if (other_tdep->features != features)
3080 tdesc_data_cleanup (tdesc_data);
3081 return arches->gdbarch;
3084 /* None found, so create a new architecture from the information provided. */
3085 tdep = new (struct gdbarch_tdep);
3086 gdbarch = gdbarch_alloc (&info, tdep);
3087 tdep->features = features;
3089 /* Target data types. */
3090 set_gdbarch_short_bit (gdbarch, 16);
3091 set_gdbarch_int_bit (gdbarch, 32);
3092 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
3093 set_gdbarch_long_long_bit (gdbarch, 64);
3094 set_gdbarch_float_bit (gdbarch, 32);
3095 set_gdbarch_double_bit (gdbarch, 64);
3096 set_gdbarch_long_double_bit (gdbarch, 128);
3097 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
3098 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
3099 set_gdbarch_char_signed (gdbarch, 0);
3101 /* Information about the target architecture. */
3102 set_gdbarch_return_value (gdbarch, riscv_return_value);
3103 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
3104 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
3105 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3107 /* Functions to analyze frames. */
3108 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
3109 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3110 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
3112 /* Functions to access frame data. */
3113 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
3114 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
3116 /* Functions handling dummy frames. */
3117 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
3118 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
3119 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
3120 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
3122 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3124 dwarf2_append_unwinders (gdbarch);
3125 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
3127 /* Register architecture. */
3128 riscv_add_reggroups (gdbarch);
3130 /* We reserve all possible register numbers for the known registers.
3131 This means the target description mechanism will add any target
3132 specific registers after this number. This helps make debugging GDB
3133 just a little easier. */
3134 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
3136 /* We don't have to provide the count of 0 here (its the default) but
3137 include this line to make it explicit that, right now, we don't have
3138 any pseudo registers on RISC-V. */
3139 set_gdbarch_num_pseudo_regs (gdbarch, 0);
3141 /* Some specific register numbers GDB likes to know about. */
3142 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
3143 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
3145 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
3147 /* Finalise the target description registers. */
3148 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3150 /* Override the register type callback setup by the target description
3151 mechanism. This allows us to provide special type for floating point
3153 set_gdbarch_register_type (gdbarch, riscv_register_type);
3155 /* Override the register name callback setup by the target description
3156 mechanism. This allows us to force our preferred names for the
3157 registers, no matter what the target description called them. */
3158 set_gdbarch_register_name (gdbarch, riscv_register_name);
3160 /* Override the register group callback setup by the target description
3161 mechanism. This allows us to force registers into the groups we
3162 want, ignoring what the target tells us. */
3163 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
3165 /* Create register aliases for alternative register names. */
3166 riscv_setup_register_aliases (gdbarch, &riscv_xreg_feature);
3167 if (riscv_has_fp_regs (gdbarch))
3168 riscv_setup_register_aliases (gdbarch, &riscv_freg_feature);
3169 riscv_setup_register_aliases (gdbarch, &riscv_csr_feature);
3171 /* Hook in OS ABI-specific overrides, if they have been registered. */
3172 gdbarch_init_osabi (info, gdbarch);
3177 /* This decodes the current instruction and determines the address of the
3178 next instruction. */
3181 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
3183 struct gdbarch *gdbarch = regcache->arch ();
3184 struct riscv_insn insn;
3187 insn.decode (gdbarch, pc);
3188 next_pc = pc + insn.length ();
3190 if (insn.opcode () == riscv_insn::JAL)
3191 next_pc = pc + insn.imm_signed ();
3192 else if (insn.opcode () == riscv_insn::JALR)
3195 regcache->cooked_read (insn.rs1 (), &source);
3196 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
3198 else if (insn.opcode () == riscv_insn::BEQ)
3201 regcache->cooked_read (insn.rs1 (), &src1);
3202 regcache->cooked_read (insn.rs2 (), &src2);
3204 next_pc = pc + insn.imm_signed ();
3206 else if (insn.opcode () == riscv_insn::BNE)
3209 regcache->cooked_read (insn.rs1 (), &src1);
3210 regcache->cooked_read (insn.rs2 (), &src2);
3212 next_pc = pc + insn.imm_signed ();
3214 else if (insn.opcode () == riscv_insn::BLT)
3217 regcache->cooked_read (insn.rs1 (), &src1);
3218 regcache->cooked_read (insn.rs2 (), &src2);
3220 next_pc = pc + insn.imm_signed ();
3222 else if (insn.opcode () == riscv_insn::BGE)
3225 regcache->cooked_read (insn.rs1 (), &src1);
3226 regcache->cooked_read (insn.rs2 (), &src2);
3228 next_pc = pc + insn.imm_signed ();
3230 else if (insn.opcode () == riscv_insn::BLTU)
3232 ULONGEST src1, src2;
3233 regcache->cooked_read (insn.rs1 (), &src1);
3234 regcache->cooked_read (insn.rs2 (), &src2);
3236 next_pc = pc + insn.imm_signed ();
3238 else if (insn.opcode () == riscv_insn::BGEU)
3240 ULONGEST src1, src2;
3241 regcache->cooked_read (insn.rs1 (), &src1);
3242 regcache->cooked_read (insn.rs2 (), &src2);
3244 next_pc = pc + insn.imm_signed ();
3250 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3251 for the end of the sequence and put the breakpoint there. */
3254 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
3257 struct gdbarch *gdbarch = regcache->arch ();
3258 struct riscv_insn insn;
3259 CORE_ADDR cur_step_pc = pc;
3260 CORE_ADDR last_addr = 0;
3262 /* First instruction has to be a load reserved. */
3263 insn.decode (gdbarch, cur_step_pc);
3264 if (insn.opcode () != riscv_insn::LR)
3266 cur_step_pc = cur_step_pc + insn.length ();
3268 /* Next instruction should be branch to exit. */
3269 insn.decode (gdbarch, cur_step_pc);
3270 if (insn.opcode () != riscv_insn::BNE)
3272 last_addr = cur_step_pc + insn.imm_signed ();
3273 cur_step_pc = cur_step_pc + insn.length ();
3275 /* Next instruction should be store conditional. */
3276 insn.decode (gdbarch, cur_step_pc);
3277 if (insn.opcode () != riscv_insn::SC)
3279 cur_step_pc = cur_step_pc + insn.length ();
3281 /* Next instruction should be branch to start. */
3282 insn.decode (gdbarch, cur_step_pc);
3283 if (insn.opcode () != riscv_insn::BNE)
3285 if (pc != (cur_step_pc + insn.imm_signed ()))
3287 cur_step_pc = cur_step_pc + insn.length ();
3289 /* We should now be at the end of the sequence. */
3290 if (cur_step_pc != last_addr)
3293 *next_pc = cur_step_pc;
3297 /* This is called just before we want to resume the inferior, if we want to
3298 single-step it but there is no hardware or kernel single-step support. We
3299 find the target of the coming instruction and breakpoint it. */
3301 std::vector<CORE_ADDR>
3302 riscv_software_single_step (struct regcache *regcache)
3304 CORE_ADDR pc, next_pc;
3306 pc = regcache_read_pc (regcache);
3308 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
3311 next_pc = riscv_next_pc (regcache, pc);
3316 /* Create RISC-V specific reggroups. */
3319 riscv_init_reggroups ()
3321 csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
3325 _initialize_riscv_tdep (void)
3327 riscv_create_csr_aliases ();
3328 riscv_init_reggroups ();
3330 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
3332 /* Add root prefix command for all "set debug riscv" and "show debug
3334 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
3335 _("RISC-V specific debug commands."),
3336 &setdebugriscvcmdlist, "set debug riscv ", 0,
3339 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
3340 _("RISC-V specific debug commands."),
3341 &showdebugriscvcmdlist, "show debug riscv ", 0,
3344 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
3345 &riscv_debug_breakpoints, _("\
3346 Set riscv breakpoint debugging."), _("\
3347 Show riscv breakpoint debugging."), _("\
3348 When non-zero, print debugging information for the riscv specific parts\n\
3349 of the breakpoint mechanism."),
3351 show_riscv_debug_variable,
3352 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3354 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
3355 &riscv_debug_infcall, _("\
3356 Set riscv inferior call debugging."), _("\
3357 Show riscv inferior call debugging."), _("\
3358 When non-zero, print debugging information for the riscv specific parts\n\
3359 of the inferior call mechanism."),
3361 show_riscv_debug_variable,
3362 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3364 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
3365 &riscv_debug_unwinder, _("\
3366 Set riscv stack unwinding debugging."), _("\
3367 Show riscv stack unwinding debugging."), _("\
3368 When non-zero, print debugging information for the riscv specific parts\n\
3369 of the stack unwinding mechanism."),
3371 show_riscv_debug_variable,
3372 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3374 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance,
3375 &riscv_debug_gdbarch, _("\
3376 Set riscv gdbarch initialisation debugging."), _("\
3377 Show riscv gdbarch initialisation debugging."), _("\
3378 When non-zero, print debugging information for the riscv gdbarch\n\
3379 initialisation process."),
3381 show_riscv_debug_variable,
3382 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3384 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3385 add_prefix_cmd ("riscv", no_class, set_riscv_command,
3386 _("RISC-V specific commands."),
3387 &setriscvcmdlist, "set riscv ", 0, &setlist);
3389 add_prefix_cmd ("riscv", no_class, show_riscv_command,
3390 _("RISC-V specific commands."),
3391 &showriscvcmdlist, "show riscv ", 0, &showlist);
3394 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
3395 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
3396 &use_compressed_breakpoints,
3398 Set debugger's use of compressed breakpoints."), _(" \
3399 Show debugger's use of compressed breakpoints."), _("\
3400 Debugging compressed code requires compressed breakpoints to be used. If\n\
3401 left to 'auto' then gdb will use them if the existing instruction is a\n\
3402 compressed instruction. If that doesn't give the correct behavior, then\n\
3403 this option can be used."),
3405 show_use_compressed_breakpoints,