1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
59 /* The stack must be 16-byte aligned. */
60 #define SP_ALIGNMENT 16
62 /* Forward declarations. */
63 static bool riscv_has_feature (struct gdbarch *gdbarch, char feature);
65 /* Define a series of is_XXX_insn functions to check if the value INSN
66 is an instance of instruction XXX. */
67 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
68 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
70 return (insn & INSN_MASK) == INSN_MATCH; \
72 #include "opcode/riscv-opc.h"
75 /* Cached information about a frame. */
77 struct riscv_unwind_cache
79 /* The register from which we can calculate the frame base. This is
80 usually $sp or $fp. */
83 /* The offset from the current value in register FRAME_BASE_REG to the
84 actual frame base address. */
85 int frame_base_offset;
87 /* Information about previous register values. */
88 struct trad_frame_saved_reg *regs;
90 /* The id for this frame. */
91 struct frame_id this_id;
93 /* The base (stack) address for this frame. This is the stack pointer
94 value on entry to this frame before any adjustments are made. */
98 /* The preferred register names for all the general purpose and floating
99 point registers. These are what GDB will use when referencing a
102 static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
104 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1",
105 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4",
106 "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
108 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
109 "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3",
110 "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9",
114 /* Map alternative register names onto their GDB register number. */
116 struct riscv_register_alias
118 /* The register alias. Usually more descriptive than the
119 architectural name of the register. */
122 /* The GDB register number. */
126 /* Table of register aliases. */
128 static const struct riscv_register_alias riscv_register_aliases[] =
130 /* Aliases for general purpose registers. These are the architectural
131 names, as GDB uses the more user friendly names by default. */
132 { "x0", (RISCV_ZERO_REGNUM + 0) },
133 { "x1", (RISCV_ZERO_REGNUM + 1) },
134 { "x2", (RISCV_ZERO_REGNUM + 2) },
135 { "x3", (RISCV_ZERO_REGNUM + 3) },
136 { "x4", (RISCV_ZERO_REGNUM + 4) },
137 { "x5", (RISCV_ZERO_REGNUM + 5) },
138 { "x6", (RISCV_ZERO_REGNUM + 6) },
139 { "x7", (RISCV_ZERO_REGNUM + 7) },
140 { "x8", (RISCV_ZERO_REGNUM + 8) },
141 { "s0", (RISCV_ZERO_REGNUM + 8) }, /* fp, s0, and x8 are all aliases. */
142 { "x9", (RISCV_ZERO_REGNUM + 9) },
143 { "x10", (RISCV_ZERO_REGNUM + 10) },
144 { "x11", (RISCV_ZERO_REGNUM + 11) },
145 { "x12", (RISCV_ZERO_REGNUM + 12) },
146 { "x13", (RISCV_ZERO_REGNUM + 13) },
147 { "x14", (RISCV_ZERO_REGNUM + 14) },
148 { "x15", (RISCV_ZERO_REGNUM + 15) },
149 { "x16", (RISCV_ZERO_REGNUM + 16) },
150 { "x17", (RISCV_ZERO_REGNUM + 17) },
151 { "x18", (RISCV_ZERO_REGNUM + 18) },
152 { "x19", (RISCV_ZERO_REGNUM + 19) },
153 { "x20", (RISCV_ZERO_REGNUM + 20) },
154 { "x21", (RISCV_ZERO_REGNUM + 21) },
155 { "x22", (RISCV_ZERO_REGNUM + 22) },
156 { "x23", (RISCV_ZERO_REGNUM + 23) },
157 { "x24", (RISCV_ZERO_REGNUM + 24) },
158 { "x25", (RISCV_ZERO_REGNUM + 25) },
159 { "x26", (RISCV_ZERO_REGNUM + 26) },
160 { "x27", (RISCV_ZERO_REGNUM + 27) },
161 { "x28", (RISCV_ZERO_REGNUM + 28) },
162 { "x29", (RISCV_ZERO_REGNUM + 29) },
163 { "x30", (RISCV_ZERO_REGNUM + 30) },
164 { "x31", (RISCV_ZERO_REGNUM + 31) },
166 /* Aliases for the floating-point registers. These are the architectural
167 names as GDB uses the more user friendly names by default. */
168 { "f0", (RISCV_FIRST_FP_REGNUM + 0) },
169 { "f1", (RISCV_FIRST_FP_REGNUM + 1) },
170 { "f2", (RISCV_FIRST_FP_REGNUM + 2) },
171 { "f3", (RISCV_FIRST_FP_REGNUM + 3) },
172 { "f4", (RISCV_FIRST_FP_REGNUM + 4) },
173 { "f5", (RISCV_FIRST_FP_REGNUM + 5) },
174 { "f6", (RISCV_FIRST_FP_REGNUM + 6) },
175 { "f7", (RISCV_FIRST_FP_REGNUM + 7) },
176 { "f8", (RISCV_FIRST_FP_REGNUM + 8) },
177 { "f9", (RISCV_FIRST_FP_REGNUM + 9) },
178 { "f10", (RISCV_FIRST_FP_REGNUM + 10) },
179 { "f11", (RISCV_FIRST_FP_REGNUM + 11) },
180 { "f12", (RISCV_FIRST_FP_REGNUM + 12) },
181 { "f13", (RISCV_FIRST_FP_REGNUM + 13) },
182 { "f14", (RISCV_FIRST_FP_REGNUM + 14) },
183 { "f15", (RISCV_FIRST_FP_REGNUM + 15) },
184 { "f16", (RISCV_FIRST_FP_REGNUM + 16) },
185 { "f17", (RISCV_FIRST_FP_REGNUM + 17) },
186 { "f18", (RISCV_FIRST_FP_REGNUM + 18) },
187 { "f19", (RISCV_FIRST_FP_REGNUM + 19) },
188 { "f20", (RISCV_FIRST_FP_REGNUM + 20) },
189 { "f21", (RISCV_FIRST_FP_REGNUM + 21) },
190 { "f22", (RISCV_FIRST_FP_REGNUM + 22) },
191 { "f23", (RISCV_FIRST_FP_REGNUM + 23) },
192 { "f24", (RISCV_FIRST_FP_REGNUM + 24) },
193 { "f25", (RISCV_FIRST_FP_REGNUM + 25) },
194 { "f26", (RISCV_FIRST_FP_REGNUM + 26) },
195 { "f27", (RISCV_FIRST_FP_REGNUM + 27) },
196 { "f28", (RISCV_FIRST_FP_REGNUM + 28) },
197 { "f29", (RISCV_FIRST_FP_REGNUM + 29) },
198 { "f30", (RISCV_FIRST_FP_REGNUM + 30) },
199 { "f31", (RISCV_FIRST_FP_REGNUM + 31) },
202 /* Controls whether we place compressed breakpoints or not. When in auto
203 mode GDB tries to determine if the target supports compressed
204 breakpoints, and uses them if it does. */
206 static enum auto_boolean use_compressed_breakpoints;
208 /* The show callback for 'show riscv use-compressed-breakpoints'. */
211 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
212 struct cmd_list_element *c,
215 fprintf_filtered (file,
216 _("Debugger's use of compressed breakpoints is set "
220 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
222 static struct cmd_list_element *setriscvcmdlist = NULL;
223 static struct cmd_list_element *showriscvcmdlist = NULL;
225 /* The show callback for the 'show riscv' prefix command. */
228 show_riscv_command (const char *args, int from_tty)
230 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
233 /* The set callback for the 'set riscv' prefix command. */
236 set_riscv_command (const char *args, int from_tty)
239 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
240 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
243 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
245 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
246 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
248 /* The show callback for the 'show debug riscv' prefix command. */
251 show_debug_riscv_command (const char *args, int from_tty)
253 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
256 /* The set callback for the 'set debug riscv' prefix command. */
259 set_debug_riscv_command (const char *args, int from_tty)
262 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
263 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
266 /* The show callback for all 'show debug riscv VARNAME' variables. */
269 show_riscv_debug_variable (struct ui_file *file, int from_tty,
270 struct cmd_list_element *c,
273 fprintf_filtered (file,
274 _("RiscV debug variable `%s' is set to: %s\n"),
278 /* When this is set to non-zero debugging information about breakpoint
279 kinds will be printed. */
281 static unsigned int riscv_debug_breakpoints = 0;
283 /* When this is set to non-zero debugging information about inferior calls
286 static unsigned int riscv_debug_infcall = 0;
288 /* When this is set to non-zero debugging information about stack unwinding
291 static unsigned int riscv_debug_unwinder = 0;
293 /* Read the MISA register from the target. There are a couple of locations
294 that the register might be found, these are all tried. If the MISA
295 register can't be found at all then the default value of 0 is returned,
296 this is inline with the RISC-V specification. */
299 riscv_read_misa_reg ()
303 if (target_has_registers)
305 /* Old cores might have MISA located at a different offset. */
306 static int misa_regs[] =
307 { RISCV_CSR_MISA_REGNUM, RISCV_CSR_LEGACY_MISA_REGNUM };
309 struct frame_info *frame = get_current_frame ();
311 for (int i = 0; i < ARRAY_SIZE (misa_regs); ++i)
313 bool success = false;
317 value = get_frame_register_unsigned (frame, misa_regs[i]);
320 CATCH (ex, RETURN_MASK_ERROR)
322 /* Ignore errors, it is acceptable for a target to not
323 provide a MISA register, in which case the default value
324 of 0 should be used. */
336 /* Return true if FEATURE is available for the architecture GDBARCH. The
337 FEATURE should be one of the single character feature codes described in
338 the RiscV ISA manual, these are between 'A' and 'Z'. */
341 riscv_has_feature (struct gdbarch *gdbarch, char feature)
343 gdb_assert (feature >= 'A' && feature <= 'Z');
345 uint32_t misa = riscv_read_misa_reg ();
347 misa = gdbarch_tdep (gdbarch)->core_features;
349 return (misa & (1 << (feature - 'A'))) != 0;
352 /* See riscv-tdep.h. */
355 riscv_isa_xlen (struct gdbarch *gdbarch)
357 switch (gdbarch_tdep (gdbarch)->abi.fields.base_len)
360 warning (_("unknown xlen size, assuming 4 bytes"));
371 /* See riscv-tdep.h. */
374 riscv_isa_flen (struct gdbarch *gdbarch)
376 if (riscv_has_feature (gdbarch, 'Q'))
378 else if (riscv_has_feature (gdbarch, 'D'))
380 else if (riscv_has_feature (gdbarch, 'F'))
386 /* Return true if the target for GDBARCH has floating point hardware. */
389 riscv_has_fp_regs (struct gdbarch *gdbarch)
391 return (riscv_isa_flen (gdbarch) > 0);
394 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
397 riscv_has_fp_abi (struct gdbarch *gdbarch)
399 return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0);
402 /* Return true if REGNO is a floating pointer register. */
405 riscv_is_fp_regno_p (int regno)
407 return (regno >= RISCV_FIRST_FP_REGNUM
408 && regno <= RISCV_LAST_FP_REGNUM);
411 /* Implement the breakpoint_kind_from_pc gdbarch method. */
414 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
416 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
420 /* Read the opcode byte to determine the instruction length. */
421 read_code (*pcptr, buf, 1);
423 if (riscv_debug_breakpoints)
426 "Using %s for breakpoint at %s (instruction length %d)\n",
427 riscv_insn_length (buf[0]) == 2 ? "C.EBREAK" : "EBREAK",
428 paddress (gdbarch, *pcptr), riscv_insn_length (buf[0]));
429 if (riscv_insn_length (buf[0]) == 2)
434 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
440 /* Implement the sw_breakpoint_from_kind gdbarch method. */
442 static const gdb_byte *
443 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
445 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
446 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
456 gdb_assert_not_reached (_("unhandled breakpoint kind"));
460 /* Callback function for user_reg_add. */
462 static struct value *
463 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
465 const int *reg_p = (const int *) baton;
466 return value_of_register (*reg_p, frame);
469 /* Implement the register_name gdbarch method. */
472 riscv_register_name (struct gdbarch *gdbarch, int regnum)
474 /* Prefer to use the alias. */
475 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
477 gdb_assert (regnum < ARRAY_SIZE (riscv_gdb_reg_names));
478 return riscv_gdb_reg_names[regnum];
481 /* Check that there's no gap between the set of registers handled above,
482 and the set of registers handled next. */
483 gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM);
485 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
487 #define DECLARE_CSR(NAME,VALUE) \
488 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
492 #include "opcode/riscv-opc.h"
497 xsnprintf (buf, sizeof (buf), "csr%d",
498 regnum - RISCV_FIRST_CSR_REGNUM);
505 if (regnum == RISCV_PRIV_REGNUM)
511 /* Construct a type for 64-bit FP registers. */
514 riscv_fpreg_d_type (struct gdbarch *gdbarch)
516 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
518 if (tdep->riscv_fpreg_d_type == nullptr)
520 const struct builtin_type *bt = builtin_type (gdbarch);
522 /* The type we're building is this: */
524 union __gdb_builtin_type_fpreg_d
533 t = arch_composite_type (gdbarch,
534 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
535 append_composite_type_field (t, "float", bt->builtin_float);
536 append_composite_type_field (t, "double", bt->builtin_double);
538 TYPE_NAME (t) = "builtin_type_fpreg_d";
539 tdep->riscv_fpreg_d_type = t;
542 return tdep->riscv_fpreg_d_type;
545 /* Construct a type for 128-bit FP registers. */
548 riscv_fpreg_q_type (struct gdbarch *gdbarch)
550 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
552 if (tdep->riscv_fpreg_q_type == nullptr)
554 const struct builtin_type *bt = builtin_type (gdbarch);
556 /* The type we're building is this: */
558 union __gdb_builtin_type_fpreg_d
568 t = arch_composite_type (gdbarch,
569 "__gdb_builtin_type_fpreg_q", TYPE_CODE_UNION);
570 append_composite_type_field (t, "float", bt->builtin_float);
571 append_composite_type_field (t, "double", bt->builtin_double);
572 append_composite_type_field (t, "long double", bt->builtin_long_double);
574 TYPE_NAME (t) = "builtin_type_fpreg_q";
575 tdep->riscv_fpreg_q_type = t;
578 return tdep->riscv_fpreg_q_type;
581 /* Implement the register_type gdbarch method. */
584 riscv_register_type (struct gdbarch *gdbarch, int regnum)
588 if (regnum < RISCV_FIRST_FP_REGNUM)
590 if (regnum == gdbarch_pc_regnum (gdbarch)
591 || regnum == RISCV_RA_REGNUM)
592 return builtin_type (gdbarch)->builtin_func_ptr;
594 if (regnum == RISCV_FP_REGNUM
595 || regnum == RISCV_SP_REGNUM
596 || regnum == RISCV_GP_REGNUM
597 || regnum == RISCV_TP_REGNUM)
598 return builtin_type (gdbarch)->builtin_data_ptr;
600 /* Remaining GPRs vary in size based on the current ISA. */
601 regsize = riscv_isa_xlen (gdbarch);
605 return builtin_type (gdbarch)->builtin_uint32;
607 return builtin_type (gdbarch)->builtin_uint64;
609 return builtin_type (gdbarch)->builtin_uint128;
611 internal_error (__FILE__, __LINE__,
612 _("unknown isa regsize %i"), regsize);
615 else if (regnum <= RISCV_LAST_FP_REGNUM)
617 regsize = riscv_isa_xlen (gdbarch);
621 return builtin_type (gdbarch)->builtin_float;
623 return riscv_fpreg_d_type (gdbarch);
625 return riscv_fpreg_q_type (gdbarch);
627 internal_error (__FILE__, __LINE__,
628 _("unknown isa regsize %i"), regsize);
631 else if (regnum == RISCV_PRIV_REGNUM)
632 return builtin_type (gdbarch)->builtin_int8;
635 if (regnum == RISCV_CSR_FFLAGS_REGNUM
636 || regnum == RISCV_CSR_FRM_REGNUM
637 || regnum == RISCV_CSR_FCSR_REGNUM)
638 return builtin_type (gdbarch)->builtin_int32;
640 regsize = riscv_isa_xlen (gdbarch);
644 return builtin_type (gdbarch)->builtin_int32;
646 return builtin_type (gdbarch)->builtin_int64;
648 return builtin_type (gdbarch)->builtin_int128;
650 internal_error (__FILE__, __LINE__,
651 _("unknown isa regsize %i"), regsize);
656 /* Helper for riscv_print_registers_info, prints info for a single register
660 riscv_print_one_register_info (struct gdbarch *gdbarch,
661 struct ui_file *file,
662 struct frame_info *frame,
665 const char *name = gdbarch_register_name (gdbarch, regnum);
666 struct value *val = value_of_register (regnum, frame);
667 struct type *regtype = value_type (val);
668 int print_raw_format;
669 enum tab_stops { value_column_1 = 15 };
671 fputs_filtered (name, file);
672 print_spaces_filtered (value_column_1 - strlen (name), file);
674 print_raw_format = (value_entirely_available (val)
675 && !value_optimized_out (val));
677 if (TYPE_CODE (regtype) == TYPE_CODE_FLT
678 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
679 && TYPE_NFIELDS (regtype) == 2
680 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
681 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
682 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
683 && TYPE_NFIELDS (regtype) == 3
684 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
685 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
686 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
688 struct value_print_options opts;
689 const gdb_byte *valaddr = value_contents_for_printing (val);
690 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
692 get_user_print_options (&opts);
696 value_embedded_offset (val), 0,
697 file, 0, val, &opts, current_language);
699 if (print_raw_format)
701 fprintf_filtered (file, "\t(raw ");
702 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
704 fprintf_filtered (file, ")");
709 struct value_print_options opts;
711 /* Print the register in hex. */
712 get_formatted_print_options (&opts, 'x');
715 value_embedded_offset (val), 0,
716 file, 0, val, &opts, current_language);
718 if (print_raw_format)
720 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
723 int size = register_size (gdbarch, regnum);
726 d = value_as_long (val);
728 fprintf_filtered (file,
729 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
730 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
731 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
732 (int) ((d >> (xlen - 1)) & 0x1),
733 (int) ((d >> 24) & 0x1f),
734 (int) ((d >> 19) & 0x1),
735 (int) ((d >> 18) & 0x1),
736 (int) ((d >> 17) & 0x1),
737 (int) ((d >> 15) & 0x3),
738 (int) ((d >> 13) & 0x3),
739 (int) ((d >> 11) & 0x3),
740 (int) ((d >> 9) & 0x3),
741 (int) ((d >> 8) & 0x1),
742 (int) ((d >> 7) & 0x1),
743 (int) ((d >> 6) & 0x1),
744 (int) ((d >> 5) & 0x1),
745 (int) ((d >> 4) & 0x1),
746 (int) ((d >> 3) & 0x1),
747 (int) ((d >> 2) & 0x1),
748 (int) ((d >> 1) & 0x1),
749 (int) ((d >> 0) & 0x1));
751 else if (regnum == RISCV_CSR_MISA_REGNUM)
757 d = value_as_long (val);
761 for (; base > 0; base--)
763 fprintf_filtered (file, "\tRV%d", xlen);
765 for (i = 0; i < 26; i++)
768 fprintf_filtered (file, "%c", 'A' + i);
771 else if (regnum == RISCV_CSR_FCSR_REGNUM
772 || regnum == RISCV_CSR_FFLAGS_REGNUM
773 || regnum == RISCV_CSR_FRM_REGNUM)
777 d = value_as_long (val);
779 fprintf_filtered (file, "\t");
780 if (regnum != RISCV_CSR_FRM_REGNUM)
781 fprintf_filtered (file,
782 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
783 (int) ((d >> 5) & 0x7),
784 (int) ((d >> 4) & 0x1),
785 (int) ((d >> 3) & 0x1),
786 (int) ((d >> 2) & 0x1),
787 (int) ((d >> 1) & 0x1),
788 (int) ((d >> 0) & 0x1));
790 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
792 static const char * const sfrm[] =
794 "RNE (round to nearest; ties to even)",
795 "RTZ (Round towards zero)",
796 "RDN (Round down towards -INF)",
797 "RUP (Round up towards +INF)",
798 "RMM (Round to nearest; ties to max magnitude)",
801 "dynamic rounding mode",
803 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
804 ? (d >> 5) : d) & 0x3;
806 fprintf_filtered (file, "%sFRM:%i [%s]",
807 (regnum == RISCV_CSR_FCSR_REGNUM
812 else if (regnum == RISCV_PRIV_REGNUM)
817 d = value_as_long (val);
822 static const char * const sprv[] =
829 fprintf_filtered (file, "\tprv:%d [%s]",
833 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
837 /* If not a vector register, print it also according to its
839 if (TYPE_VECTOR (regtype) == 0)
841 get_user_print_options (&opts);
843 fprintf_filtered (file, "\t");
845 value_embedded_offset (val), 0,
846 file, 0, val, &opts, current_language);
851 fprintf_filtered (file, "\n");
854 /* Return true if REGNUM is a valid CSR register. The CSR register space
855 is sparsely populated, so not every number is a named CSR. */
858 riscv_is_regnum_a_named_csr (int regnum)
860 gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
861 && regnum <= RISCV_LAST_CSR_REGNUM);
865 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
866 #include "opcode/riscv-opc.h"
875 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
879 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
880 struct reggroup *reggroup)
882 /* Used by 'info registers' and 'info registers <groupname>'. */
884 if (gdbarch_register_name (gdbarch, regnum) == NULL
885 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
888 if (reggroup == all_reggroup)
890 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
892 if (riscv_is_regnum_a_named_csr (regnum))
896 else if (reggroup == float_reggroup)
897 return (riscv_is_fp_regno_p (regnum)
898 || regnum == RISCV_CSR_FCSR_REGNUM
899 || regnum == RISCV_CSR_FFLAGS_REGNUM
900 || regnum == RISCV_CSR_FRM_REGNUM);
901 else if (reggroup == general_reggroup)
902 return regnum < RISCV_FIRST_FP_REGNUM;
903 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
905 if (riscv_has_fp_regs (gdbarch))
906 return regnum <= RISCV_LAST_FP_REGNUM;
908 return regnum < RISCV_FIRST_FP_REGNUM;
910 else if (reggroup == system_reggroup)
912 if (regnum == RISCV_PRIV_REGNUM)
914 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
916 if (riscv_is_regnum_a_named_csr (regnum))
920 else if (reggroup == vector_reggroup)
926 /* Implement the print_registers_info gdbarch method. This is used by
927 'info registers' and 'info all-registers'. */
930 riscv_print_registers_info (struct gdbarch *gdbarch,
931 struct ui_file *file,
932 struct frame_info *frame,
933 int regnum, int print_all)
937 /* Print one specified register. */
938 gdb_assert (regnum <= RISCV_LAST_REGNUM);
939 if (gdbarch_register_name (gdbarch, regnum) == NULL
940 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
941 error (_("Not a valid register for the current processor type"));
942 riscv_print_one_register_info (gdbarch, file, frame, regnum);
946 struct reggroup *reggroup;
949 reggroup = all_reggroup;
951 reggroup = general_reggroup;
953 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
955 /* Zero never changes, so might as well hide by default. */
956 if (regnum == RISCV_ZERO_REGNUM && !print_all)
959 /* Registers with no name are not valid on this ISA. */
960 if (gdbarch_register_name (gdbarch, regnum) == NULL
961 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
964 /* Is the register in the group we're interested in? */
965 if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup))
968 riscv_print_one_register_info (gdbarch, file, frame, regnum);
973 /* Class that handles one decoded RiscV instruction. */
979 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
982 /* Unknown value is used at initialisation time. */
985 /* These instructions are all the ones we are interested in during the
995 /* These are needed for software breakopint support. */
1004 /* These are needed for stepping over atomic sequences. */
1008 /* Other instructions are not interesting during the prologue scan, and
1023 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1025 /* Get the length of the instruction in bytes. */
1027 { return m_length; }
1029 /* Get the opcode for this instruction. */
1030 enum opcode opcode () const
1031 { return m_opcode; }
1033 /* Get destination register field for this instruction. This is only
1034 valid if the OPCODE implies there is such a field for this
1039 /* Get the RS1 register field for this instruction. This is only valid
1040 if the OPCODE implies there is such a field for this instruction. */
1044 /* Get the RS2 register field for this instruction. This is only valid
1045 if the OPCODE implies there is such a field for this instruction. */
1049 /* Get the immediate for this instruction in signed form. This is only
1050 valid if the OPCODE implies there is such a field for this
1052 int imm_signed () const
1057 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1058 int decode_register_index (unsigned long opcode, int offset)
1060 return (opcode >> offset) & 0x1F;
1063 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1064 int decode_register_index_short (unsigned long opcode, int offset)
1066 return ((opcode >> offset) & 0x7) + 8;
1069 /* Helper for DECODE, decode 32-bit R-type instruction. */
1070 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1073 m_rd = decode_register_index (ival, OP_SH_RD);
1074 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1075 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1078 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1079 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1082 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1083 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1086 /* Helper for DECODE, decode 32-bit I-type instruction. */
1087 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1090 m_rd = decode_register_index (ival, OP_SH_RD);
1091 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1092 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1095 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1096 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1099 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1100 m_imm.s = EXTRACT_RVC_IMM (ival);
1103 /* Helper for DECODE, decode 32-bit S-type instruction. */
1104 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1107 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1108 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1109 m_imm.s = EXTRACT_STYPE_IMM (ival);
1112 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1113 encoding is different for each CS format instruction, so extracting
1114 the immediate is left up to the caller, who should pass the extracted
1115 immediate value through in IMM. */
1116 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1120 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1121 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1124 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1125 encoding is different for each CSS format instruction, so extracting
1126 the immediate is left up to the caller, who should pass the extracted
1127 immediate value through in IMM. */
1128 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1132 m_rs1 = RISCV_SP_REGNUM;
1133 /* Not a compressed register number in this case. */
1134 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1137 /* Helper for DECODE, decode 32-bit U-type instruction. */
1138 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1141 m_rd = decode_register_index (ival, OP_SH_RD);
1142 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1145 /* Helper for DECODE, decode 32-bit J-type instruction. */
1146 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1149 m_rd = decode_register_index (ival, OP_SH_RD);
1150 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1153 /* Helper for DECODE, decode 32-bit J-type instruction. */
1154 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1157 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1160 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1163 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1164 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1165 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1168 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1171 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1172 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1175 /* Fetch instruction from target memory at ADDR, return the content of
1176 the instruction, and update LEN with the instruction length. */
1177 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1178 CORE_ADDR addr, int *len);
1180 /* The length of the instruction in bytes. Should be 2 or 4. */
1183 /* The instruction opcode. */
1184 enum opcode m_opcode;
1186 /* The three possible registers an instruction might reference. Not
1187 every instruction fills in all of these registers. Which fields are
1188 valid depends on the opcode. The naming of these fields matches the
1189 naming in the riscv isa manual. */
1194 /* Possible instruction immediate. This is only valid if the instruction
1195 format contains an immediate, not all instruction, whether this is
1196 valid depends on the opcode. Despite only having one format for now
1197 the immediate is packed into a union, later instructions might require
1198 an unsigned formatted immediate, having the union in place now will
1199 reduce the need for code churn later. */
1200 union riscv_insn_immediate
1202 riscv_insn_immediate ()
1212 /* Fetch instruction from target memory at ADDR, return the content of the
1213 instruction, and update LEN with the instruction length. */
1216 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1217 CORE_ADDR addr, int *len)
1219 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1221 int instlen, status;
1223 /* All insns are at least 16 bits. */
1224 status = target_read_memory (addr, buf, 2);
1226 memory_error (TARGET_XFER_E_IO, addr);
1228 /* If we need more, grab it now. */
1229 instlen = riscv_insn_length (buf[0]);
1230 gdb_assert (instlen <= sizeof (buf));
1235 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1237 memory_error (TARGET_XFER_E_IO, addr + 2);
1240 return extract_unsigned_integer (buf, instlen, byte_order);
1243 /* Fetch from target memory an instruction at PC and decode it. */
1246 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1250 /* Fetch the instruction, and the instructions length. */
1251 ival = fetch_instruction (gdbarch, pc, &m_length);
1255 if (is_add_insn (ival))
1256 decode_r_type_insn (ADD, ival);
1257 else if (is_addw_insn (ival))
1258 decode_r_type_insn (ADDW, ival);
1259 else if (is_addi_insn (ival))
1260 decode_i_type_insn (ADDI, ival);
1261 else if (is_addiw_insn (ival))
1262 decode_i_type_insn (ADDIW, ival);
1263 else if (is_auipc_insn (ival))
1264 decode_u_type_insn (AUIPC, ival);
1265 else if (is_lui_insn (ival))
1266 decode_u_type_insn (LUI, ival);
1267 else if (is_sd_insn (ival))
1268 decode_s_type_insn (SD, ival);
1269 else if (is_sw_insn (ival))
1270 decode_s_type_insn (SW, ival);
1271 else if (is_jal_insn (ival))
1272 decode_j_type_insn (JAL, ival);
1273 else if (is_jalr_insn (ival))
1274 decode_i_type_insn (JALR, ival);
1275 else if (is_beq_insn (ival))
1276 decode_b_type_insn (BEQ, ival);
1277 else if (is_bne_insn (ival))
1278 decode_b_type_insn (BNE, ival);
1279 else if (is_blt_insn (ival))
1280 decode_b_type_insn (BLT, ival);
1281 else if (is_bge_insn (ival))
1282 decode_b_type_insn (BGE, ival);
1283 else if (is_bltu_insn (ival))
1284 decode_b_type_insn (BLTU, ival);
1285 else if (is_bgeu_insn (ival))
1286 decode_b_type_insn (BGEU, ival);
1287 else if (is_lr_w_insn (ival))
1288 decode_r_type_insn (LR, ival);
1289 else if (is_lr_d_insn (ival))
1290 decode_r_type_insn (LR, ival);
1291 else if (is_sc_w_insn (ival))
1292 decode_r_type_insn (SC, ival);
1293 else if (is_sc_d_insn (ival))
1294 decode_r_type_insn (SC, ival);
1296 /* None of the other fields are valid in this case. */
1299 else if (m_length == 2)
1301 int xlen = riscv_isa_xlen (gdbarch);
1303 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1304 C_JALR. So must try to match C_JALR first as it has more bits in
1306 if (is_c_jalr_insn (ival))
1307 decode_cr_type_insn (JALR, ival);
1308 else if (is_c_add_insn (ival))
1309 decode_cr_type_insn (ADD, ival);
1310 /* C_ADDW is RV64 and RV128 only. */
1311 else if (xlen != 4 && is_c_addw_insn (ival))
1312 decode_cr_type_insn (ADDW, ival);
1313 else if (is_c_addi_insn (ival))
1314 decode_ci_type_insn (ADDI, ival);
1315 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1316 only and C_JAL is RV32 only. */
1317 else if (xlen != 4 && is_c_addiw_insn (ival))
1318 decode_ci_type_insn (ADDIW, ival);
1319 else if (xlen == 4 && is_c_jal_insn (ival))
1320 decode_cj_type_insn (JAL, ival);
1321 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1322 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1324 else if (is_c_addi16sp_insn (ival))
1327 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1328 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1330 else if (is_c_addi4spn_insn (ival))
1333 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1334 m_rs1 = RISCV_SP_REGNUM;
1335 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1337 else if (is_c_lui_insn (ival))
1340 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1341 m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
1343 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1344 and C_FSW is RV32 only. */
1345 else if (xlen != 4 && is_c_sd_insn (ival))
1346 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
1347 else if (is_c_sw_insn (ival))
1348 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1349 else if (is_c_swsp_insn (ival))
1350 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1351 else if (xlen != 4 && is_c_sdsp_insn (ival))
1352 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
1353 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1354 So must try to match C_JR first as it ahs more bits in mask. */
1355 else if (is_c_jr_insn (ival))
1356 decode_cr_type_insn (JALR, ival);
1357 else if (is_c_j_insn (ival))
1358 decode_cj_type_insn (JAL, ival);
1359 else if (is_c_beqz_insn (ival))
1360 decode_cb_type_insn (BEQ, ival);
1361 else if (is_c_bnez_insn (ival))
1362 decode_cb_type_insn (BNE, ival);
1364 /* None of the other fields of INSN are valid in this case. */
1368 internal_error (__FILE__, __LINE__,
1369 _("unable to decode %d byte instructions in "
1370 "prologue at %s"), m_length,
1371 core_addr_to_string (pc));
1374 /* The prologue scanner. This is currently only used for skipping the
1375 prologue of a function when the DWARF information is not sufficient.
1376 However, it is written with filling of the frame cache in mind, which
1377 is why different groups of stack setup instructions are split apart
1378 during the core of the inner loop. In the future, the intention is to
1379 extend this function to fully support building up a frame cache that
1380 can unwind register values when there is no DWARF information. */
1383 riscv_scan_prologue (struct gdbarch *gdbarch,
1384 CORE_ADDR start_pc, CORE_ADDR end_pc,
1385 struct riscv_unwind_cache *cache)
1387 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1388 CORE_ADDR end_prologue_addr = 0;
1390 /* Find an upper limit on the function prologue using the debug
1391 information. If the debug information could not be used to provide
1392 that bound, then use an arbitrary large number as the upper bound. */
1393 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1394 if (after_prologue_pc == 0)
1395 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1396 if (after_prologue_pc < end_pc)
1397 end_pc = after_prologue_pc;
1399 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1400 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1401 regs[regno] = pv_register (regno, 0);
1402 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1404 if (riscv_debug_unwinder)
1407 "Prologue scan for function starting at %s (limit %s)\n",
1408 core_addr_to_string (start_pc),
1409 core_addr_to_string (end_pc));
1411 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1413 struct riscv_insn insn;
1415 /* Decode the current instruction, and decide where the next
1416 instruction lives based on the size of this instruction. */
1417 insn.decode (gdbarch, cur_pc);
1418 gdb_assert (insn.length () > 0);
1419 next_pc = cur_pc + insn.length ();
1421 /* Look for common stack adjustment insns. */
1422 if ((insn.opcode () == riscv_insn::ADDI
1423 || insn.opcode () == riscv_insn::ADDIW)
1424 && insn.rd () == RISCV_SP_REGNUM
1425 && insn.rs1 () == RISCV_SP_REGNUM)
1427 /* Handle: addi sp, sp, -i
1428 or: addiw sp, sp, -i */
1429 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1430 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1432 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1434 else if ((insn.opcode () == riscv_insn::SW
1435 || insn.opcode () == riscv_insn::SD)
1436 && (insn.rs1 () == RISCV_SP_REGNUM
1437 || insn.rs1 () == RISCV_FP_REGNUM))
1439 /* Handle: sw reg, offset(sp)
1440 or: sd reg, offset(sp)
1441 or: sw reg, offset(s0)
1442 or: sd reg, offset(s0) */
1443 /* Instruction storing a register onto the stack. */
1444 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1445 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1446 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1447 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1450 else if (insn.opcode () == riscv_insn::ADDI
1451 && insn.rd () == RISCV_FP_REGNUM
1452 && insn.rs1 () == RISCV_SP_REGNUM)
1454 /* Handle: addi s0, sp, size */
1455 /* Instructions setting up the frame pointer. */
1456 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1457 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1459 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1461 else if ((insn.opcode () == riscv_insn::ADD
1462 || insn.opcode () == riscv_insn::ADDW)
1463 && insn.rd () == RISCV_FP_REGNUM
1464 && insn.rs1 () == RISCV_SP_REGNUM
1465 && insn.rs2 () == RISCV_ZERO_REGNUM)
1467 /* Handle: add s0, sp, 0
1468 or: addw s0, sp, 0 */
1469 /* Instructions setting up the frame pointer. */
1470 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1471 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1472 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1474 else if ((insn.opcode () == riscv_insn::ADDI
1475 && insn.rd () == RISCV_ZERO_REGNUM
1476 && insn.rs1 () == RISCV_ZERO_REGNUM
1477 && insn.imm_signed () == 0))
1479 /* Handle: add x0, x0, 0 (NOP) */
1481 else if (insn.opcode () == riscv_insn::AUIPC)
1483 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1484 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1486 else if (insn.opcode () == riscv_insn::LUI)
1488 /* Handle: lui REG, n
1489 Where REG is not gp register. */
1490 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1491 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1493 else if (insn.opcode () == riscv_insn::ADDI)
1495 /* Handle: addi REG1, REG2, IMM */
1496 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1497 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1499 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1501 else if (insn.opcode () == riscv_insn::ADD)
1503 /* Handle: addi REG1, REG2, IMM */
1504 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1505 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1506 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1507 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1511 end_prologue_addr = cur_pc;
1516 if (end_prologue_addr == 0)
1517 end_prologue_addr = cur_pc;
1519 if (riscv_debug_unwinder)
1520 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1521 core_addr_to_string (end_prologue_addr));
1525 /* Figure out if it is a frame pointer or just a stack pointer. Also
1526 the offset held in the pv_t is from the original register value to
1527 the current value, which for a grows down stack means a negative
1528 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1529 from the current value to the original value. */
1530 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1532 cache->frame_base_reg = RISCV_FP_REGNUM;
1533 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1537 cache->frame_base_reg = RISCV_SP_REGNUM;
1538 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1541 /* Assign offset from old SP to all saved registers. As we don't
1542 have the previous value for the frame base register at this
1543 point, we store the offset as the address in the trad_frame, and
1544 then convert this to an actual address later. */
1545 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1548 if (stack.find_reg (gdbarch, i, &offset))
1550 if (riscv_debug_unwinder)
1551 fprintf_unfiltered (gdb_stdlog,
1552 "Register $%s at stack offset %ld\n",
1553 gdbarch_register_name (gdbarch, i),
1555 trad_frame_set_addr (cache->regs, i, offset);
1560 return end_prologue_addr;
1563 /* Implement the riscv_skip_prologue gdbarch method. */
1566 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1568 CORE_ADDR func_addr;
1570 /* See if we can determine the end of the prologue via the symbol
1571 table. If so, then return either PC, or the PC after the
1572 prologue, whichever is greater. */
1573 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1575 CORE_ADDR post_prologue_pc
1576 = skip_prologue_using_sal (gdbarch, func_addr);
1578 if (post_prologue_pc != 0)
1579 return std::max (pc, post_prologue_pc);
1582 /* Can't determine prologue from the symbol table, need to examine
1583 instructions. Pass -1 for the end address to indicate the prologue
1584 scanner can scan as far as it needs to find the end of the prologue. */
1585 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1588 /* Implement the gdbarch push dummy code callback. */
1591 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1592 CORE_ADDR funaddr, struct value **args, int nargs,
1593 struct type *value_type, CORE_ADDR *real_pc,
1594 CORE_ADDR *bp_addr, struct regcache *regcache)
1596 /* Allocate space for a breakpoint, and keep the stack correctly
1604 /* Compute the alignment of the type T. Used while setting up the
1605 arguments for a dummy call. */
1608 riscv_type_alignment (struct type *t)
1610 t = check_typedef (t);
1611 switch (TYPE_CODE (t))
1614 error (_("Could not compute alignment of type"));
1616 case TYPE_CODE_RVALUE_REF:
1618 case TYPE_CODE_ENUM:
1622 case TYPE_CODE_CHAR:
1623 case TYPE_CODE_BOOL:
1624 return TYPE_LENGTH (t);
1626 case TYPE_CODE_ARRAY:
1627 case TYPE_CODE_COMPLEX:
1628 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1630 case TYPE_CODE_STRUCT:
1631 case TYPE_CODE_UNION:
1636 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1638 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1640 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1650 /* Holds information about a single argument either being passed to an
1651 inferior function, or returned from an inferior function. This includes
1652 information about the size, type, etc of the argument, and also
1653 information about how the argument will be passed (or returned). */
1655 struct riscv_arg_info
1657 /* Contents of the argument. */
1658 const gdb_byte *contents;
1660 /* Length of argument. */
1663 /* Alignment required for an argument of this type. */
1666 /* The type for this argument. */
1669 /* Each argument can have either 1 or 2 locations assigned to it. Each
1670 location describes where part of the argument will be placed. The
1671 second location is valid based on the LOC_TYPE and C_LENGTH fields
1672 of the first location (which is always valid). */
1675 /* What type of location this is. */
1678 /* Argument passed in a register. */
1681 /* Argument passed as an on stack argument. */
1684 /* Argument passed by reference. The second location is always
1685 valid for a BY_REF argument, and describes where the address
1686 of the BY_REF argument should be placed. */
1690 /* Information that depends on the location type. */
1693 /* Which register number to use. */
1696 /* The offset into the stack region. */
1700 /* The length of contents covered by this location. If this is less
1701 than the total length of the argument, then the second location
1702 will be valid, and will describe where the rest of the argument
1706 /* The offset within CONTENTS for this part of the argument. Will
1707 always be 0 for the first part. For the second part of the
1708 argument, this might be the C_LENGTH value of the first part,
1709 however, if we are passing a structure in two registers, and there's
1710 is padding between the first and second field, then this offset
1711 might be greater than the length of the first argument part. When
1712 the second argument location is not holding part of the argument
1713 value, but is instead holding the address of a reference argument,
1714 then this offset will be set to 0. */
1719 /* Information about a set of registers being used for passing arguments as
1720 part of a function call. The register set must be numerically
1721 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1722 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1724 struct riscv_arg_reg
1726 riscv_arg_reg (int first, int last)
1727 : next_regnum (first),
1733 /* The GDB register number to use in this set. */
1736 /* The last GDB register number to use in this set. */
1740 /* Arguments can be passed as on stack arguments, or by reference. The
1741 on stack arguments must be in a continuous region starting from $sp,
1742 while the by reference arguments can be anywhere, but we'll put them
1743 on the stack after (at higher address) the on stack arguments.
1745 This might not be the right approach to take. The ABI is clear that
1746 an argument passed by reference can be modified by the callee, which
1747 us placing the argument (temporarily) onto the stack will not achieve
1748 (changes will be lost). There's also the possibility that very large
1749 arguments could overflow the stack.
1751 This struct is used to track offset into these two areas for where
1752 arguments are to be placed. */
1753 struct riscv_memory_offsets
1755 riscv_memory_offsets ()
1762 /* Offset into on stack argument area. */
1765 /* Offset into the pass by reference area. */
1769 /* Holds information about where arguments to a call will be placed. This
1770 is updated as arguments are added onto the call, and can be used to
1771 figure out where the next argument should be placed. */
1773 struct riscv_call_info
1775 riscv_call_info (struct gdbarch *gdbarch)
1776 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1777 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1779 xlen = riscv_isa_xlen (gdbarch);
1780 flen = riscv_isa_flen (gdbarch);
1782 /* Disable use of floating point registers if needed. */
1783 if (!riscv_has_fp_abi (gdbarch))
1784 float_regs.next_regnum = float_regs.last_regnum + 1;
1787 /* Track the memory areas used for holding in-memory arguments to a
1789 struct riscv_memory_offsets memory;
1791 /* Holds information about the next integer register to use for passing
1793 struct riscv_arg_reg int_regs;
1795 /* Holds information about the next floating point register to use for
1796 passing an argument. */
1797 struct riscv_arg_reg float_regs;
1799 /* The XLEN and FLEN are copied in to this structure for convenience, and
1800 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1805 /* Return the number of registers available for use as parameters in the
1806 register set REG. Returned value can be 0 or more. */
1809 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1811 if (reg->next_regnum > reg->last_regnum)
1814 return (reg->last_regnum - reg->next_regnum + 1);
1817 /* If there is at least one register available in the register set REG then
1818 the next register from REG is assigned to LOC and the length field of
1819 LOC is updated to LENGTH. The register set REG is updated to indicate
1820 that the assigned register is no longer available and the function
1823 If there are no registers available in REG then the function returns
1824 false, and LOC and REG are unchanged. */
1827 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1828 struct riscv_arg_reg *reg,
1829 int length, int offset)
1831 if (reg->next_regnum <= reg->last_regnum)
1833 loc->loc_type = riscv_arg_info::location::in_reg;
1834 loc->loc_data.regno = reg->next_regnum;
1836 loc->c_length = length;
1837 loc->c_offset = offset;
1844 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1845 record that an area of stack has been used to hold the parameter
1848 The length field of LOC is updated to LENGTH, the length of the
1849 parameter being stored, and ALIGN is the alignment required by the
1850 parameter, which will affect how memory is allocated out of MEMORY. */
1853 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1854 struct riscv_memory_offsets *memory,
1855 int length, int align)
1857 loc->loc_type = riscv_arg_info::location::on_stack;
1859 = align_up (memory->arg_offset, align);
1860 loc->loc_data.offset = memory->arg_offset;
1861 memory->arg_offset += length;
1862 loc->c_length = length;
1864 /* Offset is always 0, either we're the first location part, in which
1865 case we're reading content from the start of the argument, or we're
1866 passing the address of a reference argument, so 0. */
1870 /* Update AINFO, which describes an argument that should be passed or
1871 returned using the integer ABI. The argloc fields within AINFO are
1872 updated to describe the location in which the argument will be passed to
1873 a function, or returned from a function.
1875 The CINFO structure contains the ongoing call information, the holds
1876 information such as which argument registers are remaining to be
1877 assigned to parameter, and how much memory has been used by parameters
1880 By examining the state of CINFO a suitable location can be selected,
1881 and assigned to AINFO. */
1884 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1885 struct riscv_call_info *cinfo)
1887 if (ainfo->length > (2 * cinfo->xlen))
1889 /* Argument is going to be passed by reference. */
1890 ainfo->argloc[0].loc_type
1891 = riscv_arg_info::location::by_ref;
1892 cinfo->memory.ref_offset
1893 = align_up (cinfo->memory.ref_offset, ainfo->align);
1894 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1895 cinfo->memory.ref_offset += ainfo->length;
1896 ainfo->argloc[0].c_length = ainfo->length;
1898 /* The second location for this argument is given over to holding the
1899 address of the by-reference data. Pass 0 for the offset as this
1900 is not part of the actual argument value. */
1901 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1904 riscv_assign_stack_location (&ainfo->argloc[1],
1905 &cinfo->memory, cinfo->xlen,
1910 int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length;
1912 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1913 &cinfo->int_regs, len, 0))
1914 riscv_assign_stack_location (&ainfo->argloc[0],
1915 &cinfo->memory, len, ainfo->align);
1917 if (len < ainfo->length)
1919 len = ainfo->length - len;
1920 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1921 &cinfo->int_regs, len,
1923 riscv_assign_stack_location (&ainfo->argloc[1],
1924 &cinfo->memory, len, cinfo->xlen);
1929 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1930 is being passed with the floating point ABI. */
1933 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1934 struct riscv_call_info *cinfo)
1936 if (ainfo->length > cinfo->flen)
1937 return riscv_call_arg_scalar_int (ainfo, cinfo);
1940 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1943 return riscv_call_arg_scalar_int (ainfo, cinfo);
1947 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1948 is a complex floating point argument, and is therefore handled
1949 differently to other argument types. */
1952 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1953 struct riscv_call_info *cinfo)
1955 if (ainfo->length <= (2 * cinfo->flen)
1956 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1959 int len = ainfo->length / 2;
1961 result = riscv_assign_reg_location (&ainfo->argloc[0],
1962 &cinfo->float_regs, len, len);
1963 gdb_assert (result);
1965 result = riscv_assign_reg_location (&ainfo->argloc[1],
1966 &cinfo->float_regs, len, len);
1967 gdb_assert (result);
1970 return riscv_call_arg_scalar_int (ainfo, cinfo);
1973 /* A structure used for holding information about a structure type within
1974 the inferior program. The RiscV ABI has special rules for handling some
1975 structures with a single field or with two fields. The counting of
1976 fields here is done after flattening out all nested structures. */
1978 class riscv_struct_info
1981 riscv_struct_info ()
1982 : m_number_of_fields (0),
1983 m_types { nullptr, nullptr }
1988 /* Analyse TYPE descending into nested structures, count the number of
1989 scalar fields and record the types of the first two fields found. */
1990 void analyse (struct type *type);
1992 /* The number of scalar fields found in the analysed type. This is
1993 currently only accurate if the value returned is 0, 1, or 2 as the
1994 analysis stops counting when the number of fields is 3. This is
1995 because the RiscV ABI only has special cases for 1 or 2 fields,
1996 anything else we just don't care about. */
1997 int number_of_fields () const
1998 { return m_number_of_fields; }
2000 /* Return the type for scalar field INDEX within the analysed type. Will
2001 return nullptr if there is no field at that index. Only INDEX values
2002 0 and 1 can be requested as the RiscV ABI only has special cases for
2003 structures with 1 or 2 fields. */
2004 struct type *field_type (int index) const
2006 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
2007 return m_types[index];
2011 /* The number of scalar fields found within the structure after recursing
2012 into nested structures. */
2013 int m_number_of_fields;
2015 /* The types of the first two scalar fields found within the structure
2016 after recursing into nested structures. */
2017 struct type *m_types[2];
2020 /* Analyse TYPE descending into nested structures, count the number of
2021 scalar fields and record the types of the first two fields found. */
2024 riscv_struct_info::analyse (struct type *type)
2026 unsigned int count = TYPE_NFIELDS (type);
2029 for (i = 0; i < count; ++i)
2031 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
2034 struct type *field_type = TYPE_FIELD_TYPE (type, i);
2035 field_type = check_typedef (field_type);
2037 switch (TYPE_CODE (field_type))
2039 case TYPE_CODE_STRUCT:
2040 analyse (field_type);
2044 /* RiscV only flattens out structures. Anything else does not
2045 need to be flattened, we just record the type, and when we
2046 look at the analysis results we'll realise this is not a
2047 structure we can special case, and pass the structure in
2049 if (m_number_of_fields < 2)
2050 m_types[m_number_of_fields] = field_type;
2051 m_number_of_fields++;
2055 /* RiscV only has special handling for structures with 1 or 2 scalar
2056 fields, any more than that and the structure is just passed in
2057 memory. We can safely drop out early when we find 3 or more
2060 if (m_number_of_fields > 2)
2065 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2066 is a structure. Small structures on RiscV have some special case
2067 handling in order that the structure might be passed in register.
2068 Larger structures are passed in memory. After assigning location
2069 information to AINFO, CINFO will have been updated. */
2072 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
2073 struct riscv_call_info *cinfo)
2075 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2077 struct riscv_struct_info sinfo;
2079 sinfo.analyse (ainfo->type);
2080 if (sinfo.number_of_fields () == 1
2081 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
2083 gdb_assert (TYPE_LENGTH (ainfo->type)
2084 == TYPE_LENGTH (sinfo.field_type (0)));
2085 return riscv_call_arg_complex_float (ainfo, cinfo);
2088 if (sinfo.number_of_fields () == 1
2089 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
2091 gdb_assert (TYPE_LENGTH (ainfo->type)
2092 == TYPE_LENGTH (sinfo.field_type (0)));
2093 return riscv_call_arg_scalar_float (ainfo, cinfo);
2096 if (sinfo.number_of_fields () == 2
2097 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2098 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2099 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2100 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
2101 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2103 int len0, len1, offset;
2105 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
2107 len0 = TYPE_LENGTH (sinfo.field_type (0));
2108 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2109 &cinfo->float_regs, len0, 0))
2110 error (_("failed during argument setup"));
2112 len1 = TYPE_LENGTH (sinfo.field_type (1));
2113 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2114 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2115 - TYPE_LENGTH (sinfo.field_type (0))));
2117 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2120 error (_("failed during argument setup"));
2124 if (sinfo.number_of_fields () == 2
2125 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2126 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2127 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2128 && is_integral_type (sinfo.field_type (1))
2129 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2131 int len0, len1, offset;
2133 gdb_assert (TYPE_LENGTH (ainfo->type)
2134 <= (cinfo->flen + cinfo->xlen));
2136 len0 = TYPE_LENGTH (sinfo.field_type (0));
2137 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2138 &cinfo->float_regs, len0, 0))
2139 error (_("failed during argument setup"));
2141 len1 = TYPE_LENGTH (sinfo.field_type (1));
2142 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2143 gdb_assert (len1 <= cinfo->xlen);
2144 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2145 &cinfo->int_regs, len1, offset))
2146 error (_("failed during argument setup"));
2150 if (sinfo.number_of_fields () == 2
2151 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2152 && (is_integral_type (sinfo.field_type (0))
2153 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2154 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2155 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2157 int len0, len1, offset;
2159 gdb_assert (TYPE_LENGTH (ainfo->type)
2160 <= (cinfo->flen + cinfo->xlen));
2162 len0 = TYPE_LENGTH (sinfo.field_type (0));
2163 len1 = TYPE_LENGTH (sinfo.field_type (1));
2164 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2166 gdb_assert (len0 <= cinfo->xlen);
2167 gdb_assert (len1 <= cinfo->flen);
2169 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2170 &cinfo->int_regs, len0, 0))
2171 error (_("failed during argument setup"));
2173 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2176 error (_("failed during argument setup"));
2182 /* Non of the structure flattening cases apply, so we just pass using
2184 ainfo->length = align_up (ainfo->length, cinfo->xlen);
2185 riscv_call_arg_scalar_int (ainfo, cinfo);
2188 /* Assign a location to call (or return) argument AINFO, the location is
2189 selected from CINFO which holds information about what call argument
2190 locations are available for use next. The TYPE is the type of the
2191 argument being passed, this information is recorded into AINFO (along
2192 with some additional information derived from the type).
2194 After assigning a location to AINFO, CINFO will have been updated. */
2197 riscv_arg_location (struct gdbarch *gdbarch,
2198 struct riscv_arg_info *ainfo,
2199 struct riscv_call_info *cinfo,
2203 ainfo->length = TYPE_LENGTH (ainfo->type);
2204 ainfo->align = riscv_type_alignment (ainfo->type);
2205 ainfo->contents = nullptr;
2207 switch (TYPE_CODE (ainfo->type))
2210 case TYPE_CODE_BOOL:
2211 case TYPE_CODE_CHAR:
2212 case TYPE_CODE_RANGE:
2213 case TYPE_CODE_ENUM:
2215 if (ainfo->length <= cinfo->xlen)
2217 ainfo->type = builtin_type (gdbarch)->builtin_long;
2218 ainfo->length = cinfo->xlen;
2220 else if (ainfo->length <= (2 * cinfo->xlen))
2222 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2223 ainfo->length = 2 * cinfo->xlen;
2226 /* Recalculate the alignment requirement. */
2227 ainfo->align = riscv_type_alignment (ainfo->type);
2228 riscv_call_arg_scalar_int (ainfo, cinfo);
2232 riscv_call_arg_scalar_float (ainfo, cinfo);
2235 case TYPE_CODE_COMPLEX:
2236 riscv_call_arg_complex_float (ainfo, cinfo);
2239 case TYPE_CODE_STRUCT:
2240 riscv_call_arg_struct (ainfo, cinfo);
2244 riscv_call_arg_scalar_int (ainfo, cinfo);
2249 /* Used for printing debug information about the call argument location in
2250 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2251 addresses for the location of pass-by-reference and
2252 arguments-on-the-stack memory areas. */
2255 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2256 struct riscv_arg_info *info,
2257 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2259 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2260 TYPE_SAFE_NAME (info->type), info->length, info->align);
2261 switch (info->argloc[0].loc_type)
2263 case riscv_arg_info::location::in_reg:
2265 (stream, ", register %s",
2266 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2267 if (info->argloc[0].c_length < info->length)
2269 switch (info->argloc[1].loc_type)
2271 case riscv_arg_info::location::in_reg:
2273 (stream, ", register %s",
2274 gdbarch_register_name (gdbarch,
2275 info->argloc[1].loc_data.regno));
2278 case riscv_arg_info::location::on_stack:
2279 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2280 info->argloc[1].loc_data.offset);
2283 case riscv_arg_info::location::by_ref:
2285 /* The second location should never be a reference, any
2286 argument being passed by reference just places its address
2287 in the first location and is done. */
2288 error (_("invalid argument location"));
2292 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2293 fprintf_unfiltered (stream, " (offset 0x%x)",
2294 info->argloc[1].c_offset);
2298 case riscv_arg_info::location::on_stack:
2299 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2300 info->argloc[0].loc_data.offset);
2303 case riscv_arg_info::location::by_ref:
2305 (stream, ", by reference, data at offset 0x%x (%s)",
2306 info->argloc[0].loc_data.offset,
2307 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2308 if (info->argloc[1].loc_type
2309 == riscv_arg_info::location::in_reg)
2311 (stream, ", address in register %s",
2312 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2315 gdb_assert (info->argloc[1].loc_type
2316 == riscv_arg_info::location::on_stack);
2318 (stream, ", address on stack at offset 0x%x (%s)",
2319 info->argloc[1].loc_data.offset,
2320 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2325 gdb_assert_not_reached (_("unknown argument location type"));
2329 /* Implement the push dummy call gdbarch callback. */
2332 riscv_push_dummy_call (struct gdbarch *gdbarch,
2333 struct value *function,
2334 struct regcache *regcache,
2337 struct value **args,
2340 CORE_ADDR struct_addr)
2343 CORE_ADDR sp_args, sp_refs;
2344 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2346 struct riscv_arg_info *arg_info =
2347 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2349 struct riscv_call_info call_info (gdbarch);
2353 /* We'll use register $a0 if we're returning a struct. */
2355 ++call_info.int_regs.next_regnum;
2357 for (i = 0; i < nargs; ++i)
2359 struct value *arg_value;
2360 struct type *arg_type;
2361 struct riscv_arg_info *info = &arg_info[i];
2363 arg_value = args[i];
2364 arg_type = check_typedef (value_type (arg_value));
2366 riscv_arg_location (gdbarch, info, &call_info, arg_type);
2368 if (info->type != arg_type)
2369 arg_value = value_cast (info->type, arg_value);
2370 info->contents = value_contents (arg_value);
2373 /* Adjust the stack pointer and align it. */
2374 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2375 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2377 if (riscv_debug_infcall > 0)
2379 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2380 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2381 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2382 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2383 call_info.xlen, call_info.flen);
2385 fprintf_unfiltered (gdb_stdlog,
2386 "[*] struct return pointer in register $A0\n");
2387 for (i = 0; i < nargs; ++i)
2389 struct riscv_arg_info *info = &arg_info [i];
2391 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2392 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2393 fprintf_unfiltered (gdb_stdlog, "\n");
2395 if (call_info.memory.arg_offset > 0
2396 || call_info.memory.ref_offset > 0)
2398 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2399 core_addr_to_string (osp));
2400 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2401 call_info.memory.arg_offset);
2402 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2403 call_info.memory.ref_offset);
2404 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2405 core_addr_to_string_nz (osp - sp));
2409 /* Now load the argument into registers, or onto the stack. */
2413 gdb_byte buf[sizeof (LONGEST)];
2415 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2416 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2419 for (i = 0; i < nargs; ++i)
2422 int second_arg_length = 0;
2423 const gdb_byte *second_arg_data;
2424 struct riscv_arg_info *info = &arg_info [i];
2426 gdb_assert (info->length > 0);
2428 switch (info->argloc[0].loc_type)
2430 case riscv_arg_info::location::in_reg:
2432 gdb_byte tmp [sizeof (ULONGEST)];
2434 gdb_assert (info->argloc[0].c_length <= info->length);
2435 /* FP values in FP registers must be NaN-boxed. */
2436 if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno)
2437 && info->argloc[0].c_length < call_info.flen)
2438 memset (tmp, -1, sizeof (tmp));
2440 memset (tmp, 0, sizeof (tmp));
2441 memcpy (tmp, info->contents, info->argloc[0].c_length);
2442 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2444 ((info->argloc[0].c_length < info->length)
2445 ? info->argloc[1].c_length : 0);
2446 second_arg_data = info->contents + info->argloc[1].c_offset;
2450 case riscv_arg_info::location::on_stack:
2451 dst = sp_args + info->argloc[0].loc_data.offset;
2452 write_memory (dst, info->contents, info->length);
2453 second_arg_length = 0;
2456 case riscv_arg_info::location::by_ref:
2457 dst = sp_refs + info->argloc[0].loc_data.offset;
2458 write_memory (dst, info->contents, info->length);
2460 second_arg_length = call_info.xlen;
2461 second_arg_data = (gdb_byte *) &dst;
2465 gdb_assert_not_reached (_("unknown argument location type"));
2468 if (second_arg_length > 0)
2470 switch (info->argloc[1].loc_type)
2472 case riscv_arg_info::location::in_reg:
2474 gdb_byte tmp [sizeof (ULONGEST)];
2476 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2477 && second_arg_length <= call_info.flen)
2478 || second_arg_length <= call_info.xlen);
2479 /* FP values in FP registers must be NaN-boxed. */
2480 if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2481 && second_arg_length < call_info.flen)
2482 memset (tmp, -1, sizeof (tmp));
2484 memset (tmp, 0, sizeof (tmp));
2485 memcpy (tmp, second_arg_data, second_arg_length);
2486 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2490 case riscv_arg_info::location::on_stack:
2494 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2495 write_memory (arg_addr, second_arg_data, second_arg_length);
2499 case riscv_arg_info::location::by_ref:
2501 /* The second location should never be a reference, any
2502 argument being passed by reference just places its address
2503 in the first location and is done. */
2504 error (_("invalid argument location"));
2510 /* Set the dummy return value to bp_addr.
2511 A dummy breakpoint will be setup to execute the call. */
2513 if (riscv_debug_infcall > 0)
2514 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2515 core_addr_to_string (bp_addr));
2516 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2518 /* Finally, update the stack pointer. */
2520 if (riscv_debug_infcall > 0)
2521 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2522 core_addr_to_string (sp));
2523 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2528 /* Implement the return_value gdbarch method. */
2530 static enum return_value_convention
2531 riscv_return_value (struct gdbarch *gdbarch,
2532 struct value *function,
2534 struct regcache *regcache,
2536 const gdb_byte *writebuf)
2538 struct riscv_call_info call_info (gdbarch);
2539 struct riscv_arg_info info;
2540 struct type *arg_type;
2542 arg_type = check_typedef (type);
2543 riscv_arg_location (gdbarch, &info, &call_info, arg_type);
2545 if (riscv_debug_infcall > 0)
2547 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2548 fprintf_unfiltered (gdb_stdlog, "[R] ");
2549 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2550 fprintf_unfiltered (gdb_stdlog, "\n");
2553 if (readbuf != nullptr || writebuf != nullptr)
2557 switch (info.argloc[0].loc_type)
2559 /* Return value in register(s). */
2560 case riscv_arg_info::location::in_reg:
2562 regnum = info.argloc[0].loc_data.regno;
2565 regcache->cooked_read (regnum, readbuf);
2568 regcache->cooked_write (regnum, writebuf);
2570 /* A return value in register can have a second part in a
2572 if (info.argloc[0].c_length < info.length)
2574 switch (info.argloc[1].loc_type)
2576 case riscv_arg_info::location::in_reg:
2577 regnum = info.argloc[1].loc_data.regno;
2581 readbuf += info.argloc[1].c_offset;
2582 regcache->cooked_read (regnum, readbuf);
2587 writebuf += info.argloc[1].c_offset;
2588 regcache->cooked_write (regnum, writebuf);
2592 case riscv_arg_info::location::by_ref:
2593 case riscv_arg_info::location::on_stack:
2595 error (_("invalid argument location"));
2602 /* Return value by reference will have its address in A0. */
2603 case riscv_arg_info::location::by_ref:
2607 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2609 if (readbuf != nullptr)
2610 read_memory (addr, readbuf, info.length);
2611 if (writebuf != nullptr)
2612 write_memory (addr, writebuf, info.length);
2616 case riscv_arg_info::location::on_stack:
2618 error (_("invalid argument location"));
2623 switch (info.argloc[0].loc_type)
2625 case riscv_arg_info::location::in_reg:
2626 return RETURN_VALUE_REGISTER_CONVENTION;
2627 case riscv_arg_info::location::by_ref:
2628 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2629 case riscv_arg_info::location::on_stack:
2631 error (_("invalid argument location"));
2635 /* Implement the frame_align gdbarch method. */
2638 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2640 return align_down (addr, 16);
2643 /* Implement the unwind_pc gdbarch method. */
2646 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2648 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2651 /* Implement the unwind_sp gdbarch method. */
2654 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2656 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2659 /* Implement the dummy_id gdbarch method. */
2661 static struct frame_id
2662 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2664 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2665 get_frame_pc (this_frame));
2668 /* Generate, or return the cached frame cache for the RiscV frame
2671 static struct riscv_unwind_cache *
2672 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2674 CORE_ADDR pc, start_addr;
2675 struct riscv_unwind_cache *cache;
2676 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2679 if ((*this_cache) != NULL)
2680 return (struct riscv_unwind_cache *) *this_cache;
2682 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2683 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2684 (*this_cache) = cache;
2686 /* Scan the prologue, filling in the cache. */
2687 start_addr = get_frame_func (this_frame);
2688 pc = get_frame_pc (this_frame);
2689 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2691 /* We can now calculate the frame base address. */
2693 = (get_frame_register_signed (this_frame, cache->frame_base_reg)
2694 + cache->frame_base_offset);
2695 if (riscv_debug_unwinder)
2696 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2697 core_addr_to_string (cache->frame_base),
2698 gdbarch_register_name (gdbarch,
2699 cache->frame_base_reg),
2700 cache->frame_base_offset);
2702 /* The prologue scanner sets the address of registers stored to the stack
2703 as the offset of that register from the frame base. The prologue
2704 scanner doesn't know the actual frame base value, and so is unable to
2705 compute the exact address. We do now know the frame base value, so
2706 update the address of registers stored to the stack. */
2707 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2708 for (regno = 0; regno < numregs; ++regno)
2710 if (trad_frame_addr_p (cache->regs, regno))
2711 cache->regs[regno].addr += cache->frame_base;
2714 /* The previous $pc can be found wherever the $ra value can be found.
2715 The previous $ra value is gone, this would have been stored be the
2716 previous frame if required. */
2717 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2718 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2720 /* Build the frame id. */
2721 cache->this_id = frame_id_build (cache->frame_base, start_addr);
2723 /* The previous $sp value is the frame base value. */
2724 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2730 /* Implement the this_id callback for RiscV frame unwinder. */
2733 riscv_frame_this_id (struct frame_info *this_frame,
2734 void **prologue_cache,
2735 struct frame_id *this_id)
2737 struct riscv_unwind_cache *cache;
2739 cache = riscv_frame_cache (this_frame, prologue_cache);
2740 *this_id = cache->this_id;
2743 /* Implement the prev_register callback for RiscV frame unwinder. */
2745 static struct value *
2746 riscv_frame_prev_register (struct frame_info *this_frame,
2747 void **prologue_cache,
2750 struct riscv_unwind_cache *cache;
2752 cache = riscv_frame_cache (this_frame, prologue_cache);
2753 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
2756 /* Structure defining the RiscV normal frame unwind functions. Since we
2757 are the fallback unwinder (DWARF unwinder is used first), we use the
2758 default frame sniffer, which always accepts the frame. */
2760 static const struct frame_unwind riscv_frame_unwind =
2762 /*.type =*/ NORMAL_FRAME,
2763 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2764 /*.this_id =*/ riscv_frame_this_id,
2765 /*.prev_register =*/ riscv_frame_prev_register,
2766 /*.unwind_data =*/ NULL,
2767 /*.sniffer =*/ default_frame_sniffer,
2768 /*.dealloc_cache =*/ NULL,
2769 /*.prev_arch =*/ NULL,
2772 /* Initialize the current architecture based on INFO. If possible,
2773 re-use an architecture from ARCHES, which is a list of
2774 architectures already created during this debugging session.
2776 Called e.g. at program startup, when reading a core file, and when
2777 reading a binary file. */
2779 static struct gdbarch *
2780 riscv_gdbarch_init (struct gdbarch_info info,
2781 struct gdbarch_list *arches)
2783 struct gdbarch *gdbarch;
2784 struct gdbarch_tdep *tdep;
2785 struct gdbarch_tdep tmp_tdep;
2788 /* Ideally, we'd like to get as much information from the target for
2789 things like register size, and whether the target has floating point
2790 hardware. However, there are some things that the target can't tell
2791 us, like, what ABI is being used.
2793 So, for now, we take as much information as possible from the ELF,
2794 including things like register size, and FP hardware support, along
2795 with information about the ABI.
2797 Information about this target is built up in TMP_TDEP, and then we
2798 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2799 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2800 memset (&tmp_tdep, 0, sizeof (tmp_tdep));
2802 if (info.abfd != NULL
2803 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2805 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2806 int e_flags = elf_elfheader (info.abfd)->e_flags;
2808 if (eclass == ELFCLASS32)
2809 tmp_tdep.abi.fields.base_len = 1;
2810 else if (eclass == ELFCLASS64)
2811 tmp_tdep.abi.fields.base_len = 2;
2813 internal_error (__FILE__, __LINE__,
2814 _("unknown ELF header class %d"), eclass);
2816 if (e_flags & EF_RISCV_RVC)
2817 tmp_tdep.core_features |= (1 << ('C' - 'A'));
2819 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2821 tmp_tdep.abi.fields.float_abi = 2;
2822 tmp_tdep.core_features |= (1 << ('D' - 'A'));
2823 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2825 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2827 tmp_tdep.abi.fields.float_abi = 1;
2828 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2833 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2835 if (binfo->bits_per_word == 32)
2836 tmp_tdep.abi.fields.base_len = 1;
2837 else if (binfo->bits_per_word == 64)
2838 tmp_tdep.abi.fields.base_len = 2;
2840 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2841 binfo->bits_per_word);
2844 /* Find a candidate among the list of pre-declared architectures. */
2845 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2847 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2848 if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
2849 return arches->gdbarch;
2851 /* None found, so create a new architecture from the information provided. */
2852 tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
2853 gdbarch = gdbarch_alloc (&info, tdep);
2854 memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep));
2856 /* Target data types. */
2857 set_gdbarch_short_bit (gdbarch, 16);
2858 set_gdbarch_int_bit (gdbarch, 32);
2859 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2860 set_gdbarch_long_long_bit (gdbarch, 64);
2861 set_gdbarch_float_bit (gdbarch, 32);
2862 set_gdbarch_double_bit (gdbarch, 64);
2863 set_gdbarch_long_double_bit (gdbarch, 128);
2864 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2865 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2866 set_gdbarch_char_signed (gdbarch, 0);
2868 /* Information about the target architecture. */
2869 set_gdbarch_return_value (gdbarch, riscv_return_value);
2870 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
2871 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
2872 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2874 /* Register architecture. */
2875 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
2876 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
2877 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
2878 set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
2879 set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
2881 /* Functions to supply register information. */
2882 set_gdbarch_register_name (gdbarch, riscv_register_name);
2883 set_gdbarch_register_type (gdbarch, riscv_register_type);
2884 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
2885 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
2887 /* Functions to analyze frames. */
2888 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
2889 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2890 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
2892 /* Functions to access frame data. */
2893 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
2894 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
2896 /* Functions handling dummy frames. */
2897 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2898 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
2899 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
2900 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
2902 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2904 dwarf2_append_unwinders (gdbarch);
2905 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
2907 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
2908 user_reg_add (gdbarch, riscv_register_aliases[i].name,
2909 value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
2911 /* Hook in OS ABI-specific overrides, if they have been registered. */
2912 gdbarch_init_osabi (info, gdbarch);
2917 /* This decodes the current instruction and determines the address of the
2918 next instruction. */
2921 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
2923 struct gdbarch *gdbarch = regcache->arch ();
2924 struct riscv_insn insn;
2927 insn.decode (gdbarch, pc);
2928 next_pc = pc + insn.length ();
2930 if (insn.opcode () == riscv_insn::JAL)
2931 next_pc = pc + insn.imm_signed ();
2932 else if (insn.opcode () == riscv_insn::JALR)
2935 regcache->cooked_read (insn.rs1 (), &source);
2936 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
2938 else if (insn.opcode () == riscv_insn::BEQ)
2941 regcache->cooked_read (insn.rs1 (), &src1);
2942 regcache->cooked_read (insn.rs2 (), &src2);
2944 next_pc = pc + insn.imm_signed ();
2946 else if (insn.opcode () == riscv_insn::BNE)
2949 regcache->cooked_read (insn.rs1 (), &src1);
2950 regcache->cooked_read (insn.rs2 (), &src2);
2952 next_pc = pc + insn.imm_signed ();
2954 else if (insn.opcode () == riscv_insn::BLT)
2957 regcache->cooked_read (insn.rs1 (), &src1);
2958 regcache->cooked_read (insn.rs2 (), &src2);
2960 next_pc = pc + insn.imm_signed ();
2962 else if (insn.opcode () == riscv_insn::BGE)
2965 regcache->cooked_read (insn.rs1 (), &src1);
2966 regcache->cooked_read (insn.rs2 (), &src2);
2968 next_pc = pc + insn.imm_signed ();
2970 else if (insn.opcode () == riscv_insn::BLTU)
2972 ULONGEST src1, src2;
2973 regcache->cooked_read (insn.rs1 (), &src1);
2974 regcache->cooked_read (insn.rs2 (), &src2);
2976 next_pc = pc + insn.imm_signed ();
2978 else if (insn.opcode () == riscv_insn::BGEU)
2980 ULONGEST src1, src2;
2981 regcache->cooked_read (insn.rs1 (), &src1);
2982 regcache->cooked_read (insn.rs2 (), &src2);
2984 next_pc = pc + insn.imm_signed ();
2990 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
2991 for the end of the sequence and put the breakpoint there. */
2994 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
2997 struct gdbarch *gdbarch = regcache->arch ();
2998 struct riscv_insn insn;
2999 CORE_ADDR cur_step_pc = pc;
3000 CORE_ADDR last_addr = 0;
3002 /* First instruction has to be a load reserved. */
3003 insn.decode (gdbarch, cur_step_pc);
3004 if (insn.opcode () != riscv_insn::LR)
3006 cur_step_pc = cur_step_pc + insn.length ();
3008 /* Next instruction should be branch to exit. */
3009 insn.decode (gdbarch, cur_step_pc);
3010 if (insn.opcode () != riscv_insn::BNE)
3012 last_addr = cur_step_pc + insn.imm_signed ();
3013 cur_step_pc = cur_step_pc + insn.length ();
3015 /* Next instruction should be store conditional. */
3016 insn.decode (gdbarch, cur_step_pc);
3017 if (insn.opcode () != riscv_insn::SC)
3019 cur_step_pc = cur_step_pc + insn.length ();
3021 /* Next instruction should be branch to start. */
3022 insn.decode (gdbarch, cur_step_pc);
3023 if (insn.opcode () != riscv_insn::BNE)
3025 if (pc != (cur_step_pc + insn.imm_signed ()))
3027 cur_step_pc = cur_step_pc + insn.length ();
3029 /* We should now be at the end of the sequence. */
3030 if (cur_step_pc != last_addr)
3033 *next_pc = cur_step_pc;
3037 /* This is called just before we want to resume the inferior, if we want to
3038 single-step it but there is no hardware or kernel single-step support. We
3039 find the target of the coming instruction and breakpoint it. */
3041 std::vector<CORE_ADDR>
3042 riscv_software_single_step (struct regcache *regcache)
3044 CORE_ADDR pc, next_pc;
3046 pc = regcache_read_pc (regcache);
3048 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
3051 next_pc = riscv_next_pc (regcache, pc);
3057 _initialize_riscv_tdep (void)
3059 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
3061 /* Add root prefix command for all "set debug riscv" and "show debug
3063 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
3064 _("RISC-V specific debug commands."),
3065 &setdebugriscvcmdlist, "set debug riscv ", 0,
3068 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
3069 _("RISC-V specific debug commands."),
3070 &showdebugriscvcmdlist, "show debug riscv ", 0,
3073 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
3074 &riscv_debug_breakpoints, _("\
3075 Set riscv breakpoint debugging."), _("\
3076 Show riscv breakpoint debugging."), _("\
3077 When non-zero, print debugging information for the riscv specific parts\n\
3078 of the breakpoint mechanism."),
3080 show_riscv_debug_variable,
3081 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3083 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
3084 &riscv_debug_infcall, _("\
3085 Set riscv inferior call debugging."), _("\
3086 Show riscv inferior call debugging."), _("\
3087 When non-zero, print debugging information for the riscv specific parts\n\
3088 of the inferior call mechanism."),
3090 show_riscv_debug_variable,
3091 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3093 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
3094 &riscv_debug_unwinder, _("\
3095 Set riscv stack unwinding debugging."), _("\
3096 Show riscv stack unwinding debugging."), _("\
3097 When non-zero, print debugging information for the riscv specific parts\n\
3098 of the stack unwinding mechanism."),
3100 show_riscv_debug_variable,
3101 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3103 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3104 add_prefix_cmd ("riscv", no_class, set_riscv_command,
3105 _("RISC-V specific commands."),
3106 &setriscvcmdlist, "set riscv ", 0, &setlist);
3108 add_prefix_cmd ("riscv", no_class, show_riscv_command,
3109 _("RISC-V specific commands."),
3110 &showriscvcmdlist, "show riscv ", 0, &showlist);
3113 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
3114 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
3115 &use_compressed_breakpoints,
3117 Set debugger's use of compressed breakpoints."), _(" \
3118 Show debugger's use of compressed breakpoints."), _("\
3119 Debugging compressed code requires compressed breakpoints to be used. If\n\
3120 left to 'auto' then gdb will use them if the existing instruction is a\n\
3121 compressed instruction. If that doesn't give the correct behavior, then\n\
3122 this option can be used."),
3124 show_use_compressed_breakpoints,