1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
60 /* The stack must be 16-byte aligned. */
61 #define SP_ALIGNMENT 16
63 /* The biggest alignment that the target supports. */
64 #define BIGGEST_ALIGNMENT 16
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Cached information about a frame. */
78 struct riscv_unwind_cache
80 /* The register from which we can calculate the frame base. This is
81 usually $sp or $fp. */
84 /* The offset from the current value in register FRAME_BASE_REG to the
85 actual frame base address. */
86 int frame_base_offset;
88 /* Information about previous register values. */
89 struct trad_frame_saved_reg *regs;
91 /* The id for this frame. */
92 struct frame_id this_id;
94 /* The base (stack) address for this frame. This is the stack pointer
95 value on entry to this frame before any adjustments are made. */
99 /* RISC-V specific register group for CSRs. */
101 static reggroup *csr_reggroup = NULL;
103 /* A set of registers that we expect to find in a tdesc_feature. These
104 are use in RISCV_GDBARCH_INIT when processing the target description. */
106 struct riscv_register_feature
108 /* Information for a single register. */
111 /* The GDB register number for this register. */
114 /* List of names for this register. The first name in this list is the
115 preferred name, the name GDB should use when describing this
117 std::vector <const char *> names;
119 /* When true this register is required in this feature set. */
123 /* The name for this feature. This is the name used to find this feature
124 within the target description. */
127 /* List of all the registers that we expect that we might find in this
129 std::vector <struct register_info> registers;
132 /* The general x-registers feature set. */
134 static const struct riscv_register_feature riscv_xreg_feature =
136 "org.gnu.gdb.riscv.cpu",
138 { RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, true },
139 { RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, true },
140 { RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, true },
141 { RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, true },
142 { RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, true },
143 { RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, true },
144 { RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, true },
145 { RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, true },
146 { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, true },
147 { RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, true },
148 { RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, true },
149 { RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, true },
150 { RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, true },
151 { RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, true },
152 { RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, true },
153 { RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, true },
154 { RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, true },
155 { RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, true },
156 { RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, true },
157 { RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, true },
158 { RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, true },
159 { RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, true },
160 { RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, true },
161 { RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, true },
162 { RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, true },
163 { RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, true },
164 { RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, true },
165 { RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, true },
166 { RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, true },
167 { RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, true },
168 { RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, true },
169 { RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, true },
170 { RISCV_ZERO_REGNUM + 32, { "pc" }, true }
174 /* The f-registers feature set. */
176 static const struct riscv_register_feature riscv_freg_feature =
178 "org.gnu.gdb.riscv.fpu",
180 { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, true },
181 { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, true },
182 { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" }, true },
183 { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" }, true },
184 { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" }, true },
185 { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true },
186 { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true },
187 { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true },
188 { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8", "s0" }, true },
189 { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true },
190 { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true },
191 { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true },
192 { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" }, true },
193 { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" }, true },
194 { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" }, true },
195 { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" }, true },
196 { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" }, true },
197 { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" }, true },
198 { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" }, true },
199 { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" }, true },
200 { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" }, true },
201 { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" }, true },
202 { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" }, true },
203 { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" }, true },
204 { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" }, true },
205 { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" }, true },
206 { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" }, true },
207 { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" }, true },
208 { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" }, true },
209 { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" }, true },
210 { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" }, true },
211 { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" }, true },
213 { RISCV_CSR_FFLAGS_REGNUM, { "fflags" }, true },
214 { RISCV_CSR_FRM_REGNUM, { "frm" }, true },
215 { RISCV_CSR_FCSR_REGNUM, { "fcsr" }, true },
220 /* Set of virtual registers. These are not physical registers on the
221 hardware, but might be available from the target. These are not pseudo
222 registers, reading these really does result in a register read from the
223 target, it is just that there might not be a physical register backing
226 static const struct riscv_register_feature riscv_virtual_feature =
228 "org.gnu.gdb.riscv.virtual",
230 { RISCV_PRIV_REGNUM, { "priv" }, false }
234 /* Feature set for CSRs. This set is NOT constant as the register names
235 list for each register is not complete. The aliases are computed
236 during RISCV_CREATE_CSR_ALIASES. */
238 static struct riscv_register_feature riscv_csr_feature =
240 "org.gnu.gdb.riscv.csr",
242 #define DECLARE_CSR(NAME,VALUE) \
243 { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
244 #include "opcode/riscv-opc.h"
249 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
250 to the name list for each register. */
253 riscv_create_csr_aliases ()
255 for (auto ® : riscv_csr_feature.registers)
257 int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
258 const char *alias = xstrprintf ("csr%d", csr_num);
259 reg.names.push_back (alias);
263 /* Controls whether we place compressed breakpoints or not. When in auto
264 mode GDB tries to determine if the target supports compressed
265 breakpoints, and uses them if it does. */
267 static enum auto_boolean use_compressed_breakpoints;
269 /* The show callback for 'show riscv use-compressed-breakpoints'. */
272 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
273 struct cmd_list_element *c,
276 fprintf_filtered (file,
277 _("Debugger's use of compressed breakpoints is set "
281 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
283 static struct cmd_list_element *setriscvcmdlist = NULL;
284 static struct cmd_list_element *showriscvcmdlist = NULL;
286 /* The show callback for the 'show riscv' prefix command. */
289 show_riscv_command (const char *args, int from_tty)
291 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
294 /* The set callback for the 'set riscv' prefix command. */
297 set_riscv_command (const char *args, int from_tty)
300 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
301 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
304 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
306 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
307 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
309 /* The show callback for the 'show debug riscv' prefix command. */
312 show_debug_riscv_command (const char *args, int from_tty)
314 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
317 /* The set callback for the 'set debug riscv' prefix command. */
320 set_debug_riscv_command (const char *args, int from_tty)
323 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
324 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
327 /* The show callback for all 'show debug riscv VARNAME' variables. */
330 show_riscv_debug_variable (struct ui_file *file, int from_tty,
331 struct cmd_list_element *c,
334 fprintf_filtered (file,
335 _("RiscV debug variable `%s' is set to: %s\n"),
339 /* When this is set to non-zero debugging information about breakpoint
340 kinds will be printed. */
342 static unsigned int riscv_debug_breakpoints = 0;
344 /* When this is set to non-zero debugging information about inferior calls
347 static unsigned int riscv_debug_infcall = 0;
349 /* When this is set to non-zero debugging information about stack unwinding
352 static unsigned int riscv_debug_unwinder = 0;
354 /* When this is set to non-zero debugging information about gdbarch
355 initialisation will be printed. */
357 static unsigned int riscv_debug_gdbarch = 0;
359 /* See riscv-tdep.h. */
362 riscv_isa_xlen (struct gdbarch *gdbarch)
364 return gdbarch_tdep (gdbarch)->features.xlen;
367 /* See riscv-tdep.h. */
370 riscv_isa_flen (struct gdbarch *gdbarch)
372 return gdbarch_tdep (gdbarch)->features.flen;
375 /* Return true if the target for GDBARCH has floating point hardware. */
378 riscv_has_fp_regs (struct gdbarch *gdbarch)
380 return (riscv_isa_flen (gdbarch) > 0);
383 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
386 riscv_has_fp_abi (struct gdbarch *gdbarch)
388 return gdbarch_tdep (gdbarch)->features.hw_float_abi;
391 /* Return true if REGNO is a floating pointer register. */
394 riscv_is_fp_regno_p (int regno)
396 return (regno >= RISCV_FIRST_FP_REGNUM
397 && regno <= RISCV_LAST_FP_REGNUM);
400 /* Implement the breakpoint_kind_from_pc gdbarch method. */
403 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
405 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
407 bool unaligned_p = false;
410 /* Some targets don't support unaligned reads. The address can only
411 be unaligned if the C extension is supported. So it is safe to
412 use a compressed breakpoint in this case. */
417 /* Read the opcode byte to determine the instruction length. */
418 read_code (*pcptr, buf, 1);
421 if (riscv_debug_breakpoints)
423 const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
424 ? "C.EBREAK" : "EBREAK");
426 fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ",
427 bp, paddress (gdbarch, *pcptr));
429 fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n");
431 fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n",
432 riscv_insn_length (buf[0]));
434 if (unaligned_p || riscv_insn_length (buf[0]) == 2)
439 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
445 /* Implement the sw_breakpoint_from_kind gdbarch method. */
447 static const gdb_byte *
448 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
450 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
451 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
461 gdb_assert_not_reached (_("unhandled breakpoint kind"));
465 /* Callback function for user_reg_add. */
467 static struct value *
468 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
470 const int *reg_p = (const int *) baton;
471 return value_of_register (*reg_p, frame);
474 /* Implement the register_name gdbarch method. This is used instead of
475 the function supplied by calling TDESC_USE_REGISTERS so that we can
476 ensure the preferred names are offered. */
479 riscv_register_name (struct gdbarch *gdbarch, int regnum)
481 /* Lookup the name through the target description. If we get back NULL
482 then this is an unknown register. If we do get a name back then we
483 look up the registers preferred name below. */
484 const char *name = tdesc_register_name (gdbarch, regnum);
485 if (name == NULL || name[0] == '\0')
488 if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM)
490 gdb_assert (regnum < riscv_xreg_feature.registers.size ());
491 return riscv_xreg_feature.registers[regnum].names[0];
494 if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
496 if (riscv_has_fp_regs (gdbarch))
498 regnum -= RISCV_FIRST_FP_REGNUM;
499 gdb_assert (regnum < riscv_freg_feature.registers.size ());
500 return riscv_freg_feature.registers[regnum].names[0];
506 /* Check that there's no gap between the set of registers handled above,
507 and the set of registers handled next. */
508 gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM);
510 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
512 #define DECLARE_CSR(NAME,VALUE) \
513 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
517 #include "opcode/riscv-opc.h"
522 if (regnum == RISCV_PRIV_REGNUM)
525 /* It is possible that that the target provides some registers that GDB
526 is unaware of, in that case just return the NAME from the target
531 /* Construct a type for 64-bit FP registers. */
534 riscv_fpreg_d_type (struct gdbarch *gdbarch)
536 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
538 if (tdep->riscv_fpreg_d_type == nullptr)
540 const struct builtin_type *bt = builtin_type (gdbarch);
542 /* The type we're building is this: */
544 union __gdb_builtin_type_fpreg_d
553 t = arch_composite_type (gdbarch,
554 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
555 append_composite_type_field (t, "float", bt->builtin_float);
556 append_composite_type_field (t, "double", bt->builtin_double);
558 TYPE_NAME (t) = "builtin_type_fpreg_d";
559 tdep->riscv_fpreg_d_type = t;
562 return tdep->riscv_fpreg_d_type;
565 /* Implement the register_type gdbarch method. This is installed as an
566 for the override setup by TDESC_USE_REGISTERS, for most registers we
567 delegate the type choice to the target description, but for a few
568 registers we try to improve the types if the target description has
569 taken a simplistic approach. */
572 riscv_register_type (struct gdbarch *gdbarch, int regnum)
574 struct type *type = tdesc_register_type (gdbarch, regnum);
575 int xlen = riscv_isa_xlen (gdbarch);
577 /* We want to perform some specific type "fixes" in cases where we feel
578 that we really can do better than the target description. For all
579 other cases we just return what the target description says. */
580 if (riscv_is_fp_regno_p (regnum))
582 /* This spots the case for RV64 where the double is defined as
583 either 'ieee_double' or 'float' (which is the generic name that
584 converts to 'double' on 64-bit). In these cases its better to
585 present the registers using a union type. */
586 int flen = riscv_isa_flen (gdbarch);
588 && TYPE_CODE (type) == TYPE_CODE_FLT
589 && TYPE_LENGTH (type) == flen
590 && (strcmp (TYPE_NAME (type), "builtin_type_ieee_double") == 0
591 || strcmp (TYPE_NAME (type), "double") == 0))
592 type = riscv_fpreg_d_type (gdbarch);
595 if ((regnum == gdbarch_pc_regnum (gdbarch)
596 || regnum == RISCV_RA_REGNUM
597 || regnum == RISCV_FP_REGNUM
598 || regnum == RISCV_SP_REGNUM
599 || regnum == RISCV_GP_REGNUM
600 || regnum == RISCV_TP_REGNUM)
601 && TYPE_CODE (type) == TYPE_CODE_INT
602 && TYPE_LENGTH (type) == xlen)
604 /* This spots the case where some interesting registers are defined
605 as simple integers of the expected size, we force these registers
606 to be pointers as we believe that is more useful. */
607 if (regnum == gdbarch_pc_regnum (gdbarch)
608 || regnum == RISCV_RA_REGNUM)
609 type = builtin_type (gdbarch)->builtin_func_ptr;
610 else if (regnum == RISCV_FP_REGNUM
611 || regnum == RISCV_SP_REGNUM
612 || regnum == RISCV_GP_REGNUM
613 || regnum == RISCV_TP_REGNUM)
614 type = builtin_type (gdbarch)->builtin_data_ptr;
620 /* Helper for riscv_print_registers_info, prints info for a single register
624 riscv_print_one_register_info (struct gdbarch *gdbarch,
625 struct ui_file *file,
626 struct frame_info *frame,
629 const char *name = gdbarch_register_name (gdbarch, regnum);
631 struct type *regtype;
632 int print_raw_format;
633 enum tab_stops { value_column_1 = 15 };
635 fputs_filtered (name, file);
636 print_spaces_filtered (value_column_1 - strlen (name), file);
640 val = value_of_register (regnum, frame);
641 regtype = value_type (val);
643 CATCH (ex, RETURN_MASK_ERROR)
645 /* Handle failure to read a register without interrupting the entire
646 'info registers' flow. */
647 fprintf_filtered (file, "%s\n", ex.message);
652 print_raw_format = (value_entirely_available (val)
653 && !value_optimized_out (val));
655 if (TYPE_CODE (regtype) == TYPE_CODE_FLT
656 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
657 && TYPE_NFIELDS (regtype) == 2
658 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
659 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
660 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
661 && TYPE_NFIELDS (regtype) == 3
662 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
663 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
664 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
666 struct value_print_options opts;
667 const gdb_byte *valaddr = value_contents_for_printing (val);
668 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
670 get_user_print_options (&opts);
674 value_embedded_offset (val), 0,
675 file, 0, val, &opts, current_language);
677 if (print_raw_format)
679 fprintf_filtered (file, "\t(raw ");
680 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
682 fprintf_filtered (file, ")");
687 struct value_print_options opts;
689 /* Print the register in hex. */
690 get_formatted_print_options (&opts, 'x');
693 value_embedded_offset (val), 0,
694 file, 0, val, &opts, current_language);
696 if (print_raw_format)
698 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
701 int size = register_size (gdbarch, regnum);
704 d = value_as_long (val);
706 fprintf_filtered (file,
707 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
708 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
709 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
710 (int) ((d >> (xlen - 1)) & 0x1),
711 (int) ((d >> 24) & 0x1f),
712 (int) ((d >> 19) & 0x1),
713 (int) ((d >> 18) & 0x1),
714 (int) ((d >> 17) & 0x1),
715 (int) ((d >> 15) & 0x3),
716 (int) ((d >> 13) & 0x3),
717 (int) ((d >> 11) & 0x3),
718 (int) ((d >> 9) & 0x3),
719 (int) ((d >> 8) & 0x1),
720 (int) ((d >> 7) & 0x1),
721 (int) ((d >> 6) & 0x1),
722 (int) ((d >> 5) & 0x1),
723 (int) ((d >> 4) & 0x1),
724 (int) ((d >> 3) & 0x1),
725 (int) ((d >> 2) & 0x1),
726 (int) ((d >> 1) & 0x1),
727 (int) ((d >> 0) & 0x1));
729 else if (regnum == RISCV_CSR_MISA_REGNUM)
735 d = value_as_long (val);
739 for (; base > 0; base--)
741 fprintf_filtered (file, "\tRV%d", xlen);
743 for (i = 0; i < 26; i++)
746 fprintf_filtered (file, "%c", 'A' + i);
749 else if (regnum == RISCV_CSR_FCSR_REGNUM
750 || regnum == RISCV_CSR_FFLAGS_REGNUM
751 || regnum == RISCV_CSR_FRM_REGNUM)
755 d = value_as_long (val);
757 fprintf_filtered (file, "\t");
758 if (regnum != RISCV_CSR_FRM_REGNUM)
759 fprintf_filtered (file,
760 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
761 (int) ((d >> 5) & 0x7),
762 (int) ((d >> 4) & 0x1),
763 (int) ((d >> 3) & 0x1),
764 (int) ((d >> 2) & 0x1),
765 (int) ((d >> 1) & 0x1),
766 (int) ((d >> 0) & 0x1));
768 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
770 static const char * const sfrm[] =
772 "RNE (round to nearest; ties to even)",
773 "RTZ (Round towards zero)",
774 "RDN (Round down towards -INF)",
775 "RUP (Round up towards +INF)",
776 "RMM (Round to nearest; ties to max magnitude)",
779 "dynamic rounding mode",
781 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
782 ? (d >> 5) : d) & 0x3;
784 fprintf_filtered (file, "%sFRM:%i [%s]",
785 (regnum == RISCV_CSR_FCSR_REGNUM
790 else if (regnum == RISCV_PRIV_REGNUM)
795 d = value_as_long (val);
800 static const char * const sprv[] =
807 fprintf_filtered (file, "\tprv:%d [%s]",
811 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
815 /* If not a vector register, print it also according to its
817 if (TYPE_VECTOR (regtype) == 0)
819 get_user_print_options (&opts);
821 fprintf_filtered (file, "\t");
823 value_embedded_offset (val), 0,
824 file, 0, val, &opts, current_language);
829 fprintf_filtered (file, "\n");
832 /* Return true if REGNUM is a valid CSR register. The CSR register space
833 is sparsely populated, so not every number is a named CSR. */
836 riscv_is_regnum_a_named_csr (int regnum)
838 gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
839 && regnum <= RISCV_LAST_CSR_REGNUM);
843 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
844 #include "opcode/riscv-opc.h"
853 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
857 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
858 struct reggroup *reggroup)
860 /* Used by 'info registers' and 'info registers <groupname>'. */
862 if (gdbarch_register_name (gdbarch, regnum) == NULL
863 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
866 if (regnum > RISCV_LAST_REGNUM)
868 int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
872 return default_register_reggroup_p (gdbarch, regnum, reggroup);
875 if (reggroup == all_reggroup)
877 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
879 if (riscv_is_regnum_a_named_csr (regnum))
883 else if (reggroup == float_reggroup)
884 return (riscv_is_fp_regno_p (regnum)
885 || regnum == RISCV_CSR_FCSR_REGNUM
886 || regnum == RISCV_CSR_FFLAGS_REGNUM
887 || regnum == RISCV_CSR_FRM_REGNUM);
888 else if (reggroup == general_reggroup)
889 return regnum < RISCV_FIRST_FP_REGNUM;
890 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
892 if (riscv_has_fp_regs (gdbarch))
893 return regnum <= RISCV_LAST_FP_REGNUM;
895 return regnum < RISCV_FIRST_FP_REGNUM;
897 else if (reggroup == system_reggroup || reggroup == csr_reggroup)
899 if (regnum == RISCV_PRIV_REGNUM)
901 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
903 if (riscv_is_regnum_a_named_csr (regnum))
907 else if (reggroup == vector_reggroup)
913 /* Implement the print_registers_info gdbarch method. This is used by
914 'info registers' and 'info all-registers'. */
917 riscv_print_registers_info (struct gdbarch *gdbarch,
918 struct ui_file *file,
919 struct frame_info *frame,
920 int regnum, int print_all)
924 /* Print one specified register. */
925 if (gdbarch_register_name (gdbarch, regnum) == NULL
926 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
927 error (_("Not a valid register for the current processor type"));
928 riscv_print_one_register_info (gdbarch, file, frame, regnum);
932 struct reggroup *reggroup;
935 reggroup = all_reggroup;
937 reggroup = general_reggroup;
939 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
941 /* Zero never changes, so might as well hide by default. */
942 if (regnum == RISCV_ZERO_REGNUM && !print_all)
945 /* Registers with no name are not valid on this ISA. */
946 if (gdbarch_register_name (gdbarch, regnum) == NULL
947 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
950 /* Is the register in the group we're interested in? */
951 if (!gdbarch_register_reggroup_p (gdbarch, regnum, reggroup))
954 riscv_print_one_register_info (gdbarch, file, frame, regnum);
959 /* Class that handles one decoded RiscV instruction. */
965 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
968 /* Unknown value is used at initialisation time. */
971 /* These instructions are all the ones we are interested in during the
981 /* These are needed for software breakopint support. */
990 /* These are needed for stepping over atomic sequences. */
994 /* Other instructions are not interesting during the prologue scan, and
1009 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1011 /* Get the length of the instruction in bytes. */
1013 { return m_length; }
1015 /* Get the opcode for this instruction. */
1016 enum opcode opcode () const
1017 { return m_opcode; }
1019 /* Get destination register field for this instruction. This is only
1020 valid if the OPCODE implies there is such a field for this
1025 /* Get the RS1 register field for this instruction. This is only valid
1026 if the OPCODE implies there is such a field for this instruction. */
1030 /* Get the RS2 register field for this instruction. This is only valid
1031 if the OPCODE implies there is such a field for this instruction. */
1035 /* Get the immediate for this instruction in signed form. This is only
1036 valid if the OPCODE implies there is such a field for this
1038 int imm_signed () const
1043 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1044 int decode_register_index (unsigned long opcode, int offset)
1046 return (opcode >> offset) & 0x1F;
1049 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1050 int decode_register_index_short (unsigned long opcode, int offset)
1052 return ((opcode >> offset) & 0x7) + 8;
1055 /* Helper for DECODE, decode 32-bit R-type instruction. */
1056 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1059 m_rd = decode_register_index (ival, OP_SH_RD);
1060 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1061 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1064 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1065 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1068 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1069 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1072 /* Helper for DECODE, decode 32-bit I-type instruction. */
1073 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1076 m_rd = decode_register_index (ival, OP_SH_RD);
1077 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1078 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1081 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1082 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1085 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1086 m_imm.s = EXTRACT_RVC_IMM (ival);
1089 /* Helper for DECODE, decode 32-bit S-type instruction. */
1090 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1093 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1094 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1095 m_imm.s = EXTRACT_STYPE_IMM (ival);
1098 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1099 encoding is different for each CS format instruction, so extracting
1100 the immediate is left up to the caller, who should pass the extracted
1101 immediate value through in IMM. */
1102 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1106 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1107 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1110 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1111 encoding is different for each CSS format instruction, so extracting
1112 the immediate is left up to the caller, who should pass the extracted
1113 immediate value through in IMM. */
1114 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1118 m_rs1 = RISCV_SP_REGNUM;
1119 /* Not a compressed register number in this case. */
1120 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1123 /* Helper for DECODE, decode 32-bit U-type instruction. */
1124 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1127 m_rd = decode_register_index (ival, OP_SH_RD);
1128 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1131 /* Helper for DECODE, decode 32-bit J-type instruction. */
1132 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1135 m_rd = decode_register_index (ival, OP_SH_RD);
1136 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1139 /* Helper for DECODE, decode 32-bit J-type instruction. */
1140 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1143 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1146 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1149 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1150 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1151 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1154 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1157 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1158 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1161 /* Fetch instruction from target memory at ADDR, return the content of
1162 the instruction, and update LEN with the instruction length. */
1163 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1164 CORE_ADDR addr, int *len);
1166 /* The length of the instruction in bytes. Should be 2 or 4. */
1169 /* The instruction opcode. */
1170 enum opcode m_opcode;
1172 /* The three possible registers an instruction might reference. Not
1173 every instruction fills in all of these registers. Which fields are
1174 valid depends on the opcode. The naming of these fields matches the
1175 naming in the riscv isa manual. */
1180 /* Possible instruction immediate. This is only valid if the instruction
1181 format contains an immediate, not all instruction, whether this is
1182 valid depends on the opcode. Despite only having one format for now
1183 the immediate is packed into a union, later instructions might require
1184 an unsigned formatted immediate, having the union in place now will
1185 reduce the need for code churn later. */
1186 union riscv_insn_immediate
1188 riscv_insn_immediate ()
1198 /* Fetch instruction from target memory at ADDR, return the content of the
1199 instruction, and update LEN with the instruction length. */
1202 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1203 CORE_ADDR addr, int *len)
1205 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1207 int instlen, status;
1209 /* All insns are at least 16 bits. */
1210 status = target_read_memory (addr, buf, 2);
1212 memory_error (TARGET_XFER_E_IO, addr);
1214 /* If we need more, grab it now. */
1215 instlen = riscv_insn_length (buf[0]);
1216 gdb_assert (instlen <= sizeof (buf));
1221 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1223 memory_error (TARGET_XFER_E_IO, addr + 2);
1226 return extract_unsigned_integer (buf, instlen, byte_order);
1229 /* Fetch from target memory an instruction at PC and decode it. This can
1230 throw an error if the memory access fails, callers are responsible for
1231 handling this error if that is appropriate. */
1234 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1238 /* Fetch the instruction, and the instructions length. */
1239 ival = fetch_instruction (gdbarch, pc, &m_length);
1243 if (is_add_insn (ival))
1244 decode_r_type_insn (ADD, ival);
1245 else if (is_addw_insn (ival))
1246 decode_r_type_insn (ADDW, ival);
1247 else if (is_addi_insn (ival))
1248 decode_i_type_insn (ADDI, ival);
1249 else if (is_addiw_insn (ival))
1250 decode_i_type_insn (ADDIW, ival);
1251 else if (is_auipc_insn (ival))
1252 decode_u_type_insn (AUIPC, ival);
1253 else if (is_lui_insn (ival))
1254 decode_u_type_insn (LUI, ival);
1255 else if (is_sd_insn (ival))
1256 decode_s_type_insn (SD, ival);
1257 else if (is_sw_insn (ival))
1258 decode_s_type_insn (SW, ival);
1259 else if (is_jal_insn (ival))
1260 decode_j_type_insn (JAL, ival);
1261 else if (is_jalr_insn (ival))
1262 decode_i_type_insn (JALR, ival);
1263 else if (is_beq_insn (ival))
1264 decode_b_type_insn (BEQ, ival);
1265 else if (is_bne_insn (ival))
1266 decode_b_type_insn (BNE, ival);
1267 else if (is_blt_insn (ival))
1268 decode_b_type_insn (BLT, ival);
1269 else if (is_bge_insn (ival))
1270 decode_b_type_insn (BGE, ival);
1271 else if (is_bltu_insn (ival))
1272 decode_b_type_insn (BLTU, ival);
1273 else if (is_bgeu_insn (ival))
1274 decode_b_type_insn (BGEU, ival);
1275 else if (is_lr_w_insn (ival))
1276 decode_r_type_insn (LR, ival);
1277 else if (is_lr_d_insn (ival))
1278 decode_r_type_insn (LR, ival);
1279 else if (is_sc_w_insn (ival))
1280 decode_r_type_insn (SC, ival);
1281 else if (is_sc_d_insn (ival))
1282 decode_r_type_insn (SC, ival);
1284 /* None of the other fields are valid in this case. */
1287 else if (m_length == 2)
1289 int xlen = riscv_isa_xlen (gdbarch);
1291 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1292 C_JALR. So must try to match C_JALR first as it has more bits in
1294 if (is_c_jalr_insn (ival))
1295 decode_cr_type_insn (JALR, ival);
1296 else if (is_c_add_insn (ival))
1297 decode_cr_type_insn (ADD, ival);
1298 /* C_ADDW is RV64 and RV128 only. */
1299 else if (xlen != 4 && is_c_addw_insn (ival))
1300 decode_cr_type_insn (ADDW, ival);
1301 else if (is_c_addi_insn (ival))
1302 decode_ci_type_insn (ADDI, ival);
1303 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1304 only and C_JAL is RV32 only. */
1305 else if (xlen != 4 && is_c_addiw_insn (ival))
1306 decode_ci_type_insn (ADDIW, ival);
1307 else if (xlen == 4 && is_c_jal_insn (ival))
1308 decode_cj_type_insn (JAL, ival);
1309 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1310 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1312 else if (is_c_addi16sp_insn (ival))
1315 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1316 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1318 else if (is_c_addi4spn_insn (ival))
1321 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1322 m_rs1 = RISCV_SP_REGNUM;
1323 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1325 else if (is_c_lui_insn (ival))
1328 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1329 m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
1331 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1332 and C_FSW is RV32 only. */
1333 else if (xlen != 4 && is_c_sd_insn (ival))
1334 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
1335 else if (is_c_sw_insn (ival))
1336 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1337 else if (is_c_swsp_insn (ival))
1338 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1339 else if (xlen != 4 && is_c_sdsp_insn (ival))
1340 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
1341 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1342 So must try to match C_JR first as it ahs more bits in mask. */
1343 else if (is_c_jr_insn (ival))
1344 decode_cr_type_insn (JALR, ival);
1345 else if (is_c_j_insn (ival))
1346 decode_cj_type_insn (JAL, ival);
1347 else if (is_c_beqz_insn (ival))
1348 decode_cb_type_insn (BEQ, ival);
1349 else if (is_c_bnez_insn (ival))
1350 decode_cb_type_insn (BNE, ival);
1352 /* None of the other fields of INSN are valid in this case. */
1356 internal_error (__FILE__, __LINE__,
1357 _("unable to decode %d byte instructions in "
1358 "prologue at %s"), m_length,
1359 core_addr_to_string (pc));
1362 /* The prologue scanner. This is currently only used for skipping the
1363 prologue of a function when the DWARF information is not sufficient.
1364 However, it is written with filling of the frame cache in mind, which
1365 is why different groups of stack setup instructions are split apart
1366 during the core of the inner loop. In the future, the intention is to
1367 extend this function to fully support building up a frame cache that
1368 can unwind register values when there is no DWARF information. */
1371 riscv_scan_prologue (struct gdbarch *gdbarch,
1372 CORE_ADDR start_pc, CORE_ADDR end_pc,
1373 struct riscv_unwind_cache *cache)
1375 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1376 CORE_ADDR end_prologue_addr = 0;
1378 /* Find an upper limit on the function prologue using the debug
1379 information. If the debug information could not be used to provide
1380 that bound, then use an arbitrary large number as the upper bound. */
1381 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1382 if (after_prologue_pc == 0)
1383 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1384 if (after_prologue_pc < end_pc)
1385 end_pc = after_prologue_pc;
1387 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1388 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1389 regs[regno] = pv_register (regno, 0);
1390 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1392 if (riscv_debug_unwinder)
1395 "Prologue scan for function starting at %s (limit %s)\n",
1396 core_addr_to_string (start_pc),
1397 core_addr_to_string (end_pc));
1399 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1401 struct riscv_insn insn;
1403 /* Decode the current instruction, and decide where the next
1404 instruction lives based on the size of this instruction. */
1405 insn.decode (gdbarch, cur_pc);
1406 gdb_assert (insn.length () > 0);
1407 next_pc = cur_pc + insn.length ();
1409 /* Look for common stack adjustment insns. */
1410 if ((insn.opcode () == riscv_insn::ADDI
1411 || insn.opcode () == riscv_insn::ADDIW)
1412 && insn.rd () == RISCV_SP_REGNUM
1413 && insn.rs1 () == RISCV_SP_REGNUM)
1415 /* Handle: addi sp, sp, -i
1416 or: addiw sp, sp, -i */
1417 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1418 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1420 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1422 else if ((insn.opcode () == riscv_insn::SW
1423 || insn.opcode () == riscv_insn::SD)
1424 && (insn.rs1 () == RISCV_SP_REGNUM
1425 || insn.rs1 () == RISCV_FP_REGNUM))
1427 /* Handle: sw reg, offset(sp)
1428 or: sd reg, offset(sp)
1429 or: sw reg, offset(s0)
1430 or: sd reg, offset(s0) */
1431 /* Instruction storing a register onto the stack. */
1432 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1433 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1434 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1435 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1438 else if (insn.opcode () == riscv_insn::ADDI
1439 && insn.rd () == RISCV_FP_REGNUM
1440 && insn.rs1 () == RISCV_SP_REGNUM)
1442 /* Handle: addi s0, sp, size */
1443 /* Instructions setting up the frame pointer. */
1444 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1445 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1447 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1449 else if ((insn.opcode () == riscv_insn::ADD
1450 || insn.opcode () == riscv_insn::ADDW)
1451 && insn.rd () == RISCV_FP_REGNUM
1452 && insn.rs1 () == RISCV_SP_REGNUM
1453 && insn.rs2 () == RISCV_ZERO_REGNUM)
1455 /* Handle: add s0, sp, 0
1456 or: addw s0, sp, 0 */
1457 /* Instructions setting up the frame pointer. */
1458 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1459 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1460 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1462 else if ((insn.opcode () == riscv_insn::ADDI
1463 && insn.rd () == RISCV_ZERO_REGNUM
1464 && insn.rs1 () == RISCV_ZERO_REGNUM
1465 && insn.imm_signed () == 0))
1467 /* Handle: add x0, x0, 0 (NOP) */
1469 else if (insn.opcode () == riscv_insn::AUIPC)
1471 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1472 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1474 else if (insn.opcode () == riscv_insn::LUI)
1476 /* Handle: lui REG, n
1477 Where REG is not gp register. */
1478 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1479 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1481 else if (insn.opcode () == riscv_insn::ADDI)
1483 /* Handle: addi REG1, REG2, IMM */
1484 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1485 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1487 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1489 else if (insn.opcode () == riscv_insn::ADD)
1491 /* Handle: addi REG1, REG2, IMM */
1492 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1493 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1494 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1495 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1499 end_prologue_addr = cur_pc;
1504 if (end_prologue_addr == 0)
1505 end_prologue_addr = cur_pc;
1507 if (riscv_debug_unwinder)
1508 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1509 core_addr_to_string (end_prologue_addr));
1513 /* Figure out if it is a frame pointer or just a stack pointer. Also
1514 the offset held in the pv_t is from the original register value to
1515 the current value, which for a grows down stack means a negative
1516 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1517 from the current value to the original value. */
1518 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1520 cache->frame_base_reg = RISCV_FP_REGNUM;
1521 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1525 cache->frame_base_reg = RISCV_SP_REGNUM;
1526 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1529 /* Assign offset from old SP to all saved registers. As we don't
1530 have the previous value for the frame base register at this
1531 point, we store the offset as the address in the trad_frame, and
1532 then convert this to an actual address later. */
1533 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1536 if (stack.find_reg (gdbarch, i, &offset))
1538 if (riscv_debug_unwinder)
1539 fprintf_unfiltered (gdb_stdlog,
1540 "Register $%s at stack offset %ld\n",
1541 gdbarch_register_name (gdbarch, i),
1543 trad_frame_set_addr (cache->regs, i, offset);
1548 return end_prologue_addr;
1551 /* Implement the riscv_skip_prologue gdbarch method. */
1554 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1556 CORE_ADDR func_addr;
1558 /* See if we can determine the end of the prologue via the symbol
1559 table. If so, then return either PC, or the PC after the
1560 prologue, whichever is greater. */
1561 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1563 CORE_ADDR post_prologue_pc
1564 = skip_prologue_using_sal (gdbarch, func_addr);
1566 if (post_prologue_pc != 0)
1567 return std::max (pc, post_prologue_pc);
1570 /* Can't determine prologue from the symbol table, need to examine
1571 instructions. Pass -1 for the end address to indicate the prologue
1572 scanner can scan as far as it needs to find the end of the prologue. */
1573 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1576 /* Implement the gdbarch push dummy code callback. */
1579 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1580 CORE_ADDR funaddr, struct value **args, int nargs,
1581 struct type *value_type, CORE_ADDR *real_pc,
1582 CORE_ADDR *bp_addr, struct regcache *regcache)
1584 /* Allocate space for a breakpoint, and keep the stack correctly
1592 /* Compute the alignment of the type T. Used while setting up the
1593 arguments for a dummy call. */
1596 riscv_type_alignment (struct type *t)
1598 t = check_typedef (t);
1599 switch (TYPE_CODE (t))
1602 error (_("Could not compute alignment of type"));
1604 case TYPE_CODE_RVALUE_REF:
1606 case TYPE_CODE_ENUM:
1610 case TYPE_CODE_CHAR:
1611 case TYPE_CODE_BOOL:
1612 return TYPE_LENGTH (t);
1614 case TYPE_CODE_ARRAY:
1615 if (TYPE_VECTOR (t))
1616 return std::min (TYPE_LENGTH (t), (unsigned) BIGGEST_ALIGNMENT);
1619 case TYPE_CODE_COMPLEX:
1620 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1622 case TYPE_CODE_STRUCT:
1623 case TYPE_CODE_UNION:
1628 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1630 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1632 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1642 /* Holds information about a single argument either being passed to an
1643 inferior function, or returned from an inferior function. This includes
1644 information about the size, type, etc of the argument, and also
1645 information about how the argument will be passed (or returned). */
1647 struct riscv_arg_info
1649 /* Contents of the argument. */
1650 const gdb_byte *contents;
1652 /* Length of argument. */
1655 /* Alignment required for an argument of this type. */
1658 /* The type for this argument. */
1661 /* Each argument can have either 1 or 2 locations assigned to it. Each
1662 location describes where part of the argument will be placed. The
1663 second location is valid based on the LOC_TYPE and C_LENGTH fields
1664 of the first location (which is always valid). */
1667 /* What type of location this is. */
1670 /* Argument passed in a register. */
1673 /* Argument passed as an on stack argument. */
1676 /* Argument passed by reference. The second location is always
1677 valid for a BY_REF argument, and describes where the address
1678 of the BY_REF argument should be placed. */
1682 /* Information that depends on the location type. */
1685 /* Which register number to use. */
1688 /* The offset into the stack region. */
1692 /* The length of contents covered by this location. If this is less
1693 than the total length of the argument, then the second location
1694 will be valid, and will describe where the rest of the argument
1698 /* The offset within CONTENTS for this part of the argument. Will
1699 always be 0 for the first part. For the second part of the
1700 argument, this might be the C_LENGTH value of the first part,
1701 however, if we are passing a structure in two registers, and there's
1702 is padding between the first and second field, then this offset
1703 might be greater than the length of the first argument part. When
1704 the second argument location is not holding part of the argument
1705 value, but is instead holding the address of a reference argument,
1706 then this offset will be set to 0. */
1710 /* TRUE if this is an unnamed argument. */
1714 /* Information about a set of registers being used for passing arguments as
1715 part of a function call. The register set must be numerically
1716 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1717 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1719 struct riscv_arg_reg
1721 riscv_arg_reg (int first, int last)
1722 : next_regnum (first),
1728 /* The GDB register number to use in this set. */
1731 /* The last GDB register number to use in this set. */
1735 /* Arguments can be passed as on stack arguments, or by reference. The
1736 on stack arguments must be in a continuous region starting from $sp,
1737 while the by reference arguments can be anywhere, but we'll put them
1738 on the stack after (at higher address) the on stack arguments.
1740 This might not be the right approach to take. The ABI is clear that
1741 an argument passed by reference can be modified by the callee, which
1742 us placing the argument (temporarily) onto the stack will not achieve
1743 (changes will be lost). There's also the possibility that very large
1744 arguments could overflow the stack.
1746 This struct is used to track offset into these two areas for where
1747 arguments are to be placed. */
1748 struct riscv_memory_offsets
1750 riscv_memory_offsets ()
1757 /* Offset into on stack argument area. */
1760 /* Offset into the pass by reference area. */
1764 /* Holds information about where arguments to a call will be placed. This
1765 is updated as arguments are added onto the call, and can be used to
1766 figure out where the next argument should be placed. */
1768 struct riscv_call_info
1770 riscv_call_info (struct gdbarch *gdbarch)
1771 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1772 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1774 xlen = riscv_isa_xlen (gdbarch);
1775 flen = riscv_isa_flen (gdbarch);
1777 /* Disable use of floating point registers if needed. */
1778 if (!riscv_has_fp_abi (gdbarch))
1779 float_regs.next_regnum = float_regs.last_regnum + 1;
1782 /* Track the memory areas used for holding in-memory arguments to a
1784 struct riscv_memory_offsets memory;
1786 /* Holds information about the next integer register to use for passing
1788 struct riscv_arg_reg int_regs;
1790 /* Holds information about the next floating point register to use for
1791 passing an argument. */
1792 struct riscv_arg_reg float_regs;
1794 /* The XLEN and FLEN are copied in to this structure for convenience, and
1795 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1800 /* Return the number of registers available for use as parameters in the
1801 register set REG. Returned value can be 0 or more. */
1804 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1806 if (reg->next_regnum > reg->last_regnum)
1809 return (reg->last_regnum - reg->next_regnum + 1);
1812 /* If there is at least one register available in the register set REG then
1813 the next register from REG is assigned to LOC and the length field of
1814 LOC is updated to LENGTH. The register set REG is updated to indicate
1815 that the assigned register is no longer available and the function
1818 If there are no registers available in REG then the function returns
1819 false, and LOC and REG are unchanged. */
1822 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1823 struct riscv_arg_reg *reg,
1824 int length, int offset)
1826 if (reg->next_regnum <= reg->last_regnum)
1828 loc->loc_type = riscv_arg_info::location::in_reg;
1829 loc->loc_data.regno = reg->next_regnum;
1831 loc->c_length = length;
1832 loc->c_offset = offset;
1839 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1840 record that an area of stack has been used to hold the parameter
1843 The length field of LOC is updated to LENGTH, the length of the
1844 parameter being stored, and ALIGN is the alignment required by the
1845 parameter, which will affect how memory is allocated out of MEMORY. */
1848 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1849 struct riscv_memory_offsets *memory,
1850 int length, int align)
1852 loc->loc_type = riscv_arg_info::location::on_stack;
1854 = align_up (memory->arg_offset, align);
1855 loc->loc_data.offset = memory->arg_offset;
1856 memory->arg_offset += length;
1857 loc->c_length = length;
1859 /* Offset is always 0, either we're the first location part, in which
1860 case we're reading content from the start of the argument, or we're
1861 passing the address of a reference argument, so 0. */
1865 /* Update AINFO, which describes an argument that should be passed or
1866 returned using the integer ABI. The argloc fields within AINFO are
1867 updated to describe the location in which the argument will be passed to
1868 a function, or returned from a function.
1870 The CINFO structure contains the ongoing call information, the holds
1871 information such as which argument registers are remaining to be
1872 assigned to parameter, and how much memory has been used by parameters
1875 By examining the state of CINFO a suitable location can be selected,
1876 and assigned to AINFO. */
1879 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1880 struct riscv_call_info *cinfo)
1882 if (ainfo->length > (2 * cinfo->xlen))
1884 /* Argument is going to be passed by reference. */
1885 ainfo->argloc[0].loc_type
1886 = riscv_arg_info::location::by_ref;
1887 cinfo->memory.ref_offset
1888 = align_up (cinfo->memory.ref_offset, ainfo->align);
1889 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1890 cinfo->memory.ref_offset += ainfo->length;
1891 ainfo->argloc[0].c_length = ainfo->length;
1893 /* The second location for this argument is given over to holding the
1894 address of the by-reference data. Pass 0 for the offset as this
1895 is not part of the actual argument value. */
1896 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1899 riscv_assign_stack_location (&ainfo->argloc[1],
1900 &cinfo->memory, cinfo->xlen,
1905 int len = std::min (ainfo->length, cinfo->xlen);
1906 int align = std::max (ainfo->align, cinfo->xlen);
1908 /* Unnamed arguments in registers that require 2*XLEN alignment are
1909 passed in an aligned register pair. */
1910 if (ainfo->is_unnamed && (align == cinfo->xlen * 2)
1911 && cinfo->int_regs.next_regnum & 1)
1912 cinfo->int_regs.next_regnum++;
1914 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1915 &cinfo->int_regs, len, 0))
1916 riscv_assign_stack_location (&ainfo->argloc[0],
1917 &cinfo->memory, len, align);
1919 if (len < ainfo->length)
1921 len = ainfo->length - len;
1922 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1923 &cinfo->int_regs, len,
1925 riscv_assign_stack_location (&ainfo->argloc[1],
1926 &cinfo->memory, len, cinfo->xlen);
1931 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1932 is being passed with the floating point ABI. */
1935 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1936 struct riscv_call_info *cinfo)
1938 if (ainfo->length > cinfo->flen)
1939 return riscv_call_arg_scalar_int (ainfo, cinfo);
1942 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1945 return riscv_call_arg_scalar_int (ainfo, cinfo);
1949 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1950 is a complex floating point argument, and is therefore handled
1951 differently to other argument types. */
1954 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1955 struct riscv_call_info *cinfo)
1957 if (ainfo->length <= (2 * cinfo->flen)
1958 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1961 int len = ainfo->length / 2;
1963 result = riscv_assign_reg_location (&ainfo->argloc[0],
1964 &cinfo->float_regs, len, len);
1965 gdb_assert (result);
1967 result = riscv_assign_reg_location (&ainfo->argloc[1],
1968 &cinfo->float_regs, len, len);
1969 gdb_assert (result);
1972 return riscv_call_arg_scalar_int (ainfo, cinfo);
1975 /* A structure used for holding information about a structure type within
1976 the inferior program. The RiscV ABI has special rules for handling some
1977 structures with a single field or with two fields. The counting of
1978 fields here is done after flattening out all nested structures. */
1980 class riscv_struct_info
1983 riscv_struct_info ()
1984 : m_number_of_fields (0),
1985 m_types { nullptr, nullptr }
1990 /* Analyse TYPE descending into nested structures, count the number of
1991 scalar fields and record the types of the first two fields found. */
1992 void analyse (struct type *type);
1994 /* The number of scalar fields found in the analysed type. This is
1995 currently only accurate if the value returned is 0, 1, or 2 as the
1996 analysis stops counting when the number of fields is 3. This is
1997 because the RiscV ABI only has special cases for 1 or 2 fields,
1998 anything else we just don't care about. */
1999 int number_of_fields () const
2000 { return m_number_of_fields; }
2002 /* Return the type for scalar field INDEX within the analysed type. Will
2003 return nullptr if there is no field at that index. Only INDEX values
2004 0 and 1 can be requested as the RiscV ABI only has special cases for
2005 structures with 1 or 2 fields. */
2006 struct type *field_type (int index) const
2008 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
2009 return m_types[index];
2013 /* The number of scalar fields found within the structure after recursing
2014 into nested structures. */
2015 int m_number_of_fields;
2017 /* The types of the first two scalar fields found within the structure
2018 after recursing into nested structures. */
2019 struct type *m_types[2];
2022 /* Analyse TYPE descending into nested structures, count the number of
2023 scalar fields and record the types of the first two fields found. */
2026 riscv_struct_info::analyse (struct type *type)
2028 unsigned int count = TYPE_NFIELDS (type);
2031 for (i = 0; i < count; ++i)
2033 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
2036 struct type *field_type = TYPE_FIELD_TYPE (type, i);
2037 field_type = check_typedef (field_type);
2039 switch (TYPE_CODE (field_type))
2041 case TYPE_CODE_STRUCT:
2042 analyse (field_type);
2046 /* RiscV only flattens out structures. Anything else does not
2047 need to be flattened, we just record the type, and when we
2048 look at the analysis results we'll realise this is not a
2049 structure we can special case, and pass the structure in
2051 if (m_number_of_fields < 2)
2052 m_types[m_number_of_fields] = field_type;
2053 m_number_of_fields++;
2057 /* RiscV only has special handling for structures with 1 or 2 scalar
2058 fields, any more than that and the structure is just passed in
2059 memory. We can safely drop out early when we find 3 or more
2062 if (m_number_of_fields > 2)
2067 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2068 is a structure. Small structures on RiscV have some special case
2069 handling in order that the structure might be passed in register.
2070 Larger structures are passed in memory. After assigning location
2071 information to AINFO, CINFO will have been updated. */
2074 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
2075 struct riscv_call_info *cinfo)
2077 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2079 struct riscv_struct_info sinfo;
2081 sinfo.analyse (ainfo->type);
2082 if (sinfo.number_of_fields () == 1
2083 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
2085 gdb_assert (TYPE_LENGTH (ainfo->type)
2086 == TYPE_LENGTH (sinfo.field_type (0)));
2087 return riscv_call_arg_complex_float (ainfo, cinfo);
2090 if (sinfo.number_of_fields () == 1
2091 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
2093 gdb_assert (TYPE_LENGTH (ainfo->type)
2094 == TYPE_LENGTH (sinfo.field_type (0)));
2095 return riscv_call_arg_scalar_float (ainfo, cinfo);
2098 if (sinfo.number_of_fields () == 2
2099 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2100 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2101 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2102 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
2103 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2105 int len0, len1, offset;
2107 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
2109 len0 = TYPE_LENGTH (sinfo.field_type (0));
2110 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2111 &cinfo->float_regs, len0, 0))
2112 error (_("failed during argument setup"));
2114 len1 = TYPE_LENGTH (sinfo.field_type (1));
2115 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2116 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2117 - TYPE_LENGTH (sinfo.field_type (0))));
2119 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2122 error (_("failed during argument setup"));
2126 if (sinfo.number_of_fields () == 2
2127 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2128 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2129 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2130 && is_integral_type (sinfo.field_type (1))
2131 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2133 int len0, len1, offset;
2135 gdb_assert (TYPE_LENGTH (ainfo->type)
2136 <= (cinfo->flen + cinfo->xlen));
2138 len0 = TYPE_LENGTH (sinfo.field_type (0));
2139 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2140 &cinfo->float_regs, len0, 0))
2141 error (_("failed during argument setup"));
2143 len1 = TYPE_LENGTH (sinfo.field_type (1));
2144 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2145 gdb_assert (len1 <= cinfo->xlen);
2146 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2147 &cinfo->int_regs, len1, offset))
2148 error (_("failed during argument setup"));
2152 if (sinfo.number_of_fields () == 2
2153 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2154 && (is_integral_type (sinfo.field_type (0))
2155 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2156 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2157 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2159 int len0, len1, offset;
2161 gdb_assert (TYPE_LENGTH (ainfo->type)
2162 <= (cinfo->flen + cinfo->xlen));
2164 len0 = TYPE_LENGTH (sinfo.field_type (0));
2165 len1 = TYPE_LENGTH (sinfo.field_type (1));
2166 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2168 gdb_assert (len0 <= cinfo->xlen);
2169 gdb_assert (len1 <= cinfo->flen);
2171 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2172 &cinfo->int_regs, len0, 0))
2173 error (_("failed during argument setup"));
2175 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2178 error (_("failed during argument setup"));
2184 /* Non of the structure flattening cases apply, so we just pass using
2186 ainfo->length = align_up (ainfo->length, cinfo->xlen);
2187 riscv_call_arg_scalar_int (ainfo, cinfo);
2190 /* Assign a location to call (or return) argument AINFO, the location is
2191 selected from CINFO which holds information about what call argument
2192 locations are available for use next. The TYPE is the type of the
2193 argument being passed, this information is recorded into AINFO (along
2194 with some additional information derived from the type). IS_UNNAMED
2195 is true if this is an unnamed (stdarg) argument, this info is also
2196 recorded into AINFO.
2198 After assigning a location to AINFO, CINFO will have been updated. */
2201 riscv_arg_location (struct gdbarch *gdbarch,
2202 struct riscv_arg_info *ainfo,
2203 struct riscv_call_info *cinfo,
2204 struct type *type, bool is_unnamed)
2207 ainfo->length = TYPE_LENGTH (ainfo->type);
2208 ainfo->align = riscv_type_alignment (ainfo->type);
2209 ainfo->is_unnamed = is_unnamed;
2210 ainfo->contents = nullptr;
2212 switch (TYPE_CODE (ainfo->type))
2215 case TYPE_CODE_BOOL:
2216 case TYPE_CODE_CHAR:
2217 case TYPE_CODE_RANGE:
2218 case TYPE_CODE_ENUM:
2220 if (ainfo->length <= cinfo->xlen)
2222 ainfo->type = builtin_type (gdbarch)->builtin_long;
2223 ainfo->length = cinfo->xlen;
2225 else if (ainfo->length <= (2 * cinfo->xlen))
2227 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2228 ainfo->length = 2 * cinfo->xlen;
2231 /* Recalculate the alignment requirement. */
2232 ainfo->align = riscv_type_alignment (ainfo->type);
2233 riscv_call_arg_scalar_int (ainfo, cinfo);
2237 riscv_call_arg_scalar_float (ainfo, cinfo);
2240 case TYPE_CODE_COMPLEX:
2241 riscv_call_arg_complex_float (ainfo, cinfo);
2244 case TYPE_CODE_STRUCT:
2245 riscv_call_arg_struct (ainfo, cinfo);
2249 riscv_call_arg_scalar_int (ainfo, cinfo);
2254 /* Used for printing debug information about the call argument location in
2255 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2256 addresses for the location of pass-by-reference and
2257 arguments-on-the-stack memory areas. */
2260 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2261 struct riscv_arg_info *info,
2262 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2264 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2265 TYPE_SAFE_NAME (info->type), info->length, info->align);
2266 switch (info->argloc[0].loc_type)
2268 case riscv_arg_info::location::in_reg:
2270 (stream, ", register %s",
2271 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2272 if (info->argloc[0].c_length < info->length)
2274 switch (info->argloc[1].loc_type)
2276 case riscv_arg_info::location::in_reg:
2278 (stream, ", register %s",
2279 gdbarch_register_name (gdbarch,
2280 info->argloc[1].loc_data.regno));
2283 case riscv_arg_info::location::on_stack:
2284 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2285 info->argloc[1].loc_data.offset);
2288 case riscv_arg_info::location::by_ref:
2290 /* The second location should never be a reference, any
2291 argument being passed by reference just places its address
2292 in the first location and is done. */
2293 error (_("invalid argument location"));
2297 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2298 fprintf_unfiltered (stream, " (offset 0x%x)",
2299 info->argloc[1].c_offset);
2303 case riscv_arg_info::location::on_stack:
2304 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2305 info->argloc[0].loc_data.offset);
2308 case riscv_arg_info::location::by_ref:
2310 (stream, ", by reference, data at offset 0x%x (%s)",
2311 info->argloc[0].loc_data.offset,
2312 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2313 if (info->argloc[1].loc_type
2314 == riscv_arg_info::location::in_reg)
2316 (stream, ", address in register %s",
2317 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2320 gdb_assert (info->argloc[1].loc_type
2321 == riscv_arg_info::location::on_stack);
2323 (stream, ", address on stack at offset 0x%x (%s)",
2324 info->argloc[1].loc_data.offset,
2325 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2330 gdb_assert_not_reached (_("unknown argument location type"));
2334 /* Implement the push dummy call gdbarch callback. */
2337 riscv_push_dummy_call (struct gdbarch *gdbarch,
2338 struct value *function,
2339 struct regcache *regcache,
2342 struct value **args,
2344 function_call_return_method return_method,
2345 CORE_ADDR struct_addr)
2348 CORE_ADDR sp_args, sp_refs;
2349 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2351 struct riscv_arg_info *arg_info =
2352 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2354 struct riscv_call_info call_info (gdbarch);
2358 struct type *ftype = check_typedef (value_type (function));
2360 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
2361 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
2363 /* We'll use register $a0 if we're returning a struct. */
2364 if (return_method == return_method_struct)
2365 ++call_info.int_regs.next_regnum;
2367 for (i = 0; i < nargs; ++i)
2369 struct value *arg_value;
2370 struct type *arg_type;
2371 struct riscv_arg_info *info = &arg_info[i];
2373 arg_value = args[i];
2374 arg_type = check_typedef (value_type (arg_value));
2376 riscv_arg_location (gdbarch, info, &call_info, arg_type,
2377 TYPE_VARARGS (ftype) && i >= TYPE_NFIELDS (ftype));
2379 if (info->type != arg_type)
2380 arg_value = value_cast (info->type, arg_value);
2381 info->contents = value_contents (arg_value);
2384 /* Adjust the stack pointer and align it. */
2385 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2386 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2388 if (riscv_debug_infcall > 0)
2390 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2391 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2392 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2393 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2394 call_info.xlen, call_info.flen);
2395 if (return_method == return_method_struct)
2396 fprintf_unfiltered (gdb_stdlog,
2397 "[*] struct return pointer in register $A0\n");
2398 for (i = 0; i < nargs; ++i)
2400 struct riscv_arg_info *info = &arg_info [i];
2402 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2403 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2404 fprintf_unfiltered (gdb_stdlog, "\n");
2406 if (call_info.memory.arg_offset > 0
2407 || call_info.memory.ref_offset > 0)
2409 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2410 core_addr_to_string (osp));
2411 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2412 call_info.memory.arg_offset);
2413 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2414 call_info.memory.ref_offset);
2415 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2416 core_addr_to_string_nz (osp - sp));
2420 /* Now load the argument into registers, or onto the stack. */
2422 if (return_method == return_method_struct)
2424 gdb_byte buf[sizeof (LONGEST)];
2426 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2427 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2430 for (i = 0; i < nargs; ++i)
2433 int second_arg_length = 0;
2434 const gdb_byte *second_arg_data;
2435 struct riscv_arg_info *info = &arg_info [i];
2437 gdb_assert (info->length > 0);
2439 switch (info->argloc[0].loc_type)
2441 case riscv_arg_info::location::in_reg:
2443 gdb_byte tmp [sizeof (ULONGEST)];
2445 gdb_assert (info->argloc[0].c_length <= info->length);
2446 /* FP values in FP registers must be NaN-boxed. */
2447 if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno)
2448 && info->argloc[0].c_length < call_info.flen)
2449 memset (tmp, -1, sizeof (tmp));
2451 memset (tmp, 0, sizeof (tmp));
2452 memcpy (tmp, info->contents, info->argloc[0].c_length);
2453 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2455 ((info->argloc[0].c_length < info->length)
2456 ? info->argloc[1].c_length : 0);
2457 second_arg_data = info->contents + info->argloc[1].c_offset;
2461 case riscv_arg_info::location::on_stack:
2462 dst = sp_args + info->argloc[0].loc_data.offset;
2463 write_memory (dst, info->contents, info->length);
2464 second_arg_length = 0;
2467 case riscv_arg_info::location::by_ref:
2468 dst = sp_refs + info->argloc[0].loc_data.offset;
2469 write_memory (dst, info->contents, info->length);
2471 second_arg_length = call_info.xlen;
2472 second_arg_data = (gdb_byte *) &dst;
2476 gdb_assert_not_reached (_("unknown argument location type"));
2479 if (second_arg_length > 0)
2481 switch (info->argloc[1].loc_type)
2483 case riscv_arg_info::location::in_reg:
2485 gdb_byte tmp [sizeof (ULONGEST)];
2487 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2488 && second_arg_length <= call_info.flen)
2489 || second_arg_length <= call_info.xlen);
2490 /* FP values in FP registers must be NaN-boxed. */
2491 if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2492 && second_arg_length < call_info.flen)
2493 memset (tmp, -1, sizeof (tmp));
2495 memset (tmp, 0, sizeof (tmp));
2496 memcpy (tmp, second_arg_data, second_arg_length);
2497 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2501 case riscv_arg_info::location::on_stack:
2505 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2506 write_memory (arg_addr, second_arg_data, second_arg_length);
2510 case riscv_arg_info::location::by_ref:
2512 /* The second location should never be a reference, any
2513 argument being passed by reference just places its address
2514 in the first location and is done. */
2515 error (_("invalid argument location"));
2521 /* Set the dummy return value to bp_addr.
2522 A dummy breakpoint will be setup to execute the call. */
2524 if (riscv_debug_infcall > 0)
2525 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2526 core_addr_to_string (bp_addr));
2527 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2529 /* Finally, update the stack pointer. */
2531 if (riscv_debug_infcall > 0)
2532 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2533 core_addr_to_string (sp));
2534 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2539 /* Implement the return_value gdbarch method. */
2541 static enum return_value_convention
2542 riscv_return_value (struct gdbarch *gdbarch,
2543 struct value *function,
2545 struct regcache *regcache,
2547 const gdb_byte *writebuf)
2549 struct riscv_call_info call_info (gdbarch);
2550 struct riscv_arg_info info;
2551 struct type *arg_type;
2553 arg_type = check_typedef (type);
2554 riscv_arg_location (gdbarch, &info, &call_info, arg_type, false);
2556 if (riscv_debug_infcall > 0)
2558 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2559 fprintf_unfiltered (gdb_stdlog, "[R] ");
2560 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2561 fprintf_unfiltered (gdb_stdlog, "\n");
2564 if (readbuf != nullptr || writebuf != nullptr)
2568 switch (info.argloc[0].loc_type)
2570 /* Return value in register(s). */
2571 case riscv_arg_info::location::in_reg:
2573 regnum = info.argloc[0].loc_data.regno;
2576 regcache->cooked_read (regnum, readbuf);
2579 regcache->cooked_write (regnum, writebuf);
2581 /* A return value in register can have a second part in a
2583 if (info.argloc[0].c_length < info.length)
2585 switch (info.argloc[1].loc_type)
2587 case riscv_arg_info::location::in_reg:
2588 regnum = info.argloc[1].loc_data.regno;
2592 readbuf += info.argloc[1].c_offset;
2593 regcache->cooked_read (regnum, readbuf);
2598 writebuf += info.argloc[1].c_offset;
2599 regcache->cooked_write (regnum, writebuf);
2603 case riscv_arg_info::location::by_ref:
2604 case riscv_arg_info::location::on_stack:
2606 error (_("invalid argument location"));
2613 /* Return value by reference will have its address in A0. */
2614 case riscv_arg_info::location::by_ref:
2618 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2620 if (readbuf != nullptr)
2621 read_memory (addr, readbuf, info.length);
2622 if (writebuf != nullptr)
2623 write_memory (addr, writebuf, info.length);
2627 case riscv_arg_info::location::on_stack:
2629 error (_("invalid argument location"));
2634 switch (info.argloc[0].loc_type)
2636 case riscv_arg_info::location::in_reg:
2637 return RETURN_VALUE_REGISTER_CONVENTION;
2638 case riscv_arg_info::location::by_ref:
2639 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2640 case riscv_arg_info::location::on_stack:
2642 error (_("invalid argument location"));
2646 /* Implement the frame_align gdbarch method. */
2649 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2651 return align_down (addr, 16);
2654 /* Implement the unwind_pc gdbarch method. */
2657 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2659 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2662 /* Implement the unwind_sp gdbarch method. */
2665 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2667 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2670 /* Implement the dummy_id gdbarch method. */
2672 static struct frame_id
2673 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2675 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2676 get_frame_pc (this_frame));
2679 /* Generate, or return the cached frame cache for the RiscV frame
2682 static struct riscv_unwind_cache *
2683 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2685 CORE_ADDR pc, start_addr;
2686 struct riscv_unwind_cache *cache;
2687 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2690 if ((*this_cache) != NULL)
2691 return (struct riscv_unwind_cache *) *this_cache;
2693 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2694 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2695 (*this_cache) = cache;
2697 /* Scan the prologue, filling in the cache. */
2698 start_addr = get_frame_func (this_frame);
2699 pc = get_frame_pc (this_frame);
2700 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2702 /* We can now calculate the frame base address. */
2704 = (get_frame_register_signed (this_frame, cache->frame_base_reg)
2705 + cache->frame_base_offset);
2706 if (riscv_debug_unwinder)
2707 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2708 core_addr_to_string (cache->frame_base),
2709 gdbarch_register_name (gdbarch,
2710 cache->frame_base_reg),
2711 cache->frame_base_offset);
2713 /* The prologue scanner sets the address of registers stored to the stack
2714 as the offset of that register from the frame base. The prologue
2715 scanner doesn't know the actual frame base value, and so is unable to
2716 compute the exact address. We do now know the frame base value, so
2717 update the address of registers stored to the stack. */
2718 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2719 for (regno = 0; regno < numregs; ++regno)
2721 if (trad_frame_addr_p (cache->regs, regno))
2722 cache->regs[regno].addr += cache->frame_base;
2725 /* The previous $pc can be found wherever the $ra value can be found.
2726 The previous $ra value is gone, this would have been stored be the
2727 previous frame if required. */
2728 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2729 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2731 /* Build the frame id. */
2732 cache->this_id = frame_id_build (cache->frame_base, start_addr);
2734 /* The previous $sp value is the frame base value. */
2735 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2741 /* Implement the this_id callback for RiscV frame unwinder. */
2744 riscv_frame_this_id (struct frame_info *this_frame,
2745 void **prologue_cache,
2746 struct frame_id *this_id)
2748 struct riscv_unwind_cache *cache;
2752 cache = riscv_frame_cache (this_frame, prologue_cache);
2753 *this_id = cache->this_id;
2755 CATCH (ex, RETURN_MASK_ERROR)
2757 /* Ignore errors, this leaves the frame id as the predefined outer
2758 frame id which terminates the backtrace at this point. */
2763 /* Implement the prev_register callback for RiscV frame unwinder. */
2765 static struct value *
2766 riscv_frame_prev_register (struct frame_info *this_frame,
2767 void **prologue_cache,
2770 struct riscv_unwind_cache *cache;
2772 cache = riscv_frame_cache (this_frame, prologue_cache);
2773 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
2776 /* Structure defining the RiscV normal frame unwind functions. Since we
2777 are the fallback unwinder (DWARF unwinder is used first), we use the
2778 default frame sniffer, which always accepts the frame. */
2780 static const struct frame_unwind riscv_frame_unwind =
2782 /*.type =*/ NORMAL_FRAME,
2783 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2784 /*.this_id =*/ riscv_frame_this_id,
2785 /*.prev_register =*/ riscv_frame_prev_register,
2786 /*.unwind_data =*/ NULL,
2787 /*.sniffer =*/ default_frame_sniffer,
2788 /*.dealloc_cache =*/ NULL,
2789 /*.prev_arch =*/ NULL,
2792 /* Find a suitable default target description. Use the contents of INFO,
2793 specifically the bfd object being executed, to guide the selection of a
2794 suitable default target description. */
2796 static const struct target_desc *
2797 riscv_find_default_target_description (const struct gdbarch_info info)
2799 struct riscv_gdbarch_features features;
2801 /* Setup some arbitrary defaults. */
2804 features.hw_float_abi = false;
2806 /* Now try to improve on the defaults by looking at the binary we are
2807 going to execute. We assume the user knows what they are doing and
2808 that the target will match the binary. Remember, this code path is
2809 only used at all if the target hasn't given us a description, so this
2810 is really a last ditched effort to do something sane before giving
2812 if (info.abfd != NULL
2813 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2815 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2816 int e_flags = elf_elfheader (info.abfd)->e_flags;
2818 if (eclass == ELFCLASS32)
2820 else if (eclass == ELFCLASS64)
2823 internal_error (__FILE__, __LINE__,
2824 _("unknown ELF header class %d"), eclass);
2826 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2829 features.hw_float_abi = true;
2831 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2834 features.hw_float_abi = true;
2839 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2841 if (binfo->bits_per_word == 32)
2843 else if (binfo->bits_per_word == 64)
2846 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2847 binfo->bits_per_word);
2850 /* Now build a target description based on the feature set. */
2851 return riscv_create_target_description (features);
2854 /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
2855 is updated with the register numbers for each register as listed in
2856 REG_SET. If any register marked as required in REG_SET is not found in
2857 FEATURE then this function returns false, otherwise, it returns true. */
2860 riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
2861 const struct tdesc_feature *feature,
2862 const struct riscv_register_feature *reg_set)
2864 for (const auto ® : reg_set->registers)
2868 for (const char *name : reg.names)
2871 tdesc_numbered_register (feature, tdesc_data, reg.regnum, name);
2877 if (!found && reg.required_p)
2884 /* Add all the expected register sets into GDBARCH. */
2887 riscv_add_reggroups (struct gdbarch *gdbarch)
2889 /* Add predefined register groups. */
2890 reggroup_add (gdbarch, all_reggroup);
2891 reggroup_add (gdbarch, save_reggroup);
2892 reggroup_add (gdbarch, restore_reggroup);
2893 reggroup_add (gdbarch, system_reggroup);
2894 reggroup_add (gdbarch, vector_reggroup);
2895 reggroup_add (gdbarch, general_reggroup);
2896 reggroup_add (gdbarch, float_reggroup);
2898 /* Add RISC-V specific register groups. */
2899 reggroup_add (gdbarch, csr_reggroup);
2902 /* Create register aliases for all the alternative names that exist for
2903 registers in REG_SET. */
2906 riscv_setup_register_aliases (struct gdbarch *gdbarch,
2907 const struct riscv_register_feature *reg_set)
2909 for (auto ® : reg_set->registers)
2911 /* The first item in the names list is the preferred name for the
2912 register, this is what RISCV_REGISTER_NAME returns, and so we
2913 don't need to create an alias with that name here. */
2914 for (int i = 1; i < reg.names.size (); ++i)
2915 user_reg_add (gdbarch, reg.names[i], value_of_riscv_user_reg,
2920 /* Initialize the current architecture based on INFO. If possible,
2921 re-use an architecture from ARCHES, which is a list of
2922 architectures already created during this debugging session.
2924 Called e.g. at program startup, when reading a core file, and when
2925 reading a binary file. */
2927 static struct gdbarch *
2928 riscv_gdbarch_init (struct gdbarch_info info,
2929 struct gdbarch_list *arches)
2931 struct gdbarch *gdbarch;
2932 struct gdbarch_tdep *tdep;
2933 struct riscv_gdbarch_features features;
2934 const struct target_desc *tdesc = info.target_desc;
2936 /* Ensure we always have a target description. */
2937 if (!tdesc_has_registers (tdesc))
2938 tdesc = riscv_find_default_target_description (info);
2941 if (riscv_debug_gdbarch)
2942 fprintf_unfiltered (gdb_stdlog, "Have got a target description\n");
2944 const struct tdesc_feature *feature_cpu
2945 = tdesc_find_feature (tdesc, riscv_xreg_feature.name);
2946 const struct tdesc_feature *feature_fpu
2947 = tdesc_find_feature (tdesc, riscv_freg_feature.name);
2948 const struct tdesc_feature *feature_virtual
2949 = tdesc_find_feature (tdesc, riscv_virtual_feature.name);
2950 const struct tdesc_feature *feature_csr
2951 = tdesc_find_feature (tdesc, riscv_csr_feature.name);
2953 if (feature_cpu == NULL)
2956 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
2958 bool valid_p = riscv_check_tdesc_feature (tdesc_data,
2960 &riscv_xreg_feature);
2963 /* Check that all of the core cpu registers have the same bitsize. */
2964 int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc");
2966 for (auto &tdesc_reg : feature_cpu->registers)
2967 valid_p &= (tdesc_reg->bitsize == xlen_bitsize);
2969 if (riscv_debug_gdbarch)
2972 "From target-description, xlen = %d\n", xlen_bitsize);
2974 features.xlen = (xlen_bitsize / 8);
2977 if (feature_fpu != NULL)
2979 valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
2980 &riscv_freg_feature);
2982 int bitsize = tdesc_register_bitsize (feature_fpu, "ft0");
2983 features.flen = (bitsize / 8);
2984 features.hw_float_abi = true;
2986 if (riscv_debug_gdbarch)
2989 "From target-description, flen = %d\n", bitsize);
2994 features.hw_float_abi = false;
2996 if (riscv_debug_gdbarch)
2999 "No FPU in target-description, assume soft-float ABI\n");
3002 if (feature_virtual)
3003 riscv_check_tdesc_feature (tdesc_data, feature_virtual,
3004 &riscv_virtual_feature);
3007 riscv_check_tdesc_feature (tdesc_data, feature_csr,
3008 &riscv_csr_feature);
3012 if (riscv_debug_gdbarch)
3013 fprintf_unfiltered (gdb_stdlog, "Target description is not valid\n");
3014 tdesc_data_cleanup (tdesc_data);
3018 /* Find a candidate among the list of pre-declared architectures. */
3019 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3021 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3023 /* Check that the feature set of the ARCHES matches the feature set
3024 we are looking for. If it doesn't then we can't reuse this
3026 struct gdbarch_tdep *other_tdep = gdbarch_tdep (arches->gdbarch);
3028 if (other_tdep->features != features)
3036 tdesc_data_cleanup (tdesc_data);
3037 return arches->gdbarch;
3040 /* None found, so create a new architecture from the information provided. */
3041 tdep = new (struct gdbarch_tdep);
3042 gdbarch = gdbarch_alloc (&info, tdep);
3043 tdep->features = features;
3045 /* Target data types. */
3046 set_gdbarch_short_bit (gdbarch, 16);
3047 set_gdbarch_int_bit (gdbarch, 32);
3048 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
3049 set_gdbarch_long_long_bit (gdbarch, 64);
3050 set_gdbarch_float_bit (gdbarch, 32);
3051 set_gdbarch_double_bit (gdbarch, 64);
3052 set_gdbarch_long_double_bit (gdbarch, 128);
3053 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
3054 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
3055 set_gdbarch_char_signed (gdbarch, 0);
3057 /* Information about the target architecture. */
3058 set_gdbarch_return_value (gdbarch, riscv_return_value);
3059 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
3060 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
3061 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3063 /* Functions to analyze frames. */
3064 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
3065 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3066 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
3068 /* Functions to access frame data. */
3069 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
3070 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
3072 /* Functions handling dummy frames. */
3073 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
3074 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
3075 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
3076 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
3078 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3080 dwarf2_append_unwinders (gdbarch);
3081 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
3083 /* Register architecture. */
3084 riscv_add_reggroups (gdbarch);
3086 /* We reserve all possible register numbers for the known registers.
3087 This means the target description mechanism will add any target
3088 specific registers after this number. This helps make debugging GDB
3089 just a little easier. */
3090 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
3092 /* We don't have to provide the count of 0 here (its the default) but
3093 include this line to make it explicit that, right now, we don't have
3094 any pseudo registers on RISC-V. */
3095 set_gdbarch_num_pseudo_regs (gdbarch, 0);
3097 /* Some specific register numbers GDB likes to know about. */
3098 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
3099 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
3101 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
3103 /* Finalise the target description registers. */
3104 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3106 /* Override the register type callback setup by the target description
3107 mechanism. This allows us to provide special type for floating point
3109 set_gdbarch_register_type (gdbarch, riscv_register_type);
3111 /* Override the register name callback setup by the target description
3112 mechanism. This allows us to force our preferred names for the
3113 registers, no matter what the target description called them. */
3114 set_gdbarch_register_name (gdbarch, riscv_register_name);
3116 /* Override the register group callback setup by the target description
3117 mechanism. This allows us to force registers into the groups we
3118 want, ignoring what the target tells us. */
3119 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
3121 /* Create register aliases for alternative register names. */
3122 riscv_setup_register_aliases (gdbarch, &riscv_xreg_feature);
3123 if (riscv_has_fp_regs (gdbarch))
3124 riscv_setup_register_aliases (gdbarch, &riscv_freg_feature);
3125 riscv_setup_register_aliases (gdbarch, &riscv_csr_feature);
3127 /* Hook in OS ABI-specific overrides, if they have been registered. */
3128 gdbarch_init_osabi (info, gdbarch);
3133 /* This decodes the current instruction and determines the address of the
3134 next instruction. */
3137 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
3139 struct gdbarch *gdbarch = regcache->arch ();
3140 struct riscv_insn insn;
3143 insn.decode (gdbarch, pc);
3144 next_pc = pc + insn.length ();
3146 if (insn.opcode () == riscv_insn::JAL)
3147 next_pc = pc + insn.imm_signed ();
3148 else if (insn.opcode () == riscv_insn::JALR)
3151 regcache->cooked_read (insn.rs1 (), &source);
3152 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
3154 else if (insn.opcode () == riscv_insn::BEQ)
3157 regcache->cooked_read (insn.rs1 (), &src1);
3158 regcache->cooked_read (insn.rs2 (), &src2);
3160 next_pc = pc + insn.imm_signed ();
3162 else if (insn.opcode () == riscv_insn::BNE)
3165 regcache->cooked_read (insn.rs1 (), &src1);
3166 regcache->cooked_read (insn.rs2 (), &src2);
3168 next_pc = pc + insn.imm_signed ();
3170 else if (insn.opcode () == riscv_insn::BLT)
3173 regcache->cooked_read (insn.rs1 (), &src1);
3174 regcache->cooked_read (insn.rs2 (), &src2);
3176 next_pc = pc + insn.imm_signed ();
3178 else if (insn.opcode () == riscv_insn::BGE)
3181 regcache->cooked_read (insn.rs1 (), &src1);
3182 regcache->cooked_read (insn.rs2 (), &src2);
3184 next_pc = pc + insn.imm_signed ();
3186 else if (insn.opcode () == riscv_insn::BLTU)
3188 ULONGEST src1, src2;
3189 regcache->cooked_read (insn.rs1 (), &src1);
3190 regcache->cooked_read (insn.rs2 (), &src2);
3192 next_pc = pc + insn.imm_signed ();
3194 else if (insn.opcode () == riscv_insn::BGEU)
3196 ULONGEST src1, src2;
3197 regcache->cooked_read (insn.rs1 (), &src1);
3198 regcache->cooked_read (insn.rs2 (), &src2);
3200 next_pc = pc + insn.imm_signed ();
3206 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3207 for the end of the sequence and put the breakpoint there. */
3210 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
3213 struct gdbarch *gdbarch = regcache->arch ();
3214 struct riscv_insn insn;
3215 CORE_ADDR cur_step_pc = pc;
3216 CORE_ADDR last_addr = 0;
3218 /* First instruction has to be a load reserved. */
3219 insn.decode (gdbarch, cur_step_pc);
3220 if (insn.opcode () != riscv_insn::LR)
3222 cur_step_pc = cur_step_pc + insn.length ();
3224 /* Next instruction should be branch to exit. */
3225 insn.decode (gdbarch, cur_step_pc);
3226 if (insn.opcode () != riscv_insn::BNE)
3228 last_addr = cur_step_pc + insn.imm_signed ();
3229 cur_step_pc = cur_step_pc + insn.length ();
3231 /* Next instruction should be store conditional. */
3232 insn.decode (gdbarch, cur_step_pc);
3233 if (insn.opcode () != riscv_insn::SC)
3235 cur_step_pc = cur_step_pc + insn.length ();
3237 /* Next instruction should be branch to start. */
3238 insn.decode (gdbarch, cur_step_pc);
3239 if (insn.opcode () != riscv_insn::BNE)
3241 if (pc != (cur_step_pc + insn.imm_signed ()))
3243 cur_step_pc = cur_step_pc + insn.length ();
3245 /* We should now be at the end of the sequence. */
3246 if (cur_step_pc != last_addr)
3249 *next_pc = cur_step_pc;
3253 /* This is called just before we want to resume the inferior, if we want to
3254 single-step it but there is no hardware or kernel single-step support. We
3255 find the target of the coming instruction and breakpoint it. */
3257 std::vector<CORE_ADDR>
3258 riscv_software_single_step (struct regcache *regcache)
3260 CORE_ADDR pc, next_pc;
3262 pc = regcache_read_pc (regcache);
3264 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
3267 next_pc = riscv_next_pc (regcache, pc);
3272 /* Create RISC-V specific reggroups. */
3275 riscv_init_reggroups ()
3277 csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
3281 _initialize_riscv_tdep (void)
3283 riscv_create_csr_aliases ();
3284 riscv_init_reggroups ();
3286 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
3288 /* Add root prefix command for all "set debug riscv" and "show debug
3290 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
3291 _("RISC-V specific debug commands."),
3292 &setdebugriscvcmdlist, "set debug riscv ", 0,
3295 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
3296 _("RISC-V specific debug commands."),
3297 &showdebugriscvcmdlist, "show debug riscv ", 0,
3300 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
3301 &riscv_debug_breakpoints, _("\
3302 Set riscv breakpoint debugging."), _("\
3303 Show riscv breakpoint debugging."), _("\
3304 When non-zero, print debugging information for the riscv specific parts\n\
3305 of the breakpoint mechanism."),
3307 show_riscv_debug_variable,
3308 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3310 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
3311 &riscv_debug_infcall, _("\
3312 Set riscv inferior call debugging."), _("\
3313 Show riscv inferior call debugging."), _("\
3314 When non-zero, print debugging information for the riscv specific parts\n\
3315 of the inferior call mechanism."),
3317 show_riscv_debug_variable,
3318 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3320 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
3321 &riscv_debug_unwinder, _("\
3322 Set riscv stack unwinding debugging."), _("\
3323 Show riscv stack unwinding debugging."), _("\
3324 When non-zero, print debugging information for the riscv specific parts\n\
3325 of the stack unwinding mechanism."),
3327 show_riscv_debug_variable,
3328 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3330 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance,
3331 &riscv_debug_gdbarch, _("\
3332 Set riscv gdbarch initialisation debugging."), _("\
3333 Show riscv gdbarch initialisation debugging."), _("\
3334 When non-zero, print debugging information for the riscv gdbarch\n\
3335 initialisation process."),
3337 show_riscv_debug_variable,
3338 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3340 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3341 add_prefix_cmd ("riscv", no_class, set_riscv_command,
3342 _("RISC-V specific commands."),
3343 &setriscvcmdlist, "set riscv ", 0, &setlist);
3345 add_prefix_cmd ("riscv", no_class, show_riscv_command,
3346 _("RISC-V specific commands."),
3347 &showriscvcmdlist, "show riscv ", 0, &showlist);
3350 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
3351 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
3352 &use_compressed_breakpoints,
3354 Set debugger's use of compressed breakpoints."), _(" \
3355 Show debugger's use of compressed breakpoints."), _("\
3356 Debugging compressed code requires compressed breakpoints to be used. If\n\
3357 left to 'auto' then gdb will use them if the existing instruction is a\n\
3358 compressed instruction. If that doesn't give the correct behavior, then\n\
3359 this option can be used."),
3361 show_use_compressed_breakpoints,