1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
58 /* The stack must be 16-byte aligned. */
59 #define SP_ALIGNMENT 16
61 /* Forward declarations. */
62 static bool riscv_has_feature (struct gdbarch *gdbarch, char feature);
63 struct riscv_inferior_data;
64 struct riscv_inferior_data * riscv_inferior_data (struct inferior *const inf);
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Per inferior information for RiscV. */
78 struct riscv_inferior_data
80 /* True when MISA_VALUE is valid, otherwise false. */
83 /* If MISA_READ is true then MISA_VALUE holds the value of the MISA
84 register read from the target. */
88 /* Key created when the RiscV per-inferior data is registered. */
90 static const struct inferior_data *riscv_inferior_data_reg;
92 /* Architectural name for core registers. */
94 static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
96 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
97 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
98 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
99 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
101 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
102 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
103 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
104 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
107 /* Maps "pretty" register names onto their GDB register number. */
109 struct register_alias
111 /* The register alias. Usually more descriptive than the
112 architectural name of the register. */
115 /* The GDB register number. */
119 /* Table of register aliases. */
121 static const struct register_alias riscv_register_aliases[] =
189 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
190 #include "opcode/riscv-opc.h"
194 /* Controls whether we place compressed breakpoints or not. When in auto
195 mode GDB tries to determine if the target supports compressed
196 breakpoints, and uses them if it does. */
198 static enum auto_boolean use_compressed_breakpoints;
200 /* The show callback for 'show riscv use-compressed-breakpoints'. */
203 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
204 struct cmd_list_element *c,
207 const char *additional_info;
208 struct gdbarch *gdbarch = target_gdbarch ();
210 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
211 if (riscv_has_feature (gdbarch, 'C'))
212 additional_info = _(" (currently on)");
214 additional_info = _(" (currently off)");
216 additional_info = "";
218 fprintf_filtered (file,
219 _("Debugger's use of compressed breakpoints is set "
220 "to %s%s.\n"), value, additional_info);
223 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
225 static struct cmd_list_element *setriscvcmdlist = NULL;
226 static struct cmd_list_element *showriscvcmdlist = NULL;
228 /* The show callback for the 'show riscv' prefix command. */
231 show_riscv_command (const char *args, int from_tty)
233 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
236 /* The set callback for the 'set riscv' prefix command. */
239 set_riscv_command (const char *args, int from_tty)
242 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
243 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
246 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
248 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
249 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
251 /* The show callback for the 'show debug riscv' prefix command. */
254 show_debug_riscv_command (const char *args, int from_tty)
256 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
259 /* The set callback for the 'set debug riscv' prefix command. */
262 set_debug_riscv_command (const char *args, int from_tty)
265 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
266 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
269 /* The show callback for all 'show debug riscv VARNAME' variables. */
272 show_riscv_debug_variable (struct ui_file *file, int from_tty,
273 struct cmd_list_element *c,
276 fprintf_filtered (file,
277 _("RiscV debug variable `%s' is set to: %s\n"),
281 /* When this is set to non-zero debugging information about inferior calls
284 static unsigned int riscv_debug_infcall = 0;
286 /* Read the MISA register from the target. The register will only be read
287 once, and the value read will be cached. If the register can't be read
288 from the target then a default value (0) will be returned. If the
289 pointer READ_P is not null, then the bool pointed to is updated to
290 indicate if the value returned was read from the target (true) or is the
294 riscv_read_misa_reg (bool *read_p)
296 struct riscv_inferior_data *inf_data
297 = riscv_inferior_data (current_inferior ());
299 if (!inf_data->misa_read && target_has_registers)
302 struct frame_info *frame = get_current_frame ();
306 value = get_frame_register_unsigned (frame, RISCV_CSR_MISA_REGNUM);
308 CATCH (ex, RETURN_MASK_ERROR)
310 /* Old cores might have MISA located at a different offset. */
311 value = get_frame_register_unsigned (frame,
312 RISCV_CSR_LEGACY_MISA_REGNUM);
316 inf_data->misa_read = true;
317 inf_data->misa_value = value;
320 if (read_p != nullptr)
321 *read_p = inf_data->misa_read;
323 return inf_data->misa_value;
326 /* Return true if FEATURE is available for the architecture GDBARCH. The
327 FEATURE should be one of the single character feature codes described in
328 the RiscV ISA manual, these are between 'A' and 'Z'. */
331 riscv_has_feature (struct gdbarch *gdbarch, char feature)
333 bool have_read_misa = false;
336 gdb_assert (feature >= 'A' && feature <= 'Z');
338 misa = riscv_read_misa_reg (&have_read_misa);
339 if (!have_read_misa || misa == 0)
340 misa = gdbarch_tdep (gdbarch)->core_features;
342 return (misa & (1 << (feature - 'A'))) != 0;
345 /* Return the width in bytes of the general purpose registers for GDBARCH.
346 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
350 riscv_isa_xlen (struct gdbarch *gdbarch)
352 switch (gdbarch_tdep (gdbarch)->abi.fields.base_len)
355 warning (_("unknown xlen size, assuming 4 bytes"));
366 /* Return the width in bytes of the floating point registers for GDBARCH.
367 If this architecture has no floating point registers, then return 0.
368 Possible values are 4, 8, or 16 for depending on which of single, double
369 or quad floating point support is available. */
372 riscv_isa_flen (struct gdbarch *gdbarch)
374 if (riscv_has_feature (gdbarch, 'Q'))
376 else if (riscv_has_feature (gdbarch, 'D'))
378 else if (riscv_has_feature (gdbarch, 'F'))
384 /* Return true if the target for GDBARCH has floating point hardware. */
387 riscv_has_fp_regs (struct gdbarch *gdbarch)
389 return (riscv_isa_flen (gdbarch) > 0);
392 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
395 riscv_has_fp_abi (struct gdbarch *gdbarch)
397 return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0);
400 /* Return true if REGNO is a floating pointer register. */
403 riscv_is_fp_regno_p (int regno)
405 return (regno >= RISCV_FIRST_FP_REGNUM
406 && regno <= RISCV_LAST_FP_REGNUM);
409 /* Implement the breakpoint_kind_from_pc gdbarch method. */
412 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
414 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
416 if (riscv_has_feature (gdbarch, 'C'))
421 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
427 /* Implement the sw_breakpoint_from_kind gdbarch method. */
429 static const gdb_byte *
430 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
432 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
433 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
443 gdb_assert_not_reached (_("unhandled breakpoint kind"));
447 /* Callback function for user_reg_add. */
449 static struct value *
450 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
452 const int *reg_p = (const int *) baton;
453 return value_of_register (*reg_p, frame);
456 /* Implement the register_name gdbarch method. */
459 riscv_register_name (struct gdbarch *gdbarch, int regnum)
461 /* Prefer to use the alias. */
462 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM)
466 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
467 if (regnum == riscv_register_aliases[i].regnum)
468 return riscv_register_aliases[i].name;
471 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
472 return riscv_gdb_reg_names[regnum];
474 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
478 xsnprintf (buf, sizeof (buf), "csr%d",
479 regnum - RISCV_FIRST_CSR_REGNUM);
483 if (regnum == RISCV_PRIV_REGNUM)
489 /* Implement the register_type gdbarch method. */
492 riscv_register_type (struct gdbarch *gdbarch, int regnum)
496 if (regnum < RISCV_FIRST_FP_REGNUM)
498 if (regnum == gdbarch_pc_regnum (gdbarch)
499 || regnum == RISCV_RA_REGNUM)
500 return builtin_type (gdbarch)->builtin_func_ptr;
502 if (regnum == RISCV_FP_REGNUM
503 || regnum == RISCV_SP_REGNUM
504 || regnum == RISCV_GP_REGNUM
505 || regnum == RISCV_TP_REGNUM)
506 return builtin_type (gdbarch)->builtin_data_ptr;
508 /* Remaining GPRs vary in size based on the current ISA. */
509 regsize = riscv_isa_xlen (gdbarch);
513 return builtin_type (gdbarch)->builtin_uint32;
515 return builtin_type (gdbarch)->builtin_uint64;
517 return builtin_type (gdbarch)->builtin_uint128;
519 internal_error (__FILE__, __LINE__,
520 _("unknown isa regsize %i"), regsize);
523 else if (regnum <= RISCV_LAST_FP_REGNUM)
525 regsize = riscv_isa_xlen (gdbarch);
529 return builtin_type (gdbarch)->builtin_float;
531 return builtin_type (gdbarch)->builtin_double;
533 return builtin_type (gdbarch)->builtin_long_double;
535 internal_error (__FILE__, __LINE__,
536 _("unknown isa regsize %i"), regsize);
539 else if (regnum == RISCV_PRIV_REGNUM)
540 return builtin_type (gdbarch)->builtin_int8;
543 if (regnum == RISCV_CSR_FFLAGS_REGNUM
544 || regnum == RISCV_CSR_FRM_REGNUM
545 || regnum == RISCV_CSR_FCSR_REGNUM)
546 return builtin_type (gdbarch)->builtin_int32;
548 regsize = riscv_isa_xlen (gdbarch);
552 return builtin_type (gdbarch)->builtin_int32;
554 return builtin_type (gdbarch)->builtin_int64;
556 return builtin_type (gdbarch)->builtin_int128;
558 internal_error (__FILE__, __LINE__,
559 _("unknown isa regsize %i"), regsize);
564 /* Helper for riscv_print_registers_info, prints info for a single register
568 riscv_print_one_register_info (struct gdbarch *gdbarch,
569 struct ui_file *file,
570 struct frame_info *frame,
573 const char *name = gdbarch_register_name (gdbarch, regnum);
574 struct value *val = value_of_register (regnum, frame);
575 struct type *regtype = value_type (val);
576 int print_raw_format;
577 enum tab_stops { value_column_1 = 15 };
579 fputs_filtered (name, file);
580 print_spaces_filtered (value_column_1 - strlen (name), file);
582 print_raw_format = (value_entirely_available (val)
583 && !value_optimized_out (val));
585 if (TYPE_CODE (regtype) == TYPE_CODE_FLT)
587 struct value_print_options opts;
588 const gdb_byte *valaddr = value_contents_for_printing (val);
589 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
591 get_user_print_options (&opts);
595 value_embedded_offset (val), 0,
596 file, 0, val, &opts, current_language);
598 if (print_raw_format)
600 fprintf_filtered (file, "\t(raw ");
601 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
603 fprintf_filtered (file, ")");
608 struct value_print_options opts;
610 /* Print the register in hex. */
611 get_formatted_print_options (&opts, 'x');
614 value_embedded_offset (val), 0,
615 file, 0, val, &opts, current_language);
617 if (print_raw_format)
619 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
622 int size = register_size (gdbarch, regnum);
625 d = value_as_long (val);
627 fprintf_filtered (file,
628 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
629 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
630 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
631 (int) ((d >> (xlen - 1)) & 0x1),
632 (int) ((d >> 24) & 0x1f),
633 (int) ((d >> 19) & 0x1),
634 (int) ((d >> 18) & 0x1),
635 (int) ((d >> 17) & 0x1),
636 (int) ((d >> 15) & 0x3),
637 (int) ((d >> 13) & 0x3),
638 (int) ((d >> 11) & 0x3),
639 (int) ((d >> 9) & 0x3),
640 (int) ((d >> 8) & 0x1),
641 (int) ((d >> 7) & 0x1),
642 (int) ((d >> 6) & 0x1),
643 (int) ((d >> 5) & 0x1),
644 (int) ((d >> 4) & 0x1),
645 (int) ((d >> 3) & 0x1),
646 (int) ((d >> 2) & 0x1),
647 (int) ((d >> 1) & 0x1),
648 (int) ((d >> 0) & 0x1));
650 else if (regnum == RISCV_CSR_MISA_REGNUM)
656 d = value_as_long (val);
660 for (; base > 0; base--)
662 fprintf_filtered (file, "\tRV%d", xlen);
664 for (i = 0; i < 26; i++)
667 fprintf_filtered (file, "%c", 'A' + i);
670 else if (regnum == RISCV_CSR_FCSR_REGNUM
671 || regnum == RISCV_CSR_FFLAGS_REGNUM
672 || regnum == RISCV_CSR_FRM_REGNUM)
676 d = value_as_long (val);
678 fprintf_filtered (file, "\t");
679 if (regnum != RISCV_CSR_FRM_REGNUM)
680 fprintf_filtered (file,
681 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
682 (int) ((d >> 5) & 0x7),
683 (int) ((d >> 4) & 0x1),
684 (int) ((d >> 3) & 0x1),
685 (int) ((d >> 2) & 0x1),
686 (int) ((d >> 1) & 0x1),
687 (int) ((d >> 0) & 0x1));
689 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
691 static const char * const sfrm[] =
693 "RNE (round to nearest; ties to even)",
694 "RTZ (Round towards zero)",
695 "RDN (Round down towards -INF)",
696 "RUP (Round up towards +INF)",
697 "RMM (Round to nearest; ties to max magnitude)",
700 "dynamic rounding mode",
702 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
703 ? (d >> 5) : d) & 0x3;
705 fprintf_filtered (file, "%sFRM:%i [%s]",
706 (regnum == RISCV_CSR_FCSR_REGNUM
711 else if (regnum == RISCV_PRIV_REGNUM)
716 d = value_as_long (val);
721 static const char * const sprv[] =
728 fprintf_filtered (file, "\tprv:%d [%s]",
732 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
736 /* If not a vector register, print it also according to its
738 if (TYPE_VECTOR (regtype) == 0)
740 get_user_print_options (&opts);
742 fprintf_filtered (file, "\t");
744 value_embedded_offset (val), 0,
745 file, 0, val, &opts, current_language);
750 fprintf_filtered (file, "\n");
753 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
757 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
758 struct reggroup *reggroup)
762 /* Used by 'info registers' and 'info registers <groupname>'. */
764 if (gdbarch_register_name (gdbarch, regnum) == NULL
765 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
768 if (reggroup == all_reggroup)
770 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
772 /* Only include CSRs that have aliases. */
773 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
775 if (regnum == riscv_register_aliases[i].regnum)
780 else if (reggroup == float_reggroup)
781 return (riscv_is_fp_regno_p (regnum)
782 || regnum == RISCV_CSR_FCSR_REGNUM
783 || regnum == RISCV_CSR_FFLAGS_REGNUM
784 || regnum == RISCV_CSR_FRM_REGNUM);
785 else if (reggroup == general_reggroup)
786 return regnum < RISCV_FIRST_FP_REGNUM;
787 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
789 if (riscv_has_fp_regs (gdbarch))
790 return regnum <= RISCV_LAST_FP_REGNUM;
792 return regnum < RISCV_FIRST_FP_REGNUM;
794 else if (reggroup == system_reggroup)
796 if (regnum == RISCV_PRIV_REGNUM)
798 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
800 /* Only include CSRs that have aliases. */
801 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
803 if (regnum == riscv_register_aliases[i].regnum)
808 else if (reggroup == vector_reggroup)
814 /* Implement the print_registers_info gdbarch method. This is used by
815 'info registers' and 'info all-registers'. */
818 riscv_print_registers_info (struct gdbarch *gdbarch,
819 struct ui_file *file,
820 struct frame_info *frame,
821 int regnum, int print_all)
825 /* Print one specified register. */
826 gdb_assert (regnum <= RISCV_LAST_REGNUM);
827 if (gdbarch_register_name (gdbarch, regnum) == NULL
828 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
829 error (_("Not a valid register for the current processor type"));
830 riscv_print_one_register_info (gdbarch, file, frame, regnum);
834 struct reggroup *reggroup;
837 reggroup = all_reggroup;
839 reggroup = general_reggroup;
841 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
843 /* Zero never changes, so might as well hide by default. */
844 if (regnum == RISCV_ZERO_REGNUM && !print_all)
847 /* Registers with no name are not valid on this ISA. */
848 if (gdbarch_register_name (gdbarch, regnum) == NULL
849 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
852 /* Is the register in the group we're interested in? */
853 if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup))
856 riscv_print_one_register_info (gdbarch, file, frame, regnum);
861 /* Class that handles one decoded RiscV instruction. */
867 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
870 /* Unknown value is used at initialisation time. */
873 /* These instructions are all the ones we are interested in during the
883 /* These are needed for software breakopint support. */
892 /* These are needed for stepping over atomic sequences. */
896 /* Other instructions are not interesting during the prologue scan, and
911 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
913 /* Get the length of the instruction in bytes. */
917 /* Get the opcode for this instruction. */
918 enum opcode opcode () const
921 /* Get destination register field for this instruction. This is only
922 valid if the OPCODE implies there is such a field for this
927 /* Get the RS1 register field for this instruction. This is only valid
928 if the OPCODE implies there is such a field for this instruction. */
932 /* Get the RS2 register field for this instruction. This is only valid
933 if the OPCODE implies there is such a field for this instruction. */
937 /* Get the immediate for this instruction in signed form. This is only
938 valid if the OPCODE implies there is such a field for this
940 int imm_signed () const
945 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
946 int decode_register_index (unsigned long opcode, int offset)
948 return (opcode >> offset) & 0x1F;
951 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
952 int decode_register_index_short (unsigned long opcode, int offset)
954 return ((opcode >> offset) & 0x7) + 8;
957 /* Helper for DECODE, decode 32-bit R-type instruction. */
958 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
961 m_rd = decode_register_index (ival, OP_SH_RD);
962 m_rs1 = decode_register_index (ival, OP_SH_RS1);
963 m_rs2 = decode_register_index (ival, OP_SH_RS2);
966 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
967 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
970 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
971 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
974 /* Helper for DECODE, decode 32-bit I-type instruction. */
975 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
978 m_rd = decode_register_index (ival, OP_SH_RD);
979 m_rs1 = decode_register_index (ival, OP_SH_RS1);
980 m_imm.s = EXTRACT_ITYPE_IMM (ival);
983 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
984 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
987 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
988 m_imm.s = EXTRACT_RVC_IMM (ival);
991 /* Helper for DECODE, decode 32-bit S-type instruction. */
992 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
995 m_rs1 = decode_register_index (ival, OP_SH_RS1);
996 m_rs2 = decode_register_index (ival, OP_SH_RS2);
997 m_imm.s = EXTRACT_STYPE_IMM (ival);
1000 /* Helper for DECODE, decode 32-bit U-type instruction. */
1001 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1004 m_rd = decode_register_index (ival, OP_SH_RD);
1005 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1008 /* Helper for DECODE, decode 32-bit J-type instruction. */
1009 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1012 m_rd = decode_register_index (ival, OP_SH_RD);
1013 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1016 /* Helper for DECODE, decode 32-bit J-type instruction. */
1017 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1020 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1023 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1026 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1027 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1028 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1031 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1034 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1035 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1038 /* Fetch instruction from target memory at ADDR, return the content of
1039 the instruction, and update LEN with the instruction length. */
1040 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1041 CORE_ADDR addr, int *len);
1043 /* The length of the instruction in bytes. Should be 2 or 4. */
1046 /* The instruction opcode. */
1047 enum opcode m_opcode;
1049 /* The three possible registers an instruction might reference. Not
1050 every instruction fills in all of these registers. Which fields are
1051 valid depends on the opcode. The naming of these fields matches the
1052 naming in the riscv isa manual. */
1057 /* Possible instruction immediate. This is only valid if the instruction
1058 format contains an immediate, not all instruction, whether this is
1059 valid depends on the opcode. Despite only having one format for now
1060 the immediate is packed into a union, later instructions might require
1061 an unsigned formatted immediate, having the union in place now will
1062 reduce the need for code churn later. */
1063 union riscv_insn_immediate
1065 riscv_insn_immediate ()
1075 /* Fetch instruction from target memory at ADDR, return the content of the
1076 instruction, and update LEN with the instruction length. */
1079 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1080 CORE_ADDR addr, int *len)
1082 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1084 int instlen, status;
1086 /* All insns are at least 16 bits. */
1087 status = target_read_memory (addr, buf, 2);
1089 memory_error (TARGET_XFER_E_IO, addr);
1091 /* If we need more, grab it now. */
1092 instlen = riscv_insn_length (buf[0]);
1093 gdb_assert (instlen <= sizeof (buf));
1098 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1100 memory_error (TARGET_XFER_E_IO, addr + 2);
1103 return extract_unsigned_integer (buf, instlen, byte_order);
1106 /* Fetch from target memory an instruction at PC and decode it. */
1109 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1113 /* Fetch the instruction, and the instructions length. */
1114 ival = fetch_instruction (gdbarch, pc, &m_length);
1118 if (is_add_insn (ival))
1119 decode_r_type_insn (ADD, ival);
1120 else if (is_addw_insn (ival))
1121 decode_r_type_insn (ADDW, ival);
1122 else if (is_addi_insn (ival))
1123 decode_i_type_insn (ADDI, ival);
1124 else if (is_addiw_insn (ival))
1125 decode_i_type_insn (ADDIW, ival);
1126 else if (is_auipc_insn (ival))
1127 decode_u_type_insn (AUIPC, ival);
1128 else if (is_lui_insn (ival))
1129 decode_u_type_insn (LUI, ival);
1130 else if (is_sd_insn (ival))
1131 decode_s_type_insn (SD, ival);
1132 else if (is_sw_insn (ival))
1133 decode_s_type_insn (SW, ival);
1134 else if (is_jal_insn (ival))
1135 decode_j_type_insn (JAL, ival);
1136 else if (is_jalr_insn (ival))
1137 decode_i_type_insn (JALR, ival);
1138 else if (is_beq_insn (ival))
1139 decode_b_type_insn (BEQ, ival);
1140 else if (is_bne_insn (ival))
1141 decode_b_type_insn (BNE, ival);
1142 else if (is_blt_insn (ival))
1143 decode_b_type_insn (BLT, ival);
1144 else if (is_bge_insn (ival))
1145 decode_b_type_insn (BGE, ival);
1146 else if (is_bltu_insn (ival))
1147 decode_b_type_insn (BLTU, ival);
1148 else if (is_bgeu_insn (ival))
1149 decode_b_type_insn (BGEU, ival);
1150 else if (is_lr_w_insn (ival))
1151 decode_r_type_insn (LR, ival);
1152 else if (is_lr_d_insn (ival))
1153 decode_r_type_insn (LR, ival);
1154 else if (is_sc_w_insn (ival))
1155 decode_r_type_insn (SC, ival);
1156 else if (is_sc_d_insn (ival))
1157 decode_r_type_insn (SC, ival);
1159 /* None of the other fields are valid in this case. */
1162 else if (m_length == 2)
1164 int xlen = riscv_isa_xlen (gdbarch);
1166 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1167 C_JALR. So must try to match C_JALR first as it has more bits in
1169 if (is_c_jalr_insn (ival))
1170 decode_cr_type_insn (JALR, ival);
1171 else if (is_c_add_insn (ival))
1172 decode_cr_type_insn (ADD, ival);
1173 /* C_ADDW is RV64 and RV128 only. */
1174 else if (xlen != 4 && is_c_addw_insn (ival))
1175 decode_cr_type_insn (ADDW, ival);
1176 else if (is_c_addi_insn (ival))
1177 decode_ci_type_insn (ADDI, ival);
1178 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1179 only and C_JAL is RV32 only. */
1180 else if (xlen != 4 && is_c_addiw_insn (ival))
1181 decode_ci_type_insn (ADDIW, ival);
1182 else if (xlen == 4 && is_c_jal_insn (ival))
1183 decode_cj_type_insn (JAL, ival);
1184 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1185 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1187 else if (is_c_addi16sp_insn (ival))
1190 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1191 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1193 else if (is_c_lui_insn (ival))
1195 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1196 and C_FSW is RV32 only. */
1197 else if (xlen != 4 && is_c_sd_insn (ival))
1199 else if (is_c_sw_insn (ival))
1201 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1202 So must try to match C_JR first as it ahs more bits in mask. */
1203 else if (is_c_jr_insn (ival))
1204 decode_cr_type_insn (JALR, ival);
1205 else if (is_c_j_insn (ival))
1206 decode_cj_type_insn (JAL, ival);
1207 else if (is_c_beqz_insn (ival))
1208 decode_cb_type_insn (BEQ, ival);
1209 else if (is_c_bnez_insn (ival))
1210 decode_cb_type_insn (BNE, ival);
1212 /* None of the other fields of INSN are valid in this case. */
1216 internal_error (__FILE__, __LINE__,
1217 _("unable to decode %d byte instructions in "
1218 "prologue at %s"), m_length,
1219 core_addr_to_string (pc));
1222 /* The prologue scanner. This is currently only used for skipping the
1223 prologue of a function when the DWARF information is not sufficient.
1224 However, it is written with filling of the frame cache in mind, which
1225 is why different groups of stack setup instructions are split apart
1226 during the core of the inner loop. In the future, the intention is to
1227 extend this function to fully support building up a frame cache that
1228 can unwind register values when there is no DWARF information. */
1231 riscv_scan_prologue (struct gdbarch *gdbarch,
1232 CORE_ADDR start_pc, CORE_ADDR limit_pc)
1234 CORE_ADDR cur_pc, next_pc;
1235 long frame_offset = 0;
1236 CORE_ADDR end_prologue_addr = 0;
1238 if (limit_pc > start_pc + 200)
1239 limit_pc = start_pc + 200;
1241 for (next_pc = cur_pc = start_pc; cur_pc < limit_pc; cur_pc = next_pc)
1243 struct riscv_insn insn;
1245 /* Decode the current instruction, and decide where the next
1246 instruction lives based on the size of this instruction. */
1247 insn.decode (gdbarch, cur_pc);
1248 gdb_assert (insn.length () > 0);
1249 next_pc = cur_pc + insn.length ();
1251 /* Look for common stack adjustment insns. */
1252 if ((insn.opcode () == riscv_insn::ADDI
1253 || insn.opcode () == riscv_insn::ADDIW)
1254 && insn.rd () == RISCV_SP_REGNUM
1255 && insn.rs1 () == RISCV_SP_REGNUM)
1257 /* Handle: addi sp, sp, -i
1258 or: addiw sp, sp, -i */
1259 if (insn.imm_signed () < 0)
1260 frame_offset += insn.imm_signed ();
1264 else if ((insn.opcode () == riscv_insn::SW
1265 || insn.opcode () == riscv_insn::SD)
1266 && (insn.rs1 () == RISCV_SP_REGNUM
1267 || insn.rs1 () == RISCV_FP_REGNUM))
1269 /* Handle: sw reg, offset(sp)
1270 or: sd reg, offset(sp)
1271 or: sw reg, offset(s0)
1272 or: sd reg, offset(s0) */
1273 /* Instruction storing a register onto the stack. */
1275 else if (insn.opcode () == riscv_insn::ADDI
1276 && insn.rd () == RISCV_FP_REGNUM
1277 && insn.rs1 () == RISCV_SP_REGNUM)
1279 /* Handle: addi s0, sp, size */
1280 /* Instructions setting up the frame pointer. */
1282 else if ((insn.opcode () == riscv_insn::ADD
1283 || insn.opcode () == riscv_insn::ADDW)
1284 && insn.rd () == RISCV_FP_REGNUM
1285 && insn.rs1 () == RISCV_SP_REGNUM
1286 && insn.rs2 () == RISCV_ZERO_REGNUM)
1288 /* Handle: add s0, sp, 0
1289 or: addw s0, sp, 0 */
1290 /* Instructions setting up the frame pointer. */
1292 else if ((insn.rd () == RISCV_GP_REGNUM
1293 && (insn.opcode () == riscv_insn::AUIPC
1294 || insn.opcode () == riscv_insn::LUI
1295 || (insn.opcode () == riscv_insn::ADDI
1296 && insn.rs1 () == RISCV_GP_REGNUM)
1297 || (insn.opcode () == riscv_insn::ADD
1298 && (insn.rs1 () == RISCV_GP_REGNUM
1299 || insn.rs2 () == RISCV_GP_REGNUM))))
1300 || (insn.opcode () == riscv_insn::ADDI
1301 && insn.rd () == RISCV_ZERO_REGNUM
1302 && insn.rs1 () == RISCV_ZERO_REGNUM
1303 && insn.imm_signed () == 0))
1305 /* Handle: auipc gp, n
1310 or: add x0, x0, 0 (NOP) */
1311 /* These instructions are part of the prologue, but we don't need
1312 to do anything special to handle them. */
1316 if (end_prologue_addr == 0)
1317 end_prologue_addr = cur_pc;
1321 if (end_prologue_addr == 0)
1322 end_prologue_addr = cur_pc;
1324 return end_prologue_addr;
1327 /* Implement the riscv_skip_prologue gdbarch method. */
1330 riscv_skip_prologue (struct gdbarch *gdbarch,
1334 CORE_ADDR func_addr;
1336 /* See if we can determine the end of the prologue via the symbol
1337 table. If so, then return either PC, or the PC after the
1338 prologue, whichever is greater. */
1339 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1341 CORE_ADDR post_prologue_pc
1342 = skip_prologue_using_sal (gdbarch, func_addr);
1344 if (post_prologue_pc != 0)
1345 return std::max (pc, post_prologue_pc);
1348 /* Can't determine prologue from the symbol table, need to examine
1351 /* Find an upper limit on the function prologue using the debug
1352 information. If the debug information could not be used to provide
1353 that bound, then use an arbitrary large number as the upper bound. */
1354 limit_pc = skip_prologue_using_sal (gdbarch, pc);
1356 limit_pc = pc + 100; /* MAGIC! */
1358 return riscv_scan_prologue (gdbarch, pc, limit_pc);
1361 /* Implement the gdbarch push dummy code callback. */
1364 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1365 CORE_ADDR funaddr, struct value **args, int nargs,
1366 struct type *value_type, CORE_ADDR *real_pc,
1367 CORE_ADDR *bp_addr, struct regcache *regcache)
1369 /* Allocate space for a breakpoint, and keep the stack correctly
1377 /* Compute the alignment of the type T. Used while setting up the
1378 arguments for a dummy call. */
1381 riscv_type_alignment (struct type *t)
1383 t = check_typedef (t);
1384 switch (TYPE_CODE (t))
1387 error (_("Could not compute alignment of type"));
1389 case TYPE_CODE_RVALUE_REF:
1391 case TYPE_CODE_ENUM:
1395 case TYPE_CODE_CHAR:
1396 case TYPE_CODE_BOOL:
1397 return TYPE_LENGTH (t);
1399 case TYPE_CODE_ARRAY:
1400 case TYPE_CODE_COMPLEX:
1401 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1403 case TYPE_CODE_STRUCT:
1404 case TYPE_CODE_UNION:
1409 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1411 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1413 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1423 /* Holds information about a single argument either being passed to an
1424 inferior function, or returned from an inferior function. This includes
1425 information about the size, type, etc of the argument, and also
1426 information about how the argument will be passed (or returned). */
1428 struct riscv_arg_info
1430 /* Contents of the argument. */
1431 const gdb_byte *contents;
1433 /* Length of argument. */
1436 /* Alignment required for an argument of this type. */
1439 /* The type for this argument. */
1442 /* Each argument can have either 1 or 2 locations assigned to it. Each
1443 location describes where part of the argument will be placed. The
1444 second location is valid based on the LOC_TYPE and C_LENGTH fields
1445 of the first location (which is always valid). */
1448 /* What type of location this is. */
1451 /* Argument passed in a register. */
1454 /* Argument passed as an on stack argument. */
1457 /* Argument passed by reference. The second location is always
1458 valid for a BY_REF argument, and describes where the address
1459 of the BY_REF argument should be placed. */
1463 /* Information that depends on the location type. */
1466 /* Which register number to use. */
1469 /* The offset into the stack region. */
1473 /* The length of contents covered by this location. If this is less
1474 than the total length of the argument, then the second location
1475 will be valid, and will describe where the rest of the argument
1479 /* The offset within CONTENTS for this part of the argument. Will
1480 always be 0 for the first part. For the second part of the
1481 argument, this might be the C_LENGTH value of the first part,
1482 however, if we are passing a structure in two registers, and there's
1483 is padding between the first and second field, then this offset
1484 might be greater than the length of the first argument part. When
1485 the second argument location is not holding part of the argument
1486 value, but is instead holding the address of a reference argument,
1487 then this offset will be set to 0. */
1492 /* Information about a set of registers being used for passing arguments as
1493 part of a function call. The register set must be numerically
1494 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1495 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1497 struct riscv_arg_reg
1499 riscv_arg_reg (int first, int last)
1500 : next_regnum (first),
1506 /* The GDB register number to use in this set. */
1509 /* The last GDB register number to use in this set. */
1513 /* Arguments can be passed as on stack arguments, or by reference. The
1514 on stack arguments must be in a continuous region starting from $sp,
1515 while the by reference arguments can be anywhere, but we'll put them
1516 on the stack after (at higher address) the on stack arguments.
1518 This might not be the right approach to take. The ABI is clear that
1519 an argument passed by reference can be modified by the callee, which
1520 us placing the argument (temporarily) onto the stack will not achieve
1521 (changes will be lost). There's also the possibility that very large
1522 arguments could overflow the stack.
1524 This struct is used to track offset into these two areas for where
1525 arguments are to be placed. */
1526 struct riscv_memory_offsets
1528 riscv_memory_offsets ()
1535 /* Offset into on stack argument area. */
1538 /* Offset into the pass by reference area. */
1542 /* Holds information about where arguments to a call will be placed. This
1543 is updated as arguments are added onto the call, and can be used to
1544 figure out where the next argument should be placed. */
1546 struct riscv_call_info
1548 riscv_call_info (struct gdbarch *gdbarch)
1549 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1550 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1552 xlen = riscv_isa_xlen (gdbarch);
1553 flen = riscv_isa_flen (gdbarch);
1555 /* Disable use of floating point registers if needed. */
1556 if (!riscv_has_fp_abi (gdbarch))
1557 float_regs.next_regnum = float_regs.last_regnum + 1;
1560 /* Track the memory areas used for holding in-memory arguments to a
1562 struct riscv_memory_offsets memory;
1564 /* Holds information about the next integer register to use for passing
1566 struct riscv_arg_reg int_regs;
1568 /* Holds information about the next floating point register to use for
1569 passing an argument. */
1570 struct riscv_arg_reg float_regs;
1572 /* The XLEN and FLEN are copied in to this structure for convenience, and
1573 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1578 /* Return the number of registers available for use as parameters in the
1579 register set REG. Returned value can be 0 or more. */
1582 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1584 if (reg->next_regnum > reg->last_regnum)
1587 return (reg->last_regnum - reg->next_regnum + 1);
1590 /* If there is at least one register available in the register set REG then
1591 the next register from REG is assigned to LOC and the length field of
1592 LOC is updated to LENGTH. The register set REG is updated to indicate
1593 that the assigned register is no longer available and the function
1596 If there are no registers available in REG then the function returns
1597 false, and LOC and REG are unchanged. */
1600 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1601 struct riscv_arg_reg *reg,
1602 int length, int offset)
1604 if (reg->next_regnum <= reg->last_regnum)
1606 loc->loc_type = riscv_arg_info::location::in_reg;
1607 loc->loc_data.regno = reg->next_regnum;
1609 loc->c_length = length;
1610 loc->c_offset = offset;
1617 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1618 record that an area of stack has been used to hold the parameter
1621 The length field of LOC is updated to LENGTH, the length of the
1622 parameter being stored, and ALIGN is the alignment required by the
1623 parameter, which will affect how memory is allocated out of MEMORY. */
1626 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1627 struct riscv_memory_offsets *memory,
1628 int length, int align)
1630 loc->loc_type = riscv_arg_info::location::on_stack;
1632 = align_up (memory->arg_offset, align);
1633 loc->loc_data.offset = memory->arg_offset;
1634 memory->arg_offset += length;
1635 loc->c_length = length;
1637 /* Offset is always 0, either we're the first location part, in which
1638 case we're reading content from the start of the argument, or we're
1639 passing the address of a reference argument, so 0. */
1643 /* Update AINFO, which describes an argument that should be passed or
1644 returned using the integer ABI. The argloc fields within AINFO are
1645 updated to describe the location in which the argument will be passed to
1646 a function, or returned from a function.
1648 The CINFO structure contains the ongoing call information, the holds
1649 information such as which argument registers are remaining to be
1650 assigned to parameter, and how much memory has been used by parameters
1653 By examining the state of CINFO a suitable location can be selected,
1654 and assigned to AINFO. */
1657 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1658 struct riscv_call_info *cinfo)
1660 if (ainfo->length > (2 * cinfo->xlen))
1662 /* Argument is going to be passed by reference. */
1663 ainfo->argloc[0].loc_type
1664 = riscv_arg_info::location::by_ref;
1665 cinfo->memory.ref_offset
1666 = align_up (cinfo->memory.ref_offset, ainfo->align);
1667 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1668 cinfo->memory.ref_offset += ainfo->length;
1669 ainfo->argloc[0].c_length = ainfo->length;
1671 /* The second location for this argument is given over to holding the
1672 address of the by-reference data. Pass 0 for the offset as this
1673 is not part of the actual argument value. */
1674 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1677 riscv_assign_stack_location (&ainfo->argloc[1],
1678 &cinfo->memory, cinfo->xlen,
1683 int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length;
1685 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1686 &cinfo->int_regs, len, 0))
1687 riscv_assign_stack_location (&ainfo->argloc[0],
1688 &cinfo->memory, len, ainfo->align);
1690 if (len < ainfo->length)
1692 len = ainfo->length - len;
1693 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1694 &cinfo->int_regs, len,
1696 riscv_assign_stack_location (&ainfo->argloc[1],
1697 &cinfo->memory, len, cinfo->xlen);
1702 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1703 is being passed with the floating point ABI. */
1706 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1707 struct riscv_call_info *cinfo)
1709 if (ainfo->length > cinfo->flen)
1710 return riscv_call_arg_scalar_int (ainfo, cinfo);
1713 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1716 return riscv_call_arg_scalar_int (ainfo, cinfo);
1720 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1721 is a complex floating point argument, and is therefore handled
1722 differently to other argument types. */
1725 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1726 struct riscv_call_info *cinfo)
1728 if (ainfo->length <= (2 * cinfo->flen)
1729 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1732 int len = ainfo->length / 2;
1734 result = riscv_assign_reg_location (&ainfo->argloc[0],
1735 &cinfo->float_regs, len, len);
1736 gdb_assert (result);
1738 result = riscv_assign_reg_location (&ainfo->argloc[1],
1739 &cinfo->float_regs, len, len);
1740 gdb_assert (result);
1743 return riscv_call_arg_scalar_int (ainfo, cinfo);
1746 /* A structure used for holding information about a structure type within
1747 the inferior program. The RiscV ABI has special rules for handling some
1748 structures with a single field or with two fields. The counting of
1749 fields here is done after flattening out all nested structures. */
1751 class riscv_struct_info
1754 riscv_struct_info ()
1755 : m_number_of_fields (0),
1756 m_types { nullptr, nullptr }
1761 /* Analyse TYPE descending into nested structures, count the number of
1762 scalar fields and record the types of the first two fields found. */
1763 void analyse (struct type *type);
1765 /* The number of scalar fields found in the analysed type. This is
1766 currently only accurate if the value returned is 0, 1, or 2 as the
1767 analysis stops counting when the number of fields is 3. This is
1768 because the RiscV ABI only has special cases for 1 or 2 fields,
1769 anything else we just don't care about. */
1770 int number_of_fields () const
1771 { return m_number_of_fields; }
1773 /* Return the type for scalar field INDEX within the analysed type. Will
1774 return nullptr if there is no field at that index. Only INDEX values
1775 0 and 1 can be requested as the RiscV ABI only has special cases for
1776 structures with 1 or 2 fields. */
1777 struct type *field_type (int index) const
1779 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
1780 return m_types[index];
1784 /* The number of scalar fields found within the structure after recursing
1785 into nested structures. */
1786 int m_number_of_fields;
1788 /* The types of the first two scalar fields found within the structure
1789 after recursing into nested structures. */
1790 struct type *m_types[2];
1793 /* Analyse TYPE descending into nested structures, count the number of
1794 scalar fields and record the types of the first two fields found. */
1797 riscv_struct_info::analyse (struct type *type)
1799 unsigned int count = TYPE_NFIELDS (type);
1802 for (i = 0; i < count; ++i)
1804 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
1807 struct type *field_type = TYPE_FIELD_TYPE (type, i);
1808 field_type = check_typedef (field_type);
1810 switch (TYPE_CODE (field_type))
1812 case TYPE_CODE_STRUCT:
1813 analyse (field_type);
1817 /* RiscV only flattens out structures. Anything else does not
1818 need to be flattened, we just record the type, and when we
1819 look at the analysis results we'll realise this is not a
1820 structure we can special case, and pass the structure in
1822 if (m_number_of_fields < 2)
1823 m_types[m_number_of_fields] = field_type;
1824 m_number_of_fields++;
1828 /* RiscV only has special handling for structures with 1 or 2 scalar
1829 fields, any more than that and the structure is just passed in
1830 memory. We can safely drop out early when we find 3 or more
1833 if (m_number_of_fields > 2)
1838 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1839 is a structure. Small structures on RiscV have some special case
1840 handling in order that the structure might be passed in register.
1841 Larger structures are passed in memory. After assigning location
1842 information to AINFO, CINFO will have been updated. */
1845 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
1846 struct riscv_call_info *cinfo)
1848 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
1850 struct riscv_struct_info sinfo;
1852 sinfo.analyse (ainfo->type);
1853 if (sinfo.number_of_fields () == 1
1854 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
1856 gdb_assert (TYPE_LENGTH (ainfo->type)
1857 == TYPE_LENGTH (sinfo.field_type (0)));
1858 return riscv_call_arg_complex_float (ainfo, cinfo);
1861 if (sinfo.number_of_fields () == 1
1862 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
1864 gdb_assert (TYPE_LENGTH (ainfo->type)
1865 == TYPE_LENGTH (sinfo.field_type (0)));
1866 return riscv_call_arg_scalar_float (ainfo, cinfo);
1869 if (sinfo.number_of_fields () == 2
1870 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
1871 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
1872 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
1873 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
1874 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1876 int len0, len1, offset;
1878 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
1880 len0 = TYPE_LENGTH (sinfo.field_type (0));
1881 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1882 &cinfo->float_regs, len0, 0))
1883 error (_("failed during argument setup"));
1885 len1 = TYPE_LENGTH (sinfo.field_type (1));
1886 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
1887 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
1888 - TYPE_LENGTH (sinfo.field_type (0))));
1890 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1893 error (_("failed during argument setup"));
1897 if (sinfo.number_of_fields () == 2
1898 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
1899 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
1900 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
1901 && is_integral_type (sinfo.field_type (1))
1902 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
1904 int len0, len1, offset;
1906 gdb_assert (TYPE_LENGTH (ainfo->type)
1907 <= (cinfo->flen + cinfo->xlen));
1909 len0 = TYPE_LENGTH (sinfo.field_type (0));
1910 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1911 &cinfo->float_regs, len0, 0))
1912 error (_("failed during argument setup"));
1914 len1 = TYPE_LENGTH (sinfo.field_type (1));
1915 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
1916 gdb_assert (len1 <= cinfo->xlen);
1917 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1918 &cinfo->int_regs, len1, offset))
1919 error (_("failed during argument setup"));
1923 if (sinfo.number_of_fields () == 2
1924 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
1925 && (is_integral_type (sinfo.field_type (0))
1926 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
1927 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
1928 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
1930 int len0, len1, offset;
1932 gdb_assert (TYPE_LENGTH (ainfo->type)
1933 <= (cinfo->flen + cinfo->xlen));
1935 len0 = TYPE_LENGTH (sinfo.field_type (0));
1936 len1 = TYPE_LENGTH (sinfo.field_type (1));
1937 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
1939 gdb_assert (len0 <= cinfo->xlen);
1940 gdb_assert (len1 <= cinfo->flen);
1942 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1943 &cinfo->int_regs, len0, 0))
1944 error (_("failed during argument setup"));
1946 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1949 error (_("failed during argument setup"));
1955 /* Non of the structure flattening cases apply, so we just pass using
1957 ainfo->length = align_up (ainfo->length, cinfo->xlen);
1958 riscv_call_arg_scalar_int (ainfo, cinfo);
1961 /* Assign a location to call (or return) argument AINFO, the location is
1962 selected from CINFO which holds information about what call argument
1963 locations are available for use next. The TYPE is the type of the
1964 argument being passed, this information is recorded into AINFO (along
1965 with some additional information derived from the type).
1967 After assigning a location to AINFO, CINFO will have been updated. */
1970 riscv_arg_location (struct gdbarch *gdbarch,
1971 struct riscv_arg_info *ainfo,
1972 struct riscv_call_info *cinfo,
1976 ainfo->length = TYPE_LENGTH (ainfo->type);
1977 ainfo->align = riscv_type_alignment (ainfo->type);
1978 ainfo->contents = nullptr;
1980 switch (TYPE_CODE (ainfo->type))
1983 case TYPE_CODE_BOOL:
1984 case TYPE_CODE_CHAR:
1985 case TYPE_CODE_RANGE:
1986 case TYPE_CODE_ENUM:
1988 if (ainfo->length <= cinfo->xlen)
1990 ainfo->type = builtin_type (gdbarch)->builtin_long;
1991 ainfo->length = cinfo->xlen;
1993 else if (ainfo->length <= (2 * cinfo->xlen))
1995 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
1996 ainfo->length = 2 * cinfo->xlen;
1999 /* Recalculate the alignment requirement. */
2000 ainfo->align = riscv_type_alignment (ainfo->type);
2001 riscv_call_arg_scalar_int (ainfo, cinfo);
2005 riscv_call_arg_scalar_float (ainfo, cinfo);
2008 case TYPE_CODE_COMPLEX:
2009 riscv_call_arg_complex_float (ainfo, cinfo);
2012 case TYPE_CODE_STRUCT:
2013 riscv_call_arg_struct (ainfo, cinfo);
2017 riscv_call_arg_scalar_int (ainfo, cinfo);
2022 /* Used for printing debug information about the call argument location in
2023 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2024 addresses for the location of pass-by-reference and
2025 arguments-on-the-stack memory areas. */
2028 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2029 struct riscv_arg_info *info,
2030 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2032 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2033 TYPE_SAFE_NAME (info->type), info->length, info->align);
2034 switch (info->argloc[0].loc_type)
2036 case riscv_arg_info::location::in_reg:
2038 (stream, ", register %s",
2039 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2040 if (info->argloc[0].c_length < info->length)
2042 switch (info->argloc[1].loc_type)
2044 case riscv_arg_info::location::in_reg:
2046 (stream, ", register %s",
2047 gdbarch_register_name (gdbarch,
2048 info->argloc[1].loc_data.regno));
2051 case riscv_arg_info::location::on_stack:
2052 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2053 info->argloc[1].loc_data.offset);
2056 case riscv_arg_info::location::by_ref:
2058 /* The second location should never be a reference, any
2059 argument being passed by reference just places its address
2060 in the first location and is done. */
2061 error (_("invalid argument location"));
2065 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2066 fprintf_unfiltered (stream, " (offset 0x%x)",
2067 info->argloc[1].c_offset);
2071 case riscv_arg_info::location::on_stack:
2072 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2073 info->argloc[0].loc_data.offset);
2076 case riscv_arg_info::location::by_ref:
2078 (stream, ", by reference, data at offset 0x%x (%s)",
2079 info->argloc[0].loc_data.offset,
2080 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2081 if (info->argloc[1].loc_type
2082 == riscv_arg_info::location::in_reg)
2084 (stream, ", address in register %s",
2085 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2088 gdb_assert (info->argloc[1].loc_type
2089 == riscv_arg_info::location::on_stack);
2091 (stream, ", address on stack at offset 0x%x (%s)",
2092 info->argloc[1].loc_data.offset,
2093 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2098 gdb_assert_not_reached (_("unknown argument location type"));
2102 /* Implement the push dummy call gdbarch callback. */
2105 riscv_push_dummy_call (struct gdbarch *gdbarch,
2106 struct value *function,
2107 struct regcache *regcache,
2110 struct value **args,
2113 CORE_ADDR struct_addr)
2116 CORE_ADDR sp_args, sp_refs;
2117 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2119 struct riscv_arg_info *arg_info =
2120 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2121 struct riscv_arg_info *info;
2123 struct riscv_call_info call_info (gdbarch);
2127 /* We'll use register $a0 if we're returning a struct. */
2129 ++call_info.int_regs.next_regnum;
2131 for (i = 0, info = &arg_info[0];
2135 struct value *arg_value;
2136 struct type *arg_type;
2138 arg_value = args[i];
2139 arg_type = check_typedef (value_type (arg_value));
2141 riscv_arg_location (gdbarch, info, &call_info, arg_type);
2143 if (info->type != arg_type)
2144 arg_value = value_cast (info->type, arg_value);
2145 info->contents = value_contents (arg_value);
2148 /* Adjust the stack pointer and align it. */
2149 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2150 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2152 if (riscv_debug_infcall > 0)
2154 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2155 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2156 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2157 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2158 call_info.xlen, call_info.flen);
2160 fprintf_unfiltered (gdb_stdlog,
2161 "[*] struct return pointer in register $A0\n");
2162 for (i = 0; i < nargs; ++i)
2164 struct riscv_arg_info *info = &arg_info [i];
2166 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2167 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2168 fprintf_unfiltered (gdb_stdlog, "\n");
2170 if (call_info.memory.arg_offset > 0
2171 || call_info.memory.ref_offset > 0)
2173 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2174 core_addr_to_string (osp));
2175 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2176 call_info.memory.arg_offset);
2177 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2178 call_info.memory.ref_offset);
2179 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2180 core_addr_to_string_nz (osp - sp));
2184 /* Now load the argument into registers, or onto the stack. */
2188 gdb_byte buf[sizeof (LONGEST)];
2190 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2191 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2194 for (i = 0; i < nargs; ++i)
2197 int second_arg_length = 0;
2198 const gdb_byte *second_arg_data;
2199 struct riscv_arg_info *info = &arg_info [i];
2201 gdb_assert (info->length > 0);
2203 switch (info->argloc[0].loc_type)
2205 case riscv_arg_info::location::in_reg:
2207 gdb_byte tmp [sizeof (ULONGEST)];
2209 gdb_assert (info->argloc[0].c_length <= info->length);
2210 memset (tmp, 0, sizeof (tmp));
2211 memcpy (tmp, info->contents, info->argloc[0].c_length);
2212 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2214 ((info->argloc[0].c_length < info->length)
2215 ? info->argloc[1].c_length : 0);
2216 second_arg_data = info->contents + info->argloc[1].c_offset;
2220 case riscv_arg_info::location::on_stack:
2221 dst = sp_args + info->argloc[0].loc_data.offset;
2222 write_memory (dst, info->contents, info->length);
2223 second_arg_length = 0;
2226 case riscv_arg_info::location::by_ref:
2227 dst = sp_refs + info->argloc[0].loc_data.offset;
2228 write_memory (dst, info->contents, info->length);
2230 second_arg_length = call_info.xlen;
2231 second_arg_data = (gdb_byte *) &dst;
2235 gdb_assert_not_reached (_("unknown argument location type"));
2238 if (second_arg_length > 0)
2240 switch (info->argloc[1].loc_type)
2242 case riscv_arg_info::location::in_reg:
2244 gdb_byte tmp [sizeof (ULONGEST)];
2246 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2247 && second_arg_length <= call_info.flen)
2248 || second_arg_length <= call_info.xlen);
2249 memset (tmp, 0, sizeof (tmp));
2250 memcpy (tmp, second_arg_data, second_arg_length);
2251 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2255 case riscv_arg_info::location::on_stack:
2259 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2260 write_memory (arg_addr, second_arg_data, second_arg_length);
2264 case riscv_arg_info::location::by_ref:
2266 /* The second location should never be a reference, any
2267 argument being passed by reference just places its address
2268 in the first location and is done. */
2269 error (_("invalid argument location"));
2275 /* Set the dummy return value to bp_addr.
2276 A dummy breakpoint will be setup to execute the call. */
2278 if (riscv_debug_infcall > 0)
2279 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2280 core_addr_to_string (bp_addr));
2281 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2283 /* Finally, update the stack pointer. */
2285 if (riscv_debug_infcall > 0)
2286 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2287 core_addr_to_string (sp));
2288 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2293 /* Implement the return_value gdbarch method. */
2295 static enum return_value_convention
2296 riscv_return_value (struct gdbarch *gdbarch,
2297 struct value *function,
2299 struct regcache *regcache,
2301 const gdb_byte *writebuf)
2303 struct riscv_call_info call_info (gdbarch);
2304 struct riscv_arg_info info;
2305 struct type *arg_type;
2307 arg_type = check_typedef (type);
2308 riscv_arg_location (gdbarch, &info, &call_info, arg_type);
2310 if (riscv_debug_infcall > 0)
2312 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2313 fprintf_unfiltered (gdb_stdlog, "[R] ");
2314 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2315 fprintf_unfiltered (gdb_stdlog, "\n");
2318 if (readbuf != nullptr || writebuf != nullptr)
2322 switch (info.argloc[0].loc_type)
2324 /* Return value in register(s). */
2325 case riscv_arg_info::location::in_reg:
2327 regnum = info.argloc[0].loc_data.regno;
2330 regcache->cooked_read (regnum, readbuf);
2333 regcache->cooked_write (regnum, writebuf);
2335 /* A return value in register can have a second part in a
2337 if (info.argloc[0].c_length < info.length)
2339 switch (info.argloc[1].loc_type)
2341 case riscv_arg_info::location::in_reg:
2342 regnum = info.argloc[1].loc_data.regno;
2346 readbuf += info.argloc[1].c_offset;
2347 regcache->cooked_read (regnum, readbuf);
2352 writebuf += info.argloc[1].c_offset;
2353 regcache->cooked_write (regnum, writebuf);
2357 case riscv_arg_info::location::by_ref:
2358 case riscv_arg_info::location::on_stack:
2360 error (_("invalid argument location"));
2367 /* Return value by reference will have its address in A0. */
2368 case riscv_arg_info::location::by_ref:
2372 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2374 if (readbuf != nullptr)
2375 read_memory (addr, readbuf, info.length);
2376 if (writebuf != nullptr)
2377 write_memory (addr, writebuf, info.length);
2381 case riscv_arg_info::location::on_stack:
2383 error (_("invalid argument location"));
2388 switch (info.argloc[0].loc_type)
2390 case riscv_arg_info::location::in_reg:
2391 return RETURN_VALUE_REGISTER_CONVENTION;
2392 case riscv_arg_info::location::by_ref:
2393 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2394 case riscv_arg_info::location::on_stack:
2396 error (_("invalid argument location"));
2400 /* Implement the frame_align gdbarch method. */
2403 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2405 return align_down (addr, 16);
2408 /* Implement the unwind_pc gdbarch method. */
2411 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2413 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2416 /* Implement the unwind_sp gdbarch method. */
2419 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2421 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2424 /* Implement the dummy_id gdbarch method. */
2426 static struct frame_id
2427 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2429 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2430 get_frame_pc (this_frame));
2433 /* Generate, or return the cached frame cache for the RiscV frame
2436 static struct trad_frame_cache *
2437 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2440 CORE_ADDR start_addr;
2441 CORE_ADDR stack_addr;
2442 struct trad_frame_cache *this_trad_cache;
2443 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2445 if ((*this_cache) != NULL)
2446 return (struct trad_frame_cache *) *this_cache;
2447 this_trad_cache = trad_frame_cache_zalloc (this_frame);
2448 (*this_cache) = this_trad_cache;
2450 trad_frame_set_reg_realreg (this_trad_cache, gdbarch_pc_regnum (gdbarch),
2453 pc = get_frame_pc (this_frame);
2454 find_pc_partial_function (pc, NULL, &start_addr, NULL);
2455 stack_addr = get_frame_register_signed (this_frame, RISCV_SP_REGNUM);
2456 trad_frame_set_id (this_trad_cache, frame_id_build (stack_addr, start_addr));
2458 trad_frame_set_this_base (this_trad_cache, stack_addr);
2460 return this_trad_cache;
2463 /* Implement the this_id callback for RiscV frame unwinder. */
2466 riscv_frame_this_id (struct frame_info *this_frame,
2467 void **prologue_cache,
2468 struct frame_id *this_id)
2470 struct trad_frame_cache *info;
2472 info = riscv_frame_cache (this_frame, prologue_cache);
2473 trad_frame_get_id (info, this_id);
2476 /* Implement the prev_register callback for RiscV frame unwinder. */
2478 static struct value *
2479 riscv_frame_prev_register (struct frame_info *this_frame,
2480 void **prologue_cache,
2483 struct trad_frame_cache *info;
2485 info = riscv_frame_cache (this_frame, prologue_cache);
2486 return trad_frame_get_register (info, this_frame, regnum);
2489 /* Structure defining the RiscV normal frame unwind functions. Since we
2490 are the fallback unwinder (DWARF unwinder is used first), we use the
2491 default frame sniffer, which always accepts the frame. */
2493 static const struct frame_unwind riscv_frame_unwind =
2495 /*.type =*/ NORMAL_FRAME,
2496 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2497 /*.this_id =*/ riscv_frame_this_id,
2498 /*.prev_register =*/ riscv_frame_prev_register,
2499 /*.unwind_data =*/ NULL,
2500 /*.sniffer =*/ default_frame_sniffer,
2501 /*.dealloc_cache =*/ NULL,
2502 /*.prev_arch =*/ NULL,
2505 /* Initialize the current architecture based on INFO. If possible,
2506 re-use an architecture from ARCHES, which is a list of
2507 architectures already created during this debugging session.
2509 Called e.g. at program startup, when reading a core file, and when
2510 reading a binary file. */
2512 static struct gdbarch *
2513 riscv_gdbarch_init (struct gdbarch_info info,
2514 struct gdbarch_list *arches)
2516 struct gdbarch *gdbarch;
2517 struct gdbarch_tdep *tdep;
2518 struct gdbarch_tdep tmp_tdep;
2521 /* Ideally, we'd like to get as much information from the target for
2522 things like register size, and whether the target has floating point
2523 hardware. However, there are some things that the target can't tell
2524 us, like, what ABI is being used.
2526 So, for now, we take as much information as possible from the ELF,
2527 including things like register size, and FP hardware support, along
2528 with information about the ABI.
2530 Information about this target is built up in TMP_TDEP, and then we
2531 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2532 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2533 memset (&tmp_tdep, 0, sizeof (tmp_tdep));
2535 if (info.abfd != NULL
2536 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2538 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2539 int e_flags = elf_elfheader (info.abfd)->e_flags;
2541 if (eclass == ELFCLASS32)
2542 tmp_tdep.abi.fields.base_len = 1;
2543 else if (eclass == ELFCLASS64)
2544 tmp_tdep.abi.fields.base_len = 2;
2546 internal_error (__FILE__, __LINE__,
2547 _("unknown ELF header class %d"), eclass);
2549 if (e_flags & EF_RISCV_RVC)
2550 tmp_tdep.core_features |= (1 << ('C' - 'A'));
2552 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2554 tmp_tdep.abi.fields.float_abi = 2;
2555 tmp_tdep.core_features |= (1 << ('D' - 'A'));
2556 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2558 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2560 tmp_tdep.abi.fields.float_abi = 1;
2561 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2566 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2568 if (binfo->bits_per_word == 32)
2569 tmp_tdep.abi.fields.base_len = 1;
2570 else if (binfo->bits_per_word == 64)
2571 tmp_tdep.abi.fields.base_len = 2;
2573 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2574 binfo->bits_per_word);
2577 /* Find a candidate among the list of pre-declared architectures. */
2578 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2580 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2581 if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
2582 return arches->gdbarch;
2584 /* None found, so create a new architecture from the information provided. */
2585 tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
2586 gdbarch = gdbarch_alloc (&info, tdep);
2587 memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep));
2589 /* Target data types. */
2590 set_gdbarch_short_bit (gdbarch, 16);
2591 set_gdbarch_int_bit (gdbarch, 32);
2592 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2593 set_gdbarch_long_long_bit (gdbarch, 64);
2594 set_gdbarch_float_bit (gdbarch, 32);
2595 set_gdbarch_double_bit (gdbarch, 64);
2596 set_gdbarch_long_double_bit (gdbarch, 128);
2597 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2598 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2599 set_gdbarch_char_signed (gdbarch, 0);
2601 /* Information about the target architecture. */
2602 set_gdbarch_return_value (gdbarch, riscv_return_value);
2603 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
2604 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
2606 /* Register architecture. */
2607 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
2608 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
2609 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
2610 set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
2611 set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
2613 /* Functions to supply register information. */
2614 set_gdbarch_register_name (gdbarch, riscv_register_name);
2615 set_gdbarch_register_type (gdbarch, riscv_register_type);
2616 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
2617 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
2619 /* Functions to analyze frames. */
2620 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
2621 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2622 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
2624 /* Functions to access frame data. */
2625 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
2626 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
2628 /* Functions handling dummy frames. */
2629 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2630 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
2631 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
2632 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
2634 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2636 dwarf2_append_unwinders (gdbarch);
2637 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
2639 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
2640 user_reg_add (gdbarch, riscv_register_aliases[i].name,
2641 value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
2643 /* Hook in OS ABI-specific overrides, if they have been registered. */
2644 gdbarch_init_osabi (info, gdbarch);
2650 /* Allocate new riscv_inferior_data object. */
2652 static struct riscv_inferior_data *
2653 riscv_new_inferior_data (void)
2655 struct riscv_inferior_data *inf_data
2656 = new (struct riscv_inferior_data);
2657 inf_data->misa_read = false;
2661 /* Free inferior data. */
2664 riscv_inferior_data_cleanup (struct inferior *inf, void *data)
2666 struct riscv_inferior_data *inf_data =
2667 static_cast <struct riscv_inferior_data *> (data);
2671 /* Return riscv_inferior_data for the given INFERIOR. If not yet created,
2674 struct riscv_inferior_data *
2675 riscv_inferior_data (struct inferior *const inf)
2677 struct riscv_inferior_data *inf_data;
2679 gdb_assert (inf != NULL);
2682 = (struct riscv_inferior_data *) inferior_data (inf, riscv_inferior_data_reg);
2683 if (inf_data == NULL)
2685 inf_data = riscv_new_inferior_data ();
2686 set_inferior_data (inf, riscv_inferior_data_reg, inf_data);
2692 /* Free the inferior data when an inferior exits. */
2695 riscv_invalidate_inferior_data (struct inferior *inf)
2697 struct riscv_inferior_data *inf_data;
2699 gdb_assert (inf != NULL);
2701 /* Don't call RISCV_INFERIOR_DATA as we don't want to create the data if
2702 we've not already created it by this point. */
2704 = (struct riscv_inferior_data *) inferior_data (inf, riscv_inferior_data_reg);
2705 if (inf_data != NULL)
2708 set_inferior_data (inf, riscv_inferior_data_reg, NULL);
2712 /* This decodes the current instruction and determines the address of the
2713 next instruction. */
2716 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
2718 struct gdbarch *gdbarch = regcache->arch ();
2719 struct riscv_insn insn;
2722 insn.decode (gdbarch, pc);
2723 next_pc = pc + insn.length ();
2725 if (insn.opcode () == riscv_insn::JAL)
2726 next_pc = pc + insn.imm_signed ();
2727 else if (insn.opcode () == riscv_insn::JALR)
2730 regcache->cooked_read (insn.rs1 (), &source);
2731 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
2733 else if (insn.opcode () == riscv_insn::BEQ)
2736 regcache->cooked_read (insn.rs1 (), &src1);
2737 regcache->cooked_read (insn.rs2 (), &src2);
2739 next_pc = pc + insn.imm_signed ();
2741 else if (insn.opcode () == riscv_insn::BNE)
2744 regcache->cooked_read (insn.rs1 (), &src1);
2745 regcache->cooked_read (insn.rs2 (), &src2);
2747 next_pc = pc + insn.imm_signed ();
2749 else if (insn.opcode () == riscv_insn::BLT)
2752 regcache->cooked_read (insn.rs1 (), &src1);
2753 regcache->cooked_read (insn.rs2 (), &src2);
2755 next_pc = pc + insn.imm_signed ();
2757 else if (insn.opcode () == riscv_insn::BGE)
2760 regcache->cooked_read (insn.rs1 (), &src1);
2761 regcache->cooked_read (insn.rs2 (), &src2);
2763 next_pc = pc + insn.imm_signed ();
2765 else if (insn.opcode () == riscv_insn::BLTU)
2767 ULONGEST src1, src2;
2768 regcache->cooked_read (insn.rs1 (), &src1);
2769 regcache->cooked_read (insn.rs2 (), &src2);
2771 next_pc = pc + insn.imm_signed ();
2773 else if (insn.opcode () == riscv_insn::BGEU)
2775 ULONGEST src1, src2;
2776 regcache->cooked_read (insn.rs1 (), &src1);
2777 regcache->cooked_read (insn.rs2 (), &src2);
2779 next_pc = pc + insn.imm_signed ();
2785 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
2786 for the end of the sequence and put the breakpoint there. */
2789 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
2792 struct gdbarch *gdbarch = regcache->arch ();
2793 struct riscv_insn insn;
2794 CORE_ADDR cur_step_pc = pc;
2795 CORE_ADDR last_addr = 0;
2797 /* First instruction has to be a load reserved. */
2798 insn.decode (gdbarch, cur_step_pc);
2799 if (insn.opcode () != riscv_insn::LR)
2801 cur_step_pc = cur_step_pc + insn.length ();
2803 /* Next instruction should be branch to exit. */
2804 insn.decode (gdbarch, cur_step_pc);
2805 if (insn.opcode () != riscv_insn::BNE)
2807 last_addr = cur_step_pc + insn.imm_signed ();
2808 cur_step_pc = cur_step_pc + insn.length ();
2810 /* Next instruction should be store conditional. */
2811 insn.decode (gdbarch, cur_step_pc);
2812 if (insn.opcode () != riscv_insn::SC)
2814 cur_step_pc = cur_step_pc + insn.length ();
2816 /* Next instruction should be branch to start. */
2817 insn.decode (gdbarch, cur_step_pc);
2818 if (insn.opcode () != riscv_insn::BNE)
2820 if (pc != (cur_step_pc + insn.imm_signed ()))
2822 cur_step_pc = cur_step_pc + insn.length ();
2824 /* We should now be at the end of the sequence. */
2825 if (cur_step_pc != last_addr)
2828 *next_pc = cur_step_pc;
2832 /* This is called just before we want to resume the inferior, if we want to
2833 single-step it but there is no hardware or kernel single-step support. We
2834 find the target of the coming instruction and breakpoint it. */
2836 std::vector<CORE_ADDR>
2837 riscv_software_single_step (struct regcache *regcache)
2839 CORE_ADDR pc, next_pc;
2841 pc = regcache_read_pc (regcache);
2843 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
2846 next_pc = riscv_next_pc (regcache, pc);
2852 _initialize_riscv_tdep (void)
2854 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
2856 /* Register per-inferior data. */
2857 riscv_inferior_data_reg
2858 = register_inferior_data_with_cleanup (NULL, riscv_inferior_data_cleanup);
2860 /* Observers used to invalidate the inferior data when needed. */
2861 gdb::observers::inferior_exit.attach (riscv_invalidate_inferior_data);
2862 gdb::observers::inferior_appeared.attach (riscv_invalidate_inferior_data);
2864 /* Add root prefix command for all "set debug riscv" and "show debug
2866 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
2867 _("RISC-V specific debug commands."),
2868 &setdebugriscvcmdlist, "set debug riscv ", 0,
2871 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
2872 _("RISC-V specific debug commands."),
2873 &showdebugriscvcmdlist, "show debug riscv ", 0,
2876 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
2877 &riscv_debug_infcall, _("\
2878 Set riscv inferior call debugging."), _("\
2879 Show riscv inferior call debugging."), _("\
2880 When non-zero, print debugging information for the riscv specific parts\n\
2881 of the inferior call mechanism."),
2883 show_riscv_debug_variable,
2884 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
2886 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2887 add_prefix_cmd ("riscv", no_class, set_riscv_command,
2888 _("RISC-V specific commands."),
2889 &setriscvcmdlist, "set riscv ", 0, &setlist);
2891 add_prefix_cmd ("riscv", no_class, show_riscv_command,
2892 _("RISC-V specific commands."),
2893 &showriscvcmdlist, "show riscv ", 0, &showlist);
2896 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
2897 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
2898 &use_compressed_breakpoints,
2900 Set debugger's use of compressed breakpoints."), _(" \
2901 Show debugger's use of compressed breakpoints."), _("\
2902 Debugging compressed code requires compressed breakpoints to be used. If\n \
2903 left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2904 is supported. If that doesn't give the correct behavior, then this option\n\
2907 show_use_compressed_breakpoints,