1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
59 /* The stack must be 16-byte aligned. */
60 #define SP_ALIGNMENT 16
62 /* Forward declarations. */
63 static bool riscv_has_feature (struct gdbarch *gdbarch, char feature);
65 /* Define a series of is_XXX_insn functions to check if the value INSN
66 is an instance of instruction XXX. */
67 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
68 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
70 return (insn & INSN_MASK) == INSN_MATCH; \
72 #include "opcode/riscv-opc.h"
75 /* Cached information about a frame. */
77 struct riscv_unwind_cache
79 /* The register from which we can calculate the frame base. This is
80 usually $sp or $fp. */
83 /* The offset from the current value in register FRAME_BASE_REG to the
84 actual frame base address. */
85 int frame_base_offset;
87 /* Information about previous register values. */
88 struct trad_frame_saved_reg *regs;
90 /* The id for this frame. */
91 struct frame_id this_id;
93 /* The base (stack) address for this frame. This is the stack pointer
94 value on entry to this frame before any adjustments are made. */
98 /* The preferred register names for all the general purpose and floating
99 point registers. These are what GDB will use when referencing a
102 static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
104 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1",
105 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4",
106 "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
108 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
109 "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3",
110 "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9",
114 /* Map alternative register names onto their GDB register number. */
116 struct riscv_register_alias
118 /* The register alias. Usually more descriptive than the
119 architectural name of the register. */
122 /* The GDB register number. */
126 /* Table of register aliases. */
128 static const struct riscv_register_alias riscv_register_aliases[] =
130 /* Aliases for general purpose registers. These are the architectural
131 names, as GDB uses the more user friendly names by default. */
132 { "x0", (RISCV_ZERO_REGNUM + 0) },
133 { "x1", (RISCV_ZERO_REGNUM + 1) },
134 { "x2", (RISCV_ZERO_REGNUM + 2) },
135 { "x3", (RISCV_ZERO_REGNUM + 3) },
136 { "x4", (RISCV_ZERO_REGNUM + 4) },
137 { "x5", (RISCV_ZERO_REGNUM + 5) },
138 { "x6", (RISCV_ZERO_REGNUM + 6) },
139 { "x7", (RISCV_ZERO_REGNUM + 7) },
140 { "x8", (RISCV_ZERO_REGNUM + 8) },
141 { "s0", (RISCV_ZERO_REGNUM + 8) }, /* fp, s0, and x8 are all aliases. */
142 { "x9", (RISCV_ZERO_REGNUM + 9) },
143 { "x10", (RISCV_ZERO_REGNUM + 10) },
144 { "x11", (RISCV_ZERO_REGNUM + 11) },
145 { "x12", (RISCV_ZERO_REGNUM + 12) },
146 { "x13", (RISCV_ZERO_REGNUM + 13) },
147 { "x14", (RISCV_ZERO_REGNUM + 14) },
148 { "x15", (RISCV_ZERO_REGNUM + 15) },
149 { "x16", (RISCV_ZERO_REGNUM + 16) },
150 { "x17", (RISCV_ZERO_REGNUM + 17) },
151 { "x18", (RISCV_ZERO_REGNUM + 18) },
152 { "x19", (RISCV_ZERO_REGNUM + 19) },
153 { "x20", (RISCV_ZERO_REGNUM + 20) },
154 { "x21", (RISCV_ZERO_REGNUM + 21) },
155 { "x22", (RISCV_ZERO_REGNUM + 22) },
156 { "x23", (RISCV_ZERO_REGNUM + 23) },
157 { "x24", (RISCV_ZERO_REGNUM + 24) },
158 { "x25", (RISCV_ZERO_REGNUM + 25) },
159 { "x26", (RISCV_ZERO_REGNUM + 26) },
160 { "x27", (RISCV_ZERO_REGNUM + 27) },
161 { "x28", (RISCV_ZERO_REGNUM + 28) },
162 { "x29", (RISCV_ZERO_REGNUM + 29) },
163 { "x30", (RISCV_ZERO_REGNUM + 30) },
164 { "x31", (RISCV_ZERO_REGNUM + 31) },
166 /* Aliases for the floating-point registers. These are the architectural
167 names as GDB uses the more user friendly names by default. */
168 { "f0", (RISCV_FIRST_FP_REGNUM + 0) },
169 { "f1", (RISCV_FIRST_FP_REGNUM + 1) },
170 { "f2", (RISCV_FIRST_FP_REGNUM + 2) },
171 { "f3", (RISCV_FIRST_FP_REGNUM + 3) },
172 { "f4", (RISCV_FIRST_FP_REGNUM + 4) },
173 { "f5", (RISCV_FIRST_FP_REGNUM + 5) },
174 { "f6", (RISCV_FIRST_FP_REGNUM + 6) },
175 { "f7", (RISCV_FIRST_FP_REGNUM + 7) },
176 { "f8", (RISCV_FIRST_FP_REGNUM + 8) },
177 { "f9", (RISCV_FIRST_FP_REGNUM + 9) },
178 { "f10", (RISCV_FIRST_FP_REGNUM + 10) },
179 { "f11", (RISCV_FIRST_FP_REGNUM + 11) },
180 { "f12", (RISCV_FIRST_FP_REGNUM + 12) },
181 { "f13", (RISCV_FIRST_FP_REGNUM + 13) },
182 { "f14", (RISCV_FIRST_FP_REGNUM + 14) },
183 { "f15", (RISCV_FIRST_FP_REGNUM + 15) },
184 { "f16", (RISCV_FIRST_FP_REGNUM + 16) },
185 { "f17", (RISCV_FIRST_FP_REGNUM + 17) },
186 { "f18", (RISCV_FIRST_FP_REGNUM + 18) },
187 { "f19", (RISCV_FIRST_FP_REGNUM + 19) },
188 { "f20", (RISCV_FIRST_FP_REGNUM + 20) },
189 { "f21", (RISCV_FIRST_FP_REGNUM + 21) },
190 { "f22", (RISCV_FIRST_FP_REGNUM + 22) },
191 { "f23", (RISCV_FIRST_FP_REGNUM + 23) },
192 { "f24", (RISCV_FIRST_FP_REGNUM + 24) },
193 { "f25", (RISCV_FIRST_FP_REGNUM + 25) },
194 { "f26", (RISCV_FIRST_FP_REGNUM + 26) },
195 { "f27", (RISCV_FIRST_FP_REGNUM + 27) },
196 { "f28", (RISCV_FIRST_FP_REGNUM + 28) },
197 { "f29", (RISCV_FIRST_FP_REGNUM + 29) },
198 { "f30", (RISCV_FIRST_FP_REGNUM + 30) },
199 { "f31", (RISCV_FIRST_FP_REGNUM + 31) },
202 /* Controls whether we place compressed breakpoints or not. When in auto
203 mode GDB tries to determine if the target supports compressed
204 breakpoints, and uses them if it does. */
206 static enum auto_boolean use_compressed_breakpoints;
208 /* The show callback for 'show riscv use-compressed-breakpoints'. */
211 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
212 struct cmd_list_element *c,
215 fprintf_filtered (file,
216 _("Debugger's use of compressed breakpoints is set "
220 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
222 static struct cmd_list_element *setriscvcmdlist = NULL;
223 static struct cmd_list_element *showriscvcmdlist = NULL;
225 /* The show callback for the 'show riscv' prefix command. */
228 show_riscv_command (const char *args, int from_tty)
230 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
233 /* The set callback for the 'set riscv' prefix command. */
236 set_riscv_command (const char *args, int from_tty)
239 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
240 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
243 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
245 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
246 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
248 /* The show callback for the 'show debug riscv' prefix command. */
251 show_debug_riscv_command (const char *args, int from_tty)
253 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
256 /* The set callback for the 'set debug riscv' prefix command. */
259 set_debug_riscv_command (const char *args, int from_tty)
262 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
263 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
266 /* The show callback for all 'show debug riscv VARNAME' variables. */
269 show_riscv_debug_variable (struct ui_file *file, int from_tty,
270 struct cmd_list_element *c,
273 fprintf_filtered (file,
274 _("RiscV debug variable `%s' is set to: %s\n"),
278 /* When this is set to non-zero debugging information about breakpoint
279 kinds will be printed. */
281 static unsigned int riscv_debug_breakpoints = 0;
283 /* When this is set to non-zero debugging information about inferior calls
286 static unsigned int riscv_debug_infcall = 0;
288 /* When this is set to non-zero debugging information about stack unwinding
291 static unsigned int riscv_debug_unwinder = 0;
293 /* Read the MISA register from the target. The register will only be read
294 once, and the value read will be cached. If the register can't be read
295 from the target then a default value (0) will be returned. If the
296 pointer READ_P is not null, then the bool pointed to is updated to
297 indicate if the value returned was read from the target (true) or is the
301 riscv_read_misa_reg (bool *read_p)
305 if (target_has_registers)
307 struct frame_info *frame = get_current_frame ();
311 value = get_frame_register_unsigned (frame,
312 RISCV_CSR_MISA_REGNUM);
314 CATCH (ex, RETURN_MASK_ERROR)
316 /* Old cores might have MISA located at a different offset. */
317 value = get_frame_register_unsigned (frame,
318 RISCV_CSR_LEGACY_MISA_REGNUM);
326 /* Return true if FEATURE is available for the architecture GDBARCH. The
327 FEATURE should be one of the single character feature codes described in
328 the RiscV ISA manual, these are between 'A' and 'Z'. */
331 riscv_has_feature (struct gdbarch *gdbarch, char feature)
333 bool have_read_misa = false;
336 gdb_assert (feature >= 'A' && feature <= 'Z');
338 misa = riscv_read_misa_reg (&have_read_misa);
339 if (!have_read_misa || misa == 0)
340 misa = gdbarch_tdep (gdbarch)->core_features;
342 return (misa & (1 << (feature - 'A'))) != 0;
345 /* Return the width in bytes of the general purpose registers for GDBARCH.
346 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
350 riscv_isa_xlen (struct gdbarch *gdbarch)
352 switch (gdbarch_tdep (gdbarch)->abi.fields.base_len)
355 warning (_("unknown xlen size, assuming 4 bytes"));
366 /* Return the width in bytes of the floating point registers for GDBARCH.
367 If this architecture has no floating point registers, then return 0.
368 Possible values are 4, 8, or 16 for depending on which of single, double
369 or quad floating point support is available. */
372 riscv_isa_flen (struct gdbarch *gdbarch)
374 if (riscv_has_feature (gdbarch, 'Q'))
376 else if (riscv_has_feature (gdbarch, 'D'))
378 else if (riscv_has_feature (gdbarch, 'F'))
384 /* Return true if the target for GDBARCH has floating point hardware. */
387 riscv_has_fp_regs (struct gdbarch *gdbarch)
389 return (riscv_isa_flen (gdbarch) > 0);
392 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
395 riscv_has_fp_abi (struct gdbarch *gdbarch)
397 return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0);
400 /* Return true if REGNO is a floating pointer register. */
403 riscv_is_fp_regno_p (int regno)
405 return (regno >= RISCV_FIRST_FP_REGNUM
406 && regno <= RISCV_LAST_FP_REGNUM);
409 /* Implement the breakpoint_kind_from_pc gdbarch method. */
412 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
414 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
418 /* Read the opcode byte to determine the instruction length. */
419 read_code (*pcptr, buf, 1);
421 if (riscv_debug_breakpoints)
424 "Using %s for breakpoint at %s (instruction length %d)\n",
425 riscv_insn_length (buf[0]) == 2 ? "C.EBREAK" : "EBREAK",
426 paddress (gdbarch, *pcptr), riscv_insn_length (buf[0]));
427 if (riscv_insn_length (buf[0]) == 2)
432 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
438 /* Implement the sw_breakpoint_from_kind gdbarch method. */
440 static const gdb_byte *
441 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
443 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
444 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
454 gdb_assert_not_reached (_("unhandled breakpoint kind"));
458 /* Callback function for user_reg_add. */
460 static struct value *
461 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
463 const int *reg_p = (const int *) baton;
464 return value_of_register (*reg_p, frame);
467 /* Implement the register_name gdbarch method. */
470 riscv_register_name (struct gdbarch *gdbarch, int regnum)
472 /* Prefer to use the alias. */
473 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
475 gdb_assert (regnum < ARRAY_SIZE (riscv_gdb_reg_names));
476 return riscv_gdb_reg_names[regnum];
479 /* Check that there's no gap between the set of registers handled above,
480 and the set of registers handled next. */
481 gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM);
483 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
487 xsnprintf (buf, sizeof (buf), "csr%d",
488 regnum - RISCV_FIRST_CSR_REGNUM);
492 if (regnum == RISCV_PRIV_REGNUM)
498 /* Construct a type for 64-bit FP registers. */
501 riscv_fpreg_d_type (struct gdbarch *gdbarch)
503 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
505 if (tdep->riscv_fpreg_d_type == nullptr)
507 const struct builtin_type *bt = builtin_type (gdbarch);
509 /* The type we're building is this: */
511 union __gdb_builtin_type_fpreg_d
520 t = arch_composite_type (gdbarch,
521 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
522 append_composite_type_field (t, "float", bt->builtin_float);
523 append_composite_type_field (t, "double", bt->builtin_double);
525 TYPE_NAME (t) = "builtin_type_fpreg_d";
526 tdep->riscv_fpreg_d_type = t;
529 return tdep->riscv_fpreg_d_type;
532 /* Construct a type for 128-bit FP registers. */
535 riscv_fpreg_q_type (struct gdbarch *gdbarch)
537 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
539 if (tdep->riscv_fpreg_q_type == nullptr)
541 const struct builtin_type *bt = builtin_type (gdbarch);
543 /* The type we're building is this: */
545 union __gdb_builtin_type_fpreg_d
555 t = arch_composite_type (gdbarch,
556 "__gdb_builtin_type_fpreg_q", TYPE_CODE_UNION);
557 append_composite_type_field (t, "float", bt->builtin_float);
558 append_composite_type_field (t, "double", bt->builtin_double);
559 append_composite_type_field (t, "long double", bt->builtin_long_double);
561 TYPE_NAME (t) = "builtin_type_fpreg_q";
562 tdep->riscv_fpreg_q_type = t;
565 return tdep->riscv_fpreg_q_type;
568 /* Implement the register_type gdbarch method. */
571 riscv_register_type (struct gdbarch *gdbarch, int regnum)
575 if (regnum < RISCV_FIRST_FP_REGNUM)
577 if (regnum == gdbarch_pc_regnum (gdbarch)
578 || regnum == RISCV_RA_REGNUM)
579 return builtin_type (gdbarch)->builtin_func_ptr;
581 if (regnum == RISCV_FP_REGNUM
582 || regnum == RISCV_SP_REGNUM
583 || regnum == RISCV_GP_REGNUM
584 || regnum == RISCV_TP_REGNUM)
585 return builtin_type (gdbarch)->builtin_data_ptr;
587 /* Remaining GPRs vary in size based on the current ISA. */
588 regsize = riscv_isa_xlen (gdbarch);
592 return builtin_type (gdbarch)->builtin_uint32;
594 return builtin_type (gdbarch)->builtin_uint64;
596 return builtin_type (gdbarch)->builtin_uint128;
598 internal_error (__FILE__, __LINE__,
599 _("unknown isa regsize %i"), regsize);
602 else if (regnum <= RISCV_LAST_FP_REGNUM)
604 regsize = riscv_isa_xlen (gdbarch);
608 return builtin_type (gdbarch)->builtin_float;
610 return riscv_fpreg_d_type (gdbarch);
612 return riscv_fpreg_q_type (gdbarch);
614 internal_error (__FILE__, __LINE__,
615 _("unknown isa regsize %i"), regsize);
618 else if (regnum == RISCV_PRIV_REGNUM)
619 return builtin_type (gdbarch)->builtin_int8;
622 if (regnum == RISCV_CSR_FFLAGS_REGNUM
623 || regnum == RISCV_CSR_FRM_REGNUM
624 || regnum == RISCV_CSR_FCSR_REGNUM)
625 return builtin_type (gdbarch)->builtin_int32;
627 regsize = riscv_isa_xlen (gdbarch);
631 return builtin_type (gdbarch)->builtin_int32;
633 return builtin_type (gdbarch)->builtin_int64;
635 return builtin_type (gdbarch)->builtin_int128;
637 internal_error (__FILE__, __LINE__,
638 _("unknown isa regsize %i"), regsize);
643 /* Helper for riscv_print_registers_info, prints info for a single register
647 riscv_print_one_register_info (struct gdbarch *gdbarch,
648 struct ui_file *file,
649 struct frame_info *frame,
652 const char *name = gdbarch_register_name (gdbarch, regnum);
653 struct value *val = value_of_register (regnum, frame);
654 struct type *regtype = value_type (val);
655 int print_raw_format;
656 enum tab_stops { value_column_1 = 15 };
658 fputs_filtered (name, file);
659 print_spaces_filtered (value_column_1 - strlen (name), file);
661 print_raw_format = (value_entirely_available (val)
662 && !value_optimized_out (val));
664 if (TYPE_CODE (regtype) == TYPE_CODE_FLT
665 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
666 && TYPE_NFIELDS (regtype) == 2
667 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
668 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
669 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
670 && TYPE_NFIELDS (regtype) == 3
671 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
672 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
673 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
675 struct value_print_options opts;
676 const gdb_byte *valaddr = value_contents_for_printing (val);
677 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
679 get_user_print_options (&opts);
683 value_embedded_offset (val), 0,
684 file, 0, val, &opts, current_language);
686 if (print_raw_format)
688 fprintf_filtered (file, "\t(raw ");
689 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
691 fprintf_filtered (file, ")");
696 struct value_print_options opts;
698 /* Print the register in hex. */
699 get_formatted_print_options (&opts, 'x');
702 value_embedded_offset (val), 0,
703 file, 0, val, &opts, current_language);
705 if (print_raw_format)
707 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
710 int size = register_size (gdbarch, regnum);
713 d = value_as_long (val);
715 fprintf_filtered (file,
716 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
717 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
718 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
719 (int) ((d >> (xlen - 1)) & 0x1),
720 (int) ((d >> 24) & 0x1f),
721 (int) ((d >> 19) & 0x1),
722 (int) ((d >> 18) & 0x1),
723 (int) ((d >> 17) & 0x1),
724 (int) ((d >> 15) & 0x3),
725 (int) ((d >> 13) & 0x3),
726 (int) ((d >> 11) & 0x3),
727 (int) ((d >> 9) & 0x3),
728 (int) ((d >> 8) & 0x1),
729 (int) ((d >> 7) & 0x1),
730 (int) ((d >> 6) & 0x1),
731 (int) ((d >> 5) & 0x1),
732 (int) ((d >> 4) & 0x1),
733 (int) ((d >> 3) & 0x1),
734 (int) ((d >> 2) & 0x1),
735 (int) ((d >> 1) & 0x1),
736 (int) ((d >> 0) & 0x1));
738 else if (regnum == RISCV_CSR_MISA_REGNUM)
744 d = value_as_long (val);
748 for (; base > 0; base--)
750 fprintf_filtered (file, "\tRV%d", xlen);
752 for (i = 0; i < 26; i++)
755 fprintf_filtered (file, "%c", 'A' + i);
758 else if (regnum == RISCV_CSR_FCSR_REGNUM
759 || regnum == RISCV_CSR_FFLAGS_REGNUM
760 || regnum == RISCV_CSR_FRM_REGNUM)
764 d = value_as_long (val);
766 fprintf_filtered (file, "\t");
767 if (regnum != RISCV_CSR_FRM_REGNUM)
768 fprintf_filtered (file,
769 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
770 (int) ((d >> 5) & 0x7),
771 (int) ((d >> 4) & 0x1),
772 (int) ((d >> 3) & 0x1),
773 (int) ((d >> 2) & 0x1),
774 (int) ((d >> 1) & 0x1),
775 (int) ((d >> 0) & 0x1));
777 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
779 static const char * const sfrm[] =
781 "RNE (round to nearest; ties to even)",
782 "RTZ (Round towards zero)",
783 "RDN (Round down towards -INF)",
784 "RUP (Round up towards +INF)",
785 "RMM (Round to nearest; ties to max magnitude)",
788 "dynamic rounding mode",
790 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
791 ? (d >> 5) : d) & 0x3;
793 fprintf_filtered (file, "%sFRM:%i [%s]",
794 (regnum == RISCV_CSR_FCSR_REGNUM
799 else if (regnum == RISCV_PRIV_REGNUM)
804 d = value_as_long (val);
809 static const char * const sprv[] =
816 fprintf_filtered (file, "\tprv:%d [%s]",
820 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
824 /* If not a vector register, print it also according to its
826 if (TYPE_VECTOR (regtype) == 0)
828 get_user_print_options (&opts);
830 fprintf_filtered (file, "\t");
832 value_embedded_offset (val), 0,
833 file, 0, val, &opts, current_language);
838 fprintf_filtered (file, "\n");
841 /* Return true if REGNUM is a valid CSR register. The CSR register space
842 is sparsely populated, so not every number is a named CSR. */
845 riscv_is_regnum_a_named_csr (int regnum)
847 gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
848 && regnum <= RISCV_LAST_CSR_REGNUM);
852 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
853 #include "opcode/riscv-opc.h"
862 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
866 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
867 struct reggroup *reggroup)
869 /* Used by 'info registers' and 'info registers <groupname>'. */
871 if (gdbarch_register_name (gdbarch, regnum) == NULL
872 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
875 if (reggroup == all_reggroup)
877 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
879 if (riscv_is_regnum_a_named_csr (regnum))
883 else if (reggroup == float_reggroup)
884 return (riscv_is_fp_regno_p (regnum)
885 || regnum == RISCV_CSR_FCSR_REGNUM
886 || regnum == RISCV_CSR_FFLAGS_REGNUM
887 || regnum == RISCV_CSR_FRM_REGNUM);
888 else if (reggroup == general_reggroup)
889 return regnum < RISCV_FIRST_FP_REGNUM;
890 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
892 if (riscv_has_fp_regs (gdbarch))
893 return regnum <= RISCV_LAST_FP_REGNUM;
895 return regnum < RISCV_FIRST_FP_REGNUM;
897 else if (reggroup == system_reggroup)
899 if (regnum == RISCV_PRIV_REGNUM)
901 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
903 if (riscv_is_regnum_a_named_csr (regnum))
907 else if (reggroup == vector_reggroup)
913 /* Implement the print_registers_info gdbarch method. This is used by
914 'info registers' and 'info all-registers'. */
917 riscv_print_registers_info (struct gdbarch *gdbarch,
918 struct ui_file *file,
919 struct frame_info *frame,
920 int regnum, int print_all)
924 /* Print one specified register. */
925 gdb_assert (regnum <= RISCV_LAST_REGNUM);
926 if (gdbarch_register_name (gdbarch, regnum) == NULL
927 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
928 error (_("Not a valid register for the current processor type"));
929 riscv_print_one_register_info (gdbarch, file, frame, regnum);
933 struct reggroup *reggroup;
936 reggroup = all_reggroup;
938 reggroup = general_reggroup;
940 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
942 /* Zero never changes, so might as well hide by default. */
943 if (regnum == RISCV_ZERO_REGNUM && !print_all)
946 /* Registers with no name are not valid on this ISA. */
947 if (gdbarch_register_name (gdbarch, regnum) == NULL
948 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
951 /* Is the register in the group we're interested in? */
952 if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup))
955 riscv_print_one_register_info (gdbarch, file, frame, regnum);
960 /* Class that handles one decoded RiscV instruction. */
966 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
969 /* Unknown value is used at initialisation time. */
972 /* These instructions are all the ones we are interested in during the
982 /* These are needed for software breakopint support. */
991 /* These are needed for stepping over atomic sequences. */
995 /* Other instructions are not interesting during the prologue scan, and
1010 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1012 /* Get the length of the instruction in bytes. */
1014 { return m_length; }
1016 /* Get the opcode for this instruction. */
1017 enum opcode opcode () const
1018 { return m_opcode; }
1020 /* Get destination register field for this instruction. This is only
1021 valid if the OPCODE implies there is such a field for this
1026 /* Get the RS1 register field for this instruction. This is only valid
1027 if the OPCODE implies there is such a field for this instruction. */
1031 /* Get the RS2 register field for this instruction. This is only valid
1032 if the OPCODE implies there is such a field for this instruction. */
1036 /* Get the immediate for this instruction in signed form. This is only
1037 valid if the OPCODE implies there is such a field for this
1039 int imm_signed () const
1044 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1045 int decode_register_index (unsigned long opcode, int offset)
1047 return (opcode >> offset) & 0x1F;
1050 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1051 int decode_register_index_short (unsigned long opcode, int offset)
1053 return ((opcode >> offset) & 0x7) + 8;
1056 /* Helper for DECODE, decode 32-bit R-type instruction. */
1057 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1060 m_rd = decode_register_index (ival, OP_SH_RD);
1061 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1062 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1065 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1066 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1069 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1070 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1073 /* Helper for DECODE, decode 32-bit I-type instruction. */
1074 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1077 m_rd = decode_register_index (ival, OP_SH_RD);
1078 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1079 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1082 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1083 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1086 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1087 m_imm.s = EXTRACT_RVC_IMM (ival);
1090 /* Helper for DECODE, decode 32-bit S-type instruction. */
1091 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1094 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1095 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1096 m_imm.s = EXTRACT_STYPE_IMM (ival);
1099 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1100 encoding is different for each CS format instruction, so extracting
1101 the immediate is left up to the caller, who should pass the extracted
1102 immediate value through in IMM. */
1103 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1107 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1108 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1111 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1112 encoding is different for each CSS format instruction, so extracting
1113 the immediate is left up to the caller, who should pass the extracted
1114 immediate value through in IMM. */
1115 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1119 m_rs1 = RISCV_SP_REGNUM;
1120 /* Not a compressed register number in this case. */
1121 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1124 /* Helper for DECODE, decode 32-bit U-type instruction. */
1125 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1128 m_rd = decode_register_index (ival, OP_SH_RD);
1129 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1132 /* Helper for DECODE, decode 32-bit J-type instruction. */
1133 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1136 m_rd = decode_register_index (ival, OP_SH_RD);
1137 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1140 /* Helper for DECODE, decode 32-bit J-type instruction. */
1141 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1144 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1147 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1150 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1151 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1152 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1155 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1158 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1159 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1162 /* Fetch instruction from target memory at ADDR, return the content of
1163 the instruction, and update LEN with the instruction length. */
1164 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1165 CORE_ADDR addr, int *len);
1167 /* The length of the instruction in bytes. Should be 2 or 4. */
1170 /* The instruction opcode. */
1171 enum opcode m_opcode;
1173 /* The three possible registers an instruction might reference. Not
1174 every instruction fills in all of these registers. Which fields are
1175 valid depends on the opcode. The naming of these fields matches the
1176 naming in the riscv isa manual. */
1181 /* Possible instruction immediate. This is only valid if the instruction
1182 format contains an immediate, not all instruction, whether this is
1183 valid depends on the opcode. Despite only having one format for now
1184 the immediate is packed into a union, later instructions might require
1185 an unsigned formatted immediate, having the union in place now will
1186 reduce the need for code churn later. */
1187 union riscv_insn_immediate
1189 riscv_insn_immediate ()
1199 /* Fetch instruction from target memory at ADDR, return the content of the
1200 instruction, and update LEN with the instruction length. */
1203 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1204 CORE_ADDR addr, int *len)
1206 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1208 int instlen, status;
1210 /* All insns are at least 16 bits. */
1211 status = target_read_memory (addr, buf, 2);
1213 memory_error (TARGET_XFER_E_IO, addr);
1215 /* If we need more, grab it now. */
1216 instlen = riscv_insn_length (buf[0]);
1217 gdb_assert (instlen <= sizeof (buf));
1222 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1224 memory_error (TARGET_XFER_E_IO, addr + 2);
1227 return extract_unsigned_integer (buf, instlen, byte_order);
1230 /* Fetch from target memory an instruction at PC and decode it. */
1233 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1237 /* Fetch the instruction, and the instructions length. */
1238 ival = fetch_instruction (gdbarch, pc, &m_length);
1242 if (is_add_insn (ival))
1243 decode_r_type_insn (ADD, ival);
1244 else if (is_addw_insn (ival))
1245 decode_r_type_insn (ADDW, ival);
1246 else if (is_addi_insn (ival))
1247 decode_i_type_insn (ADDI, ival);
1248 else if (is_addiw_insn (ival))
1249 decode_i_type_insn (ADDIW, ival);
1250 else if (is_auipc_insn (ival))
1251 decode_u_type_insn (AUIPC, ival);
1252 else if (is_lui_insn (ival))
1253 decode_u_type_insn (LUI, ival);
1254 else if (is_sd_insn (ival))
1255 decode_s_type_insn (SD, ival);
1256 else if (is_sw_insn (ival))
1257 decode_s_type_insn (SW, ival);
1258 else if (is_jal_insn (ival))
1259 decode_j_type_insn (JAL, ival);
1260 else if (is_jalr_insn (ival))
1261 decode_i_type_insn (JALR, ival);
1262 else if (is_beq_insn (ival))
1263 decode_b_type_insn (BEQ, ival);
1264 else if (is_bne_insn (ival))
1265 decode_b_type_insn (BNE, ival);
1266 else if (is_blt_insn (ival))
1267 decode_b_type_insn (BLT, ival);
1268 else if (is_bge_insn (ival))
1269 decode_b_type_insn (BGE, ival);
1270 else if (is_bltu_insn (ival))
1271 decode_b_type_insn (BLTU, ival);
1272 else if (is_bgeu_insn (ival))
1273 decode_b_type_insn (BGEU, ival);
1274 else if (is_lr_w_insn (ival))
1275 decode_r_type_insn (LR, ival);
1276 else if (is_lr_d_insn (ival))
1277 decode_r_type_insn (LR, ival);
1278 else if (is_sc_w_insn (ival))
1279 decode_r_type_insn (SC, ival);
1280 else if (is_sc_d_insn (ival))
1281 decode_r_type_insn (SC, ival);
1283 /* None of the other fields are valid in this case. */
1286 else if (m_length == 2)
1288 int xlen = riscv_isa_xlen (gdbarch);
1290 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1291 C_JALR. So must try to match C_JALR first as it has more bits in
1293 if (is_c_jalr_insn (ival))
1294 decode_cr_type_insn (JALR, ival);
1295 else if (is_c_add_insn (ival))
1296 decode_cr_type_insn (ADD, ival);
1297 /* C_ADDW is RV64 and RV128 only. */
1298 else if (xlen != 4 && is_c_addw_insn (ival))
1299 decode_cr_type_insn (ADDW, ival);
1300 else if (is_c_addi_insn (ival))
1301 decode_ci_type_insn (ADDI, ival);
1302 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1303 only and C_JAL is RV32 only. */
1304 else if (xlen != 4 && is_c_addiw_insn (ival))
1305 decode_ci_type_insn (ADDIW, ival);
1306 else if (xlen == 4 && is_c_jal_insn (ival))
1307 decode_cj_type_insn (JAL, ival);
1308 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1309 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1311 else if (is_c_addi16sp_insn (ival))
1314 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1315 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1317 else if (is_c_addi4spn_insn (ival))
1320 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1321 m_rs1 = RISCV_SP_REGNUM;
1322 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1324 else if (is_c_lui_insn (ival))
1327 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1328 m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
1330 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1331 and C_FSW is RV32 only. */
1332 else if (xlen != 4 && is_c_sd_insn (ival))
1333 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
1334 else if (is_c_sw_insn (ival))
1335 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1336 else if (is_c_swsp_insn (ival))
1337 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1338 else if (xlen != 4 && is_c_sdsp_insn (ival))
1339 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
1340 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1341 So must try to match C_JR first as it ahs more bits in mask. */
1342 else if (is_c_jr_insn (ival))
1343 decode_cr_type_insn (JALR, ival);
1344 else if (is_c_j_insn (ival))
1345 decode_cj_type_insn (JAL, ival);
1346 else if (is_c_beqz_insn (ival))
1347 decode_cb_type_insn (BEQ, ival);
1348 else if (is_c_bnez_insn (ival))
1349 decode_cb_type_insn (BNE, ival);
1351 /* None of the other fields of INSN are valid in this case. */
1355 internal_error (__FILE__, __LINE__,
1356 _("unable to decode %d byte instructions in "
1357 "prologue at %s"), m_length,
1358 core_addr_to_string (pc));
1361 /* The prologue scanner. This is currently only used for skipping the
1362 prologue of a function when the DWARF information is not sufficient.
1363 However, it is written with filling of the frame cache in mind, which
1364 is why different groups of stack setup instructions are split apart
1365 during the core of the inner loop. In the future, the intention is to
1366 extend this function to fully support building up a frame cache that
1367 can unwind register values when there is no DWARF information. */
1370 riscv_scan_prologue (struct gdbarch *gdbarch,
1371 CORE_ADDR start_pc, CORE_ADDR end_pc,
1372 struct riscv_unwind_cache *cache)
1374 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1375 CORE_ADDR end_prologue_addr = 0;
1377 /* Find an upper limit on the function prologue using the debug
1378 information. If the debug information could not be used to provide
1379 that bound, then use an arbitrary large number as the upper bound. */
1380 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1381 if (after_prologue_pc == 0)
1382 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1383 if (after_prologue_pc < end_pc)
1384 end_pc = after_prologue_pc;
1386 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1387 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1388 regs[regno] = pv_register (regno, 0);
1389 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1391 if (riscv_debug_unwinder)
1394 "Prologue scan for function starting at %s (limit %s)\n",
1395 core_addr_to_string (start_pc),
1396 core_addr_to_string (end_pc));
1398 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1400 struct riscv_insn insn;
1402 /* Decode the current instruction, and decide where the next
1403 instruction lives based on the size of this instruction. */
1404 insn.decode (gdbarch, cur_pc);
1405 gdb_assert (insn.length () > 0);
1406 next_pc = cur_pc + insn.length ();
1408 /* Look for common stack adjustment insns. */
1409 if ((insn.opcode () == riscv_insn::ADDI
1410 || insn.opcode () == riscv_insn::ADDIW)
1411 && insn.rd () == RISCV_SP_REGNUM
1412 && insn.rs1 () == RISCV_SP_REGNUM)
1414 /* Handle: addi sp, sp, -i
1415 or: addiw sp, sp, -i */
1416 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1417 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1419 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1421 else if ((insn.opcode () == riscv_insn::SW
1422 || insn.opcode () == riscv_insn::SD)
1423 && (insn.rs1 () == RISCV_SP_REGNUM
1424 || insn.rs1 () == RISCV_FP_REGNUM))
1426 /* Handle: sw reg, offset(sp)
1427 or: sd reg, offset(sp)
1428 or: sw reg, offset(s0)
1429 or: sd reg, offset(s0) */
1430 /* Instruction storing a register onto the stack. */
1431 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1432 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1433 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1434 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1437 else if (insn.opcode () == riscv_insn::ADDI
1438 && insn.rd () == RISCV_FP_REGNUM
1439 && insn.rs1 () == RISCV_SP_REGNUM)
1441 /* Handle: addi s0, sp, size */
1442 /* Instructions setting up the frame pointer. */
1443 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1444 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1446 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1448 else if ((insn.opcode () == riscv_insn::ADD
1449 || insn.opcode () == riscv_insn::ADDW)
1450 && insn.rd () == RISCV_FP_REGNUM
1451 && insn.rs1 () == RISCV_SP_REGNUM
1452 && insn.rs2 () == RISCV_ZERO_REGNUM)
1454 /* Handle: add s0, sp, 0
1455 or: addw s0, sp, 0 */
1456 /* Instructions setting up the frame pointer. */
1457 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1458 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1459 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1461 else if ((insn.opcode () == riscv_insn::ADDI
1462 && insn.rd () == RISCV_ZERO_REGNUM
1463 && insn.rs1 () == RISCV_ZERO_REGNUM
1464 && insn.imm_signed () == 0))
1466 /* Handle: add x0, x0, 0 (NOP) */
1468 else if (insn.opcode () == riscv_insn::AUIPC)
1470 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1471 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1473 else if (insn.opcode () == riscv_insn::LUI)
1475 /* Handle: lui REG, n
1476 Where REG is not gp register. */
1477 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1478 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1480 else if (insn.opcode () == riscv_insn::ADDI)
1482 /* Handle: addi REG1, REG2, IMM */
1483 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1484 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1486 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1488 else if (insn.opcode () == riscv_insn::ADD)
1490 /* Handle: addi REG1, REG2, IMM */
1491 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1492 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1493 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1494 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1498 end_prologue_addr = cur_pc;
1503 if (end_prologue_addr == 0)
1504 end_prologue_addr = cur_pc;
1506 if (riscv_debug_unwinder)
1507 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1508 core_addr_to_string (end_prologue_addr));
1512 /* Figure out if it is a frame pointer or just a stack pointer. Also
1513 the offset held in the pv_t is from the original register value to
1514 the current value, which for a grows down stack means a negative
1515 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1516 from the current value to the original value. */
1517 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1519 cache->frame_base_reg = RISCV_FP_REGNUM;
1520 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1524 cache->frame_base_reg = RISCV_SP_REGNUM;
1525 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1528 /* Assign offset from old SP to all saved registers. As we don't
1529 have the previous value for the frame base register at this
1530 point, we store the offset as the address in the trad_frame, and
1531 then convert this to an actual address later. */
1532 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1535 if (stack.find_reg (gdbarch, i, &offset))
1537 if (riscv_debug_unwinder)
1538 fprintf_unfiltered (gdb_stdlog,
1539 "Register $%s at stack offset %ld\n",
1540 gdbarch_register_name (gdbarch, i),
1542 trad_frame_set_addr (cache->regs, i, offset);
1547 return end_prologue_addr;
1550 /* Implement the riscv_skip_prologue gdbarch method. */
1553 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1555 CORE_ADDR func_addr;
1557 /* See if we can determine the end of the prologue via the symbol
1558 table. If so, then return either PC, or the PC after the
1559 prologue, whichever is greater. */
1560 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1562 CORE_ADDR post_prologue_pc
1563 = skip_prologue_using_sal (gdbarch, func_addr);
1565 if (post_prologue_pc != 0)
1566 return std::max (pc, post_prologue_pc);
1569 /* Can't determine prologue from the symbol table, need to examine
1570 instructions. Pass -1 for the end address to indicate the prologue
1571 scanner can scan as far as it needs to find the end of the prologue. */
1572 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1575 /* Implement the gdbarch push dummy code callback. */
1578 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1579 CORE_ADDR funaddr, struct value **args, int nargs,
1580 struct type *value_type, CORE_ADDR *real_pc,
1581 CORE_ADDR *bp_addr, struct regcache *regcache)
1583 /* Allocate space for a breakpoint, and keep the stack correctly
1591 /* Compute the alignment of the type T. Used while setting up the
1592 arguments for a dummy call. */
1595 riscv_type_alignment (struct type *t)
1597 t = check_typedef (t);
1598 switch (TYPE_CODE (t))
1601 error (_("Could not compute alignment of type"));
1603 case TYPE_CODE_RVALUE_REF:
1605 case TYPE_CODE_ENUM:
1609 case TYPE_CODE_CHAR:
1610 case TYPE_CODE_BOOL:
1611 return TYPE_LENGTH (t);
1613 case TYPE_CODE_ARRAY:
1614 case TYPE_CODE_COMPLEX:
1615 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1617 case TYPE_CODE_STRUCT:
1618 case TYPE_CODE_UNION:
1623 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1625 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1627 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1637 /* Holds information about a single argument either being passed to an
1638 inferior function, or returned from an inferior function. This includes
1639 information about the size, type, etc of the argument, and also
1640 information about how the argument will be passed (or returned). */
1642 struct riscv_arg_info
1644 /* Contents of the argument. */
1645 const gdb_byte *contents;
1647 /* Length of argument. */
1650 /* Alignment required for an argument of this type. */
1653 /* The type for this argument. */
1656 /* Each argument can have either 1 or 2 locations assigned to it. Each
1657 location describes where part of the argument will be placed. The
1658 second location is valid based on the LOC_TYPE and C_LENGTH fields
1659 of the first location (which is always valid). */
1662 /* What type of location this is. */
1665 /* Argument passed in a register. */
1668 /* Argument passed as an on stack argument. */
1671 /* Argument passed by reference. The second location is always
1672 valid for a BY_REF argument, and describes where the address
1673 of the BY_REF argument should be placed. */
1677 /* Information that depends on the location type. */
1680 /* Which register number to use. */
1683 /* The offset into the stack region. */
1687 /* The length of contents covered by this location. If this is less
1688 than the total length of the argument, then the second location
1689 will be valid, and will describe where the rest of the argument
1693 /* The offset within CONTENTS for this part of the argument. Will
1694 always be 0 for the first part. For the second part of the
1695 argument, this might be the C_LENGTH value of the first part,
1696 however, if we are passing a structure in two registers, and there's
1697 is padding between the first and second field, then this offset
1698 might be greater than the length of the first argument part. When
1699 the second argument location is not holding part of the argument
1700 value, but is instead holding the address of a reference argument,
1701 then this offset will be set to 0. */
1706 /* Information about a set of registers being used for passing arguments as
1707 part of a function call. The register set must be numerically
1708 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1709 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1711 struct riscv_arg_reg
1713 riscv_arg_reg (int first, int last)
1714 : next_regnum (first),
1720 /* The GDB register number to use in this set. */
1723 /* The last GDB register number to use in this set. */
1727 /* Arguments can be passed as on stack arguments, or by reference. The
1728 on stack arguments must be in a continuous region starting from $sp,
1729 while the by reference arguments can be anywhere, but we'll put them
1730 on the stack after (at higher address) the on stack arguments.
1732 This might not be the right approach to take. The ABI is clear that
1733 an argument passed by reference can be modified by the callee, which
1734 us placing the argument (temporarily) onto the stack will not achieve
1735 (changes will be lost). There's also the possibility that very large
1736 arguments could overflow the stack.
1738 This struct is used to track offset into these two areas for where
1739 arguments are to be placed. */
1740 struct riscv_memory_offsets
1742 riscv_memory_offsets ()
1749 /* Offset into on stack argument area. */
1752 /* Offset into the pass by reference area. */
1756 /* Holds information about where arguments to a call will be placed. This
1757 is updated as arguments are added onto the call, and can be used to
1758 figure out where the next argument should be placed. */
1760 struct riscv_call_info
1762 riscv_call_info (struct gdbarch *gdbarch)
1763 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1764 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1766 xlen = riscv_isa_xlen (gdbarch);
1767 flen = riscv_isa_flen (gdbarch);
1769 /* Disable use of floating point registers if needed. */
1770 if (!riscv_has_fp_abi (gdbarch))
1771 float_regs.next_regnum = float_regs.last_regnum + 1;
1774 /* Track the memory areas used for holding in-memory arguments to a
1776 struct riscv_memory_offsets memory;
1778 /* Holds information about the next integer register to use for passing
1780 struct riscv_arg_reg int_regs;
1782 /* Holds information about the next floating point register to use for
1783 passing an argument. */
1784 struct riscv_arg_reg float_regs;
1786 /* The XLEN and FLEN are copied in to this structure for convenience, and
1787 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1792 /* Return the number of registers available for use as parameters in the
1793 register set REG. Returned value can be 0 or more. */
1796 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1798 if (reg->next_regnum > reg->last_regnum)
1801 return (reg->last_regnum - reg->next_regnum + 1);
1804 /* If there is at least one register available in the register set REG then
1805 the next register from REG is assigned to LOC and the length field of
1806 LOC is updated to LENGTH. The register set REG is updated to indicate
1807 that the assigned register is no longer available and the function
1810 If there are no registers available in REG then the function returns
1811 false, and LOC and REG are unchanged. */
1814 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1815 struct riscv_arg_reg *reg,
1816 int length, int offset)
1818 if (reg->next_regnum <= reg->last_regnum)
1820 loc->loc_type = riscv_arg_info::location::in_reg;
1821 loc->loc_data.regno = reg->next_regnum;
1823 loc->c_length = length;
1824 loc->c_offset = offset;
1831 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1832 record that an area of stack has been used to hold the parameter
1835 The length field of LOC is updated to LENGTH, the length of the
1836 parameter being stored, and ALIGN is the alignment required by the
1837 parameter, which will affect how memory is allocated out of MEMORY. */
1840 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1841 struct riscv_memory_offsets *memory,
1842 int length, int align)
1844 loc->loc_type = riscv_arg_info::location::on_stack;
1846 = align_up (memory->arg_offset, align);
1847 loc->loc_data.offset = memory->arg_offset;
1848 memory->arg_offset += length;
1849 loc->c_length = length;
1851 /* Offset is always 0, either we're the first location part, in which
1852 case we're reading content from the start of the argument, or we're
1853 passing the address of a reference argument, so 0. */
1857 /* Update AINFO, which describes an argument that should be passed or
1858 returned using the integer ABI. The argloc fields within AINFO are
1859 updated to describe the location in which the argument will be passed to
1860 a function, or returned from a function.
1862 The CINFO structure contains the ongoing call information, the holds
1863 information such as which argument registers are remaining to be
1864 assigned to parameter, and how much memory has been used by parameters
1867 By examining the state of CINFO a suitable location can be selected,
1868 and assigned to AINFO. */
1871 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1872 struct riscv_call_info *cinfo)
1874 if (ainfo->length > (2 * cinfo->xlen))
1876 /* Argument is going to be passed by reference. */
1877 ainfo->argloc[0].loc_type
1878 = riscv_arg_info::location::by_ref;
1879 cinfo->memory.ref_offset
1880 = align_up (cinfo->memory.ref_offset, ainfo->align);
1881 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1882 cinfo->memory.ref_offset += ainfo->length;
1883 ainfo->argloc[0].c_length = ainfo->length;
1885 /* The second location for this argument is given over to holding the
1886 address of the by-reference data. Pass 0 for the offset as this
1887 is not part of the actual argument value. */
1888 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1891 riscv_assign_stack_location (&ainfo->argloc[1],
1892 &cinfo->memory, cinfo->xlen,
1897 int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length;
1899 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1900 &cinfo->int_regs, len, 0))
1901 riscv_assign_stack_location (&ainfo->argloc[0],
1902 &cinfo->memory, len, ainfo->align);
1904 if (len < ainfo->length)
1906 len = ainfo->length - len;
1907 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1908 &cinfo->int_regs, len,
1910 riscv_assign_stack_location (&ainfo->argloc[1],
1911 &cinfo->memory, len, cinfo->xlen);
1916 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1917 is being passed with the floating point ABI. */
1920 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1921 struct riscv_call_info *cinfo)
1923 if (ainfo->length > cinfo->flen)
1924 return riscv_call_arg_scalar_int (ainfo, cinfo);
1927 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1930 return riscv_call_arg_scalar_int (ainfo, cinfo);
1934 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1935 is a complex floating point argument, and is therefore handled
1936 differently to other argument types. */
1939 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1940 struct riscv_call_info *cinfo)
1942 if (ainfo->length <= (2 * cinfo->flen)
1943 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1946 int len = ainfo->length / 2;
1948 result = riscv_assign_reg_location (&ainfo->argloc[0],
1949 &cinfo->float_regs, len, len);
1950 gdb_assert (result);
1952 result = riscv_assign_reg_location (&ainfo->argloc[1],
1953 &cinfo->float_regs, len, len);
1954 gdb_assert (result);
1957 return riscv_call_arg_scalar_int (ainfo, cinfo);
1960 /* A structure used for holding information about a structure type within
1961 the inferior program. The RiscV ABI has special rules for handling some
1962 structures with a single field or with two fields. The counting of
1963 fields here is done after flattening out all nested structures. */
1965 class riscv_struct_info
1968 riscv_struct_info ()
1969 : m_number_of_fields (0),
1970 m_types { nullptr, nullptr }
1975 /* Analyse TYPE descending into nested structures, count the number of
1976 scalar fields and record the types of the first two fields found. */
1977 void analyse (struct type *type);
1979 /* The number of scalar fields found in the analysed type. This is
1980 currently only accurate if the value returned is 0, 1, or 2 as the
1981 analysis stops counting when the number of fields is 3. This is
1982 because the RiscV ABI only has special cases for 1 or 2 fields,
1983 anything else we just don't care about. */
1984 int number_of_fields () const
1985 { return m_number_of_fields; }
1987 /* Return the type for scalar field INDEX within the analysed type. Will
1988 return nullptr if there is no field at that index. Only INDEX values
1989 0 and 1 can be requested as the RiscV ABI only has special cases for
1990 structures with 1 or 2 fields. */
1991 struct type *field_type (int index) const
1993 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
1994 return m_types[index];
1998 /* The number of scalar fields found within the structure after recursing
1999 into nested structures. */
2000 int m_number_of_fields;
2002 /* The types of the first two scalar fields found within the structure
2003 after recursing into nested structures. */
2004 struct type *m_types[2];
2007 /* Analyse TYPE descending into nested structures, count the number of
2008 scalar fields and record the types of the first two fields found. */
2011 riscv_struct_info::analyse (struct type *type)
2013 unsigned int count = TYPE_NFIELDS (type);
2016 for (i = 0; i < count; ++i)
2018 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
2021 struct type *field_type = TYPE_FIELD_TYPE (type, i);
2022 field_type = check_typedef (field_type);
2024 switch (TYPE_CODE (field_type))
2026 case TYPE_CODE_STRUCT:
2027 analyse (field_type);
2031 /* RiscV only flattens out structures. Anything else does not
2032 need to be flattened, we just record the type, and when we
2033 look at the analysis results we'll realise this is not a
2034 structure we can special case, and pass the structure in
2036 if (m_number_of_fields < 2)
2037 m_types[m_number_of_fields] = field_type;
2038 m_number_of_fields++;
2042 /* RiscV only has special handling for structures with 1 or 2 scalar
2043 fields, any more than that and the structure is just passed in
2044 memory. We can safely drop out early when we find 3 or more
2047 if (m_number_of_fields > 2)
2052 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2053 is a structure. Small structures on RiscV have some special case
2054 handling in order that the structure might be passed in register.
2055 Larger structures are passed in memory. After assigning location
2056 information to AINFO, CINFO will have been updated. */
2059 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
2060 struct riscv_call_info *cinfo)
2062 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2064 struct riscv_struct_info sinfo;
2066 sinfo.analyse (ainfo->type);
2067 if (sinfo.number_of_fields () == 1
2068 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
2070 gdb_assert (TYPE_LENGTH (ainfo->type)
2071 == TYPE_LENGTH (sinfo.field_type (0)));
2072 return riscv_call_arg_complex_float (ainfo, cinfo);
2075 if (sinfo.number_of_fields () == 1
2076 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
2078 gdb_assert (TYPE_LENGTH (ainfo->type)
2079 == TYPE_LENGTH (sinfo.field_type (0)));
2080 return riscv_call_arg_scalar_float (ainfo, cinfo);
2083 if (sinfo.number_of_fields () == 2
2084 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2085 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2086 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2087 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
2088 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2090 int len0, len1, offset;
2092 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
2094 len0 = TYPE_LENGTH (sinfo.field_type (0));
2095 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2096 &cinfo->float_regs, len0, 0))
2097 error (_("failed during argument setup"));
2099 len1 = TYPE_LENGTH (sinfo.field_type (1));
2100 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2101 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2102 - TYPE_LENGTH (sinfo.field_type (0))));
2104 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2107 error (_("failed during argument setup"));
2111 if (sinfo.number_of_fields () == 2
2112 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2113 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2114 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2115 && is_integral_type (sinfo.field_type (1))
2116 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2118 int len0, len1, offset;
2120 gdb_assert (TYPE_LENGTH (ainfo->type)
2121 <= (cinfo->flen + cinfo->xlen));
2123 len0 = TYPE_LENGTH (sinfo.field_type (0));
2124 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2125 &cinfo->float_regs, len0, 0))
2126 error (_("failed during argument setup"));
2128 len1 = TYPE_LENGTH (sinfo.field_type (1));
2129 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2130 gdb_assert (len1 <= cinfo->xlen);
2131 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2132 &cinfo->int_regs, len1, offset))
2133 error (_("failed during argument setup"));
2137 if (sinfo.number_of_fields () == 2
2138 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2139 && (is_integral_type (sinfo.field_type (0))
2140 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2141 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2142 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2144 int len0, len1, offset;
2146 gdb_assert (TYPE_LENGTH (ainfo->type)
2147 <= (cinfo->flen + cinfo->xlen));
2149 len0 = TYPE_LENGTH (sinfo.field_type (0));
2150 len1 = TYPE_LENGTH (sinfo.field_type (1));
2151 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2153 gdb_assert (len0 <= cinfo->xlen);
2154 gdb_assert (len1 <= cinfo->flen);
2156 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2157 &cinfo->int_regs, len0, 0))
2158 error (_("failed during argument setup"));
2160 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2163 error (_("failed during argument setup"));
2169 /* Non of the structure flattening cases apply, so we just pass using
2171 ainfo->length = align_up (ainfo->length, cinfo->xlen);
2172 riscv_call_arg_scalar_int (ainfo, cinfo);
2175 /* Assign a location to call (or return) argument AINFO, the location is
2176 selected from CINFO which holds information about what call argument
2177 locations are available for use next. The TYPE is the type of the
2178 argument being passed, this information is recorded into AINFO (along
2179 with some additional information derived from the type).
2181 After assigning a location to AINFO, CINFO will have been updated. */
2184 riscv_arg_location (struct gdbarch *gdbarch,
2185 struct riscv_arg_info *ainfo,
2186 struct riscv_call_info *cinfo,
2190 ainfo->length = TYPE_LENGTH (ainfo->type);
2191 ainfo->align = riscv_type_alignment (ainfo->type);
2192 ainfo->contents = nullptr;
2194 switch (TYPE_CODE (ainfo->type))
2197 case TYPE_CODE_BOOL:
2198 case TYPE_CODE_CHAR:
2199 case TYPE_CODE_RANGE:
2200 case TYPE_CODE_ENUM:
2202 if (ainfo->length <= cinfo->xlen)
2204 ainfo->type = builtin_type (gdbarch)->builtin_long;
2205 ainfo->length = cinfo->xlen;
2207 else if (ainfo->length <= (2 * cinfo->xlen))
2209 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2210 ainfo->length = 2 * cinfo->xlen;
2213 /* Recalculate the alignment requirement. */
2214 ainfo->align = riscv_type_alignment (ainfo->type);
2215 riscv_call_arg_scalar_int (ainfo, cinfo);
2219 riscv_call_arg_scalar_float (ainfo, cinfo);
2222 case TYPE_CODE_COMPLEX:
2223 riscv_call_arg_complex_float (ainfo, cinfo);
2226 case TYPE_CODE_STRUCT:
2227 riscv_call_arg_struct (ainfo, cinfo);
2231 riscv_call_arg_scalar_int (ainfo, cinfo);
2236 /* Used for printing debug information about the call argument location in
2237 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2238 addresses for the location of pass-by-reference and
2239 arguments-on-the-stack memory areas. */
2242 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2243 struct riscv_arg_info *info,
2244 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2246 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2247 TYPE_SAFE_NAME (info->type), info->length, info->align);
2248 switch (info->argloc[0].loc_type)
2250 case riscv_arg_info::location::in_reg:
2252 (stream, ", register %s",
2253 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2254 if (info->argloc[0].c_length < info->length)
2256 switch (info->argloc[1].loc_type)
2258 case riscv_arg_info::location::in_reg:
2260 (stream, ", register %s",
2261 gdbarch_register_name (gdbarch,
2262 info->argloc[1].loc_data.regno));
2265 case riscv_arg_info::location::on_stack:
2266 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2267 info->argloc[1].loc_data.offset);
2270 case riscv_arg_info::location::by_ref:
2272 /* The second location should never be a reference, any
2273 argument being passed by reference just places its address
2274 in the first location and is done. */
2275 error (_("invalid argument location"));
2279 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2280 fprintf_unfiltered (stream, " (offset 0x%x)",
2281 info->argloc[1].c_offset);
2285 case riscv_arg_info::location::on_stack:
2286 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2287 info->argloc[0].loc_data.offset);
2290 case riscv_arg_info::location::by_ref:
2292 (stream, ", by reference, data at offset 0x%x (%s)",
2293 info->argloc[0].loc_data.offset,
2294 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2295 if (info->argloc[1].loc_type
2296 == riscv_arg_info::location::in_reg)
2298 (stream, ", address in register %s",
2299 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2302 gdb_assert (info->argloc[1].loc_type
2303 == riscv_arg_info::location::on_stack);
2305 (stream, ", address on stack at offset 0x%x (%s)",
2306 info->argloc[1].loc_data.offset,
2307 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2312 gdb_assert_not_reached (_("unknown argument location type"));
2316 /* Implement the push dummy call gdbarch callback. */
2319 riscv_push_dummy_call (struct gdbarch *gdbarch,
2320 struct value *function,
2321 struct regcache *regcache,
2324 struct value **args,
2327 CORE_ADDR struct_addr)
2330 CORE_ADDR sp_args, sp_refs;
2331 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2333 struct riscv_arg_info *arg_info =
2334 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2336 struct riscv_call_info call_info (gdbarch);
2340 /* We'll use register $a0 if we're returning a struct. */
2342 ++call_info.int_regs.next_regnum;
2344 for (i = 0; i < nargs; ++i)
2346 struct value *arg_value;
2347 struct type *arg_type;
2348 struct riscv_arg_info *info = &arg_info[i];
2350 arg_value = args[i];
2351 arg_type = check_typedef (value_type (arg_value));
2353 riscv_arg_location (gdbarch, info, &call_info, arg_type);
2355 if (info->type != arg_type)
2356 arg_value = value_cast (info->type, arg_value);
2357 info->contents = value_contents (arg_value);
2360 /* Adjust the stack pointer and align it. */
2361 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2362 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2364 if (riscv_debug_infcall > 0)
2366 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2367 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2368 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2369 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2370 call_info.xlen, call_info.flen);
2372 fprintf_unfiltered (gdb_stdlog,
2373 "[*] struct return pointer in register $A0\n");
2374 for (i = 0; i < nargs; ++i)
2376 struct riscv_arg_info *info = &arg_info [i];
2378 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2379 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2380 fprintf_unfiltered (gdb_stdlog, "\n");
2382 if (call_info.memory.arg_offset > 0
2383 || call_info.memory.ref_offset > 0)
2385 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2386 core_addr_to_string (osp));
2387 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2388 call_info.memory.arg_offset);
2389 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2390 call_info.memory.ref_offset);
2391 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2392 core_addr_to_string_nz (osp - sp));
2396 /* Now load the argument into registers, or onto the stack. */
2400 gdb_byte buf[sizeof (LONGEST)];
2402 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2403 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2406 for (i = 0; i < nargs; ++i)
2409 int second_arg_length = 0;
2410 const gdb_byte *second_arg_data;
2411 struct riscv_arg_info *info = &arg_info [i];
2413 gdb_assert (info->length > 0);
2415 switch (info->argloc[0].loc_type)
2417 case riscv_arg_info::location::in_reg:
2419 gdb_byte tmp [sizeof (ULONGEST)];
2421 gdb_assert (info->argloc[0].c_length <= info->length);
2422 /* FP values in FP registers must be NaN-boxed. */
2423 if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno)
2424 && info->argloc[0].c_length < call_info.flen)
2425 memset (tmp, -1, sizeof (tmp));
2427 memset (tmp, 0, sizeof (tmp));
2428 memcpy (tmp, info->contents, info->argloc[0].c_length);
2429 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2431 ((info->argloc[0].c_length < info->length)
2432 ? info->argloc[1].c_length : 0);
2433 second_arg_data = info->contents + info->argloc[1].c_offset;
2437 case riscv_arg_info::location::on_stack:
2438 dst = sp_args + info->argloc[0].loc_data.offset;
2439 write_memory (dst, info->contents, info->length);
2440 second_arg_length = 0;
2443 case riscv_arg_info::location::by_ref:
2444 dst = sp_refs + info->argloc[0].loc_data.offset;
2445 write_memory (dst, info->contents, info->length);
2447 second_arg_length = call_info.xlen;
2448 second_arg_data = (gdb_byte *) &dst;
2452 gdb_assert_not_reached (_("unknown argument location type"));
2455 if (second_arg_length > 0)
2457 switch (info->argloc[1].loc_type)
2459 case riscv_arg_info::location::in_reg:
2461 gdb_byte tmp [sizeof (ULONGEST)];
2463 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2464 && second_arg_length <= call_info.flen)
2465 || second_arg_length <= call_info.xlen);
2466 /* FP values in FP registers must be NaN-boxed. */
2467 if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2468 && second_arg_length < call_info.flen)
2469 memset (tmp, -1, sizeof (tmp));
2471 memset (tmp, 0, sizeof (tmp));
2472 memcpy (tmp, second_arg_data, second_arg_length);
2473 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2477 case riscv_arg_info::location::on_stack:
2481 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2482 write_memory (arg_addr, second_arg_data, second_arg_length);
2486 case riscv_arg_info::location::by_ref:
2488 /* The second location should never be a reference, any
2489 argument being passed by reference just places its address
2490 in the first location and is done. */
2491 error (_("invalid argument location"));
2497 /* Set the dummy return value to bp_addr.
2498 A dummy breakpoint will be setup to execute the call. */
2500 if (riscv_debug_infcall > 0)
2501 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2502 core_addr_to_string (bp_addr));
2503 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2505 /* Finally, update the stack pointer. */
2507 if (riscv_debug_infcall > 0)
2508 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2509 core_addr_to_string (sp));
2510 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2515 /* Implement the return_value gdbarch method. */
2517 static enum return_value_convention
2518 riscv_return_value (struct gdbarch *gdbarch,
2519 struct value *function,
2521 struct regcache *regcache,
2523 const gdb_byte *writebuf)
2525 struct riscv_call_info call_info (gdbarch);
2526 struct riscv_arg_info info;
2527 struct type *arg_type;
2529 arg_type = check_typedef (type);
2530 riscv_arg_location (gdbarch, &info, &call_info, arg_type);
2532 if (riscv_debug_infcall > 0)
2534 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2535 fprintf_unfiltered (gdb_stdlog, "[R] ");
2536 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2537 fprintf_unfiltered (gdb_stdlog, "\n");
2540 if (readbuf != nullptr || writebuf != nullptr)
2544 switch (info.argloc[0].loc_type)
2546 /* Return value in register(s). */
2547 case riscv_arg_info::location::in_reg:
2549 regnum = info.argloc[0].loc_data.regno;
2552 regcache->cooked_read (regnum, readbuf);
2555 regcache->cooked_write (regnum, writebuf);
2557 /* A return value in register can have a second part in a
2559 if (info.argloc[0].c_length < info.length)
2561 switch (info.argloc[1].loc_type)
2563 case riscv_arg_info::location::in_reg:
2564 regnum = info.argloc[1].loc_data.regno;
2568 readbuf += info.argloc[1].c_offset;
2569 regcache->cooked_read (regnum, readbuf);
2574 writebuf += info.argloc[1].c_offset;
2575 regcache->cooked_write (regnum, writebuf);
2579 case riscv_arg_info::location::by_ref:
2580 case riscv_arg_info::location::on_stack:
2582 error (_("invalid argument location"));
2589 /* Return value by reference will have its address in A0. */
2590 case riscv_arg_info::location::by_ref:
2594 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2596 if (readbuf != nullptr)
2597 read_memory (addr, readbuf, info.length);
2598 if (writebuf != nullptr)
2599 write_memory (addr, writebuf, info.length);
2603 case riscv_arg_info::location::on_stack:
2605 error (_("invalid argument location"));
2610 switch (info.argloc[0].loc_type)
2612 case riscv_arg_info::location::in_reg:
2613 return RETURN_VALUE_REGISTER_CONVENTION;
2614 case riscv_arg_info::location::by_ref:
2615 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2616 case riscv_arg_info::location::on_stack:
2618 error (_("invalid argument location"));
2622 /* Implement the frame_align gdbarch method. */
2625 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2627 return align_down (addr, 16);
2630 /* Implement the unwind_pc gdbarch method. */
2633 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2635 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2638 /* Implement the unwind_sp gdbarch method. */
2641 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2643 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2646 /* Implement the dummy_id gdbarch method. */
2648 static struct frame_id
2649 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2651 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2652 get_frame_pc (this_frame));
2655 /* Generate, or return the cached frame cache for the RiscV frame
2658 static struct riscv_unwind_cache *
2659 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2661 CORE_ADDR pc, start_addr;
2662 struct riscv_unwind_cache *cache;
2663 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2666 if ((*this_cache) != NULL)
2667 return (struct riscv_unwind_cache *) *this_cache;
2669 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2670 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2671 (*this_cache) = cache;
2673 /* Scan the prologue, filling in the cache. */
2674 start_addr = get_frame_func (this_frame);
2675 pc = get_frame_pc (this_frame);
2676 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2678 /* We can now calculate the frame base address. */
2680 = (get_frame_register_signed (this_frame, cache->frame_base_reg)
2681 + cache->frame_base_offset);
2682 if (riscv_debug_unwinder)
2683 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2684 core_addr_to_string (cache->frame_base),
2685 gdbarch_register_name (gdbarch,
2686 cache->frame_base_reg),
2687 cache->frame_base_offset);
2689 /* The prologue scanner sets the address of registers stored to the stack
2690 as the offset of that register from the frame base. The prologue
2691 scanner doesn't know the actual frame base value, and so is unable to
2692 compute the exact address. We do now know the frame base value, so
2693 update the address of registers stored to the stack. */
2694 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2695 for (regno = 0; regno < numregs; ++regno)
2697 if (trad_frame_addr_p (cache->regs, regno))
2698 cache->regs[regno].addr += cache->frame_base;
2701 /* The previous $pc can be found wherever the $ra value can be found.
2702 The previous $ra value is gone, this would have been stored be the
2703 previous frame if required. */
2704 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2705 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2707 /* Build the frame id. */
2708 cache->this_id = frame_id_build (cache->frame_base, start_addr);
2710 /* The previous $sp value is the frame base value. */
2711 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2717 /* Implement the this_id callback for RiscV frame unwinder. */
2720 riscv_frame_this_id (struct frame_info *this_frame,
2721 void **prologue_cache,
2722 struct frame_id *this_id)
2724 struct riscv_unwind_cache *cache;
2726 cache = riscv_frame_cache (this_frame, prologue_cache);
2727 *this_id = cache->this_id;
2730 /* Implement the prev_register callback for RiscV frame unwinder. */
2732 static struct value *
2733 riscv_frame_prev_register (struct frame_info *this_frame,
2734 void **prologue_cache,
2737 struct riscv_unwind_cache *cache;
2739 cache = riscv_frame_cache (this_frame, prologue_cache);
2740 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
2743 /* Structure defining the RiscV normal frame unwind functions. Since we
2744 are the fallback unwinder (DWARF unwinder is used first), we use the
2745 default frame sniffer, which always accepts the frame. */
2747 static const struct frame_unwind riscv_frame_unwind =
2749 /*.type =*/ NORMAL_FRAME,
2750 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2751 /*.this_id =*/ riscv_frame_this_id,
2752 /*.prev_register =*/ riscv_frame_prev_register,
2753 /*.unwind_data =*/ NULL,
2754 /*.sniffer =*/ default_frame_sniffer,
2755 /*.dealloc_cache =*/ NULL,
2756 /*.prev_arch =*/ NULL,
2759 /* Initialize the current architecture based on INFO. If possible,
2760 re-use an architecture from ARCHES, which is a list of
2761 architectures already created during this debugging session.
2763 Called e.g. at program startup, when reading a core file, and when
2764 reading a binary file. */
2766 static struct gdbarch *
2767 riscv_gdbarch_init (struct gdbarch_info info,
2768 struct gdbarch_list *arches)
2770 struct gdbarch *gdbarch;
2771 struct gdbarch_tdep *tdep;
2772 struct gdbarch_tdep tmp_tdep;
2775 /* Ideally, we'd like to get as much information from the target for
2776 things like register size, and whether the target has floating point
2777 hardware. However, there are some things that the target can't tell
2778 us, like, what ABI is being used.
2780 So, for now, we take as much information as possible from the ELF,
2781 including things like register size, and FP hardware support, along
2782 with information about the ABI.
2784 Information about this target is built up in TMP_TDEP, and then we
2785 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2786 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2787 memset (&tmp_tdep, 0, sizeof (tmp_tdep));
2789 if (info.abfd != NULL
2790 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2792 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2793 int e_flags = elf_elfheader (info.abfd)->e_flags;
2795 if (eclass == ELFCLASS32)
2796 tmp_tdep.abi.fields.base_len = 1;
2797 else if (eclass == ELFCLASS64)
2798 tmp_tdep.abi.fields.base_len = 2;
2800 internal_error (__FILE__, __LINE__,
2801 _("unknown ELF header class %d"), eclass);
2803 if (e_flags & EF_RISCV_RVC)
2804 tmp_tdep.core_features |= (1 << ('C' - 'A'));
2806 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2808 tmp_tdep.abi.fields.float_abi = 2;
2809 tmp_tdep.core_features |= (1 << ('D' - 'A'));
2810 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2812 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2814 tmp_tdep.abi.fields.float_abi = 1;
2815 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2820 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2822 if (binfo->bits_per_word == 32)
2823 tmp_tdep.abi.fields.base_len = 1;
2824 else if (binfo->bits_per_word == 64)
2825 tmp_tdep.abi.fields.base_len = 2;
2827 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2828 binfo->bits_per_word);
2831 /* Find a candidate among the list of pre-declared architectures. */
2832 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2834 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2835 if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
2836 return arches->gdbarch;
2838 /* None found, so create a new architecture from the information provided. */
2839 tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
2840 gdbarch = gdbarch_alloc (&info, tdep);
2841 memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep));
2843 /* Target data types. */
2844 set_gdbarch_short_bit (gdbarch, 16);
2845 set_gdbarch_int_bit (gdbarch, 32);
2846 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2847 set_gdbarch_long_long_bit (gdbarch, 64);
2848 set_gdbarch_float_bit (gdbarch, 32);
2849 set_gdbarch_double_bit (gdbarch, 64);
2850 set_gdbarch_long_double_bit (gdbarch, 128);
2851 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2852 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2853 set_gdbarch_char_signed (gdbarch, 0);
2855 /* Information about the target architecture. */
2856 set_gdbarch_return_value (gdbarch, riscv_return_value);
2857 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
2858 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
2859 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2861 /* Register architecture. */
2862 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
2863 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
2864 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
2865 set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
2866 set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
2868 /* Functions to supply register information. */
2869 set_gdbarch_register_name (gdbarch, riscv_register_name);
2870 set_gdbarch_register_type (gdbarch, riscv_register_type);
2871 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
2872 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
2874 /* Functions to analyze frames. */
2875 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
2876 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2877 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
2879 /* Functions to access frame data. */
2880 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
2881 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
2883 /* Functions handling dummy frames. */
2884 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2885 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
2886 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
2887 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
2889 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2891 dwarf2_append_unwinders (gdbarch);
2892 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
2894 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
2895 user_reg_add (gdbarch, riscv_register_aliases[i].name,
2896 value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
2898 /* Hook in OS ABI-specific overrides, if they have been registered. */
2899 gdbarch_init_osabi (info, gdbarch);
2904 /* This decodes the current instruction and determines the address of the
2905 next instruction. */
2908 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
2910 struct gdbarch *gdbarch = regcache->arch ();
2911 struct riscv_insn insn;
2914 insn.decode (gdbarch, pc);
2915 next_pc = pc + insn.length ();
2917 if (insn.opcode () == riscv_insn::JAL)
2918 next_pc = pc + insn.imm_signed ();
2919 else if (insn.opcode () == riscv_insn::JALR)
2922 regcache->cooked_read (insn.rs1 (), &source);
2923 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
2925 else if (insn.opcode () == riscv_insn::BEQ)
2928 regcache->cooked_read (insn.rs1 (), &src1);
2929 regcache->cooked_read (insn.rs2 (), &src2);
2931 next_pc = pc + insn.imm_signed ();
2933 else if (insn.opcode () == riscv_insn::BNE)
2936 regcache->cooked_read (insn.rs1 (), &src1);
2937 regcache->cooked_read (insn.rs2 (), &src2);
2939 next_pc = pc + insn.imm_signed ();
2941 else if (insn.opcode () == riscv_insn::BLT)
2944 regcache->cooked_read (insn.rs1 (), &src1);
2945 regcache->cooked_read (insn.rs2 (), &src2);
2947 next_pc = pc + insn.imm_signed ();
2949 else if (insn.opcode () == riscv_insn::BGE)
2952 regcache->cooked_read (insn.rs1 (), &src1);
2953 regcache->cooked_read (insn.rs2 (), &src2);
2955 next_pc = pc + insn.imm_signed ();
2957 else if (insn.opcode () == riscv_insn::BLTU)
2959 ULONGEST src1, src2;
2960 regcache->cooked_read (insn.rs1 (), &src1);
2961 regcache->cooked_read (insn.rs2 (), &src2);
2963 next_pc = pc + insn.imm_signed ();
2965 else if (insn.opcode () == riscv_insn::BGEU)
2967 ULONGEST src1, src2;
2968 regcache->cooked_read (insn.rs1 (), &src1);
2969 regcache->cooked_read (insn.rs2 (), &src2);
2971 next_pc = pc + insn.imm_signed ();
2977 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
2978 for the end of the sequence and put the breakpoint there. */
2981 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
2984 struct gdbarch *gdbarch = regcache->arch ();
2985 struct riscv_insn insn;
2986 CORE_ADDR cur_step_pc = pc;
2987 CORE_ADDR last_addr = 0;
2989 /* First instruction has to be a load reserved. */
2990 insn.decode (gdbarch, cur_step_pc);
2991 if (insn.opcode () != riscv_insn::LR)
2993 cur_step_pc = cur_step_pc + insn.length ();
2995 /* Next instruction should be branch to exit. */
2996 insn.decode (gdbarch, cur_step_pc);
2997 if (insn.opcode () != riscv_insn::BNE)
2999 last_addr = cur_step_pc + insn.imm_signed ();
3000 cur_step_pc = cur_step_pc + insn.length ();
3002 /* Next instruction should be store conditional. */
3003 insn.decode (gdbarch, cur_step_pc);
3004 if (insn.opcode () != riscv_insn::SC)
3006 cur_step_pc = cur_step_pc + insn.length ();
3008 /* Next instruction should be branch to start. */
3009 insn.decode (gdbarch, cur_step_pc);
3010 if (insn.opcode () != riscv_insn::BNE)
3012 if (pc != (cur_step_pc + insn.imm_signed ()))
3014 cur_step_pc = cur_step_pc + insn.length ();
3016 /* We should now be at the end of the sequence. */
3017 if (cur_step_pc != last_addr)
3020 *next_pc = cur_step_pc;
3024 /* This is called just before we want to resume the inferior, if we want to
3025 single-step it but there is no hardware or kernel single-step support. We
3026 find the target of the coming instruction and breakpoint it. */
3028 std::vector<CORE_ADDR>
3029 riscv_software_single_step (struct regcache *regcache)
3031 CORE_ADDR pc, next_pc;
3033 pc = regcache_read_pc (regcache);
3035 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
3038 next_pc = riscv_next_pc (regcache, pc);
3044 _initialize_riscv_tdep (void)
3046 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
3048 /* Add root prefix command for all "set debug riscv" and "show debug
3050 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
3051 _("RISC-V specific debug commands."),
3052 &setdebugriscvcmdlist, "set debug riscv ", 0,
3055 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
3056 _("RISC-V specific debug commands."),
3057 &showdebugriscvcmdlist, "show debug riscv ", 0,
3060 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
3061 &riscv_debug_breakpoints, _("\
3062 Set riscv breakpoint debugging."), _("\
3063 Show riscv breakpoint debugging."), _("\
3064 When non-zero, print debugging information for the riscv specific parts\n\
3065 of the breakpoint mechanism."),
3067 show_riscv_debug_variable,
3068 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3070 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
3071 &riscv_debug_infcall, _("\
3072 Set riscv inferior call debugging."), _("\
3073 Show riscv inferior call debugging."), _("\
3074 When non-zero, print debugging information for the riscv specific parts\n\
3075 of the inferior call mechanism."),
3077 show_riscv_debug_variable,
3078 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3080 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
3081 &riscv_debug_unwinder, _("\
3082 Set riscv stack unwinding debugging."), _("\
3083 Show riscv stack unwinding debugging."), _("\
3084 When non-zero, print debugging information for the riscv specific parts\n\
3085 of the stack unwinding mechanism."),
3087 show_riscv_debug_variable,
3088 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3090 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3091 add_prefix_cmd ("riscv", no_class, set_riscv_command,
3092 _("RISC-V specific commands."),
3093 &setriscvcmdlist, "set riscv ", 0, &setlist);
3095 add_prefix_cmd ("riscv", no_class, show_riscv_command,
3096 _("RISC-V specific commands."),
3097 &showriscvcmdlist, "show riscv ", 0, &showlist);
3100 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
3101 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
3102 &use_compressed_breakpoints,
3104 Set debugger's use of compressed breakpoints."), _(" \
3105 Show debugger's use of compressed breakpoints."), _("\
3106 Debugging compressed code requires compressed breakpoints to be used. If\n\
3107 left to 'auto' then gdb will use them if the existing instruction is a\n\
3108 compressed instruction. If that doesn't give the correct behavior, then\n\
3109 this option can be used."),
3111 show_use_compressed_breakpoints,