1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
59 /* The stack must be 16-byte aligned. */
60 #define SP_ALIGNMENT 16
62 /* Forward declarations. */
63 static bool riscv_has_feature (struct gdbarch *gdbarch, char feature);
65 /* Define a series of is_XXX_insn functions to check if the value INSN
66 is an instance of instruction XXX. */
67 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
68 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
70 return (insn & INSN_MASK) == INSN_MATCH; \
72 #include "opcode/riscv-opc.h"
75 /* Cached information about a frame. */
77 struct riscv_unwind_cache
79 /* The register from which we can calculate the frame base. This is
80 usually $sp or $fp. */
83 /* The offset from the current value in register FRAME_BASE_REG to the
84 actual frame base address. */
85 int frame_base_offset;
87 /* Information about previous register values. */
88 struct trad_frame_saved_reg *regs;
90 /* The id for this frame. */
91 struct frame_id this_id;
93 /* The base (stack) address for this frame. This is the stack pointer
94 value on entry to this frame before any adjustments are made. */
98 /* Architectural name for core registers. */
100 static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
102 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
103 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
104 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
105 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
113 /* Maps "pretty" register names onto their GDB register number. */
115 struct register_alias
117 /* The register alias. Usually more descriptive than the
118 architectural name of the register. */
121 /* The GDB register number. */
125 /* Table of register aliases. */
127 static const struct register_alias riscv_register_aliases[] =
195 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
196 #include "opcode/riscv-opc.h"
200 /* Controls whether we place compressed breakpoints or not. When in auto
201 mode GDB tries to determine if the target supports compressed
202 breakpoints, and uses them if it does. */
204 static enum auto_boolean use_compressed_breakpoints;
206 /* The show callback for 'show riscv use-compressed-breakpoints'. */
209 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
210 struct cmd_list_element *c,
213 fprintf_filtered (file,
214 _("Debugger's use of compressed breakpoints is set "
218 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
220 static struct cmd_list_element *setriscvcmdlist = NULL;
221 static struct cmd_list_element *showriscvcmdlist = NULL;
223 /* The show callback for the 'show riscv' prefix command. */
226 show_riscv_command (const char *args, int from_tty)
228 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
231 /* The set callback for the 'set riscv' prefix command. */
234 set_riscv_command (const char *args, int from_tty)
237 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
238 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
241 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
243 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
244 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
246 /* The show callback for the 'show debug riscv' prefix command. */
249 show_debug_riscv_command (const char *args, int from_tty)
251 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
254 /* The set callback for the 'set debug riscv' prefix command. */
257 set_debug_riscv_command (const char *args, int from_tty)
260 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
261 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
264 /* The show callback for all 'show debug riscv VARNAME' variables. */
267 show_riscv_debug_variable (struct ui_file *file, int from_tty,
268 struct cmd_list_element *c,
271 fprintf_filtered (file,
272 _("RiscV debug variable `%s' is set to: %s\n"),
276 /* When this is set to non-zero debugging information about breakpoint
277 kinds will be printed. */
279 static unsigned int riscv_debug_breakpoints = 0;
281 /* When this is set to non-zero debugging information about inferior calls
284 static unsigned int riscv_debug_infcall = 0;
286 /* When this is set to non-zero debugging information about stack unwinding
289 static unsigned int riscv_debug_unwinder = 0;
291 /* Read the MISA register from the target. The register will only be read
292 once, and the value read will be cached. If the register can't be read
293 from the target then a default value (0) will be returned. If the
294 pointer READ_P is not null, then the bool pointed to is updated to
295 indicate if the value returned was read from the target (true) or is the
299 riscv_read_misa_reg (bool *read_p)
303 if (target_has_registers)
305 struct frame_info *frame = get_current_frame ();
309 value = get_frame_register_unsigned (frame,
310 RISCV_CSR_MISA_REGNUM);
312 CATCH (ex, RETURN_MASK_ERROR)
314 /* Old cores might have MISA located at a different offset. */
315 value = get_frame_register_unsigned (frame,
316 RISCV_CSR_LEGACY_MISA_REGNUM);
324 /* Return true if FEATURE is available for the architecture GDBARCH. The
325 FEATURE should be one of the single character feature codes described in
326 the RiscV ISA manual, these are between 'A' and 'Z'. */
329 riscv_has_feature (struct gdbarch *gdbarch, char feature)
331 bool have_read_misa = false;
334 gdb_assert (feature >= 'A' && feature <= 'Z');
336 misa = riscv_read_misa_reg (&have_read_misa);
337 if (!have_read_misa || misa == 0)
338 misa = gdbarch_tdep (gdbarch)->core_features;
340 return (misa & (1 << (feature - 'A'))) != 0;
343 /* Return the width in bytes of the general purpose registers for GDBARCH.
344 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
348 riscv_isa_xlen (struct gdbarch *gdbarch)
350 switch (gdbarch_tdep (gdbarch)->abi.fields.base_len)
353 warning (_("unknown xlen size, assuming 4 bytes"));
364 /* Return the width in bytes of the floating point registers for GDBARCH.
365 If this architecture has no floating point registers, then return 0.
366 Possible values are 4, 8, or 16 for depending on which of single, double
367 or quad floating point support is available. */
370 riscv_isa_flen (struct gdbarch *gdbarch)
372 if (riscv_has_feature (gdbarch, 'Q'))
374 else if (riscv_has_feature (gdbarch, 'D'))
376 else if (riscv_has_feature (gdbarch, 'F'))
382 /* Return true if the target for GDBARCH has floating point hardware. */
385 riscv_has_fp_regs (struct gdbarch *gdbarch)
387 return (riscv_isa_flen (gdbarch) > 0);
390 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
393 riscv_has_fp_abi (struct gdbarch *gdbarch)
395 return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0);
398 /* Return true if REGNO is a floating pointer register. */
401 riscv_is_fp_regno_p (int regno)
403 return (regno >= RISCV_FIRST_FP_REGNUM
404 && regno <= RISCV_LAST_FP_REGNUM);
407 /* Implement the breakpoint_kind_from_pc gdbarch method. */
410 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
412 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
416 /* Read the opcode byte to determine the instruction length. */
417 read_code (*pcptr, buf, 1);
419 if (riscv_debug_breakpoints)
422 "Using %s for breakpoint at %s (instruction length %d)\n",
423 riscv_insn_length (buf[0]) == 2 ? "C.EBREAK" : "EBREAK",
424 paddress (gdbarch, *pcptr), riscv_insn_length (buf[0]));
425 if (riscv_insn_length (buf[0]) == 2)
430 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
436 /* Implement the sw_breakpoint_from_kind gdbarch method. */
438 static const gdb_byte *
439 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
441 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
442 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
452 gdb_assert_not_reached (_("unhandled breakpoint kind"));
456 /* Callback function for user_reg_add. */
458 static struct value *
459 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
461 const int *reg_p = (const int *) baton;
462 return value_of_register (*reg_p, frame);
465 /* Implement the register_name gdbarch method. */
468 riscv_register_name (struct gdbarch *gdbarch, int regnum)
470 /* Prefer to use the alias. */
471 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM)
475 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
476 if (regnum == riscv_register_aliases[i].regnum)
477 return riscv_register_aliases[i].name;
480 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
481 return riscv_gdb_reg_names[regnum];
483 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
487 xsnprintf (buf, sizeof (buf), "csr%d",
488 regnum - RISCV_FIRST_CSR_REGNUM);
492 if (regnum == RISCV_PRIV_REGNUM)
498 /* Construct a type for 64-bit FP registers. */
501 riscv_fpreg_d_type (struct gdbarch *gdbarch)
503 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
505 if (tdep->riscv_fpreg_d_type == nullptr)
507 const struct builtin_type *bt = builtin_type (gdbarch);
509 /* The type we're building is this: */
511 union __gdb_builtin_type_fpreg_d
520 t = arch_composite_type (gdbarch,
521 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
522 append_composite_type_field (t, "float", bt->builtin_float);
523 append_composite_type_field (t, "double", bt->builtin_double);
525 TYPE_NAME (t) = "builtin_type_fpreg_d";
526 tdep->riscv_fpreg_d_type = t;
529 return tdep->riscv_fpreg_d_type;
532 /* Construct a type for 128-bit FP registers. */
535 riscv_fpreg_q_type (struct gdbarch *gdbarch)
537 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
539 if (tdep->riscv_fpreg_q_type == nullptr)
541 const struct builtin_type *bt = builtin_type (gdbarch);
543 /* The type we're building is this: */
545 union __gdb_builtin_type_fpreg_d
555 t = arch_composite_type (gdbarch,
556 "__gdb_builtin_type_fpreg_q", TYPE_CODE_UNION);
557 append_composite_type_field (t, "float", bt->builtin_float);
558 append_composite_type_field (t, "double", bt->builtin_double);
559 append_composite_type_field (t, "long double", bt->builtin_long_double);
561 TYPE_NAME (t) = "builtin_type_fpreg_q";
562 tdep->riscv_fpreg_q_type = t;
565 return tdep->riscv_fpreg_q_type;
568 /* Implement the register_type gdbarch method. */
571 riscv_register_type (struct gdbarch *gdbarch, int regnum)
575 if (regnum < RISCV_FIRST_FP_REGNUM)
577 if (regnum == gdbarch_pc_regnum (gdbarch)
578 || regnum == RISCV_RA_REGNUM)
579 return builtin_type (gdbarch)->builtin_func_ptr;
581 if (regnum == RISCV_FP_REGNUM
582 || regnum == RISCV_SP_REGNUM
583 || regnum == RISCV_GP_REGNUM
584 || regnum == RISCV_TP_REGNUM)
585 return builtin_type (gdbarch)->builtin_data_ptr;
587 /* Remaining GPRs vary in size based on the current ISA. */
588 regsize = riscv_isa_xlen (gdbarch);
592 return builtin_type (gdbarch)->builtin_uint32;
594 return builtin_type (gdbarch)->builtin_uint64;
596 return builtin_type (gdbarch)->builtin_uint128;
598 internal_error (__FILE__, __LINE__,
599 _("unknown isa regsize %i"), regsize);
602 else if (regnum <= RISCV_LAST_FP_REGNUM)
604 regsize = riscv_isa_xlen (gdbarch);
608 return builtin_type (gdbarch)->builtin_float;
610 return riscv_fpreg_d_type (gdbarch);
612 return riscv_fpreg_q_type (gdbarch);
614 internal_error (__FILE__, __LINE__,
615 _("unknown isa regsize %i"), regsize);
618 else if (regnum == RISCV_PRIV_REGNUM)
619 return builtin_type (gdbarch)->builtin_int8;
622 if (regnum == RISCV_CSR_FFLAGS_REGNUM
623 || regnum == RISCV_CSR_FRM_REGNUM
624 || regnum == RISCV_CSR_FCSR_REGNUM)
625 return builtin_type (gdbarch)->builtin_int32;
627 regsize = riscv_isa_xlen (gdbarch);
631 return builtin_type (gdbarch)->builtin_int32;
633 return builtin_type (gdbarch)->builtin_int64;
635 return builtin_type (gdbarch)->builtin_int128;
637 internal_error (__FILE__, __LINE__,
638 _("unknown isa regsize %i"), regsize);
643 /* Helper for riscv_print_registers_info, prints info for a single register
647 riscv_print_one_register_info (struct gdbarch *gdbarch,
648 struct ui_file *file,
649 struct frame_info *frame,
652 const char *name = gdbarch_register_name (gdbarch, regnum);
653 struct value *val = value_of_register (regnum, frame);
654 struct type *regtype = value_type (val);
655 int print_raw_format;
656 enum tab_stops { value_column_1 = 15 };
658 fputs_filtered (name, file);
659 print_spaces_filtered (value_column_1 - strlen (name), file);
661 print_raw_format = (value_entirely_available (val)
662 && !value_optimized_out (val));
664 if (TYPE_CODE (regtype) == TYPE_CODE_FLT
665 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
666 && TYPE_NFIELDS (regtype) == 2
667 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
668 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
669 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
670 && TYPE_NFIELDS (regtype) == 3
671 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
672 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
673 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
675 struct value_print_options opts;
676 const gdb_byte *valaddr = value_contents_for_printing (val);
677 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
679 get_user_print_options (&opts);
683 value_embedded_offset (val), 0,
684 file, 0, val, &opts, current_language);
686 if (print_raw_format)
688 fprintf_filtered (file, "\t(raw ");
689 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
691 fprintf_filtered (file, ")");
696 struct value_print_options opts;
698 /* Print the register in hex. */
699 get_formatted_print_options (&opts, 'x');
702 value_embedded_offset (val), 0,
703 file, 0, val, &opts, current_language);
705 if (print_raw_format)
707 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
710 int size = register_size (gdbarch, regnum);
713 d = value_as_long (val);
715 fprintf_filtered (file,
716 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
717 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
718 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
719 (int) ((d >> (xlen - 1)) & 0x1),
720 (int) ((d >> 24) & 0x1f),
721 (int) ((d >> 19) & 0x1),
722 (int) ((d >> 18) & 0x1),
723 (int) ((d >> 17) & 0x1),
724 (int) ((d >> 15) & 0x3),
725 (int) ((d >> 13) & 0x3),
726 (int) ((d >> 11) & 0x3),
727 (int) ((d >> 9) & 0x3),
728 (int) ((d >> 8) & 0x1),
729 (int) ((d >> 7) & 0x1),
730 (int) ((d >> 6) & 0x1),
731 (int) ((d >> 5) & 0x1),
732 (int) ((d >> 4) & 0x1),
733 (int) ((d >> 3) & 0x1),
734 (int) ((d >> 2) & 0x1),
735 (int) ((d >> 1) & 0x1),
736 (int) ((d >> 0) & 0x1));
738 else if (regnum == RISCV_CSR_MISA_REGNUM)
744 d = value_as_long (val);
748 for (; base > 0; base--)
750 fprintf_filtered (file, "\tRV%d", xlen);
752 for (i = 0; i < 26; i++)
755 fprintf_filtered (file, "%c", 'A' + i);
758 else if (regnum == RISCV_CSR_FCSR_REGNUM
759 || regnum == RISCV_CSR_FFLAGS_REGNUM
760 || regnum == RISCV_CSR_FRM_REGNUM)
764 d = value_as_long (val);
766 fprintf_filtered (file, "\t");
767 if (regnum != RISCV_CSR_FRM_REGNUM)
768 fprintf_filtered (file,
769 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
770 (int) ((d >> 5) & 0x7),
771 (int) ((d >> 4) & 0x1),
772 (int) ((d >> 3) & 0x1),
773 (int) ((d >> 2) & 0x1),
774 (int) ((d >> 1) & 0x1),
775 (int) ((d >> 0) & 0x1));
777 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
779 static const char * const sfrm[] =
781 "RNE (round to nearest; ties to even)",
782 "RTZ (Round towards zero)",
783 "RDN (Round down towards -INF)",
784 "RUP (Round up towards +INF)",
785 "RMM (Round to nearest; ties to max magnitude)",
788 "dynamic rounding mode",
790 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
791 ? (d >> 5) : d) & 0x3;
793 fprintf_filtered (file, "%sFRM:%i [%s]",
794 (regnum == RISCV_CSR_FCSR_REGNUM
799 else if (regnum == RISCV_PRIV_REGNUM)
804 d = value_as_long (val);
809 static const char * const sprv[] =
816 fprintf_filtered (file, "\tprv:%d [%s]",
820 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
824 /* If not a vector register, print it also according to its
826 if (TYPE_VECTOR (regtype) == 0)
828 get_user_print_options (&opts);
830 fprintf_filtered (file, "\t");
832 value_embedded_offset (val), 0,
833 file, 0, val, &opts, current_language);
838 fprintf_filtered (file, "\n");
841 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
845 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
846 struct reggroup *reggroup)
850 /* Used by 'info registers' and 'info registers <groupname>'. */
852 if (gdbarch_register_name (gdbarch, regnum) == NULL
853 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
856 if (reggroup == all_reggroup)
858 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
860 /* Only include CSRs that have aliases. */
861 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
863 if (regnum == riscv_register_aliases[i].regnum)
868 else if (reggroup == float_reggroup)
869 return (riscv_is_fp_regno_p (regnum)
870 || regnum == RISCV_CSR_FCSR_REGNUM
871 || regnum == RISCV_CSR_FFLAGS_REGNUM
872 || regnum == RISCV_CSR_FRM_REGNUM);
873 else if (reggroup == general_reggroup)
874 return regnum < RISCV_FIRST_FP_REGNUM;
875 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
877 if (riscv_has_fp_regs (gdbarch))
878 return regnum <= RISCV_LAST_FP_REGNUM;
880 return regnum < RISCV_FIRST_FP_REGNUM;
882 else if (reggroup == system_reggroup)
884 if (regnum == RISCV_PRIV_REGNUM)
886 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
888 /* Only include CSRs that have aliases. */
889 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
891 if (regnum == riscv_register_aliases[i].regnum)
896 else if (reggroup == vector_reggroup)
902 /* Implement the print_registers_info gdbarch method. This is used by
903 'info registers' and 'info all-registers'. */
906 riscv_print_registers_info (struct gdbarch *gdbarch,
907 struct ui_file *file,
908 struct frame_info *frame,
909 int regnum, int print_all)
913 /* Print one specified register. */
914 gdb_assert (regnum <= RISCV_LAST_REGNUM);
915 if (gdbarch_register_name (gdbarch, regnum) == NULL
916 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
917 error (_("Not a valid register for the current processor type"));
918 riscv_print_one_register_info (gdbarch, file, frame, regnum);
922 struct reggroup *reggroup;
925 reggroup = all_reggroup;
927 reggroup = general_reggroup;
929 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
931 /* Zero never changes, so might as well hide by default. */
932 if (regnum == RISCV_ZERO_REGNUM && !print_all)
935 /* Registers with no name are not valid on this ISA. */
936 if (gdbarch_register_name (gdbarch, regnum) == NULL
937 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
940 /* Is the register in the group we're interested in? */
941 if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup))
944 riscv_print_one_register_info (gdbarch, file, frame, regnum);
949 /* Class that handles one decoded RiscV instruction. */
955 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
958 /* Unknown value is used at initialisation time. */
961 /* These instructions are all the ones we are interested in during the
971 /* These are needed for software breakopint support. */
980 /* These are needed for stepping over atomic sequences. */
984 /* Other instructions are not interesting during the prologue scan, and
999 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1001 /* Get the length of the instruction in bytes. */
1003 { return m_length; }
1005 /* Get the opcode for this instruction. */
1006 enum opcode opcode () const
1007 { return m_opcode; }
1009 /* Get destination register field for this instruction. This is only
1010 valid if the OPCODE implies there is such a field for this
1015 /* Get the RS1 register field for this instruction. This is only valid
1016 if the OPCODE implies there is such a field for this instruction. */
1020 /* Get the RS2 register field for this instruction. This is only valid
1021 if the OPCODE implies there is such a field for this instruction. */
1025 /* Get the immediate for this instruction in signed form. This is only
1026 valid if the OPCODE implies there is such a field for this
1028 int imm_signed () const
1033 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1034 int decode_register_index (unsigned long opcode, int offset)
1036 return (opcode >> offset) & 0x1F;
1039 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1040 int decode_register_index_short (unsigned long opcode, int offset)
1042 return ((opcode >> offset) & 0x7) + 8;
1045 /* Helper for DECODE, decode 32-bit R-type instruction. */
1046 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1049 m_rd = decode_register_index (ival, OP_SH_RD);
1050 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1051 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1054 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1055 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1058 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1059 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1062 /* Helper for DECODE, decode 32-bit I-type instruction. */
1063 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1066 m_rd = decode_register_index (ival, OP_SH_RD);
1067 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1068 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1071 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1072 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1075 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1076 m_imm.s = EXTRACT_RVC_IMM (ival);
1079 /* Helper for DECODE, decode 32-bit S-type instruction. */
1080 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1083 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1084 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1085 m_imm.s = EXTRACT_STYPE_IMM (ival);
1088 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1089 encoding is different for each CS format instruction, so extracting
1090 the immediate is left up to the caller, who should pass the extracted
1091 immediate value through in IMM. */
1092 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1096 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1097 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1100 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1101 encoding is different for each CSS format instruction, so extracting
1102 the immediate is left up to the caller, who should pass the extracted
1103 immediate value through in IMM. */
1104 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1108 m_rs1 = RISCV_SP_REGNUM;
1109 /* Not a compressed register number in this case. */
1110 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1113 /* Helper for DECODE, decode 32-bit U-type instruction. */
1114 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1117 m_rd = decode_register_index (ival, OP_SH_RD);
1118 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1121 /* Helper for DECODE, decode 32-bit J-type instruction. */
1122 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1125 m_rd = decode_register_index (ival, OP_SH_RD);
1126 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1129 /* Helper for DECODE, decode 32-bit J-type instruction. */
1130 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1133 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1136 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1139 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1140 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1141 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1144 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1147 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1148 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1151 /* Fetch instruction from target memory at ADDR, return the content of
1152 the instruction, and update LEN with the instruction length. */
1153 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1154 CORE_ADDR addr, int *len);
1156 /* The length of the instruction in bytes. Should be 2 or 4. */
1159 /* The instruction opcode. */
1160 enum opcode m_opcode;
1162 /* The three possible registers an instruction might reference. Not
1163 every instruction fills in all of these registers. Which fields are
1164 valid depends on the opcode. The naming of these fields matches the
1165 naming in the riscv isa manual. */
1170 /* Possible instruction immediate. This is only valid if the instruction
1171 format contains an immediate, not all instruction, whether this is
1172 valid depends on the opcode. Despite only having one format for now
1173 the immediate is packed into a union, later instructions might require
1174 an unsigned formatted immediate, having the union in place now will
1175 reduce the need for code churn later. */
1176 union riscv_insn_immediate
1178 riscv_insn_immediate ()
1188 /* Fetch instruction from target memory at ADDR, return the content of the
1189 instruction, and update LEN with the instruction length. */
1192 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1193 CORE_ADDR addr, int *len)
1195 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1197 int instlen, status;
1199 /* All insns are at least 16 bits. */
1200 status = target_read_memory (addr, buf, 2);
1202 memory_error (TARGET_XFER_E_IO, addr);
1204 /* If we need more, grab it now. */
1205 instlen = riscv_insn_length (buf[0]);
1206 gdb_assert (instlen <= sizeof (buf));
1211 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1213 memory_error (TARGET_XFER_E_IO, addr + 2);
1216 return extract_unsigned_integer (buf, instlen, byte_order);
1219 /* Fetch from target memory an instruction at PC and decode it. */
1222 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1226 /* Fetch the instruction, and the instructions length. */
1227 ival = fetch_instruction (gdbarch, pc, &m_length);
1231 if (is_add_insn (ival))
1232 decode_r_type_insn (ADD, ival);
1233 else if (is_addw_insn (ival))
1234 decode_r_type_insn (ADDW, ival);
1235 else if (is_addi_insn (ival))
1236 decode_i_type_insn (ADDI, ival);
1237 else if (is_addiw_insn (ival))
1238 decode_i_type_insn (ADDIW, ival);
1239 else if (is_auipc_insn (ival))
1240 decode_u_type_insn (AUIPC, ival);
1241 else if (is_lui_insn (ival))
1242 decode_u_type_insn (LUI, ival);
1243 else if (is_sd_insn (ival))
1244 decode_s_type_insn (SD, ival);
1245 else if (is_sw_insn (ival))
1246 decode_s_type_insn (SW, ival);
1247 else if (is_jal_insn (ival))
1248 decode_j_type_insn (JAL, ival);
1249 else if (is_jalr_insn (ival))
1250 decode_i_type_insn (JALR, ival);
1251 else if (is_beq_insn (ival))
1252 decode_b_type_insn (BEQ, ival);
1253 else if (is_bne_insn (ival))
1254 decode_b_type_insn (BNE, ival);
1255 else if (is_blt_insn (ival))
1256 decode_b_type_insn (BLT, ival);
1257 else if (is_bge_insn (ival))
1258 decode_b_type_insn (BGE, ival);
1259 else if (is_bltu_insn (ival))
1260 decode_b_type_insn (BLTU, ival);
1261 else if (is_bgeu_insn (ival))
1262 decode_b_type_insn (BGEU, ival);
1263 else if (is_lr_w_insn (ival))
1264 decode_r_type_insn (LR, ival);
1265 else if (is_lr_d_insn (ival))
1266 decode_r_type_insn (LR, ival);
1267 else if (is_sc_w_insn (ival))
1268 decode_r_type_insn (SC, ival);
1269 else if (is_sc_d_insn (ival))
1270 decode_r_type_insn (SC, ival);
1272 /* None of the other fields are valid in this case. */
1275 else if (m_length == 2)
1277 int xlen = riscv_isa_xlen (gdbarch);
1279 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1280 C_JALR. So must try to match C_JALR first as it has more bits in
1282 if (is_c_jalr_insn (ival))
1283 decode_cr_type_insn (JALR, ival);
1284 else if (is_c_add_insn (ival))
1285 decode_cr_type_insn (ADD, ival);
1286 /* C_ADDW is RV64 and RV128 only. */
1287 else if (xlen != 4 && is_c_addw_insn (ival))
1288 decode_cr_type_insn (ADDW, ival);
1289 else if (is_c_addi_insn (ival))
1290 decode_ci_type_insn (ADDI, ival);
1291 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1292 only and C_JAL is RV32 only. */
1293 else if (xlen != 4 && is_c_addiw_insn (ival))
1294 decode_ci_type_insn (ADDIW, ival);
1295 else if (xlen == 4 && is_c_jal_insn (ival))
1296 decode_cj_type_insn (JAL, ival);
1297 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1298 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1300 else if (is_c_addi16sp_insn (ival))
1303 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1304 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1306 else if (is_c_addi4spn_insn (ival))
1309 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1310 m_rs1 = RISCV_SP_REGNUM;
1311 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1313 else if (is_c_lui_insn (ival))
1316 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1317 m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
1319 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1320 and C_FSW is RV32 only. */
1321 else if (xlen != 4 && is_c_sd_insn (ival))
1322 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
1323 else if (is_c_sw_insn (ival))
1324 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1325 else if (is_c_swsp_insn (ival))
1326 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1327 else if (xlen != 4 && is_c_sdsp_insn (ival))
1328 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
1329 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1330 So must try to match C_JR first as it ahs more bits in mask. */
1331 else if (is_c_jr_insn (ival))
1332 decode_cr_type_insn (JALR, ival);
1333 else if (is_c_j_insn (ival))
1334 decode_cj_type_insn (JAL, ival);
1335 else if (is_c_beqz_insn (ival))
1336 decode_cb_type_insn (BEQ, ival);
1337 else if (is_c_bnez_insn (ival))
1338 decode_cb_type_insn (BNE, ival);
1340 /* None of the other fields of INSN are valid in this case. */
1344 internal_error (__FILE__, __LINE__,
1345 _("unable to decode %d byte instructions in "
1346 "prologue at %s"), m_length,
1347 core_addr_to_string (pc));
1350 /* The prologue scanner. This is currently only used for skipping the
1351 prologue of a function when the DWARF information is not sufficient.
1352 However, it is written with filling of the frame cache in mind, which
1353 is why different groups of stack setup instructions are split apart
1354 during the core of the inner loop. In the future, the intention is to
1355 extend this function to fully support building up a frame cache that
1356 can unwind register values when there is no DWARF information. */
1359 riscv_scan_prologue (struct gdbarch *gdbarch,
1360 CORE_ADDR start_pc, CORE_ADDR end_pc,
1361 struct riscv_unwind_cache *cache)
1363 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1364 CORE_ADDR end_prologue_addr = 0;
1366 /* Find an upper limit on the function prologue using the debug
1367 information. If the debug information could not be used to provide
1368 that bound, then use an arbitrary large number as the upper bound. */
1369 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1370 if (after_prologue_pc == 0)
1371 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1372 if (after_prologue_pc < end_pc)
1373 end_pc = after_prologue_pc;
1375 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1376 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1377 regs[regno] = pv_register (regno, 0);
1378 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1380 if (riscv_debug_unwinder)
1383 "Prologue scan for function starting at %s (limit %s)\n",
1384 core_addr_to_string (start_pc),
1385 core_addr_to_string (end_pc));
1387 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1389 struct riscv_insn insn;
1391 /* Decode the current instruction, and decide where the next
1392 instruction lives based on the size of this instruction. */
1393 insn.decode (gdbarch, cur_pc);
1394 gdb_assert (insn.length () > 0);
1395 next_pc = cur_pc + insn.length ();
1397 /* Look for common stack adjustment insns. */
1398 if ((insn.opcode () == riscv_insn::ADDI
1399 || insn.opcode () == riscv_insn::ADDIW)
1400 && insn.rd () == RISCV_SP_REGNUM
1401 && insn.rs1 () == RISCV_SP_REGNUM)
1403 /* Handle: addi sp, sp, -i
1404 or: addiw sp, sp, -i */
1405 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1406 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1408 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1410 else if ((insn.opcode () == riscv_insn::SW
1411 || insn.opcode () == riscv_insn::SD)
1412 && (insn.rs1 () == RISCV_SP_REGNUM
1413 || insn.rs1 () == RISCV_FP_REGNUM))
1415 /* Handle: sw reg, offset(sp)
1416 or: sd reg, offset(sp)
1417 or: sw reg, offset(s0)
1418 or: sd reg, offset(s0) */
1419 /* Instruction storing a register onto the stack. */
1420 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1421 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1422 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1423 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1426 else if (insn.opcode () == riscv_insn::ADDI
1427 && insn.rd () == RISCV_FP_REGNUM
1428 && insn.rs1 () == RISCV_SP_REGNUM)
1430 /* Handle: addi s0, sp, size */
1431 /* Instructions setting up the frame pointer. */
1432 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1433 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1435 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1437 else if ((insn.opcode () == riscv_insn::ADD
1438 || insn.opcode () == riscv_insn::ADDW)
1439 && insn.rd () == RISCV_FP_REGNUM
1440 && insn.rs1 () == RISCV_SP_REGNUM
1441 && insn.rs2 () == RISCV_ZERO_REGNUM)
1443 /* Handle: add s0, sp, 0
1444 or: addw s0, sp, 0 */
1445 /* Instructions setting up the frame pointer. */
1446 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1447 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1448 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1450 else if ((insn.opcode () == riscv_insn::ADDI
1451 && insn.rd () == RISCV_ZERO_REGNUM
1452 && insn.rs1 () == RISCV_ZERO_REGNUM
1453 && insn.imm_signed () == 0))
1455 /* Handle: add x0, x0, 0 (NOP) */
1457 else if (insn.opcode () == riscv_insn::AUIPC)
1459 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1460 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1462 else if (insn.opcode () == riscv_insn::LUI)
1464 /* Handle: lui REG, n
1465 Where REG is not gp register. */
1466 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1467 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1469 else if (insn.opcode () == riscv_insn::ADDI)
1471 /* Handle: addi REG1, REG2, IMM */
1472 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1473 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1475 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1477 else if (insn.opcode () == riscv_insn::ADD)
1479 /* Handle: addi REG1, REG2, IMM */
1480 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1481 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1482 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1483 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1487 end_prologue_addr = cur_pc;
1492 if (end_prologue_addr == 0)
1493 end_prologue_addr = cur_pc;
1495 if (riscv_debug_unwinder)
1496 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1497 core_addr_to_string (end_prologue_addr));
1501 /* Figure out if it is a frame pointer or just a stack pointer. Also
1502 the offset held in the pv_t is from the original register value to
1503 the current value, which for a grows down stack means a negative
1504 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1505 from the current value to the original value. */
1506 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1508 cache->frame_base_reg = RISCV_FP_REGNUM;
1509 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1513 cache->frame_base_reg = RISCV_SP_REGNUM;
1514 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1517 /* Assign offset from old SP to all saved registers. As we don't
1518 have the previous value for the frame base register at this
1519 point, we store the offset as the address in the trad_frame, and
1520 then convert this to an actual address later. */
1521 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1524 if (stack.find_reg (gdbarch, i, &offset))
1526 if (riscv_debug_unwinder)
1527 fprintf_unfiltered (gdb_stdlog,
1528 "Register $%s at stack offset %ld\n",
1529 gdbarch_register_name (gdbarch, i),
1531 trad_frame_set_addr (cache->regs, i, offset);
1536 return end_prologue_addr;
1539 /* Implement the riscv_skip_prologue gdbarch method. */
1542 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1544 CORE_ADDR func_addr;
1546 /* See if we can determine the end of the prologue via the symbol
1547 table. If so, then return either PC, or the PC after the
1548 prologue, whichever is greater. */
1549 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1551 CORE_ADDR post_prologue_pc
1552 = skip_prologue_using_sal (gdbarch, func_addr);
1554 if (post_prologue_pc != 0)
1555 return std::max (pc, post_prologue_pc);
1558 /* Can't determine prologue from the symbol table, need to examine
1559 instructions. Pass -1 for the end address to indicate the prologue
1560 scanner can scan as far as it needs to find the end of the prologue. */
1561 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1564 /* Implement the gdbarch push dummy code callback. */
1567 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1568 CORE_ADDR funaddr, struct value **args, int nargs,
1569 struct type *value_type, CORE_ADDR *real_pc,
1570 CORE_ADDR *bp_addr, struct regcache *regcache)
1572 /* Allocate space for a breakpoint, and keep the stack correctly
1580 /* Compute the alignment of the type T. Used while setting up the
1581 arguments for a dummy call. */
1584 riscv_type_alignment (struct type *t)
1586 t = check_typedef (t);
1587 switch (TYPE_CODE (t))
1590 error (_("Could not compute alignment of type"));
1592 case TYPE_CODE_RVALUE_REF:
1594 case TYPE_CODE_ENUM:
1598 case TYPE_CODE_CHAR:
1599 case TYPE_CODE_BOOL:
1600 return TYPE_LENGTH (t);
1602 case TYPE_CODE_ARRAY:
1603 case TYPE_CODE_COMPLEX:
1604 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1606 case TYPE_CODE_STRUCT:
1607 case TYPE_CODE_UNION:
1612 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1614 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1616 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1626 /* Holds information about a single argument either being passed to an
1627 inferior function, or returned from an inferior function. This includes
1628 information about the size, type, etc of the argument, and also
1629 information about how the argument will be passed (or returned). */
1631 struct riscv_arg_info
1633 /* Contents of the argument. */
1634 const gdb_byte *contents;
1636 /* Length of argument. */
1639 /* Alignment required for an argument of this type. */
1642 /* The type for this argument. */
1645 /* Each argument can have either 1 or 2 locations assigned to it. Each
1646 location describes where part of the argument will be placed. The
1647 second location is valid based on the LOC_TYPE and C_LENGTH fields
1648 of the first location (which is always valid). */
1651 /* What type of location this is. */
1654 /* Argument passed in a register. */
1657 /* Argument passed as an on stack argument. */
1660 /* Argument passed by reference. The second location is always
1661 valid for a BY_REF argument, and describes where the address
1662 of the BY_REF argument should be placed. */
1666 /* Information that depends on the location type. */
1669 /* Which register number to use. */
1672 /* The offset into the stack region. */
1676 /* The length of contents covered by this location. If this is less
1677 than the total length of the argument, then the second location
1678 will be valid, and will describe where the rest of the argument
1682 /* The offset within CONTENTS for this part of the argument. Will
1683 always be 0 for the first part. For the second part of the
1684 argument, this might be the C_LENGTH value of the first part,
1685 however, if we are passing a structure in two registers, and there's
1686 is padding between the first and second field, then this offset
1687 might be greater than the length of the first argument part. When
1688 the second argument location is not holding part of the argument
1689 value, but is instead holding the address of a reference argument,
1690 then this offset will be set to 0. */
1695 /* Information about a set of registers being used for passing arguments as
1696 part of a function call. The register set must be numerically
1697 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1698 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1700 struct riscv_arg_reg
1702 riscv_arg_reg (int first, int last)
1703 : next_regnum (first),
1709 /* The GDB register number to use in this set. */
1712 /* The last GDB register number to use in this set. */
1716 /* Arguments can be passed as on stack arguments, or by reference. The
1717 on stack arguments must be in a continuous region starting from $sp,
1718 while the by reference arguments can be anywhere, but we'll put them
1719 on the stack after (at higher address) the on stack arguments.
1721 This might not be the right approach to take. The ABI is clear that
1722 an argument passed by reference can be modified by the callee, which
1723 us placing the argument (temporarily) onto the stack will not achieve
1724 (changes will be lost). There's also the possibility that very large
1725 arguments could overflow the stack.
1727 This struct is used to track offset into these two areas for where
1728 arguments are to be placed. */
1729 struct riscv_memory_offsets
1731 riscv_memory_offsets ()
1738 /* Offset into on stack argument area. */
1741 /* Offset into the pass by reference area. */
1745 /* Holds information about where arguments to a call will be placed. This
1746 is updated as arguments are added onto the call, and can be used to
1747 figure out where the next argument should be placed. */
1749 struct riscv_call_info
1751 riscv_call_info (struct gdbarch *gdbarch)
1752 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1753 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1755 xlen = riscv_isa_xlen (gdbarch);
1756 flen = riscv_isa_flen (gdbarch);
1758 /* Disable use of floating point registers if needed. */
1759 if (!riscv_has_fp_abi (gdbarch))
1760 float_regs.next_regnum = float_regs.last_regnum + 1;
1763 /* Track the memory areas used for holding in-memory arguments to a
1765 struct riscv_memory_offsets memory;
1767 /* Holds information about the next integer register to use for passing
1769 struct riscv_arg_reg int_regs;
1771 /* Holds information about the next floating point register to use for
1772 passing an argument. */
1773 struct riscv_arg_reg float_regs;
1775 /* The XLEN and FLEN are copied in to this structure for convenience, and
1776 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1781 /* Return the number of registers available for use as parameters in the
1782 register set REG. Returned value can be 0 or more. */
1785 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1787 if (reg->next_regnum > reg->last_regnum)
1790 return (reg->last_regnum - reg->next_regnum + 1);
1793 /* If there is at least one register available in the register set REG then
1794 the next register from REG is assigned to LOC and the length field of
1795 LOC is updated to LENGTH. The register set REG is updated to indicate
1796 that the assigned register is no longer available and the function
1799 If there are no registers available in REG then the function returns
1800 false, and LOC and REG are unchanged. */
1803 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1804 struct riscv_arg_reg *reg,
1805 int length, int offset)
1807 if (reg->next_regnum <= reg->last_regnum)
1809 loc->loc_type = riscv_arg_info::location::in_reg;
1810 loc->loc_data.regno = reg->next_regnum;
1812 loc->c_length = length;
1813 loc->c_offset = offset;
1820 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1821 record that an area of stack has been used to hold the parameter
1824 The length field of LOC is updated to LENGTH, the length of the
1825 parameter being stored, and ALIGN is the alignment required by the
1826 parameter, which will affect how memory is allocated out of MEMORY. */
1829 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1830 struct riscv_memory_offsets *memory,
1831 int length, int align)
1833 loc->loc_type = riscv_arg_info::location::on_stack;
1835 = align_up (memory->arg_offset, align);
1836 loc->loc_data.offset = memory->arg_offset;
1837 memory->arg_offset += length;
1838 loc->c_length = length;
1840 /* Offset is always 0, either we're the first location part, in which
1841 case we're reading content from the start of the argument, or we're
1842 passing the address of a reference argument, so 0. */
1846 /* Update AINFO, which describes an argument that should be passed or
1847 returned using the integer ABI. The argloc fields within AINFO are
1848 updated to describe the location in which the argument will be passed to
1849 a function, or returned from a function.
1851 The CINFO structure contains the ongoing call information, the holds
1852 information such as which argument registers are remaining to be
1853 assigned to parameter, and how much memory has been used by parameters
1856 By examining the state of CINFO a suitable location can be selected,
1857 and assigned to AINFO. */
1860 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1861 struct riscv_call_info *cinfo)
1863 if (ainfo->length > (2 * cinfo->xlen))
1865 /* Argument is going to be passed by reference. */
1866 ainfo->argloc[0].loc_type
1867 = riscv_arg_info::location::by_ref;
1868 cinfo->memory.ref_offset
1869 = align_up (cinfo->memory.ref_offset, ainfo->align);
1870 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1871 cinfo->memory.ref_offset += ainfo->length;
1872 ainfo->argloc[0].c_length = ainfo->length;
1874 /* The second location for this argument is given over to holding the
1875 address of the by-reference data. Pass 0 for the offset as this
1876 is not part of the actual argument value. */
1877 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1880 riscv_assign_stack_location (&ainfo->argloc[1],
1881 &cinfo->memory, cinfo->xlen,
1886 int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length;
1888 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1889 &cinfo->int_regs, len, 0))
1890 riscv_assign_stack_location (&ainfo->argloc[0],
1891 &cinfo->memory, len, ainfo->align);
1893 if (len < ainfo->length)
1895 len = ainfo->length - len;
1896 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1897 &cinfo->int_regs, len,
1899 riscv_assign_stack_location (&ainfo->argloc[1],
1900 &cinfo->memory, len, cinfo->xlen);
1905 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1906 is being passed with the floating point ABI. */
1909 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1910 struct riscv_call_info *cinfo)
1912 if (ainfo->length > cinfo->flen)
1913 return riscv_call_arg_scalar_int (ainfo, cinfo);
1916 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1919 return riscv_call_arg_scalar_int (ainfo, cinfo);
1923 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1924 is a complex floating point argument, and is therefore handled
1925 differently to other argument types. */
1928 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1929 struct riscv_call_info *cinfo)
1931 if (ainfo->length <= (2 * cinfo->flen)
1932 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1935 int len = ainfo->length / 2;
1937 result = riscv_assign_reg_location (&ainfo->argloc[0],
1938 &cinfo->float_regs, len, len);
1939 gdb_assert (result);
1941 result = riscv_assign_reg_location (&ainfo->argloc[1],
1942 &cinfo->float_regs, len, len);
1943 gdb_assert (result);
1946 return riscv_call_arg_scalar_int (ainfo, cinfo);
1949 /* A structure used for holding information about a structure type within
1950 the inferior program. The RiscV ABI has special rules for handling some
1951 structures with a single field or with two fields. The counting of
1952 fields here is done after flattening out all nested structures. */
1954 class riscv_struct_info
1957 riscv_struct_info ()
1958 : m_number_of_fields (0),
1959 m_types { nullptr, nullptr }
1964 /* Analyse TYPE descending into nested structures, count the number of
1965 scalar fields and record the types of the first two fields found. */
1966 void analyse (struct type *type);
1968 /* The number of scalar fields found in the analysed type. This is
1969 currently only accurate if the value returned is 0, 1, or 2 as the
1970 analysis stops counting when the number of fields is 3. This is
1971 because the RiscV ABI only has special cases for 1 or 2 fields,
1972 anything else we just don't care about. */
1973 int number_of_fields () const
1974 { return m_number_of_fields; }
1976 /* Return the type for scalar field INDEX within the analysed type. Will
1977 return nullptr if there is no field at that index. Only INDEX values
1978 0 and 1 can be requested as the RiscV ABI only has special cases for
1979 structures with 1 or 2 fields. */
1980 struct type *field_type (int index) const
1982 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
1983 return m_types[index];
1987 /* The number of scalar fields found within the structure after recursing
1988 into nested structures. */
1989 int m_number_of_fields;
1991 /* The types of the first two scalar fields found within the structure
1992 after recursing into nested structures. */
1993 struct type *m_types[2];
1996 /* Analyse TYPE descending into nested structures, count the number of
1997 scalar fields and record the types of the first two fields found. */
2000 riscv_struct_info::analyse (struct type *type)
2002 unsigned int count = TYPE_NFIELDS (type);
2005 for (i = 0; i < count; ++i)
2007 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
2010 struct type *field_type = TYPE_FIELD_TYPE (type, i);
2011 field_type = check_typedef (field_type);
2013 switch (TYPE_CODE (field_type))
2015 case TYPE_CODE_STRUCT:
2016 analyse (field_type);
2020 /* RiscV only flattens out structures. Anything else does not
2021 need to be flattened, we just record the type, and when we
2022 look at the analysis results we'll realise this is not a
2023 structure we can special case, and pass the structure in
2025 if (m_number_of_fields < 2)
2026 m_types[m_number_of_fields] = field_type;
2027 m_number_of_fields++;
2031 /* RiscV only has special handling for structures with 1 or 2 scalar
2032 fields, any more than that and the structure is just passed in
2033 memory. We can safely drop out early when we find 3 or more
2036 if (m_number_of_fields > 2)
2041 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2042 is a structure. Small structures on RiscV have some special case
2043 handling in order that the structure might be passed in register.
2044 Larger structures are passed in memory. After assigning location
2045 information to AINFO, CINFO will have been updated. */
2048 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
2049 struct riscv_call_info *cinfo)
2051 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2053 struct riscv_struct_info sinfo;
2055 sinfo.analyse (ainfo->type);
2056 if (sinfo.number_of_fields () == 1
2057 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
2059 gdb_assert (TYPE_LENGTH (ainfo->type)
2060 == TYPE_LENGTH (sinfo.field_type (0)));
2061 return riscv_call_arg_complex_float (ainfo, cinfo);
2064 if (sinfo.number_of_fields () == 1
2065 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
2067 gdb_assert (TYPE_LENGTH (ainfo->type)
2068 == TYPE_LENGTH (sinfo.field_type (0)));
2069 return riscv_call_arg_scalar_float (ainfo, cinfo);
2072 if (sinfo.number_of_fields () == 2
2073 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2074 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2075 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2076 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
2077 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2079 int len0, len1, offset;
2081 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
2083 len0 = TYPE_LENGTH (sinfo.field_type (0));
2084 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2085 &cinfo->float_regs, len0, 0))
2086 error (_("failed during argument setup"));
2088 len1 = TYPE_LENGTH (sinfo.field_type (1));
2089 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2090 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2091 - TYPE_LENGTH (sinfo.field_type (0))));
2093 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2096 error (_("failed during argument setup"));
2100 if (sinfo.number_of_fields () == 2
2101 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2102 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2103 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2104 && is_integral_type (sinfo.field_type (1))
2105 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2107 int len0, len1, offset;
2109 gdb_assert (TYPE_LENGTH (ainfo->type)
2110 <= (cinfo->flen + cinfo->xlen));
2112 len0 = TYPE_LENGTH (sinfo.field_type (0));
2113 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2114 &cinfo->float_regs, len0, 0))
2115 error (_("failed during argument setup"));
2117 len1 = TYPE_LENGTH (sinfo.field_type (1));
2118 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2119 gdb_assert (len1 <= cinfo->xlen);
2120 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2121 &cinfo->int_regs, len1, offset))
2122 error (_("failed during argument setup"));
2126 if (sinfo.number_of_fields () == 2
2127 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2128 && (is_integral_type (sinfo.field_type (0))
2129 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2130 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2131 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2133 int len0, len1, offset;
2135 gdb_assert (TYPE_LENGTH (ainfo->type)
2136 <= (cinfo->flen + cinfo->xlen));
2138 len0 = TYPE_LENGTH (sinfo.field_type (0));
2139 len1 = TYPE_LENGTH (sinfo.field_type (1));
2140 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2142 gdb_assert (len0 <= cinfo->xlen);
2143 gdb_assert (len1 <= cinfo->flen);
2145 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2146 &cinfo->int_regs, len0, 0))
2147 error (_("failed during argument setup"));
2149 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2152 error (_("failed during argument setup"));
2158 /* Non of the structure flattening cases apply, so we just pass using
2160 ainfo->length = align_up (ainfo->length, cinfo->xlen);
2161 riscv_call_arg_scalar_int (ainfo, cinfo);
2164 /* Assign a location to call (or return) argument AINFO, the location is
2165 selected from CINFO which holds information about what call argument
2166 locations are available for use next. The TYPE is the type of the
2167 argument being passed, this information is recorded into AINFO (along
2168 with some additional information derived from the type).
2170 After assigning a location to AINFO, CINFO will have been updated. */
2173 riscv_arg_location (struct gdbarch *gdbarch,
2174 struct riscv_arg_info *ainfo,
2175 struct riscv_call_info *cinfo,
2179 ainfo->length = TYPE_LENGTH (ainfo->type);
2180 ainfo->align = riscv_type_alignment (ainfo->type);
2181 ainfo->contents = nullptr;
2183 switch (TYPE_CODE (ainfo->type))
2186 case TYPE_CODE_BOOL:
2187 case TYPE_CODE_CHAR:
2188 case TYPE_CODE_RANGE:
2189 case TYPE_CODE_ENUM:
2191 if (ainfo->length <= cinfo->xlen)
2193 ainfo->type = builtin_type (gdbarch)->builtin_long;
2194 ainfo->length = cinfo->xlen;
2196 else if (ainfo->length <= (2 * cinfo->xlen))
2198 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2199 ainfo->length = 2 * cinfo->xlen;
2202 /* Recalculate the alignment requirement. */
2203 ainfo->align = riscv_type_alignment (ainfo->type);
2204 riscv_call_arg_scalar_int (ainfo, cinfo);
2208 riscv_call_arg_scalar_float (ainfo, cinfo);
2211 case TYPE_CODE_COMPLEX:
2212 riscv_call_arg_complex_float (ainfo, cinfo);
2215 case TYPE_CODE_STRUCT:
2216 riscv_call_arg_struct (ainfo, cinfo);
2220 riscv_call_arg_scalar_int (ainfo, cinfo);
2225 /* Used for printing debug information about the call argument location in
2226 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2227 addresses for the location of pass-by-reference and
2228 arguments-on-the-stack memory areas. */
2231 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2232 struct riscv_arg_info *info,
2233 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2235 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2236 TYPE_SAFE_NAME (info->type), info->length, info->align);
2237 switch (info->argloc[0].loc_type)
2239 case riscv_arg_info::location::in_reg:
2241 (stream, ", register %s",
2242 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2243 if (info->argloc[0].c_length < info->length)
2245 switch (info->argloc[1].loc_type)
2247 case riscv_arg_info::location::in_reg:
2249 (stream, ", register %s",
2250 gdbarch_register_name (gdbarch,
2251 info->argloc[1].loc_data.regno));
2254 case riscv_arg_info::location::on_stack:
2255 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2256 info->argloc[1].loc_data.offset);
2259 case riscv_arg_info::location::by_ref:
2261 /* The second location should never be a reference, any
2262 argument being passed by reference just places its address
2263 in the first location and is done. */
2264 error (_("invalid argument location"));
2268 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2269 fprintf_unfiltered (stream, " (offset 0x%x)",
2270 info->argloc[1].c_offset);
2274 case riscv_arg_info::location::on_stack:
2275 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2276 info->argloc[0].loc_data.offset);
2279 case riscv_arg_info::location::by_ref:
2281 (stream, ", by reference, data at offset 0x%x (%s)",
2282 info->argloc[0].loc_data.offset,
2283 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2284 if (info->argloc[1].loc_type
2285 == riscv_arg_info::location::in_reg)
2287 (stream, ", address in register %s",
2288 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2291 gdb_assert (info->argloc[1].loc_type
2292 == riscv_arg_info::location::on_stack);
2294 (stream, ", address on stack at offset 0x%x (%s)",
2295 info->argloc[1].loc_data.offset,
2296 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2301 gdb_assert_not_reached (_("unknown argument location type"));
2305 /* Implement the push dummy call gdbarch callback. */
2308 riscv_push_dummy_call (struct gdbarch *gdbarch,
2309 struct value *function,
2310 struct regcache *regcache,
2313 struct value **args,
2316 CORE_ADDR struct_addr)
2319 CORE_ADDR sp_args, sp_refs;
2320 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2322 struct riscv_arg_info *arg_info =
2323 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2325 struct riscv_call_info call_info (gdbarch);
2329 /* We'll use register $a0 if we're returning a struct. */
2331 ++call_info.int_regs.next_regnum;
2333 for (i = 0; i < nargs; ++i)
2335 struct value *arg_value;
2336 struct type *arg_type;
2337 struct riscv_arg_info *info = &arg_info[i];
2339 arg_value = args[i];
2340 arg_type = check_typedef (value_type (arg_value));
2342 riscv_arg_location (gdbarch, info, &call_info, arg_type);
2344 if (info->type != arg_type)
2345 arg_value = value_cast (info->type, arg_value);
2346 info->contents = value_contents (arg_value);
2349 /* Adjust the stack pointer and align it. */
2350 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2351 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2353 if (riscv_debug_infcall > 0)
2355 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2356 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2357 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2358 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2359 call_info.xlen, call_info.flen);
2361 fprintf_unfiltered (gdb_stdlog,
2362 "[*] struct return pointer in register $A0\n");
2363 for (i = 0; i < nargs; ++i)
2365 struct riscv_arg_info *info = &arg_info [i];
2367 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2368 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2369 fprintf_unfiltered (gdb_stdlog, "\n");
2371 if (call_info.memory.arg_offset > 0
2372 || call_info.memory.ref_offset > 0)
2374 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2375 core_addr_to_string (osp));
2376 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2377 call_info.memory.arg_offset);
2378 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2379 call_info.memory.ref_offset);
2380 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2381 core_addr_to_string_nz (osp - sp));
2385 /* Now load the argument into registers, or onto the stack. */
2389 gdb_byte buf[sizeof (LONGEST)];
2391 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2392 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2395 for (i = 0; i < nargs; ++i)
2398 int second_arg_length = 0;
2399 const gdb_byte *second_arg_data;
2400 struct riscv_arg_info *info = &arg_info [i];
2402 gdb_assert (info->length > 0);
2404 switch (info->argloc[0].loc_type)
2406 case riscv_arg_info::location::in_reg:
2408 gdb_byte tmp [sizeof (ULONGEST)];
2410 gdb_assert (info->argloc[0].c_length <= info->length);
2411 memset (tmp, 0, sizeof (tmp));
2412 memcpy (tmp, info->contents, info->argloc[0].c_length);
2413 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2415 ((info->argloc[0].c_length < info->length)
2416 ? info->argloc[1].c_length : 0);
2417 second_arg_data = info->contents + info->argloc[1].c_offset;
2421 case riscv_arg_info::location::on_stack:
2422 dst = sp_args + info->argloc[0].loc_data.offset;
2423 write_memory (dst, info->contents, info->length);
2424 second_arg_length = 0;
2427 case riscv_arg_info::location::by_ref:
2428 dst = sp_refs + info->argloc[0].loc_data.offset;
2429 write_memory (dst, info->contents, info->length);
2431 second_arg_length = call_info.xlen;
2432 second_arg_data = (gdb_byte *) &dst;
2436 gdb_assert_not_reached (_("unknown argument location type"));
2439 if (second_arg_length > 0)
2441 switch (info->argloc[1].loc_type)
2443 case riscv_arg_info::location::in_reg:
2445 gdb_byte tmp [sizeof (ULONGEST)];
2447 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2448 && second_arg_length <= call_info.flen)
2449 || second_arg_length <= call_info.xlen);
2450 memset (tmp, 0, sizeof (tmp));
2451 memcpy (tmp, second_arg_data, second_arg_length);
2452 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2456 case riscv_arg_info::location::on_stack:
2460 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2461 write_memory (arg_addr, second_arg_data, second_arg_length);
2465 case riscv_arg_info::location::by_ref:
2467 /* The second location should never be a reference, any
2468 argument being passed by reference just places its address
2469 in the first location and is done. */
2470 error (_("invalid argument location"));
2476 /* Set the dummy return value to bp_addr.
2477 A dummy breakpoint will be setup to execute the call. */
2479 if (riscv_debug_infcall > 0)
2480 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2481 core_addr_to_string (bp_addr));
2482 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2484 /* Finally, update the stack pointer. */
2486 if (riscv_debug_infcall > 0)
2487 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2488 core_addr_to_string (sp));
2489 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2494 /* Implement the return_value gdbarch method. */
2496 static enum return_value_convention
2497 riscv_return_value (struct gdbarch *gdbarch,
2498 struct value *function,
2500 struct regcache *regcache,
2502 const gdb_byte *writebuf)
2504 struct riscv_call_info call_info (gdbarch);
2505 struct riscv_arg_info info;
2506 struct type *arg_type;
2508 arg_type = check_typedef (type);
2509 riscv_arg_location (gdbarch, &info, &call_info, arg_type);
2511 if (riscv_debug_infcall > 0)
2513 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2514 fprintf_unfiltered (gdb_stdlog, "[R] ");
2515 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2516 fprintf_unfiltered (gdb_stdlog, "\n");
2519 if (readbuf != nullptr || writebuf != nullptr)
2523 switch (info.argloc[0].loc_type)
2525 /* Return value in register(s). */
2526 case riscv_arg_info::location::in_reg:
2528 regnum = info.argloc[0].loc_data.regno;
2531 regcache->cooked_read (regnum, readbuf);
2534 regcache->cooked_write (regnum, writebuf);
2536 /* A return value in register can have a second part in a
2538 if (info.argloc[0].c_length < info.length)
2540 switch (info.argloc[1].loc_type)
2542 case riscv_arg_info::location::in_reg:
2543 regnum = info.argloc[1].loc_data.regno;
2547 readbuf += info.argloc[1].c_offset;
2548 regcache->cooked_read (regnum, readbuf);
2553 writebuf += info.argloc[1].c_offset;
2554 regcache->cooked_write (regnum, writebuf);
2558 case riscv_arg_info::location::by_ref:
2559 case riscv_arg_info::location::on_stack:
2561 error (_("invalid argument location"));
2568 /* Return value by reference will have its address in A0. */
2569 case riscv_arg_info::location::by_ref:
2573 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2575 if (readbuf != nullptr)
2576 read_memory (addr, readbuf, info.length);
2577 if (writebuf != nullptr)
2578 write_memory (addr, writebuf, info.length);
2582 case riscv_arg_info::location::on_stack:
2584 error (_("invalid argument location"));
2589 switch (info.argloc[0].loc_type)
2591 case riscv_arg_info::location::in_reg:
2592 return RETURN_VALUE_REGISTER_CONVENTION;
2593 case riscv_arg_info::location::by_ref:
2594 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2595 case riscv_arg_info::location::on_stack:
2597 error (_("invalid argument location"));
2601 /* Implement the frame_align gdbarch method. */
2604 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2606 return align_down (addr, 16);
2609 /* Implement the unwind_pc gdbarch method. */
2612 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2614 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2617 /* Implement the unwind_sp gdbarch method. */
2620 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2622 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2625 /* Implement the dummy_id gdbarch method. */
2627 static struct frame_id
2628 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2630 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2631 get_frame_pc (this_frame));
2634 /* Generate, or return the cached frame cache for the RiscV frame
2637 static struct riscv_unwind_cache *
2638 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2640 CORE_ADDR pc, start_addr;
2641 struct riscv_unwind_cache *cache;
2642 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2645 if ((*this_cache) != NULL)
2646 return (struct riscv_unwind_cache *) *this_cache;
2648 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2649 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2650 (*this_cache) = cache;
2652 /* Scan the prologue, filling in the cache. */
2653 start_addr = get_frame_func (this_frame);
2654 pc = get_frame_pc (this_frame);
2655 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2657 /* We can now calculate the frame base address. */
2659 = (get_frame_register_signed (this_frame, cache->frame_base_reg)
2660 + cache->frame_base_offset);
2661 if (riscv_debug_unwinder)
2662 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2663 core_addr_to_string (cache->frame_base),
2664 gdbarch_register_name (gdbarch,
2665 cache->frame_base_reg),
2666 cache->frame_base_offset);
2668 /* The prologue scanner sets the address of registers stored to the stack
2669 as the offset of that register from the frame base. The prologue
2670 scanner doesn't know the actual frame base value, and so is unable to
2671 compute the exact address. We do now know the frame base value, so
2672 update the address of registers stored to the stack. */
2673 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2674 for (regno = 0; regno < numregs; ++regno)
2676 if (trad_frame_addr_p (cache->regs, regno))
2677 cache->regs[regno].addr += cache->frame_base;
2680 /* The previous $pc can be found wherever the $ra value can be found.
2681 The previous $ra value is gone, this would have been stored be the
2682 previous frame if required. */
2683 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2684 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2686 /* Build the frame id. */
2687 cache->this_id = frame_id_build (cache->frame_base, start_addr);
2689 /* The previous $sp value is the frame base value. */
2690 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2696 /* Implement the this_id callback for RiscV frame unwinder. */
2699 riscv_frame_this_id (struct frame_info *this_frame,
2700 void **prologue_cache,
2701 struct frame_id *this_id)
2703 struct riscv_unwind_cache *cache;
2705 cache = riscv_frame_cache (this_frame, prologue_cache);
2706 *this_id = cache->this_id;
2709 /* Implement the prev_register callback for RiscV frame unwinder. */
2711 static struct value *
2712 riscv_frame_prev_register (struct frame_info *this_frame,
2713 void **prologue_cache,
2716 struct riscv_unwind_cache *cache;
2718 cache = riscv_frame_cache (this_frame, prologue_cache);
2719 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
2722 /* Structure defining the RiscV normal frame unwind functions. Since we
2723 are the fallback unwinder (DWARF unwinder is used first), we use the
2724 default frame sniffer, which always accepts the frame. */
2726 static const struct frame_unwind riscv_frame_unwind =
2728 /*.type =*/ NORMAL_FRAME,
2729 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2730 /*.this_id =*/ riscv_frame_this_id,
2731 /*.prev_register =*/ riscv_frame_prev_register,
2732 /*.unwind_data =*/ NULL,
2733 /*.sniffer =*/ default_frame_sniffer,
2734 /*.dealloc_cache =*/ NULL,
2735 /*.prev_arch =*/ NULL,
2738 /* Initialize the current architecture based on INFO. If possible,
2739 re-use an architecture from ARCHES, which is a list of
2740 architectures already created during this debugging session.
2742 Called e.g. at program startup, when reading a core file, and when
2743 reading a binary file. */
2745 static struct gdbarch *
2746 riscv_gdbarch_init (struct gdbarch_info info,
2747 struct gdbarch_list *arches)
2749 struct gdbarch *gdbarch;
2750 struct gdbarch_tdep *tdep;
2751 struct gdbarch_tdep tmp_tdep;
2754 /* Ideally, we'd like to get as much information from the target for
2755 things like register size, and whether the target has floating point
2756 hardware. However, there are some things that the target can't tell
2757 us, like, what ABI is being used.
2759 So, for now, we take as much information as possible from the ELF,
2760 including things like register size, and FP hardware support, along
2761 with information about the ABI.
2763 Information about this target is built up in TMP_TDEP, and then we
2764 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2765 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2766 memset (&tmp_tdep, 0, sizeof (tmp_tdep));
2768 if (info.abfd != NULL
2769 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2771 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2772 int e_flags = elf_elfheader (info.abfd)->e_flags;
2774 if (eclass == ELFCLASS32)
2775 tmp_tdep.abi.fields.base_len = 1;
2776 else if (eclass == ELFCLASS64)
2777 tmp_tdep.abi.fields.base_len = 2;
2779 internal_error (__FILE__, __LINE__,
2780 _("unknown ELF header class %d"), eclass);
2782 if (e_flags & EF_RISCV_RVC)
2783 tmp_tdep.core_features |= (1 << ('C' - 'A'));
2785 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2787 tmp_tdep.abi.fields.float_abi = 2;
2788 tmp_tdep.core_features |= (1 << ('D' - 'A'));
2789 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2791 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2793 tmp_tdep.abi.fields.float_abi = 1;
2794 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2799 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2801 if (binfo->bits_per_word == 32)
2802 tmp_tdep.abi.fields.base_len = 1;
2803 else if (binfo->bits_per_word == 64)
2804 tmp_tdep.abi.fields.base_len = 2;
2806 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2807 binfo->bits_per_word);
2810 /* Find a candidate among the list of pre-declared architectures. */
2811 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2813 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2814 if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
2815 return arches->gdbarch;
2817 /* None found, so create a new architecture from the information provided. */
2818 tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
2819 gdbarch = gdbarch_alloc (&info, tdep);
2820 memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep));
2822 /* Target data types. */
2823 set_gdbarch_short_bit (gdbarch, 16);
2824 set_gdbarch_int_bit (gdbarch, 32);
2825 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2826 set_gdbarch_long_long_bit (gdbarch, 64);
2827 set_gdbarch_float_bit (gdbarch, 32);
2828 set_gdbarch_double_bit (gdbarch, 64);
2829 set_gdbarch_long_double_bit (gdbarch, 128);
2830 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2831 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2832 set_gdbarch_char_signed (gdbarch, 0);
2834 /* Information about the target architecture. */
2835 set_gdbarch_return_value (gdbarch, riscv_return_value);
2836 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
2837 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
2839 /* Register architecture. */
2840 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
2841 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
2842 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
2843 set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
2844 set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
2846 /* Functions to supply register information. */
2847 set_gdbarch_register_name (gdbarch, riscv_register_name);
2848 set_gdbarch_register_type (gdbarch, riscv_register_type);
2849 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
2850 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
2852 /* Functions to analyze frames. */
2853 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
2854 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2855 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
2857 /* Functions to access frame data. */
2858 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
2859 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
2861 /* Functions handling dummy frames. */
2862 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2863 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
2864 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
2865 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
2867 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2869 dwarf2_append_unwinders (gdbarch);
2870 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
2872 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
2873 user_reg_add (gdbarch, riscv_register_aliases[i].name,
2874 value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
2876 /* Hook in OS ABI-specific overrides, if they have been registered. */
2877 gdbarch_init_osabi (info, gdbarch);
2882 /* This decodes the current instruction and determines the address of the
2883 next instruction. */
2886 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
2888 struct gdbarch *gdbarch = regcache->arch ();
2889 struct riscv_insn insn;
2892 insn.decode (gdbarch, pc);
2893 next_pc = pc + insn.length ();
2895 if (insn.opcode () == riscv_insn::JAL)
2896 next_pc = pc + insn.imm_signed ();
2897 else if (insn.opcode () == riscv_insn::JALR)
2900 regcache->cooked_read (insn.rs1 (), &source);
2901 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
2903 else if (insn.opcode () == riscv_insn::BEQ)
2906 regcache->cooked_read (insn.rs1 (), &src1);
2907 regcache->cooked_read (insn.rs2 (), &src2);
2909 next_pc = pc + insn.imm_signed ();
2911 else if (insn.opcode () == riscv_insn::BNE)
2914 regcache->cooked_read (insn.rs1 (), &src1);
2915 regcache->cooked_read (insn.rs2 (), &src2);
2917 next_pc = pc + insn.imm_signed ();
2919 else if (insn.opcode () == riscv_insn::BLT)
2922 regcache->cooked_read (insn.rs1 (), &src1);
2923 regcache->cooked_read (insn.rs2 (), &src2);
2925 next_pc = pc + insn.imm_signed ();
2927 else if (insn.opcode () == riscv_insn::BGE)
2930 regcache->cooked_read (insn.rs1 (), &src1);
2931 regcache->cooked_read (insn.rs2 (), &src2);
2933 next_pc = pc + insn.imm_signed ();
2935 else if (insn.opcode () == riscv_insn::BLTU)
2937 ULONGEST src1, src2;
2938 regcache->cooked_read (insn.rs1 (), &src1);
2939 regcache->cooked_read (insn.rs2 (), &src2);
2941 next_pc = pc + insn.imm_signed ();
2943 else if (insn.opcode () == riscv_insn::BGEU)
2945 ULONGEST src1, src2;
2946 regcache->cooked_read (insn.rs1 (), &src1);
2947 regcache->cooked_read (insn.rs2 (), &src2);
2949 next_pc = pc + insn.imm_signed ();
2955 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
2956 for the end of the sequence and put the breakpoint there. */
2959 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
2962 struct gdbarch *gdbarch = regcache->arch ();
2963 struct riscv_insn insn;
2964 CORE_ADDR cur_step_pc = pc;
2965 CORE_ADDR last_addr = 0;
2967 /* First instruction has to be a load reserved. */
2968 insn.decode (gdbarch, cur_step_pc);
2969 if (insn.opcode () != riscv_insn::LR)
2971 cur_step_pc = cur_step_pc + insn.length ();
2973 /* Next instruction should be branch to exit. */
2974 insn.decode (gdbarch, cur_step_pc);
2975 if (insn.opcode () != riscv_insn::BNE)
2977 last_addr = cur_step_pc + insn.imm_signed ();
2978 cur_step_pc = cur_step_pc + insn.length ();
2980 /* Next instruction should be store conditional. */
2981 insn.decode (gdbarch, cur_step_pc);
2982 if (insn.opcode () != riscv_insn::SC)
2984 cur_step_pc = cur_step_pc + insn.length ();
2986 /* Next instruction should be branch to start. */
2987 insn.decode (gdbarch, cur_step_pc);
2988 if (insn.opcode () != riscv_insn::BNE)
2990 if (pc != (cur_step_pc + insn.imm_signed ()))
2992 cur_step_pc = cur_step_pc + insn.length ();
2994 /* We should now be at the end of the sequence. */
2995 if (cur_step_pc != last_addr)
2998 *next_pc = cur_step_pc;
3002 /* This is called just before we want to resume the inferior, if we want to
3003 single-step it but there is no hardware or kernel single-step support. We
3004 find the target of the coming instruction and breakpoint it. */
3006 std::vector<CORE_ADDR>
3007 riscv_software_single_step (struct regcache *regcache)
3009 CORE_ADDR pc, next_pc;
3011 pc = regcache_read_pc (regcache);
3013 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
3016 next_pc = riscv_next_pc (regcache, pc);
3022 _initialize_riscv_tdep (void)
3024 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
3026 /* Add root prefix command for all "set debug riscv" and "show debug
3028 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
3029 _("RISC-V specific debug commands."),
3030 &setdebugriscvcmdlist, "set debug riscv ", 0,
3033 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
3034 _("RISC-V specific debug commands."),
3035 &showdebugriscvcmdlist, "show debug riscv ", 0,
3038 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
3039 &riscv_debug_breakpoints, _("\
3040 Set riscv breakpoint debugging."), _("\
3041 Show riscv breakpoint debugging."), _("\
3042 When non-zero, print debugging information for the riscv specific parts\n\
3043 of the breakpoint mechanism."),
3045 show_riscv_debug_variable,
3046 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3048 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
3049 &riscv_debug_infcall, _("\
3050 Set riscv inferior call debugging."), _("\
3051 Show riscv inferior call debugging."), _("\
3052 When non-zero, print debugging information for the riscv specific parts\n\
3053 of the inferior call mechanism."),
3055 show_riscv_debug_variable,
3056 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3058 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
3059 &riscv_debug_unwinder, _("\
3060 Set riscv stack unwinding debugging."), _("\
3061 Show riscv stack unwinding debugging."), _("\
3062 When non-zero, print debugging information for the riscv specific parts\n\
3063 of the stack unwinding mechanism."),
3065 show_riscv_debug_variable,
3066 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3068 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3069 add_prefix_cmd ("riscv", no_class, set_riscv_command,
3070 _("RISC-V specific commands."),
3071 &setriscvcmdlist, "set riscv ", 0, &setlist);
3073 add_prefix_cmd ("riscv", no_class, show_riscv_command,
3074 _("RISC-V specific commands."),
3075 &showriscvcmdlist, "show riscv ", 0, &showlist);
3078 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
3079 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
3080 &use_compressed_breakpoints,
3082 Set debugger's use of compressed breakpoints."), _(" \
3083 Show debugger's use of compressed breakpoints."), _("\
3084 Debugging compressed code requires compressed breakpoints to be used. If\n\
3085 left to 'auto' then gdb will use them if the existing instruction is a\n\
3086 compressed instruction. If that doesn't give the correct behavior, then\n\
3087 this option can be used."),
3089 show_use_compressed_breakpoints,