1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
59 /* The stack must be 16-byte aligned. */
60 #define SP_ALIGNMENT 16
62 /* Forward declarations. */
63 static bool riscv_has_feature (struct gdbarch *gdbarch, char feature);
65 /* Define a series of is_XXX_insn functions to check if the value INSN
66 is an instance of instruction XXX. */
67 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
68 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
70 return (insn & INSN_MASK) == INSN_MATCH; \
72 #include "opcode/riscv-opc.h"
75 /* Cached information about a frame. */
77 struct riscv_unwind_cache
79 /* The register from which we can calculate the frame base. This is
80 usually $sp or $fp. */
83 /* The offset from the current value in register FRAME_BASE_REG to the
84 actual frame base address. */
85 int frame_base_offset;
87 /* Information about previous register values. */
88 struct trad_frame_saved_reg *regs;
90 /* The id for this frame. */
91 struct frame_id this_id;
93 /* The base (stack) address for this frame. This is the stack pointer
94 value on entry to this frame before any adjustments are made. */
98 /* The preferred register names for all the general purpose and floating
99 point registers. These are what GDB will use when referencing a
102 static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
104 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1",
105 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4",
106 "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
108 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
109 "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3",
110 "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9",
114 /* Map alternative register names onto their GDB register number. */
116 struct riscv_register_alias
118 /* The register alias. Usually more descriptive than the
119 architectural name of the register. */
122 /* The GDB register number. */
126 /* Table of register aliases. */
128 static const struct riscv_register_alias riscv_register_aliases[] =
130 /* Aliases for general purpose registers. These are the architectural
131 names, as GDB uses the more user friendly names by default. */
132 { "x0", (RISCV_ZERO_REGNUM + 0) },
133 { "x1", (RISCV_ZERO_REGNUM + 1) },
134 { "x2", (RISCV_ZERO_REGNUM + 2) },
135 { "x3", (RISCV_ZERO_REGNUM + 3) },
136 { "x4", (RISCV_ZERO_REGNUM + 4) },
137 { "x5", (RISCV_ZERO_REGNUM + 5) },
138 { "x6", (RISCV_ZERO_REGNUM + 6) },
139 { "x7", (RISCV_ZERO_REGNUM + 7) },
140 { "x8", (RISCV_ZERO_REGNUM + 8) },
141 { "s0", (RISCV_ZERO_REGNUM + 8) }, /* fp, s0, and x8 are all aliases. */
142 { "x9", (RISCV_ZERO_REGNUM + 9) },
143 { "x10", (RISCV_ZERO_REGNUM + 10) },
144 { "x11", (RISCV_ZERO_REGNUM + 11) },
145 { "x12", (RISCV_ZERO_REGNUM + 12) },
146 { "x13", (RISCV_ZERO_REGNUM + 13) },
147 { "x14", (RISCV_ZERO_REGNUM + 14) },
148 { "x15", (RISCV_ZERO_REGNUM + 15) },
149 { "x16", (RISCV_ZERO_REGNUM + 16) },
150 { "x17", (RISCV_ZERO_REGNUM + 17) },
151 { "x18", (RISCV_ZERO_REGNUM + 18) },
152 { "x19", (RISCV_ZERO_REGNUM + 19) },
153 { "x20", (RISCV_ZERO_REGNUM + 20) },
154 { "x21", (RISCV_ZERO_REGNUM + 21) },
155 { "x22", (RISCV_ZERO_REGNUM + 22) },
156 { "x23", (RISCV_ZERO_REGNUM + 23) },
157 { "x24", (RISCV_ZERO_REGNUM + 24) },
158 { "x25", (RISCV_ZERO_REGNUM + 25) },
159 { "x26", (RISCV_ZERO_REGNUM + 26) },
160 { "x27", (RISCV_ZERO_REGNUM + 27) },
161 { "x28", (RISCV_ZERO_REGNUM + 28) },
162 { "x29", (RISCV_ZERO_REGNUM + 29) },
163 { "x30", (RISCV_ZERO_REGNUM + 30) },
164 { "x31", (RISCV_ZERO_REGNUM + 31) },
166 /* Aliases for the floating-point registers. These are the architectural
167 names as GDB uses the more user friendly names by default. */
168 { "f0", (RISCV_FIRST_FP_REGNUM + 0) },
169 { "f1", (RISCV_FIRST_FP_REGNUM + 1) },
170 { "f2", (RISCV_FIRST_FP_REGNUM + 2) },
171 { "f3", (RISCV_FIRST_FP_REGNUM + 3) },
172 { "f4", (RISCV_FIRST_FP_REGNUM + 4) },
173 { "f5", (RISCV_FIRST_FP_REGNUM + 5) },
174 { "f6", (RISCV_FIRST_FP_REGNUM + 6) },
175 { "f7", (RISCV_FIRST_FP_REGNUM + 7) },
176 { "f8", (RISCV_FIRST_FP_REGNUM + 8) },
177 { "f9", (RISCV_FIRST_FP_REGNUM + 9) },
178 { "f10", (RISCV_FIRST_FP_REGNUM + 10) },
179 { "f11", (RISCV_FIRST_FP_REGNUM + 11) },
180 { "f12", (RISCV_FIRST_FP_REGNUM + 12) },
181 { "f13", (RISCV_FIRST_FP_REGNUM + 13) },
182 { "f14", (RISCV_FIRST_FP_REGNUM + 14) },
183 { "f15", (RISCV_FIRST_FP_REGNUM + 15) },
184 { "f16", (RISCV_FIRST_FP_REGNUM + 16) },
185 { "f17", (RISCV_FIRST_FP_REGNUM + 17) },
186 { "f18", (RISCV_FIRST_FP_REGNUM + 18) },
187 { "f19", (RISCV_FIRST_FP_REGNUM + 19) },
188 { "f20", (RISCV_FIRST_FP_REGNUM + 20) },
189 { "f21", (RISCV_FIRST_FP_REGNUM + 21) },
190 { "f22", (RISCV_FIRST_FP_REGNUM + 22) },
191 { "f23", (RISCV_FIRST_FP_REGNUM + 23) },
192 { "f24", (RISCV_FIRST_FP_REGNUM + 24) },
193 { "f25", (RISCV_FIRST_FP_REGNUM + 25) },
194 { "f26", (RISCV_FIRST_FP_REGNUM + 26) },
195 { "f27", (RISCV_FIRST_FP_REGNUM + 27) },
196 { "f28", (RISCV_FIRST_FP_REGNUM + 28) },
197 { "f29", (RISCV_FIRST_FP_REGNUM + 29) },
198 { "f30", (RISCV_FIRST_FP_REGNUM + 30) },
199 { "f31", (RISCV_FIRST_FP_REGNUM + 31) },
202 /* Controls whether we place compressed breakpoints or not. When in auto
203 mode GDB tries to determine if the target supports compressed
204 breakpoints, and uses them if it does. */
206 static enum auto_boolean use_compressed_breakpoints;
208 /* The show callback for 'show riscv use-compressed-breakpoints'. */
211 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
212 struct cmd_list_element *c,
215 fprintf_filtered (file,
216 _("Debugger's use of compressed breakpoints is set "
220 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
222 static struct cmd_list_element *setriscvcmdlist = NULL;
223 static struct cmd_list_element *showriscvcmdlist = NULL;
225 /* The show callback for the 'show riscv' prefix command. */
228 show_riscv_command (const char *args, int from_tty)
230 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
233 /* The set callback for the 'set riscv' prefix command. */
236 set_riscv_command (const char *args, int from_tty)
239 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
240 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
243 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
245 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
246 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
248 /* The show callback for the 'show debug riscv' prefix command. */
251 show_debug_riscv_command (const char *args, int from_tty)
253 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
256 /* The set callback for the 'set debug riscv' prefix command. */
259 set_debug_riscv_command (const char *args, int from_tty)
262 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
263 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
266 /* The show callback for all 'show debug riscv VARNAME' variables. */
269 show_riscv_debug_variable (struct ui_file *file, int from_tty,
270 struct cmd_list_element *c,
273 fprintf_filtered (file,
274 _("RiscV debug variable `%s' is set to: %s\n"),
278 /* When this is set to non-zero debugging information about breakpoint
279 kinds will be printed. */
281 static unsigned int riscv_debug_breakpoints = 0;
283 /* When this is set to non-zero debugging information about inferior calls
286 static unsigned int riscv_debug_infcall = 0;
288 /* When this is set to non-zero debugging information about stack unwinding
291 static unsigned int riscv_debug_unwinder = 0;
293 /* Read the MISA register from the target. There are a couple of locations
294 that the register might be found, these are all tried. If the MISA
295 register can't be found at all then the default value of 0 is returned,
296 this is inline with the RISC-V specification. */
299 riscv_read_misa_reg ()
303 if (target_has_registers)
305 /* Old cores might have MISA located at a different offset. */
306 static int misa_regs[] =
307 { RISCV_CSR_MISA_REGNUM, RISCV_CSR_LEGACY_MISA_REGNUM };
309 struct frame_info *frame = get_current_frame ();
311 for (int i = 0; i < ARRAY_SIZE (misa_regs); ++i)
313 bool success = false;
317 value = get_frame_register_unsigned (frame, misa_regs[i]);
320 CATCH (ex, RETURN_MASK_ERROR)
322 /* Ignore errors, it is acceptable for a target to not
323 provide a MISA register, in which case the default value
324 of 0 should be used. */
336 /* Return true if FEATURE is available for the architecture GDBARCH. The
337 FEATURE should be one of the single character feature codes described in
338 the RiscV ISA manual, these are between 'A' and 'Z'. */
341 riscv_has_feature (struct gdbarch *gdbarch, char feature)
343 gdb_assert (feature >= 'A' && feature <= 'Z');
345 uint32_t misa = riscv_read_misa_reg ();
347 misa = gdbarch_tdep (gdbarch)->core_features;
349 return (misa & (1 << (feature - 'A'))) != 0;
352 /* See riscv-tdep.h. */
355 riscv_isa_xlen (struct gdbarch *gdbarch)
357 switch (gdbarch_tdep (gdbarch)->abi.fields.base_len)
360 warning (_("unknown xlen size, assuming 4 bytes"));
371 /* See riscv-tdep.h. */
374 riscv_isa_flen (struct gdbarch *gdbarch)
376 if (riscv_has_feature (gdbarch, 'Q'))
378 else if (riscv_has_feature (gdbarch, 'D'))
380 else if (riscv_has_feature (gdbarch, 'F'))
386 /* Return true if the target for GDBARCH has floating point hardware. */
389 riscv_has_fp_regs (struct gdbarch *gdbarch)
391 return (riscv_isa_flen (gdbarch) > 0);
394 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
397 riscv_has_fp_abi (struct gdbarch *gdbarch)
399 return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0);
402 /* Return true if REGNO is a floating pointer register. */
405 riscv_is_fp_regno_p (int regno)
407 return (regno >= RISCV_FIRST_FP_REGNUM
408 && regno <= RISCV_LAST_FP_REGNUM);
411 /* Implement the breakpoint_kind_from_pc gdbarch method. */
414 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
416 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
418 bool unaligned_p = false;
421 /* Some targets don't support unaligned reads. The address can only
422 be unaligned if the C extension is supported. So it is safe to
423 use a compressed breakpoint in this case. */
428 /* Read the opcode byte to determine the instruction length. */
429 read_code (*pcptr, buf, 1);
432 if (riscv_debug_breakpoints)
434 const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
435 ? "C.EBREAK" : "EBREAK");
437 fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ",
438 bp, paddress (gdbarch, *pcptr));
440 fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n");
442 fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n",
443 riscv_insn_length (buf[0]));
445 if (unaligned_p || riscv_insn_length (buf[0]) == 2)
450 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
456 /* Implement the sw_breakpoint_from_kind gdbarch method. */
458 static const gdb_byte *
459 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
461 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
462 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
472 gdb_assert_not_reached (_("unhandled breakpoint kind"));
476 /* Callback function for user_reg_add. */
478 static struct value *
479 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
481 const int *reg_p = (const int *) baton;
482 return value_of_register (*reg_p, frame);
485 /* Implement the register_name gdbarch method. */
488 riscv_register_name (struct gdbarch *gdbarch, int regnum)
490 /* Prefer to use the alias. */
491 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
493 gdb_assert (regnum < ARRAY_SIZE (riscv_gdb_reg_names));
494 return riscv_gdb_reg_names[regnum];
497 /* Check that there's no gap between the set of registers handled above,
498 and the set of registers handled next. */
499 gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM);
501 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
503 #define DECLARE_CSR(NAME,VALUE) \
504 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
508 #include "opcode/riscv-opc.h"
513 xsnprintf (buf, sizeof (buf), "csr%d",
514 regnum - RISCV_FIRST_CSR_REGNUM);
521 if (regnum == RISCV_PRIV_REGNUM)
527 /* Construct a type for 64-bit FP registers. */
530 riscv_fpreg_d_type (struct gdbarch *gdbarch)
532 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
534 if (tdep->riscv_fpreg_d_type == nullptr)
536 const struct builtin_type *bt = builtin_type (gdbarch);
538 /* The type we're building is this: */
540 union __gdb_builtin_type_fpreg_d
549 t = arch_composite_type (gdbarch,
550 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
551 append_composite_type_field (t, "float", bt->builtin_float);
552 append_composite_type_field (t, "double", bt->builtin_double);
554 TYPE_NAME (t) = "builtin_type_fpreg_d";
555 tdep->riscv_fpreg_d_type = t;
558 return tdep->riscv_fpreg_d_type;
561 /* Construct a type for 128-bit FP registers. */
564 riscv_fpreg_q_type (struct gdbarch *gdbarch)
566 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
568 if (tdep->riscv_fpreg_q_type == nullptr)
570 const struct builtin_type *bt = builtin_type (gdbarch);
572 /* The type we're building is this: */
574 union __gdb_builtin_type_fpreg_d
584 t = arch_composite_type (gdbarch,
585 "__gdb_builtin_type_fpreg_q", TYPE_CODE_UNION);
586 append_composite_type_field (t, "float", bt->builtin_float);
587 append_composite_type_field (t, "double", bt->builtin_double);
588 append_composite_type_field (t, "long double", bt->builtin_long_double);
590 TYPE_NAME (t) = "builtin_type_fpreg_q";
591 tdep->riscv_fpreg_q_type = t;
594 return tdep->riscv_fpreg_q_type;
597 /* Implement the register_type gdbarch method. */
600 riscv_register_type (struct gdbarch *gdbarch, int regnum)
604 if (regnum < RISCV_FIRST_FP_REGNUM)
606 if (regnum == gdbarch_pc_regnum (gdbarch)
607 || regnum == RISCV_RA_REGNUM)
608 return builtin_type (gdbarch)->builtin_func_ptr;
610 if (regnum == RISCV_FP_REGNUM
611 || regnum == RISCV_SP_REGNUM
612 || regnum == RISCV_GP_REGNUM
613 || regnum == RISCV_TP_REGNUM)
614 return builtin_type (gdbarch)->builtin_data_ptr;
616 /* Remaining GPRs vary in size based on the current ISA. */
617 regsize = riscv_isa_xlen (gdbarch);
621 return builtin_type (gdbarch)->builtin_uint32;
623 return builtin_type (gdbarch)->builtin_uint64;
625 return builtin_type (gdbarch)->builtin_uint128;
627 internal_error (__FILE__, __LINE__,
628 _("unknown isa regsize %i"), regsize);
631 else if (regnum <= RISCV_LAST_FP_REGNUM)
633 regsize = riscv_isa_xlen (gdbarch);
637 return builtin_type (gdbarch)->builtin_float;
639 return riscv_fpreg_d_type (gdbarch);
641 return riscv_fpreg_q_type (gdbarch);
643 internal_error (__FILE__, __LINE__,
644 _("unknown isa regsize %i"), regsize);
647 else if (regnum == RISCV_PRIV_REGNUM)
648 return builtin_type (gdbarch)->builtin_int8;
651 if (regnum == RISCV_CSR_FFLAGS_REGNUM
652 || regnum == RISCV_CSR_FRM_REGNUM
653 || regnum == RISCV_CSR_FCSR_REGNUM)
654 return builtin_type (gdbarch)->builtin_int32;
656 regsize = riscv_isa_xlen (gdbarch);
660 return builtin_type (gdbarch)->builtin_int32;
662 return builtin_type (gdbarch)->builtin_int64;
664 return builtin_type (gdbarch)->builtin_int128;
666 internal_error (__FILE__, __LINE__,
667 _("unknown isa regsize %i"), regsize);
672 /* Helper for riscv_print_registers_info, prints info for a single register
676 riscv_print_one_register_info (struct gdbarch *gdbarch,
677 struct ui_file *file,
678 struct frame_info *frame,
681 const char *name = gdbarch_register_name (gdbarch, regnum);
682 struct value *val = value_of_register (regnum, frame);
683 struct type *regtype = value_type (val);
684 int print_raw_format;
685 enum tab_stops { value_column_1 = 15 };
687 fputs_filtered (name, file);
688 print_spaces_filtered (value_column_1 - strlen (name), file);
690 print_raw_format = (value_entirely_available (val)
691 && !value_optimized_out (val));
693 if (TYPE_CODE (regtype) == TYPE_CODE_FLT
694 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
695 && TYPE_NFIELDS (regtype) == 2
696 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
697 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
698 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
699 && TYPE_NFIELDS (regtype) == 3
700 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
701 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
702 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
704 struct value_print_options opts;
705 const gdb_byte *valaddr = value_contents_for_printing (val);
706 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
708 get_user_print_options (&opts);
712 value_embedded_offset (val), 0,
713 file, 0, val, &opts, current_language);
715 if (print_raw_format)
717 fprintf_filtered (file, "\t(raw ");
718 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
720 fprintf_filtered (file, ")");
725 struct value_print_options opts;
727 /* Print the register in hex. */
728 get_formatted_print_options (&opts, 'x');
731 value_embedded_offset (val), 0,
732 file, 0, val, &opts, current_language);
734 if (print_raw_format)
736 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
739 int size = register_size (gdbarch, regnum);
742 d = value_as_long (val);
744 fprintf_filtered (file,
745 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
746 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
747 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
748 (int) ((d >> (xlen - 1)) & 0x1),
749 (int) ((d >> 24) & 0x1f),
750 (int) ((d >> 19) & 0x1),
751 (int) ((d >> 18) & 0x1),
752 (int) ((d >> 17) & 0x1),
753 (int) ((d >> 15) & 0x3),
754 (int) ((d >> 13) & 0x3),
755 (int) ((d >> 11) & 0x3),
756 (int) ((d >> 9) & 0x3),
757 (int) ((d >> 8) & 0x1),
758 (int) ((d >> 7) & 0x1),
759 (int) ((d >> 6) & 0x1),
760 (int) ((d >> 5) & 0x1),
761 (int) ((d >> 4) & 0x1),
762 (int) ((d >> 3) & 0x1),
763 (int) ((d >> 2) & 0x1),
764 (int) ((d >> 1) & 0x1),
765 (int) ((d >> 0) & 0x1));
767 else if (regnum == RISCV_CSR_MISA_REGNUM)
773 d = value_as_long (val);
777 for (; base > 0; base--)
779 fprintf_filtered (file, "\tRV%d", xlen);
781 for (i = 0; i < 26; i++)
784 fprintf_filtered (file, "%c", 'A' + i);
787 else if (regnum == RISCV_CSR_FCSR_REGNUM
788 || regnum == RISCV_CSR_FFLAGS_REGNUM
789 || regnum == RISCV_CSR_FRM_REGNUM)
793 d = value_as_long (val);
795 fprintf_filtered (file, "\t");
796 if (regnum != RISCV_CSR_FRM_REGNUM)
797 fprintf_filtered (file,
798 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
799 (int) ((d >> 5) & 0x7),
800 (int) ((d >> 4) & 0x1),
801 (int) ((d >> 3) & 0x1),
802 (int) ((d >> 2) & 0x1),
803 (int) ((d >> 1) & 0x1),
804 (int) ((d >> 0) & 0x1));
806 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
808 static const char * const sfrm[] =
810 "RNE (round to nearest; ties to even)",
811 "RTZ (Round towards zero)",
812 "RDN (Round down towards -INF)",
813 "RUP (Round up towards +INF)",
814 "RMM (Round to nearest; ties to max magnitude)",
817 "dynamic rounding mode",
819 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
820 ? (d >> 5) : d) & 0x3;
822 fprintf_filtered (file, "%sFRM:%i [%s]",
823 (regnum == RISCV_CSR_FCSR_REGNUM
828 else if (regnum == RISCV_PRIV_REGNUM)
833 d = value_as_long (val);
838 static const char * const sprv[] =
845 fprintf_filtered (file, "\tprv:%d [%s]",
849 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
853 /* If not a vector register, print it also according to its
855 if (TYPE_VECTOR (regtype) == 0)
857 get_user_print_options (&opts);
859 fprintf_filtered (file, "\t");
861 value_embedded_offset (val), 0,
862 file, 0, val, &opts, current_language);
867 fprintf_filtered (file, "\n");
870 /* Return true if REGNUM is a valid CSR register. The CSR register space
871 is sparsely populated, so not every number is a named CSR. */
874 riscv_is_regnum_a_named_csr (int regnum)
876 gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
877 && regnum <= RISCV_LAST_CSR_REGNUM);
881 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
882 #include "opcode/riscv-opc.h"
891 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
895 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
896 struct reggroup *reggroup)
898 /* Used by 'info registers' and 'info registers <groupname>'. */
900 if (gdbarch_register_name (gdbarch, regnum) == NULL
901 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
904 if (reggroup == all_reggroup)
906 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
908 if (riscv_is_regnum_a_named_csr (regnum))
912 else if (reggroup == float_reggroup)
913 return (riscv_is_fp_regno_p (regnum)
914 || regnum == RISCV_CSR_FCSR_REGNUM
915 || regnum == RISCV_CSR_FFLAGS_REGNUM
916 || regnum == RISCV_CSR_FRM_REGNUM);
917 else if (reggroup == general_reggroup)
918 return regnum < RISCV_FIRST_FP_REGNUM;
919 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
921 if (riscv_has_fp_regs (gdbarch))
922 return regnum <= RISCV_LAST_FP_REGNUM;
924 return regnum < RISCV_FIRST_FP_REGNUM;
926 else if (reggroup == system_reggroup)
928 if (regnum == RISCV_PRIV_REGNUM)
930 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
932 if (riscv_is_regnum_a_named_csr (regnum))
936 else if (reggroup == vector_reggroup)
942 /* Implement the print_registers_info gdbarch method. This is used by
943 'info registers' and 'info all-registers'. */
946 riscv_print_registers_info (struct gdbarch *gdbarch,
947 struct ui_file *file,
948 struct frame_info *frame,
949 int regnum, int print_all)
953 /* Print one specified register. */
954 gdb_assert (regnum <= RISCV_LAST_REGNUM);
955 if (gdbarch_register_name (gdbarch, regnum) == NULL
956 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
957 error (_("Not a valid register for the current processor type"));
958 riscv_print_one_register_info (gdbarch, file, frame, regnum);
962 struct reggroup *reggroup;
965 reggroup = all_reggroup;
967 reggroup = general_reggroup;
969 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
971 /* Zero never changes, so might as well hide by default. */
972 if (regnum == RISCV_ZERO_REGNUM && !print_all)
975 /* Registers with no name are not valid on this ISA. */
976 if (gdbarch_register_name (gdbarch, regnum) == NULL
977 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
980 /* Is the register in the group we're interested in? */
981 if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup))
984 riscv_print_one_register_info (gdbarch, file, frame, regnum);
989 /* Class that handles one decoded RiscV instruction. */
995 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
998 /* Unknown value is used at initialisation time. */
1001 /* These instructions are all the ones we are interested in during the
1011 /* These are needed for software breakopint support. */
1020 /* These are needed for stepping over atomic sequences. */
1024 /* Other instructions are not interesting during the prologue scan, and
1039 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1041 /* Get the length of the instruction in bytes. */
1043 { return m_length; }
1045 /* Get the opcode for this instruction. */
1046 enum opcode opcode () const
1047 { return m_opcode; }
1049 /* Get destination register field for this instruction. This is only
1050 valid if the OPCODE implies there is such a field for this
1055 /* Get the RS1 register field for this instruction. This is only valid
1056 if the OPCODE implies there is such a field for this instruction. */
1060 /* Get the RS2 register field for this instruction. This is only valid
1061 if the OPCODE implies there is such a field for this instruction. */
1065 /* Get the immediate for this instruction in signed form. This is only
1066 valid if the OPCODE implies there is such a field for this
1068 int imm_signed () const
1073 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1074 int decode_register_index (unsigned long opcode, int offset)
1076 return (opcode >> offset) & 0x1F;
1079 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1080 int decode_register_index_short (unsigned long opcode, int offset)
1082 return ((opcode >> offset) & 0x7) + 8;
1085 /* Helper for DECODE, decode 32-bit R-type instruction. */
1086 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1089 m_rd = decode_register_index (ival, OP_SH_RD);
1090 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1091 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1094 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1095 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1098 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1099 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1102 /* Helper for DECODE, decode 32-bit I-type instruction. */
1103 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1106 m_rd = decode_register_index (ival, OP_SH_RD);
1107 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1108 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1111 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1112 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1115 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1116 m_imm.s = EXTRACT_RVC_IMM (ival);
1119 /* Helper for DECODE, decode 32-bit S-type instruction. */
1120 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1123 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1124 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1125 m_imm.s = EXTRACT_STYPE_IMM (ival);
1128 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1129 encoding is different for each CS format instruction, so extracting
1130 the immediate is left up to the caller, who should pass the extracted
1131 immediate value through in IMM. */
1132 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1136 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1137 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1140 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1141 encoding is different for each CSS format instruction, so extracting
1142 the immediate is left up to the caller, who should pass the extracted
1143 immediate value through in IMM. */
1144 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1148 m_rs1 = RISCV_SP_REGNUM;
1149 /* Not a compressed register number in this case. */
1150 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1153 /* Helper for DECODE, decode 32-bit U-type instruction. */
1154 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1157 m_rd = decode_register_index (ival, OP_SH_RD);
1158 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1161 /* Helper for DECODE, decode 32-bit J-type instruction. */
1162 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1165 m_rd = decode_register_index (ival, OP_SH_RD);
1166 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1169 /* Helper for DECODE, decode 32-bit J-type instruction. */
1170 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1173 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1176 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1179 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1180 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1181 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1184 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1187 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1188 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1191 /* Fetch instruction from target memory at ADDR, return the content of
1192 the instruction, and update LEN with the instruction length. */
1193 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1194 CORE_ADDR addr, int *len);
1196 /* The length of the instruction in bytes. Should be 2 or 4. */
1199 /* The instruction opcode. */
1200 enum opcode m_opcode;
1202 /* The three possible registers an instruction might reference. Not
1203 every instruction fills in all of these registers. Which fields are
1204 valid depends on the opcode. The naming of these fields matches the
1205 naming in the riscv isa manual. */
1210 /* Possible instruction immediate. This is only valid if the instruction
1211 format contains an immediate, not all instruction, whether this is
1212 valid depends on the opcode. Despite only having one format for now
1213 the immediate is packed into a union, later instructions might require
1214 an unsigned formatted immediate, having the union in place now will
1215 reduce the need for code churn later. */
1216 union riscv_insn_immediate
1218 riscv_insn_immediate ()
1228 /* Fetch instruction from target memory at ADDR, return the content of the
1229 instruction, and update LEN with the instruction length. */
1232 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1233 CORE_ADDR addr, int *len)
1235 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1237 int instlen, status;
1239 /* All insns are at least 16 bits. */
1240 status = target_read_memory (addr, buf, 2);
1242 memory_error (TARGET_XFER_E_IO, addr);
1244 /* If we need more, grab it now. */
1245 instlen = riscv_insn_length (buf[0]);
1246 gdb_assert (instlen <= sizeof (buf));
1251 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1253 memory_error (TARGET_XFER_E_IO, addr + 2);
1256 return extract_unsigned_integer (buf, instlen, byte_order);
1259 /* Fetch from target memory an instruction at PC and decode it. This can
1260 throw an error if the memory access fails, callers are responsible for
1261 handling this error if that is appropriate. */
1264 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1268 /* Fetch the instruction, and the instructions length. */
1269 ival = fetch_instruction (gdbarch, pc, &m_length);
1273 if (is_add_insn (ival))
1274 decode_r_type_insn (ADD, ival);
1275 else if (is_addw_insn (ival))
1276 decode_r_type_insn (ADDW, ival);
1277 else if (is_addi_insn (ival))
1278 decode_i_type_insn (ADDI, ival);
1279 else if (is_addiw_insn (ival))
1280 decode_i_type_insn (ADDIW, ival);
1281 else if (is_auipc_insn (ival))
1282 decode_u_type_insn (AUIPC, ival);
1283 else if (is_lui_insn (ival))
1284 decode_u_type_insn (LUI, ival);
1285 else if (is_sd_insn (ival))
1286 decode_s_type_insn (SD, ival);
1287 else if (is_sw_insn (ival))
1288 decode_s_type_insn (SW, ival);
1289 else if (is_jal_insn (ival))
1290 decode_j_type_insn (JAL, ival);
1291 else if (is_jalr_insn (ival))
1292 decode_i_type_insn (JALR, ival);
1293 else if (is_beq_insn (ival))
1294 decode_b_type_insn (BEQ, ival);
1295 else if (is_bne_insn (ival))
1296 decode_b_type_insn (BNE, ival);
1297 else if (is_blt_insn (ival))
1298 decode_b_type_insn (BLT, ival);
1299 else if (is_bge_insn (ival))
1300 decode_b_type_insn (BGE, ival);
1301 else if (is_bltu_insn (ival))
1302 decode_b_type_insn (BLTU, ival);
1303 else if (is_bgeu_insn (ival))
1304 decode_b_type_insn (BGEU, ival);
1305 else if (is_lr_w_insn (ival))
1306 decode_r_type_insn (LR, ival);
1307 else if (is_lr_d_insn (ival))
1308 decode_r_type_insn (LR, ival);
1309 else if (is_sc_w_insn (ival))
1310 decode_r_type_insn (SC, ival);
1311 else if (is_sc_d_insn (ival))
1312 decode_r_type_insn (SC, ival);
1314 /* None of the other fields are valid in this case. */
1317 else if (m_length == 2)
1319 int xlen = riscv_isa_xlen (gdbarch);
1321 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1322 C_JALR. So must try to match C_JALR first as it has more bits in
1324 if (is_c_jalr_insn (ival))
1325 decode_cr_type_insn (JALR, ival);
1326 else if (is_c_add_insn (ival))
1327 decode_cr_type_insn (ADD, ival);
1328 /* C_ADDW is RV64 and RV128 only. */
1329 else if (xlen != 4 && is_c_addw_insn (ival))
1330 decode_cr_type_insn (ADDW, ival);
1331 else if (is_c_addi_insn (ival))
1332 decode_ci_type_insn (ADDI, ival);
1333 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1334 only and C_JAL is RV32 only. */
1335 else if (xlen != 4 && is_c_addiw_insn (ival))
1336 decode_ci_type_insn (ADDIW, ival);
1337 else if (xlen == 4 && is_c_jal_insn (ival))
1338 decode_cj_type_insn (JAL, ival);
1339 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1340 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1342 else if (is_c_addi16sp_insn (ival))
1345 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1346 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1348 else if (is_c_addi4spn_insn (ival))
1351 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1352 m_rs1 = RISCV_SP_REGNUM;
1353 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1355 else if (is_c_lui_insn (ival))
1358 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1359 m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
1361 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1362 and C_FSW is RV32 only. */
1363 else if (xlen != 4 && is_c_sd_insn (ival))
1364 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
1365 else if (is_c_sw_insn (ival))
1366 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1367 else if (is_c_swsp_insn (ival))
1368 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1369 else if (xlen != 4 && is_c_sdsp_insn (ival))
1370 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
1371 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1372 So must try to match C_JR first as it ahs more bits in mask. */
1373 else if (is_c_jr_insn (ival))
1374 decode_cr_type_insn (JALR, ival);
1375 else if (is_c_j_insn (ival))
1376 decode_cj_type_insn (JAL, ival);
1377 else if (is_c_beqz_insn (ival))
1378 decode_cb_type_insn (BEQ, ival);
1379 else if (is_c_bnez_insn (ival))
1380 decode_cb_type_insn (BNE, ival);
1382 /* None of the other fields of INSN are valid in this case. */
1386 internal_error (__FILE__, __LINE__,
1387 _("unable to decode %d byte instructions in "
1388 "prologue at %s"), m_length,
1389 core_addr_to_string (pc));
1392 /* The prologue scanner. This is currently only used for skipping the
1393 prologue of a function when the DWARF information is not sufficient.
1394 However, it is written with filling of the frame cache in mind, which
1395 is why different groups of stack setup instructions are split apart
1396 during the core of the inner loop. In the future, the intention is to
1397 extend this function to fully support building up a frame cache that
1398 can unwind register values when there is no DWARF information. */
1401 riscv_scan_prologue (struct gdbarch *gdbarch,
1402 CORE_ADDR start_pc, CORE_ADDR end_pc,
1403 struct riscv_unwind_cache *cache)
1405 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1406 CORE_ADDR end_prologue_addr = 0;
1408 /* Find an upper limit on the function prologue using the debug
1409 information. If the debug information could not be used to provide
1410 that bound, then use an arbitrary large number as the upper bound. */
1411 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1412 if (after_prologue_pc == 0)
1413 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1414 if (after_prologue_pc < end_pc)
1415 end_pc = after_prologue_pc;
1417 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1418 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1419 regs[regno] = pv_register (regno, 0);
1420 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1422 if (riscv_debug_unwinder)
1425 "Prologue scan for function starting at %s (limit %s)\n",
1426 core_addr_to_string (start_pc),
1427 core_addr_to_string (end_pc));
1429 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1431 struct riscv_insn insn;
1433 /* Decode the current instruction, and decide where the next
1434 instruction lives based on the size of this instruction. */
1435 insn.decode (gdbarch, cur_pc);
1436 gdb_assert (insn.length () > 0);
1437 next_pc = cur_pc + insn.length ();
1439 /* Look for common stack adjustment insns. */
1440 if ((insn.opcode () == riscv_insn::ADDI
1441 || insn.opcode () == riscv_insn::ADDIW)
1442 && insn.rd () == RISCV_SP_REGNUM
1443 && insn.rs1 () == RISCV_SP_REGNUM)
1445 /* Handle: addi sp, sp, -i
1446 or: addiw sp, sp, -i */
1447 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1448 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1450 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1452 else if ((insn.opcode () == riscv_insn::SW
1453 || insn.opcode () == riscv_insn::SD)
1454 && (insn.rs1 () == RISCV_SP_REGNUM
1455 || insn.rs1 () == RISCV_FP_REGNUM))
1457 /* Handle: sw reg, offset(sp)
1458 or: sd reg, offset(sp)
1459 or: sw reg, offset(s0)
1460 or: sd reg, offset(s0) */
1461 /* Instruction storing a register onto the stack. */
1462 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1463 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1464 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1465 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1468 else if (insn.opcode () == riscv_insn::ADDI
1469 && insn.rd () == RISCV_FP_REGNUM
1470 && insn.rs1 () == RISCV_SP_REGNUM)
1472 /* Handle: addi s0, sp, size */
1473 /* Instructions setting up the frame pointer. */
1474 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1475 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1477 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1479 else if ((insn.opcode () == riscv_insn::ADD
1480 || insn.opcode () == riscv_insn::ADDW)
1481 && insn.rd () == RISCV_FP_REGNUM
1482 && insn.rs1 () == RISCV_SP_REGNUM
1483 && insn.rs2 () == RISCV_ZERO_REGNUM)
1485 /* Handle: add s0, sp, 0
1486 or: addw s0, sp, 0 */
1487 /* Instructions setting up the frame pointer. */
1488 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1489 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1490 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1492 else if ((insn.opcode () == riscv_insn::ADDI
1493 && insn.rd () == RISCV_ZERO_REGNUM
1494 && insn.rs1 () == RISCV_ZERO_REGNUM
1495 && insn.imm_signed () == 0))
1497 /* Handle: add x0, x0, 0 (NOP) */
1499 else if (insn.opcode () == riscv_insn::AUIPC)
1501 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1502 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1504 else if (insn.opcode () == riscv_insn::LUI)
1506 /* Handle: lui REG, n
1507 Where REG is not gp register. */
1508 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1509 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1511 else if (insn.opcode () == riscv_insn::ADDI)
1513 /* Handle: addi REG1, REG2, IMM */
1514 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1515 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1517 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1519 else if (insn.opcode () == riscv_insn::ADD)
1521 /* Handle: addi REG1, REG2, IMM */
1522 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1523 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1524 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1525 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1529 end_prologue_addr = cur_pc;
1534 if (end_prologue_addr == 0)
1535 end_prologue_addr = cur_pc;
1537 if (riscv_debug_unwinder)
1538 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1539 core_addr_to_string (end_prologue_addr));
1543 /* Figure out if it is a frame pointer or just a stack pointer. Also
1544 the offset held in the pv_t is from the original register value to
1545 the current value, which for a grows down stack means a negative
1546 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1547 from the current value to the original value. */
1548 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1550 cache->frame_base_reg = RISCV_FP_REGNUM;
1551 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1555 cache->frame_base_reg = RISCV_SP_REGNUM;
1556 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1559 /* Assign offset from old SP to all saved registers. As we don't
1560 have the previous value for the frame base register at this
1561 point, we store the offset as the address in the trad_frame, and
1562 then convert this to an actual address later. */
1563 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1566 if (stack.find_reg (gdbarch, i, &offset))
1568 if (riscv_debug_unwinder)
1569 fprintf_unfiltered (gdb_stdlog,
1570 "Register $%s at stack offset %ld\n",
1571 gdbarch_register_name (gdbarch, i),
1573 trad_frame_set_addr (cache->regs, i, offset);
1578 return end_prologue_addr;
1581 /* Implement the riscv_skip_prologue gdbarch method. */
1584 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1586 CORE_ADDR func_addr;
1588 /* See if we can determine the end of the prologue via the symbol
1589 table. If so, then return either PC, or the PC after the
1590 prologue, whichever is greater. */
1591 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1593 CORE_ADDR post_prologue_pc
1594 = skip_prologue_using_sal (gdbarch, func_addr);
1596 if (post_prologue_pc != 0)
1597 return std::max (pc, post_prologue_pc);
1600 /* Can't determine prologue from the symbol table, need to examine
1601 instructions. Pass -1 for the end address to indicate the prologue
1602 scanner can scan as far as it needs to find the end of the prologue. */
1603 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1606 /* Implement the gdbarch push dummy code callback. */
1609 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1610 CORE_ADDR funaddr, struct value **args, int nargs,
1611 struct type *value_type, CORE_ADDR *real_pc,
1612 CORE_ADDR *bp_addr, struct regcache *regcache)
1614 /* Allocate space for a breakpoint, and keep the stack correctly
1622 /* Compute the alignment of the type T. Used while setting up the
1623 arguments for a dummy call. */
1626 riscv_type_alignment (struct type *t)
1628 t = check_typedef (t);
1629 switch (TYPE_CODE (t))
1632 error (_("Could not compute alignment of type"));
1634 case TYPE_CODE_RVALUE_REF:
1636 case TYPE_CODE_ENUM:
1640 case TYPE_CODE_CHAR:
1641 case TYPE_CODE_BOOL:
1642 return TYPE_LENGTH (t);
1644 case TYPE_CODE_ARRAY:
1645 case TYPE_CODE_COMPLEX:
1646 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1648 case TYPE_CODE_STRUCT:
1649 case TYPE_CODE_UNION:
1654 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1656 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1658 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1668 /* Holds information about a single argument either being passed to an
1669 inferior function, or returned from an inferior function. This includes
1670 information about the size, type, etc of the argument, and also
1671 information about how the argument will be passed (or returned). */
1673 struct riscv_arg_info
1675 /* Contents of the argument. */
1676 const gdb_byte *contents;
1678 /* Length of argument. */
1681 /* Alignment required for an argument of this type. */
1684 /* The type for this argument. */
1687 /* Each argument can have either 1 or 2 locations assigned to it. Each
1688 location describes where part of the argument will be placed. The
1689 second location is valid based on the LOC_TYPE and C_LENGTH fields
1690 of the first location (which is always valid). */
1693 /* What type of location this is. */
1696 /* Argument passed in a register. */
1699 /* Argument passed as an on stack argument. */
1702 /* Argument passed by reference. The second location is always
1703 valid for a BY_REF argument, and describes where the address
1704 of the BY_REF argument should be placed. */
1708 /* Information that depends on the location type. */
1711 /* Which register number to use. */
1714 /* The offset into the stack region. */
1718 /* The length of contents covered by this location. If this is less
1719 than the total length of the argument, then the second location
1720 will be valid, and will describe where the rest of the argument
1724 /* The offset within CONTENTS for this part of the argument. Will
1725 always be 0 for the first part. For the second part of the
1726 argument, this might be the C_LENGTH value of the first part,
1727 however, if we are passing a structure in two registers, and there's
1728 is padding between the first and second field, then this offset
1729 might be greater than the length of the first argument part. When
1730 the second argument location is not holding part of the argument
1731 value, but is instead holding the address of a reference argument,
1732 then this offset will be set to 0. */
1737 /* Information about a set of registers being used for passing arguments as
1738 part of a function call. The register set must be numerically
1739 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1740 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1742 struct riscv_arg_reg
1744 riscv_arg_reg (int first, int last)
1745 : next_regnum (first),
1751 /* The GDB register number to use in this set. */
1754 /* The last GDB register number to use in this set. */
1758 /* Arguments can be passed as on stack arguments, or by reference. The
1759 on stack arguments must be in a continuous region starting from $sp,
1760 while the by reference arguments can be anywhere, but we'll put them
1761 on the stack after (at higher address) the on stack arguments.
1763 This might not be the right approach to take. The ABI is clear that
1764 an argument passed by reference can be modified by the callee, which
1765 us placing the argument (temporarily) onto the stack will not achieve
1766 (changes will be lost). There's also the possibility that very large
1767 arguments could overflow the stack.
1769 This struct is used to track offset into these two areas for where
1770 arguments are to be placed. */
1771 struct riscv_memory_offsets
1773 riscv_memory_offsets ()
1780 /* Offset into on stack argument area. */
1783 /* Offset into the pass by reference area. */
1787 /* Holds information about where arguments to a call will be placed. This
1788 is updated as arguments are added onto the call, and can be used to
1789 figure out where the next argument should be placed. */
1791 struct riscv_call_info
1793 riscv_call_info (struct gdbarch *gdbarch)
1794 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1795 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1797 xlen = riscv_isa_xlen (gdbarch);
1798 flen = riscv_isa_flen (gdbarch);
1800 /* Disable use of floating point registers if needed. */
1801 if (!riscv_has_fp_abi (gdbarch))
1802 float_regs.next_regnum = float_regs.last_regnum + 1;
1805 /* Track the memory areas used for holding in-memory arguments to a
1807 struct riscv_memory_offsets memory;
1809 /* Holds information about the next integer register to use for passing
1811 struct riscv_arg_reg int_regs;
1813 /* Holds information about the next floating point register to use for
1814 passing an argument. */
1815 struct riscv_arg_reg float_regs;
1817 /* The XLEN and FLEN are copied in to this structure for convenience, and
1818 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1823 /* Return the number of registers available for use as parameters in the
1824 register set REG. Returned value can be 0 or more. */
1827 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1829 if (reg->next_regnum > reg->last_regnum)
1832 return (reg->last_regnum - reg->next_regnum + 1);
1835 /* If there is at least one register available in the register set REG then
1836 the next register from REG is assigned to LOC and the length field of
1837 LOC is updated to LENGTH. The register set REG is updated to indicate
1838 that the assigned register is no longer available and the function
1841 If there are no registers available in REG then the function returns
1842 false, and LOC and REG are unchanged. */
1845 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1846 struct riscv_arg_reg *reg,
1847 int length, int offset)
1849 if (reg->next_regnum <= reg->last_regnum)
1851 loc->loc_type = riscv_arg_info::location::in_reg;
1852 loc->loc_data.regno = reg->next_regnum;
1854 loc->c_length = length;
1855 loc->c_offset = offset;
1862 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1863 record that an area of stack has been used to hold the parameter
1866 The length field of LOC is updated to LENGTH, the length of the
1867 parameter being stored, and ALIGN is the alignment required by the
1868 parameter, which will affect how memory is allocated out of MEMORY. */
1871 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1872 struct riscv_memory_offsets *memory,
1873 int length, int align)
1875 loc->loc_type = riscv_arg_info::location::on_stack;
1877 = align_up (memory->arg_offset, align);
1878 loc->loc_data.offset = memory->arg_offset;
1879 memory->arg_offset += length;
1880 loc->c_length = length;
1882 /* Offset is always 0, either we're the first location part, in which
1883 case we're reading content from the start of the argument, or we're
1884 passing the address of a reference argument, so 0. */
1888 /* Update AINFO, which describes an argument that should be passed or
1889 returned using the integer ABI. The argloc fields within AINFO are
1890 updated to describe the location in which the argument will be passed to
1891 a function, or returned from a function.
1893 The CINFO structure contains the ongoing call information, the holds
1894 information such as which argument registers are remaining to be
1895 assigned to parameter, and how much memory has been used by parameters
1898 By examining the state of CINFO a suitable location can be selected,
1899 and assigned to AINFO. */
1902 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1903 struct riscv_call_info *cinfo)
1905 if (ainfo->length > (2 * cinfo->xlen))
1907 /* Argument is going to be passed by reference. */
1908 ainfo->argloc[0].loc_type
1909 = riscv_arg_info::location::by_ref;
1910 cinfo->memory.ref_offset
1911 = align_up (cinfo->memory.ref_offset, ainfo->align);
1912 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1913 cinfo->memory.ref_offset += ainfo->length;
1914 ainfo->argloc[0].c_length = ainfo->length;
1916 /* The second location for this argument is given over to holding the
1917 address of the by-reference data. Pass 0 for the offset as this
1918 is not part of the actual argument value. */
1919 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1922 riscv_assign_stack_location (&ainfo->argloc[1],
1923 &cinfo->memory, cinfo->xlen,
1928 int len = std::min (ainfo->length, cinfo->xlen);
1929 int align = std::max (ainfo->align, cinfo->xlen);
1931 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1932 &cinfo->int_regs, len, 0))
1933 riscv_assign_stack_location (&ainfo->argloc[0],
1934 &cinfo->memory, len, align);
1936 if (len < ainfo->length)
1938 len = ainfo->length - len;
1939 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1940 &cinfo->int_regs, len,
1942 riscv_assign_stack_location (&ainfo->argloc[1],
1943 &cinfo->memory, len, cinfo->xlen);
1948 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1949 is being passed with the floating point ABI. */
1952 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1953 struct riscv_call_info *cinfo)
1955 if (ainfo->length > cinfo->flen)
1956 return riscv_call_arg_scalar_int (ainfo, cinfo);
1959 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1962 return riscv_call_arg_scalar_int (ainfo, cinfo);
1966 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1967 is a complex floating point argument, and is therefore handled
1968 differently to other argument types. */
1971 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1972 struct riscv_call_info *cinfo)
1974 if (ainfo->length <= (2 * cinfo->flen)
1975 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1978 int len = ainfo->length / 2;
1980 result = riscv_assign_reg_location (&ainfo->argloc[0],
1981 &cinfo->float_regs, len, len);
1982 gdb_assert (result);
1984 result = riscv_assign_reg_location (&ainfo->argloc[1],
1985 &cinfo->float_regs, len, len);
1986 gdb_assert (result);
1989 return riscv_call_arg_scalar_int (ainfo, cinfo);
1992 /* A structure used for holding information about a structure type within
1993 the inferior program. The RiscV ABI has special rules for handling some
1994 structures with a single field or with two fields. The counting of
1995 fields here is done after flattening out all nested structures. */
1997 class riscv_struct_info
2000 riscv_struct_info ()
2001 : m_number_of_fields (0),
2002 m_types { nullptr, nullptr }
2007 /* Analyse TYPE descending into nested structures, count the number of
2008 scalar fields and record the types of the first two fields found. */
2009 void analyse (struct type *type);
2011 /* The number of scalar fields found in the analysed type. This is
2012 currently only accurate if the value returned is 0, 1, or 2 as the
2013 analysis stops counting when the number of fields is 3. This is
2014 because the RiscV ABI only has special cases for 1 or 2 fields,
2015 anything else we just don't care about. */
2016 int number_of_fields () const
2017 { return m_number_of_fields; }
2019 /* Return the type for scalar field INDEX within the analysed type. Will
2020 return nullptr if there is no field at that index. Only INDEX values
2021 0 and 1 can be requested as the RiscV ABI only has special cases for
2022 structures with 1 or 2 fields. */
2023 struct type *field_type (int index) const
2025 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
2026 return m_types[index];
2030 /* The number of scalar fields found within the structure after recursing
2031 into nested structures. */
2032 int m_number_of_fields;
2034 /* The types of the first two scalar fields found within the structure
2035 after recursing into nested structures. */
2036 struct type *m_types[2];
2039 /* Analyse TYPE descending into nested structures, count the number of
2040 scalar fields and record the types of the first two fields found. */
2043 riscv_struct_info::analyse (struct type *type)
2045 unsigned int count = TYPE_NFIELDS (type);
2048 for (i = 0; i < count; ++i)
2050 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
2053 struct type *field_type = TYPE_FIELD_TYPE (type, i);
2054 field_type = check_typedef (field_type);
2056 switch (TYPE_CODE (field_type))
2058 case TYPE_CODE_STRUCT:
2059 analyse (field_type);
2063 /* RiscV only flattens out structures. Anything else does not
2064 need to be flattened, we just record the type, and when we
2065 look at the analysis results we'll realise this is not a
2066 structure we can special case, and pass the structure in
2068 if (m_number_of_fields < 2)
2069 m_types[m_number_of_fields] = field_type;
2070 m_number_of_fields++;
2074 /* RiscV only has special handling for structures with 1 or 2 scalar
2075 fields, any more than that and the structure is just passed in
2076 memory. We can safely drop out early when we find 3 or more
2079 if (m_number_of_fields > 2)
2084 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2085 is a structure. Small structures on RiscV have some special case
2086 handling in order that the structure might be passed in register.
2087 Larger structures are passed in memory. After assigning location
2088 information to AINFO, CINFO will have been updated. */
2091 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
2092 struct riscv_call_info *cinfo)
2094 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2096 struct riscv_struct_info sinfo;
2098 sinfo.analyse (ainfo->type);
2099 if (sinfo.number_of_fields () == 1
2100 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
2102 gdb_assert (TYPE_LENGTH (ainfo->type)
2103 == TYPE_LENGTH (sinfo.field_type (0)));
2104 return riscv_call_arg_complex_float (ainfo, cinfo);
2107 if (sinfo.number_of_fields () == 1
2108 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
2110 gdb_assert (TYPE_LENGTH (ainfo->type)
2111 == TYPE_LENGTH (sinfo.field_type (0)));
2112 return riscv_call_arg_scalar_float (ainfo, cinfo);
2115 if (sinfo.number_of_fields () == 2
2116 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2117 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2118 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2119 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
2120 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2122 int len0, len1, offset;
2124 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
2126 len0 = TYPE_LENGTH (sinfo.field_type (0));
2127 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2128 &cinfo->float_regs, len0, 0))
2129 error (_("failed during argument setup"));
2131 len1 = TYPE_LENGTH (sinfo.field_type (1));
2132 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2133 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2134 - TYPE_LENGTH (sinfo.field_type (0))));
2136 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2139 error (_("failed during argument setup"));
2143 if (sinfo.number_of_fields () == 2
2144 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2145 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2146 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2147 && is_integral_type (sinfo.field_type (1))
2148 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2150 int len0, len1, offset;
2152 gdb_assert (TYPE_LENGTH (ainfo->type)
2153 <= (cinfo->flen + cinfo->xlen));
2155 len0 = TYPE_LENGTH (sinfo.field_type (0));
2156 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2157 &cinfo->float_regs, len0, 0))
2158 error (_("failed during argument setup"));
2160 len1 = TYPE_LENGTH (sinfo.field_type (1));
2161 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2162 gdb_assert (len1 <= cinfo->xlen);
2163 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2164 &cinfo->int_regs, len1, offset))
2165 error (_("failed during argument setup"));
2169 if (sinfo.number_of_fields () == 2
2170 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2171 && (is_integral_type (sinfo.field_type (0))
2172 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2173 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2174 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2176 int len0, len1, offset;
2178 gdb_assert (TYPE_LENGTH (ainfo->type)
2179 <= (cinfo->flen + cinfo->xlen));
2181 len0 = TYPE_LENGTH (sinfo.field_type (0));
2182 len1 = TYPE_LENGTH (sinfo.field_type (1));
2183 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2185 gdb_assert (len0 <= cinfo->xlen);
2186 gdb_assert (len1 <= cinfo->flen);
2188 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2189 &cinfo->int_regs, len0, 0))
2190 error (_("failed during argument setup"));
2192 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2195 error (_("failed during argument setup"));
2201 /* Non of the structure flattening cases apply, so we just pass using
2203 ainfo->length = align_up (ainfo->length, cinfo->xlen);
2204 riscv_call_arg_scalar_int (ainfo, cinfo);
2207 /* Assign a location to call (or return) argument AINFO, the location is
2208 selected from CINFO which holds information about what call argument
2209 locations are available for use next. The TYPE is the type of the
2210 argument being passed, this information is recorded into AINFO (along
2211 with some additional information derived from the type).
2213 After assigning a location to AINFO, CINFO will have been updated. */
2216 riscv_arg_location (struct gdbarch *gdbarch,
2217 struct riscv_arg_info *ainfo,
2218 struct riscv_call_info *cinfo,
2222 ainfo->length = TYPE_LENGTH (ainfo->type);
2223 ainfo->align = riscv_type_alignment (ainfo->type);
2224 ainfo->contents = nullptr;
2226 switch (TYPE_CODE (ainfo->type))
2229 case TYPE_CODE_BOOL:
2230 case TYPE_CODE_CHAR:
2231 case TYPE_CODE_RANGE:
2232 case TYPE_CODE_ENUM:
2234 if (ainfo->length <= cinfo->xlen)
2236 ainfo->type = builtin_type (gdbarch)->builtin_long;
2237 ainfo->length = cinfo->xlen;
2239 else if (ainfo->length <= (2 * cinfo->xlen))
2241 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2242 ainfo->length = 2 * cinfo->xlen;
2245 /* Recalculate the alignment requirement. */
2246 ainfo->align = riscv_type_alignment (ainfo->type);
2247 riscv_call_arg_scalar_int (ainfo, cinfo);
2251 riscv_call_arg_scalar_float (ainfo, cinfo);
2254 case TYPE_CODE_COMPLEX:
2255 riscv_call_arg_complex_float (ainfo, cinfo);
2258 case TYPE_CODE_STRUCT:
2259 riscv_call_arg_struct (ainfo, cinfo);
2263 riscv_call_arg_scalar_int (ainfo, cinfo);
2268 /* Used for printing debug information about the call argument location in
2269 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2270 addresses for the location of pass-by-reference and
2271 arguments-on-the-stack memory areas. */
2274 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2275 struct riscv_arg_info *info,
2276 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2278 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2279 TYPE_SAFE_NAME (info->type), info->length, info->align);
2280 switch (info->argloc[0].loc_type)
2282 case riscv_arg_info::location::in_reg:
2284 (stream, ", register %s",
2285 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2286 if (info->argloc[0].c_length < info->length)
2288 switch (info->argloc[1].loc_type)
2290 case riscv_arg_info::location::in_reg:
2292 (stream, ", register %s",
2293 gdbarch_register_name (gdbarch,
2294 info->argloc[1].loc_data.regno));
2297 case riscv_arg_info::location::on_stack:
2298 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2299 info->argloc[1].loc_data.offset);
2302 case riscv_arg_info::location::by_ref:
2304 /* The second location should never be a reference, any
2305 argument being passed by reference just places its address
2306 in the first location and is done. */
2307 error (_("invalid argument location"));
2311 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2312 fprintf_unfiltered (stream, " (offset 0x%x)",
2313 info->argloc[1].c_offset);
2317 case riscv_arg_info::location::on_stack:
2318 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2319 info->argloc[0].loc_data.offset);
2322 case riscv_arg_info::location::by_ref:
2324 (stream, ", by reference, data at offset 0x%x (%s)",
2325 info->argloc[0].loc_data.offset,
2326 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2327 if (info->argloc[1].loc_type
2328 == riscv_arg_info::location::in_reg)
2330 (stream, ", address in register %s",
2331 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2334 gdb_assert (info->argloc[1].loc_type
2335 == riscv_arg_info::location::on_stack);
2337 (stream, ", address on stack at offset 0x%x (%s)",
2338 info->argloc[1].loc_data.offset,
2339 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2344 gdb_assert_not_reached (_("unknown argument location type"));
2348 /* Implement the push dummy call gdbarch callback. */
2351 riscv_push_dummy_call (struct gdbarch *gdbarch,
2352 struct value *function,
2353 struct regcache *regcache,
2356 struct value **args,
2359 CORE_ADDR struct_addr)
2362 CORE_ADDR sp_args, sp_refs;
2363 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2365 struct riscv_arg_info *arg_info =
2366 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2368 struct riscv_call_info call_info (gdbarch);
2372 /* We'll use register $a0 if we're returning a struct. */
2374 ++call_info.int_regs.next_regnum;
2376 for (i = 0; i < nargs; ++i)
2378 struct value *arg_value;
2379 struct type *arg_type;
2380 struct riscv_arg_info *info = &arg_info[i];
2382 arg_value = args[i];
2383 arg_type = check_typedef (value_type (arg_value));
2385 riscv_arg_location (gdbarch, info, &call_info, arg_type);
2387 if (info->type != arg_type)
2388 arg_value = value_cast (info->type, arg_value);
2389 info->contents = value_contents (arg_value);
2392 /* Adjust the stack pointer and align it. */
2393 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2394 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2396 if (riscv_debug_infcall > 0)
2398 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2399 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2400 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2401 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2402 call_info.xlen, call_info.flen);
2404 fprintf_unfiltered (gdb_stdlog,
2405 "[*] struct return pointer in register $A0\n");
2406 for (i = 0; i < nargs; ++i)
2408 struct riscv_arg_info *info = &arg_info [i];
2410 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2411 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2412 fprintf_unfiltered (gdb_stdlog, "\n");
2414 if (call_info.memory.arg_offset > 0
2415 || call_info.memory.ref_offset > 0)
2417 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2418 core_addr_to_string (osp));
2419 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2420 call_info.memory.arg_offset);
2421 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2422 call_info.memory.ref_offset);
2423 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2424 core_addr_to_string_nz (osp - sp));
2428 /* Now load the argument into registers, or onto the stack. */
2432 gdb_byte buf[sizeof (LONGEST)];
2434 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2435 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2438 for (i = 0; i < nargs; ++i)
2441 int second_arg_length = 0;
2442 const gdb_byte *second_arg_data;
2443 struct riscv_arg_info *info = &arg_info [i];
2445 gdb_assert (info->length > 0);
2447 switch (info->argloc[0].loc_type)
2449 case riscv_arg_info::location::in_reg:
2451 gdb_byte tmp [sizeof (ULONGEST)];
2453 gdb_assert (info->argloc[0].c_length <= info->length);
2454 /* FP values in FP registers must be NaN-boxed. */
2455 if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno)
2456 && info->argloc[0].c_length < call_info.flen)
2457 memset (tmp, -1, sizeof (tmp));
2459 memset (tmp, 0, sizeof (tmp));
2460 memcpy (tmp, info->contents, info->argloc[0].c_length);
2461 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2463 ((info->argloc[0].c_length < info->length)
2464 ? info->argloc[1].c_length : 0);
2465 second_arg_data = info->contents + info->argloc[1].c_offset;
2469 case riscv_arg_info::location::on_stack:
2470 dst = sp_args + info->argloc[0].loc_data.offset;
2471 write_memory (dst, info->contents, info->length);
2472 second_arg_length = 0;
2475 case riscv_arg_info::location::by_ref:
2476 dst = sp_refs + info->argloc[0].loc_data.offset;
2477 write_memory (dst, info->contents, info->length);
2479 second_arg_length = call_info.xlen;
2480 second_arg_data = (gdb_byte *) &dst;
2484 gdb_assert_not_reached (_("unknown argument location type"));
2487 if (second_arg_length > 0)
2489 switch (info->argloc[1].loc_type)
2491 case riscv_arg_info::location::in_reg:
2493 gdb_byte tmp [sizeof (ULONGEST)];
2495 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2496 && second_arg_length <= call_info.flen)
2497 || second_arg_length <= call_info.xlen);
2498 /* FP values in FP registers must be NaN-boxed. */
2499 if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2500 && second_arg_length < call_info.flen)
2501 memset (tmp, -1, sizeof (tmp));
2503 memset (tmp, 0, sizeof (tmp));
2504 memcpy (tmp, second_arg_data, second_arg_length);
2505 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2509 case riscv_arg_info::location::on_stack:
2513 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2514 write_memory (arg_addr, second_arg_data, second_arg_length);
2518 case riscv_arg_info::location::by_ref:
2520 /* The second location should never be a reference, any
2521 argument being passed by reference just places its address
2522 in the first location and is done. */
2523 error (_("invalid argument location"));
2529 /* Set the dummy return value to bp_addr.
2530 A dummy breakpoint will be setup to execute the call. */
2532 if (riscv_debug_infcall > 0)
2533 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2534 core_addr_to_string (bp_addr));
2535 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2537 /* Finally, update the stack pointer. */
2539 if (riscv_debug_infcall > 0)
2540 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2541 core_addr_to_string (sp));
2542 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2547 /* Implement the return_value gdbarch method. */
2549 static enum return_value_convention
2550 riscv_return_value (struct gdbarch *gdbarch,
2551 struct value *function,
2553 struct regcache *regcache,
2555 const gdb_byte *writebuf)
2557 struct riscv_call_info call_info (gdbarch);
2558 struct riscv_arg_info info;
2559 struct type *arg_type;
2561 arg_type = check_typedef (type);
2562 riscv_arg_location (gdbarch, &info, &call_info, arg_type);
2564 if (riscv_debug_infcall > 0)
2566 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2567 fprintf_unfiltered (gdb_stdlog, "[R] ");
2568 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2569 fprintf_unfiltered (gdb_stdlog, "\n");
2572 if (readbuf != nullptr || writebuf != nullptr)
2576 switch (info.argloc[0].loc_type)
2578 /* Return value in register(s). */
2579 case riscv_arg_info::location::in_reg:
2581 regnum = info.argloc[0].loc_data.regno;
2584 regcache->cooked_read (regnum, readbuf);
2587 regcache->cooked_write (regnum, writebuf);
2589 /* A return value in register can have a second part in a
2591 if (info.argloc[0].c_length < info.length)
2593 switch (info.argloc[1].loc_type)
2595 case riscv_arg_info::location::in_reg:
2596 regnum = info.argloc[1].loc_data.regno;
2600 readbuf += info.argloc[1].c_offset;
2601 regcache->cooked_read (regnum, readbuf);
2606 writebuf += info.argloc[1].c_offset;
2607 regcache->cooked_write (regnum, writebuf);
2611 case riscv_arg_info::location::by_ref:
2612 case riscv_arg_info::location::on_stack:
2614 error (_("invalid argument location"));
2621 /* Return value by reference will have its address in A0. */
2622 case riscv_arg_info::location::by_ref:
2626 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2628 if (readbuf != nullptr)
2629 read_memory (addr, readbuf, info.length);
2630 if (writebuf != nullptr)
2631 write_memory (addr, writebuf, info.length);
2635 case riscv_arg_info::location::on_stack:
2637 error (_("invalid argument location"));
2642 switch (info.argloc[0].loc_type)
2644 case riscv_arg_info::location::in_reg:
2645 return RETURN_VALUE_REGISTER_CONVENTION;
2646 case riscv_arg_info::location::by_ref:
2647 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2648 case riscv_arg_info::location::on_stack:
2650 error (_("invalid argument location"));
2654 /* Implement the frame_align gdbarch method. */
2657 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2659 return align_down (addr, 16);
2662 /* Implement the unwind_pc gdbarch method. */
2665 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2667 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2670 /* Implement the unwind_sp gdbarch method. */
2673 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2675 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2678 /* Implement the dummy_id gdbarch method. */
2680 static struct frame_id
2681 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2683 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2684 get_frame_pc (this_frame));
2687 /* Generate, or return the cached frame cache for the RiscV frame
2690 static struct riscv_unwind_cache *
2691 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2693 CORE_ADDR pc, start_addr;
2694 struct riscv_unwind_cache *cache;
2695 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2698 if ((*this_cache) != NULL)
2699 return (struct riscv_unwind_cache *) *this_cache;
2701 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2702 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2703 (*this_cache) = cache;
2705 /* Scan the prologue, filling in the cache. */
2706 start_addr = get_frame_func (this_frame);
2707 pc = get_frame_pc (this_frame);
2708 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2710 /* We can now calculate the frame base address. */
2712 = (get_frame_register_signed (this_frame, cache->frame_base_reg)
2713 + cache->frame_base_offset);
2714 if (riscv_debug_unwinder)
2715 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2716 core_addr_to_string (cache->frame_base),
2717 gdbarch_register_name (gdbarch,
2718 cache->frame_base_reg),
2719 cache->frame_base_offset);
2721 /* The prologue scanner sets the address of registers stored to the stack
2722 as the offset of that register from the frame base. The prologue
2723 scanner doesn't know the actual frame base value, and so is unable to
2724 compute the exact address. We do now know the frame base value, so
2725 update the address of registers stored to the stack. */
2726 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2727 for (regno = 0; regno < numregs; ++regno)
2729 if (trad_frame_addr_p (cache->regs, regno))
2730 cache->regs[regno].addr += cache->frame_base;
2733 /* The previous $pc can be found wherever the $ra value can be found.
2734 The previous $ra value is gone, this would have been stored be the
2735 previous frame if required. */
2736 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2737 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2739 /* Build the frame id. */
2740 cache->this_id = frame_id_build (cache->frame_base, start_addr);
2742 /* The previous $sp value is the frame base value. */
2743 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2749 /* Implement the this_id callback for RiscV frame unwinder. */
2752 riscv_frame_this_id (struct frame_info *this_frame,
2753 void **prologue_cache,
2754 struct frame_id *this_id)
2756 struct riscv_unwind_cache *cache;
2760 cache = riscv_frame_cache (this_frame, prologue_cache);
2761 *this_id = cache->this_id;
2763 CATCH (ex, RETURN_MASK_ERROR)
2765 /* Ignore errors, this leaves the frame id as the predefined outer
2766 frame id which terminates the backtrace at this point. */
2771 /* Implement the prev_register callback for RiscV frame unwinder. */
2773 static struct value *
2774 riscv_frame_prev_register (struct frame_info *this_frame,
2775 void **prologue_cache,
2778 struct riscv_unwind_cache *cache;
2780 cache = riscv_frame_cache (this_frame, prologue_cache);
2781 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
2784 /* Structure defining the RiscV normal frame unwind functions. Since we
2785 are the fallback unwinder (DWARF unwinder is used first), we use the
2786 default frame sniffer, which always accepts the frame. */
2788 static const struct frame_unwind riscv_frame_unwind =
2790 /*.type =*/ NORMAL_FRAME,
2791 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2792 /*.this_id =*/ riscv_frame_this_id,
2793 /*.prev_register =*/ riscv_frame_prev_register,
2794 /*.unwind_data =*/ NULL,
2795 /*.sniffer =*/ default_frame_sniffer,
2796 /*.dealloc_cache =*/ NULL,
2797 /*.prev_arch =*/ NULL,
2800 /* Initialize the current architecture based on INFO. If possible,
2801 re-use an architecture from ARCHES, which is a list of
2802 architectures already created during this debugging session.
2804 Called e.g. at program startup, when reading a core file, and when
2805 reading a binary file. */
2807 static struct gdbarch *
2808 riscv_gdbarch_init (struct gdbarch_info info,
2809 struct gdbarch_list *arches)
2811 struct gdbarch *gdbarch;
2812 struct gdbarch_tdep *tdep;
2813 struct gdbarch_tdep tmp_tdep;
2816 /* Ideally, we'd like to get as much information from the target for
2817 things like register size, and whether the target has floating point
2818 hardware. However, there are some things that the target can't tell
2819 us, like, what ABI is being used.
2821 So, for now, we take as much information as possible from the ELF,
2822 including things like register size, and FP hardware support, along
2823 with information about the ABI.
2825 Information about this target is built up in TMP_TDEP, and then we
2826 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2827 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2828 memset (&tmp_tdep, 0, sizeof (tmp_tdep));
2830 if (info.abfd != NULL
2831 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2833 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2834 int e_flags = elf_elfheader (info.abfd)->e_flags;
2836 if (eclass == ELFCLASS32)
2837 tmp_tdep.abi.fields.base_len = 1;
2838 else if (eclass == ELFCLASS64)
2839 tmp_tdep.abi.fields.base_len = 2;
2841 internal_error (__FILE__, __LINE__,
2842 _("unknown ELF header class %d"), eclass);
2844 if (e_flags & EF_RISCV_RVC)
2845 tmp_tdep.core_features |= (1 << ('C' - 'A'));
2847 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2849 tmp_tdep.abi.fields.float_abi = 2;
2850 tmp_tdep.core_features |= (1 << ('D' - 'A'));
2851 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2853 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2855 tmp_tdep.abi.fields.float_abi = 1;
2856 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2861 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2863 if (binfo->bits_per_word == 32)
2864 tmp_tdep.abi.fields.base_len = 1;
2865 else if (binfo->bits_per_word == 64)
2866 tmp_tdep.abi.fields.base_len = 2;
2868 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2869 binfo->bits_per_word);
2872 /* Find a candidate among the list of pre-declared architectures. */
2873 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2875 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2876 if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
2877 return arches->gdbarch;
2879 /* None found, so create a new architecture from the information provided. */
2880 tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
2881 gdbarch = gdbarch_alloc (&info, tdep);
2882 memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep));
2884 /* Target data types. */
2885 set_gdbarch_short_bit (gdbarch, 16);
2886 set_gdbarch_int_bit (gdbarch, 32);
2887 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2888 set_gdbarch_long_long_bit (gdbarch, 64);
2889 set_gdbarch_float_bit (gdbarch, 32);
2890 set_gdbarch_double_bit (gdbarch, 64);
2891 set_gdbarch_long_double_bit (gdbarch, 128);
2892 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2893 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2894 set_gdbarch_char_signed (gdbarch, 0);
2896 /* Information about the target architecture. */
2897 set_gdbarch_return_value (gdbarch, riscv_return_value);
2898 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
2899 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
2900 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2902 /* Register architecture. */
2903 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
2904 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
2905 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
2906 set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
2907 set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
2909 /* Functions to supply register information. */
2910 set_gdbarch_register_name (gdbarch, riscv_register_name);
2911 set_gdbarch_register_type (gdbarch, riscv_register_type);
2912 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
2913 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
2915 /* Functions to analyze frames. */
2916 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
2917 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2918 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
2920 /* Functions to access frame data. */
2921 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
2922 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
2924 /* Functions handling dummy frames. */
2925 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2926 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
2927 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
2928 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
2930 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2932 dwarf2_append_unwinders (gdbarch);
2933 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
2935 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
2936 user_reg_add (gdbarch, riscv_register_aliases[i].name,
2937 value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
2939 /* Hook in OS ABI-specific overrides, if they have been registered. */
2940 gdbarch_init_osabi (info, gdbarch);
2945 /* This decodes the current instruction and determines the address of the
2946 next instruction. */
2949 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
2951 struct gdbarch *gdbarch = regcache->arch ();
2952 struct riscv_insn insn;
2955 insn.decode (gdbarch, pc);
2956 next_pc = pc + insn.length ();
2958 if (insn.opcode () == riscv_insn::JAL)
2959 next_pc = pc + insn.imm_signed ();
2960 else if (insn.opcode () == riscv_insn::JALR)
2963 regcache->cooked_read (insn.rs1 (), &source);
2964 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
2966 else if (insn.opcode () == riscv_insn::BEQ)
2969 regcache->cooked_read (insn.rs1 (), &src1);
2970 regcache->cooked_read (insn.rs2 (), &src2);
2972 next_pc = pc + insn.imm_signed ();
2974 else if (insn.opcode () == riscv_insn::BNE)
2977 regcache->cooked_read (insn.rs1 (), &src1);
2978 regcache->cooked_read (insn.rs2 (), &src2);
2980 next_pc = pc + insn.imm_signed ();
2982 else if (insn.opcode () == riscv_insn::BLT)
2985 regcache->cooked_read (insn.rs1 (), &src1);
2986 regcache->cooked_read (insn.rs2 (), &src2);
2988 next_pc = pc + insn.imm_signed ();
2990 else if (insn.opcode () == riscv_insn::BGE)
2993 regcache->cooked_read (insn.rs1 (), &src1);
2994 regcache->cooked_read (insn.rs2 (), &src2);
2996 next_pc = pc + insn.imm_signed ();
2998 else if (insn.opcode () == riscv_insn::BLTU)
3000 ULONGEST src1, src2;
3001 regcache->cooked_read (insn.rs1 (), &src1);
3002 regcache->cooked_read (insn.rs2 (), &src2);
3004 next_pc = pc + insn.imm_signed ();
3006 else if (insn.opcode () == riscv_insn::BGEU)
3008 ULONGEST src1, src2;
3009 regcache->cooked_read (insn.rs1 (), &src1);
3010 regcache->cooked_read (insn.rs2 (), &src2);
3012 next_pc = pc + insn.imm_signed ();
3018 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3019 for the end of the sequence and put the breakpoint there. */
3022 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
3025 struct gdbarch *gdbarch = regcache->arch ();
3026 struct riscv_insn insn;
3027 CORE_ADDR cur_step_pc = pc;
3028 CORE_ADDR last_addr = 0;
3030 /* First instruction has to be a load reserved. */
3031 insn.decode (gdbarch, cur_step_pc);
3032 if (insn.opcode () != riscv_insn::LR)
3034 cur_step_pc = cur_step_pc + insn.length ();
3036 /* Next instruction should be branch to exit. */
3037 insn.decode (gdbarch, cur_step_pc);
3038 if (insn.opcode () != riscv_insn::BNE)
3040 last_addr = cur_step_pc + insn.imm_signed ();
3041 cur_step_pc = cur_step_pc + insn.length ();
3043 /* Next instruction should be store conditional. */
3044 insn.decode (gdbarch, cur_step_pc);
3045 if (insn.opcode () != riscv_insn::SC)
3047 cur_step_pc = cur_step_pc + insn.length ();
3049 /* Next instruction should be branch to start. */
3050 insn.decode (gdbarch, cur_step_pc);
3051 if (insn.opcode () != riscv_insn::BNE)
3053 if (pc != (cur_step_pc + insn.imm_signed ()))
3055 cur_step_pc = cur_step_pc + insn.length ();
3057 /* We should now be at the end of the sequence. */
3058 if (cur_step_pc != last_addr)
3061 *next_pc = cur_step_pc;
3065 /* This is called just before we want to resume the inferior, if we want to
3066 single-step it but there is no hardware or kernel single-step support. We
3067 find the target of the coming instruction and breakpoint it. */
3069 std::vector<CORE_ADDR>
3070 riscv_software_single_step (struct regcache *regcache)
3072 CORE_ADDR pc, next_pc;
3074 pc = regcache_read_pc (regcache);
3076 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
3079 next_pc = riscv_next_pc (regcache, pc);
3085 _initialize_riscv_tdep (void)
3087 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
3089 /* Add root prefix command for all "set debug riscv" and "show debug
3091 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
3092 _("RISC-V specific debug commands."),
3093 &setdebugriscvcmdlist, "set debug riscv ", 0,
3096 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
3097 _("RISC-V specific debug commands."),
3098 &showdebugriscvcmdlist, "show debug riscv ", 0,
3101 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
3102 &riscv_debug_breakpoints, _("\
3103 Set riscv breakpoint debugging."), _("\
3104 Show riscv breakpoint debugging."), _("\
3105 When non-zero, print debugging information for the riscv specific parts\n\
3106 of the breakpoint mechanism."),
3108 show_riscv_debug_variable,
3109 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3111 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
3112 &riscv_debug_infcall, _("\
3113 Set riscv inferior call debugging."), _("\
3114 Show riscv inferior call debugging."), _("\
3115 When non-zero, print debugging information for the riscv specific parts\n\
3116 of the inferior call mechanism."),
3118 show_riscv_debug_variable,
3119 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3121 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
3122 &riscv_debug_unwinder, _("\
3123 Set riscv stack unwinding debugging."), _("\
3124 Show riscv stack unwinding debugging."), _("\
3125 When non-zero, print debugging information for the riscv specific parts\n\
3126 of the stack unwinding mechanism."),
3128 show_riscv_debug_variable,
3129 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3131 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3132 add_prefix_cmd ("riscv", no_class, set_riscv_command,
3133 _("RISC-V specific commands."),
3134 &setriscvcmdlist, "set riscv ", 0, &setlist);
3136 add_prefix_cmd ("riscv", no_class, show_riscv_command,
3137 _("RISC-V specific commands."),
3138 &showriscvcmdlist, "show riscv ", 0, &showlist);
3141 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
3142 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
3143 &use_compressed_breakpoints,
3145 Set debugger's use of compressed breakpoints."), _(" \
3146 Show debugger's use of compressed breakpoints."), _("\
3147 Debugging compressed code requires compressed breakpoints to be used. If\n\
3148 left to 'auto' then gdb will use them if the existing instruction is a\n\
3149 compressed instruction. If that doesn't give the correct behavior, then\n\
3150 this option can be used."),
3152 show_use_compressed_breakpoints,