1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018-2019 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
58 #include "arch/riscv.h"
60 /* The stack must be 16-byte aligned. */
61 #define SP_ALIGNMENT 16
63 /* The biggest alignment that the target supports. */
64 #define BIGGEST_ALIGNMENT 16
66 /* Define a series of is_XXX_insn functions to check if the value INSN
67 is an instance of instruction XXX. */
68 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
69 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
71 return (insn & INSN_MASK) == INSN_MATCH; \
73 #include "opcode/riscv-opc.h"
76 /* Cached information about a frame. */
78 struct riscv_unwind_cache
80 /* The register from which we can calculate the frame base. This is
81 usually $sp or $fp. */
84 /* The offset from the current value in register FRAME_BASE_REG to the
85 actual frame base address. */
86 int frame_base_offset;
88 /* Information about previous register values. */
89 struct trad_frame_saved_reg *regs;
91 /* The id for this frame. */
92 struct frame_id this_id;
94 /* The base (stack) address for this frame. This is the stack pointer
95 value on entry to this frame before any adjustments are made. */
99 /* RISC-V specific register group for CSRs. */
101 static reggroup *csr_reggroup = NULL;
103 /* A set of registers that we expect to find in a tdesc_feature. These
104 are use in RISCV_GDBARCH_INIT when processing the target description. */
106 struct riscv_register_feature
108 /* Information for a single register. */
111 /* The GDB register number for this register. */
114 /* List of names for this register. The first name in this list is the
115 preferred name, the name GDB should use when describing this
117 std::vector <const char *> names;
119 /* When true this register is required in this feature set. */
123 /* The name for this feature. This is the name used to find this feature
124 within the target description. */
127 /* List of all the registers that we expect that we might find in this
129 std::vector <struct register_info> registers;
132 /* The general x-registers feature set. */
134 static const struct riscv_register_feature riscv_xreg_feature =
136 "org.gnu.gdb.riscv.cpu",
138 { RISCV_ZERO_REGNUM + 0, { "zero", "x0" }, true },
139 { RISCV_ZERO_REGNUM + 1, { "ra", "x1" }, true },
140 { RISCV_ZERO_REGNUM + 2, { "sp", "x2" }, true },
141 { RISCV_ZERO_REGNUM + 3, { "gp", "x3" }, true },
142 { RISCV_ZERO_REGNUM + 4, { "tp", "x4" }, true },
143 { RISCV_ZERO_REGNUM + 5, { "t0", "x5" }, true },
144 { RISCV_ZERO_REGNUM + 6, { "t1", "x6" }, true },
145 { RISCV_ZERO_REGNUM + 7, { "t2", "x7" }, true },
146 { RISCV_ZERO_REGNUM + 8, { "fp", "x8", "s0" }, true },
147 { RISCV_ZERO_REGNUM + 9, { "s1", "x9" }, true },
148 { RISCV_ZERO_REGNUM + 10, { "a0", "x10" }, true },
149 { RISCV_ZERO_REGNUM + 11, { "a1", "x11" }, true },
150 { RISCV_ZERO_REGNUM + 12, { "a2", "x12" }, true },
151 { RISCV_ZERO_REGNUM + 13, { "a3", "x13" }, true },
152 { RISCV_ZERO_REGNUM + 14, { "a4", "x14" }, true },
153 { RISCV_ZERO_REGNUM + 15, { "a5", "x15" }, true },
154 { RISCV_ZERO_REGNUM + 16, { "a6", "x16" }, true },
155 { RISCV_ZERO_REGNUM + 17, { "a7", "x17" }, true },
156 { RISCV_ZERO_REGNUM + 18, { "s2", "x18" }, true },
157 { RISCV_ZERO_REGNUM + 19, { "s3", "x19" }, true },
158 { RISCV_ZERO_REGNUM + 20, { "s4", "x20" }, true },
159 { RISCV_ZERO_REGNUM + 21, { "s5", "x21" }, true },
160 { RISCV_ZERO_REGNUM + 22, { "s6", "x22" }, true },
161 { RISCV_ZERO_REGNUM + 23, { "s7", "x23" }, true },
162 { RISCV_ZERO_REGNUM + 24, { "s8", "x24" }, true },
163 { RISCV_ZERO_REGNUM + 25, { "s9", "x25" }, true },
164 { RISCV_ZERO_REGNUM + 26, { "s10", "x26" }, true },
165 { RISCV_ZERO_REGNUM + 27, { "s11", "x27" }, true },
166 { RISCV_ZERO_REGNUM + 28, { "t3", "x28" }, true },
167 { RISCV_ZERO_REGNUM + 29, { "t4", "x29" }, true },
168 { RISCV_ZERO_REGNUM + 30, { "t5", "x30" }, true },
169 { RISCV_ZERO_REGNUM + 31, { "t6", "x31" }, true },
170 { RISCV_ZERO_REGNUM + 32, { "pc" }, true }
174 /* The f-registers feature set. */
176 static const struct riscv_register_feature riscv_freg_feature =
178 "org.gnu.gdb.riscv.fpu",
180 { RISCV_FIRST_FP_REGNUM + 0, { "ft0", "f0" }, true },
181 { RISCV_FIRST_FP_REGNUM + 1, { "ft1", "f1" }, true },
182 { RISCV_FIRST_FP_REGNUM + 2, { "ft2", "f2" }, true },
183 { RISCV_FIRST_FP_REGNUM + 3, { "ft3", "f3" }, true },
184 { RISCV_FIRST_FP_REGNUM + 4, { "ft4", "f4" }, true },
185 { RISCV_FIRST_FP_REGNUM + 5, { "ft5", "f5" }, true },
186 { RISCV_FIRST_FP_REGNUM + 6, { "ft6", "f6" }, true },
187 { RISCV_FIRST_FP_REGNUM + 7, { "ft7", "f7" }, true },
188 { RISCV_FIRST_FP_REGNUM + 8, { "fs0", "f8", "s0" }, true },
189 { RISCV_FIRST_FP_REGNUM + 9, { "fs1", "f9" }, true },
190 { RISCV_FIRST_FP_REGNUM + 10, { "fa0", "f10" }, true },
191 { RISCV_FIRST_FP_REGNUM + 11, { "fa1", "f11" }, true },
192 { RISCV_FIRST_FP_REGNUM + 12, { "fa2", "f12" }, true },
193 { RISCV_FIRST_FP_REGNUM + 13, { "fa3", "f13" }, true },
194 { RISCV_FIRST_FP_REGNUM + 14, { "fa4", "f14" }, true },
195 { RISCV_FIRST_FP_REGNUM + 15, { "fa5", "f15" }, true },
196 { RISCV_FIRST_FP_REGNUM + 16, { "fa6", "f16" }, true },
197 { RISCV_FIRST_FP_REGNUM + 17, { "fa7", "f17" }, true },
198 { RISCV_FIRST_FP_REGNUM + 18, { "fs2", "f18" }, true },
199 { RISCV_FIRST_FP_REGNUM + 19, { "fs3", "f19" }, true },
200 { RISCV_FIRST_FP_REGNUM + 20, { "fs4", "f20" }, true },
201 { RISCV_FIRST_FP_REGNUM + 21, { "fs5", "f21" }, true },
202 { RISCV_FIRST_FP_REGNUM + 22, { "fs6", "f22" }, true },
203 { RISCV_FIRST_FP_REGNUM + 23, { "fs7", "f23" }, true },
204 { RISCV_FIRST_FP_REGNUM + 24, { "fs8", "f24" }, true },
205 { RISCV_FIRST_FP_REGNUM + 25, { "fs9", "f25" }, true },
206 { RISCV_FIRST_FP_REGNUM + 26, { "fs10", "f26" }, true },
207 { RISCV_FIRST_FP_REGNUM + 27, { "fs11", "f27" }, true },
208 { RISCV_FIRST_FP_REGNUM + 28, { "ft8", "f28" }, true },
209 { RISCV_FIRST_FP_REGNUM + 29, { "ft9", "f29" }, true },
210 { RISCV_FIRST_FP_REGNUM + 30, { "ft10", "f30" }, true },
211 { RISCV_FIRST_FP_REGNUM + 31, { "ft11", "f31" }, true },
213 { RISCV_CSR_FFLAGS_REGNUM, { "fflags" }, true },
214 { RISCV_CSR_FRM_REGNUM, { "frm" }, true },
215 { RISCV_CSR_FCSR_REGNUM, { "fcsr" }, true },
220 /* Set of virtual registers. These are not physical registers on the
221 hardware, but might be available from the target. These are not pseudo
222 registers, reading these really does result in a register read from the
223 target, it is just that there might not be a physical register backing
226 static const struct riscv_register_feature riscv_virtual_feature =
228 "org.gnu.gdb.riscv.virtual",
230 { RISCV_PRIV_REGNUM, { "priv" }, false }
234 /* Feature set for CSRs. This set is NOT constant as the register names
235 list for each register is not complete. The aliases are computed
236 during RISCV_CREATE_CSR_ALIASES. */
238 static struct riscv_register_feature riscv_csr_feature =
240 "org.gnu.gdb.riscv.csr",
242 #define DECLARE_CSR(NAME,VALUE) \
243 { RISCV_ ## VALUE ## _REGNUM, { # NAME }, false },
244 #include "opcode/riscv-opc.h"
249 /* Complete RISCV_CSR_FEATURE, building the CSR alias names and adding them
250 to the name list for each register. */
253 riscv_create_csr_aliases ()
255 for (auto ® : riscv_csr_feature.registers)
257 int csr_num = reg.regnum - RISCV_FIRST_CSR_REGNUM;
258 const char *alias = xstrprintf ("csr%d", csr_num);
259 reg.names.push_back (alias);
263 /* Controls whether we place compressed breakpoints or not. When in auto
264 mode GDB tries to determine if the target supports compressed
265 breakpoints, and uses them if it does. */
267 static enum auto_boolean use_compressed_breakpoints;
269 /* The show callback for 'show riscv use-compressed-breakpoints'. */
272 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
273 struct cmd_list_element *c,
276 fprintf_filtered (file,
277 _("Debugger's use of compressed breakpoints is set "
281 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
283 static struct cmd_list_element *setriscvcmdlist = NULL;
284 static struct cmd_list_element *showriscvcmdlist = NULL;
286 /* The show callback for the 'show riscv' prefix command. */
289 show_riscv_command (const char *args, int from_tty)
291 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
294 /* The set callback for the 'set riscv' prefix command. */
297 set_riscv_command (const char *args, int from_tty)
300 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
301 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
304 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
306 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
307 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
309 /* The show callback for the 'show debug riscv' prefix command. */
312 show_debug_riscv_command (const char *args, int from_tty)
314 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
317 /* The set callback for the 'set debug riscv' prefix command. */
320 set_debug_riscv_command (const char *args, int from_tty)
323 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
324 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
327 /* The show callback for all 'show debug riscv VARNAME' variables. */
330 show_riscv_debug_variable (struct ui_file *file, int from_tty,
331 struct cmd_list_element *c,
334 fprintf_filtered (file,
335 _("RiscV debug variable `%s' is set to: %s\n"),
339 /* When this is set to non-zero debugging information about breakpoint
340 kinds will be printed. */
342 static unsigned int riscv_debug_breakpoints = 0;
344 /* When this is set to non-zero debugging information about inferior calls
347 static unsigned int riscv_debug_infcall = 0;
349 /* When this is set to non-zero debugging information about stack unwinding
352 static unsigned int riscv_debug_unwinder = 0;
354 /* When this is set to non-zero debugging information about gdbarch
355 initialisation will be printed. */
357 static unsigned int riscv_debug_gdbarch = 0;
359 /* See riscv-tdep.h. */
362 riscv_isa_xlen (struct gdbarch *gdbarch)
364 return gdbarch_tdep (gdbarch)->isa_features.xlen;
367 /* See riscv-tdep.h. */
370 riscv_abi_xlen (struct gdbarch *gdbarch)
372 return gdbarch_tdep (gdbarch)->abi_features.xlen;
375 /* See riscv-tdep.h. */
378 riscv_isa_flen (struct gdbarch *gdbarch)
380 return gdbarch_tdep (gdbarch)->isa_features.flen;
383 /* See riscv-tdep.h. */
386 riscv_abi_flen (struct gdbarch *gdbarch)
388 return gdbarch_tdep (gdbarch)->abi_features.flen;
391 /* Return true if the target for GDBARCH has floating point hardware. */
394 riscv_has_fp_regs (struct gdbarch *gdbarch)
396 return (riscv_isa_flen (gdbarch) > 0);
399 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
402 riscv_has_fp_abi (struct gdbarch *gdbarch)
404 return gdbarch_tdep (gdbarch)->abi_features.flen > 0;
407 /* Return true if REGNO is a floating pointer register. */
410 riscv_is_fp_regno_p (int regno)
412 return (regno >= RISCV_FIRST_FP_REGNUM
413 && regno <= RISCV_LAST_FP_REGNUM);
416 /* Implement the breakpoint_kind_from_pc gdbarch method. */
419 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
421 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
423 bool unaligned_p = false;
426 /* Some targets don't support unaligned reads. The address can only
427 be unaligned if the C extension is supported. So it is safe to
428 use a compressed breakpoint in this case. */
433 /* Read the opcode byte to determine the instruction length. */
434 read_code (*pcptr, buf, 1);
437 if (riscv_debug_breakpoints)
439 const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
440 ? "C.EBREAK" : "EBREAK");
442 fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ",
443 bp, paddress (gdbarch, *pcptr));
445 fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n");
447 fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n",
448 riscv_insn_length (buf[0]));
450 if (unaligned_p || riscv_insn_length (buf[0]) == 2)
455 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
461 /* Implement the sw_breakpoint_from_kind gdbarch method. */
463 static const gdb_byte *
464 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
466 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
467 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
477 gdb_assert_not_reached (_("unhandled breakpoint kind"));
481 /* Callback function for user_reg_add. */
483 static struct value *
484 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
486 const int *reg_p = (const int *) baton;
487 return value_of_register (*reg_p, frame);
490 /* Implement the register_name gdbarch method. This is used instead of
491 the function supplied by calling TDESC_USE_REGISTERS so that we can
492 ensure the preferred names are offered. */
495 riscv_register_name (struct gdbarch *gdbarch, int regnum)
497 /* Lookup the name through the target description. If we get back NULL
498 then this is an unknown register. If we do get a name back then we
499 look up the registers preferred name below. */
500 const char *name = tdesc_register_name (gdbarch, regnum);
501 if (name == NULL || name[0] == '\0')
504 if (regnum >= RISCV_ZERO_REGNUM && regnum < RISCV_FIRST_FP_REGNUM)
506 gdb_assert (regnum < riscv_xreg_feature.registers.size ());
507 return riscv_xreg_feature.registers[regnum].names[0];
510 if (regnum >= RISCV_FIRST_FP_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
512 if (riscv_has_fp_regs (gdbarch))
514 regnum -= RISCV_FIRST_FP_REGNUM;
515 gdb_assert (regnum < riscv_freg_feature.registers.size ());
516 return riscv_freg_feature.registers[regnum].names[0];
522 /* Check that there's no gap between the set of registers handled above,
523 and the set of registers handled next. */
524 gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM);
526 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
528 #define DECLARE_CSR(NAME,VALUE) \
529 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
533 #include "opcode/riscv-opc.h"
538 if (regnum == RISCV_PRIV_REGNUM)
541 /* It is possible that that the target provides some registers that GDB
542 is unaware of, in that case just return the NAME from the target
547 /* Construct a type for 64-bit FP registers. */
550 riscv_fpreg_d_type (struct gdbarch *gdbarch)
552 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
554 if (tdep->riscv_fpreg_d_type == nullptr)
556 const struct builtin_type *bt = builtin_type (gdbarch);
558 /* The type we're building is this: */
560 union __gdb_builtin_type_fpreg_d
569 t = arch_composite_type (gdbarch,
570 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
571 append_composite_type_field (t, "float", bt->builtin_float);
572 append_composite_type_field (t, "double", bt->builtin_double);
574 TYPE_NAME (t) = "builtin_type_fpreg_d";
575 tdep->riscv_fpreg_d_type = t;
578 return tdep->riscv_fpreg_d_type;
581 /* Implement the register_type gdbarch method. This is installed as an
582 for the override setup by TDESC_USE_REGISTERS, for most registers we
583 delegate the type choice to the target description, but for a few
584 registers we try to improve the types if the target description has
585 taken a simplistic approach. */
588 riscv_register_type (struct gdbarch *gdbarch, int regnum)
590 struct type *type = tdesc_register_type (gdbarch, regnum);
591 int xlen = riscv_isa_xlen (gdbarch);
593 /* We want to perform some specific type "fixes" in cases where we feel
594 that we really can do better than the target description. For all
595 other cases we just return what the target description says. */
596 if (riscv_is_fp_regno_p (regnum))
598 /* This spots the case for RV64 where the double is defined as
599 either 'ieee_double' or 'float' (which is the generic name that
600 converts to 'double' on 64-bit). In these cases its better to
601 present the registers using a union type. */
602 int flen = riscv_isa_flen (gdbarch);
604 && TYPE_CODE (type) == TYPE_CODE_FLT
605 && TYPE_LENGTH (type) == flen
606 && (strcmp (TYPE_NAME (type), "builtin_type_ieee_double") == 0
607 || strcmp (TYPE_NAME (type), "double") == 0))
608 type = riscv_fpreg_d_type (gdbarch);
611 if ((regnum == gdbarch_pc_regnum (gdbarch)
612 || regnum == RISCV_RA_REGNUM
613 || regnum == RISCV_FP_REGNUM
614 || regnum == RISCV_SP_REGNUM
615 || regnum == RISCV_GP_REGNUM
616 || regnum == RISCV_TP_REGNUM)
617 && TYPE_CODE (type) == TYPE_CODE_INT
618 && TYPE_LENGTH (type) == xlen)
620 /* This spots the case where some interesting registers are defined
621 as simple integers of the expected size, we force these registers
622 to be pointers as we believe that is more useful. */
623 if (regnum == gdbarch_pc_regnum (gdbarch)
624 || regnum == RISCV_RA_REGNUM)
625 type = builtin_type (gdbarch)->builtin_func_ptr;
626 else if (regnum == RISCV_FP_REGNUM
627 || regnum == RISCV_SP_REGNUM
628 || regnum == RISCV_GP_REGNUM
629 || regnum == RISCV_TP_REGNUM)
630 type = builtin_type (gdbarch)->builtin_data_ptr;
636 /* Helper for riscv_print_registers_info, prints info for a single register
640 riscv_print_one_register_info (struct gdbarch *gdbarch,
641 struct ui_file *file,
642 struct frame_info *frame,
645 const char *name = gdbarch_register_name (gdbarch, regnum);
647 struct type *regtype;
648 int print_raw_format;
649 enum tab_stops { value_column_1 = 15 };
651 fputs_filtered (name, file);
652 print_spaces_filtered (value_column_1 - strlen (name), file);
656 val = value_of_register (regnum, frame);
657 regtype = value_type (val);
659 CATCH (ex, RETURN_MASK_ERROR)
661 /* Handle failure to read a register without interrupting the entire
662 'info registers' flow. */
663 fprintf_filtered (file, "%s\n", ex.message);
668 print_raw_format = (value_entirely_available (val)
669 && !value_optimized_out (val));
671 if (TYPE_CODE (regtype) == TYPE_CODE_FLT
672 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
673 && TYPE_NFIELDS (regtype) == 2
674 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
675 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
676 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
677 && TYPE_NFIELDS (regtype) == 3
678 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
679 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
680 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
682 struct value_print_options opts;
683 const gdb_byte *valaddr = value_contents_for_printing (val);
684 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
686 get_user_print_options (&opts);
690 value_embedded_offset (val), 0,
691 file, 0, val, &opts, current_language);
693 if (print_raw_format)
695 fprintf_filtered (file, "\t(raw ");
696 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
698 fprintf_filtered (file, ")");
703 struct value_print_options opts;
705 /* Print the register in hex. */
706 get_formatted_print_options (&opts, 'x');
709 value_embedded_offset (val), 0,
710 file, 0, val, &opts, current_language);
712 if (print_raw_format)
714 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
717 int size = register_size (gdbarch, regnum);
720 /* The SD field is always in the upper bit of MSTATUS, regardless
721 of the number of bits in MSTATUS. */
722 d = value_as_long (val);
724 fprintf_filtered (file,
725 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
726 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
727 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
728 (int) ((d >> (xlen - 1)) & 0x1),
729 (int) ((d >> 24) & 0x1f),
730 (int) ((d >> 19) & 0x1),
731 (int) ((d >> 18) & 0x1),
732 (int) ((d >> 17) & 0x1),
733 (int) ((d >> 15) & 0x3),
734 (int) ((d >> 13) & 0x3),
735 (int) ((d >> 11) & 0x3),
736 (int) ((d >> 9) & 0x3),
737 (int) ((d >> 8) & 0x1),
738 (int) ((d >> 7) & 0x1),
739 (int) ((d >> 6) & 0x1),
740 (int) ((d >> 5) & 0x1),
741 (int) ((d >> 4) & 0x1),
742 (int) ((d >> 3) & 0x1),
743 (int) ((d >> 2) & 0x1),
744 (int) ((d >> 1) & 0x1),
745 (int) ((d >> 0) & 0x1));
747 else if (regnum == RISCV_CSR_MISA_REGNUM)
752 int size = register_size (gdbarch, regnum);
754 /* The MXL field is always in the upper two bits of MISA,
755 regardless of the number of bits in MISA. Mask out other
756 bits to ensure we have a positive value. */
757 d = value_as_long (val);
758 base = (d >> ((size * 8) - 2)) & 0x3;
761 for (; base > 0; base--)
763 fprintf_filtered (file, "\tRV%d", xlen);
765 for (i = 0; i < 26; i++)
768 fprintf_filtered (file, "%c", 'A' + i);
771 else if (regnum == RISCV_CSR_FCSR_REGNUM
772 || regnum == RISCV_CSR_FFLAGS_REGNUM
773 || regnum == RISCV_CSR_FRM_REGNUM)
777 d = value_as_long (val);
779 fprintf_filtered (file, "\t");
780 if (regnum != RISCV_CSR_FRM_REGNUM)
781 fprintf_filtered (file,
782 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
783 (int) ((d >> 5) & 0x7),
784 (int) ((d >> 4) & 0x1),
785 (int) ((d >> 3) & 0x1),
786 (int) ((d >> 2) & 0x1),
787 (int) ((d >> 1) & 0x1),
788 (int) ((d >> 0) & 0x1));
790 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
792 static const char * const sfrm[] =
794 "RNE (round to nearest; ties to even)",
795 "RTZ (Round towards zero)",
796 "RDN (Round down towards -INF)",
797 "RUP (Round up towards +INF)",
798 "RMM (Round to nearest; ties to max magnitude)",
801 "dynamic rounding mode",
803 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
804 ? (d >> 5) : d) & 0x3;
806 fprintf_filtered (file, "%sFRM:%i [%s]",
807 (regnum == RISCV_CSR_FCSR_REGNUM
812 else if (regnum == RISCV_PRIV_REGNUM)
817 d = value_as_long (val);
822 static const char * const sprv[] =
829 fprintf_filtered (file, "\tprv:%d [%s]",
833 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
837 /* If not a vector register, print it also according to its
839 if (TYPE_VECTOR (regtype) == 0)
841 get_user_print_options (&opts);
843 fprintf_filtered (file, "\t");
845 value_embedded_offset (val), 0,
846 file, 0, val, &opts, current_language);
851 fprintf_filtered (file, "\n");
854 /* Return true if REGNUM is a valid CSR register. The CSR register space
855 is sparsely populated, so not every number is a named CSR. */
858 riscv_is_regnum_a_named_csr (int regnum)
860 gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
861 && regnum <= RISCV_LAST_CSR_REGNUM);
865 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
866 #include "opcode/riscv-opc.h"
875 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
879 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
880 struct reggroup *reggroup)
882 /* Used by 'info registers' and 'info registers <groupname>'. */
884 if (gdbarch_register_name (gdbarch, regnum) == NULL
885 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
888 if (regnum > RISCV_LAST_REGNUM)
890 int ret = tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup);
894 return default_register_reggroup_p (gdbarch, regnum, reggroup);
897 if (reggroup == all_reggroup)
899 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
901 if (riscv_is_regnum_a_named_csr (regnum))
905 else if (reggroup == float_reggroup)
906 return (riscv_is_fp_regno_p (regnum)
907 || regnum == RISCV_CSR_FCSR_REGNUM
908 || regnum == RISCV_CSR_FFLAGS_REGNUM
909 || regnum == RISCV_CSR_FRM_REGNUM);
910 else if (reggroup == general_reggroup)
911 return regnum < RISCV_FIRST_FP_REGNUM;
912 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
914 if (riscv_has_fp_regs (gdbarch))
915 return (regnum <= RISCV_LAST_FP_REGNUM
916 || regnum == RISCV_CSR_FCSR_REGNUM
917 || regnum == RISCV_CSR_FFLAGS_REGNUM
918 || regnum == RISCV_CSR_FRM_REGNUM);
920 return regnum < RISCV_FIRST_FP_REGNUM;
922 else if (reggroup == system_reggroup || reggroup == csr_reggroup)
924 if (regnum == RISCV_PRIV_REGNUM)
926 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
928 if (riscv_is_regnum_a_named_csr (regnum))
932 else if (reggroup == vector_reggroup)
938 /* Implement the print_registers_info gdbarch method. This is used by
939 'info registers' and 'info all-registers'. */
942 riscv_print_registers_info (struct gdbarch *gdbarch,
943 struct ui_file *file,
944 struct frame_info *frame,
945 int regnum, int print_all)
949 /* Print one specified register. */
950 if (gdbarch_register_name (gdbarch, regnum) == NULL
951 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
952 error (_("Not a valid register for the current processor type"));
953 riscv_print_one_register_info (gdbarch, file, frame, regnum);
957 struct reggroup *reggroup;
960 reggroup = all_reggroup;
962 reggroup = general_reggroup;
964 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
966 /* Zero never changes, so might as well hide by default. */
967 if (regnum == RISCV_ZERO_REGNUM && !print_all)
970 /* Registers with no name are not valid on this ISA. */
971 if (gdbarch_register_name (gdbarch, regnum) == NULL
972 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
975 /* Is the register in the group we're interested in? */
976 if (!gdbarch_register_reggroup_p (gdbarch, regnum, reggroup))
979 riscv_print_one_register_info (gdbarch, file, frame, regnum);
984 /* Class that handles one decoded RiscV instruction. */
990 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
993 /* Unknown value is used at initialisation time. */
996 /* These instructions are all the ones we are interested in during the
1006 /* These are needed for software breakopint support. */
1015 /* These are needed for stepping over atomic sequences. */
1019 /* Other instructions are not interesting during the prologue scan, and
1034 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1036 /* Get the length of the instruction in bytes. */
1038 { return m_length; }
1040 /* Get the opcode for this instruction. */
1041 enum opcode opcode () const
1042 { return m_opcode; }
1044 /* Get destination register field for this instruction. This is only
1045 valid if the OPCODE implies there is such a field for this
1050 /* Get the RS1 register field for this instruction. This is only valid
1051 if the OPCODE implies there is such a field for this instruction. */
1055 /* Get the RS2 register field for this instruction. This is only valid
1056 if the OPCODE implies there is such a field for this instruction. */
1060 /* Get the immediate for this instruction in signed form. This is only
1061 valid if the OPCODE implies there is such a field for this
1063 int imm_signed () const
1068 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1069 int decode_register_index (unsigned long opcode, int offset)
1071 return (opcode >> offset) & 0x1F;
1074 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1075 int decode_register_index_short (unsigned long opcode, int offset)
1077 return ((opcode >> offset) & 0x7) + 8;
1080 /* Helper for DECODE, decode 32-bit R-type instruction. */
1081 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1084 m_rd = decode_register_index (ival, OP_SH_RD);
1085 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1086 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1089 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1090 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1093 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1094 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1097 /* Helper for DECODE, decode 32-bit I-type instruction. */
1098 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1101 m_rd = decode_register_index (ival, OP_SH_RD);
1102 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1103 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1106 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1107 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1110 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1111 m_imm.s = EXTRACT_RVC_IMM (ival);
1114 /* Helper for DECODE, decode 32-bit S-type instruction. */
1115 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1118 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1119 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1120 m_imm.s = EXTRACT_STYPE_IMM (ival);
1123 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1124 encoding is different for each CS format instruction, so extracting
1125 the immediate is left up to the caller, who should pass the extracted
1126 immediate value through in IMM. */
1127 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1131 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1132 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1135 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1136 encoding is different for each CSS format instruction, so extracting
1137 the immediate is left up to the caller, who should pass the extracted
1138 immediate value through in IMM. */
1139 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1143 m_rs1 = RISCV_SP_REGNUM;
1144 /* Not a compressed register number in this case. */
1145 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1148 /* Helper for DECODE, decode 32-bit U-type instruction. */
1149 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1152 m_rd = decode_register_index (ival, OP_SH_RD);
1153 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1156 /* Helper for DECODE, decode 32-bit J-type instruction. */
1157 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1160 m_rd = decode_register_index (ival, OP_SH_RD);
1161 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1164 /* Helper for DECODE, decode 32-bit J-type instruction. */
1165 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1168 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1171 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1174 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1175 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1176 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1179 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1182 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1183 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1186 /* Fetch instruction from target memory at ADDR, return the content of
1187 the instruction, and update LEN with the instruction length. */
1188 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1189 CORE_ADDR addr, int *len);
1191 /* The length of the instruction in bytes. Should be 2 or 4. */
1194 /* The instruction opcode. */
1195 enum opcode m_opcode;
1197 /* The three possible registers an instruction might reference. Not
1198 every instruction fills in all of these registers. Which fields are
1199 valid depends on the opcode. The naming of these fields matches the
1200 naming in the riscv isa manual. */
1205 /* Possible instruction immediate. This is only valid if the instruction
1206 format contains an immediate, not all instruction, whether this is
1207 valid depends on the opcode. Despite only having one format for now
1208 the immediate is packed into a union, later instructions might require
1209 an unsigned formatted immediate, having the union in place now will
1210 reduce the need for code churn later. */
1211 union riscv_insn_immediate
1213 riscv_insn_immediate ()
1223 /* Fetch instruction from target memory at ADDR, return the content of the
1224 instruction, and update LEN with the instruction length. */
1227 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1228 CORE_ADDR addr, int *len)
1230 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1232 int instlen, status;
1234 /* All insns are at least 16 bits. */
1235 status = target_read_memory (addr, buf, 2);
1237 memory_error (TARGET_XFER_E_IO, addr);
1239 /* If we need more, grab it now. */
1240 instlen = riscv_insn_length (buf[0]);
1241 gdb_assert (instlen <= sizeof (buf));
1246 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1248 memory_error (TARGET_XFER_E_IO, addr + 2);
1251 return extract_unsigned_integer (buf, instlen, byte_order);
1254 /* Fetch from target memory an instruction at PC and decode it. This can
1255 throw an error if the memory access fails, callers are responsible for
1256 handling this error if that is appropriate. */
1259 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1263 /* Fetch the instruction, and the instructions length. */
1264 ival = fetch_instruction (gdbarch, pc, &m_length);
1268 if (is_add_insn (ival))
1269 decode_r_type_insn (ADD, ival);
1270 else if (is_addw_insn (ival))
1271 decode_r_type_insn (ADDW, ival);
1272 else if (is_addi_insn (ival))
1273 decode_i_type_insn (ADDI, ival);
1274 else if (is_addiw_insn (ival))
1275 decode_i_type_insn (ADDIW, ival);
1276 else if (is_auipc_insn (ival))
1277 decode_u_type_insn (AUIPC, ival);
1278 else if (is_lui_insn (ival))
1279 decode_u_type_insn (LUI, ival);
1280 else if (is_sd_insn (ival))
1281 decode_s_type_insn (SD, ival);
1282 else if (is_sw_insn (ival))
1283 decode_s_type_insn (SW, ival);
1284 else if (is_jal_insn (ival))
1285 decode_j_type_insn (JAL, ival);
1286 else if (is_jalr_insn (ival))
1287 decode_i_type_insn (JALR, ival);
1288 else if (is_beq_insn (ival))
1289 decode_b_type_insn (BEQ, ival);
1290 else if (is_bne_insn (ival))
1291 decode_b_type_insn (BNE, ival);
1292 else if (is_blt_insn (ival))
1293 decode_b_type_insn (BLT, ival);
1294 else if (is_bge_insn (ival))
1295 decode_b_type_insn (BGE, ival);
1296 else if (is_bltu_insn (ival))
1297 decode_b_type_insn (BLTU, ival);
1298 else if (is_bgeu_insn (ival))
1299 decode_b_type_insn (BGEU, ival);
1300 else if (is_lr_w_insn (ival))
1301 decode_r_type_insn (LR, ival);
1302 else if (is_lr_d_insn (ival))
1303 decode_r_type_insn (LR, ival);
1304 else if (is_sc_w_insn (ival))
1305 decode_r_type_insn (SC, ival);
1306 else if (is_sc_d_insn (ival))
1307 decode_r_type_insn (SC, ival);
1309 /* None of the other fields are valid in this case. */
1312 else if (m_length == 2)
1314 int xlen = riscv_isa_xlen (gdbarch);
1316 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1317 C_JALR. So must try to match C_JALR first as it has more bits in
1319 if (is_c_jalr_insn (ival))
1320 decode_cr_type_insn (JALR, ival);
1321 else if (is_c_add_insn (ival))
1322 decode_cr_type_insn (ADD, ival);
1323 /* C_ADDW is RV64 and RV128 only. */
1324 else if (xlen != 4 && is_c_addw_insn (ival))
1325 decode_cr_type_insn (ADDW, ival);
1326 else if (is_c_addi_insn (ival))
1327 decode_ci_type_insn (ADDI, ival);
1328 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1329 only and C_JAL is RV32 only. */
1330 else if (xlen != 4 && is_c_addiw_insn (ival))
1331 decode_ci_type_insn (ADDIW, ival);
1332 else if (xlen == 4 && is_c_jal_insn (ival))
1333 decode_cj_type_insn (JAL, ival);
1334 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1335 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1337 else if (is_c_addi16sp_insn (ival))
1340 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1341 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1343 else if (is_c_addi4spn_insn (ival))
1346 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1347 m_rs1 = RISCV_SP_REGNUM;
1348 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1350 else if (is_c_lui_insn (ival))
1353 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1354 m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
1356 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1357 and C_FSW is RV32 only. */
1358 else if (xlen != 4 && is_c_sd_insn (ival))
1359 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
1360 else if (is_c_sw_insn (ival))
1361 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1362 else if (is_c_swsp_insn (ival))
1363 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1364 else if (xlen != 4 && is_c_sdsp_insn (ival))
1365 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
1366 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1367 So must try to match C_JR first as it ahs more bits in mask. */
1368 else if (is_c_jr_insn (ival))
1369 decode_cr_type_insn (JALR, ival);
1370 else if (is_c_j_insn (ival))
1371 decode_cj_type_insn (JAL, ival);
1372 else if (is_c_beqz_insn (ival))
1373 decode_cb_type_insn (BEQ, ival);
1374 else if (is_c_bnez_insn (ival))
1375 decode_cb_type_insn (BNE, ival);
1377 /* None of the other fields of INSN are valid in this case. */
1381 internal_error (__FILE__, __LINE__,
1382 _("unable to decode %d byte instructions in "
1383 "prologue at %s"), m_length,
1384 core_addr_to_string (pc));
1387 /* The prologue scanner. This is currently only used for skipping the
1388 prologue of a function when the DWARF information is not sufficient.
1389 However, it is written with filling of the frame cache in mind, which
1390 is why different groups of stack setup instructions are split apart
1391 during the core of the inner loop. In the future, the intention is to
1392 extend this function to fully support building up a frame cache that
1393 can unwind register values when there is no DWARF information. */
1396 riscv_scan_prologue (struct gdbarch *gdbarch,
1397 CORE_ADDR start_pc, CORE_ADDR end_pc,
1398 struct riscv_unwind_cache *cache)
1400 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1401 CORE_ADDR end_prologue_addr = 0;
1403 /* Find an upper limit on the function prologue using the debug
1404 information. If the debug information could not be used to provide
1405 that bound, then use an arbitrary large number as the upper bound. */
1406 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1407 if (after_prologue_pc == 0)
1408 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1409 if (after_prologue_pc < end_pc)
1410 end_pc = after_prologue_pc;
1412 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1413 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1414 regs[regno] = pv_register (regno, 0);
1415 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1417 if (riscv_debug_unwinder)
1420 "Prologue scan for function starting at %s (limit %s)\n",
1421 core_addr_to_string (start_pc),
1422 core_addr_to_string (end_pc));
1424 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1426 struct riscv_insn insn;
1428 /* Decode the current instruction, and decide where the next
1429 instruction lives based on the size of this instruction. */
1430 insn.decode (gdbarch, cur_pc);
1431 gdb_assert (insn.length () > 0);
1432 next_pc = cur_pc + insn.length ();
1434 /* Look for common stack adjustment insns. */
1435 if ((insn.opcode () == riscv_insn::ADDI
1436 || insn.opcode () == riscv_insn::ADDIW)
1437 && insn.rd () == RISCV_SP_REGNUM
1438 && insn.rs1 () == RISCV_SP_REGNUM)
1440 /* Handle: addi sp, sp, -i
1441 or: addiw sp, sp, -i */
1442 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1443 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1445 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1447 else if ((insn.opcode () == riscv_insn::SW
1448 || insn.opcode () == riscv_insn::SD)
1449 && (insn.rs1 () == RISCV_SP_REGNUM
1450 || insn.rs1 () == RISCV_FP_REGNUM))
1452 /* Handle: sw reg, offset(sp)
1453 or: sd reg, offset(sp)
1454 or: sw reg, offset(s0)
1455 or: sd reg, offset(s0) */
1456 /* Instruction storing a register onto the stack. */
1457 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1458 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1459 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1460 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1463 else if (insn.opcode () == riscv_insn::ADDI
1464 && insn.rd () == RISCV_FP_REGNUM
1465 && insn.rs1 () == RISCV_SP_REGNUM)
1467 /* Handle: addi s0, sp, size */
1468 /* Instructions setting up the frame pointer. */
1469 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1470 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1472 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1474 else if ((insn.opcode () == riscv_insn::ADD
1475 || insn.opcode () == riscv_insn::ADDW)
1476 && insn.rd () == RISCV_FP_REGNUM
1477 && insn.rs1 () == RISCV_SP_REGNUM
1478 && insn.rs2 () == RISCV_ZERO_REGNUM)
1480 /* Handle: add s0, sp, 0
1481 or: addw s0, sp, 0 */
1482 /* Instructions setting up the frame pointer. */
1483 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1484 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1485 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1487 else if ((insn.opcode () == riscv_insn::ADDI
1488 && insn.rd () == RISCV_ZERO_REGNUM
1489 && insn.rs1 () == RISCV_ZERO_REGNUM
1490 && insn.imm_signed () == 0))
1492 /* Handle: add x0, x0, 0 (NOP) */
1494 else if (insn.opcode () == riscv_insn::AUIPC)
1496 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1497 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1499 else if (insn.opcode () == riscv_insn::LUI)
1501 /* Handle: lui REG, n
1502 Where REG is not gp register. */
1503 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1504 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1506 else if (insn.opcode () == riscv_insn::ADDI)
1508 /* Handle: addi REG1, REG2, IMM */
1509 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1510 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1512 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1514 else if (insn.opcode () == riscv_insn::ADD)
1516 /* Handle: addi REG1, REG2, IMM */
1517 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1518 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1519 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1520 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1524 end_prologue_addr = cur_pc;
1529 if (end_prologue_addr == 0)
1530 end_prologue_addr = cur_pc;
1532 if (riscv_debug_unwinder)
1533 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1534 core_addr_to_string (end_prologue_addr));
1538 /* Figure out if it is a frame pointer or just a stack pointer. Also
1539 the offset held in the pv_t is from the original register value to
1540 the current value, which for a grows down stack means a negative
1541 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1542 from the current value to the original value. */
1543 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1545 cache->frame_base_reg = RISCV_FP_REGNUM;
1546 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1550 cache->frame_base_reg = RISCV_SP_REGNUM;
1551 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1554 /* Assign offset from old SP to all saved registers. As we don't
1555 have the previous value for the frame base register at this
1556 point, we store the offset as the address in the trad_frame, and
1557 then convert this to an actual address later. */
1558 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1561 if (stack.find_reg (gdbarch, i, &offset))
1563 if (riscv_debug_unwinder)
1565 /* Display OFFSET as a signed value, the offsets are from
1566 the frame base address to the registers location on
1567 the stack, with a descending stack this means the
1568 offsets are always negative. */
1569 fprintf_unfiltered (gdb_stdlog,
1570 "Register $%s at stack offset %s\n",
1571 gdbarch_register_name (gdbarch, i),
1572 plongest ((LONGEST) offset));
1574 trad_frame_set_addr (cache->regs, i, offset);
1579 return end_prologue_addr;
1582 /* Implement the riscv_skip_prologue gdbarch method. */
1585 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1587 CORE_ADDR func_addr;
1589 /* See if we can determine the end of the prologue via the symbol
1590 table. If so, then return either PC, or the PC after the
1591 prologue, whichever is greater. */
1592 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1594 CORE_ADDR post_prologue_pc
1595 = skip_prologue_using_sal (gdbarch, func_addr);
1597 if (post_prologue_pc != 0)
1598 return std::max (pc, post_prologue_pc);
1601 /* Can't determine prologue from the symbol table, need to examine
1602 instructions. Pass -1 for the end address to indicate the prologue
1603 scanner can scan as far as it needs to find the end of the prologue. */
1604 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1607 /* Implement the gdbarch push dummy code callback. */
1610 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1611 CORE_ADDR funaddr, struct value **args, int nargs,
1612 struct type *value_type, CORE_ADDR *real_pc,
1613 CORE_ADDR *bp_addr, struct regcache *regcache)
1615 /* Allocate space for a breakpoint, and keep the stack correctly
1623 /* Compute the alignment of the type T. Used while setting up the
1624 arguments for a dummy call. */
1627 riscv_type_alignment (struct type *t)
1629 t = check_typedef (t);
1630 switch (TYPE_CODE (t))
1633 error (_("Could not compute alignment of type"));
1635 case TYPE_CODE_RVALUE_REF:
1637 case TYPE_CODE_ENUM:
1641 case TYPE_CODE_CHAR:
1642 case TYPE_CODE_BOOL:
1643 return TYPE_LENGTH (t);
1645 case TYPE_CODE_ARRAY:
1646 if (TYPE_VECTOR (t))
1647 return std::min (TYPE_LENGTH (t), (unsigned) BIGGEST_ALIGNMENT);
1650 case TYPE_CODE_COMPLEX:
1651 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1653 case TYPE_CODE_STRUCT:
1654 case TYPE_CODE_UNION:
1659 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1661 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1663 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1673 /* Holds information about a single argument either being passed to an
1674 inferior function, or returned from an inferior function. This includes
1675 information about the size, type, etc of the argument, and also
1676 information about how the argument will be passed (or returned). */
1678 struct riscv_arg_info
1680 /* Contents of the argument. */
1681 const gdb_byte *contents;
1683 /* Length of argument. */
1686 /* Alignment required for an argument of this type. */
1689 /* The type for this argument. */
1692 /* Each argument can have either 1 or 2 locations assigned to it. Each
1693 location describes where part of the argument will be placed. The
1694 second location is valid based on the LOC_TYPE and C_LENGTH fields
1695 of the first location (which is always valid). */
1698 /* What type of location this is. */
1701 /* Argument passed in a register. */
1704 /* Argument passed as an on stack argument. */
1707 /* Argument passed by reference. The second location is always
1708 valid for a BY_REF argument, and describes where the address
1709 of the BY_REF argument should be placed. */
1713 /* Information that depends on the location type. */
1716 /* Which register number to use. */
1719 /* The offset into the stack region. */
1723 /* The length of contents covered by this location. If this is less
1724 than the total length of the argument, then the second location
1725 will be valid, and will describe where the rest of the argument
1729 /* The offset within CONTENTS for this part of the argument. Will
1730 always be 0 for the first part. For the second part of the
1731 argument, this might be the C_LENGTH value of the first part,
1732 however, if we are passing a structure in two registers, and there's
1733 is padding between the first and second field, then this offset
1734 might be greater than the length of the first argument part. When
1735 the second argument location is not holding part of the argument
1736 value, but is instead holding the address of a reference argument,
1737 then this offset will be set to 0. */
1741 /* TRUE if this is an unnamed argument. */
1745 /* Information about a set of registers being used for passing arguments as
1746 part of a function call. The register set must be numerically
1747 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1748 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1750 struct riscv_arg_reg
1752 riscv_arg_reg (int first, int last)
1753 : next_regnum (first),
1759 /* The GDB register number to use in this set. */
1762 /* The last GDB register number to use in this set. */
1766 /* Arguments can be passed as on stack arguments, or by reference. The
1767 on stack arguments must be in a continuous region starting from $sp,
1768 while the by reference arguments can be anywhere, but we'll put them
1769 on the stack after (at higher address) the on stack arguments.
1771 This might not be the right approach to take. The ABI is clear that
1772 an argument passed by reference can be modified by the callee, which
1773 us placing the argument (temporarily) onto the stack will not achieve
1774 (changes will be lost). There's also the possibility that very large
1775 arguments could overflow the stack.
1777 This struct is used to track offset into these two areas for where
1778 arguments are to be placed. */
1779 struct riscv_memory_offsets
1781 riscv_memory_offsets ()
1788 /* Offset into on stack argument area. */
1791 /* Offset into the pass by reference area. */
1795 /* Holds information about where arguments to a call will be placed. This
1796 is updated as arguments are added onto the call, and can be used to
1797 figure out where the next argument should be placed. */
1799 struct riscv_call_info
1801 riscv_call_info (struct gdbarch *gdbarch)
1802 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1803 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1805 xlen = riscv_abi_xlen (gdbarch);
1806 flen = riscv_abi_flen (gdbarch);
1808 /* Disable use of floating point registers if needed. */
1809 if (!riscv_has_fp_abi (gdbarch))
1810 float_regs.next_regnum = float_regs.last_regnum + 1;
1813 /* Track the memory areas used for holding in-memory arguments to a
1815 struct riscv_memory_offsets memory;
1817 /* Holds information about the next integer register to use for passing
1819 struct riscv_arg_reg int_regs;
1821 /* Holds information about the next floating point register to use for
1822 passing an argument. */
1823 struct riscv_arg_reg float_regs;
1825 /* The XLEN and FLEN are copied in to this structure for convenience, and
1826 are just the results of calling RISCV_ABI_XLEN and RISCV_ABI_FLEN. */
1831 /* Return the number of registers available for use as parameters in the
1832 register set REG. Returned value can be 0 or more. */
1835 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1837 if (reg->next_regnum > reg->last_regnum)
1840 return (reg->last_regnum - reg->next_regnum + 1);
1843 /* If there is at least one register available in the register set REG then
1844 the next register from REG is assigned to LOC and the length field of
1845 LOC is updated to LENGTH. The register set REG is updated to indicate
1846 that the assigned register is no longer available and the function
1849 If there are no registers available in REG then the function returns
1850 false, and LOC and REG are unchanged. */
1853 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1854 struct riscv_arg_reg *reg,
1855 int length, int offset)
1857 if (reg->next_regnum <= reg->last_regnum)
1859 loc->loc_type = riscv_arg_info::location::in_reg;
1860 loc->loc_data.regno = reg->next_regnum;
1862 loc->c_length = length;
1863 loc->c_offset = offset;
1870 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1871 record that an area of stack has been used to hold the parameter
1874 The length field of LOC is updated to LENGTH, the length of the
1875 parameter being stored, and ALIGN is the alignment required by the
1876 parameter, which will affect how memory is allocated out of MEMORY. */
1879 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1880 struct riscv_memory_offsets *memory,
1881 int length, int align)
1883 loc->loc_type = riscv_arg_info::location::on_stack;
1885 = align_up (memory->arg_offset, align);
1886 loc->loc_data.offset = memory->arg_offset;
1887 memory->arg_offset += length;
1888 loc->c_length = length;
1890 /* Offset is always 0, either we're the first location part, in which
1891 case we're reading content from the start of the argument, or we're
1892 passing the address of a reference argument, so 0. */
1896 /* Update AINFO, which describes an argument that should be passed or
1897 returned using the integer ABI. The argloc fields within AINFO are
1898 updated to describe the location in which the argument will be passed to
1899 a function, or returned from a function.
1901 The CINFO structure contains the ongoing call information, the holds
1902 information such as which argument registers are remaining to be
1903 assigned to parameter, and how much memory has been used by parameters
1906 By examining the state of CINFO a suitable location can be selected,
1907 and assigned to AINFO. */
1910 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1911 struct riscv_call_info *cinfo)
1913 if (ainfo->length > (2 * cinfo->xlen))
1915 /* Argument is going to be passed by reference. */
1916 ainfo->argloc[0].loc_type
1917 = riscv_arg_info::location::by_ref;
1918 cinfo->memory.ref_offset
1919 = align_up (cinfo->memory.ref_offset, ainfo->align);
1920 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1921 cinfo->memory.ref_offset += ainfo->length;
1922 ainfo->argloc[0].c_length = ainfo->length;
1924 /* The second location for this argument is given over to holding the
1925 address of the by-reference data. Pass 0 for the offset as this
1926 is not part of the actual argument value. */
1927 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1930 riscv_assign_stack_location (&ainfo->argloc[1],
1931 &cinfo->memory, cinfo->xlen,
1936 int len = std::min (ainfo->length, cinfo->xlen);
1937 int align = std::max (ainfo->align, cinfo->xlen);
1939 /* Unnamed arguments in registers that require 2*XLEN alignment are
1940 passed in an aligned register pair. */
1941 if (ainfo->is_unnamed && (align == cinfo->xlen * 2)
1942 && cinfo->int_regs.next_regnum & 1)
1943 cinfo->int_regs.next_regnum++;
1945 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1946 &cinfo->int_regs, len, 0))
1947 riscv_assign_stack_location (&ainfo->argloc[0],
1948 &cinfo->memory, len, align);
1950 if (len < ainfo->length)
1952 len = ainfo->length - len;
1953 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1954 &cinfo->int_regs, len,
1956 riscv_assign_stack_location (&ainfo->argloc[1],
1957 &cinfo->memory, len, cinfo->xlen);
1962 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1963 is being passed with the floating point ABI. */
1966 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1967 struct riscv_call_info *cinfo)
1969 if (ainfo->length > cinfo->flen || ainfo->is_unnamed)
1970 return riscv_call_arg_scalar_int (ainfo, cinfo);
1973 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1976 return riscv_call_arg_scalar_int (ainfo, cinfo);
1980 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1981 is a complex floating point argument, and is therefore handled
1982 differently to other argument types. */
1985 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1986 struct riscv_call_info *cinfo)
1988 if (ainfo->length <= (2 * cinfo->flen)
1989 && riscv_arg_regs_available (&cinfo->float_regs) >= 2
1990 && !ainfo->is_unnamed)
1993 int len = ainfo->length / 2;
1995 result = riscv_assign_reg_location (&ainfo->argloc[0],
1996 &cinfo->float_regs, len, len);
1997 gdb_assert (result);
1999 result = riscv_assign_reg_location (&ainfo->argloc[1],
2000 &cinfo->float_regs, len, len);
2001 gdb_assert (result);
2004 return riscv_call_arg_scalar_int (ainfo, cinfo);
2007 /* A structure used for holding information about a structure type within
2008 the inferior program. The RiscV ABI has special rules for handling some
2009 structures with a single field or with two fields. The counting of
2010 fields here is done after flattening out all nested structures. */
2012 class riscv_struct_info
2015 riscv_struct_info ()
2016 : m_number_of_fields (0),
2017 m_types { nullptr, nullptr }
2022 /* Analyse TYPE descending into nested structures, count the number of
2023 scalar fields and record the types of the first two fields found. */
2024 void analyse (struct type *type);
2026 /* The number of scalar fields found in the analysed type. This is
2027 currently only accurate if the value returned is 0, 1, or 2 as the
2028 analysis stops counting when the number of fields is 3. This is
2029 because the RiscV ABI only has special cases for 1 or 2 fields,
2030 anything else we just don't care about. */
2031 int number_of_fields () const
2032 { return m_number_of_fields; }
2034 /* Return the type for scalar field INDEX within the analysed type. Will
2035 return nullptr if there is no field at that index. Only INDEX values
2036 0 and 1 can be requested as the RiscV ABI only has special cases for
2037 structures with 1 or 2 fields. */
2038 struct type *field_type (int index) const
2040 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
2041 return m_types[index];
2045 /* The number of scalar fields found within the structure after recursing
2046 into nested structures. */
2047 int m_number_of_fields;
2049 /* The types of the first two scalar fields found within the structure
2050 after recursing into nested structures. */
2051 struct type *m_types[2];
2054 /* Analyse TYPE descending into nested structures, count the number of
2055 scalar fields and record the types of the first two fields found. */
2058 riscv_struct_info::analyse (struct type *type)
2060 unsigned int count = TYPE_NFIELDS (type);
2063 for (i = 0; i < count; ++i)
2065 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
2068 struct type *field_type = TYPE_FIELD_TYPE (type, i);
2069 field_type = check_typedef (field_type);
2071 switch (TYPE_CODE (field_type))
2073 case TYPE_CODE_STRUCT:
2074 analyse (field_type);
2078 /* RiscV only flattens out structures. Anything else does not
2079 need to be flattened, we just record the type, and when we
2080 look at the analysis results we'll realise this is not a
2081 structure we can special case, and pass the structure in
2083 if (m_number_of_fields < 2)
2084 m_types[m_number_of_fields] = field_type;
2085 m_number_of_fields++;
2089 /* RiscV only has special handling for structures with 1 or 2 scalar
2090 fields, any more than that and the structure is just passed in
2091 memory. We can safely drop out early when we find 3 or more
2094 if (m_number_of_fields > 2)
2099 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2100 is a structure. Small structures on RiscV have some special case
2101 handling in order that the structure might be passed in register.
2102 Larger structures are passed in memory. After assigning location
2103 information to AINFO, CINFO will have been updated. */
2106 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
2107 struct riscv_call_info *cinfo)
2109 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2111 struct riscv_struct_info sinfo;
2113 sinfo.analyse (ainfo->type);
2114 if (sinfo.number_of_fields () == 1
2115 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
2117 gdb_assert (TYPE_LENGTH (ainfo->type)
2118 == TYPE_LENGTH (sinfo.field_type (0)));
2119 return riscv_call_arg_complex_float (ainfo, cinfo);
2122 if (sinfo.number_of_fields () == 1
2123 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
2125 gdb_assert (TYPE_LENGTH (ainfo->type)
2126 == TYPE_LENGTH (sinfo.field_type (0)));
2127 return riscv_call_arg_scalar_float (ainfo, cinfo);
2130 if (sinfo.number_of_fields () == 2
2131 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2132 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2133 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2134 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
2135 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2137 int len0, len1, offset;
2139 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
2141 len0 = TYPE_LENGTH (sinfo.field_type (0));
2142 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2143 &cinfo->float_regs, len0, 0))
2144 error (_("failed during argument setup"));
2146 len1 = TYPE_LENGTH (sinfo.field_type (1));
2147 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2148 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2149 - TYPE_LENGTH (sinfo.field_type (0))));
2151 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2154 error (_("failed during argument setup"));
2158 if (sinfo.number_of_fields () == 2
2159 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2160 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2161 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2162 && is_integral_type (sinfo.field_type (1))
2163 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2165 int len0, len1, offset;
2167 len0 = TYPE_LENGTH (sinfo.field_type (0));
2168 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2169 &cinfo->float_regs, len0, 0))
2170 error (_("failed during argument setup"));
2172 len1 = TYPE_LENGTH (sinfo.field_type (1));
2173 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2174 gdb_assert (len1 <= cinfo->xlen);
2175 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2176 &cinfo->int_regs, len1, offset))
2177 error (_("failed during argument setup"));
2181 if (sinfo.number_of_fields () == 2
2182 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2183 && (is_integral_type (sinfo.field_type (0))
2184 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2185 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2186 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2188 int len0, len1, offset;
2190 len0 = TYPE_LENGTH (sinfo.field_type (0));
2191 len1 = TYPE_LENGTH (sinfo.field_type (1));
2192 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2194 gdb_assert (len0 <= cinfo->xlen);
2195 gdb_assert (len1 <= cinfo->flen);
2197 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2198 &cinfo->int_regs, len0, 0))
2199 error (_("failed during argument setup"));
2201 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2204 error (_("failed during argument setup"));
2210 /* Non of the structure flattening cases apply, so we just pass using
2212 riscv_call_arg_scalar_int (ainfo, cinfo);
2215 /* Assign a location to call (or return) argument AINFO, the location is
2216 selected from CINFO which holds information about what call argument
2217 locations are available for use next. The TYPE is the type of the
2218 argument being passed, this information is recorded into AINFO (along
2219 with some additional information derived from the type). IS_UNNAMED
2220 is true if this is an unnamed (stdarg) argument, this info is also
2221 recorded into AINFO.
2223 After assigning a location to AINFO, CINFO will have been updated. */
2226 riscv_arg_location (struct gdbarch *gdbarch,
2227 struct riscv_arg_info *ainfo,
2228 struct riscv_call_info *cinfo,
2229 struct type *type, bool is_unnamed)
2232 ainfo->length = TYPE_LENGTH (ainfo->type);
2233 ainfo->align = riscv_type_alignment (ainfo->type);
2234 ainfo->is_unnamed = is_unnamed;
2235 ainfo->contents = nullptr;
2237 switch (TYPE_CODE (ainfo->type))
2240 case TYPE_CODE_BOOL:
2241 case TYPE_CODE_CHAR:
2242 case TYPE_CODE_RANGE:
2243 case TYPE_CODE_ENUM:
2245 if (ainfo->length <= cinfo->xlen)
2247 ainfo->type = builtin_type (gdbarch)->builtin_long;
2248 ainfo->length = cinfo->xlen;
2250 else if (ainfo->length <= (2 * cinfo->xlen))
2252 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2253 ainfo->length = 2 * cinfo->xlen;
2256 /* Recalculate the alignment requirement. */
2257 ainfo->align = riscv_type_alignment (ainfo->type);
2258 riscv_call_arg_scalar_int (ainfo, cinfo);
2262 riscv_call_arg_scalar_float (ainfo, cinfo);
2265 case TYPE_CODE_COMPLEX:
2266 riscv_call_arg_complex_float (ainfo, cinfo);
2269 case TYPE_CODE_STRUCT:
2270 riscv_call_arg_struct (ainfo, cinfo);
2274 riscv_call_arg_scalar_int (ainfo, cinfo);
2279 /* Used for printing debug information about the call argument location in
2280 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2281 addresses for the location of pass-by-reference and
2282 arguments-on-the-stack memory areas. */
2285 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2286 struct riscv_arg_info *info,
2287 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2289 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2290 TYPE_SAFE_NAME (info->type), info->length, info->align);
2291 switch (info->argloc[0].loc_type)
2293 case riscv_arg_info::location::in_reg:
2295 (stream, ", register %s",
2296 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2297 if (info->argloc[0].c_length < info->length)
2299 switch (info->argloc[1].loc_type)
2301 case riscv_arg_info::location::in_reg:
2303 (stream, ", register %s",
2304 gdbarch_register_name (gdbarch,
2305 info->argloc[1].loc_data.regno));
2308 case riscv_arg_info::location::on_stack:
2309 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2310 info->argloc[1].loc_data.offset);
2313 case riscv_arg_info::location::by_ref:
2315 /* The second location should never be a reference, any
2316 argument being passed by reference just places its address
2317 in the first location and is done. */
2318 error (_("invalid argument location"));
2322 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2323 fprintf_unfiltered (stream, " (offset 0x%x)",
2324 info->argloc[1].c_offset);
2328 case riscv_arg_info::location::on_stack:
2329 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2330 info->argloc[0].loc_data.offset);
2333 case riscv_arg_info::location::by_ref:
2335 (stream, ", by reference, data at offset 0x%x (%s)",
2336 info->argloc[0].loc_data.offset,
2337 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2338 if (info->argloc[1].loc_type
2339 == riscv_arg_info::location::in_reg)
2341 (stream, ", address in register %s",
2342 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2345 gdb_assert (info->argloc[1].loc_type
2346 == riscv_arg_info::location::on_stack);
2348 (stream, ", address on stack at offset 0x%x (%s)",
2349 info->argloc[1].loc_data.offset,
2350 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2355 gdb_assert_not_reached (_("unknown argument location type"));
2359 /* Implement the push dummy call gdbarch callback. */
2362 riscv_push_dummy_call (struct gdbarch *gdbarch,
2363 struct value *function,
2364 struct regcache *regcache,
2367 struct value **args,
2369 function_call_return_method return_method,
2370 CORE_ADDR struct_addr)
2373 CORE_ADDR sp_args, sp_refs;
2374 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2376 struct riscv_arg_info *arg_info =
2377 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2379 struct riscv_call_info call_info (gdbarch);
2383 struct type *ftype = check_typedef (value_type (function));
2385 if (TYPE_CODE (ftype) == TYPE_CODE_PTR)
2386 ftype = check_typedef (TYPE_TARGET_TYPE (ftype));
2388 /* We'll use register $a0 if we're returning a struct. */
2389 if (return_method == return_method_struct)
2390 ++call_info.int_regs.next_regnum;
2392 for (i = 0; i < nargs; ++i)
2394 struct value *arg_value;
2395 struct type *arg_type;
2396 struct riscv_arg_info *info = &arg_info[i];
2398 arg_value = args[i];
2399 arg_type = check_typedef (value_type (arg_value));
2401 riscv_arg_location (gdbarch, info, &call_info, arg_type,
2402 TYPE_VARARGS (ftype) && i >= TYPE_NFIELDS (ftype));
2404 if (info->type != arg_type)
2405 arg_value = value_cast (info->type, arg_value);
2406 info->contents = value_contents (arg_value);
2409 /* Adjust the stack pointer and align it. */
2410 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2411 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2413 if (riscv_debug_infcall > 0)
2415 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2416 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2417 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2418 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2419 call_info.xlen, call_info.flen);
2420 if (return_method == return_method_struct)
2421 fprintf_unfiltered (gdb_stdlog,
2422 "[*] struct return pointer in register $A0\n");
2423 for (i = 0; i < nargs; ++i)
2425 struct riscv_arg_info *info = &arg_info [i];
2427 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2428 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2429 fprintf_unfiltered (gdb_stdlog, "\n");
2431 if (call_info.memory.arg_offset > 0
2432 || call_info.memory.ref_offset > 0)
2434 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2435 core_addr_to_string (osp));
2436 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2437 call_info.memory.arg_offset);
2438 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2439 call_info.memory.ref_offset);
2440 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2441 core_addr_to_string_nz (osp - sp));
2445 /* Now load the argument into registers, or onto the stack. */
2447 if (return_method == return_method_struct)
2449 gdb_byte buf[sizeof (LONGEST)];
2451 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2452 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2455 for (i = 0; i < nargs; ++i)
2458 int second_arg_length = 0;
2459 const gdb_byte *second_arg_data;
2460 struct riscv_arg_info *info = &arg_info [i];
2462 gdb_assert (info->length > 0);
2464 switch (info->argloc[0].loc_type)
2466 case riscv_arg_info::location::in_reg:
2468 gdb_byte tmp [sizeof (ULONGEST)];
2470 gdb_assert (info->argloc[0].c_length <= info->length);
2471 /* FP values in FP registers must be NaN-boxed. */
2472 if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno)
2473 && info->argloc[0].c_length < call_info.flen)
2474 memset (tmp, -1, sizeof (tmp));
2476 memset (tmp, 0, sizeof (tmp));
2477 memcpy (tmp, info->contents, info->argloc[0].c_length);
2478 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2480 ((info->argloc[0].c_length < info->length)
2481 ? info->argloc[1].c_length : 0);
2482 second_arg_data = info->contents + info->argloc[1].c_offset;
2486 case riscv_arg_info::location::on_stack:
2487 dst = sp_args + info->argloc[0].loc_data.offset;
2488 write_memory (dst, info->contents, info->length);
2489 second_arg_length = 0;
2492 case riscv_arg_info::location::by_ref:
2493 dst = sp_refs + info->argloc[0].loc_data.offset;
2494 write_memory (dst, info->contents, info->length);
2496 second_arg_length = call_info.xlen;
2497 second_arg_data = (gdb_byte *) &dst;
2501 gdb_assert_not_reached (_("unknown argument location type"));
2504 if (second_arg_length > 0)
2506 switch (info->argloc[1].loc_type)
2508 case riscv_arg_info::location::in_reg:
2510 gdb_byte tmp [sizeof (ULONGEST)];
2512 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2513 && second_arg_length <= call_info.flen)
2514 || second_arg_length <= call_info.xlen);
2515 /* FP values in FP registers must be NaN-boxed. */
2516 if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2517 && second_arg_length < call_info.flen)
2518 memset (tmp, -1, sizeof (tmp));
2520 memset (tmp, 0, sizeof (tmp));
2521 memcpy (tmp, second_arg_data, second_arg_length);
2522 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2526 case riscv_arg_info::location::on_stack:
2530 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2531 write_memory (arg_addr, second_arg_data, second_arg_length);
2535 case riscv_arg_info::location::by_ref:
2537 /* The second location should never be a reference, any
2538 argument being passed by reference just places its address
2539 in the first location and is done. */
2540 error (_("invalid argument location"));
2546 /* Set the dummy return value to bp_addr.
2547 A dummy breakpoint will be setup to execute the call. */
2549 if (riscv_debug_infcall > 0)
2550 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2551 core_addr_to_string (bp_addr));
2552 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2554 /* Finally, update the stack pointer. */
2556 if (riscv_debug_infcall > 0)
2557 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2558 core_addr_to_string (sp));
2559 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2564 /* Implement the return_value gdbarch method. */
2566 static enum return_value_convention
2567 riscv_return_value (struct gdbarch *gdbarch,
2568 struct value *function,
2570 struct regcache *regcache,
2572 const gdb_byte *writebuf)
2574 struct riscv_call_info call_info (gdbarch);
2575 struct riscv_arg_info info;
2576 struct type *arg_type;
2578 arg_type = check_typedef (type);
2579 riscv_arg_location (gdbarch, &info, &call_info, arg_type, false);
2581 if (riscv_debug_infcall > 0)
2583 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2584 fprintf_unfiltered (gdb_stdlog, "[R] ");
2585 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2586 fprintf_unfiltered (gdb_stdlog, "\n");
2589 if (readbuf != nullptr || writebuf != nullptr)
2591 unsigned int arg_len;
2592 struct value *abi_val;
2593 gdb_byte *old_readbuf = nullptr;
2596 /* We only do one thing at a time. */
2597 gdb_assert (readbuf == nullptr || writebuf == nullptr);
2599 /* In some cases the argument is not returned as the declared type,
2600 and we need to cast to or from the ABI type in order to
2601 correctly access the argument. When writing to the machine we
2602 do the cast here, when reading from the machine the cast occurs
2603 later, after extracting the value. As the ABI type can be
2604 larger than the declared type, then the read or write buffers
2605 passed in might be too small. Here we ensure that we are using
2606 buffers of sufficient size. */
2607 if (writebuf != nullptr)
2609 struct value *arg_val = value_from_contents (arg_type, writebuf);
2610 abi_val = value_cast (info.type, arg_val);
2611 writebuf = value_contents_raw (abi_val);
2615 abi_val = allocate_value (info.type);
2616 old_readbuf = readbuf;
2617 readbuf = value_contents_raw (abi_val);
2619 arg_len = TYPE_LENGTH (info.type);
2621 switch (info.argloc[0].loc_type)
2623 /* Return value in register(s). */
2624 case riscv_arg_info::location::in_reg:
2626 regnum = info.argloc[0].loc_data.regno;
2627 gdb_assert (info.argloc[0].c_length <= arg_len);
2628 gdb_assert (info.argloc[0].c_length
2629 <= register_size (gdbarch, regnum));
2632 regcache->cooked_read_part (regnum, 0,
2633 info.argloc[0].c_length,
2637 regcache->cooked_write_part (regnum, 0,
2638 info.argloc[0].c_length,
2641 /* A return value in register can have a second part in a
2643 if (info.argloc[0].c_length < info.length)
2645 switch (info.argloc[1].loc_type)
2647 case riscv_arg_info::location::in_reg:
2648 regnum = info.argloc[1].loc_data.regno;
2650 gdb_assert ((info.argloc[0].c_length
2651 + info.argloc[1].c_length) <= arg_len);
2652 gdb_assert (info.argloc[1].c_length
2653 <= register_size (gdbarch, regnum));
2657 readbuf += info.argloc[1].c_offset;
2658 regcache->cooked_read_part (regnum, 0,
2659 info.argloc[1].c_length,
2665 writebuf += info.argloc[1].c_offset;
2666 regcache->cooked_write_part (regnum, 0,
2667 info.argloc[1].c_length,
2672 case riscv_arg_info::location::by_ref:
2673 case riscv_arg_info::location::on_stack:
2675 error (_("invalid argument location"));
2682 /* Return value by reference will have its address in A0. */
2683 case riscv_arg_info::location::by_ref:
2687 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2689 if (readbuf != nullptr)
2690 read_memory (addr, readbuf, info.length);
2691 if (writebuf != nullptr)
2692 write_memory (addr, writebuf, info.length);
2696 case riscv_arg_info::location::on_stack:
2698 error (_("invalid argument location"));
2702 /* This completes the cast from abi type back to the declared type
2703 in the case that we are reading from the machine. See the
2704 comment at the head of this block for more details. */
2705 if (readbuf != nullptr)
2707 struct value *arg_val = value_cast (arg_type, abi_val);
2708 memcpy (old_readbuf, value_contents_raw (arg_val),
2709 TYPE_LENGTH (arg_type));
2713 switch (info.argloc[0].loc_type)
2715 case riscv_arg_info::location::in_reg:
2716 return RETURN_VALUE_REGISTER_CONVENTION;
2717 case riscv_arg_info::location::by_ref:
2718 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2719 case riscv_arg_info::location::on_stack:
2721 error (_("invalid argument location"));
2725 /* Implement the frame_align gdbarch method. */
2728 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2730 return align_down (addr, 16);
2733 /* Implement the unwind_pc gdbarch method. */
2736 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2738 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2741 /* Implement the unwind_sp gdbarch method. */
2744 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2746 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2749 /* Implement the dummy_id gdbarch method. */
2751 static struct frame_id
2752 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2754 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2755 get_frame_pc (this_frame));
2758 /* Generate, or return the cached frame cache for the RiscV frame
2761 static struct riscv_unwind_cache *
2762 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2764 CORE_ADDR pc, start_addr;
2765 struct riscv_unwind_cache *cache;
2766 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2769 if ((*this_cache) != NULL)
2770 return (struct riscv_unwind_cache *) *this_cache;
2772 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2773 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2774 (*this_cache) = cache;
2776 /* Scan the prologue, filling in the cache. */
2777 start_addr = get_frame_func (this_frame);
2778 pc = get_frame_pc (this_frame);
2779 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2781 /* We can now calculate the frame base address. */
2783 = (get_frame_register_signed (this_frame, cache->frame_base_reg)
2784 + cache->frame_base_offset);
2785 if (riscv_debug_unwinder)
2786 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2787 core_addr_to_string (cache->frame_base),
2788 gdbarch_register_name (gdbarch,
2789 cache->frame_base_reg),
2790 cache->frame_base_offset);
2792 /* The prologue scanner sets the address of registers stored to the stack
2793 as the offset of that register from the frame base. The prologue
2794 scanner doesn't know the actual frame base value, and so is unable to
2795 compute the exact address. We do now know the frame base value, so
2796 update the address of registers stored to the stack. */
2797 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2798 for (regno = 0; regno < numregs; ++regno)
2800 if (trad_frame_addr_p (cache->regs, regno))
2801 cache->regs[regno].addr += cache->frame_base;
2804 /* The previous $pc can be found wherever the $ra value can be found.
2805 The previous $ra value is gone, this would have been stored be the
2806 previous frame if required. */
2807 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2808 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2810 /* Build the frame id. */
2811 cache->this_id = frame_id_build (cache->frame_base, start_addr);
2813 /* The previous $sp value is the frame base value. */
2814 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2820 /* Implement the this_id callback for RiscV frame unwinder. */
2823 riscv_frame_this_id (struct frame_info *this_frame,
2824 void **prologue_cache,
2825 struct frame_id *this_id)
2827 struct riscv_unwind_cache *cache;
2831 cache = riscv_frame_cache (this_frame, prologue_cache);
2832 *this_id = cache->this_id;
2834 CATCH (ex, RETURN_MASK_ERROR)
2836 /* Ignore errors, this leaves the frame id as the predefined outer
2837 frame id which terminates the backtrace at this point. */
2842 /* Implement the prev_register callback for RiscV frame unwinder. */
2844 static struct value *
2845 riscv_frame_prev_register (struct frame_info *this_frame,
2846 void **prologue_cache,
2849 struct riscv_unwind_cache *cache;
2851 cache = riscv_frame_cache (this_frame, prologue_cache);
2852 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
2855 /* Structure defining the RiscV normal frame unwind functions. Since we
2856 are the fallback unwinder (DWARF unwinder is used first), we use the
2857 default frame sniffer, which always accepts the frame. */
2859 static const struct frame_unwind riscv_frame_unwind =
2861 /*.type =*/ NORMAL_FRAME,
2862 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2863 /*.this_id =*/ riscv_frame_this_id,
2864 /*.prev_register =*/ riscv_frame_prev_register,
2865 /*.unwind_data =*/ NULL,
2866 /*.sniffer =*/ default_frame_sniffer,
2867 /*.dealloc_cache =*/ NULL,
2868 /*.prev_arch =*/ NULL,
2871 /* Extract a set of required target features out of INFO, specifically the
2872 bfd being executed is examined to see what target features it requires.
2873 IF there is no current bfd, or the bfd doesn't indicate any useful
2874 features then a RISCV_GDBARCH_FEATURES is returned in its default state. */
2876 static struct riscv_gdbarch_features
2877 riscv_features_from_gdbarch_info (const struct gdbarch_info info)
2879 struct riscv_gdbarch_features features;
2881 /* Now try to improve on the defaults by looking at the binary we are
2882 going to execute. We assume the user knows what they are doing and
2883 that the target will match the binary. Remember, this code path is
2884 only used at all if the target hasn't given us a description, so this
2885 is really a last ditched effort to do something sane before giving
2887 if (info.abfd != NULL
2888 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2890 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2891 int e_flags = elf_elfheader (info.abfd)->e_flags;
2893 if (eclass == ELFCLASS32)
2895 else if (eclass == ELFCLASS64)
2898 internal_error (__FILE__, __LINE__,
2899 _("unknown ELF header class %d"), eclass);
2901 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2903 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2908 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2910 if (binfo->bits_per_word == 32)
2912 else if (binfo->bits_per_word == 64)
2915 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2916 binfo->bits_per_word);
2922 /* Find a suitable default target description. Use the contents of INFO,
2923 specifically the bfd object being executed, to guide the selection of a
2924 suitable default target description. */
2926 static const struct target_desc *
2927 riscv_find_default_target_description (const struct gdbarch_info info)
2929 /* Extract desired feature set from INFO. */
2930 struct riscv_gdbarch_features features
2931 = riscv_features_from_gdbarch_info (info);
2933 /* If the XLEN field is still 0 then we got nothing useful from INFO. In
2934 this case we fall back to a minimal useful target, 8-byte x-registers,
2935 with no floating point. */
2936 if (features.xlen == 0)
2939 /* Now build a target description based on the feature set. */
2940 return riscv_create_target_description (features);
2943 /* All of the registers in REG_SET are checked for in FEATURE, TDESC_DATA
2944 is updated with the register numbers for each register as listed in
2945 REG_SET. If any register marked as required in REG_SET is not found in
2946 FEATURE then this function returns false, otherwise, it returns true. */
2949 riscv_check_tdesc_feature (struct tdesc_arch_data *tdesc_data,
2950 const struct tdesc_feature *feature,
2951 const struct riscv_register_feature *reg_set)
2953 for (const auto ® : reg_set->registers)
2957 for (const char *name : reg.names)
2960 tdesc_numbered_register (feature, tdesc_data, reg.regnum, name);
2966 if (!found && reg.required_p)
2973 /* Add all the expected register sets into GDBARCH. */
2976 riscv_add_reggroups (struct gdbarch *gdbarch)
2978 /* Add predefined register groups. */
2979 reggroup_add (gdbarch, all_reggroup);
2980 reggroup_add (gdbarch, save_reggroup);
2981 reggroup_add (gdbarch, restore_reggroup);
2982 reggroup_add (gdbarch, system_reggroup);
2983 reggroup_add (gdbarch, vector_reggroup);
2984 reggroup_add (gdbarch, general_reggroup);
2985 reggroup_add (gdbarch, float_reggroup);
2987 /* Add RISC-V specific register groups. */
2988 reggroup_add (gdbarch, csr_reggroup);
2991 /* Create register aliases for all the alternative names that exist for
2992 registers in REG_SET. */
2995 riscv_setup_register_aliases (struct gdbarch *gdbarch,
2996 const struct riscv_register_feature *reg_set)
2998 for (auto ® : reg_set->registers)
3000 /* The first item in the names list is the preferred name for the
3001 register, this is what RISCV_REGISTER_NAME returns, and so we
3002 don't need to create an alias with that name here. */
3003 for (int i = 1; i < reg.names.size (); ++i)
3004 user_reg_add (gdbarch, reg.names[i], value_of_riscv_user_reg,
3009 /* Implement the "dwarf2_reg_to_regnum" gdbarch method. */
3012 riscv_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
3014 if (reg < RISCV_DWARF_REGNUM_X31)
3015 return RISCV_ZERO_REGNUM + (reg - RISCV_DWARF_REGNUM_X0);
3017 else if (reg < RISCV_DWARF_REGNUM_F31)
3018 return RISCV_FIRST_FP_REGNUM + (reg - RISCV_DWARF_REGNUM_F0);
3023 /* Initialize the current architecture based on INFO. If possible,
3024 re-use an architecture from ARCHES, which is a list of
3025 architectures already created during this debugging session.
3027 Called e.g. at program startup, when reading a core file, and when
3028 reading a binary file. */
3030 static struct gdbarch *
3031 riscv_gdbarch_init (struct gdbarch_info info,
3032 struct gdbarch_list *arches)
3034 struct gdbarch *gdbarch;
3035 struct gdbarch_tdep *tdep;
3036 struct riscv_gdbarch_features features;
3037 const struct target_desc *tdesc = info.target_desc;
3039 /* Ensure we always have a target description. */
3040 if (!tdesc_has_registers (tdesc))
3041 tdesc = riscv_find_default_target_description (info);
3044 if (riscv_debug_gdbarch)
3045 fprintf_unfiltered (gdb_stdlog, "Have got a target description\n");
3047 const struct tdesc_feature *feature_cpu
3048 = tdesc_find_feature (tdesc, riscv_xreg_feature.name);
3049 const struct tdesc_feature *feature_fpu
3050 = tdesc_find_feature (tdesc, riscv_freg_feature.name);
3051 const struct tdesc_feature *feature_virtual
3052 = tdesc_find_feature (tdesc, riscv_virtual_feature.name);
3053 const struct tdesc_feature *feature_csr
3054 = tdesc_find_feature (tdesc, riscv_csr_feature.name);
3056 if (feature_cpu == NULL)
3059 struct tdesc_arch_data *tdesc_data = tdesc_data_alloc ();
3061 bool valid_p = riscv_check_tdesc_feature (tdesc_data,
3063 &riscv_xreg_feature);
3066 /* Check that all of the core cpu registers have the same bitsize. */
3067 int xlen_bitsize = tdesc_register_bitsize (feature_cpu, "pc");
3069 for (auto &tdesc_reg : feature_cpu->registers)
3070 valid_p &= (tdesc_reg->bitsize == xlen_bitsize);
3072 if (riscv_debug_gdbarch)
3075 "From target-description, xlen = %d\n", xlen_bitsize);
3077 features.xlen = (xlen_bitsize / 8);
3080 if (feature_fpu != NULL)
3082 valid_p &= riscv_check_tdesc_feature (tdesc_data, feature_fpu,
3083 &riscv_freg_feature);
3085 int bitsize = tdesc_register_bitsize (feature_fpu, "ft0");
3086 features.flen = (bitsize / 8);
3088 if (riscv_debug_gdbarch)
3091 "From target-description, flen = %d\n", bitsize);
3097 if (riscv_debug_gdbarch)
3100 "No FPU in target-description, assume soft-float ABI\n");
3103 if (feature_virtual)
3104 riscv_check_tdesc_feature (tdesc_data, feature_virtual,
3105 &riscv_virtual_feature);
3108 riscv_check_tdesc_feature (tdesc_data, feature_csr,
3109 &riscv_csr_feature);
3113 if (riscv_debug_gdbarch)
3114 fprintf_unfiltered (gdb_stdlog, "Target description is not valid\n");
3115 tdesc_data_cleanup (tdesc_data);
3119 /* Have a look at what the supplied (if any) bfd object requires of the
3120 target, then check that this matches with what the target is
3122 struct riscv_gdbarch_features abi_features
3123 = riscv_features_from_gdbarch_info (info);
3124 /* In theory a binary compiled for RV32 could run on an RV64 target,
3125 however, this has not been tested in GDB yet, so for now we require
3126 that the requested xlen match the targets xlen. */
3127 if (abi_features.xlen != 0 && abi_features.xlen != features.xlen)
3128 error (_("bfd requires xlen %d, but target has xlen %d"),
3129 abi_features.xlen, features.xlen);
3130 /* We do support running binaries compiled for 32-bit float on targets
3131 with 64-bit float, so we only complain if the binary requires more
3132 than the target has available. */
3133 if (abi_features.flen > features.flen)
3134 error (_("bfd requires flen %d, but target has flen %d"),
3135 abi_features.flen, features.flen);
3137 /* If the ABI_FEATURES xlen is 0 then this indicates we got no useful abi
3138 features from the INFO object. In this case we assume that the xlen
3139 abi matches the hardware. */
3140 if (abi_features.xlen == 0)
3141 abi_features.xlen = features.xlen;
3143 /* Find a candidate among the list of pre-declared architectures. */
3144 for (arches = gdbarch_list_lookup_by_info (arches, &info);
3146 arches = gdbarch_list_lookup_by_info (arches->next, &info))
3148 /* Check that the feature set of the ARCHES matches the feature set
3149 we are looking for. If it doesn't then we can't reuse this
3151 struct gdbarch_tdep *other_tdep = gdbarch_tdep (arches->gdbarch);
3153 if (other_tdep->isa_features != features
3154 || other_tdep->abi_features != abi_features)
3162 tdesc_data_cleanup (tdesc_data);
3163 return arches->gdbarch;
3166 /* None found, so create a new architecture from the information provided. */
3167 tdep = new (struct gdbarch_tdep);
3168 gdbarch = gdbarch_alloc (&info, tdep);
3169 tdep->isa_features = features;
3170 tdep->abi_features = abi_features;
3172 /* Target data types. */
3173 set_gdbarch_short_bit (gdbarch, 16);
3174 set_gdbarch_int_bit (gdbarch, 32);
3175 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
3176 set_gdbarch_long_long_bit (gdbarch, 64);
3177 set_gdbarch_float_bit (gdbarch, 32);
3178 set_gdbarch_double_bit (gdbarch, 64);
3179 set_gdbarch_long_double_bit (gdbarch, 128);
3180 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
3181 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
3182 set_gdbarch_char_signed (gdbarch, 0);
3184 /* Information about the target architecture. */
3185 set_gdbarch_return_value (gdbarch, riscv_return_value);
3186 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
3187 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
3188 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3190 /* Functions to analyze frames. */
3191 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
3192 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3193 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
3195 /* Functions to access frame data. */
3196 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
3197 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
3199 /* Functions handling dummy frames. */
3200 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
3201 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
3202 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
3203 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
3205 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
3207 dwarf2_append_unwinders (gdbarch);
3208 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
3210 /* Register architecture. */
3211 riscv_add_reggroups (gdbarch);
3213 /* Internal <-> external register number maps. */
3214 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, riscv_dwarf_reg_to_regnum);
3216 /* We reserve all possible register numbers for the known registers.
3217 This means the target description mechanism will add any target
3218 specific registers after this number. This helps make debugging GDB
3219 just a little easier. */
3220 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
3222 /* We don't have to provide the count of 0 here (its the default) but
3223 include this line to make it explicit that, right now, we don't have
3224 any pseudo registers on RISC-V. */
3225 set_gdbarch_num_pseudo_regs (gdbarch, 0);
3227 /* Some specific register numbers GDB likes to know about. */
3228 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
3229 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
3231 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
3233 /* Finalise the target description registers. */
3234 tdesc_use_registers (gdbarch, tdesc, tdesc_data);
3236 /* Override the register type callback setup by the target description
3237 mechanism. This allows us to provide special type for floating point
3239 set_gdbarch_register_type (gdbarch, riscv_register_type);
3241 /* Override the register name callback setup by the target description
3242 mechanism. This allows us to force our preferred names for the
3243 registers, no matter what the target description called them. */
3244 set_gdbarch_register_name (gdbarch, riscv_register_name);
3246 /* Override the register group callback setup by the target description
3247 mechanism. This allows us to force registers into the groups we
3248 want, ignoring what the target tells us. */
3249 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
3251 /* Create register aliases for alternative register names. */
3252 riscv_setup_register_aliases (gdbarch, &riscv_xreg_feature);
3253 if (riscv_has_fp_regs (gdbarch))
3254 riscv_setup_register_aliases (gdbarch, &riscv_freg_feature);
3255 riscv_setup_register_aliases (gdbarch, &riscv_csr_feature);
3257 /* Hook in OS ABI-specific overrides, if they have been registered. */
3258 gdbarch_init_osabi (info, gdbarch);
3263 /* This decodes the current instruction and determines the address of the
3264 next instruction. */
3267 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
3269 struct gdbarch *gdbarch = regcache->arch ();
3270 struct riscv_insn insn;
3273 insn.decode (gdbarch, pc);
3274 next_pc = pc + insn.length ();
3276 if (insn.opcode () == riscv_insn::JAL)
3277 next_pc = pc + insn.imm_signed ();
3278 else if (insn.opcode () == riscv_insn::JALR)
3281 regcache->cooked_read (insn.rs1 (), &source);
3282 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
3284 else if (insn.opcode () == riscv_insn::BEQ)
3287 regcache->cooked_read (insn.rs1 (), &src1);
3288 regcache->cooked_read (insn.rs2 (), &src2);
3290 next_pc = pc + insn.imm_signed ();
3292 else if (insn.opcode () == riscv_insn::BNE)
3295 regcache->cooked_read (insn.rs1 (), &src1);
3296 regcache->cooked_read (insn.rs2 (), &src2);
3298 next_pc = pc + insn.imm_signed ();
3300 else if (insn.opcode () == riscv_insn::BLT)
3303 regcache->cooked_read (insn.rs1 (), &src1);
3304 regcache->cooked_read (insn.rs2 (), &src2);
3306 next_pc = pc + insn.imm_signed ();
3308 else if (insn.opcode () == riscv_insn::BGE)
3311 regcache->cooked_read (insn.rs1 (), &src1);
3312 regcache->cooked_read (insn.rs2 (), &src2);
3314 next_pc = pc + insn.imm_signed ();
3316 else if (insn.opcode () == riscv_insn::BLTU)
3318 ULONGEST src1, src2;
3319 regcache->cooked_read (insn.rs1 (), &src1);
3320 regcache->cooked_read (insn.rs2 (), &src2);
3322 next_pc = pc + insn.imm_signed ();
3324 else if (insn.opcode () == riscv_insn::BGEU)
3326 ULONGEST src1, src2;
3327 regcache->cooked_read (insn.rs1 (), &src1);
3328 regcache->cooked_read (insn.rs2 (), &src2);
3330 next_pc = pc + insn.imm_signed ();
3336 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3337 for the end of the sequence and put the breakpoint there. */
3340 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
3343 struct gdbarch *gdbarch = regcache->arch ();
3344 struct riscv_insn insn;
3345 CORE_ADDR cur_step_pc = pc;
3346 CORE_ADDR last_addr = 0;
3348 /* First instruction has to be a load reserved. */
3349 insn.decode (gdbarch, cur_step_pc);
3350 if (insn.opcode () != riscv_insn::LR)
3352 cur_step_pc = cur_step_pc + insn.length ();
3354 /* Next instruction should be branch to exit. */
3355 insn.decode (gdbarch, cur_step_pc);
3356 if (insn.opcode () != riscv_insn::BNE)
3358 last_addr = cur_step_pc + insn.imm_signed ();
3359 cur_step_pc = cur_step_pc + insn.length ();
3361 /* Next instruction should be store conditional. */
3362 insn.decode (gdbarch, cur_step_pc);
3363 if (insn.opcode () != riscv_insn::SC)
3365 cur_step_pc = cur_step_pc + insn.length ();
3367 /* Next instruction should be branch to start. */
3368 insn.decode (gdbarch, cur_step_pc);
3369 if (insn.opcode () != riscv_insn::BNE)
3371 if (pc != (cur_step_pc + insn.imm_signed ()))
3373 cur_step_pc = cur_step_pc + insn.length ();
3375 /* We should now be at the end of the sequence. */
3376 if (cur_step_pc != last_addr)
3379 *next_pc = cur_step_pc;
3383 /* This is called just before we want to resume the inferior, if we want to
3384 single-step it but there is no hardware or kernel single-step support. We
3385 find the target of the coming instruction and breakpoint it. */
3387 std::vector<CORE_ADDR>
3388 riscv_software_single_step (struct regcache *regcache)
3390 CORE_ADDR pc, next_pc;
3392 pc = regcache_read_pc (regcache);
3394 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
3397 next_pc = riscv_next_pc (regcache, pc);
3402 /* Create RISC-V specific reggroups. */
3405 riscv_init_reggroups ()
3407 csr_reggroup = reggroup_new ("csr", USER_REGGROUP);
3411 _initialize_riscv_tdep (void)
3413 riscv_create_csr_aliases ();
3414 riscv_init_reggroups ();
3416 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
3418 /* Add root prefix command for all "set debug riscv" and "show debug
3420 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
3421 _("RISC-V specific debug commands."),
3422 &setdebugriscvcmdlist, "set debug riscv ", 0,
3425 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
3426 _("RISC-V specific debug commands."),
3427 &showdebugriscvcmdlist, "show debug riscv ", 0,
3430 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
3431 &riscv_debug_breakpoints, _("\
3432 Set riscv breakpoint debugging."), _("\
3433 Show riscv breakpoint debugging."), _("\
3434 When non-zero, print debugging information for the riscv specific parts\n\
3435 of the breakpoint mechanism."),
3437 show_riscv_debug_variable,
3438 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3440 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
3441 &riscv_debug_infcall, _("\
3442 Set riscv inferior call debugging."), _("\
3443 Show riscv inferior call debugging."), _("\
3444 When non-zero, print debugging information for the riscv specific parts\n\
3445 of the inferior call mechanism."),
3447 show_riscv_debug_variable,
3448 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3450 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
3451 &riscv_debug_unwinder, _("\
3452 Set riscv stack unwinding debugging."), _("\
3453 Show riscv stack unwinding debugging."), _("\
3454 When non-zero, print debugging information for the riscv specific parts\n\
3455 of the stack unwinding mechanism."),
3457 show_riscv_debug_variable,
3458 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3460 add_setshow_zuinteger_cmd ("gdbarch", class_maintenance,
3461 &riscv_debug_gdbarch, _("\
3462 Set riscv gdbarch initialisation debugging."), _("\
3463 Show riscv gdbarch initialisation debugging."), _("\
3464 When non-zero, print debugging information for the riscv gdbarch\n\
3465 initialisation process."),
3467 show_riscv_debug_variable,
3468 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3470 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3471 add_prefix_cmd ("riscv", no_class, set_riscv_command,
3472 _("RISC-V specific commands."),
3473 &setriscvcmdlist, "set riscv ", 0, &setlist);
3475 add_prefix_cmd ("riscv", no_class, show_riscv_command,
3476 _("RISC-V specific commands."),
3477 &showriscvcmdlist, "show riscv ", 0, &showlist);
3480 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
3481 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
3482 &use_compressed_breakpoints,
3484 Set debugger's use of compressed breakpoints."), _(" \
3485 Show debugger's use of compressed breakpoints."), _("\
3486 Debugging compressed code requires compressed breakpoints to be used. If\n\
3487 left to 'auto' then gdb will use them if the existing instruction is a\n\
3488 compressed instruction. If that doesn't give the correct behavior, then\n\
3489 this option can be used."),
3491 show_use_compressed_breakpoints,