1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
59 /* The stack must be 16-byte aligned. */
60 #define SP_ALIGNMENT 16
62 /* The biggest alignment that the target supports. */
63 #define BIGGEST_ALIGNMENT 16
65 /* Forward declarations. */
66 static bool riscv_has_feature (struct gdbarch *gdbarch, char feature);
68 /* Define a series of is_XXX_insn functions to check if the value INSN
69 is an instance of instruction XXX. */
70 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
71 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
73 return (insn & INSN_MASK) == INSN_MATCH; \
75 #include "opcode/riscv-opc.h"
78 /* Cached information about a frame. */
80 struct riscv_unwind_cache
82 /* The register from which we can calculate the frame base. This is
83 usually $sp or $fp. */
86 /* The offset from the current value in register FRAME_BASE_REG to the
87 actual frame base address. */
88 int frame_base_offset;
90 /* Information about previous register values. */
91 struct trad_frame_saved_reg *regs;
93 /* The id for this frame. */
94 struct frame_id this_id;
96 /* The base (stack) address for this frame. This is the stack pointer
97 value on entry to this frame before any adjustments are made. */
101 /* The preferred register names for all the general purpose and floating
102 point registers. These are what GDB will use when referencing a
105 static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
107 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", "fp", "s1",
108 "a0", "a1", "a2", "a3", "a4", "a5", "a6", "a7", "s2", "s3", "s4",
109 "s5", "s6", "s7", "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6",
111 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", "fs0", "fs1",
112 "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", "fa6", "fa7", "fs2", "fs3",
113 "fs4", "fs5", "fs6", "fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9",
117 /* Map alternative register names onto their GDB register number. */
119 struct riscv_register_alias
121 /* The register alias. Usually more descriptive than the
122 architectural name of the register. */
125 /* The GDB register number. */
129 /* Table of register aliases. */
131 static const struct riscv_register_alias riscv_register_aliases[] =
133 /* Aliases for general purpose registers. These are the architectural
134 names, as GDB uses the more user friendly names by default. */
135 { "x0", (RISCV_ZERO_REGNUM + 0) },
136 { "x1", (RISCV_ZERO_REGNUM + 1) },
137 { "x2", (RISCV_ZERO_REGNUM + 2) },
138 { "x3", (RISCV_ZERO_REGNUM + 3) },
139 { "x4", (RISCV_ZERO_REGNUM + 4) },
140 { "x5", (RISCV_ZERO_REGNUM + 5) },
141 { "x6", (RISCV_ZERO_REGNUM + 6) },
142 { "x7", (RISCV_ZERO_REGNUM + 7) },
143 { "x8", (RISCV_ZERO_REGNUM + 8) },
144 { "s0", (RISCV_ZERO_REGNUM + 8) }, /* fp, s0, and x8 are all aliases. */
145 { "x9", (RISCV_ZERO_REGNUM + 9) },
146 { "x10", (RISCV_ZERO_REGNUM + 10) },
147 { "x11", (RISCV_ZERO_REGNUM + 11) },
148 { "x12", (RISCV_ZERO_REGNUM + 12) },
149 { "x13", (RISCV_ZERO_REGNUM + 13) },
150 { "x14", (RISCV_ZERO_REGNUM + 14) },
151 { "x15", (RISCV_ZERO_REGNUM + 15) },
152 { "x16", (RISCV_ZERO_REGNUM + 16) },
153 { "x17", (RISCV_ZERO_REGNUM + 17) },
154 { "x18", (RISCV_ZERO_REGNUM + 18) },
155 { "x19", (RISCV_ZERO_REGNUM + 19) },
156 { "x20", (RISCV_ZERO_REGNUM + 20) },
157 { "x21", (RISCV_ZERO_REGNUM + 21) },
158 { "x22", (RISCV_ZERO_REGNUM + 22) },
159 { "x23", (RISCV_ZERO_REGNUM + 23) },
160 { "x24", (RISCV_ZERO_REGNUM + 24) },
161 { "x25", (RISCV_ZERO_REGNUM + 25) },
162 { "x26", (RISCV_ZERO_REGNUM + 26) },
163 { "x27", (RISCV_ZERO_REGNUM + 27) },
164 { "x28", (RISCV_ZERO_REGNUM + 28) },
165 { "x29", (RISCV_ZERO_REGNUM + 29) },
166 { "x30", (RISCV_ZERO_REGNUM + 30) },
167 { "x31", (RISCV_ZERO_REGNUM + 31) },
169 /* Aliases for the floating-point registers. These are the architectural
170 names as GDB uses the more user friendly names by default. */
171 { "f0", (RISCV_FIRST_FP_REGNUM + 0) },
172 { "f1", (RISCV_FIRST_FP_REGNUM + 1) },
173 { "f2", (RISCV_FIRST_FP_REGNUM + 2) },
174 { "f3", (RISCV_FIRST_FP_REGNUM + 3) },
175 { "f4", (RISCV_FIRST_FP_REGNUM + 4) },
176 { "f5", (RISCV_FIRST_FP_REGNUM + 5) },
177 { "f6", (RISCV_FIRST_FP_REGNUM + 6) },
178 { "f7", (RISCV_FIRST_FP_REGNUM + 7) },
179 { "f8", (RISCV_FIRST_FP_REGNUM + 8) },
180 { "f9", (RISCV_FIRST_FP_REGNUM + 9) },
181 { "f10", (RISCV_FIRST_FP_REGNUM + 10) },
182 { "f11", (RISCV_FIRST_FP_REGNUM + 11) },
183 { "f12", (RISCV_FIRST_FP_REGNUM + 12) },
184 { "f13", (RISCV_FIRST_FP_REGNUM + 13) },
185 { "f14", (RISCV_FIRST_FP_REGNUM + 14) },
186 { "f15", (RISCV_FIRST_FP_REGNUM + 15) },
187 { "f16", (RISCV_FIRST_FP_REGNUM + 16) },
188 { "f17", (RISCV_FIRST_FP_REGNUM + 17) },
189 { "f18", (RISCV_FIRST_FP_REGNUM + 18) },
190 { "f19", (RISCV_FIRST_FP_REGNUM + 19) },
191 { "f20", (RISCV_FIRST_FP_REGNUM + 20) },
192 { "f21", (RISCV_FIRST_FP_REGNUM + 21) },
193 { "f22", (RISCV_FIRST_FP_REGNUM + 22) },
194 { "f23", (RISCV_FIRST_FP_REGNUM + 23) },
195 { "f24", (RISCV_FIRST_FP_REGNUM + 24) },
196 { "f25", (RISCV_FIRST_FP_REGNUM + 25) },
197 { "f26", (RISCV_FIRST_FP_REGNUM + 26) },
198 { "f27", (RISCV_FIRST_FP_REGNUM + 27) },
199 { "f28", (RISCV_FIRST_FP_REGNUM + 28) },
200 { "f29", (RISCV_FIRST_FP_REGNUM + 29) },
201 { "f30", (RISCV_FIRST_FP_REGNUM + 30) },
202 { "f31", (RISCV_FIRST_FP_REGNUM + 31) },
205 /* Controls whether we place compressed breakpoints or not. When in auto
206 mode GDB tries to determine if the target supports compressed
207 breakpoints, and uses them if it does. */
209 static enum auto_boolean use_compressed_breakpoints;
211 /* The show callback for 'show riscv use-compressed-breakpoints'. */
214 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
215 struct cmd_list_element *c,
218 fprintf_filtered (file,
219 _("Debugger's use of compressed breakpoints is set "
223 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
225 static struct cmd_list_element *setriscvcmdlist = NULL;
226 static struct cmd_list_element *showriscvcmdlist = NULL;
228 /* The show callback for the 'show riscv' prefix command. */
231 show_riscv_command (const char *args, int from_tty)
233 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
236 /* The set callback for the 'set riscv' prefix command. */
239 set_riscv_command (const char *args, int from_tty)
242 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
243 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
246 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
248 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
249 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
251 /* The show callback for the 'show debug riscv' prefix command. */
254 show_debug_riscv_command (const char *args, int from_tty)
256 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
259 /* The set callback for the 'set debug riscv' prefix command. */
262 set_debug_riscv_command (const char *args, int from_tty)
265 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
266 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
269 /* The show callback for all 'show debug riscv VARNAME' variables. */
272 show_riscv_debug_variable (struct ui_file *file, int from_tty,
273 struct cmd_list_element *c,
276 fprintf_filtered (file,
277 _("RiscV debug variable `%s' is set to: %s\n"),
281 /* When this is set to non-zero debugging information about breakpoint
282 kinds will be printed. */
284 static unsigned int riscv_debug_breakpoints = 0;
286 /* When this is set to non-zero debugging information about inferior calls
289 static unsigned int riscv_debug_infcall = 0;
291 /* When this is set to non-zero debugging information about stack unwinding
294 static unsigned int riscv_debug_unwinder = 0;
296 /* Read the MISA register from the target. There are a couple of locations
297 that the register might be found, these are all tried. If the MISA
298 register can't be found at all then the default value of 0 is returned,
299 this is inline with the RISC-V specification. */
302 riscv_read_misa_reg ()
306 if (target_has_registers)
308 /* Old cores might have MISA located at a different offset. */
309 static int misa_regs[] =
310 { RISCV_CSR_MISA_REGNUM, RISCV_CSR_LEGACY_MISA_REGNUM };
312 struct frame_info *frame = get_current_frame ();
314 for (int i = 0; i < ARRAY_SIZE (misa_regs); ++i)
316 bool success = false;
320 value = get_frame_register_unsigned (frame, misa_regs[i]);
323 CATCH (ex, RETURN_MASK_ERROR)
325 /* Ignore errors, it is acceptable for a target to not
326 provide a MISA register, in which case the default value
327 of 0 should be used. */
339 /* Return true if FEATURE is available for the architecture GDBARCH. The
340 FEATURE should be one of the single character feature codes described in
341 the RiscV ISA manual, these are between 'A' and 'Z'. */
344 riscv_has_feature (struct gdbarch *gdbarch, char feature)
346 gdb_assert (feature >= 'A' && feature <= 'Z');
348 uint32_t misa = riscv_read_misa_reg ();
350 misa = gdbarch_tdep (gdbarch)->core_features;
352 return (misa & (1 << (feature - 'A'))) != 0;
355 /* See riscv-tdep.h. */
358 riscv_isa_xlen (struct gdbarch *gdbarch)
360 switch (gdbarch_tdep (gdbarch)->abi.fields.base_len)
363 warning (_("unknown xlen size, assuming 4 bytes"));
374 /* See riscv-tdep.h. */
377 riscv_isa_flen (struct gdbarch *gdbarch)
379 if (riscv_has_feature (gdbarch, 'Q'))
381 else if (riscv_has_feature (gdbarch, 'D'))
383 else if (riscv_has_feature (gdbarch, 'F'))
389 /* Return true if the target for GDBARCH has floating point hardware. */
392 riscv_has_fp_regs (struct gdbarch *gdbarch)
394 return (riscv_isa_flen (gdbarch) > 0);
397 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
400 riscv_has_fp_abi (struct gdbarch *gdbarch)
402 return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0);
405 /* Return true if REGNO is a floating pointer register. */
408 riscv_is_fp_regno_p (int regno)
410 return (regno >= RISCV_FIRST_FP_REGNUM
411 && regno <= RISCV_LAST_FP_REGNUM);
414 /* Implement the breakpoint_kind_from_pc gdbarch method. */
417 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
419 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
421 bool unaligned_p = false;
424 /* Some targets don't support unaligned reads. The address can only
425 be unaligned if the C extension is supported. So it is safe to
426 use a compressed breakpoint in this case. */
431 /* Read the opcode byte to determine the instruction length. */
432 read_code (*pcptr, buf, 1);
435 if (riscv_debug_breakpoints)
437 const char *bp = (unaligned_p || riscv_insn_length (buf[0]) == 2
438 ? "C.EBREAK" : "EBREAK");
440 fprintf_unfiltered (gdb_stdlog, "Using %s for breakpoint at %s ",
441 bp, paddress (gdbarch, *pcptr));
443 fprintf_unfiltered (gdb_stdlog, "(unaligned address)\n");
445 fprintf_unfiltered (gdb_stdlog, "(instruction length %d)\n",
446 riscv_insn_length (buf[0]));
448 if (unaligned_p || riscv_insn_length (buf[0]) == 2)
453 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
459 /* Implement the sw_breakpoint_from_kind gdbarch method. */
461 static const gdb_byte *
462 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
464 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
465 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
475 gdb_assert_not_reached (_("unhandled breakpoint kind"));
479 /* Callback function for user_reg_add. */
481 static struct value *
482 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
484 const int *reg_p = (const int *) baton;
485 return value_of_register (*reg_p, frame);
488 /* Implement the register_name gdbarch method. */
491 riscv_register_name (struct gdbarch *gdbarch, int regnum)
493 /* Prefer to use the alias. */
494 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
496 gdb_assert (regnum < ARRAY_SIZE (riscv_gdb_reg_names));
497 return riscv_gdb_reg_names[regnum];
500 /* Check that there's no gap between the set of registers handled above,
501 and the set of registers handled next. */
502 gdb_assert ((RISCV_LAST_FP_REGNUM + 1) == RISCV_FIRST_CSR_REGNUM);
504 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
506 #define DECLARE_CSR(NAME,VALUE) \
507 case RISCV_ ## VALUE ## _REGNUM: return # NAME;
511 #include "opcode/riscv-opc.h"
516 xsnprintf (buf, sizeof (buf), "csr%d",
517 regnum - RISCV_FIRST_CSR_REGNUM);
524 if (regnum == RISCV_PRIV_REGNUM)
530 /* Construct a type for 64-bit FP registers. */
533 riscv_fpreg_d_type (struct gdbarch *gdbarch)
535 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
537 if (tdep->riscv_fpreg_d_type == nullptr)
539 const struct builtin_type *bt = builtin_type (gdbarch);
541 /* The type we're building is this: */
543 union __gdb_builtin_type_fpreg_d
552 t = arch_composite_type (gdbarch,
553 "__gdb_builtin_type_fpreg_d", TYPE_CODE_UNION);
554 append_composite_type_field (t, "float", bt->builtin_float);
555 append_composite_type_field (t, "double", bt->builtin_double);
557 TYPE_NAME (t) = "builtin_type_fpreg_d";
558 tdep->riscv_fpreg_d_type = t;
561 return tdep->riscv_fpreg_d_type;
564 /* Construct a type for 128-bit FP registers. */
567 riscv_fpreg_q_type (struct gdbarch *gdbarch)
569 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
571 if (tdep->riscv_fpreg_q_type == nullptr)
573 const struct builtin_type *bt = builtin_type (gdbarch);
575 /* The type we're building is this: */
577 union __gdb_builtin_type_fpreg_d
587 t = arch_composite_type (gdbarch,
588 "__gdb_builtin_type_fpreg_q", TYPE_CODE_UNION);
589 append_composite_type_field (t, "float", bt->builtin_float);
590 append_composite_type_field (t, "double", bt->builtin_double);
591 append_composite_type_field (t, "long double", bt->builtin_long_double);
593 TYPE_NAME (t) = "builtin_type_fpreg_q";
594 tdep->riscv_fpreg_q_type = t;
597 return tdep->riscv_fpreg_q_type;
600 /* Implement the register_type gdbarch method. */
603 riscv_register_type (struct gdbarch *gdbarch, int regnum)
607 if (regnum < RISCV_FIRST_FP_REGNUM)
609 if (regnum == gdbarch_pc_regnum (gdbarch)
610 || regnum == RISCV_RA_REGNUM)
611 return builtin_type (gdbarch)->builtin_func_ptr;
613 if (regnum == RISCV_FP_REGNUM
614 || regnum == RISCV_SP_REGNUM
615 || regnum == RISCV_GP_REGNUM
616 || regnum == RISCV_TP_REGNUM)
617 return builtin_type (gdbarch)->builtin_data_ptr;
619 /* Remaining GPRs vary in size based on the current ISA. */
620 regsize = riscv_isa_xlen (gdbarch);
624 return builtin_type (gdbarch)->builtin_uint32;
626 return builtin_type (gdbarch)->builtin_uint64;
628 return builtin_type (gdbarch)->builtin_uint128;
630 internal_error (__FILE__, __LINE__,
631 _("unknown isa regsize %i"), regsize);
634 else if (regnum <= RISCV_LAST_FP_REGNUM)
636 regsize = riscv_isa_xlen (gdbarch);
640 return builtin_type (gdbarch)->builtin_float;
642 return riscv_fpreg_d_type (gdbarch);
644 return riscv_fpreg_q_type (gdbarch);
646 internal_error (__FILE__, __LINE__,
647 _("unknown isa regsize %i"), regsize);
650 else if (regnum == RISCV_PRIV_REGNUM)
651 return builtin_type (gdbarch)->builtin_int8;
654 if (regnum == RISCV_CSR_FFLAGS_REGNUM
655 || regnum == RISCV_CSR_FRM_REGNUM
656 || regnum == RISCV_CSR_FCSR_REGNUM)
657 return builtin_type (gdbarch)->builtin_int32;
659 regsize = riscv_isa_xlen (gdbarch);
663 return builtin_type (gdbarch)->builtin_int32;
665 return builtin_type (gdbarch)->builtin_int64;
667 return builtin_type (gdbarch)->builtin_int128;
669 internal_error (__FILE__, __LINE__,
670 _("unknown isa regsize %i"), regsize);
675 /* Helper for riscv_print_registers_info, prints info for a single register
679 riscv_print_one_register_info (struct gdbarch *gdbarch,
680 struct ui_file *file,
681 struct frame_info *frame,
684 const char *name = gdbarch_register_name (gdbarch, regnum);
685 struct value *val = value_of_register (regnum, frame);
686 struct type *regtype = value_type (val);
687 int print_raw_format;
688 enum tab_stops { value_column_1 = 15 };
690 fputs_filtered (name, file);
691 print_spaces_filtered (value_column_1 - strlen (name), file);
693 print_raw_format = (value_entirely_available (val)
694 && !value_optimized_out (val));
696 if (TYPE_CODE (regtype) == TYPE_CODE_FLT
697 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
698 && TYPE_NFIELDS (regtype) == 2
699 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
700 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT)
701 || (TYPE_CODE (regtype) == TYPE_CODE_UNION
702 && TYPE_NFIELDS (regtype) == 3
703 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 0)) == TYPE_CODE_FLT
704 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 1)) == TYPE_CODE_FLT
705 && TYPE_CODE (TYPE_FIELD_TYPE (regtype, 2)) == TYPE_CODE_FLT))
707 struct value_print_options opts;
708 const gdb_byte *valaddr = value_contents_for_printing (val);
709 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
711 get_user_print_options (&opts);
715 value_embedded_offset (val), 0,
716 file, 0, val, &opts, current_language);
718 if (print_raw_format)
720 fprintf_filtered (file, "\t(raw ");
721 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
723 fprintf_filtered (file, ")");
728 struct value_print_options opts;
730 /* Print the register in hex. */
731 get_formatted_print_options (&opts, 'x');
734 value_embedded_offset (val), 0,
735 file, 0, val, &opts, current_language);
737 if (print_raw_format)
739 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
742 int size = register_size (gdbarch, regnum);
745 d = value_as_long (val);
747 fprintf_filtered (file,
748 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
749 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
750 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
751 (int) ((d >> (xlen - 1)) & 0x1),
752 (int) ((d >> 24) & 0x1f),
753 (int) ((d >> 19) & 0x1),
754 (int) ((d >> 18) & 0x1),
755 (int) ((d >> 17) & 0x1),
756 (int) ((d >> 15) & 0x3),
757 (int) ((d >> 13) & 0x3),
758 (int) ((d >> 11) & 0x3),
759 (int) ((d >> 9) & 0x3),
760 (int) ((d >> 8) & 0x1),
761 (int) ((d >> 7) & 0x1),
762 (int) ((d >> 6) & 0x1),
763 (int) ((d >> 5) & 0x1),
764 (int) ((d >> 4) & 0x1),
765 (int) ((d >> 3) & 0x1),
766 (int) ((d >> 2) & 0x1),
767 (int) ((d >> 1) & 0x1),
768 (int) ((d >> 0) & 0x1));
770 else if (regnum == RISCV_CSR_MISA_REGNUM)
776 d = value_as_long (val);
780 for (; base > 0; base--)
782 fprintf_filtered (file, "\tRV%d", xlen);
784 for (i = 0; i < 26; i++)
787 fprintf_filtered (file, "%c", 'A' + i);
790 else if (regnum == RISCV_CSR_FCSR_REGNUM
791 || regnum == RISCV_CSR_FFLAGS_REGNUM
792 || regnum == RISCV_CSR_FRM_REGNUM)
796 d = value_as_long (val);
798 fprintf_filtered (file, "\t");
799 if (regnum != RISCV_CSR_FRM_REGNUM)
800 fprintf_filtered (file,
801 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
802 (int) ((d >> 5) & 0x7),
803 (int) ((d >> 4) & 0x1),
804 (int) ((d >> 3) & 0x1),
805 (int) ((d >> 2) & 0x1),
806 (int) ((d >> 1) & 0x1),
807 (int) ((d >> 0) & 0x1));
809 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
811 static const char * const sfrm[] =
813 "RNE (round to nearest; ties to even)",
814 "RTZ (Round towards zero)",
815 "RDN (Round down towards -INF)",
816 "RUP (Round up towards +INF)",
817 "RMM (Round to nearest; ties to max magnitude)",
820 "dynamic rounding mode",
822 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
823 ? (d >> 5) : d) & 0x3;
825 fprintf_filtered (file, "%sFRM:%i [%s]",
826 (regnum == RISCV_CSR_FCSR_REGNUM
831 else if (regnum == RISCV_PRIV_REGNUM)
836 d = value_as_long (val);
841 static const char * const sprv[] =
848 fprintf_filtered (file, "\tprv:%d [%s]",
852 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
856 /* If not a vector register, print it also according to its
858 if (TYPE_VECTOR (regtype) == 0)
860 get_user_print_options (&opts);
862 fprintf_filtered (file, "\t");
864 value_embedded_offset (val), 0,
865 file, 0, val, &opts, current_language);
870 fprintf_filtered (file, "\n");
873 /* Return true if REGNUM is a valid CSR register. The CSR register space
874 is sparsely populated, so not every number is a named CSR. */
877 riscv_is_regnum_a_named_csr (int regnum)
879 gdb_assert (regnum >= RISCV_FIRST_CSR_REGNUM
880 && regnum <= RISCV_LAST_CSR_REGNUM);
884 #define DECLARE_CSR(name, num) case RISCV_ ## num ## _REGNUM:
885 #include "opcode/riscv-opc.h"
894 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
898 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
899 struct reggroup *reggroup)
901 /* Used by 'info registers' and 'info registers <groupname>'. */
903 if (gdbarch_register_name (gdbarch, regnum) == NULL
904 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
907 if (reggroup == all_reggroup)
909 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
911 if (riscv_is_regnum_a_named_csr (regnum))
915 else if (reggroup == float_reggroup)
916 return (riscv_is_fp_regno_p (regnum)
917 || regnum == RISCV_CSR_FCSR_REGNUM
918 || regnum == RISCV_CSR_FFLAGS_REGNUM
919 || regnum == RISCV_CSR_FRM_REGNUM);
920 else if (reggroup == general_reggroup)
921 return regnum < RISCV_FIRST_FP_REGNUM;
922 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
924 if (riscv_has_fp_regs (gdbarch))
925 return regnum <= RISCV_LAST_FP_REGNUM;
927 return regnum < RISCV_FIRST_FP_REGNUM;
929 else if (reggroup == system_reggroup)
931 if (regnum == RISCV_PRIV_REGNUM)
933 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
935 if (riscv_is_regnum_a_named_csr (regnum))
939 else if (reggroup == vector_reggroup)
945 /* Implement the print_registers_info gdbarch method. This is used by
946 'info registers' and 'info all-registers'. */
949 riscv_print_registers_info (struct gdbarch *gdbarch,
950 struct ui_file *file,
951 struct frame_info *frame,
952 int regnum, int print_all)
956 /* Print one specified register. */
957 gdb_assert (regnum <= RISCV_LAST_REGNUM);
958 if (gdbarch_register_name (gdbarch, regnum) == NULL
959 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
960 error (_("Not a valid register for the current processor type"));
961 riscv_print_one_register_info (gdbarch, file, frame, regnum);
965 struct reggroup *reggroup;
968 reggroup = all_reggroup;
970 reggroup = general_reggroup;
972 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
974 /* Zero never changes, so might as well hide by default. */
975 if (regnum == RISCV_ZERO_REGNUM && !print_all)
978 /* Registers with no name are not valid on this ISA. */
979 if (gdbarch_register_name (gdbarch, regnum) == NULL
980 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
983 /* Is the register in the group we're interested in? */
984 if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup))
987 riscv_print_one_register_info (gdbarch, file, frame, regnum);
992 /* Class that handles one decoded RiscV instruction. */
998 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
1001 /* Unknown value is used at initialisation time. */
1004 /* These instructions are all the ones we are interested in during the
1014 /* These are needed for software breakopint support. */
1023 /* These are needed for stepping over atomic sequences. */
1027 /* Other instructions are not interesting during the prologue scan, and
1042 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
1044 /* Get the length of the instruction in bytes. */
1046 { return m_length; }
1048 /* Get the opcode for this instruction. */
1049 enum opcode opcode () const
1050 { return m_opcode; }
1052 /* Get destination register field for this instruction. This is only
1053 valid if the OPCODE implies there is such a field for this
1058 /* Get the RS1 register field for this instruction. This is only valid
1059 if the OPCODE implies there is such a field for this instruction. */
1063 /* Get the RS2 register field for this instruction. This is only valid
1064 if the OPCODE implies there is such a field for this instruction. */
1068 /* Get the immediate for this instruction in signed form. This is only
1069 valid if the OPCODE implies there is such a field for this
1071 int imm_signed () const
1076 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1077 int decode_register_index (unsigned long opcode, int offset)
1079 return (opcode >> offset) & 0x1F;
1082 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
1083 int decode_register_index_short (unsigned long opcode, int offset)
1085 return ((opcode >> offset) & 0x7) + 8;
1088 /* Helper for DECODE, decode 32-bit R-type instruction. */
1089 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
1092 m_rd = decode_register_index (ival, OP_SH_RD);
1093 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1094 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1097 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
1098 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
1101 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1102 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1105 /* Helper for DECODE, decode 32-bit I-type instruction. */
1106 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
1109 m_rd = decode_register_index (ival, OP_SH_RD);
1110 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1111 m_imm.s = EXTRACT_ITYPE_IMM (ival);
1114 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
1115 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
1118 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
1119 m_imm.s = EXTRACT_RVC_IMM (ival);
1122 /* Helper for DECODE, decode 32-bit S-type instruction. */
1123 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
1126 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1127 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1128 m_imm.s = EXTRACT_STYPE_IMM (ival);
1131 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1132 encoding is different for each CS format instruction, so extracting
1133 the immediate is left up to the caller, who should pass the extracted
1134 immediate value through in IMM. */
1135 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1139 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1140 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1143 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1144 encoding is different for each CSS format instruction, so extracting
1145 the immediate is left up to the caller, who should pass the extracted
1146 immediate value through in IMM. */
1147 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1151 m_rs1 = RISCV_SP_REGNUM;
1152 /* Not a compressed register number in this case. */
1153 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1156 /* Helper for DECODE, decode 32-bit U-type instruction. */
1157 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1160 m_rd = decode_register_index (ival, OP_SH_RD);
1161 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1164 /* Helper for DECODE, decode 32-bit J-type instruction. */
1165 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1168 m_rd = decode_register_index (ival, OP_SH_RD);
1169 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1172 /* Helper for DECODE, decode 32-bit J-type instruction. */
1173 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1176 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1179 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1182 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1183 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1184 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1187 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1190 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1191 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1194 /* Fetch instruction from target memory at ADDR, return the content of
1195 the instruction, and update LEN with the instruction length. */
1196 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1197 CORE_ADDR addr, int *len);
1199 /* The length of the instruction in bytes. Should be 2 or 4. */
1202 /* The instruction opcode. */
1203 enum opcode m_opcode;
1205 /* The three possible registers an instruction might reference. Not
1206 every instruction fills in all of these registers. Which fields are
1207 valid depends on the opcode. The naming of these fields matches the
1208 naming in the riscv isa manual. */
1213 /* Possible instruction immediate. This is only valid if the instruction
1214 format contains an immediate, not all instruction, whether this is
1215 valid depends on the opcode. Despite only having one format for now
1216 the immediate is packed into a union, later instructions might require
1217 an unsigned formatted immediate, having the union in place now will
1218 reduce the need for code churn later. */
1219 union riscv_insn_immediate
1221 riscv_insn_immediate ()
1231 /* Fetch instruction from target memory at ADDR, return the content of the
1232 instruction, and update LEN with the instruction length. */
1235 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1236 CORE_ADDR addr, int *len)
1238 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1240 int instlen, status;
1242 /* All insns are at least 16 bits. */
1243 status = target_read_memory (addr, buf, 2);
1245 memory_error (TARGET_XFER_E_IO, addr);
1247 /* If we need more, grab it now. */
1248 instlen = riscv_insn_length (buf[0]);
1249 gdb_assert (instlen <= sizeof (buf));
1254 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1256 memory_error (TARGET_XFER_E_IO, addr + 2);
1259 return extract_unsigned_integer (buf, instlen, byte_order);
1262 /* Fetch from target memory an instruction at PC and decode it. This can
1263 throw an error if the memory access fails, callers are responsible for
1264 handling this error if that is appropriate. */
1267 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1271 /* Fetch the instruction, and the instructions length. */
1272 ival = fetch_instruction (gdbarch, pc, &m_length);
1276 if (is_add_insn (ival))
1277 decode_r_type_insn (ADD, ival);
1278 else if (is_addw_insn (ival))
1279 decode_r_type_insn (ADDW, ival);
1280 else if (is_addi_insn (ival))
1281 decode_i_type_insn (ADDI, ival);
1282 else if (is_addiw_insn (ival))
1283 decode_i_type_insn (ADDIW, ival);
1284 else if (is_auipc_insn (ival))
1285 decode_u_type_insn (AUIPC, ival);
1286 else if (is_lui_insn (ival))
1287 decode_u_type_insn (LUI, ival);
1288 else if (is_sd_insn (ival))
1289 decode_s_type_insn (SD, ival);
1290 else if (is_sw_insn (ival))
1291 decode_s_type_insn (SW, ival);
1292 else if (is_jal_insn (ival))
1293 decode_j_type_insn (JAL, ival);
1294 else if (is_jalr_insn (ival))
1295 decode_i_type_insn (JALR, ival);
1296 else if (is_beq_insn (ival))
1297 decode_b_type_insn (BEQ, ival);
1298 else if (is_bne_insn (ival))
1299 decode_b_type_insn (BNE, ival);
1300 else if (is_blt_insn (ival))
1301 decode_b_type_insn (BLT, ival);
1302 else if (is_bge_insn (ival))
1303 decode_b_type_insn (BGE, ival);
1304 else if (is_bltu_insn (ival))
1305 decode_b_type_insn (BLTU, ival);
1306 else if (is_bgeu_insn (ival))
1307 decode_b_type_insn (BGEU, ival);
1308 else if (is_lr_w_insn (ival))
1309 decode_r_type_insn (LR, ival);
1310 else if (is_lr_d_insn (ival))
1311 decode_r_type_insn (LR, ival);
1312 else if (is_sc_w_insn (ival))
1313 decode_r_type_insn (SC, ival);
1314 else if (is_sc_d_insn (ival))
1315 decode_r_type_insn (SC, ival);
1317 /* None of the other fields are valid in this case. */
1320 else if (m_length == 2)
1322 int xlen = riscv_isa_xlen (gdbarch);
1324 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1325 C_JALR. So must try to match C_JALR first as it has more bits in
1327 if (is_c_jalr_insn (ival))
1328 decode_cr_type_insn (JALR, ival);
1329 else if (is_c_add_insn (ival))
1330 decode_cr_type_insn (ADD, ival);
1331 /* C_ADDW is RV64 and RV128 only. */
1332 else if (xlen != 4 && is_c_addw_insn (ival))
1333 decode_cr_type_insn (ADDW, ival);
1334 else if (is_c_addi_insn (ival))
1335 decode_ci_type_insn (ADDI, ival);
1336 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1337 only and C_JAL is RV32 only. */
1338 else if (xlen != 4 && is_c_addiw_insn (ival))
1339 decode_ci_type_insn (ADDIW, ival);
1340 else if (xlen == 4 && is_c_jal_insn (ival))
1341 decode_cj_type_insn (JAL, ival);
1342 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1343 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1345 else if (is_c_addi16sp_insn (ival))
1348 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1349 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1351 else if (is_c_addi4spn_insn (ival))
1354 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1355 m_rs1 = RISCV_SP_REGNUM;
1356 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1358 else if (is_c_lui_insn (ival))
1361 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1362 m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
1364 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1365 and C_FSW is RV32 only. */
1366 else if (xlen != 4 && is_c_sd_insn (ival))
1367 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
1368 else if (is_c_sw_insn (ival))
1369 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1370 else if (is_c_swsp_insn (ival))
1371 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1372 else if (xlen != 4 && is_c_sdsp_insn (ival))
1373 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
1374 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1375 So must try to match C_JR first as it ahs more bits in mask. */
1376 else if (is_c_jr_insn (ival))
1377 decode_cr_type_insn (JALR, ival);
1378 else if (is_c_j_insn (ival))
1379 decode_cj_type_insn (JAL, ival);
1380 else if (is_c_beqz_insn (ival))
1381 decode_cb_type_insn (BEQ, ival);
1382 else if (is_c_bnez_insn (ival))
1383 decode_cb_type_insn (BNE, ival);
1385 /* None of the other fields of INSN are valid in this case. */
1389 internal_error (__FILE__, __LINE__,
1390 _("unable to decode %d byte instructions in "
1391 "prologue at %s"), m_length,
1392 core_addr_to_string (pc));
1395 /* The prologue scanner. This is currently only used for skipping the
1396 prologue of a function when the DWARF information is not sufficient.
1397 However, it is written with filling of the frame cache in mind, which
1398 is why different groups of stack setup instructions are split apart
1399 during the core of the inner loop. In the future, the intention is to
1400 extend this function to fully support building up a frame cache that
1401 can unwind register values when there is no DWARF information. */
1404 riscv_scan_prologue (struct gdbarch *gdbarch,
1405 CORE_ADDR start_pc, CORE_ADDR end_pc,
1406 struct riscv_unwind_cache *cache)
1408 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1409 CORE_ADDR end_prologue_addr = 0;
1411 /* Find an upper limit on the function prologue using the debug
1412 information. If the debug information could not be used to provide
1413 that bound, then use an arbitrary large number as the upper bound. */
1414 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1415 if (after_prologue_pc == 0)
1416 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1417 if (after_prologue_pc < end_pc)
1418 end_pc = after_prologue_pc;
1420 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1421 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1422 regs[regno] = pv_register (regno, 0);
1423 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1425 if (riscv_debug_unwinder)
1428 "Prologue scan for function starting at %s (limit %s)\n",
1429 core_addr_to_string (start_pc),
1430 core_addr_to_string (end_pc));
1432 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1434 struct riscv_insn insn;
1436 /* Decode the current instruction, and decide where the next
1437 instruction lives based on the size of this instruction. */
1438 insn.decode (gdbarch, cur_pc);
1439 gdb_assert (insn.length () > 0);
1440 next_pc = cur_pc + insn.length ();
1442 /* Look for common stack adjustment insns. */
1443 if ((insn.opcode () == riscv_insn::ADDI
1444 || insn.opcode () == riscv_insn::ADDIW)
1445 && insn.rd () == RISCV_SP_REGNUM
1446 && insn.rs1 () == RISCV_SP_REGNUM)
1448 /* Handle: addi sp, sp, -i
1449 or: addiw sp, sp, -i */
1450 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1451 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1453 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1455 else if ((insn.opcode () == riscv_insn::SW
1456 || insn.opcode () == riscv_insn::SD)
1457 && (insn.rs1 () == RISCV_SP_REGNUM
1458 || insn.rs1 () == RISCV_FP_REGNUM))
1460 /* Handle: sw reg, offset(sp)
1461 or: sd reg, offset(sp)
1462 or: sw reg, offset(s0)
1463 or: sd reg, offset(s0) */
1464 /* Instruction storing a register onto the stack. */
1465 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1466 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1467 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1468 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1471 else if (insn.opcode () == riscv_insn::ADDI
1472 && insn.rd () == RISCV_FP_REGNUM
1473 && insn.rs1 () == RISCV_SP_REGNUM)
1475 /* Handle: addi s0, sp, size */
1476 /* Instructions setting up the frame pointer. */
1477 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1478 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1480 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1482 else if ((insn.opcode () == riscv_insn::ADD
1483 || insn.opcode () == riscv_insn::ADDW)
1484 && insn.rd () == RISCV_FP_REGNUM
1485 && insn.rs1 () == RISCV_SP_REGNUM
1486 && insn.rs2 () == RISCV_ZERO_REGNUM)
1488 /* Handle: add s0, sp, 0
1489 or: addw s0, sp, 0 */
1490 /* Instructions setting up the frame pointer. */
1491 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1492 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1493 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1495 else if ((insn.opcode () == riscv_insn::ADDI
1496 && insn.rd () == RISCV_ZERO_REGNUM
1497 && insn.rs1 () == RISCV_ZERO_REGNUM
1498 && insn.imm_signed () == 0))
1500 /* Handle: add x0, x0, 0 (NOP) */
1502 else if (insn.opcode () == riscv_insn::AUIPC)
1504 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1505 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1507 else if (insn.opcode () == riscv_insn::LUI)
1509 /* Handle: lui REG, n
1510 Where REG is not gp register. */
1511 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1512 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1514 else if (insn.opcode () == riscv_insn::ADDI)
1516 /* Handle: addi REG1, REG2, IMM */
1517 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1518 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1520 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1522 else if (insn.opcode () == riscv_insn::ADD)
1524 /* Handle: addi REG1, REG2, IMM */
1525 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1526 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1527 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1528 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1532 end_prologue_addr = cur_pc;
1537 if (end_prologue_addr == 0)
1538 end_prologue_addr = cur_pc;
1540 if (riscv_debug_unwinder)
1541 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1542 core_addr_to_string (end_prologue_addr));
1546 /* Figure out if it is a frame pointer or just a stack pointer. Also
1547 the offset held in the pv_t is from the original register value to
1548 the current value, which for a grows down stack means a negative
1549 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1550 from the current value to the original value. */
1551 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1553 cache->frame_base_reg = RISCV_FP_REGNUM;
1554 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1558 cache->frame_base_reg = RISCV_SP_REGNUM;
1559 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1562 /* Assign offset from old SP to all saved registers. As we don't
1563 have the previous value for the frame base register at this
1564 point, we store the offset as the address in the trad_frame, and
1565 then convert this to an actual address later. */
1566 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1569 if (stack.find_reg (gdbarch, i, &offset))
1571 if (riscv_debug_unwinder)
1572 fprintf_unfiltered (gdb_stdlog,
1573 "Register $%s at stack offset %ld\n",
1574 gdbarch_register_name (gdbarch, i),
1576 trad_frame_set_addr (cache->regs, i, offset);
1581 return end_prologue_addr;
1584 /* Implement the riscv_skip_prologue gdbarch method. */
1587 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1589 CORE_ADDR func_addr;
1591 /* See if we can determine the end of the prologue via the symbol
1592 table. If so, then return either PC, or the PC after the
1593 prologue, whichever is greater. */
1594 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1596 CORE_ADDR post_prologue_pc
1597 = skip_prologue_using_sal (gdbarch, func_addr);
1599 if (post_prologue_pc != 0)
1600 return std::max (pc, post_prologue_pc);
1603 /* Can't determine prologue from the symbol table, need to examine
1604 instructions. Pass -1 for the end address to indicate the prologue
1605 scanner can scan as far as it needs to find the end of the prologue. */
1606 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1609 /* Implement the gdbarch push dummy code callback. */
1612 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1613 CORE_ADDR funaddr, struct value **args, int nargs,
1614 struct type *value_type, CORE_ADDR *real_pc,
1615 CORE_ADDR *bp_addr, struct regcache *regcache)
1617 /* Allocate space for a breakpoint, and keep the stack correctly
1625 /* Compute the alignment of the type T. Used while setting up the
1626 arguments for a dummy call. */
1629 riscv_type_alignment (struct type *t)
1631 t = check_typedef (t);
1632 switch (TYPE_CODE (t))
1635 error (_("Could not compute alignment of type"));
1637 case TYPE_CODE_RVALUE_REF:
1639 case TYPE_CODE_ENUM:
1643 case TYPE_CODE_CHAR:
1644 case TYPE_CODE_BOOL:
1645 return TYPE_LENGTH (t);
1647 case TYPE_CODE_ARRAY:
1648 if (TYPE_VECTOR (t))
1649 return std::min (TYPE_LENGTH (t), (unsigned) BIGGEST_ALIGNMENT);
1652 case TYPE_CODE_COMPLEX:
1653 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1655 case TYPE_CODE_STRUCT:
1656 case TYPE_CODE_UNION:
1661 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1663 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1665 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1675 /* Holds information about a single argument either being passed to an
1676 inferior function, or returned from an inferior function. This includes
1677 information about the size, type, etc of the argument, and also
1678 information about how the argument will be passed (or returned). */
1680 struct riscv_arg_info
1682 /* Contents of the argument. */
1683 const gdb_byte *contents;
1685 /* Length of argument. */
1688 /* Alignment required for an argument of this type. */
1691 /* The type for this argument. */
1694 /* Each argument can have either 1 or 2 locations assigned to it. Each
1695 location describes where part of the argument will be placed. The
1696 second location is valid based on the LOC_TYPE and C_LENGTH fields
1697 of the first location (which is always valid). */
1700 /* What type of location this is. */
1703 /* Argument passed in a register. */
1706 /* Argument passed as an on stack argument. */
1709 /* Argument passed by reference. The second location is always
1710 valid for a BY_REF argument, and describes where the address
1711 of the BY_REF argument should be placed. */
1715 /* Information that depends on the location type. */
1718 /* Which register number to use. */
1721 /* The offset into the stack region. */
1725 /* The length of contents covered by this location. If this is less
1726 than the total length of the argument, then the second location
1727 will be valid, and will describe where the rest of the argument
1731 /* The offset within CONTENTS for this part of the argument. Will
1732 always be 0 for the first part. For the second part of the
1733 argument, this might be the C_LENGTH value of the first part,
1734 however, if we are passing a structure in two registers, and there's
1735 is padding between the first and second field, then this offset
1736 might be greater than the length of the first argument part. When
1737 the second argument location is not holding part of the argument
1738 value, but is instead holding the address of a reference argument,
1739 then this offset will be set to 0. */
1744 /* Information about a set of registers being used for passing arguments as
1745 part of a function call. The register set must be numerically
1746 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1747 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1749 struct riscv_arg_reg
1751 riscv_arg_reg (int first, int last)
1752 : next_regnum (first),
1758 /* The GDB register number to use in this set. */
1761 /* The last GDB register number to use in this set. */
1765 /* Arguments can be passed as on stack arguments, or by reference. The
1766 on stack arguments must be in a continuous region starting from $sp,
1767 while the by reference arguments can be anywhere, but we'll put them
1768 on the stack after (at higher address) the on stack arguments.
1770 This might not be the right approach to take. The ABI is clear that
1771 an argument passed by reference can be modified by the callee, which
1772 us placing the argument (temporarily) onto the stack will not achieve
1773 (changes will be lost). There's also the possibility that very large
1774 arguments could overflow the stack.
1776 This struct is used to track offset into these two areas for where
1777 arguments are to be placed. */
1778 struct riscv_memory_offsets
1780 riscv_memory_offsets ()
1787 /* Offset into on stack argument area. */
1790 /* Offset into the pass by reference area. */
1794 /* Holds information about where arguments to a call will be placed. This
1795 is updated as arguments are added onto the call, and can be used to
1796 figure out where the next argument should be placed. */
1798 struct riscv_call_info
1800 riscv_call_info (struct gdbarch *gdbarch)
1801 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1802 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1804 xlen = riscv_isa_xlen (gdbarch);
1805 flen = riscv_isa_flen (gdbarch);
1807 /* Disable use of floating point registers if needed. */
1808 if (!riscv_has_fp_abi (gdbarch))
1809 float_regs.next_regnum = float_regs.last_regnum + 1;
1812 /* Track the memory areas used for holding in-memory arguments to a
1814 struct riscv_memory_offsets memory;
1816 /* Holds information about the next integer register to use for passing
1818 struct riscv_arg_reg int_regs;
1820 /* Holds information about the next floating point register to use for
1821 passing an argument. */
1822 struct riscv_arg_reg float_regs;
1824 /* The XLEN and FLEN are copied in to this structure for convenience, and
1825 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1830 /* Return the number of registers available for use as parameters in the
1831 register set REG. Returned value can be 0 or more. */
1834 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1836 if (reg->next_regnum > reg->last_regnum)
1839 return (reg->last_regnum - reg->next_regnum + 1);
1842 /* If there is at least one register available in the register set REG then
1843 the next register from REG is assigned to LOC and the length field of
1844 LOC is updated to LENGTH. The register set REG is updated to indicate
1845 that the assigned register is no longer available and the function
1848 If there are no registers available in REG then the function returns
1849 false, and LOC and REG are unchanged. */
1852 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1853 struct riscv_arg_reg *reg,
1854 int length, int offset)
1856 if (reg->next_regnum <= reg->last_regnum)
1858 loc->loc_type = riscv_arg_info::location::in_reg;
1859 loc->loc_data.regno = reg->next_regnum;
1861 loc->c_length = length;
1862 loc->c_offset = offset;
1869 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1870 record that an area of stack has been used to hold the parameter
1873 The length field of LOC is updated to LENGTH, the length of the
1874 parameter being stored, and ALIGN is the alignment required by the
1875 parameter, which will affect how memory is allocated out of MEMORY. */
1878 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1879 struct riscv_memory_offsets *memory,
1880 int length, int align)
1882 loc->loc_type = riscv_arg_info::location::on_stack;
1884 = align_up (memory->arg_offset, align);
1885 loc->loc_data.offset = memory->arg_offset;
1886 memory->arg_offset += length;
1887 loc->c_length = length;
1889 /* Offset is always 0, either we're the first location part, in which
1890 case we're reading content from the start of the argument, or we're
1891 passing the address of a reference argument, so 0. */
1895 /* Update AINFO, which describes an argument that should be passed or
1896 returned using the integer ABI. The argloc fields within AINFO are
1897 updated to describe the location in which the argument will be passed to
1898 a function, or returned from a function.
1900 The CINFO structure contains the ongoing call information, the holds
1901 information such as which argument registers are remaining to be
1902 assigned to parameter, and how much memory has been used by parameters
1905 By examining the state of CINFO a suitable location can be selected,
1906 and assigned to AINFO. */
1909 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1910 struct riscv_call_info *cinfo)
1912 if (ainfo->length > (2 * cinfo->xlen))
1914 /* Argument is going to be passed by reference. */
1915 ainfo->argloc[0].loc_type
1916 = riscv_arg_info::location::by_ref;
1917 cinfo->memory.ref_offset
1918 = align_up (cinfo->memory.ref_offset, ainfo->align);
1919 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1920 cinfo->memory.ref_offset += ainfo->length;
1921 ainfo->argloc[0].c_length = ainfo->length;
1923 /* The second location for this argument is given over to holding the
1924 address of the by-reference data. Pass 0 for the offset as this
1925 is not part of the actual argument value. */
1926 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1929 riscv_assign_stack_location (&ainfo->argloc[1],
1930 &cinfo->memory, cinfo->xlen,
1935 int len = std::min (ainfo->length, cinfo->xlen);
1936 int align = std::max (ainfo->align, cinfo->xlen);
1938 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1939 &cinfo->int_regs, len, 0))
1940 riscv_assign_stack_location (&ainfo->argloc[0],
1941 &cinfo->memory, len, align);
1943 if (len < ainfo->length)
1945 len = ainfo->length - len;
1946 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1947 &cinfo->int_regs, len,
1949 riscv_assign_stack_location (&ainfo->argloc[1],
1950 &cinfo->memory, len, cinfo->xlen);
1955 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1956 is being passed with the floating point ABI. */
1959 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1960 struct riscv_call_info *cinfo)
1962 if (ainfo->length > cinfo->flen)
1963 return riscv_call_arg_scalar_int (ainfo, cinfo);
1966 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1969 return riscv_call_arg_scalar_int (ainfo, cinfo);
1973 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1974 is a complex floating point argument, and is therefore handled
1975 differently to other argument types. */
1978 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1979 struct riscv_call_info *cinfo)
1981 if (ainfo->length <= (2 * cinfo->flen)
1982 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1985 int len = ainfo->length / 2;
1987 result = riscv_assign_reg_location (&ainfo->argloc[0],
1988 &cinfo->float_regs, len, len);
1989 gdb_assert (result);
1991 result = riscv_assign_reg_location (&ainfo->argloc[1],
1992 &cinfo->float_regs, len, len);
1993 gdb_assert (result);
1996 return riscv_call_arg_scalar_int (ainfo, cinfo);
1999 /* A structure used for holding information about a structure type within
2000 the inferior program. The RiscV ABI has special rules for handling some
2001 structures with a single field or with two fields. The counting of
2002 fields here is done after flattening out all nested structures. */
2004 class riscv_struct_info
2007 riscv_struct_info ()
2008 : m_number_of_fields (0),
2009 m_types { nullptr, nullptr }
2014 /* Analyse TYPE descending into nested structures, count the number of
2015 scalar fields and record the types of the first two fields found. */
2016 void analyse (struct type *type);
2018 /* The number of scalar fields found in the analysed type. This is
2019 currently only accurate if the value returned is 0, 1, or 2 as the
2020 analysis stops counting when the number of fields is 3. This is
2021 because the RiscV ABI only has special cases for 1 or 2 fields,
2022 anything else we just don't care about. */
2023 int number_of_fields () const
2024 { return m_number_of_fields; }
2026 /* Return the type for scalar field INDEX within the analysed type. Will
2027 return nullptr if there is no field at that index. Only INDEX values
2028 0 and 1 can be requested as the RiscV ABI only has special cases for
2029 structures with 1 or 2 fields. */
2030 struct type *field_type (int index) const
2032 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
2033 return m_types[index];
2037 /* The number of scalar fields found within the structure after recursing
2038 into nested structures. */
2039 int m_number_of_fields;
2041 /* The types of the first two scalar fields found within the structure
2042 after recursing into nested structures. */
2043 struct type *m_types[2];
2046 /* Analyse TYPE descending into nested structures, count the number of
2047 scalar fields and record the types of the first two fields found. */
2050 riscv_struct_info::analyse (struct type *type)
2052 unsigned int count = TYPE_NFIELDS (type);
2055 for (i = 0; i < count; ++i)
2057 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
2060 struct type *field_type = TYPE_FIELD_TYPE (type, i);
2061 field_type = check_typedef (field_type);
2063 switch (TYPE_CODE (field_type))
2065 case TYPE_CODE_STRUCT:
2066 analyse (field_type);
2070 /* RiscV only flattens out structures. Anything else does not
2071 need to be flattened, we just record the type, and when we
2072 look at the analysis results we'll realise this is not a
2073 structure we can special case, and pass the structure in
2075 if (m_number_of_fields < 2)
2076 m_types[m_number_of_fields] = field_type;
2077 m_number_of_fields++;
2081 /* RiscV only has special handling for structures with 1 or 2 scalar
2082 fields, any more than that and the structure is just passed in
2083 memory. We can safely drop out early when we find 3 or more
2086 if (m_number_of_fields > 2)
2091 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
2092 is a structure. Small structures on RiscV have some special case
2093 handling in order that the structure might be passed in register.
2094 Larger structures are passed in memory. After assigning location
2095 information to AINFO, CINFO will have been updated. */
2098 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
2099 struct riscv_call_info *cinfo)
2101 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
2103 struct riscv_struct_info sinfo;
2105 sinfo.analyse (ainfo->type);
2106 if (sinfo.number_of_fields () == 1
2107 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
2109 gdb_assert (TYPE_LENGTH (ainfo->type)
2110 == TYPE_LENGTH (sinfo.field_type (0)));
2111 return riscv_call_arg_complex_float (ainfo, cinfo);
2114 if (sinfo.number_of_fields () == 1
2115 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
2117 gdb_assert (TYPE_LENGTH (ainfo->type)
2118 == TYPE_LENGTH (sinfo.field_type (0)));
2119 return riscv_call_arg_scalar_float (ainfo, cinfo);
2122 if (sinfo.number_of_fields () == 2
2123 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2124 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2125 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2126 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
2127 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
2129 int len0, len1, offset;
2131 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
2133 len0 = TYPE_LENGTH (sinfo.field_type (0));
2134 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2135 &cinfo->float_regs, len0, 0))
2136 error (_("failed during argument setup"));
2138 len1 = TYPE_LENGTH (sinfo.field_type (1));
2139 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2140 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2141 - TYPE_LENGTH (sinfo.field_type (0))));
2143 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2146 error (_("failed during argument setup"));
2150 if (sinfo.number_of_fields () == 2
2151 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2152 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2153 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2154 && is_integral_type (sinfo.field_type (1))
2155 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2157 int len0, len1, offset;
2159 gdb_assert (TYPE_LENGTH (ainfo->type)
2160 <= (cinfo->flen + cinfo->xlen));
2162 len0 = TYPE_LENGTH (sinfo.field_type (0));
2163 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2164 &cinfo->float_regs, len0, 0))
2165 error (_("failed during argument setup"));
2167 len1 = TYPE_LENGTH (sinfo.field_type (1));
2168 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2169 gdb_assert (len1 <= cinfo->xlen);
2170 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2171 &cinfo->int_regs, len1, offset))
2172 error (_("failed during argument setup"));
2176 if (sinfo.number_of_fields () == 2
2177 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2178 && (is_integral_type (sinfo.field_type (0))
2179 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2180 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2181 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2183 int len0, len1, offset;
2185 gdb_assert (TYPE_LENGTH (ainfo->type)
2186 <= (cinfo->flen + cinfo->xlen));
2188 len0 = TYPE_LENGTH (sinfo.field_type (0));
2189 len1 = TYPE_LENGTH (sinfo.field_type (1));
2190 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2192 gdb_assert (len0 <= cinfo->xlen);
2193 gdb_assert (len1 <= cinfo->flen);
2195 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2196 &cinfo->int_regs, len0, 0))
2197 error (_("failed during argument setup"));
2199 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2202 error (_("failed during argument setup"));
2208 /* Non of the structure flattening cases apply, so we just pass using
2210 ainfo->length = align_up (ainfo->length, cinfo->xlen);
2211 riscv_call_arg_scalar_int (ainfo, cinfo);
2214 /* Assign a location to call (or return) argument AINFO, the location is
2215 selected from CINFO which holds information about what call argument
2216 locations are available for use next. The TYPE is the type of the
2217 argument being passed, this information is recorded into AINFO (along
2218 with some additional information derived from the type).
2220 After assigning a location to AINFO, CINFO will have been updated. */
2223 riscv_arg_location (struct gdbarch *gdbarch,
2224 struct riscv_arg_info *ainfo,
2225 struct riscv_call_info *cinfo,
2229 ainfo->length = TYPE_LENGTH (ainfo->type);
2230 ainfo->align = riscv_type_alignment (ainfo->type);
2231 ainfo->contents = nullptr;
2233 switch (TYPE_CODE (ainfo->type))
2236 case TYPE_CODE_BOOL:
2237 case TYPE_CODE_CHAR:
2238 case TYPE_CODE_RANGE:
2239 case TYPE_CODE_ENUM:
2241 if (ainfo->length <= cinfo->xlen)
2243 ainfo->type = builtin_type (gdbarch)->builtin_long;
2244 ainfo->length = cinfo->xlen;
2246 else if (ainfo->length <= (2 * cinfo->xlen))
2248 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2249 ainfo->length = 2 * cinfo->xlen;
2252 /* Recalculate the alignment requirement. */
2253 ainfo->align = riscv_type_alignment (ainfo->type);
2254 riscv_call_arg_scalar_int (ainfo, cinfo);
2258 riscv_call_arg_scalar_float (ainfo, cinfo);
2261 case TYPE_CODE_COMPLEX:
2262 riscv_call_arg_complex_float (ainfo, cinfo);
2265 case TYPE_CODE_STRUCT:
2266 riscv_call_arg_struct (ainfo, cinfo);
2270 riscv_call_arg_scalar_int (ainfo, cinfo);
2275 /* Used for printing debug information about the call argument location in
2276 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2277 addresses for the location of pass-by-reference and
2278 arguments-on-the-stack memory areas. */
2281 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2282 struct riscv_arg_info *info,
2283 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2285 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2286 TYPE_SAFE_NAME (info->type), info->length, info->align);
2287 switch (info->argloc[0].loc_type)
2289 case riscv_arg_info::location::in_reg:
2291 (stream, ", register %s",
2292 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2293 if (info->argloc[0].c_length < info->length)
2295 switch (info->argloc[1].loc_type)
2297 case riscv_arg_info::location::in_reg:
2299 (stream, ", register %s",
2300 gdbarch_register_name (gdbarch,
2301 info->argloc[1].loc_data.regno));
2304 case riscv_arg_info::location::on_stack:
2305 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2306 info->argloc[1].loc_data.offset);
2309 case riscv_arg_info::location::by_ref:
2311 /* The second location should never be a reference, any
2312 argument being passed by reference just places its address
2313 in the first location and is done. */
2314 error (_("invalid argument location"));
2318 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2319 fprintf_unfiltered (stream, " (offset 0x%x)",
2320 info->argloc[1].c_offset);
2324 case riscv_arg_info::location::on_stack:
2325 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2326 info->argloc[0].loc_data.offset);
2329 case riscv_arg_info::location::by_ref:
2331 (stream, ", by reference, data at offset 0x%x (%s)",
2332 info->argloc[0].loc_data.offset,
2333 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2334 if (info->argloc[1].loc_type
2335 == riscv_arg_info::location::in_reg)
2337 (stream, ", address in register %s",
2338 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2341 gdb_assert (info->argloc[1].loc_type
2342 == riscv_arg_info::location::on_stack);
2344 (stream, ", address on stack at offset 0x%x (%s)",
2345 info->argloc[1].loc_data.offset,
2346 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2351 gdb_assert_not_reached (_("unknown argument location type"));
2355 /* Implement the push dummy call gdbarch callback. */
2358 riscv_push_dummy_call (struct gdbarch *gdbarch,
2359 struct value *function,
2360 struct regcache *regcache,
2363 struct value **args,
2366 CORE_ADDR struct_addr)
2369 CORE_ADDR sp_args, sp_refs;
2370 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2372 struct riscv_arg_info *arg_info =
2373 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2375 struct riscv_call_info call_info (gdbarch);
2379 /* We'll use register $a0 if we're returning a struct. */
2381 ++call_info.int_regs.next_regnum;
2383 for (i = 0; i < nargs; ++i)
2385 struct value *arg_value;
2386 struct type *arg_type;
2387 struct riscv_arg_info *info = &arg_info[i];
2389 arg_value = args[i];
2390 arg_type = check_typedef (value_type (arg_value));
2392 riscv_arg_location (gdbarch, info, &call_info, arg_type);
2394 if (info->type != arg_type)
2395 arg_value = value_cast (info->type, arg_value);
2396 info->contents = value_contents (arg_value);
2399 /* Adjust the stack pointer and align it. */
2400 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2401 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2403 if (riscv_debug_infcall > 0)
2405 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2406 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2407 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2408 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2409 call_info.xlen, call_info.flen);
2411 fprintf_unfiltered (gdb_stdlog,
2412 "[*] struct return pointer in register $A0\n");
2413 for (i = 0; i < nargs; ++i)
2415 struct riscv_arg_info *info = &arg_info [i];
2417 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2418 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2419 fprintf_unfiltered (gdb_stdlog, "\n");
2421 if (call_info.memory.arg_offset > 0
2422 || call_info.memory.ref_offset > 0)
2424 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2425 core_addr_to_string (osp));
2426 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2427 call_info.memory.arg_offset);
2428 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2429 call_info.memory.ref_offset);
2430 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2431 core_addr_to_string_nz (osp - sp));
2435 /* Now load the argument into registers, or onto the stack. */
2439 gdb_byte buf[sizeof (LONGEST)];
2441 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2442 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2445 for (i = 0; i < nargs; ++i)
2448 int second_arg_length = 0;
2449 const gdb_byte *second_arg_data;
2450 struct riscv_arg_info *info = &arg_info [i];
2452 gdb_assert (info->length > 0);
2454 switch (info->argloc[0].loc_type)
2456 case riscv_arg_info::location::in_reg:
2458 gdb_byte tmp [sizeof (ULONGEST)];
2460 gdb_assert (info->argloc[0].c_length <= info->length);
2461 /* FP values in FP registers must be NaN-boxed. */
2462 if (riscv_is_fp_regno_p (info->argloc[0].loc_data.regno)
2463 && info->argloc[0].c_length < call_info.flen)
2464 memset (tmp, -1, sizeof (tmp));
2466 memset (tmp, 0, sizeof (tmp));
2467 memcpy (tmp, info->contents, info->argloc[0].c_length);
2468 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2470 ((info->argloc[0].c_length < info->length)
2471 ? info->argloc[1].c_length : 0);
2472 second_arg_data = info->contents + info->argloc[1].c_offset;
2476 case riscv_arg_info::location::on_stack:
2477 dst = sp_args + info->argloc[0].loc_data.offset;
2478 write_memory (dst, info->contents, info->length);
2479 second_arg_length = 0;
2482 case riscv_arg_info::location::by_ref:
2483 dst = sp_refs + info->argloc[0].loc_data.offset;
2484 write_memory (dst, info->contents, info->length);
2486 second_arg_length = call_info.xlen;
2487 second_arg_data = (gdb_byte *) &dst;
2491 gdb_assert_not_reached (_("unknown argument location type"));
2494 if (second_arg_length > 0)
2496 switch (info->argloc[1].loc_type)
2498 case riscv_arg_info::location::in_reg:
2500 gdb_byte tmp [sizeof (ULONGEST)];
2502 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2503 && second_arg_length <= call_info.flen)
2504 || second_arg_length <= call_info.xlen);
2505 /* FP values in FP registers must be NaN-boxed. */
2506 if (riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2507 && second_arg_length < call_info.flen)
2508 memset (tmp, -1, sizeof (tmp));
2510 memset (tmp, 0, sizeof (tmp));
2511 memcpy (tmp, second_arg_data, second_arg_length);
2512 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2516 case riscv_arg_info::location::on_stack:
2520 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2521 write_memory (arg_addr, second_arg_data, second_arg_length);
2525 case riscv_arg_info::location::by_ref:
2527 /* The second location should never be a reference, any
2528 argument being passed by reference just places its address
2529 in the first location and is done. */
2530 error (_("invalid argument location"));
2536 /* Set the dummy return value to bp_addr.
2537 A dummy breakpoint will be setup to execute the call. */
2539 if (riscv_debug_infcall > 0)
2540 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2541 core_addr_to_string (bp_addr));
2542 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2544 /* Finally, update the stack pointer. */
2546 if (riscv_debug_infcall > 0)
2547 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2548 core_addr_to_string (sp));
2549 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2554 /* Implement the return_value gdbarch method. */
2556 static enum return_value_convention
2557 riscv_return_value (struct gdbarch *gdbarch,
2558 struct value *function,
2560 struct regcache *regcache,
2562 const gdb_byte *writebuf)
2564 struct riscv_call_info call_info (gdbarch);
2565 struct riscv_arg_info info;
2566 struct type *arg_type;
2568 arg_type = check_typedef (type);
2569 riscv_arg_location (gdbarch, &info, &call_info, arg_type);
2571 if (riscv_debug_infcall > 0)
2573 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2574 fprintf_unfiltered (gdb_stdlog, "[R] ");
2575 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2576 fprintf_unfiltered (gdb_stdlog, "\n");
2579 if (readbuf != nullptr || writebuf != nullptr)
2583 switch (info.argloc[0].loc_type)
2585 /* Return value in register(s). */
2586 case riscv_arg_info::location::in_reg:
2588 regnum = info.argloc[0].loc_data.regno;
2591 regcache->cooked_read (regnum, readbuf);
2594 regcache->cooked_write (regnum, writebuf);
2596 /* A return value in register can have a second part in a
2598 if (info.argloc[0].c_length < info.length)
2600 switch (info.argloc[1].loc_type)
2602 case riscv_arg_info::location::in_reg:
2603 regnum = info.argloc[1].loc_data.regno;
2607 readbuf += info.argloc[1].c_offset;
2608 regcache->cooked_read (regnum, readbuf);
2613 writebuf += info.argloc[1].c_offset;
2614 regcache->cooked_write (regnum, writebuf);
2618 case riscv_arg_info::location::by_ref:
2619 case riscv_arg_info::location::on_stack:
2621 error (_("invalid argument location"));
2628 /* Return value by reference will have its address in A0. */
2629 case riscv_arg_info::location::by_ref:
2633 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2635 if (readbuf != nullptr)
2636 read_memory (addr, readbuf, info.length);
2637 if (writebuf != nullptr)
2638 write_memory (addr, writebuf, info.length);
2642 case riscv_arg_info::location::on_stack:
2644 error (_("invalid argument location"));
2649 switch (info.argloc[0].loc_type)
2651 case riscv_arg_info::location::in_reg:
2652 return RETURN_VALUE_REGISTER_CONVENTION;
2653 case riscv_arg_info::location::by_ref:
2654 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2655 case riscv_arg_info::location::on_stack:
2657 error (_("invalid argument location"));
2661 /* Implement the frame_align gdbarch method. */
2664 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2666 return align_down (addr, 16);
2669 /* Implement the unwind_pc gdbarch method. */
2672 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2674 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2677 /* Implement the unwind_sp gdbarch method. */
2680 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2682 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2685 /* Implement the dummy_id gdbarch method. */
2687 static struct frame_id
2688 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2690 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2691 get_frame_pc (this_frame));
2694 /* Generate, or return the cached frame cache for the RiscV frame
2697 static struct riscv_unwind_cache *
2698 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2700 CORE_ADDR pc, start_addr;
2701 struct riscv_unwind_cache *cache;
2702 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2705 if ((*this_cache) != NULL)
2706 return (struct riscv_unwind_cache *) *this_cache;
2708 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2709 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2710 (*this_cache) = cache;
2712 /* Scan the prologue, filling in the cache. */
2713 start_addr = get_frame_func (this_frame);
2714 pc = get_frame_pc (this_frame);
2715 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2717 /* We can now calculate the frame base address. */
2719 = (get_frame_register_signed (this_frame, cache->frame_base_reg)
2720 + cache->frame_base_offset);
2721 if (riscv_debug_unwinder)
2722 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2723 core_addr_to_string (cache->frame_base),
2724 gdbarch_register_name (gdbarch,
2725 cache->frame_base_reg),
2726 cache->frame_base_offset);
2728 /* The prologue scanner sets the address of registers stored to the stack
2729 as the offset of that register from the frame base. The prologue
2730 scanner doesn't know the actual frame base value, and so is unable to
2731 compute the exact address. We do now know the frame base value, so
2732 update the address of registers stored to the stack. */
2733 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2734 for (regno = 0; regno < numregs; ++regno)
2736 if (trad_frame_addr_p (cache->regs, regno))
2737 cache->regs[regno].addr += cache->frame_base;
2740 /* The previous $pc can be found wherever the $ra value can be found.
2741 The previous $ra value is gone, this would have been stored be the
2742 previous frame if required. */
2743 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2744 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2746 /* Build the frame id. */
2747 cache->this_id = frame_id_build (cache->frame_base, start_addr);
2749 /* The previous $sp value is the frame base value. */
2750 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2756 /* Implement the this_id callback for RiscV frame unwinder. */
2759 riscv_frame_this_id (struct frame_info *this_frame,
2760 void **prologue_cache,
2761 struct frame_id *this_id)
2763 struct riscv_unwind_cache *cache;
2767 cache = riscv_frame_cache (this_frame, prologue_cache);
2768 *this_id = cache->this_id;
2770 CATCH (ex, RETURN_MASK_ERROR)
2772 /* Ignore errors, this leaves the frame id as the predefined outer
2773 frame id which terminates the backtrace at this point. */
2778 /* Implement the prev_register callback for RiscV frame unwinder. */
2780 static struct value *
2781 riscv_frame_prev_register (struct frame_info *this_frame,
2782 void **prologue_cache,
2785 struct riscv_unwind_cache *cache;
2787 cache = riscv_frame_cache (this_frame, prologue_cache);
2788 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
2791 /* Structure defining the RiscV normal frame unwind functions. Since we
2792 are the fallback unwinder (DWARF unwinder is used first), we use the
2793 default frame sniffer, which always accepts the frame. */
2795 static const struct frame_unwind riscv_frame_unwind =
2797 /*.type =*/ NORMAL_FRAME,
2798 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2799 /*.this_id =*/ riscv_frame_this_id,
2800 /*.prev_register =*/ riscv_frame_prev_register,
2801 /*.unwind_data =*/ NULL,
2802 /*.sniffer =*/ default_frame_sniffer,
2803 /*.dealloc_cache =*/ NULL,
2804 /*.prev_arch =*/ NULL,
2807 /* Initialize the current architecture based on INFO. If possible,
2808 re-use an architecture from ARCHES, which is a list of
2809 architectures already created during this debugging session.
2811 Called e.g. at program startup, when reading a core file, and when
2812 reading a binary file. */
2814 static struct gdbarch *
2815 riscv_gdbarch_init (struct gdbarch_info info,
2816 struct gdbarch_list *arches)
2818 struct gdbarch *gdbarch;
2819 struct gdbarch_tdep *tdep;
2820 struct gdbarch_tdep tmp_tdep;
2823 /* Ideally, we'd like to get as much information from the target for
2824 things like register size, and whether the target has floating point
2825 hardware. However, there are some things that the target can't tell
2826 us, like, what ABI is being used.
2828 So, for now, we take as much information as possible from the ELF,
2829 including things like register size, and FP hardware support, along
2830 with information about the ABI.
2832 Information about this target is built up in TMP_TDEP, and then we
2833 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2834 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2835 memset (&tmp_tdep, 0, sizeof (tmp_tdep));
2837 if (info.abfd != NULL
2838 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2840 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2841 int e_flags = elf_elfheader (info.abfd)->e_flags;
2843 if (eclass == ELFCLASS32)
2844 tmp_tdep.abi.fields.base_len = 1;
2845 else if (eclass == ELFCLASS64)
2846 tmp_tdep.abi.fields.base_len = 2;
2848 internal_error (__FILE__, __LINE__,
2849 _("unknown ELF header class %d"), eclass);
2851 if (e_flags & EF_RISCV_RVC)
2852 tmp_tdep.core_features |= (1 << ('C' - 'A'));
2854 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2856 tmp_tdep.abi.fields.float_abi = 2;
2857 tmp_tdep.core_features |= (1 << ('D' - 'A'));
2858 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2860 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2862 tmp_tdep.abi.fields.float_abi = 1;
2863 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2868 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2870 if (binfo->bits_per_word == 32)
2871 tmp_tdep.abi.fields.base_len = 1;
2872 else if (binfo->bits_per_word == 64)
2873 tmp_tdep.abi.fields.base_len = 2;
2875 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2876 binfo->bits_per_word);
2879 /* Find a candidate among the list of pre-declared architectures. */
2880 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2882 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2883 if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
2884 return arches->gdbarch;
2886 /* None found, so create a new architecture from the information provided. */
2887 tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
2888 gdbarch = gdbarch_alloc (&info, tdep);
2889 memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep));
2891 /* Target data types. */
2892 set_gdbarch_short_bit (gdbarch, 16);
2893 set_gdbarch_int_bit (gdbarch, 32);
2894 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2895 set_gdbarch_long_long_bit (gdbarch, 64);
2896 set_gdbarch_float_bit (gdbarch, 32);
2897 set_gdbarch_double_bit (gdbarch, 64);
2898 set_gdbarch_long_double_bit (gdbarch, 128);
2899 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2900 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2901 set_gdbarch_char_signed (gdbarch, 0);
2903 /* Information about the target architecture. */
2904 set_gdbarch_return_value (gdbarch, riscv_return_value);
2905 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
2906 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
2907 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
2909 /* Register architecture. */
2910 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
2911 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
2912 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
2913 set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
2914 set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
2916 /* Functions to supply register information. */
2917 set_gdbarch_register_name (gdbarch, riscv_register_name);
2918 set_gdbarch_register_type (gdbarch, riscv_register_type);
2919 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
2920 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
2922 /* Functions to analyze frames. */
2923 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
2924 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2925 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
2927 /* Functions to access frame data. */
2928 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
2929 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
2931 /* Functions handling dummy frames. */
2932 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2933 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
2934 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
2935 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
2937 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2939 dwarf2_append_unwinders (gdbarch);
2940 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
2942 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
2943 user_reg_add (gdbarch, riscv_register_aliases[i].name,
2944 value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
2946 /* Hook in OS ABI-specific overrides, if they have been registered. */
2947 gdbarch_init_osabi (info, gdbarch);
2952 /* This decodes the current instruction and determines the address of the
2953 next instruction. */
2956 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
2958 struct gdbarch *gdbarch = regcache->arch ();
2959 struct riscv_insn insn;
2962 insn.decode (gdbarch, pc);
2963 next_pc = pc + insn.length ();
2965 if (insn.opcode () == riscv_insn::JAL)
2966 next_pc = pc + insn.imm_signed ();
2967 else if (insn.opcode () == riscv_insn::JALR)
2970 regcache->cooked_read (insn.rs1 (), &source);
2971 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
2973 else if (insn.opcode () == riscv_insn::BEQ)
2976 regcache->cooked_read (insn.rs1 (), &src1);
2977 regcache->cooked_read (insn.rs2 (), &src2);
2979 next_pc = pc + insn.imm_signed ();
2981 else if (insn.opcode () == riscv_insn::BNE)
2984 regcache->cooked_read (insn.rs1 (), &src1);
2985 regcache->cooked_read (insn.rs2 (), &src2);
2987 next_pc = pc + insn.imm_signed ();
2989 else if (insn.opcode () == riscv_insn::BLT)
2992 regcache->cooked_read (insn.rs1 (), &src1);
2993 regcache->cooked_read (insn.rs2 (), &src2);
2995 next_pc = pc + insn.imm_signed ();
2997 else if (insn.opcode () == riscv_insn::BGE)
3000 regcache->cooked_read (insn.rs1 (), &src1);
3001 regcache->cooked_read (insn.rs2 (), &src2);
3003 next_pc = pc + insn.imm_signed ();
3005 else if (insn.opcode () == riscv_insn::BLTU)
3007 ULONGEST src1, src2;
3008 regcache->cooked_read (insn.rs1 (), &src1);
3009 regcache->cooked_read (insn.rs2 (), &src2);
3011 next_pc = pc + insn.imm_signed ();
3013 else if (insn.opcode () == riscv_insn::BGEU)
3015 ULONGEST src1, src2;
3016 regcache->cooked_read (insn.rs1 (), &src1);
3017 regcache->cooked_read (insn.rs2 (), &src2);
3019 next_pc = pc + insn.imm_signed ();
3025 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
3026 for the end of the sequence and put the breakpoint there. */
3029 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
3032 struct gdbarch *gdbarch = regcache->arch ();
3033 struct riscv_insn insn;
3034 CORE_ADDR cur_step_pc = pc;
3035 CORE_ADDR last_addr = 0;
3037 /* First instruction has to be a load reserved. */
3038 insn.decode (gdbarch, cur_step_pc);
3039 if (insn.opcode () != riscv_insn::LR)
3041 cur_step_pc = cur_step_pc + insn.length ();
3043 /* Next instruction should be branch to exit. */
3044 insn.decode (gdbarch, cur_step_pc);
3045 if (insn.opcode () != riscv_insn::BNE)
3047 last_addr = cur_step_pc + insn.imm_signed ();
3048 cur_step_pc = cur_step_pc + insn.length ();
3050 /* Next instruction should be store conditional. */
3051 insn.decode (gdbarch, cur_step_pc);
3052 if (insn.opcode () != riscv_insn::SC)
3054 cur_step_pc = cur_step_pc + insn.length ();
3056 /* Next instruction should be branch to start. */
3057 insn.decode (gdbarch, cur_step_pc);
3058 if (insn.opcode () != riscv_insn::BNE)
3060 if (pc != (cur_step_pc + insn.imm_signed ()))
3062 cur_step_pc = cur_step_pc + insn.length ();
3064 /* We should now be at the end of the sequence. */
3065 if (cur_step_pc != last_addr)
3068 *next_pc = cur_step_pc;
3072 /* This is called just before we want to resume the inferior, if we want to
3073 single-step it but there is no hardware or kernel single-step support. We
3074 find the target of the coming instruction and breakpoint it. */
3076 std::vector<CORE_ADDR>
3077 riscv_software_single_step (struct regcache *regcache)
3079 CORE_ADDR pc, next_pc;
3081 pc = regcache_read_pc (regcache);
3083 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
3086 next_pc = riscv_next_pc (regcache, pc);
3092 _initialize_riscv_tdep (void)
3094 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
3096 /* Add root prefix command for all "set debug riscv" and "show debug
3098 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
3099 _("RISC-V specific debug commands."),
3100 &setdebugriscvcmdlist, "set debug riscv ", 0,
3103 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
3104 _("RISC-V specific debug commands."),
3105 &showdebugriscvcmdlist, "show debug riscv ", 0,
3108 add_setshow_zuinteger_cmd ("breakpoints", class_maintenance,
3109 &riscv_debug_breakpoints, _("\
3110 Set riscv breakpoint debugging."), _("\
3111 Show riscv breakpoint debugging."), _("\
3112 When non-zero, print debugging information for the riscv specific parts\n\
3113 of the breakpoint mechanism."),
3115 show_riscv_debug_variable,
3116 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3118 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
3119 &riscv_debug_infcall, _("\
3120 Set riscv inferior call debugging."), _("\
3121 Show riscv inferior call debugging."), _("\
3122 When non-zero, print debugging information for the riscv specific parts\n\
3123 of the inferior call mechanism."),
3125 show_riscv_debug_variable,
3126 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3128 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
3129 &riscv_debug_unwinder, _("\
3130 Set riscv stack unwinding debugging."), _("\
3131 Show riscv stack unwinding debugging."), _("\
3132 When non-zero, print debugging information for the riscv specific parts\n\
3133 of the stack unwinding mechanism."),
3135 show_riscv_debug_variable,
3136 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
3138 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
3139 add_prefix_cmd ("riscv", no_class, set_riscv_command,
3140 _("RISC-V specific commands."),
3141 &setriscvcmdlist, "set riscv ", 0, &setlist);
3143 add_prefix_cmd ("riscv", no_class, show_riscv_command,
3144 _("RISC-V specific commands."),
3145 &showriscvcmdlist, "show riscv ", 0, &showlist);
3148 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
3149 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
3150 &use_compressed_breakpoints,
3152 Set debugger's use of compressed breakpoints."), _(" \
3153 Show debugger's use of compressed breakpoints."), _("\
3154 Debugging compressed code requires compressed breakpoints to be used. If\n\
3155 left to 'auto' then gdb will use them if the existing instruction is a\n\
3156 compressed instruction. If that doesn't give the correct behavior, then\n\
3157 this option can be used."),
3159 show_use_compressed_breakpoints,