1 /* Target-dependent code for the RISC-V architecture, for GDB.
3 Copyright (C) 2018 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
32 #include "arch-utils.h"
35 #include "riscv-tdep.h"
37 #include "reggroups.h"
38 #include "opcode/riscv.h"
39 #include "elf/riscv.h"
43 #include "frame-unwind.h"
44 #include "frame-base.h"
45 #include "trad-frame.h"
47 #include "floatformat.h"
49 #include "target-descriptions.h"
50 #include "dwarf2-frame.h"
51 #include "user-regs.h"
53 #include "common-defs.h"
54 #include "opcode/riscv-opc.h"
55 #include "cli/cli-decode.h"
56 #include "observable.h"
57 #include "prologue-value.h"
59 /* The stack must be 16-byte aligned. */
60 #define SP_ALIGNMENT 16
62 /* Forward declarations. */
63 static bool riscv_has_feature (struct gdbarch *gdbarch, char feature);
65 /* Define a series of is_XXX_insn functions to check if the value INSN
66 is an instance of instruction XXX. */
67 #define DECLARE_INSN(INSN_NAME, INSN_MATCH, INSN_MASK) \
68 static inline bool is_ ## INSN_NAME ## _insn (long insn) \
70 return (insn & INSN_MASK) == INSN_MATCH; \
72 #include "opcode/riscv-opc.h"
75 /* Cached information about a frame. */
77 struct riscv_unwind_cache
79 /* The register from which we can calculate the frame base. This is
80 usually $sp or $fp. */
83 /* The offset from the current value in register FRAME_BASE_REG to the
84 actual frame base address. */
85 int frame_base_offset;
87 /* Information about previous register values. */
88 struct trad_frame_saved_reg *regs;
90 /* The id for this frame. */
91 struct frame_id this_id;
93 /* The base (stack) address for this frame. This is the stack pointer
94 value on entry to this frame before any adjustments are made. */
98 /* Architectural name for core registers. */
100 static const char * const riscv_gdb_reg_names[RISCV_LAST_FP_REGNUM + 1] =
102 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
103 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
104 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
105 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
107 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
108 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
109 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
110 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
113 /* Maps "pretty" register names onto their GDB register number. */
115 struct register_alias
117 /* The register alias. Usually more descriptive than the
118 architectural name of the register. */
121 /* The GDB register number. */
125 /* Table of register aliases. */
127 static const struct register_alias riscv_register_aliases[] =
195 #define DECLARE_CSR(name, num) { #name, (num) + 65 },
196 #include "opcode/riscv-opc.h"
200 /* Controls whether we place compressed breakpoints or not. When in auto
201 mode GDB tries to determine if the target supports compressed
202 breakpoints, and uses them if it does. */
204 static enum auto_boolean use_compressed_breakpoints;
206 /* The show callback for 'show riscv use-compressed-breakpoints'. */
209 show_use_compressed_breakpoints (struct ui_file *file, int from_tty,
210 struct cmd_list_element *c,
213 const char *additional_info;
214 struct gdbarch *gdbarch = target_gdbarch ();
216 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
217 if (riscv_has_feature (gdbarch, 'C'))
218 additional_info = _(" (currently on)");
220 additional_info = _(" (currently off)");
222 additional_info = "";
224 fprintf_filtered (file,
225 _("Debugger's use of compressed breakpoints is set "
226 "to %s%s.\n"), value, additional_info);
229 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
231 static struct cmd_list_element *setriscvcmdlist = NULL;
232 static struct cmd_list_element *showriscvcmdlist = NULL;
234 /* The show callback for the 'show riscv' prefix command. */
237 show_riscv_command (const char *args, int from_tty)
239 help_list (showriscvcmdlist, "show riscv ", all_commands, gdb_stdout);
242 /* The set callback for the 'set riscv' prefix command. */
245 set_riscv_command (const char *args, int from_tty)
248 (_("\"set riscv\" must be followed by an appropriate subcommand.\n"));
249 help_list (setriscvcmdlist, "set riscv ", all_commands, gdb_stdout);
252 /* The set and show lists for 'set riscv' and 'show riscv' prefixes. */
254 static struct cmd_list_element *setdebugriscvcmdlist = NULL;
255 static struct cmd_list_element *showdebugriscvcmdlist = NULL;
257 /* The show callback for the 'show debug riscv' prefix command. */
260 show_debug_riscv_command (const char *args, int from_tty)
262 help_list (showdebugriscvcmdlist, "show debug riscv ", all_commands, gdb_stdout);
265 /* The set callback for the 'set debug riscv' prefix command. */
268 set_debug_riscv_command (const char *args, int from_tty)
271 (_("\"set debug riscv\" must be followed by an appropriate subcommand.\n"));
272 help_list (setdebugriscvcmdlist, "set debug riscv ", all_commands, gdb_stdout);
275 /* The show callback for all 'show debug riscv VARNAME' variables. */
278 show_riscv_debug_variable (struct ui_file *file, int from_tty,
279 struct cmd_list_element *c,
282 fprintf_filtered (file,
283 _("RiscV debug variable `%s' is set to: %s\n"),
287 /* When this is set to non-zero debugging information about inferior calls
290 static unsigned int riscv_debug_infcall = 0;
292 /* When this is set to non-zero debugging information about stack unwinding
295 static unsigned int riscv_debug_unwinder = 0;
297 /* Read the MISA register from the target. The register will only be read
298 once, and the value read will be cached. If the register can't be read
299 from the target then a default value (0) will be returned. If the
300 pointer READ_P is not null, then the bool pointed to is updated to
301 indicate if the value returned was read from the target (true) or is the
305 riscv_read_misa_reg (bool *read_p)
309 if (target_has_registers)
311 struct frame_info *frame = get_current_frame ();
315 value = get_frame_register_unsigned (frame,
316 RISCV_CSR_MISA_REGNUM);
318 CATCH (ex, RETURN_MASK_ERROR)
320 /* Old cores might have MISA located at a different offset. */
321 value = get_frame_register_unsigned (frame,
322 RISCV_CSR_LEGACY_MISA_REGNUM);
330 /* Return true if FEATURE is available for the architecture GDBARCH. The
331 FEATURE should be one of the single character feature codes described in
332 the RiscV ISA manual, these are between 'A' and 'Z'. */
335 riscv_has_feature (struct gdbarch *gdbarch, char feature)
337 bool have_read_misa = false;
340 gdb_assert (feature >= 'A' && feature <= 'Z');
342 misa = riscv_read_misa_reg (&have_read_misa);
343 if (!have_read_misa || misa == 0)
344 misa = gdbarch_tdep (gdbarch)->core_features;
346 return (misa & (1 << (feature - 'A'))) != 0;
349 /* Return the width in bytes of the general purpose registers for GDBARCH.
350 Possible return values are 4, 8, or 16 for RiscV variants RV32, RV64, or
354 riscv_isa_xlen (struct gdbarch *gdbarch)
356 switch (gdbarch_tdep (gdbarch)->abi.fields.base_len)
359 warning (_("unknown xlen size, assuming 4 bytes"));
370 /* Return the width in bytes of the floating point registers for GDBARCH.
371 If this architecture has no floating point registers, then return 0.
372 Possible values are 4, 8, or 16 for depending on which of single, double
373 or quad floating point support is available. */
376 riscv_isa_flen (struct gdbarch *gdbarch)
378 if (riscv_has_feature (gdbarch, 'Q'))
380 else if (riscv_has_feature (gdbarch, 'D'))
382 else if (riscv_has_feature (gdbarch, 'F'))
388 /* Return true if the target for GDBARCH has floating point hardware. */
391 riscv_has_fp_regs (struct gdbarch *gdbarch)
393 return (riscv_isa_flen (gdbarch) > 0);
396 /* Return true if GDBARCH is using any of the floating point hardware ABIs. */
399 riscv_has_fp_abi (struct gdbarch *gdbarch)
401 return (gdbarch_tdep (gdbarch)->abi.fields.float_abi != 0);
404 /* Return true if REGNO is a floating pointer register. */
407 riscv_is_fp_regno_p (int regno)
409 return (regno >= RISCV_FIRST_FP_REGNUM
410 && regno <= RISCV_LAST_FP_REGNUM);
413 /* Implement the breakpoint_kind_from_pc gdbarch method. */
416 riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
418 if (use_compressed_breakpoints == AUTO_BOOLEAN_AUTO)
420 if (riscv_has_feature (gdbarch, 'C'))
425 else if (use_compressed_breakpoints == AUTO_BOOLEAN_TRUE)
431 /* Implement the sw_breakpoint_from_kind gdbarch method. */
433 static const gdb_byte *
434 riscv_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
436 static const gdb_byte ebreak[] = { 0x73, 0x00, 0x10, 0x00, };
437 static const gdb_byte c_ebreak[] = { 0x02, 0x90 };
447 gdb_assert_not_reached (_("unhandled breakpoint kind"));
451 /* Callback function for user_reg_add. */
453 static struct value *
454 value_of_riscv_user_reg (struct frame_info *frame, const void *baton)
456 const int *reg_p = (const int *) baton;
457 return value_of_register (*reg_p, frame);
460 /* Implement the register_name gdbarch method. */
463 riscv_register_name (struct gdbarch *gdbarch, int regnum)
465 /* Prefer to use the alias. */
466 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_REGNUM)
470 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
471 if (regnum == riscv_register_aliases[i].regnum)
472 return riscv_register_aliases[i].name;
475 if (regnum >= RISCV_ZERO_REGNUM && regnum <= RISCV_LAST_FP_REGNUM)
476 return riscv_gdb_reg_names[regnum];
478 if (regnum >= RISCV_FIRST_CSR_REGNUM && regnum <= RISCV_LAST_CSR_REGNUM)
482 xsnprintf (buf, sizeof (buf), "csr%d",
483 regnum - RISCV_FIRST_CSR_REGNUM);
487 if (regnum == RISCV_PRIV_REGNUM)
493 /* Implement the register_type gdbarch method. */
496 riscv_register_type (struct gdbarch *gdbarch, int regnum)
500 if (regnum < RISCV_FIRST_FP_REGNUM)
502 if (regnum == gdbarch_pc_regnum (gdbarch)
503 || regnum == RISCV_RA_REGNUM)
504 return builtin_type (gdbarch)->builtin_func_ptr;
506 if (regnum == RISCV_FP_REGNUM
507 || regnum == RISCV_SP_REGNUM
508 || regnum == RISCV_GP_REGNUM
509 || regnum == RISCV_TP_REGNUM)
510 return builtin_type (gdbarch)->builtin_data_ptr;
512 /* Remaining GPRs vary in size based on the current ISA. */
513 regsize = riscv_isa_xlen (gdbarch);
517 return builtin_type (gdbarch)->builtin_uint32;
519 return builtin_type (gdbarch)->builtin_uint64;
521 return builtin_type (gdbarch)->builtin_uint128;
523 internal_error (__FILE__, __LINE__,
524 _("unknown isa regsize %i"), regsize);
527 else if (regnum <= RISCV_LAST_FP_REGNUM)
529 regsize = riscv_isa_xlen (gdbarch);
533 return builtin_type (gdbarch)->builtin_float;
535 return builtin_type (gdbarch)->builtin_double;
537 return builtin_type (gdbarch)->builtin_long_double;
539 internal_error (__FILE__, __LINE__,
540 _("unknown isa regsize %i"), regsize);
543 else if (regnum == RISCV_PRIV_REGNUM)
544 return builtin_type (gdbarch)->builtin_int8;
547 if (regnum == RISCV_CSR_FFLAGS_REGNUM
548 || regnum == RISCV_CSR_FRM_REGNUM
549 || regnum == RISCV_CSR_FCSR_REGNUM)
550 return builtin_type (gdbarch)->builtin_int32;
552 regsize = riscv_isa_xlen (gdbarch);
556 return builtin_type (gdbarch)->builtin_int32;
558 return builtin_type (gdbarch)->builtin_int64;
560 return builtin_type (gdbarch)->builtin_int128;
562 internal_error (__FILE__, __LINE__,
563 _("unknown isa regsize %i"), regsize);
568 /* Helper for riscv_print_registers_info, prints info for a single register
572 riscv_print_one_register_info (struct gdbarch *gdbarch,
573 struct ui_file *file,
574 struct frame_info *frame,
577 const char *name = gdbarch_register_name (gdbarch, regnum);
578 struct value *val = value_of_register (regnum, frame);
579 struct type *regtype = value_type (val);
580 int print_raw_format;
581 enum tab_stops { value_column_1 = 15 };
583 fputs_filtered (name, file);
584 print_spaces_filtered (value_column_1 - strlen (name), file);
586 print_raw_format = (value_entirely_available (val)
587 && !value_optimized_out (val));
589 if (TYPE_CODE (regtype) == TYPE_CODE_FLT)
591 struct value_print_options opts;
592 const gdb_byte *valaddr = value_contents_for_printing (val);
593 enum bfd_endian byte_order = gdbarch_byte_order (get_type_arch (regtype));
595 get_user_print_options (&opts);
599 value_embedded_offset (val), 0,
600 file, 0, val, &opts, current_language);
602 if (print_raw_format)
604 fprintf_filtered (file, "\t(raw ");
605 print_hex_chars (file, valaddr, TYPE_LENGTH (regtype), byte_order,
607 fprintf_filtered (file, ")");
612 struct value_print_options opts;
614 /* Print the register in hex. */
615 get_formatted_print_options (&opts, 'x');
618 value_embedded_offset (val), 0,
619 file, 0, val, &opts, current_language);
621 if (print_raw_format)
623 if (regnum == RISCV_CSR_MSTATUS_REGNUM)
626 int size = register_size (gdbarch, regnum);
629 d = value_as_long (val);
631 fprintf_filtered (file,
632 "\tSD:%X VM:%02X MXR:%X PUM:%X MPRV:%X XS:%X "
633 "FS:%X MPP:%x HPP:%X SPP:%X MPIE:%X HPIE:%X "
634 "SPIE:%X UPIE:%X MIE:%X HIE:%X SIE:%X UIE:%X",
635 (int) ((d >> (xlen - 1)) & 0x1),
636 (int) ((d >> 24) & 0x1f),
637 (int) ((d >> 19) & 0x1),
638 (int) ((d >> 18) & 0x1),
639 (int) ((d >> 17) & 0x1),
640 (int) ((d >> 15) & 0x3),
641 (int) ((d >> 13) & 0x3),
642 (int) ((d >> 11) & 0x3),
643 (int) ((d >> 9) & 0x3),
644 (int) ((d >> 8) & 0x1),
645 (int) ((d >> 7) & 0x1),
646 (int) ((d >> 6) & 0x1),
647 (int) ((d >> 5) & 0x1),
648 (int) ((d >> 4) & 0x1),
649 (int) ((d >> 3) & 0x1),
650 (int) ((d >> 2) & 0x1),
651 (int) ((d >> 1) & 0x1),
652 (int) ((d >> 0) & 0x1));
654 else if (regnum == RISCV_CSR_MISA_REGNUM)
660 d = value_as_long (val);
664 for (; base > 0; base--)
666 fprintf_filtered (file, "\tRV%d", xlen);
668 for (i = 0; i < 26; i++)
671 fprintf_filtered (file, "%c", 'A' + i);
674 else if (regnum == RISCV_CSR_FCSR_REGNUM
675 || regnum == RISCV_CSR_FFLAGS_REGNUM
676 || regnum == RISCV_CSR_FRM_REGNUM)
680 d = value_as_long (val);
682 fprintf_filtered (file, "\t");
683 if (regnum != RISCV_CSR_FRM_REGNUM)
684 fprintf_filtered (file,
685 "RD:%01X NV:%d DZ:%d OF:%d UF:%d NX:%d",
686 (int) ((d >> 5) & 0x7),
687 (int) ((d >> 4) & 0x1),
688 (int) ((d >> 3) & 0x1),
689 (int) ((d >> 2) & 0x1),
690 (int) ((d >> 1) & 0x1),
691 (int) ((d >> 0) & 0x1));
693 if (regnum != RISCV_CSR_FFLAGS_REGNUM)
695 static const char * const sfrm[] =
697 "RNE (round to nearest; ties to even)",
698 "RTZ (Round towards zero)",
699 "RDN (Round down towards -INF)",
700 "RUP (Round up towards +INF)",
701 "RMM (Round to nearest; ties to max magnitude)",
704 "dynamic rounding mode",
706 int frm = ((regnum == RISCV_CSR_FCSR_REGNUM)
707 ? (d >> 5) : d) & 0x3;
709 fprintf_filtered (file, "%sFRM:%i [%s]",
710 (regnum == RISCV_CSR_FCSR_REGNUM
715 else if (regnum == RISCV_PRIV_REGNUM)
720 d = value_as_long (val);
725 static const char * const sprv[] =
732 fprintf_filtered (file, "\tprv:%d [%s]",
736 fprintf_filtered (file, "\tprv:%d [INVALID]", priv);
740 /* If not a vector register, print it also according to its
742 if (TYPE_VECTOR (regtype) == 0)
744 get_user_print_options (&opts);
746 fprintf_filtered (file, "\t");
748 value_embedded_offset (val), 0,
749 file, 0, val, &opts, current_language);
754 fprintf_filtered (file, "\n");
757 /* Implement the register_reggroup_p gdbarch method. Is REGNUM a member
761 riscv_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
762 struct reggroup *reggroup)
766 /* Used by 'info registers' and 'info registers <groupname>'. */
768 if (gdbarch_register_name (gdbarch, regnum) == NULL
769 || gdbarch_register_name (gdbarch, regnum)[0] == '\0')
772 if (reggroup == all_reggroup)
774 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum == RISCV_PRIV_REGNUM)
776 /* Only include CSRs that have aliases. */
777 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
779 if (regnum == riscv_register_aliases[i].regnum)
784 else if (reggroup == float_reggroup)
785 return (riscv_is_fp_regno_p (regnum)
786 || regnum == RISCV_CSR_FCSR_REGNUM
787 || regnum == RISCV_CSR_FFLAGS_REGNUM
788 || regnum == RISCV_CSR_FRM_REGNUM);
789 else if (reggroup == general_reggroup)
790 return regnum < RISCV_FIRST_FP_REGNUM;
791 else if (reggroup == restore_reggroup || reggroup == save_reggroup)
793 if (riscv_has_fp_regs (gdbarch))
794 return regnum <= RISCV_LAST_FP_REGNUM;
796 return regnum < RISCV_FIRST_FP_REGNUM;
798 else if (reggroup == system_reggroup)
800 if (regnum == RISCV_PRIV_REGNUM)
802 if (regnum < RISCV_FIRST_CSR_REGNUM || regnum > RISCV_LAST_CSR_REGNUM)
804 /* Only include CSRs that have aliases. */
805 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
807 if (regnum == riscv_register_aliases[i].regnum)
812 else if (reggroup == vector_reggroup)
818 /* Implement the print_registers_info gdbarch method. This is used by
819 'info registers' and 'info all-registers'. */
822 riscv_print_registers_info (struct gdbarch *gdbarch,
823 struct ui_file *file,
824 struct frame_info *frame,
825 int regnum, int print_all)
829 /* Print one specified register. */
830 gdb_assert (regnum <= RISCV_LAST_REGNUM);
831 if (gdbarch_register_name (gdbarch, regnum) == NULL
832 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
833 error (_("Not a valid register for the current processor type"));
834 riscv_print_one_register_info (gdbarch, file, frame, regnum);
838 struct reggroup *reggroup;
841 reggroup = all_reggroup;
843 reggroup = general_reggroup;
845 for (regnum = 0; regnum <= RISCV_LAST_REGNUM; ++regnum)
847 /* Zero never changes, so might as well hide by default. */
848 if (regnum == RISCV_ZERO_REGNUM && !print_all)
851 /* Registers with no name are not valid on this ISA. */
852 if (gdbarch_register_name (gdbarch, regnum) == NULL
853 || *(gdbarch_register_name (gdbarch, regnum)) == '\0')
856 /* Is the register in the group we're interested in? */
857 if (!riscv_register_reggroup_p (gdbarch, regnum, reggroup))
860 riscv_print_one_register_info (gdbarch, file, frame, regnum);
865 /* Class that handles one decoded RiscV instruction. */
871 /* Enum of all the opcodes that GDB cares about during the prologue scan. */
874 /* Unknown value is used at initialisation time. */
877 /* These instructions are all the ones we are interested in during the
887 /* These are needed for software breakopint support. */
896 /* These are needed for stepping over atomic sequences. */
900 /* Other instructions are not interesting during the prologue scan, and
915 void decode (struct gdbarch *gdbarch, CORE_ADDR pc);
917 /* Get the length of the instruction in bytes. */
921 /* Get the opcode for this instruction. */
922 enum opcode opcode () const
925 /* Get destination register field for this instruction. This is only
926 valid if the OPCODE implies there is such a field for this
931 /* Get the RS1 register field for this instruction. This is only valid
932 if the OPCODE implies there is such a field for this instruction. */
936 /* Get the RS2 register field for this instruction. This is only valid
937 if the OPCODE implies there is such a field for this instruction. */
941 /* Get the immediate for this instruction in signed form. This is only
942 valid if the OPCODE implies there is such a field for this
944 int imm_signed () const
949 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
950 int decode_register_index (unsigned long opcode, int offset)
952 return (opcode >> offset) & 0x1F;
955 /* Extract 5 bit register field at OFFSET from instruction OPCODE. */
956 int decode_register_index_short (unsigned long opcode, int offset)
958 return ((opcode >> offset) & 0x7) + 8;
961 /* Helper for DECODE, decode 32-bit R-type instruction. */
962 void decode_r_type_insn (enum opcode opcode, ULONGEST ival)
965 m_rd = decode_register_index (ival, OP_SH_RD);
966 m_rs1 = decode_register_index (ival, OP_SH_RS1);
967 m_rs2 = decode_register_index (ival, OP_SH_RS2);
970 /* Helper for DECODE, decode 16-bit compressed R-type instruction. */
971 void decode_cr_type_insn (enum opcode opcode, ULONGEST ival)
974 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
975 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
978 /* Helper for DECODE, decode 32-bit I-type instruction. */
979 void decode_i_type_insn (enum opcode opcode, ULONGEST ival)
982 m_rd = decode_register_index (ival, OP_SH_RD);
983 m_rs1 = decode_register_index (ival, OP_SH_RS1);
984 m_imm.s = EXTRACT_ITYPE_IMM (ival);
987 /* Helper for DECODE, decode 16-bit compressed I-type instruction. */
988 void decode_ci_type_insn (enum opcode opcode, ULONGEST ival)
991 m_rd = m_rs1 = decode_register_index (ival, OP_SH_CRS1S);
992 m_imm.s = EXTRACT_RVC_IMM (ival);
995 /* Helper for DECODE, decode 32-bit S-type instruction. */
996 void decode_s_type_insn (enum opcode opcode, ULONGEST ival)
999 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1000 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1001 m_imm.s = EXTRACT_STYPE_IMM (ival);
1004 /* Helper for DECODE, decode 16-bit CS-type instruction. The immediate
1005 encoding is different for each CS format instruction, so extracting
1006 the immediate is left up to the caller, who should pass the extracted
1007 immediate value through in IMM. */
1008 void decode_cs_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1012 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1013 m_rs2 = decode_register_index_short (ival, OP_SH_CRS2S);
1016 /* Helper for DECODE, decode 16-bit CSS-type instruction. The immediate
1017 encoding is different for each CSS format instruction, so extracting
1018 the immediate is left up to the caller, who should pass the extracted
1019 immediate value through in IMM. */
1020 void decode_css_type_insn (enum opcode opcode, ULONGEST ival, int imm)
1024 m_rs1 = RISCV_SP_REGNUM;
1025 /* Not a compressed register number in this case. */
1026 m_rs2 = decode_register_index (ival, OP_SH_CRS2);
1029 /* Helper for DECODE, decode 32-bit U-type instruction. */
1030 void decode_u_type_insn (enum opcode opcode, ULONGEST ival)
1033 m_rd = decode_register_index (ival, OP_SH_RD);
1034 m_imm.s = EXTRACT_UTYPE_IMM (ival);
1037 /* Helper for DECODE, decode 32-bit J-type instruction. */
1038 void decode_j_type_insn (enum opcode opcode, ULONGEST ival)
1041 m_rd = decode_register_index (ival, OP_SH_RD);
1042 m_imm.s = EXTRACT_UJTYPE_IMM (ival);
1045 /* Helper for DECODE, decode 32-bit J-type instruction. */
1046 void decode_cj_type_insn (enum opcode opcode, ULONGEST ival)
1049 m_imm.s = EXTRACT_RVC_J_IMM (ival);
1052 void decode_b_type_insn (enum opcode opcode, ULONGEST ival)
1055 m_rs1 = decode_register_index (ival, OP_SH_RS1);
1056 m_rs2 = decode_register_index (ival, OP_SH_RS2);
1057 m_imm.s = EXTRACT_SBTYPE_IMM (ival);
1060 void decode_cb_type_insn (enum opcode opcode, ULONGEST ival)
1063 m_rs1 = decode_register_index_short (ival, OP_SH_CRS1S);
1064 m_imm.s = EXTRACT_RVC_B_IMM (ival);
1067 /* Fetch instruction from target memory at ADDR, return the content of
1068 the instruction, and update LEN with the instruction length. */
1069 static ULONGEST fetch_instruction (struct gdbarch *gdbarch,
1070 CORE_ADDR addr, int *len);
1072 /* The length of the instruction in bytes. Should be 2 or 4. */
1075 /* The instruction opcode. */
1076 enum opcode m_opcode;
1078 /* The three possible registers an instruction might reference. Not
1079 every instruction fills in all of these registers. Which fields are
1080 valid depends on the opcode. The naming of these fields matches the
1081 naming in the riscv isa manual. */
1086 /* Possible instruction immediate. This is only valid if the instruction
1087 format contains an immediate, not all instruction, whether this is
1088 valid depends on the opcode. Despite only having one format for now
1089 the immediate is packed into a union, later instructions might require
1090 an unsigned formatted immediate, having the union in place now will
1091 reduce the need for code churn later. */
1092 union riscv_insn_immediate
1094 riscv_insn_immediate ()
1104 /* Fetch instruction from target memory at ADDR, return the content of the
1105 instruction, and update LEN with the instruction length. */
1108 riscv_insn::fetch_instruction (struct gdbarch *gdbarch,
1109 CORE_ADDR addr, int *len)
1111 enum bfd_endian byte_order = gdbarch_byte_order_for_code (gdbarch);
1113 int instlen, status;
1115 /* All insns are at least 16 bits. */
1116 status = target_read_memory (addr, buf, 2);
1118 memory_error (TARGET_XFER_E_IO, addr);
1120 /* If we need more, grab it now. */
1121 instlen = riscv_insn_length (buf[0]);
1122 gdb_assert (instlen <= sizeof (buf));
1127 status = target_read_memory (addr + 2, buf + 2, instlen - 2);
1129 memory_error (TARGET_XFER_E_IO, addr + 2);
1132 return extract_unsigned_integer (buf, instlen, byte_order);
1135 /* Fetch from target memory an instruction at PC and decode it. */
1138 riscv_insn::decode (struct gdbarch *gdbarch, CORE_ADDR pc)
1142 /* Fetch the instruction, and the instructions length. */
1143 ival = fetch_instruction (gdbarch, pc, &m_length);
1147 if (is_add_insn (ival))
1148 decode_r_type_insn (ADD, ival);
1149 else if (is_addw_insn (ival))
1150 decode_r_type_insn (ADDW, ival);
1151 else if (is_addi_insn (ival))
1152 decode_i_type_insn (ADDI, ival);
1153 else if (is_addiw_insn (ival))
1154 decode_i_type_insn (ADDIW, ival);
1155 else if (is_auipc_insn (ival))
1156 decode_u_type_insn (AUIPC, ival);
1157 else if (is_lui_insn (ival))
1158 decode_u_type_insn (LUI, ival);
1159 else if (is_sd_insn (ival))
1160 decode_s_type_insn (SD, ival);
1161 else if (is_sw_insn (ival))
1162 decode_s_type_insn (SW, ival);
1163 else if (is_jal_insn (ival))
1164 decode_j_type_insn (JAL, ival);
1165 else if (is_jalr_insn (ival))
1166 decode_i_type_insn (JALR, ival);
1167 else if (is_beq_insn (ival))
1168 decode_b_type_insn (BEQ, ival);
1169 else if (is_bne_insn (ival))
1170 decode_b_type_insn (BNE, ival);
1171 else if (is_blt_insn (ival))
1172 decode_b_type_insn (BLT, ival);
1173 else if (is_bge_insn (ival))
1174 decode_b_type_insn (BGE, ival);
1175 else if (is_bltu_insn (ival))
1176 decode_b_type_insn (BLTU, ival);
1177 else if (is_bgeu_insn (ival))
1178 decode_b_type_insn (BGEU, ival);
1179 else if (is_lr_w_insn (ival))
1180 decode_r_type_insn (LR, ival);
1181 else if (is_lr_d_insn (ival))
1182 decode_r_type_insn (LR, ival);
1183 else if (is_sc_w_insn (ival))
1184 decode_r_type_insn (SC, ival);
1185 else if (is_sc_d_insn (ival))
1186 decode_r_type_insn (SC, ival);
1188 /* None of the other fields are valid in this case. */
1191 else if (m_length == 2)
1193 int xlen = riscv_isa_xlen (gdbarch);
1195 /* C_ADD and C_JALR have the same opcode. If RS2 is 0, then this is a
1196 C_JALR. So must try to match C_JALR first as it has more bits in
1198 if (is_c_jalr_insn (ival))
1199 decode_cr_type_insn (JALR, ival);
1200 else if (is_c_add_insn (ival))
1201 decode_cr_type_insn (ADD, ival);
1202 /* C_ADDW is RV64 and RV128 only. */
1203 else if (xlen != 4 && is_c_addw_insn (ival))
1204 decode_cr_type_insn (ADDW, ival);
1205 else if (is_c_addi_insn (ival))
1206 decode_ci_type_insn (ADDI, ival);
1207 /* C_ADDIW and C_JAL have the same opcode. C_ADDIW is RV64 and RV128
1208 only and C_JAL is RV32 only. */
1209 else if (xlen != 4 && is_c_addiw_insn (ival))
1210 decode_ci_type_insn (ADDIW, ival);
1211 else if (xlen == 4 && is_c_jal_insn (ival))
1212 decode_cj_type_insn (JAL, ival);
1213 /* C_ADDI16SP and C_LUI have the same opcode. If RD is 2, then this is a
1214 C_ADDI16SP. So must try to match C_ADDI16SP first as it has more bits
1216 else if (is_c_addi16sp_insn (ival))
1219 m_rd = m_rs1 = decode_register_index (ival, OP_SH_RD);
1220 m_imm.s = EXTRACT_RVC_ADDI16SP_IMM (ival);
1222 else if (is_c_addi4spn_insn (ival))
1225 m_rd = decode_register_index_short (ival, OP_SH_CRS2S);
1226 m_rs1 = RISCV_SP_REGNUM;
1227 m_imm.s = EXTRACT_RVC_ADDI4SPN_IMM (ival);
1229 else if (is_c_lui_insn (ival))
1232 m_rd = decode_register_index (ival, OP_SH_CRS1S);
1233 m_imm.s = EXTRACT_RVC_LUI_IMM (ival);
1235 /* C_SD and C_FSW have the same opcode. C_SD is RV64 and RV128 only,
1236 and C_FSW is RV32 only. */
1237 else if (xlen != 4 && is_c_sd_insn (ival))
1238 decode_cs_type_insn (SD, ival, EXTRACT_RVC_LD_IMM (ival));
1239 else if (is_c_sw_insn (ival))
1240 decode_cs_type_insn (SW, ival, EXTRACT_RVC_LW_IMM (ival));
1241 else if (is_c_swsp_insn (ival))
1242 decode_css_type_insn (SW, ival, EXTRACT_RVC_SWSP_IMM (ival));
1243 else if (xlen != 4 && is_c_sdsp_insn (ival))
1244 decode_css_type_insn (SW, ival, EXTRACT_RVC_SDSP_IMM (ival));
1245 /* C_JR and C_MV have the same opcode. If RS2 is 0, then this is a C_JR.
1246 So must try to match C_JR first as it ahs more bits in mask. */
1247 else if (is_c_jr_insn (ival))
1248 decode_cr_type_insn (JALR, ival);
1249 else if (is_c_j_insn (ival))
1250 decode_cj_type_insn (JAL, ival);
1251 else if (is_c_beqz_insn (ival))
1252 decode_cb_type_insn (BEQ, ival);
1253 else if (is_c_bnez_insn (ival))
1254 decode_cb_type_insn (BNE, ival);
1256 /* None of the other fields of INSN are valid in this case. */
1260 internal_error (__FILE__, __LINE__,
1261 _("unable to decode %d byte instructions in "
1262 "prologue at %s"), m_length,
1263 core_addr_to_string (pc));
1266 /* The prologue scanner. This is currently only used for skipping the
1267 prologue of a function when the DWARF information is not sufficient.
1268 However, it is written with filling of the frame cache in mind, which
1269 is why different groups of stack setup instructions are split apart
1270 during the core of the inner loop. In the future, the intention is to
1271 extend this function to fully support building up a frame cache that
1272 can unwind register values when there is no DWARF information. */
1275 riscv_scan_prologue (struct gdbarch *gdbarch,
1276 CORE_ADDR start_pc, CORE_ADDR end_pc,
1277 struct riscv_unwind_cache *cache)
1279 CORE_ADDR cur_pc, next_pc, after_prologue_pc;
1280 CORE_ADDR end_prologue_addr = 0;
1282 /* Find an upper limit on the function prologue using the debug
1283 information. If the debug information could not be used to provide
1284 that bound, then use an arbitrary large number as the upper bound. */
1285 after_prologue_pc = skip_prologue_using_sal (gdbarch, start_pc);
1286 if (after_prologue_pc == 0)
1287 after_prologue_pc = start_pc + 100; /* Arbitrary large number. */
1288 if (after_prologue_pc < end_pc)
1289 end_pc = after_prologue_pc;
1291 pv_t regs[RISCV_NUM_INTEGER_REGS]; /* Number of GPR. */
1292 for (int regno = 0; regno < RISCV_NUM_INTEGER_REGS; regno++)
1293 regs[regno] = pv_register (regno, 0);
1294 pv_area stack (RISCV_SP_REGNUM, gdbarch_addr_bit (gdbarch));
1296 if (riscv_debug_unwinder)
1299 "Prologue scan for function starting at %s (limit %s)\n",
1300 core_addr_to_string (start_pc),
1301 core_addr_to_string (end_pc));
1303 for (next_pc = cur_pc = start_pc; cur_pc < end_pc; cur_pc = next_pc)
1305 struct riscv_insn insn;
1307 /* Decode the current instruction, and decide where the next
1308 instruction lives based on the size of this instruction. */
1309 insn.decode (gdbarch, cur_pc);
1310 gdb_assert (insn.length () > 0);
1311 next_pc = cur_pc + insn.length ();
1313 /* Look for common stack adjustment insns. */
1314 if ((insn.opcode () == riscv_insn::ADDI
1315 || insn.opcode () == riscv_insn::ADDIW)
1316 && insn.rd () == RISCV_SP_REGNUM
1317 && insn.rs1 () == RISCV_SP_REGNUM)
1319 /* Handle: addi sp, sp, -i
1320 or: addiw sp, sp, -i */
1321 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1322 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1324 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1326 else if ((insn.opcode () == riscv_insn::SW
1327 || insn.opcode () == riscv_insn::SD)
1328 && (insn.rs1 () == RISCV_SP_REGNUM
1329 || insn.rs1 () == RISCV_FP_REGNUM))
1331 /* Handle: sw reg, offset(sp)
1332 or: sd reg, offset(sp)
1333 or: sw reg, offset(s0)
1334 or: sd reg, offset(s0) */
1335 /* Instruction storing a register onto the stack. */
1336 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1337 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1338 stack.store (pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ()),
1339 (insn.opcode () == riscv_insn::SW ? 4 : 8),
1342 else if (insn.opcode () == riscv_insn::ADDI
1343 && insn.rd () == RISCV_FP_REGNUM
1344 && insn.rs1 () == RISCV_SP_REGNUM)
1346 /* Handle: addi s0, sp, size */
1347 /* Instructions setting up the frame pointer. */
1348 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1349 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1351 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1353 else if ((insn.opcode () == riscv_insn::ADD
1354 || insn.opcode () == riscv_insn::ADDW)
1355 && insn.rd () == RISCV_FP_REGNUM
1356 && insn.rs1 () == RISCV_SP_REGNUM
1357 && insn.rs2 () == RISCV_ZERO_REGNUM)
1359 /* Handle: add s0, sp, 0
1360 or: addw s0, sp, 0 */
1361 /* Instructions setting up the frame pointer. */
1362 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1363 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1364 regs[insn.rd ()] = pv_add_constant (regs[insn.rs1 ()], 0);
1366 else if ((insn.opcode () == riscv_insn::ADDI
1367 && insn.rd () == RISCV_ZERO_REGNUM
1368 && insn.rs1 () == RISCV_ZERO_REGNUM
1369 && insn.imm_signed () == 0))
1371 /* Handle: add x0, x0, 0 (NOP) */
1373 else if (insn.opcode () == riscv_insn::AUIPC)
1375 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1376 regs[insn.rd ()] = pv_constant (cur_pc + insn.imm_signed ());
1378 else if (insn.opcode () == riscv_insn::LUI)
1380 /* Handle: lui REG, n
1381 Where REG is not gp register. */
1382 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1383 regs[insn.rd ()] = pv_constant (insn.imm_signed ());
1385 else if (insn.opcode () == riscv_insn::ADDI)
1387 /* Handle: addi REG1, REG2, IMM */
1388 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1389 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1391 = pv_add_constant (regs[insn.rs1 ()], insn.imm_signed ());
1393 else if (insn.opcode () == riscv_insn::ADD)
1395 /* Handle: addi REG1, REG2, IMM */
1396 gdb_assert (insn.rd () < RISCV_NUM_INTEGER_REGS);
1397 gdb_assert (insn.rs1 () < RISCV_NUM_INTEGER_REGS);
1398 gdb_assert (insn.rs2 () < RISCV_NUM_INTEGER_REGS);
1399 regs[insn.rd ()] = pv_add (regs[insn.rs1 ()], regs[insn.rs2 ()]);
1403 end_prologue_addr = cur_pc;
1408 if (end_prologue_addr == 0)
1409 end_prologue_addr = cur_pc;
1411 if (riscv_debug_unwinder)
1412 fprintf_unfiltered (gdb_stdlog, "End of prologue at %s\n",
1413 core_addr_to_string (end_prologue_addr));
1417 /* Figure out if it is a frame pointer or just a stack pointer. Also
1418 the offset held in the pv_t is from the original register value to
1419 the current value, which for a grows down stack means a negative
1420 value. The FRAME_BASE_OFFSET is the negation of this, how to get
1421 from the current value to the original value. */
1422 if (pv_is_register (regs[RISCV_FP_REGNUM], RISCV_SP_REGNUM))
1424 cache->frame_base_reg = RISCV_FP_REGNUM;
1425 cache->frame_base_offset = -regs[RISCV_FP_REGNUM].k;
1429 cache->frame_base_reg = RISCV_SP_REGNUM;
1430 cache->frame_base_offset = -regs[RISCV_SP_REGNUM].k;
1433 /* Assign offset from old SP to all saved registers. As we don't
1434 have the previous value for the frame base register at this
1435 point, we store the offset as the address in the trad_frame, and
1436 then convert this to an actual address later. */
1437 for (int i = 0; i <= RISCV_NUM_INTEGER_REGS; i++)
1440 if (stack.find_reg (gdbarch, i, &offset))
1442 if (riscv_debug_unwinder)
1443 fprintf_unfiltered (gdb_stdlog,
1444 "Register $%s at stack offset %ld\n",
1445 gdbarch_register_name (gdbarch, i),
1447 trad_frame_set_addr (cache->regs, i, offset);
1452 return end_prologue_addr;
1455 /* Implement the riscv_skip_prologue gdbarch method. */
1458 riscv_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1460 CORE_ADDR func_addr;
1462 /* See if we can determine the end of the prologue via the symbol
1463 table. If so, then return either PC, or the PC after the
1464 prologue, whichever is greater. */
1465 if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
1467 CORE_ADDR post_prologue_pc
1468 = skip_prologue_using_sal (gdbarch, func_addr);
1470 if (post_prologue_pc != 0)
1471 return std::max (pc, post_prologue_pc);
1474 /* Can't determine prologue from the symbol table, need to examine
1475 instructions. Pass -1 for the end address to indicate the prologue
1476 scanner can scan as far as it needs to find the end of the prologue. */
1477 return riscv_scan_prologue (gdbarch, pc, ((CORE_ADDR) -1), NULL);
1480 /* Implement the gdbarch push dummy code callback. */
1483 riscv_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp,
1484 CORE_ADDR funaddr, struct value **args, int nargs,
1485 struct type *value_type, CORE_ADDR *real_pc,
1486 CORE_ADDR *bp_addr, struct regcache *regcache)
1488 /* Allocate space for a breakpoint, and keep the stack correctly
1496 /* Compute the alignment of the type T. Used while setting up the
1497 arguments for a dummy call. */
1500 riscv_type_alignment (struct type *t)
1502 t = check_typedef (t);
1503 switch (TYPE_CODE (t))
1506 error (_("Could not compute alignment of type"));
1508 case TYPE_CODE_RVALUE_REF:
1510 case TYPE_CODE_ENUM:
1514 case TYPE_CODE_CHAR:
1515 case TYPE_CODE_BOOL:
1516 return TYPE_LENGTH (t);
1518 case TYPE_CODE_ARRAY:
1519 case TYPE_CODE_COMPLEX:
1520 return riscv_type_alignment (TYPE_TARGET_TYPE (t));
1522 case TYPE_CODE_STRUCT:
1523 case TYPE_CODE_UNION:
1528 for (i = 0; i < TYPE_NFIELDS (t); ++i)
1530 if (TYPE_FIELD_LOC_KIND (t, i) == FIELD_LOC_KIND_BITPOS)
1532 int a = riscv_type_alignment (TYPE_FIELD_TYPE (t, i));
1542 /* Holds information about a single argument either being passed to an
1543 inferior function, or returned from an inferior function. This includes
1544 information about the size, type, etc of the argument, and also
1545 information about how the argument will be passed (or returned). */
1547 struct riscv_arg_info
1549 /* Contents of the argument. */
1550 const gdb_byte *contents;
1552 /* Length of argument. */
1555 /* Alignment required for an argument of this type. */
1558 /* The type for this argument. */
1561 /* Each argument can have either 1 or 2 locations assigned to it. Each
1562 location describes where part of the argument will be placed. The
1563 second location is valid based on the LOC_TYPE and C_LENGTH fields
1564 of the first location (which is always valid). */
1567 /* What type of location this is. */
1570 /* Argument passed in a register. */
1573 /* Argument passed as an on stack argument. */
1576 /* Argument passed by reference. The second location is always
1577 valid for a BY_REF argument, and describes where the address
1578 of the BY_REF argument should be placed. */
1582 /* Information that depends on the location type. */
1585 /* Which register number to use. */
1588 /* The offset into the stack region. */
1592 /* The length of contents covered by this location. If this is less
1593 than the total length of the argument, then the second location
1594 will be valid, and will describe where the rest of the argument
1598 /* The offset within CONTENTS for this part of the argument. Will
1599 always be 0 for the first part. For the second part of the
1600 argument, this might be the C_LENGTH value of the first part,
1601 however, if we are passing a structure in two registers, and there's
1602 is padding between the first and second field, then this offset
1603 might be greater than the length of the first argument part. When
1604 the second argument location is not holding part of the argument
1605 value, but is instead holding the address of a reference argument,
1606 then this offset will be set to 0. */
1611 /* Information about a set of registers being used for passing arguments as
1612 part of a function call. The register set must be numerically
1613 sequential from NEXT_REGNUM to LAST_REGNUM. The register set can be
1614 disabled from use by setting NEXT_REGNUM greater than LAST_REGNUM. */
1616 struct riscv_arg_reg
1618 riscv_arg_reg (int first, int last)
1619 : next_regnum (first),
1625 /* The GDB register number to use in this set. */
1628 /* The last GDB register number to use in this set. */
1632 /* Arguments can be passed as on stack arguments, or by reference. The
1633 on stack arguments must be in a continuous region starting from $sp,
1634 while the by reference arguments can be anywhere, but we'll put them
1635 on the stack after (at higher address) the on stack arguments.
1637 This might not be the right approach to take. The ABI is clear that
1638 an argument passed by reference can be modified by the callee, which
1639 us placing the argument (temporarily) onto the stack will not achieve
1640 (changes will be lost). There's also the possibility that very large
1641 arguments could overflow the stack.
1643 This struct is used to track offset into these two areas for where
1644 arguments are to be placed. */
1645 struct riscv_memory_offsets
1647 riscv_memory_offsets ()
1654 /* Offset into on stack argument area. */
1657 /* Offset into the pass by reference area. */
1661 /* Holds information about where arguments to a call will be placed. This
1662 is updated as arguments are added onto the call, and can be used to
1663 figure out where the next argument should be placed. */
1665 struct riscv_call_info
1667 riscv_call_info (struct gdbarch *gdbarch)
1668 : int_regs (RISCV_A0_REGNUM, RISCV_A0_REGNUM + 7),
1669 float_regs (RISCV_FA0_REGNUM, RISCV_FA0_REGNUM + 7)
1671 xlen = riscv_isa_xlen (gdbarch);
1672 flen = riscv_isa_flen (gdbarch);
1674 /* Disable use of floating point registers if needed. */
1675 if (!riscv_has_fp_abi (gdbarch))
1676 float_regs.next_regnum = float_regs.last_regnum + 1;
1679 /* Track the memory areas used for holding in-memory arguments to a
1681 struct riscv_memory_offsets memory;
1683 /* Holds information about the next integer register to use for passing
1685 struct riscv_arg_reg int_regs;
1687 /* Holds information about the next floating point register to use for
1688 passing an argument. */
1689 struct riscv_arg_reg float_regs;
1691 /* The XLEN and FLEN are copied in to this structure for convenience, and
1692 are just the results of calling RISCV_ISA_XLEN and RISCV_ISA_FLEN. */
1697 /* Return the number of registers available for use as parameters in the
1698 register set REG. Returned value can be 0 or more. */
1701 riscv_arg_regs_available (struct riscv_arg_reg *reg)
1703 if (reg->next_regnum > reg->last_regnum)
1706 return (reg->last_regnum - reg->next_regnum + 1);
1709 /* If there is at least one register available in the register set REG then
1710 the next register from REG is assigned to LOC and the length field of
1711 LOC is updated to LENGTH. The register set REG is updated to indicate
1712 that the assigned register is no longer available and the function
1715 If there are no registers available in REG then the function returns
1716 false, and LOC and REG are unchanged. */
1719 riscv_assign_reg_location (struct riscv_arg_info::location *loc,
1720 struct riscv_arg_reg *reg,
1721 int length, int offset)
1723 if (reg->next_regnum <= reg->last_regnum)
1725 loc->loc_type = riscv_arg_info::location::in_reg;
1726 loc->loc_data.regno = reg->next_regnum;
1728 loc->c_length = length;
1729 loc->c_offset = offset;
1736 /* Assign LOC a location as the next stack parameter, and update MEMORY to
1737 record that an area of stack has been used to hold the parameter
1740 The length field of LOC is updated to LENGTH, the length of the
1741 parameter being stored, and ALIGN is the alignment required by the
1742 parameter, which will affect how memory is allocated out of MEMORY. */
1745 riscv_assign_stack_location (struct riscv_arg_info::location *loc,
1746 struct riscv_memory_offsets *memory,
1747 int length, int align)
1749 loc->loc_type = riscv_arg_info::location::on_stack;
1751 = align_up (memory->arg_offset, align);
1752 loc->loc_data.offset = memory->arg_offset;
1753 memory->arg_offset += length;
1754 loc->c_length = length;
1756 /* Offset is always 0, either we're the first location part, in which
1757 case we're reading content from the start of the argument, or we're
1758 passing the address of a reference argument, so 0. */
1762 /* Update AINFO, which describes an argument that should be passed or
1763 returned using the integer ABI. The argloc fields within AINFO are
1764 updated to describe the location in which the argument will be passed to
1765 a function, or returned from a function.
1767 The CINFO structure contains the ongoing call information, the holds
1768 information such as which argument registers are remaining to be
1769 assigned to parameter, and how much memory has been used by parameters
1772 By examining the state of CINFO a suitable location can be selected,
1773 and assigned to AINFO. */
1776 riscv_call_arg_scalar_int (struct riscv_arg_info *ainfo,
1777 struct riscv_call_info *cinfo)
1779 if (ainfo->length > (2 * cinfo->xlen))
1781 /* Argument is going to be passed by reference. */
1782 ainfo->argloc[0].loc_type
1783 = riscv_arg_info::location::by_ref;
1784 cinfo->memory.ref_offset
1785 = align_up (cinfo->memory.ref_offset, ainfo->align);
1786 ainfo->argloc[0].loc_data.offset = cinfo->memory.ref_offset;
1787 cinfo->memory.ref_offset += ainfo->length;
1788 ainfo->argloc[0].c_length = ainfo->length;
1790 /* The second location for this argument is given over to holding the
1791 address of the by-reference data. Pass 0 for the offset as this
1792 is not part of the actual argument value. */
1793 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1796 riscv_assign_stack_location (&ainfo->argloc[1],
1797 &cinfo->memory, cinfo->xlen,
1802 int len = (ainfo->length > cinfo->xlen) ? cinfo->xlen : ainfo->length;
1804 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1805 &cinfo->int_regs, len, 0))
1806 riscv_assign_stack_location (&ainfo->argloc[0],
1807 &cinfo->memory, len, ainfo->align);
1809 if (len < ainfo->length)
1811 len = ainfo->length - len;
1812 if (!riscv_assign_reg_location (&ainfo->argloc[1],
1813 &cinfo->int_regs, len,
1815 riscv_assign_stack_location (&ainfo->argloc[1],
1816 &cinfo->memory, len, cinfo->xlen);
1821 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1822 is being passed with the floating point ABI. */
1825 riscv_call_arg_scalar_float (struct riscv_arg_info *ainfo,
1826 struct riscv_call_info *cinfo)
1828 if (ainfo->length > cinfo->flen)
1829 return riscv_call_arg_scalar_int (ainfo, cinfo);
1832 if (!riscv_assign_reg_location (&ainfo->argloc[0],
1835 return riscv_call_arg_scalar_int (ainfo, cinfo);
1839 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1840 is a complex floating point argument, and is therefore handled
1841 differently to other argument types. */
1844 riscv_call_arg_complex_float (struct riscv_arg_info *ainfo,
1845 struct riscv_call_info *cinfo)
1847 if (ainfo->length <= (2 * cinfo->flen)
1848 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1851 int len = ainfo->length / 2;
1853 result = riscv_assign_reg_location (&ainfo->argloc[0],
1854 &cinfo->float_regs, len, len);
1855 gdb_assert (result);
1857 result = riscv_assign_reg_location (&ainfo->argloc[1],
1858 &cinfo->float_regs, len, len);
1859 gdb_assert (result);
1862 return riscv_call_arg_scalar_int (ainfo, cinfo);
1865 /* A structure used for holding information about a structure type within
1866 the inferior program. The RiscV ABI has special rules for handling some
1867 structures with a single field or with two fields. The counting of
1868 fields here is done after flattening out all nested structures. */
1870 class riscv_struct_info
1873 riscv_struct_info ()
1874 : m_number_of_fields (0),
1875 m_types { nullptr, nullptr }
1880 /* Analyse TYPE descending into nested structures, count the number of
1881 scalar fields and record the types of the first two fields found. */
1882 void analyse (struct type *type);
1884 /* The number of scalar fields found in the analysed type. This is
1885 currently only accurate if the value returned is 0, 1, or 2 as the
1886 analysis stops counting when the number of fields is 3. This is
1887 because the RiscV ABI only has special cases for 1 or 2 fields,
1888 anything else we just don't care about. */
1889 int number_of_fields () const
1890 { return m_number_of_fields; }
1892 /* Return the type for scalar field INDEX within the analysed type. Will
1893 return nullptr if there is no field at that index. Only INDEX values
1894 0 and 1 can be requested as the RiscV ABI only has special cases for
1895 structures with 1 or 2 fields. */
1896 struct type *field_type (int index) const
1898 gdb_assert (index < (sizeof (m_types) / sizeof (m_types[0])));
1899 return m_types[index];
1903 /* The number of scalar fields found within the structure after recursing
1904 into nested structures. */
1905 int m_number_of_fields;
1907 /* The types of the first two scalar fields found within the structure
1908 after recursing into nested structures. */
1909 struct type *m_types[2];
1912 /* Analyse TYPE descending into nested structures, count the number of
1913 scalar fields and record the types of the first two fields found. */
1916 riscv_struct_info::analyse (struct type *type)
1918 unsigned int count = TYPE_NFIELDS (type);
1921 for (i = 0; i < count; ++i)
1923 if (TYPE_FIELD_LOC_KIND (type, i) != FIELD_LOC_KIND_BITPOS)
1926 struct type *field_type = TYPE_FIELD_TYPE (type, i);
1927 field_type = check_typedef (field_type);
1929 switch (TYPE_CODE (field_type))
1931 case TYPE_CODE_STRUCT:
1932 analyse (field_type);
1936 /* RiscV only flattens out structures. Anything else does not
1937 need to be flattened, we just record the type, and when we
1938 look at the analysis results we'll realise this is not a
1939 structure we can special case, and pass the structure in
1941 if (m_number_of_fields < 2)
1942 m_types[m_number_of_fields] = field_type;
1943 m_number_of_fields++;
1947 /* RiscV only has special handling for structures with 1 or 2 scalar
1948 fields, any more than that and the structure is just passed in
1949 memory. We can safely drop out early when we find 3 or more
1952 if (m_number_of_fields > 2)
1957 /* Like RISCV_CALL_ARG_SCALAR_INT, except the argument described by AINFO
1958 is a structure. Small structures on RiscV have some special case
1959 handling in order that the structure might be passed in register.
1960 Larger structures are passed in memory. After assigning location
1961 information to AINFO, CINFO will have been updated. */
1964 riscv_call_arg_struct (struct riscv_arg_info *ainfo,
1965 struct riscv_call_info *cinfo)
1967 if (riscv_arg_regs_available (&cinfo->float_regs) >= 1)
1969 struct riscv_struct_info sinfo;
1971 sinfo.analyse (ainfo->type);
1972 if (sinfo.number_of_fields () == 1
1973 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_COMPLEX)
1975 gdb_assert (TYPE_LENGTH (ainfo->type)
1976 == TYPE_LENGTH (sinfo.field_type (0)));
1977 return riscv_call_arg_complex_float (ainfo, cinfo);
1980 if (sinfo.number_of_fields () == 1
1981 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT)
1983 gdb_assert (TYPE_LENGTH (ainfo->type)
1984 == TYPE_LENGTH (sinfo.field_type (0)));
1985 return riscv_call_arg_scalar_float (ainfo, cinfo);
1988 if (sinfo.number_of_fields () == 2
1989 && TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
1990 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
1991 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
1992 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen
1993 && riscv_arg_regs_available (&cinfo->float_regs) >= 2)
1995 int len0, len1, offset;
1997 gdb_assert (TYPE_LENGTH (ainfo->type) <= (2 * cinfo->flen));
1999 len0 = TYPE_LENGTH (sinfo.field_type (0));
2000 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2001 &cinfo->float_regs, len0, 0))
2002 error (_("failed during argument setup"));
2004 len1 = TYPE_LENGTH (sinfo.field_type (1));
2005 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2006 gdb_assert (len1 <= (TYPE_LENGTH (ainfo->type)
2007 - TYPE_LENGTH (sinfo.field_type (0))));
2009 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2012 error (_("failed during argument setup"));
2016 if (sinfo.number_of_fields () == 2
2017 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2018 && (TYPE_CODE (sinfo.field_type (0)) == TYPE_CODE_FLT
2019 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->flen
2020 && is_integral_type (sinfo.field_type (1))
2021 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->xlen))
2023 int len0, len1, offset;
2025 gdb_assert (TYPE_LENGTH (ainfo->type)
2026 <= (cinfo->flen + cinfo->xlen));
2028 len0 = TYPE_LENGTH (sinfo.field_type (0));
2029 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2030 &cinfo->float_regs, len0, 0))
2031 error (_("failed during argument setup"));
2033 len1 = TYPE_LENGTH (sinfo.field_type (1));
2034 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2035 gdb_assert (len1 <= cinfo->xlen);
2036 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2037 &cinfo->int_regs, len1, offset))
2038 error (_("failed during argument setup"));
2042 if (sinfo.number_of_fields () == 2
2043 && riscv_arg_regs_available (&cinfo->int_regs) >= 1
2044 && (is_integral_type (sinfo.field_type (0))
2045 && TYPE_LENGTH (sinfo.field_type (0)) <= cinfo->xlen
2046 && TYPE_CODE (sinfo.field_type (1)) == TYPE_CODE_FLT
2047 && TYPE_LENGTH (sinfo.field_type (1)) <= cinfo->flen))
2049 int len0, len1, offset;
2051 gdb_assert (TYPE_LENGTH (ainfo->type)
2052 <= (cinfo->flen + cinfo->xlen));
2054 len0 = TYPE_LENGTH (sinfo.field_type (0));
2055 len1 = TYPE_LENGTH (sinfo.field_type (1));
2056 offset = align_up (len0, riscv_type_alignment (sinfo.field_type (1)));
2058 gdb_assert (len0 <= cinfo->xlen);
2059 gdb_assert (len1 <= cinfo->flen);
2061 if (!riscv_assign_reg_location (&ainfo->argloc[0],
2062 &cinfo->int_regs, len0, 0))
2063 error (_("failed during argument setup"));
2065 if (!riscv_assign_reg_location (&ainfo->argloc[1],
2068 error (_("failed during argument setup"));
2074 /* Non of the structure flattening cases apply, so we just pass using
2076 ainfo->length = align_up (ainfo->length, cinfo->xlen);
2077 riscv_call_arg_scalar_int (ainfo, cinfo);
2080 /* Assign a location to call (or return) argument AINFO, the location is
2081 selected from CINFO which holds information about what call argument
2082 locations are available for use next. The TYPE is the type of the
2083 argument being passed, this information is recorded into AINFO (along
2084 with some additional information derived from the type).
2086 After assigning a location to AINFO, CINFO will have been updated. */
2089 riscv_arg_location (struct gdbarch *gdbarch,
2090 struct riscv_arg_info *ainfo,
2091 struct riscv_call_info *cinfo,
2095 ainfo->length = TYPE_LENGTH (ainfo->type);
2096 ainfo->align = riscv_type_alignment (ainfo->type);
2097 ainfo->contents = nullptr;
2099 switch (TYPE_CODE (ainfo->type))
2102 case TYPE_CODE_BOOL:
2103 case TYPE_CODE_CHAR:
2104 case TYPE_CODE_RANGE:
2105 case TYPE_CODE_ENUM:
2107 if (ainfo->length <= cinfo->xlen)
2109 ainfo->type = builtin_type (gdbarch)->builtin_long;
2110 ainfo->length = cinfo->xlen;
2112 else if (ainfo->length <= (2 * cinfo->xlen))
2114 ainfo->type = builtin_type (gdbarch)->builtin_long_long;
2115 ainfo->length = 2 * cinfo->xlen;
2118 /* Recalculate the alignment requirement. */
2119 ainfo->align = riscv_type_alignment (ainfo->type);
2120 riscv_call_arg_scalar_int (ainfo, cinfo);
2124 riscv_call_arg_scalar_float (ainfo, cinfo);
2127 case TYPE_CODE_COMPLEX:
2128 riscv_call_arg_complex_float (ainfo, cinfo);
2131 case TYPE_CODE_STRUCT:
2132 riscv_call_arg_struct (ainfo, cinfo);
2136 riscv_call_arg_scalar_int (ainfo, cinfo);
2141 /* Used for printing debug information about the call argument location in
2142 INFO to STREAM. The addresses in SP_REFS and SP_ARGS are the base
2143 addresses for the location of pass-by-reference and
2144 arguments-on-the-stack memory areas. */
2147 riscv_print_arg_location (ui_file *stream, struct gdbarch *gdbarch,
2148 struct riscv_arg_info *info,
2149 CORE_ADDR sp_refs, CORE_ADDR sp_args)
2151 fprintf_unfiltered (stream, "type: '%s', length: 0x%x, alignment: 0x%x",
2152 TYPE_SAFE_NAME (info->type), info->length, info->align);
2153 switch (info->argloc[0].loc_type)
2155 case riscv_arg_info::location::in_reg:
2157 (stream, ", register %s",
2158 gdbarch_register_name (gdbarch, info->argloc[0].loc_data.regno));
2159 if (info->argloc[0].c_length < info->length)
2161 switch (info->argloc[1].loc_type)
2163 case riscv_arg_info::location::in_reg:
2165 (stream, ", register %s",
2166 gdbarch_register_name (gdbarch,
2167 info->argloc[1].loc_data.regno));
2170 case riscv_arg_info::location::on_stack:
2171 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2172 info->argloc[1].loc_data.offset);
2175 case riscv_arg_info::location::by_ref:
2177 /* The second location should never be a reference, any
2178 argument being passed by reference just places its address
2179 in the first location and is done. */
2180 error (_("invalid argument location"));
2184 if (info->argloc[1].c_offset > info->argloc[0].c_length)
2185 fprintf_unfiltered (stream, " (offset 0x%x)",
2186 info->argloc[1].c_offset);
2190 case riscv_arg_info::location::on_stack:
2191 fprintf_unfiltered (stream, ", on stack at offset 0x%x",
2192 info->argloc[0].loc_data.offset);
2195 case riscv_arg_info::location::by_ref:
2197 (stream, ", by reference, data at offset 0x%x (%s)",
2198 info->argloc[0].loc_data.offset,
2199 core_addr_to_string (sp_refs + info->argloc[0].loc_data.offset));
2200 if (info->argloc[1].loc_type
2201 == riscv_arg_info::location::in_reg)
2203 (stream, ", address in register %s",
2204 gdbarch_register_name (gdbarch, info->argloc[1].loc_data.regno));
2207 gdb_assert (info->argloc[1].loc_type
2208 == riscv_arg_info::location::on_stack);
2210 (stream, ", address on stack at offset 0x%x (%s)",
2211 info->argloc[1].loc_data.offset,
2212 core_addr_to_string (sp_args + info->argloc[1].loc_data.offset));
2217 gdb_assert_not_reached (_("unknown argument location type"));
2221 /* Implement the push dummy call gdbarch callback. */
2224 riscv_push_dummy_call (struct gdbarch *gdbarch,
2225 struct value *function,
2226 struct regcache *regcache,
2229 struct value **args,
2232 CORE_ADDR struct_addr)
2235 CORE_ADDR sp_args, sp_refs;
2236 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2238 struct riscv_arg_info *arg_info =
2239 (struct riscv_arg_info *) alloca (nargs * sizeof (struct riscv_arg_info));
2240 struct riscv_arg_info *info;
2242 struct riscv_call_info call_info (gdbarch);
2246 /* We'll use register $a0 if we're returning a struct. */
2248 ++call_info.int_regs.next_regnum;
2250 for (i = 0, info = &arg_info[0];
2254 struct value *arg_value;
2255 struct type *arg_type;
2257 arg_value = args[i];
2258 arg_type = check_typedef (value_type (arg_value));
2260 riscv_arg_location (gdbarch, info, &call_info, arg_type);
2262 if (info->type != arg_type)
2263 arg_value = value_cast (info->type, arg_value);
2264 info->contents = value_contents (arg_value);
2267 /* Adjust the stack pointer and align it. */
2268 sp = sp_refs = align_down (sp - call_info.memory.ref_offset, SP_ALIGNMENT);
2269 sp = sp_args = align_down (sp - call_info.memory.arg_offset, SP_ALIGNMENT);
2271 if (riscv_debug_infcall > 0)
2273 fprintf_unfiltered (gdb_stdlog, "dummy call args:\n");
2274 fprintf_unfiltered (gdb_stdlog, ": floating point ABI %s in use\n",
2275 (riscv_has_fp_abi (gdbarch) ? "is" : "is not"));
2276 fprintf_unfiltered (gdb_stdlog, ": xlen: %d\n: flen: %d\n",
2277 call_info.xlen, call_info.flen);
2279 fprintf_unfiltered (gdb_stdlog,
2280 "[*] struct return pointer in register $A0\n");
2281 for (i = 0; i < nargs; ++i)
2283 struct riscv_arg_info *info = &arg_info [i];
2285 fprintf_unfiltered (gdb_stdlog, "[%2d] ", i);
2286 riscv_print_arg_location (gdb_stdlog, gdbarch, info, sp_refs, sp_args);
2287 fprintf_unfiltered (gdb_stdlog, "\n");
2289 if (call_info.memory.arg_offset > 0
2290 || call_info.memory.ref_offset > 0)
2292 fprintf_unfiltered (gdb_stdlog, " Original sp: %s\n",
2293 core_addr_to_string (osp));
2294 fprintf_unfiltered (gdb_stdlog, "Stack required (for args): 0x%x\n",
2295 call_info.memory.arg_offset);
2296 fprintf_unfiltered (gdb_stdlog, "Stack required (for refs): 0x%x\n",
2297 call_info.memory.ref_offset);
2298 fprintf_unfiltered (gdb_stdlog, " Stack allocated: %s\n",
2299 core_addr_to_string_nz (osp - sp));
2303 /* Now load the argument into registers, or onto the stack. */
2307 gdb_byte buf[sizeof (LONGEST)];
2309 store_unsigned_integer (buf, call_info.xlen, byte_order, struct_addr);
2310 regcache->cooked_write (RISCV_A0_REGNUM, buf);
2313 for (i = 0; i < nargs; ++i)
2316 int second_arg_length = 0;
2317 const gdb_byte *second_arg_data;
2318 struct riscv_arg_info *info = &arg_info [i];
2320 gdb_assert (info->length > 0);
2322 switch (info->argloc[0].loc_type)
2324 case riscv_arg_info::location::in_reg:
2326 gdb_byte tmp [sizeof (ULONGEST)];
2328 gdb_assert (info->argloc[0].c_length <= info->length);
2329 memset (tmp, 0, sizeof (tmp));
2330 memcpy (tmp, info->contents, info->argloc[0].c_length);
2331 regcache->cooked_write (info->argloc[0].loc_data.regno, tmp);
2333 ((info->argloc[0].c_length < info->length)
2334 ? info->argloc[1].c_length : 0);
2335 second_arg_data = info->contents + info->argloc[1].c_offset;
2339 case riscv_arg_info::location::on_stack:
2340 dst = sp_args + info->argloc[0].loc_data.offset;
2341 write_memory (dst, info->contents, info->length);
2342 second_arg_length = 0;
2345 case riscv_arg_info::location::by_ref:
2346 dst = sp_refs + info->argloc[0].loc_data.offset;
2347 write_memory (dst, info->contents, info->length);
2349 second_arg_length = call_info.xlen;
2350 second_arg_data = (gdb_byte *) &dst;
2354 gdb_assert_not_reached (_("unknown argument location type"));
2357 if (second_arg_length > 0)
2359 switch (info->argloc[1].loc_type)
2361 case riscv_arg_info::location::in_reg:
2363 gdb_byte tmp [sizeof (ULONGEST)];
2365 gdb_assert ((riscv_is_fp_regno_p (info->argloc[1].loc_data.regno)
2366 && second_arg_length <= call_info.flen)
2367 || second_arg_length <= call_info.xlen);
2368 memset (tmp, 0, sizeof (tmp));
2369 memcpy (tmp, second_arg_data, second_arg_length);
2370 regcache->cooked_write (info->argloc[1].loc_data.regno, tmp);
2374 case riscv_arg_info::location::on_stack:
2378 arg_addr = sp_args + info->argloc[1].loc_data.offset;
2379 write_memory (arg_addr, second_arg_data, second_arg_length);
2383 case riscv_arg_info::location::by_ref:
2385 /* The second location should never be a reference, any
2386 argument being passed by reference just places its address
2387 in the first location and is done. */
2388 error (_("invalid argument location"));
2394 /* Set the dummy return value to bp_addr.
2395 A dummy breakpoint will be setup to execute the call. */
2397 if (riscv_debug_infcall > 0)
2398 fprintf_unfiltered (gdb_stdlog, ": writing $ra = %s\n",
2399 core_addr_to_string (bp_addr));
2400 regcache_cooked_write_unsigned (regcache, RISCV_RA_REGNUM, bp_addr);
2402 /* Finally, update the stack pointer. */
2404 if (riscv_debug_infcall > 0)
2405 fprintf_unfiltered (gdb_stdlog, ": writing $sp = %s\n",
2406 core_addr_to_string (sp));
2407 regcache_cooked_write_unsigned (regcache, RISCV_SP_REGNUM, sp);
2412 /* Implement the return_value gdbarch method. */
2414 static enum return_value_convention
2415 riscv_return_value (struct gdbarch *gdbarch,
2416 struct value *function,
2418 struct regcache *regcache,
2420 const gdb_byte *writebuf)
2422 struct riscv_call_info call_info (gdbarch);
2423 struct riscv_arg_info info;
2424 struct type *arg_type;
2426 arg_type = check_typedef (type);
2427 riscv_arg_location (gdbarch, &info, &call_info, arg_type);
2429 if (riscv_debug_infcall > 0)
2431 fprintf_unfiltered (gdb_stdlog, "riscv return value:\n");
2432 fprintf_unfiltered (gdb_stdlog, "[R] ");
2433 riscv_print_arg_location (gdb_stdlog, gdbarch, &info, 0, 0);
2434 fprintf_unfiltered (gdb_stdlog, "\n");
2437 if (readbuf != nullptr || writebuf != nullptr)
2441 switch (info.argloc[0].loc_type)
2443 /* Return value in register(s). */
2444 case riscv_arg_info::location::in_reg:
2446 regnum = info.argloc[0].loc_data.regno;
2449 regcache->cooked_read (regnum, readbuf);
2452 regcache->cooked_write (regnum, writebuf);
2454 /* A return value in register can have a second part in a
2456 if (info.argloc[0].c_length < info.length)
2458 switch (info.argloc[1].loc_type)
2460 case riscv_arg_info::location::in_reg:
2461 regnum = info.argloc[1].loc_data.regno;
2465 readbuf += info.argloc[1].c_offset;
2466 regcache->cooked_read (regnum, readbuf);
2471 writebuf += info.argloc[1].c_offset;
2472 regcache->cooked_write (regnum, writebuf);
2476 case riscv_arg_info::location::by_ref:
2477 case riscv_arg_info::location::on_stack:
2479 error (_("invalid argument location"));
2486 /* Return value by reference will have its address in A0. */
2487 case riscv_arg_info::location::by_ref:
2491 regcache_cooked_read_unsigned (regcache, RISCV_A0_REGNUM,
2493 if (readbuf != nullptr)
2494 read_memory (addr, readbuf, info.length);
2495 if (writebuf != nullptr)
2496 write_memory (addr, writebuf, info.length);
2500 case riscv_arg_info::location::on_stack:
2502 error (_("invalid argument location"));
2507 switch (info.argloc[0].loc_type)
2509 case riscv_arg_info::location::in_reg:
2510 return RETURN_VALUE_REGISTER_CONVENTION;
2511 case riscv_arg_info::location::by_ref:
2512 return RETURN_VALUE_ABI_RETURNS_ADDRESS;
2513 case riscv_arg_info::location::on_stack:
2515 error (_("invalid argument location"));
2519 /* Implement the frame_align gdbarch method. */
2522 riscv_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
2524 return align_down (addr, 16);
2527 /* Implement the unwind_pc gdbarch method. */
2530 riscv_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
2532 return frame_unwind_register_unsigned (next_frame, RISCV_PC_REGNUM);
2535 /* Implement the unwind_sp gdbarch method. */
2538 riscv_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
2540 return frame_unwind_register_unsigned (next_frame, RISCV_SP_REGNUM);
2543 /* Implement the dummy_id gdbarch method. */
2545 static struct frame_id
2546 riscv_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
2548 return frame_id_build (get_frame_register_signed (this_frame, RISCV_SP_REGNUM),
2549 get_frame_pc (this_frame));
2552 /* Generate, or return the cached frame cache for the RiscV frame
2555 static struct riscv_unwind_cache *
2556 riscv_frame_cache (struct frame_info *this_frame, void **this_cache)
2558 CORE_ADDR pc, start_addr;
2559 struct riscv_unwind_cache *cache;
2560 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2563 if ((*this_cache) != NULL)
2564 return (struct riscv_unwind_cache *) *this_cache;
2566 cache = FRAME_OBSTACK_ZALLOC (struct riscv_unwind_cache);
2567 cache->regs = trad_frame_alloc_saved_regs (this_frame);
2568 (*this_cache) = cache;
2570 /* Scan the prologue, filling in the cache. */
2571 start_addr = get_frame_func (this_frame);
2572 pc = get_frame_pc (this_frame);
2573 riscv_scan_prologue (gdbarch, start_addr, pc, cache);
2575 /* We can now calculate the frame base address. */
2577 = (get_frame_register_signed (this_frame, cache->frame_base_reg)
2578 + cache->frame_base_offset);
2579 if (riscv_debug_unwinder)
2580 fprintf_unfiltered (gdb_stdlog, "Frame base is %s ($%s + 0x%x)\n",
2581 core_addr_to_string (cache->frame_base),
2582 gdbarch_register_name (gdbarch,
2583 cache->frame_base_reg),
2584 cache->frame_base_offset);
2586 /* The prologue scanner sets the address of registers stored to the stack
2587 as the offset of that register from the frame base. The prologue
2588 scanner doesn't know the actual frame base value, and so is unable to
2589 compute the exact address. We do now know the frame base value, so
2590 update the address of registers stored to the stack. */
2591 numregs = gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
2592 for (regno = 0; regno < numregs; ++regno)
2594 if (trad_frame_addr_p (cache->regs, regno))
2595 cache->regs[regno].addr += cache->frame_base;
2598 /* The previous $pc can be found wherever the $ra value can be found.
2599 The previous $ra value is gone, this would have been stored be the
2600 previous frame if required. */
2601 cache->regs[gdbarch_pc_regnum (gdbarch)] = cache->regs[RISCV_RA_REGNUM];
2602 trad_frame_set_unknown (cache->regs, RISCV_RA_REGNUM);
2604 /* Build the frame id. */
2605 cache->this_id = frame_id_build (cache->frame_base, start_addr);
2607 /* The previous $sp value is the frame base value. */
2608 trad_frame_set_value (cache->regs, gdbarch_sp_regnum (gdbarch),
2614 /* Implement the this_id callback for RiscV frame unwinder. */
2617 riscv_frame_this_id (struct frame_info *this_frame,
2618 void **prologue_cache,
2619 struct frame_id *this_id)
2621 struct riscv_unwind_cache *cache;
2623 cache = riscv_frame_cache (this_frame, prologue_cache);
2624 *this_id = cache->this_id;
2627 /* Implement the prev_register callback for RiscV frame unwinder. */
2629 static struct value *
2630 riscv_frame_prev_register (struct frame_info *this_frame,
2631 void **prologue_cache,
2634 struct riscv_unwind_cache *cache;
2636 cache = riscv_frame_cache (this_frame, prologue_cache);
2637 return trad_frame_get_prev_register (this_frame, cache->regs, regnum);
2640 /* Structure defining the RiscV normal frame unwind functions. Since we
2641 are the fallback unwinder (DWARF unwinder is used first), we use the
2642 default frame sniffer, which always accepts the frame. */
2644 static const struct frame_unwind riscv_frame_unwind =
2646 /*.type =*/ NORMAL_FRAME,
2647 /*.stop_reason =*/ default_frame_unwind_stop_reason,
2648 /*.this_id =*/ riscv_frame_this_id,
2649 /*.prev_register =*/ riscv_frame_prev_register,
2650 /*.unwind_data =*/ NULL,
2651 /*.sniffer =*/ default_frame_sniffer,
2652 /*.dealloc_cache =*/ NULL,
2653 /*.prev_arch =*/ NULL,
2656 /* Initialize the current architecture based on INFO. If possible,
2657 re-use an architecture from ARCHES, which is a list of
2658 architectures already created during this debugging session.
2660 Called e.g. at program startup, when reading a core file, and when
2661 reading a binary file. */
2663 static struct gdbarch *
2664 riscv_gdbarch_init (struct gdbarch_info info,
2665 struct gdbarch_list *arches)
2667 struct gdbarch *gdbarch;
2668 struct gdbarch_tdep *tdep;
2669 struct gdbarch_tdep tmp_tdep;
2672 /* Ideally, we'd like to get as much information from the target for
2673 things like register size, and whether the target has floating point
2674 hardware. However, there are some things that the target can't tell
2675 us, like, what ABI is being used.
2677 So, for now, we take as much information as possible from the ELF,
2678 including things like register size, and FP hardware support, along
2679 with information about the ABI.
2681 Information about this target is built up in TMP_TDEP, and then we
2682 look for an existing gdbarch in ARCHES that matches TMP_TDEP. If no
2683 match is found we'll create a new gdbarch and copy TMP_TDEP over. */
2684 memset (&tmp_tdep, 0, sizeof (tmp_tdep));
2686 if (info.abfd != NULL
2687 && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2689 unsigned char eclass = elf_elfheader (info.abfd)->e_ident[EI_CLASS];
2690 int e_flags = elf_elfheader (info.abfd)->e_flags;
2692 if (eclass == ELFCLASS32)
2693 tmp_tdep.abi.fields.base_len = 1;
2694 else if (eclass == ELFCLASS64)
2695 tmp_tdep.abi.fields.base_len = 2;
2697 internal_error (__FILE__, __LINE__,
2698 _("unknown ELF header class %d"), eclass);
2700 if (e_flags & EF_RISCV_RVC)
2701 tmp_tdep.core_features |= (1 << ('C' - 'A'));
2703 if (e_flags & EF_RISCV_FLOAT_ABI_DOUBLE)
2705 tmp_tdep.abi.fields.float_abi = 2;
2706 tmp_tdep.core_features |= (1 << ('D' - 'A'));
2707 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2709 else if (e_flags & EF_RISCV_FLOAT_ABI_SINGLE)
2711 tmp_tdep.abi.fields.float_abi = 1;
2712 tmp_tdep.core_features |= (1 << ('F' - 'A'));
2717 const struct bfd_arch_info *binfo = info.bfd_arch_info;
2719 if (binfo->bits_per_word == 32)
2720 tmp_tdep.abi.fields.base_len = 1;
2721 else if (binfo->bits_per_word == 64)
2722 tmp_tdep.abi.fields.base_len = 2;
2724 internal_error (__FILE__, __LINE__, _("unknown bits_per_word %d"),
2725 binfo->bits_per_word);
2728 /* Find a candidate among the list of pre-declared architectures. */
2729 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2731 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2732 if (gdbarch_tdep (arches->gdbarch)->abi.value == tmp_tdep.abi.value)
2733 return arches->gdbarch;
2735 /* None found, so create a new architecture from the information provided. */
2736 tdep = (struct gdbarch_tdep *) xmalloc (sizeof *tdep);
2737 gdbarch = gdbarch_alloc (&info, tdep);
2738 memcpy (tdep, &tmp_tdep, sizeof (tmp_tdep));
2740 /* Target data types. */
2741 set_gdbarch_short_bit (gdbarch, 16);
2742 set_gdbarch_int_bit (gdbarch, 32);
2743 set_gdbarch_long_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2744 set_gdbarch_long_long_bit (gdbarch, 64);
2745 set_gdbarch_float_bit (gdbarch, 32);
2746 set_gdbarch_double_bit (gdbarch, 64);
2747 set_gdbarch_long_double_bit (gdbarch, 128);
2748 set_gdbarch_long_double_format (gdbarch, floatformats_ia64_quad);
2749 set_gdbarch_ptr_bit (gdbarch, riscv_isa_xlen (gdbarch) * 8);
2750 set_gdbarch_char_signed (gdbarch, 0);
2752 /* Information about the target architecture. */
2753 set_gdbarch_return_value (gdbarch, riscv_return_value);
2754 set_gdbarch_breakpoint_kind_from_pc (gdbarch, riscv_breakpoint_kind_from_pc);
2755 set_gdbarch_sw_breakpoint_from_kind (gdbarch, riscv_sw_breakpoint_from_kind);
2757 /* Register architecture. */
2758 set_gdbarch_num_regs (gdbarch, RISCV_LAST_REGNUM + 1);
2759 set_gdbarch_sp_regnum (gdbarch, RISCV_SP_REGNUM);
2760 set_gdbarch_pc_regnum (gdbarch, RISCV_PC_REGNUM);
2761 set_gdbarch_ps_regnum (gdbarch, RISCV_FP_REGNUM);
2762 set_gdbarch_deprecated_fp_regnum (gdbarch, RISCV_FP_REGNUM);
2764 /* Functions to supply register information. */
2765 set_gdbarch_register_name (gdbarch, riscv_register_name);
2766 set_gdbarch_register_type (gdbarch, riscv_register_type);
2767 set_gdbarch_print_registers_info (gdbarch, riscv_print_registers_info);
2768 set_gdbarch_register_reggroup_p (gdbarch, riscv_register_reggroup_p);
2770 /* Functions to analyze frames. */
2771 set_gdbarch_skip_prologue (gdbarch, riscv_skip_prologue);
2772 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2773 set_gdbarch_frame_align (gdbarch, riscv_frame_align);
2775 /* Functions to access frame data. */
2776 set_gdbarch_unwind_pc (gdbarch, riscv_unwind_pc);
2777 set_gdbarch_unwind_sp (gdbarch, riscv_unwind_sp);
2779 /* Functions handling dummy frames. */
2780 set_gdbarch_call_dummy_location (gdbarch, ON_STACK);
2781 set_gdbarch_push_dummy_code (gdbarch, riscv_push_dummy_code);
2782 set_gdbarch_push_dummy_call (gdbarch, riscv_push_dummy_call);
2783 set_gdbarch_dummy_id (gdbarch, riscv_dummy_id);
2785 /* Frame unwinders. Use DWARF debug info if available, otherwise use our own
2787 dwarf2_append_unwinders (gdbarch);
2788 frame_unwind_append_unwinder (gdbarch, &riscv_frame_unwind);
2790 for (i = 0; i < ARRAY_SIZE (riscv_register_aliases); ++i)
2791 user_reg_add (gdbarch, riscv_register_aliases[i].name,
2792 value_of_riscv_user_reg, &riscv_register_aliases[i].regnum);
2794 /* Hook in OS ABI-specific overrides, if they have been registered. */
2795 gdbarch_init_osabi (info, gdbarch);
2800 /* This decodes the current instruction and determines the address of the
2801 next instruction. */
2804 riscv_next_pc (struct regcache *regcache, CORE_ADDR pc)
2806 struct gdbarch *gdbarch = regcache->arch ();
2807 struct riscv_insn insn;
2810 insn.decode (gdbarch, pc);
2811 next_pc = pc + insn.length ();
2813 if (insn.opcode () == riscv_insn::JAL)
2814 next_pc = pc + insn.imm_signed ();
2815 else if (insn.opcode () == riscv_insn::JALR)
2818 regcache->cooked_read (insn.rs1 (), &source);
2819 next_pc = (source + insn.imm_signed ()) & ~(CORE_ADDR) 0x1;
2821 else if (insn.opcode () == riscv_insn::BEQ)
2824 regcache->cooked_read (insn.rs1 (), &src1);
2825 regcache->cooked_read (insn.rs2 (), &src2);
2827 next_pc = pc + insn.imm_signed ();
2829 else if (insn.opcode () == riscv_insn::BNE)
2832 regcache->cooked_read (insn.rs1 (), &src1);
2833 regcache->cooked_read (insn.rs2 (), &src2);
2835 next_pc = pc + insn.imm_signed ();
2837 else if (insn.opcode () == riscv_insn::BLT)
2840 regcache->cooked_read (insn.rs1 (), &src1);
2841 regcache->cooked_read (insn.rs2 (), &src2);
2843 next_pc = pc + insn.imm_signed ();
2845 else if (insn.opcode () == riscv_insn::BGE)
2848 regcache->cooked_read (insn.rs1 (), &src1);
2849 regcache->cooked_read (insn.rs2 (), &src2);
2851 next_pc = pc + insn.imm_signed ();
2853 else if (insn.opcode () == riscv_insn::BLTU)
2855 ULONGEST src1, src2;
2856 regcache->cooked_read (insn.rs1 (), &src1);
2857 regcache->cooked_read (insn.rs2 (), &src2);
2859 next_pc = pc + insn.imm_signed ();
2861 else if (insn.opcode () == riscv_insn::BGEU)
2863 ULONGEST src1, src2;
2864 regcache->cooked_read (insn.rs1 (), &src1);
2865 regcache->cooked_read (insn.rs2 (), &src2);
2867 next_pc = pc + insn.imm_signed ();
2873 /* We can't put a breakpoint in the middle of a lr/sc atomic sequence, so look
2874 for the end of the sequence and put the breakpoint there. */
2877 riscv_next_pc_atomic_sequence (struct regcache *regcache, CORE_ADDR pc,
2880 struct gdbarch *gdbarch = regcache->arch ();
2881 struct riscv_insn insn;
2882 CORE_ADDR cur_step_pc = pc;
2883 CORE_ADDR last_addr = 0;
2885 /* First instruction has to be a load reserved. */
2886 insn.decode (gdbarch, cur_step_pc);
2887 if (insn.opcode () != riscv_insn::LR)
2889 cur_step_pc = cur_step_pc + insn.length ();
2891 /* Next instruction should be branch to exit. */
2892 insn.decode (gdbarch, cur_step_pc);
2893 if (insn.opcode () != riscv_insn::BNE)
2895 last_addr = cur_step_pc + insn.imm_signed ();
2896 cur_step_pc = cur_step_pc + insn.length ();
2898 /* Next instruction should be store conditional. */
2899 insn.decode (gdbarch, cur_step_pc);
2900 if (insn.opcode () != riscv_insn::SC)
2902 cur_step_pc = cur_step_pc + insn.length ();
2904 /* Next instruction should be branch to start. */
2905 insn.decode (gdbarch, cur_step_pc);
2906 if (insn.opcode () != riscv_insn::BNE)
2908 if (pc != (cur_step_pc + insn.imm_signed ()))
2910 cur_step_pc = cur_step_pc + insn.length ();
2912 /* We should now be at the end of the sequence. */
2913 if (cur_step_pc != last_addr)
2916 *next_pc = cur_step_pc;
2920 /* This is called just before we want to resume the inferior, if we want to
2921 single-step it but there is no hardware or kernel single-step support. We
2922 find the target of the coming instruction and breakpoint it. */
2924 std::vector<CORE_ADDR>
2925 riscv_software_single_step (struct regcache *regcache)
2927 CORE_ADDR pc, next_pc;
2929 pc = regcache_read_pc (regcache);
2931 if (riscv_next_pc_atomic_sequence (regcache, pc, &next_pc))
2934 next_pc = riscv_next_pc (regcache, pc);
2940 _initialize_riscv_tdep (void)
2942 gdbarch_register (bfd_arch_riscv, riscv_gdbarch_init, NULL);
2944 /* Add root prefix command for all "set debug riscv" and "show debug
2946 add_prefix_cmd ("riscv", no_class, set_debug_riscv_command,
2947 _("RISC-V specific debug commands."),
2948 &setdebugriscvcmdlist, "set debug riscv ", 0,
2951 add_prefix_cmd ("riscv", no_class, show_debug_riscv_command,
2952 _("RISC-V specific debug commands."),
2953 &showdebugriscvcmdlist, "show debug riscv ", 0,
2956 add_setshow_zuinteger_cmd ("infcall", class_maintenance,
2957 &riscv_debug_infcall, _("\
2958 Set riscv inferior call debugging."), _("\
2959 Show riscv inferior call debugging."), _("\
2960 When non-zero, print debugging information for the riscv specific parts\n\
2961 of the inferior call mechanism."),
2963 show_riscv_debug_variable,
2964 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
2966 add_setshow_zuinteger_cmd ("unwinder", class_maintenance,
2967 &riscv_debug_unwinder, _("\
2968 Set riscv stack unwinding debugging."), _("\
2969 Show riscv stack unwinding debugging."), _("\
2970 When non-zero, print debugging information for the riscv specific parts\n\
2971 of the stack unwinding mechanism."),
2973 show_riscv_debug_variable,
2974 &setdebugriscvcmdlist, &showdebugriscvcmdlist);
2976 /* Add root prefix command for all "set riscv" and "show riscv" commands. */
2977 add_prefix_cmd ("riscv", no_class, set_riscv_command,
2978 _("RISC-V specific commands."),
2979 &setriscvcmdlist, "set riscv ", 0, &setlist);
2981 add_prefix_cmd ("riscv", no_class, show_riscv_command,
2982 _("RISC-V specific commands."),
2983 &showriscvcmdlist, "show riscv ", 0, &showlist);
2986 use_compressed_breakpoints = AUTO_BOOLEAN_AUTO;
2987 add_setshow_auto_boolean_cmd ("use-compressed-breakpoints", no_class,
2988 &use_compressed_breakpoints,
2990 Set debugger's use of compressed breakpoints."), _(" \
2991 Show debugger's use of compressed breakpoints."), _("\
2992 Debugging compressed code requires compressed breakpoints to be used. If\n \
2993 left to 'auto' then gdb will use them if $misa indicates the C extension\n \
2994 is supported. If that doesn't give the correct behavior, then this option\n\
2997 show_use_compressed_breakpoints,