1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 /* From ppc-linux-tdep.c... */
31 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
33 struct regcache *regcache,
35 const gdb_byte *writebuf);
36 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
38 struct regcache *regcache,
40 const gdb_byte *writebuf);
41 CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
42 struct value *function,
43 struct regcache *regcache,
44 CORE_ADDR bp_addr, int nargs,
45 struct value **args, CORE_ADDR sp,
47 CORE_ADDR struct_addr);
48 CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
49 struct value *function,
50 struct regcache *regcache,
51 CORE_ADDR bp_addr, int nargs,
52 struct value **args, CORE_ADDR sp,
54 CORE_ADDR struct_addr);
55 CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
57 int ppc_linux_memory_remove_breakpoint (struct bp_target_info *bp_tgt);
58 struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
59 const struct regset *ppc_linux_gregset (int);
60 const struct regset *ppc_linux_fpregset (void);
62 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
64 struct regcache *regcache,
66 const gdb_byte *writebuf);
68 /* From rs6000-tdep.c... */
69 int altivec_register_p (int regno);
70 int spe_register_p (int regno);
72 /* Return non-zero if the architecture described by GDBARCH has
73 floating-point registers (f0 --- f31 and fpscr). */
74 int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
76 /* Register set description. */
78 struct ppc_reg_offsets
80 /* General-purpose registers. */
82 int gpr_size; /* size for r0-31, pc, ps, lr, ctr. */
83 int xr_size; /* size for cr, xer, mq. */
92 /* Floating-point registers. */
97 /* AltiVec registers. */
103 /* Supply register REGNUM in the general-purpose register set REGSET
104 from the buffer specified by GREGS and LEN to register cache
105 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
107 extern void ppc_supply_gregset (const struct regset *regset,
108 struct regcache *regcache,
109 int regnum, const void *gregs, size_t len);
111 /* Supply register REGNUM in the floating-point register set REGSET
112 from the buffer specified by FPREGS and LEN to register cache
113 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
115 extern void ppc_supply_fpregset (const struct regset *regset,
116 struct regcache *regcache,
117 int regnum, const void *fpregs, size_t len);
119 /* Collect register REGNUM in the general-purpose register set
120 REGSET. from register cache REGCACHE into the buffer specified by
121 GREGS and LEN. If REGNUM is -1, do this for all registers in
124 extern void ppc_collect_gregset (const struct regset *regset,
125 const struct regcache *regcache,
126 int regnum, void *gregs, size_t len);
128 /* Collect register REGNUM in the floating-point register set
129 REGSET. from register cache REGCACHE into the buffer specified by
130 FPREGS and LEN. If REGNUM is -1, do this for all registers in
133 extern void ppc_collect_fpregset (const struct regset *regset,
134 const struct regcache *regcache,
135 int regnum, void *fpregs, size_t len);
137 /* Private data that this module attaches to struct gdbarch. */
141 int wordsize; /* size in bytes of fixed-point word */
142 const struct reg *regs; /* from current variant */
143 int ppc_gp0_regnum; /* GPR register 0 */
144 int ppc_toc_regnum; /* TOC register */
145 int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
146 int ppc_cr_regnum; /* Condition register */
147 int ppc_lr_regnum; /* Link register */
148 int ppc_ctr_regnum; /* Count register */
149 int ppc_xer_regnum; /* Integer exception register */
151 /* Not all PPC and RS6000 variants will have the registers
152 represented below. A -1 is used to indicate that the register
153 is not present in this variant. */
155 /* Floating-point registers. */
156 int ppc_fp0_regnum; /* floating-point register 0 */
157 int ppc_fpscr_regnum; /* fp status and condition register */
159 /* Segment registers. */
160 int ppc_sr0_regnum; /* segment register 0 */
162 /* Multiplier-Quotient Register (older POWER architectures only). */
165 /* Altivec registers. */
166 int ppc_vr0_regnum; /* First AltiVec register */
167 int ppc_vrsave_regnum; /* Last AltiVec register */
170 int ppc_ev0_upper_regnum; /* First GPR upper half register */
171 int ppc_ev0_regnum; /* First ev register */
172 int ppc_ev31_regnum; /* Last ev register */
173 int ppc_acc_regnum; /* SPE 'acc' register */
174 int ppc_spefscr_regnum; /* SPE 'spefscr' register */
176 /* Offset to ABI specific location where link register is saved. */
179 /* An array of integers, such that sim_regno[I] is the simulator
180 register number for GDB register number I, or -1 if the
181 simulator does not implement that register. */
184 /* Minimum possible text address. */
185 CORE_ADDR text_segment_base;
187 /* ISA-specific types. */
188 struct type *ppc_builtin_type_vec64;
189 struct type *ppc_builtin_type_vec128;
193 /* Constants for register set sizes. */
196 ppc_num_gprs = 32, /* 32 general-purpose registers */
197 ppc_num_fprs = 32, /* 32 floating-point registers */
198 ppc_num_srs = 16, /* 16 segment registers */
199 ppc_num_vrs = 32 /* 32 Altivec vector registers */
203 /* Constants for SPR register numbers. These are *not* GDB register
204 numbers: they are the numbers used in the PowerPC ISA itself to
205 refer to these registers.
207 This table includes all the SPRs from all the variants I could find
210 There may be registers from different PowerPC variants assigned the
211 same number, but that's fine: GDB and the SIM always use the
212 numbers in the context of a particular variant, so it's not
215 We need to deviate from the naming pattern when variants have
216 special-purpose registers of the same name, but with different
217 numbers. Fortunately, this is rare: look below to see how we
218 handle the 'tcr' registers on the 403/403GX and 602. */
245 ppc_spr_counta = 150,
246 ppc_spr_countb = 151,
251 ppc_spr_lctrl1 = 156,
252 ppc_spr_lctrl2 = 157,
255 ppc_spr_vrsave = 256,
265 ppc_spr_spefscr = 512,
266 ppc_spr_ibat0u = 528,
267 ppc_spr_ibat0l = 529,
268 ppc_spr_ibat1u = 530,
269 ppc_spr_ibat1l = 531,
270 ppc_spr_ibat2u = 532,
271 ppc_spr_ibat2l = 533,
272 ppc_spr_ibat3u = 534,
273 ppc_spr_ibat3l = 535,
274 ppc_spr_dbat0u = 536,
275 ppc_spr_dbat0l = 537,
276 ppc_spr_dbat1u = 538,
277 ppc_spr_dbat1l = 539,
278 ppc_spr_dbat2u = 540,
279 ppc_spr_dbat2l = 541,
280 ppc_spr_dbat3u = 542,
281 ppc_spr_dbat3l = 543,
282 ppc_spr_ic_cst = 560,
283 ppc_spr_ic_adr = 561,
284 ppc_spr_ic_dat = 562,
285 ppc_spr_dc_cst = 568,
286 ppc_spr_dc_adr = 569,
287 ppc_spr_dc_dat = 570,
291 ppc_spr_mi_ctr = 784,
293 ppc_spr_mi_epn = 787,
294 ppc_spr_mi_twc = 789,
295 ppc_spr_mi_rpn = 790,
296 ppc_spr_mi_cam = 816,
297 ppc_spr_mi_ram0 = 817,
298 ppc_spr_mi_ram1 = 818,
299 ppc_spr_md_ctr = 792,
300 ppc_spr_m_casid = 793,
302 ppc_spr_md_epn = 795,
304 ppc_spr_md_twc = 797,
305 ppc_spr_md_rpn = 798,
307 ppc_spr_mi_dbcam = 816,
308 ppc_spr_mi_dbram0 = 817,
309 ppc_spr_mi_dbram1 = 818,
310 ppc_spr_md_dbcam = 824,
311 ppc_spr_md_cam = 824,
312 ppc_spr_md_dbram0 = 825,
313 ppc_spr_md_ram0 = 825,
314 ppc_spr_md_dbram1 = 826,
315 ppc_spr_md_ram1 = 826,
316 ppc_spr_ummcr0 = 936,
320 ppc_spr_ummcr1 = 940,
341 ppc_spr_icdbdr = 979,
350 ppc_spr_602_tcr = 984,
351 ppc_spr_403_tcr = 986,
354 ppc_spr_esasrr = 988,
375 ppc_spr_thrm1 = 1020,
377 ppc_spr_thrm2 = 1021,
379 ppc_spr_thrm3 = 1022,
381 ppc_spr_fpecr = 1022,
387 /* Instruction size. */
388 #define PPC_INSN_SIZE 4
390 /* Estimate for the maximum number of instrctions in a function epilogue. */
391 #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
393 #endif /* ppc-tdep.h */