1 /* Target-dependent code for GDB, the GNU debugger.
3 Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
30 /* From ppc-linux-tdep.c... */
31 enum return_value_convention ppc_sysv_abi_return_value (struct gdbarch *gdbarch,
33 struct regcache *regcache,
35 const gdb_byte *writebuf);
36 enum return_value_convention ppc_sysv_abi_broken_return_value (struct gdbarch *gdbarch,
38 struct regcache *regcache,
40 const gdb_byte *writebuf);
41 CORE_ADDR ppc_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
42 struct value *function,
43 struct regcache *regcache,
44 CORE_ADDR bp_addr, int nargs,
45 struct value **args, CORE_ADDR sp,
47 CORE_ADDR struct_addr);
48 CORE_ADDR ppc64_sysv_abi_push_dummy_call (struct gdbarch *gdbarch,
49 struct value *function,
50 struct regcache *regcache,
51 CORE_ADDR bp_addr, int nargs,
52 struct value **args, CORE_ADDR sp,
54 CORE_ADDR struct_addr);
55 CORE_ADDR ppc64_sysv_abi_adjust_breakpoint_address (struct gdbarch *gdbarch,
57 int ppc_linux_memory_remove_breakpoint (struct bp_target_info *bp_tgt);
58 struct link_map_offsets *ppc_linux_svr4_fetch_link_map_offsets (void);
59 void ppc_linux_supply_gregset (struct regcache *regcache,
60 int regnum, const void *gregs, size_t size,
62 void ppc_linux_supply_fpregset (const struct regset *regset,
63 struct regcache *regcache,
64 int regnum, const void *gregs, size_t size);
66 enum return_value_convention ppc64_sysv_abi_return_value (struct gdbarch *gdbarch,
68 struct regcache *regcache,
70 const gdb_byte *writebuf);
72 /* From rs6000-tdep.c... */
73 int altivec_register_p (int regno);
74 int spe_register_p (int regno);
76 /* Return non-zero if the architecture described by GDBARCH has
77 floating-point registers (f0 --- f31 and fpscr). */
78 int ppc_floating_point_unit_p (struct gdbarch *gdbarch);
80 /* Register set description. */
82 struct ppc_reg_offsets
84 /* General-purpose registers. */
94 /* Floating-point registers. */
98 /* AltiVec registers. */
104 /* Supply register REGNUM in the general-purpose register set REGSET
105 from the buffer specified by GREGS and LEN to register cache
106 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
108 extern void ppc_supply_gregset (const struct regset *regset,
109 struct regcache *regcache,
110 int regnum, const void *gregs, size_t len);
112 /* Supply register REGNUM in the floating-point register set REGSET
113 from the buffer specified by FPREGS and LEN to register cache
114 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
116 extern void ppc_supply_fpregset (const struct regset *regset,
117 struct regcache *regcache,
118 int regnum, const void *fpregs, size_t len);
120 /* Collect register REGNUM in the general-purpose register set
121 REGSET. from register cache REGCACHE into the buffer specified by
122 GREGS and LEN. If REGNUM is -1, do this for all registers in
125 extern void ppc_collect_gregset (const struct regset *regset,
126 const struct regcache *regcache,
127 int regnum, void *gregs, size_t len);
129 /* Collect register REGNUM in the floating-point register set
130 REGSET. from register cache REGCACHE into the buffer specified by
131 FPREGS and LEN. If REGNUM is -1, do this for all registers in
134 extern void ppc_collect_fpregset (const struct regset *regset,
135 const struct regcache *regcache,
136 int regnum, void *fpregs, size_t len);
138 /* Private data that this module attaches to struct gdbarch. */
142 int wordsize; /* size in bytes of fixed-point word */
143 const struct reg *regs; /* from current variant */
144 int ppc_gp0_regnum; /* GPR register 0 */
145 int ppc_toc_regnum; /* TOC register */
146 int ppc_ps_regnum; /* Processor (or machine) status (%msr) */
147 int ppc_cr_regnum; /* Condition register */
148 int ppc_lr_regnum; /* Link register */
149 int ppc_ctr_regnum; /* Count register */
150 int ppc_xer_regnum; /* Integer exception register */
152 /* Not all PPC and RS6000 variants will have the registers
153 represented below. A -1 is used to indicate that the register
154 is not present in this variant. */
156 /* Floating-point registers. */
157 int ppc_fp0_regnum; /* floating-point register 0 */
158 int ppc_fpscr_regnum; /* fp status and condition register */
160 /* Segment registers. */
161 int ppc_sr0_regnum; /* segment register 0 */
163 /* Multiplier-Quotient Register (older POWER architectures only). */
166 /* Altivec registers. */
167 int ppc_vr0_regnum; /* First AltiVec register */
168 int ppc_vrsave_regnum; /* Last AltiVec register */
171 int ppc_ev0_upper_regnum; /* First GPR upper half register */
172 int ppc_ev0_regnum; /* First ev register */
173 int ppc_ev31_regnum; /* Last ev register */
174 int ppc_acc_regnum; /* SPE 'acc' register */
175 int ppc_spefscr_regnum; /* SPE 'spefscr' register */
177 /* Offset to ABI specific location where link register is saved. */
180 /* An array of integers, such that sim_regno[I] is the simulator
181 register number for GDB register number I, or -1 if the
182 simulator does not implement that register. */
185 /* Minimum possible text address. */
186 CORE_ADDR text_segment_base;
188 /* ISA-specific types. */
189 struct type *ppc_builtin_type_vec64;
190 struct type *ppc_builtin_type_vec128;
194 /* Constants for register set sizes. */
197 ppc_num_gprs = 32, /* 32 general-purpose registers */
198 ppc_num_fprs = 32, /* 32 floating-point registers */
199 ppc_num_srs = 16, /* 16 segment registers */
200 ppc_num_vrs = 32 /* 32 Altivec vector registers */
204 /* Constants for SPR register numbers. These are *not* GDB register
205 numbers: they are the numbers used in the PowerPC ISA itself to
206 refer to these registers.
208 This table includes all the SPRs from all the variants I could find
211 There may be registers from different PowerPC variants assigned the
212 same number, but that's fine: GDB and the SIM always use the
213 numbers in the context of a particular variant, so it's not
216 We need to deviate from the naming pattern when variants have
217 special-purpose registers of the same name, but with different
218 numbers. Fortunately, this is rare: look below to see how we
219 handle the 'tcr' registers on the 403/403GX and 602. */
246 ppc_spr_counta = 150,
247 ppc_spr_countb = 151,
252 ppc_spr_lctrl1 = 156,
253 ppc_spr_lctrl2 = 157,
256 ppc_spr_vrsave = 256,
266 ppc_spr_spefscr = 512,
267 ppc_spr_ibat0u = 528,
268 ppc_spr_ibat0l = 529,
269 ppc_spr_ibat1u = 530,
270 ppc_spr_ibat1l = 531,
271 ppc_spr_ibat2u = 532,
272 ppc_spr_ibat2l = 533,
273 ppc_spr_ibat3u = 534,
274 ppc_spr_ibat3l = 535,
275 ppc_spr_dbat0u = 536,
276 ppc_spr_dbat0l = 537,
277 ppc_spr_dbat1u = 538,
278 ppc_spr_dbat1l = 539,
279 ppc_spr_dbat2u = 540,
280 ppc_spr_dbat2l = 541,
281 ppc_spr_dbat3u = 542,
282 ppc_spr_dbat3l = 543,
283 ppc_spr_ic_cst = 560,
284 ppc_spr_ic_adr = 561,
285 ppc_spr_ic_dat = 562,
286 ppc_spr_dc_cst = 568,
287 ppc_spr_dc_adr = 569,
288 ppc_spr_dc_dat = 570,
292 ppc_spr_mi_ctr = 784,
294 ppc_spr_mi_epn = 787,
295 ppc_spr_mi_twc = 789,
296 ppc_spr_mi_rpn = 790,
297 ppc_spr_mi_cam = 816,
298 ppc_spr_mi_ram0 = 817,
299 ppc_spr_mi_ram1 = 818,
300 ppc_spr_md_ctr = 792,
301 ppc_spr_m_casid = 793,
303 ppc_spr_md_epn = 795,
305 ppc_spr_md_twc = 797,
306 ppc_spr_md_rpn = 798,
308 ppc_spr_mi_dbcam = 816,
309 ppc_spr_mi_dbram0 = 817,
310 ppc_spr_mi_dbram1 = 818,
311 ppc_spr_md_dbcam = 824,
312 ppc_spr_md_cam = 824,
313 ppc_spr_md_dbram0 = 825,
314 ppc_spr_md_ram0 = 825,
315 ppc_spr_md_dbram1 = 826,
316 ppc_spr_md_ram1 = 826,
317 ppc_spr_ummcr0 = 936,
321 ppc_spr_ummcr1 = 940,
342 ppc_spr_icdbdr = 979,
351 ppc_spr_602_tcr = 984,
352 ppc_spr_403_tcr = 986,
355 ppc_spr_esasrr = 988,
376 ppc_spr_thrm1 = 1020,
378 ppc_spr_thrm2 = 1021,
380 ppc_spr_thrm3 = 1022,
382 ppc_spr_fpecr = 1022,
388 /* Instruction size. */
389 #define PPC_INSN_SIZE 4
391 /* Estimate for the maximum number of instrctions in a function epilogue. */
392 #define PPC_MAX_EPILOGUE_INSTRUCTIONS 52
394 #endif /* ppc-tdep.h */